See

discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/309818099

A 155-dB Dynamic Range Current Measurement

Front End for Electrochemical Biosensing

Article in IEEE Transactions on Biomedical Circuits and Systems · November 2016

DOI: 10.1109/TBCAS.2016.2612581

CITATIONS READS

3 66

4 authors, including:

Shanshan Dai Rukshan Perera

Brown University Brown University
7 PUBLICATIONS 24 CITATIONS 10 PUBLICATIONS 50 CITATIONS

SEE PROFILE SEE PROFILE

All content following this page was uploaded by Shanshan Dai on 18 October 2017.

The user has requested enhancement of the downloaded file.

 1

A 155-dB Dynamic Range Current Measurement

Front End for Electrochemical Biosensing
Shanshan Dai, Rukshan T. Perera, Zi Yang and Jacob K. Rosenstein

Abstract—An integrated current measurement system with

ultra wide dynamic range is presented and fabricated in a 180- dynamic
nm CMOS technology. Its dual-mode design provides concurrent range (V)
voltage and frequency outputs, without requiring an external maximum input
clock source. An integrator-differentiator
√ core provides a voltage μA
output with a noise floor of 11.6 fA/ Hz and a -3 dB cutoff fre-
quency of 1.4 MHz. It is merged with an asynchronous current-
to-frequency converter, which generates an output frequency dynamic

Current
range (I) macroscale
linearly proportional to the input current. Together, the voltage

current
biochemical
and frequency outputs yield a current measurement range of response
155 dB, spanning from 204 fA (100 Hz) or 1.25 pA (10 kHz) to nanoscale
time
11.6 µA. The proposed architecture’s low noise, wide bandwidth, single-unit
and wide dynamic range make it ideal for measurements of highly response
pA
nonlinear electrochemical and electrophysiological systems.
noise floor
Index Terms—Amperometric, analog front end, current mea-
surement, current to voltage converter, low noise, high dynamic Voltage
range, electrochemistry, nanosensors.

I. I NTRODUCTION Fig. 1. The exponential voltage dependence of biochemical systems makes it

challenging to observe single-unit and aggregate behaviors in the same system.

B iological and chemical processes span many orders of

magnitude in time, space, and energy. Thus, acquiring
signals at high fidelity is often a balance between the smallest
For example, currents through single biological ion channels are in the fA-pA
range, while net currents in a cell membrane can reach µA.

and largest signals which can be resolved. Biochemical reac-

tions are highly nonlinear, and the dynamic range of a mea-
surement system dictates the range of observable conditions.
For example, classical electrochemical reactions can follow the
Tafel equation, which relates the applied potential and reaction
rate. This follows an exponential relationship [1]:
 
V − V0
i ∝ exp ±αF , (1)
RT
where α is a charge transfer coefficient, F is Faraday’s
constant, V0 is the open circuit potential, V is the applied
potential, R is the gas constant, and T is the absolute temper-
ature. This implies that the measurable range of overpotential
(∆V = Vmax − Vmin ) is logarithmically limited by the ratio
between the minimum and maximum measurable currents by:
 
imax
∆V ∝ ln . (2)
imin
Another important metric for any measurement is the min-
imum resolvable signal, which is ultimately limited by noise
processes. The minimum measurable current, denoted imin ,
is related to the input-referred noise density Si (f ) and signal
bandwidth B by:
s
Z B
imin ≈ SN Rmin × Si (f )df , (3)
0 and closing of a large number of channels, as illustrated in
The authors are with the School of Engineering, Brown Univer-
sity, Providence, RI 02912, USA (e-mail: shanshan dai@brown.edu; ja-
cob rosenstein@brown.edu).
where SN Rmin is the minimum tolerable signal-to-noise
ratio.
Similarly to simple electrochemical reactions, more com-
plex biological systems also exhibit highly nonlinear voltage-
current relationships. For example, voltage-gated sodium chan-
nels participate in neural signaling by sensing a small potential
change across a cell membrane, and responding by opening
channels for dissolved sodium (N a+ ) ions to flow into the cell,
initiating an action potential. These proteins change shape in
response to an electric field, which opens and closes discrete
ion channels through the cell membrane. The probability Popen
of a channel being open can be an exponential function of
voltage:  
zT V
Popen (V ) ∝ exp , (4)
kT
where k is Boltzmann’s constant, and zT is an equivalent
gating charge which moves in response to the change in
membrane potential [2].
Although the Popen is a continuous function, the time-
resolved current entering the cell is not constant or even con-
tinuous. Instead, the membrane current will be an integer mul-
tiple of the single-channel conductance, and the true current is
an approximately stepwise function representing the opening
Fig. 1. Observations of single channel characteristics can yield
insights into the kinetics of membrane proteins which are not
accessible from macroscale measurements.

(a)
(b)
Fig. 2. (a) Integrator-Differentiator current measurement setup. (b) Logarith-
mic current measurement setup.
These fundamental challenges set the stage for further in-
evitable tradeoffs between dynamic range, noise, and temporal
resolution in any sensitive measurement. Electronic circuits
which push the boundaries of these tradeoffs can relieve
pressure on the conditions of the experiment, and allow for
a wider range of biochemical and environmental parameters
to be explored.
In this paper, we present an integrated circuit for sen-
sitive current measurements, which combines the low-noise
performance of a charge-sensitive front end with the ultra-
wide dynamic range of an asynchronous current-to-frequency
converter. The circuit includes a capacitor network which min-
imizes reset glitches in the continuous-time output, eliminating
dead time and achieving ultra-wide dynamic range and low-
noise operation.
This paper is an expanded presentation of the circuit ini-
tially introduced in [3], with an expanded system design
consideration including bandwidth analysis of the integrator-
differentiator, signal-to-noise ratio and nonlinearity of the
current-to-frequency converter, and biological ion channel
experiments. The rest of the paper is organized as follows:
Section II describes common circuit topologies for low-noise
current recordings. In Section III, we present the new arrange-
ment which achieves both low noise and wide dynamic range
with two simultaneous and complementary outputs. Section
IV describes implementation details of this integrated current
measurement system in 180-nm CMOS. Section V presents
experimental test results from the prototype chip. We conclude
with Section VI.
II. C URRENT M EASUREMENT C IRCUITS
There are many high-performance current measurement
circuits, which have been reviewed in detail elsewhere [4],
[5]. In the following, we give a brief discussion of common
circuit topologies for low-noise current recordings, to place
our new design in context. For detailed treatments we refer
the reader to one of the review articles above.
One well-known structure for transient low current measure-
ments is based on an integrator followed by a differentiator
[6]–[8], as shown in Fig. 2 (a). The high gain of the integrator
stage can yield very low noise density, while the differentiator
ensures a flat frequency response.
2
The first limitation of this structure is its low dynamic
current measurement range. If Rf is the dominant noise
source, the noise-limited resolution can be derived as:
p
4kT B/Rf
Iin,min = SN Rmin × . (5)
Cd /Ci
For this reason the circuit is often designed with Cd /Ci >> 1
and a moderately large Rf . Unfortunately, this high gain
and linear response also means that it has a fairly small
measurement range. If the differentiator output is limited by
[0, VDD ], the maximum measurable signal is:
VDD
Iin,max = . (6)
Rf · Cd /Ci
This leaves the circuit with a dynamic range described by:
Iin,max VDD
DR = = SN Rmin × p , (7)
Iin,min 4kT BRf
where k, T and B are the Boltzmann constant, the absolute
temperature and the measurement bandwidth, respectively.
Typical IC values may be Rf = 500 KΩ, B = 10∼100 kHz,
and VDD = 1.8 V, which yield a minimum measurable current
of 1 pA and a maximum measurable current on the order of
100 nA, roughly corresponding to a 5-decade dynamic range.
A second limitation is that the integrator is prone to sat-
uration and requires either supplementary DC current offset
compensation [7], [8] or an active reset switch. Unfortunately,
DC current offset networks introduce broadband noise, while
discrete reset events can induce large transients which push
the differentiator into saturation, producing a long recovery
time during which the input signal is not observable and
information may be lost.
Other current measurement circuit architectures include
those relying on high-value pseudo-resistors [9]–[11], timed
integrators with an external frequency reference [12]–[14], and
switched-capacitor networks [15]–[17]. In general, resistive
transimpedance amplifiers [18] can be the most straightfor-
ward to implement but have relatively low dynamic range
for low supply voltages. Discrete-time systems have high
performance with low power consumption and opportunities
for noise-shaping, but somewhat lower bandwidth [15], [16],
[19].
At the other end of the spectrum lies the logarithmic current-
to-voltage converter [20], [21], [23], which uses an exponential
device as the feedback element in a transimpedance amplifier,
as shown in Fig. 2 (b). This results in a maximum measurable
current of:  
VDD
Iin,max = Is exp . (8)
kT /q
The minimum resolvable current can also be quite small, and
is ultimately limited by shot noise in the feedback network.
Although the logarithmic amplifier can provide a very wide
dynamic range, this is accompanied by significant temperature
sensitivity and nonlinearities. These nonlinearities are difficult
to address, but the temperature drift can be managed to a
limited extent by means of continuous temperature calibration
[21] or additional temperature compensation circuits [22].

Fig. 3. Proposed current measurement system. The circuit produces both
an output voltage (Vout ) and an output frequency (fout ), each of which is
linearly proportional to the input current (Iin ) .
Fig. 4. Charge and voltage distribution on Ci1 and Ci2 before and after the
integrator output “Vi ” crosses the voltage window.
III. P ROPOSED C URRENT M EASUREMENT A RCHITECTURE
A. Proposed architecture and principle of operation
The architecture of the proposed current measurement front-
end is shown in Fig. 3, with a voltage output Vout and
frequency outputs foutp and foutn . In each of the two clock
phases ϕ1 and ϕ2 the circuit behaves similarly to the conven-
tional integrator-differentiator structure, with a voltage output
given by:
Cd
Vout = Vref + Rf · Iin · , (9)
Ci
where Vref = VDD /2, Rf = 500 kΩ, Ci1 = Ci2 =
Ci = 0.5 pF and Cd1 = Cd2 = Cd = 10 pF.
A self-timed switched-capacitor reset network is introduced
which minimizes reset transients and prevents the integra-
tor from saturating. Two complementary control signals ϕ1
and ϕ2 alternate the integrator-differentiator between matched
pairs of capacitors Ci1 and Cd1 or Ci2 and Cd2 . Thus at
any given moment, one pair of capacitors is active while
the other is reset. Vref p and Vref n are chosen such that
Vref p − Vref = Vref − Vref n = ∆Vw .
Fig. 4 shows in more detail how the capacitors are reset
for an input current Iin flowing out of the integrator. Initially,
ϕ1 = 1 and ϕ2 = 0, and the input current is being integrated
onto Ci2 , while there is no charge on Ci1 thanks to the
3
Fig. 5. Timing diagram of proposed structure.
closed switch across it. At the moment Vi crosses Vref p ,
ϕ1 and ϕ2 toggle and Ci1 replaces Ci2 as the integrator
capacitor. Similarly, Cd1 replaces Cd2 in the differentiator in
the same instant. Importantly, all of these capacitor operations
are locally charge-balanced, and occur much faster than the
settling time of the amplifiers; current is not supplied from
the amplifier to discharge the capacitors. At the moment of
reset, Vout has only a small impulse due to mismatch, which
does not saturate the output.
The time elapsed between integrator resets contains addi-
tional information about the input current. To consider the
dependence of the frequency output foutp(n) and the input
current Iin , Fig. 5 shows a timing diagram of the integrator
output Vi , the comparator output Vcmpp and the control signal
ϕ1 . For an input current Iin , the slope of the voltage at
the integrator output (Vi ) is Iin /Ci . When the integrator
output voltage exceeds the upper threshold window (Vref p ),
the comparator produces a pulse which reverses foutp , ϕ1
and ϕ2 , and resets the integrator output to Vref . For a fixed
voltage window of ±∆Vw , the output frequency foutp can be
expressed as:
1

∆Vw
−1
Iin
foutp(n) = · = . (10)
2 Iin /Ci 2∆Vw Ci
Equation (10) implies that the output frequency is proportional
to the magnitude of the input current. For example, with
∆Vw = 0.3 V and Ci = 0.5 pF, an input current of 1 pA
corresponds to a output frequency of 3.3 Hz, while 10 µA
corresponds to 33.3 MHz. The polarity of the input current
determines whether foutp or foutn is active.
Compared with other current measurement topologies, the
advantages of this proposed self-resetting structure are: (i)
No external reset/sample clock is needed. Thus, the system
bandwidth is not constrained by a pre-determined sample
rate. (ii) Since both the integrator and differentiator capacitors
are reset in a charge-conserving manner, reset transients and
recovery time are minimized. (iii) The architecture inherently
and instantly transitions between voltage- and frequency-mode
operation, which expands its dynamic range by increasing the
maximum measurable current. The voltage output is more
suitable for smaller and faster current signals, while the
frequency output can represent larger magnitude inputs.
 4

Fig. 6. (a) Single-stage folded-cascode integrator opamp. (b) Two-stage class AB output stage differentiator opamp.

IV. C IRCUIT I MPLEMENTATION AND D ESIGN

C ONSIDERATION
A. Circuit description
The transistor dimensions and bias currents of the integrator
opamp are noted in Fig. 6 (a). Additional bias circuits are
excluded for simplicity. The integrator opamp utilizes a single-
stage folded cascode √ with simulated equivalent input-referred (a)
noise of 4.1 nV/ Hz, and a gain-bandwidth product of
122 MHz when driving Cd = 10 pF. The total static current
consumption of the integrator amplifier is 2.2 mA.
The differentiator utilizes a two-stage cascode-compensated
opamp with a class AB output stage, whose schematic is
presented in Fig. 6 (b) The simulated open-loop gain is 96 dB
and the static current consumption is 0.42 mA. (We note (b)
that although this design meets the given speed and noise Fig. 7. (a) Noise sources inside the integrator-differentiator. (b) The input-
constraints, it has limited power supply rejection and common- referred current noise spectral density diagram of an integrator-differentiator.
mode rejection, and in future iterations this will be replaced
with a fully-differential op amp.)
With Cd = 10 pF, Rf = 500 KΩ, Cf = 0.3 pF and
B. Bandwidth of the integrator-differentiator Ad f0 = 72 MHz, the overall simulated gain of the integrator-
To calculate the cutoff frequency of the overall integrator- differentiator signal path is 140 dBΩ (10 MΩ) and its -3dB
differentiator structure, suppose that the differentiator opamp bandwidth is 1.4 MHz.
has a dominant pole of f0 introduced by the internal miller
capacitance Cm and a dc gain of Ad . The transimpedance gain
T (s) can be then expressed as C. Input-referred current noise of the integrator-differentiator
Vout Cd 1
T (s) = = Rf · , (11) Fig. 7 (a) illustrates the noise sources in the integrator-
Iin Ci 1 + sRf Cf + s2 Rf (Cf +Cd ) 2 is the input-referred voltage noise of
2πAd f0 differentiator, where vn,i
from which the -3dB cutoff frequency fc of the integrator- the integrator opamp, vn,d2 is the input-referred voltage noise
differentiator and the system damping factor ξ can be obtained: of the differentiator opamp, and 4kT Rf is the voltage noise of
1 2ξ the feedback resistor. The input-referred current noise equals
fc = · , (12) the voltage noise at the output divided by the transimpedance
2π Rf Cf
s gain described in (11). Over the frequency range of interest,
Rf Cf2 · 2πAd f0 we assume that the feedback capacitor Cf is small enough so
ξ= . (13) that its effect is negligible; and only take the low-frequency
4(Cf + Cd )
transimpedance gain into account. Thus the output-referred
To minimize the output overshoots and ringing, the damping 2
voltage noise vn,out (V 2 /Hz), and the input-referred current
factor for this second-order system should satisfy ξ ≥ √12 . In noise Sn (ω) (A2 /Hz) can be derived as follows:
other words, based on (13), the differentiator opamp should
have a large gain-bandwidth product (Ad f0 ) to avoid ringing  2
Cp 2
and instability: 2
vn,out = 2
vn,i 1+ ω 2 Cd2 Rf2 + vn,d
2 |1 + jωC R |
d f
2
Ci
1 Cd + Cf 4ξ Cd + Cf 1
Ad f0 = · · ≥ · . (14) + 4kT Rf (15)
2π Cf Rf Cf Cf πRf Cf
 5

One critical factor is clock jitter introduced by the compara-

tor voltage noise, which Fig. 8 illustrates in more detail. When
Vi crosses one of the threshold voltages, the comparator’s
input-referred voltage noise introduces a stochastic delay to the
rising/falling edge of the digital output, affecting the frequency
output. The total voltage noise at the input of the comparators
consists of the integrator’s output-referred voltage noise voutn,i
plus the comparator input-referred voltage noise vn,cmp :
2
vn2 = voutn,i 2
+ vn,cmp (19)
Fig. 8. Comparator timing jitter degrades the signal-to-noise ratio of the From Fig. 8, the clock edge jitter δtjitter at the comparator
frequency output. output can be obtained by
vn Toutp(n) vn
δtjitter = = · (20)
Iin /Ci 2 ∆Vw
2
vn,out where Toutp(n) is the frequency output period and can be
Sn (ω) = 2 ω 2 (C + C )2
= vn,i
2 i p expressed as below according to (10):
Tdc

Ci 1
2 h i 2∆Vw Ci
+ 2
vn,d 1 + ω 2 Cd2 Rf2 + 4kT Rf (16)

Toutp(n) = (21)
C d Rf Iin
The clock jitter limits the minimal detectable change in the
where Cp is the total input capacitance including any parasitic
frequency output. Suppose that there is a small ac current δIin
contribution from interconnects. The integrator and differentia-
2 and v 2 imposed upon a much larger dc input current Iin . By taking
tor opamp input-referred noise densities vn,i n,d exhibit the partial derivative of Toutp(n) in (21) with respect to Iin ,
both flicker noise and thermal noise:
we can find the clock variation/jitter at the frequency output:
KF,i(d)
2
vn,i(d) = + e2n,i(d) (17) 2∆Vw Ci
ω δtjitter = δToutp(n) = − 2 · δIin
Iin
where KF,i(d) is the flicker noise coefficient of the integrator (22)
δIin
(differentiator) opamp, and en,i(d) is the thermal channel noise = −Toutp(n) ·
Iin
from the internal transistors of the integrator (differentiator),
which is independent of frequency. Substituting (17) into (16) Thus, the signal to noise ratio (SNR) can be obtained from
yields a more detailed expression of Sn (ω) in ascending (20) and (22):
powers of ω: δIin δtjitter vn
= = (23)
 2 Iin Toutp(n) ∆Vw
Ci 1 KF,d
Sn (ω) = · With ∆Vw = 300 mV and simulated vn = 44 µVrms over a
Cd Rf ω
 2 bandwidth of 2 MHz, the frequency output has an expected
Ci 1
+ · (e2n,d + 4kT Rf ) SNR of 76.7 dB. Equation (23) shows that SNR of the
Cd Rf frequency output can be improved by using a larger voltage
+ KF,d Ci2 ω + KF,i (Ci + Cp )2 ω window or reducing the total voltage noise referred to the
+ e2n,d Ci2 ω 2 + e2n,i (Ci + Cp )2 ω 2 (18) comparator input node.

Equation (18) is plotted in Fig. 7 (b), where the input-

referred current noise Sn (ω) has three distinct regimes domi-
nated by different noise sources: in the low-frequency regime,
1/f flicker noise from the differentiator opamp dominates;
at moderate frequencies, the Rf thermal noise and channel
thermal noise from the differentiator opamp’s internal transis-
tors determine the flat-band noise floor; at high frequencies,
the dominant noise source comes from the integrator opamp’s
and the differentiator opamp’s voltage noises interacting with
the input capacitance.
D. Signal to Noise Ratio of the Digital Frequency Output
The digital frequency outputs foutp and foutn are generated
asynchronously, and thus do not contain quantization noise
[24]. However, several factors can affect the output frequency
in ways that add noise and nonlinearities.
E. Nonlinearity at the Digital Frequency output
There are two dominant mechanisms which introduce
nonlinearity to the current-to-frequency conversion process:
charge injection from the switches in the integrator, and
propagation delays in the digital logic paths.
1) Channel charge injection: Each time that ϕ1 and ϕ2
toggle, half of the inversion charge from the reset switches
is injected into the left side of Ci1 or Ci2 , introducing an
error voltage at the beginning of the following clock phase.
This is shown in Fig. 9 (a). To reduce the net injected charge,
complementary switches are used to reset the capacitors.
However, the injected channel charge at the start of ϕ1 is
different from that of ϕ2 due to different Vgs of the switch
transistors. For example, during the reset phase of Ci1 , the
source (drain) voltage of its nmos reset switch equals Vref ,
corresponding to channel charge of Wn Ln Cox (VDD − Vref −
 6

(a)

(b)
Fig. 9. (a) Channel charge injection. (b) Total effect of channel charge
injection and propagation delay.
Fig. 10. Chip micrograph, layout, and packaged chip.

Vth,n ). However, during the reset phase of Ci2 , the source

(drain) voltage of its nmos switch follows Vout . The latter
reaches (Vref ± ∆Vw ) at the end, resulting in channel charge
of Wn Ln Cox (VDD − Vref ∓ ∆Vw − Vth,n ).
To simplify the derivation of the charge injection offsets,
we assume that the nmos and pmos devices inside each
Fig. 11. High-level diagram of the measurement setup. Note that the off-chip
complementary switch pair are well matched so that Wn Ln = buffers and anti-aliasing filters are not shown here for simplicity.
Wp Lp = W L, and VDD = 2Vref . In this case:
(Qp − Qn )ϕ1 W LCox (Vth,n − |Vth,p |)
∆eϕ1 = = (24)
2Ci 2Ci

(Qp − Qn )ϕ2,p
∆eϕ2,p =
2Ci
W LCox (Vth,n − |Vth,p | + 2∆Vw )
= (25)
2Ci

(Qp − Qn )ϕ2,n
∆eϕ2,n =
2Ci Fig. 12. Measured and simulated transimpedance gain (Vout /Iin ).
W LCox (Vth,n − |Vth,p | − 2∆Vw )
= (26)
2Ci
where ∆eϕ2,p is the error voltage at the initial of ϕ2 with an Thus we see that both the clock jitter and the nonlinearity
input current flowing out of the integrator input, and ∆eϕ2,n can limit the output frequency accuracy, and that the nonlin-
is with an input current flowing into the integrator input. earity increases for large input currents.
2) Propagation delay: As the integrator output Vi exceeds
the voltage window, as shown in Fig. 3, the integrator resetting
operation is delayed by the propagation time of the compara- V. E XPERIMENTAL R ESULTS
tor, OR gate and D-flip flop. This propagation delay td results
in a longer period or slower output frequency. Our proposed circuit was fabricated in a 180-nm CMOS
process, occupying a total area of 240 µm × 380 µm and
The total effect of channel charge injection and propagation consuming 2.9 mA from a 1.8 V supply. Fig. 10 shows the
delay is depicted in Fig. 9 (b), based on which the nonlinearity chip micrograph, layout, and the packaged die.
of the frequency outputs can be derived as:
A data acquisition (DAQ) system was developed to measure
−1
the outputs of the proposed circuit, as depicted in Fig. 11. The

foutp,new ∆eϕ1 + ∆eϕ2,p Iin
= 1+ + td , (27) voltage output was sampled by a 14-bit ADC at 6.25 MS/s,
foutp 2∆Vw ∆Vw Ci
buffered on a Xilinx FPGA module (Opal Kelly XEM6310),
−1
and transferred over a USB interface to a Matlab control

foutn,new ∆eϕ1 + ∆eϕ2,n Iin
= 1− + td . (28) interface on a standard PC.
foutn 2∆Vw ∆Vw Ci

(a)
(b)
Fig. 13. (a) Theoretical, simulated and measured equivalent input-inferred
noise density. (b) Input-referred integrated noise versus measurement band-
width.
Fig. 14. Recorded Vout for Iin = 40 pApp (500Hz), with measurement
bandwidth B=100 kHz.
A. Integrator-differentiator measurement
The measured and simulated frequency response of the
integrator-differentiator are shown in Fig. 12. It has a measured
transimpedance gain of 139.6 dBΩ (9.5 MΩ) and a -3 dB
cutoff frequency of 1.4 MHz.
The theoretical, simulated and measured equivalent input
current noises of the integrator-differentiator are illustrated in
Fig. 13 (a). The measured 1/f √ noise corner is 100 Hz, and the
white noise floor is 11.6 fA/ Hz. For a bandwidth of 100 Hz
the measured integrated noise current is 204 fARMS , and for
10 kHz it is 1.25 pARMS , as shown in Fig. 13 (b).
Fig. 14 presents Vout for a 40 pApp 500 Hz square wave
current input, filtered to a bandwidth of 100 kHz. The am-
plitude of this ac signal is too small to cause the integrator
output to exceed the threshold window, and thus foutn/p are
inactive.
Fig. 15 (a) shows measured Vout signal for a 3 nApp 500 Hz
square wave, using a measurement bandwidth of 500 kHz. The
signal is large enough to trigger the reset network, which in-
troduces microsecond-scale impulses on Vout . These impulses
are on the order of several nA, whereas the full range of Vout
is 100 nA, so the amplifier does not saturate. These transients
can be removed with a simple lowpass filter; but for even
better performance, since the transients are perfectly aligned
with switching of foutp and foutn , they can be identified and
removed with digital subtraction. The left curves in Fig. 15 (b)
7
Fig. 15. (a) Recorded Vout for Iin = 3 nApp (500 Hz), with measurement
bandwidth B=500 kHz. (b) From left to right: four glitch patterns recorded
and overlaid from 1,000 reset transients, overlaid tuning curves after digital
subtraction, and overlaid tuning curves after digital subtraction and a 100 kHz
digital low-pass filter. (c) 500 Hz 3 nApp square waveform after digital
subtraction. (d) Waveform after digital subtraction and a 100 kHz digital low-
pass filter.
(a)
(b)
Fig. 16. (a) Frequency outputs with a 300-nApp 10 kHz sinusoid input
current. (b) Reconstructed current signal from foutp and foutn
are aligned and overlaid reset transients (N = 1000), which
fall into four groups corresponding to the rising and falling
edges of foutn and foutp . After classifying the transients, we
average each group separately and subtract the mean from
each impulse in the recorded waveform, and overlay these
digital subtraction tuning curves in the middle of Fig. 15 (b).
The right curves in Fig. 15 (b) are the curves after digital
subtraction and a 100 kHz digital low-pass filter. Fig. 15 (c)
depicts the resulting 500 Hz 3 nApp current waveform with
digital subtraction, and Fig. 15 (d) shows the waveform after
a further 100 kHz digital low-pass filter.
B. Current-to-frequency converter measurement
In addition to looking at transients in Vout , we can also
recover time-varying signals directly from the modulations of
frequency in fout . To illustrate this concept, we introduced a
bipolar 300 nApp 10 kHz sinusoidal current. Fig. 16 (a) plots
the resulting digital outputs foutp and foutn . By measuring

Fig. 17. Spectrum of a sinusoidal current signal reconstructed from fout for
a 500 kHz 500 nApp signal applied on top of a 2 µA DC input current.
Fig. 18. Measured output frequency and linearity error of fout versus Iin .
the time intervals between adjacent frequency pulse edges,
Fig. 16 (b) shows the reconstructed current signal based on
the relationship expressed in (21).
In a second example, a 500 kHz 500 nApp sinusoidal
current was applied with a dc offset of 2 µA. This produced
a modulated frequency output, with a carrier frequency of
6.67 MHz and a fundamental frequency of 500 kHz, which
we then reconstructed/demodulated based on (21). Fig. 17
presents the spectrum of the reconstructed signal, showing
the expected peaks at the fundamental frequency and its
harmonics. For a 2 MHz bandwidth, the calculated SNDR is
35.2 dB.
Fig. 18 shows the measured fout frequency versus dc input
current Iin , along with its linearity error. The maximum mea-
surable current is 11.6 µA (33.18 MHz), corresponding to a
dynamic range of nearly 8 decades. Currents less than 100 nA
can be observed on both the frequency and voltage outputs, but
for the lowest amplitude signals the integrator-differentiator
output offers the best fidelity and wider bandwidth.
C. Biological Ion Channel Current Recordings
As a demonstration of one of the applications for this
new CMOS current measurement system, we recorded ionic
currents through alamethicin channels in reconstituted lipid
bilayers. Alamethicin is an antibiotic peptide which forms
ionic channels in lipid membranes, and is often used as
a biophysical model for voltage-gated ion channels in cell
membranes [25].
8
As shown in Fig. 19, a conical aperture was fabricated
in an ≈50-µm-thick glass membrane at the end of a glass
capillary [26]. The glass surface was modified with 2% (v:v)
3-cyanopropyldimethylchlorosilane in CH3 CN overnight at
room temperature to introduce a moderately hydrophobic sur-
face. The capillary was filled with 1M KCl, and an Ag/AgCl
electrode was inserted into it and connected to the CMOS
current measurement input. A lipid bilayer was then painted
across the glass aperture using a solution of 1,2-diphytanoyl-
sn-glycero-3-phosphochline dissolved in decane at 10 mg/mL.
Using a syringe, the liquid level was slowly raised above the
glass aperture to form the bilayer. A small quantity of alame-
thicin (Sigma) was added to the electrolyte. The alamethicin
was suspended in ethanol at 1 mg/mL and refrigerated before
use.
At low bias voltages, the lipid membrane was insulating,
leading to a measured ion current less than 1 pA, and fout
toggled at approximately 1 Hz. As the bias voltage increased,
intermittent stepwise bursts appeared, which correspond to
single ion channels formed by groups of alamethicin molecules
inserted into the bilayer. The recorded single-channel currents
in Fig. 19 were processed to remove reset transients and fil-
tered at a bandwidth of 30 kHz. At higher bias voltages, Popen
increases and the measured current increases exponentially.
D. Performance Comparison
Table I summarizes the proposed front-end performance and
compares it with other recent state-of-the-art demonstrations.
Especially notable in this work is the dramatic improvement
in dynamic range, while maintaining a competitive noise
floor and signal bandwidth. This is achieved with a simple
asynchronous architecture which naturally adapts to the input
signal, and whose measurement bandwidth is not limited by a
predetermined clock frequency. It is also worth noting that
the proposed system can access its entire dynamic range
instantaneously, without the settling time or complexity of a
secondary offset subtraction loop.
VI. C ONCLUSION
An integrated dual-mode low-noise current measurement
front-end is presented. This circuit is uniquely suited for high
dynamic range electrochemical measurements. The system
operates concurrently as a low-noise linear amplifier and as
a high dynamic range asynchronous current-to-frequency con-
verter, with no nonlinear reset transients, no external control
loop, and no dead time. A dynamic range spanning pA to µA
offers the possibility of observing single-unit and macroscale
electrochemical and electrophysiological responses within the
same experiment.
ACKNOWLEDGMENT
The authors would like to thank the anonymous reviewers
for helpful suggestions which improved the quality of this
paper. This work was supported in part by a sponsored research
agreement from Hoffmann-LaRoche.
 9

Fig. 19. Lipid bilayer experimental setup and recorded ionic currents with 30 kHz measurement bandwidth under different voltages.

TABLE I
P ERFORMANCE C OMPARISON OF CMOS C URRENT M EASUREMENT F RONT-E ND C IRCUITS

[7] [8] [12] [13] [27] [28] [29] This work

Technology 0.35µm CMOS Discrete IC 0.5µm CMOS 0.35µm CMOS 90nm CMOS 0.35µm CMOS 0.35µm CMOS 0.18µm CMOS
Area (mm2 ) 0.34 NA 0.14 0.30 0.065 0.5 5 0.091
Noise√floor 4 8.5 6 <42.1 0.235 5 3 11.6
(f A/ Hz)
Current noise floor * ∼400 fA 3.4 pA 2.44 pA 4.21 pA 75 fA pA’s 1.2 pA 204 fA (100 Hz)
(Meas. bandwidth) (10 kHz) (10 kHz) (10 kHz) (10 kHz) (1 kHz) (1 kHz) (10 kHz) 1.25 pA (10 kHz)
Max. Meas. current 25 nA 158 nA 13 nA 369 nA 200 pA 5 nA 20 nA 11.6 µA
Dynamic range 95.9 dB 93.3 dB 74.5 dB 98.9 dB 68.5 dB 74.0 dB 84.4 dB 155.1dB @ BW=100 Hz
140.8 dB @ BW=10 kHz
Sampling clock fs None None 100 Hz–100 kHz None 2 kHz–10 kHz 7.8 kHz None None
Signal bandwidth 4 MHz 950 kHz 50 Hz–50 kHz 10 kHz 1 kHz–5 kHz 3.9 kHz 10 kHz 1.4 MHz
Power Consump. 45 mW 65 mW 1.5 mW 0.5 mW 0.147 mW 23 mW 40 mW 5.22 mW
@supply voltage @±1.5 V @5V @3.3 V @±1.5 V @2.5 V/1 V @3.3 V @3.3±1.65 V @1.8 V
* Integrated RMS input-referred noise over the specified measurement bandwidth

R EFERENCES [12] B. Goldstein, D. Kim, A. Rottigni, J. Xu, T. K. Vanderlick, and E.

[1] A. J. Bard and L. R. Faulkner, Electrochemical Methods: Fundamentals
and Applications,2nd ed. New York, NY, USA: Wiley, 2001.
[2] F. Bezanilla, “Voltage-gated ion channels,” IEEE Trans. Nanobioscience,
vol. 4, no. 1, pp. 34-48, 2005.
[3] S. Dai, and J. K. Rosenstein, “A dual-mode low-noise nanosensor front-
end with 155-dB dynamic range,” in Proc. IEEE Biomed. Circuits Syst.
Conf., 2015.
[4] M. Crescentini, M. Bennati, M. Carminati and M. Tartagni, “Noise
limits of CMOS current interfaces for biosensors: A review,” IEEE Trans.
Biomed. Circuits Syst., vol. 8, no. 2, pp.278-292, 2013.
[5] D. Kim, B. Goldstein, W. Tang, F. J. Sigworth, and E. Culurciello, “Noise
analysis and performance comparison of low current measurement systems
for biomedical applications,” IEEE Trans. Biomed. Circuits Syst., vol. 7,
no. 1, pp. 52-62, 2013.
[6] R. Sherman-Gold, The Axon Guide for Electrophysiology and Biophysics
Laboratory Techniques, 3rd Ed. Foster City, CA, USA: Axon Instruments,
2008.
[7] G. Ferrari, F. Gozzini, A. Molari, and M. Sampietro, “Transimpedance
amplifier for high sensitivity current measurements on nanodevices,” IEEE
J. Solid-State Circuits, vol. 44, no. 5, pp. 1609-1616, 2009.
[8] C. L. Hsu, H. Jiang, A. G. Venkatesh, and D. A. Hall, “A Hybrid Semi-
Digital Transimpedance Amplifier With Noise Cancellation Technique for
Nanopore-Based DNA Sequencing,” IEEE Trans. Biomed. Circuits Syst.,
vol.9, no.5, pp.652-661, 2015.
[9] J. K. Rosenstein, M. Wanunu, C. Merchant, M. Drndic, K. L. Shepard,
“Integrated Nanopore Sensing Platform with Sub-Microsecond Temporal
Resolution,” Nature Methods, vol. 9, pp. 487-492, 2012.
[10] J. K. Rosenstein, S. Ramakrishnan, J. Roseman, K. L. Shepard, “Single
Ion Channel Recordings with CMOS-Anchored Lipid Membranes,” Nano
Letters, 2013.
[11] M. M. Ibrahim, and P. M. Levine, “CMOS transimpedance amplifier for
biosensor signal acquisition,” in Proc. IEEE Biomed. Circuits Syst. Conf.,
pp. 25-28, 2014.
Culurciello, “CMOS low current measurement system for biomedical
applications,” IEEE Trans. Biomed. Circuits Syst., pp. 111-119, 2012.
[13] J. Kim, R. Maitra, K. D. Pedrotti, and W. B. Dunbar, “A patch-clamp
ASIC for nanopore-based DNA analysis,” IEEE Trans. Biomed. Circuits
Syst., vol. 7, no. 3, pp. 285-295, 2013.
[14] G. Massicotte, S. Carrara, G. Di Micheli and M. Sawan, “A CMOS
Amperometric System for Multi-Neurotransmitter Detection,” IEEE Trans.
Biomed. Circuits Syst., vol. 10, no. 3, pp. 731-741, 2016.
[15] A. Gore, S. Chakrabartty, S. Pal, and E.C. Alocilja, “A multichannel
femtoampere-sensitivity potentiostat array for biosensing applications,”
IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 11, pp. 2357-2363,
2006.
[16] M. Stanacevic, K. Murari, A. Rege, G. Cauwenberghs, and N.V. Thakor,
“VLSI potentiostat array with oversampling gain modulation for wide-
range neurotransmitter sensing,” IEEE Trans. Biomed. Circuits Syst., vol.1,
no.1, pp. 63-72, 2007.
[17] H.M. Jafari, and R. Genov, “Chopper-stabilized bidirectional current
acquisition circuits for electrochemical amperometric biosensors,” IEEE
Trans. Circuits Syst. I, Reg. Papers, vol.60, no.5, pp.1149-1157, 2013.
[18] D. L. Bellin, H. Sakhtah, Y. Zhang, A. Price-Whelan, L. E. P. Dietrich,
and K. L. Shepard, “Electrochemical camera chip for simultaneous imaging
of multiple metabolites in biofilms,” Nature communications, vol. 7, 2016.
[19] H. Li, C. S. Boling, and A. J. Mason, “CMOS Amperometric ADC With
High Sensitivity, Dynamic Range and Power Efficiency for Air Quality
Monitoring,” IEEE Trans. Biomed. Circuits Syst., pp. 1-11, 2016.
[20] G. Meszaros, C. Li, I. Pobelov, and T. Wandlowski, “Current mea-
surements in a wide dynamic range – applications in electrochemical
nanotechnology,” Nanotechnology, vol.18, no.42, 2007.
[21] R. R. Harrison, I. Kolb, S.B. Kodandaramaiah, A.A. Chubykin, A.
Yang, M.F. Bear, E.S. Boyden, and C.R. Forest, “Microchip amplifier
for in vitro, in vivo, and automated whole-cell patch-clamp recording,”
J. Neurophysiology, 2014.
[22] M. Gu, and S. Chakrabartty. “Design of a Programmable Gain, Tem-
perature Compensated Current-Input Current-Output CMOS Logarithmic
 10

Amplifier.” IEEE Trans. Biomed. Circuits Syst., vol. 8, no. 3, pp. 423-431, Jacob K. Rosenstein is an Assistant Professor of
2014. Engineering at Brown University in Providence, RI.
[23] C. Chen, S. Yemenicioglu, A. Uddin, E. Corgliano, L. Theogarajan, He received Sc.M. and Ph.D. degrees in electrical
“A CMOS enhanced solid-state nanopore based single molecule detection engineering from Columbia University in 2009 and
platform,” in Proc. 35th Annu. Int. Conf. IEEE Engineering in Medicine 2013, respectively, and an Sc.B in Computer Engi-
and Biology Soc., pp. 164-167, 2013. neering from Brown University in 2005. From 2005
[24] S. Ouzounov, R. Engel , A. H. Johannes, W. Gerard, and R. Arthur, to 2008 he worked as a hardware systems engineer
“Analysis and design of high-performance asynchronous sigma-delta mod- at Analog Devices Inc, and MediaTek Wireless Inc,
ulators with a binary quantizer,” IEEE J. Solid-State Circuits, vol. 41, no. in Wilmingon, MA. His current research interests
3, pp. 588-596, 2006. include mixed-signal circuit design, biomolecular
[25] J. E. Hall, I. Vodyanoy, T. M. Balasubramanian, and G. R. Marshall, sensors, and biomedical electronics.
”Alamethicin. A rich model for channel behavior.,” Biophys. J., vol. 45,
no. 1, pp. 233-247, 1984.
[26] X. Zhang, B. Galusha, J. Shiozawa, P. G. Wang, G. Bergren, A. J. Jones,
R. M. White, R. J. Ervin, E. N. Cauley, C. C. H. S. White, ”Bench-Top
Method for Fabricating Glass-Sealed Nanodisk Electrodes, Glass Nanopore
Electrodes, and Glass Nanopore Membranes of Controlled Size”.Anal.
Chem. 79, pp. 4778-4787, 2007.
[27] J. Lu, and J. Holleman, “A wideband ultra-low-current on-chip amme-
ter,” in Proc. IEEE Custom Integr. Circ. Conf, 2012.
[28] M. Bennati, F. Thei, M. Rossi, M. Crescentini, G. D’Avino, A. Baschi-
rotto, and M. Tartagni, “A Sub-pA ∆Σ Current Amplifier for Single-
Molecule Nanosensors,” in IEEE Int. Solid-State Circuits Conf. (ISSCC),
Dig. Tech. Papers, pp. 348-349, 2009.
[29] M. Crescentini, F. Thei, M. Bennati, S. Saha, M. R. de Planque, H. Mor-
gan, and M. Tartagni, “A Distributed Amplifier System for Bilayer Lipid
Membrane (BLM) Arrays With Noise and Individual Offset Cancellation,”
IEEE Trans. Biomed. Circuits Syst., pp. 334-344, 2015.

Shanshan Dai received the B.Sc. degree in micro-

electronics from Fudan University, Shanghai, China,
and the M.Sc. degree in computer engineering from
Boston University, Boston, MA, in 2010 and 2012,
respectively. Now she is pursuing her Ph.D. degree
in electrical engineering at Brown University. Her
current research interests include design and model-
ing of low-power analog circuits, and mixed signal
integrated circuit design.

Rukshan T. Perera Rukshan T. Perera is a postdoc-

toral associate at Brown University in Providence,
RI. He received his B.Sc. in 2008 from the Univer-
sity of Rajarata, Sri Lanka and M.Sc. from Central
Michigan University in 2011. His Ph.D. research
at the University of Utah (2011-2015) focused on
fundamentals and applications of solid-state and
biological nanopores. His current research interests
include single molecule electrochemical sensors.

Zi Yang received the B.Eng. degree in automa-

tion from Shanghai Maritime University, Shanghai,
China, in 2010 and the M.S. degree in electrical
engineering from Brown University, Providence, RI,
USA, in 2015. He is currently a senior field appli-
cation engineer with DJI, Shenzhen, China.

View publication stats