Documente Academic
Documente Profesional
Documente Cultură
0
Product Version 12.0
December 2012
© 2011-2012 Cadence Design Systems, Inc. All rights reserved.
Printed in the United States of America.
Cadence Design Systems, Inc. (Cadence), 2655 Seely Ave., San Jose, CA 95134, USA.
Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. (Cadence)
contained in this document are attributed to Cadence with the appropriate symbol. For queries
regarding Cadence’s trademarks, contact the corporate legal department at the address shown
above or call 1-800-862-4522.
Restricted Print Permission: This publication is protected by copyright and any unauthorized
use of this publication may violate copyright, trademark, and other laws. Except as specified in this
permission statement, this publication may not be copied, reproduced, modified, published,
uploaded, posted, transmitted, or distributed in any way, without prior written permission from
Cadence. This statement grants you permission to print one (1) hard copy of this publication
subject to the following conditions:
1. The publication may be used solely for personal, informational, and noncommercial
purposes;
2. The publication may not be modified in any way;
3. Any copy of the publication or portion thereof must include all original copyright, trademark,
and other proprietary notices and this permission statement; and
4. Cadence reserves the right to revoke this authorization at any time, and any such use shall
be discontinued immediately upon written notice from Cadence.
Disclaimer: Information in this publication is subject to change without notice and does not
represent a commitment on the part of Cadence. The information contained herein is the
proprietary and confidential information of Cadence or its licensors, and is supplied subject to, and
may be used only by Cadence’s customer in accordance with, a written agreement between
Cadence and its customer. Except as may be explicitly set forth in such agreement, Cadence
does not make, and expressly disclaims, any representations or warranties as to the
completeness, accuracy or usefulness of the information contained in this document. Cadence
does not warrant that use of such information will not infringe any third party rights, nor does
Cadence assume any liability for damages or costs of any kind that may result from use of such
information.
Contents
1. 11
About This Manual 11
How This Document Is Organized 11
Related Documents 11
EDI System Product Documentation 11
2. 13
Release Overview 13
Release 12.0 Overview 13
New Text Commands and Global Variables 13
New Command Parameters 15
Obsolete Text Commands and Global Variables 21
Supported in this Release 21
Removed from Software 23
Obsolete Command Parameters 24
Supported in this Release 24
Removed from the Software 25
Default Behavior Changes 28
3. 29
Licensing Changes for Release 12 29
Release 12.0 Enhancements 29
Product Changes for 20nm Support 29
Multi-CPU Acceleration Tokens for ETS-XL Changed to Four 29
4. 30
Foundation Flows 30
Release 12.0 Enhancements 30
New Variables for Foundation Flow 30
Support for Power Domain - Delay Corner Binding Via 30
Hierarchical Two-Pass Automated Re-budgeting Flow Extended 30
5. 31
EDI System Display and Tools 31
Release 12.0 Enhancements 31
Ruler Enhancements 31
New and Enhanced Ruler Modes 31
Total Ruler Length Display 33
Auto Snap to Object Edges 33
Custom Colors 33
Enhancements in Pin Display and Selection 33
New Option for Viewing Enlarged Logical Pins 33
19. 86
Timing 86
Release 12.0 Enhancements 86
Constraint Handling Enhancements 86
Ability to Override Local Clock Latency Value 86
Reporting Enhancements 86
Added New Global Variable to Track Reported Paths Limit 86
Ability to Report on AOCV Stage Counts 87
Timing Report Enhanced to Show Markers for Pins 88
Added New Command to Report AOCV Derating Factors 88
Added New Parameters for Statistical Derating 88
Ability to Perform Arc-Based AOCV Weight Analysis 89
Added New Global to Improve Reporting of Clock Objects 89
Added New Property Attribute 89
Added New Property to Report Constants 89
Added New Library Properties 89
Report_timing Command Enhanced 90
Timing Modeling 90
Ability to Perform AOCV-Based ETM Extraction 90
do_extract_model Command Enhancements 91
Other Enhancements 91
Ability to Perform AOCV Analysis on Data Paths 91
Added New Property to Report Macros 91
Added New Global to Control Clock Reconvergence 91
20. 92
Timing Debug 92
New Options for load_timing_debug_report 92
21. 93
Verification 93
Release 12.0 Enhancements 93
New Command To Support 20nm and Lower DRC Rules 93
Verify Geometry Enhancements 93
Option -minPinArea Now Obsolete 93
Option -warning Now Obsolete 93
Violation Browser Enhancements 93
Auto Zoom Enhanced To Display Only Active Layers for Violations 93
Option Added for Limiting Number of Errors Displayed Per Type 94
Support Added for Complex Logical Expressions for Filtering Violations 95
New Forms Added for Loading and Saving DRC Markers 95
22. 97
Power Calculation 97
Release 12.0 Enhancements 97
read_activity_file Parameters Consolidated 97
28. 118
OpenAccess 118
Release 12.0 Enhancements 118
New Command to Access the 5.x Library Structure 118
New Parameter to Add Voltage Information to the Nets 118
29. 119
TSV 119
Release 12.0 Enhancements 119
Embedded Bump Flow Supported in Hierarchical Designs 119
New Parameter Added to Output Selected Bumps 119
30. 120
Timing Optimization 120
Release 12.0 Enhancements 120
New Command Introduced 120
timeDesign Command Updated 120
reclaimArea Command Updated 120
setOptMode Command Updated 120
New Parameters Added 120
GigaOpt as the Default Optimization Engine 121
Obsolete Parameters 121
31. 122
Placement 122
Release 12 Enhancements 122
New Commands 122
New Options for setPlaceMode 122
New Option for addFillerGap 122
32. 124
Yield Analysis 124
Release 12.0 Enhancements 124
Yield Analysis Discontinued 124
33. 125
Delay Calculation 125
Release 12.0 Enhancements 125
Vectorized Delay Calculation Support in MMMC with AAE 125
34. 126
Netlist-to-Netlist 126
Release 12.0 Enhancements 126
runN2NOpt -optimizeYield Parameter Now Obsolete 126
35. 127
Prototyping Foundation Flow 127
Release 12.0 Enhancements 127
1
About This Manual
This manual provides information about Product Version 12 of the Cadence® Encounter® Digital
Implementation System family of products.
The Encounter Digital Implementation System (EDI System) family encompasses the following
products:
Encounter Digital Implementation System L
Encounter Digital Implementation System XL
NanoRoute® Ultra SoC Routing Solution
Virtuoso® Digital Implementation
Encounter Timing System L
Encounter Timing System XL
Encounter Power System L
Encounter Power System XL
First Encounter™ L
First Encounter XL
First Encounter GXL
Related Documents
For more information about the EDI System family of products, see the following documents. You
can access these and other Cadence documents with the Cadence Help documentation system.
README file
Contains installation, compatibility, and other prerequisite information, including a list of
Cadence Change Requests (CCRs) that were resolved in this release. You can read this
file online at downloads.cadence.com.
2
Release Overview
Release 12.0 Overview
New Text Commands and Global Variables
New Command Parameters
Obsolete Text Commands and Global Variables
Supported in this Release
Removed from Software
Obsolete Command Parameters
Supported in this Release
Removed from the Software
Default Behavior Changes
Variables
get_well_tap_mode Placement
Commands
and Global
Variables
getPinConstraint Partition
Commands
and Global
Variables
init_design_uniquify Import and
Export
Commands
and Global
Variables
place_connnected Placement
Commands
and Global
Variables
proto_design Prototyping
Foundation
Flow
Commands
report_pba_aocv_derate Timing
Analysis
Commands
report_rcdb RC
Extraction
Commands
set_message General
Commands
and Global
Variables
timing_cppr_skip_clock_reconvergence Timing
Global
Variables
timing_extract_model_aocv_mode Timing
Global
Variables
timing_property_clock_used_as_data_unconstrained_clock_source_paths Timing
Global
Variables
timing_report_enable_markers Timing
Global
Variables
timing_report_enable_max_path_limit_crossed Timing
Global
Variables
verify_drc Verify
Commands
-wires_only
editDeselect Wire Edit Commands
-wires_only
getFlipChipMode Flip Chip Commands and Global
-prevent_via_under_bump Variables
load_timing_debug_report Timing Debug Commands
-additonal_slack_past_wns
-num_path
-proto
-fplan Variables
set_clock_latency Timing Constraint Commands
-clock_gate
setDelayCalMode Delay Calculation Commands
-combine_mmmc
-timeDesignExpandedView
-timeDesignReportNet
-postRouteAreaReclaim
-create_characterize_percent_rt_blockage
-identify_partition_min_inst
-identify_partition_max_inst
-create_gate_area
-create_gate_count
-accumulated_small_attacker_threshold
-individual_attacker_threshold
-separate_delta_delay_on_data
-delta_delay_annotation_mode
-switch_prob
-receiver_peak_limit
-input_glitch_thresh
The following obsolete text commands and global variables will continue to be supported in this
release, but will be removed in the next major release of the software.
createObsAroundInst
Use the createPlaceBlockage command instead.
auto_fetch_dc_sources
Use the create_power_pads command instead.
add_pad_location
This command has not been replaced.
clear_pad_loc_display
Use the create_power_pads command instead.
delete_pad_location
This command has not been replaced.
display_pad_loc
Use the create_power_pads command instead.
getAllowedPinLayersOnEdge
getGlobalMinPinSpacing
getLayerPinDepth
getLayerPinWidth
getMinPinSpacing
getMinPinSpacingOnEdge
getPinDepth
getPinToCornerDistance
getPinWidth
Use the getPinConstraint command instead. It provides the needed functionality for
all these commands.
load_pad_location
Use the create_power_pads command instead.
save_pad_location
Use the create_power_pads command instead.
setAllowedPinLayersOnEdge
setGlobalMinPinSpacing
setLayerPinDepth
setLayerPinWidth
setMinPinSpacing
setMinPinSpacingOnEdge
setPinDepth
setPinToCornerDistance
setPinWidth
Use the setPinConstraint command instead. It provides the needed functionality for
all these commands.
setOptMode
congOpt
considerNonActivePathGroup
critPathCellYield
postRouteAllowOverlap
yieldEffort
The following obsolete text commands and global variables have been removed from the
software.
createNdr
This command has been replaced by add_ndr .
elaborateBlackBlob
This command has not been replaced.
initNdr
This command has been replaced by add_ndr .
loadBlackBlobNetlist
This command has not been replaced.
loadYieldTechFile
This command has not been replaced.
modifyNdrViaList
This command has been replaced by add_ndr .
reportYield
This command has not been replaced.
setPrerouteAsObs
This command has been replaced with the setPlaceMode option -
prerouteAsObs
setNdrSpacing
This command has been replaced by add_ndr .
setNdrWidth
This command has been replaced by add_ndr .
specifyBlackBlob
This command has not been replaced.
unplaceBlackBlob
This command has not been replaced.
unspecifyBlackBlob
This command has not been replaced.
The following obsolete text command parameters will continue to be supported in this release, but
will be removed in the next major release of the software. Update your scripts to avoid warnings
and to ensure compatibility with future releases.
checkPinAssignment
-busGuideCheck
-netGroupCheck
-pinAbutmentCheck
-pinDepthCheck
-pinGroupCheck
-pinGuideCheck
-pinLayerCheck
-pinMinAreaCheck
-pinOnFenceCheck
-pinOnTrackCheck
-pinSpacingCheck
-pinWidthCheck
Use -ignore {bus_guide net_group pin_abutment pin_depth
pin_group pin_guide pin_layer pin_min_area pin_on_fence
pin_on_track pin_spacing pin_width clones} instead.
optPowerSwitch -reportViolationsOnly
Use -reportOnly instead.
-unchainByInstances
The -unchainByInstances parameter of the addPowerSwitch command has been
replaced by commandrechainPowerSwitch.
-chainByInstances
The -chainByInstances parameter of the addPowerSwitch command has
been replaced by the command rechainPowerSwitch parameter -
chainByInstances.
-powerDomainBufList
The -powerDomainBufList parameter of the bufferTreeSynthesis command
will be removed in the next release. You can specify both always-on and regular buffers in
the buffer list. bufferTreeSynthesis will be able to pick up the right buffer.
-srpgEnablePins
The -srpgEnablePins parameter of the bufferTreeSynthesis command will
be removed in the next release. optDesign is able to optimize the always-on nets
automatically.
getVerifyGeometryMode -minPinArea
setVerifyGeometryMode -minPinArea
verifyGeometry -minPinArea
Use the -sameCellViol parameter of these commands instead to report minimum area
violations for pin shapes in the cell, along with other cell violations.
getVerifyGeometryMode -warning
setVerifyGeometryMode -warning
verifyGeometry -warning
This parameter is not being replaced as Verify Geometry does not write warning markers.
runN2NOpt -optimizeYield
This parameter is not being replaced as the Yield Analysis feature is becoming obsolete.
The following obsolete text command parameters have been removed from the software.
fcroute
-allowOverCongestion
This parameter is not being replaced.
-balancePairThreshold
Use the THRESHOLD keyword in the DIFFPAIR section of the constraint file.
-connectPowerCellToBump
Use setFlipChipMode -connectPowerCellToBump instead.
-differentialPairRoute
Specify the pair of nets in the DIFFPAIR section of the constraint file.
-differentialRoute
Use the exta configuration file option
srouteDifferentialRouteTolerance instead.
-differentialRouteTolerance
Use the TOLERANCE keyword in the MATCH section of the constraint file instead.
-interleaveStyle
Use SPLITSTYLE keyword in the constraint file instead.
-multiBumpsToPad
Use setFlipChipMode -multipleConnection multiBumpsToPad instead.
-multiPadsToBump
Use setFlipChipMode -multipleConnection multiPadsToBump instead.
-optWidth
Use the exta configuration file option srouteGrouteOptimizeWidth instead.
-preventViaUnderBump
Use setFlipChipMode -prevent_via_under_bump instead.
-routeStyle
Use setFlipChipMode -route_style instead.
-shieldBump
Use the SHIELDBUMP keyword in the SHIELDING section of the constraint file instead.
-shieldLayers
Use the SHIELDSTYLE keyword in the SHIELDING section of the constraint file instead.
-shieldNet
Use the SHIELDNET keyword in the SHIELDING section of the constraint file instead.
-shieldWidth
Use the SHIELDWIDTH keyword in the SHIELDING section of the constraint file instead.
-splitGap
Use the SPLITGAP keyword in the constraint file instead.
-widthLimit
Use the SPLITWIDTH keyword in the constraint file instead.
getNanoRouteMode and setNanoRouteMode
-dbCheckRule
-dbReportWireExtraction
-dbReportWireExtractionEcoOnly
-drouteAutoCreateShield
-drouteCheckMinstepOnTopLevelPin
-drouteElapsedTimeLimit
-routeAutoGgrid
-routeDeleteAntennaReroute
-routeInsertAntennaInVerticalRow
-routeMergeSpecialWire
-routeSiEffort
-routeTdrEffort
-routeUseBlockageForAutoGgrid
-routeWithSiPostRouteFix
-timingEngine
These parameters are not being replaced.
setExtractRCMode
-ipdb
This parameter is no longer required as this feature is now ON by default.
-noReduce
This parameter is no longer required as the software does not perform RC reduction by
default.
-rcdb
This parameter is no longer required as the software generates the RCDB in the current
working directory by default.
-scOpTemp
This parameter is not supported in the MMMC mode. Use the -T parameter of the
create_rc_corner and update_rc_corner commands instead.
-useNDRForClockNets
This parameter is no longer required as this feature is now ON by default.
setPlaceMode
-blockedShifterCols
-blockedShifterRows
-colShiftersOnly
-dividedShifterCols
-dividedShifterRows
-rowShiftersOnly
-strictShifterSide
-strictShifterSpot
-rpSpreadEffort
spefIn -dumpMissedNet
This parameter is no longer required as the software prints the missing nets in file
rc_corner_name.missing_nets.rpt by default.
Note: Each description in this list is also the section in the What's New where you can find more
detailed information on the specific behavior change.
Power Variation in Switching Power Numbers when Running Power Analysis from
Calculation EDI
Rail Analysis Change in Extraction Results for Designs with Dangling Resistors
Block Level DEF Pin Checking Capability Enhanced
3
Licensing Changes for Release 12
Release 12.0 Enhancements
Product Changes for 20nm Support
Multi-CPU Acceleration Tokens for ETS-XL Changed to Four
For more information, see Checking Out Licenses for Product Options in the Product and
Licensing Information chapter of the EDI System User Guide.
4
Foundation Flows
Release 12.0 Enhancements
New Variables for Foundation Flow
Support for Power Domain - Delay Corner Binding Via
Hierarchical Two-Pass Automated Re-budgeting Flow Extended
5
EDI System Display and Tools
Release 12.0 Enhancements
Ruler Enhancements
New and Enhanced Ruler Modes
Total Ruler Length Display
Auto Snap to Object Edges
Custom Colors
Enhancements in Pin Display and Selection
New Option for Viewing Enlarged Logical Pins
New Pin Shapes Option in Layer Control Bar
New Option for Highlighting Pin Shapes on Net Selection
Enhancements in Flightline Preferences
New Option for Displaying Only Clock Nets
New Options for Controlling Flightline Color and Width
Enhancement in the Ungroup Feature
Log File Enhancement
find_global Enhancement
set_object_color Enhancement
New Command for Limiting Display of Return Values
New Command To Launch DB Browser
New Form for Going to a Specific Location
New DBTCL Option
New Command to Control Message Severity Level
To end a Single edge ruler, either click at the point where you
want to end the ruler or press Enter.
Orthogonal Specifies that ruler lines can be drawn in horizontal as well as Orthogonal
edges vertical directions. Use this option if you want to measure
orthogonal edges, such as follows:
Multiple Specifies that ruler lines can be turned in multiple directions. Use -
edges this option if you want to measure multiple segments in a complex
pattern.
To draw a Multiple edge ruler, click at the point where you want
the ruler to start. Move the mouse in the required direction, clicking
at evey point you want the ruler to turn. To end the ruler, press
Enter .
Cross Specifies that ruler lines can be drawn in a + shape. Use this -
Ruler option to measure two edges at the same time, see the overall X
You can access the Create Ruler Preferences form either by choosing Tools - Create Ruler or
clicking the Create Ruler widget and press the F3 key.
Custom Colors
You can now change the color of the ruler from the default yellow to any color of your choice. In
the color preferences form, click the color box next to Ruler on the View-Only page and choose
the desired color.
On On Pin shape
You can get a pin's instance terminal (InstTerm) information by selecting the pin and then running
the dbGet selected command.
This enhancement prevents any accidental ungrouping and therefore saves you the effort of
finding and regrouping standard cells and macros that were in the module.
find_global Enhancement
The find_global command has been enhanced to display the variables it returns in alphabetical
order. This makes the find_global results easier to read.
set_object_color Enhancement
The set_object_color command is used to set the color of objects of an instance, hierarchical
instance, SDP, or module. In this release, the set_object_color command has been
enhanced to support power domains and instance groups as well. You can now use
set_object_color -object_name to set the color of objects of a specific power domain or
instance group. Alternatively, you can use set_object_color -object_type to set the
color of all power domain objects or instance group objects. For example, use the following
command to color all power domain objects in multiple colors:
set_object_color -object_type PowerDomain -multicolor
set_message
[-help]
[-id list_of_msgIDs]
6
Multiple CPU Processing
Release 12.0 Enhancements
Memory Reporting Improved
When you run report_resource -verbose, the following detailed memory information is
displayed:
The -verbose parameter also works in conjunction with the -peak and -start/-end
parameters of the report_resource command. When you run the local distributed slave
(setDistributeHost -local) command, the memory information will include the memory
consumed by master and slaves.
For -start/-end parameters, use -verbose with the -end parameter only.
For details on memory information, refer to the Accelerating the Design Process By Using Multiple-
CPU Processing chapter of the EDI System User Guide.
7
Importing and Exporting the Design
Release 12.0 Enhancements
lefOut and defOut Enhanced To Support Embedded Bumps
lefOut Enhanced To Output PG Bump Information along with PG Physical Pins
New Global Variable To Uniquify the Design
New Global Variable for Power Routing
New Options for Command add_shape
In this release, the PASSIVATION layer is used to define an embedded bump in the block. If a
PORT in a block has a PASSIVATION layer, the tool treats it as an embedded bump. lefOut has
been enhanced to output both metal layer and PASSIVATION layer information for the embedded
bump to the LEF file. In addition, the defOut -bumpAsPin option has been enhanced to catch
embedded bumps and output all their layer information (metal layers as well as PASSIVATION
layer geometry) in the PIN section of the DEF file in the same way as for normal bumps.
in EDI11. You can use the init_design_uniquify global variable to uniquify the design
automatically during the read and flatten process.
8
LEF-DEF Properties
Release 12.0 Enhancements
LEF 5.8 Properties for Creating New DRC Rules for 32-28
nm and Smaller Nodes
Cut Layer Enhancements
You can define new CUT LAYER properties to create rules for cut layers that:
Add ANTENNAGATEPWL rule, to define a PWL (piece-wise linear) table that is indexed by
the real gate area, and returns an “effective gate-area” interpolated from the table. If the
table it not defined, the real gate area is used.
Add BELOWENCLOSURE in PARALLEL to cut layer ENCLOSURE rules, to indicate that the
enclosure rule only applies if the enclosure on the below metal layer is less than the
specified below enclosure value on either sides perpendicular to the side having neighbors
or the wire direction containing the cut on the above metal layer.
For more information, see Defining Cut Layer Properties to Create 32/28 nm and Smaller Nodes
Rules in the "LEF Syntax" chapter of the LEF/DEF Language Reference Guide.
You can define new ROUTING LAYER properties to create rules for routing layers that:
Add JOINTCORNERSPACING rule, to indicate that the spacing between two facing joints
of joint corners with parallel run length less than zero to be the spacing.
Add ENCLOSURESPACING rule, to specify the spacing on an edge with enclosure less
than the specified enclosure.
Add ANTENNAGATEPWL rule, to define a PWL (piece-wise linear) table that is indexed by
the real gate area, and returns an “effective gate-area” interpolated from the table. If this
table it not defined, the real gate area is used.
Add CONCAVECORNERS in NOADJACENTEOL to routing layer MINSTEP rules, to indicate
that the adjacent EOL minimum step rules only apply if both the neighbor edges of the EOL
have concave corner on the other end.
Add SAMEMASK to routing layer EOLEXTENSIONSPACING rules, to specify that the EOL
extension spacing only applies to same-mask objects.
Add the following new variables and keywords to routing layer FORBIDDENSPACING
rules:
TWOEDGES in WIDTH, to indicate that the forbidden spacing only applies if the wire
width is less than the maximum width that has neighbors on both sides within the
specified within value.
For more information, see Defining Routing Layer Properties to Create 32/28 nm and Smaller
Nodes Rules in the "LEF Syntax" chapter of the LEF/DEF Language Reference Guide.
9
Wire Editing
Release 12.0 Enhancements
New setSpecialRouteOption options for Supporting Multiple-Layer P/G Pins
New Option for Selecting/Deselecting Via along with Wire
New setViaEdit Option for Creating Special Vias
New setViaEdit Option To Prevent Replacement of Existing Via with New,
Overlapping Via
New setEdit Option for Stretching Wires Along with Via
To turn on the multi-layer P/G pin feature, you must set the new setSpecialRouteOption -
multi_layer_pin option to 1. You can specify the name of the via cell on which you want to
base the multi-layer pin by using the new -multi_layer_via option of
the setSpecialRouteOption command.
You can do the same from the GUI by using the highlighted options in the Special Route Options
form. The Special Route Options form can be accessed by clicking the Options button in the Edit
Route form:
Via selection/deselection happens by default when you select/deselect a wire. If you want to
select/deselect only the wire and not the associated via, use the new -wires_only option of
editSelect and editDeselect, respectively.
Impact on Other Commands, Parameters, and Globals: If you specify the editSelect -
wires_only option and then run editChangeNet, the net will be changed only for the wire
and not for the via.
10
Flip Chip
Release 12.0 Enhancements
Flip Chip Flightline Enhancements
Highlight by Selection
Colored Flightlines
Object-Specific Flightlines
DIFFPAIR-Based Highlighting
New Display Flightline Form
Add Bump to Array Form Renamed and Enhanced
New changeBumpMaster Parameters
New Change Bump Master Form
Enhanced Assign/Unassign Signals Form
New Auto Zoom Feature
New Filter Options
New Criterion for Assigning Bumps
Support for Assigning Multiple PG Pads to Multi Bumps
New assignPGBumps Parameter
New Option for Flip Chip Routing in View Area
Obsolete fcroute Parameters
Highlight by Selection
When you select an object, the corresponding flightlines are now highlighted in bold.
When a bump or IO pad is selected, its corresponding flightline is highlighted in bold.
When multiple bumps/IO pads are selected, all their flightlines are highlighted in bold.
If a block with multiple IO pins is selected, all its flightlines are highlighted in bold.
When the objects are deselected, the corresponding flightlines return to non-bold status.
1. Run
viewBumpConnection
to display all flip chip
flightlines.
2. Click on an object to
highlight its flightline in
bold.
Colored Flightlines
By default, all flip chip flightlines are displayed in yellow. You can now use the new
viewBumpConnnection –honor_color option to color these flightlines based on either
bump type or the nets to which the bumps are assigned:
To color flightlines by bump type, simply run viewBumpConnection –honor_color.
The tool displays flightlines using the default colors of the bumps:
Blue for signal bumps
Red for power bumps
Yellow for ground bumps
To color flightlines based on the nets to which they are assigned, you must:
a. Define bump color settings in a bump color map file using the following format :
net_name color_name
Example:
int cyan
reset pink
For bumps whose nets are not defined in the bump color file, the default colors are
used as follows--blue for signal bumps, red for power bumps, and yellow for ground
bumps. A flightline has the same color as its bump.
Impact on Other Commands, Parameters, and Globals: If you want to assign custom colors to
flightlines, you must specify the colors as required in the bump color map file and
run ciopLoadBumpColorMapFile before running viewBumpConnection –
honor_color.
Object-Specific Flightlines
You can now easily view connections for specific objects, such as bumps, nets, and IO instances,
using the following new viewBumpConnection parameters:
For example, the following command displays the flightlines for the port_pad_data_out[10]
net, the Bump_29 bump, and the IOPADS_INST/Ptdspop07 instance. It also displays in bold
the flightline for the selected bump:
viewBumpConnection \
-net {port_pad_data_out[10]} \
-bump Bump_29 \
-io_inst IOPADS_INST/Ptdspop07 \
-selected \
-honor_color
DIFFPAIR-Based Highlighting
Flip chip flightlines now honor the DIFFPAIR constraints specified in the flip chip router constraint
file. This means that when you select any one bump or IO pad that is part of a DIFFPAIR
constraint, the tool highlights all flightlines of that DIFFPAIR in bold.
For example, suppose the flip chip router constraint file, diffpair.const, has the following
setting:
DIFFPAIR
port_pad_data_in[15]
port_pad_data_in[13]
END DIFFPAIR
Currently, you cannot turn off normal flightlines to focus on DIFFPAIR flightlines. However, you can
use viewBumpConnection –nets net_list as a workaround. Here, net_list specifies
nets of the DIFFPAIR. This way, you can display only the flightlines for the DIFFPAIR and turn off all
other flightlines.
In both cases, the tool changes the cell master to the one specified using the existing -
bumpMasterName parameter.
In this release, the following enhancements have been made to the Assign/Unassign Signals form
to make it easy for you to search for pads, bumps, or nets:
the Get Selected Bump button to compile the names of selected bumps in the text box
automatically. After the required bump names are specified in the In Bump Names text box,
click Assign to call the assignIOPinToBump command. This command assigns the signals
highlighted in the Signal List table to the specified bumps.
Assume that the number of IO Signal selected in the Signal List table is X and the number of
bumps specified in the In Bump Names text box is Y. The bump assignment happens as follows:
If X is equal to Y, the tool completes X assignments.
If X is greater than Y, the tool displays a warning and assigns the first Y pins in selection
order to the bumps.
If X is smaller than Y, the tool displays a warning and assigns all pins to X bumps in the
specified order in the In Bump Names text box.
Use the new assignBump -ratio parameter to assign multiple PG pads to one bump.
For more information, see the Multi-PG Pads to Multi Bumps Assignment with a Controlled
Ratio section in the Flip Chip Methodologies chapter of the EDI System User Guide.
The -checkerboard parameter is to be used typically for a regular (rectangular) bump array.
However, you can also it for an irregular (rectilinear) bump array. To do so, first form a regular array
by creating virtual bumps in the areas where there are no bumps. Then, apply the checkboard
pattern. Once you have assigned the bumps, you can remove the virtual bumps.
Impact on Other Commands, Parameters, and Globals: The checkerboard style can be
used only with two nets. If -checkerboard is specified and the number of nets defined with -
nets is more than two, the tool reports an error and does not assign any bumps.
END DIFFPAIR
END DIFFPAIR
END MATCH
SPLITGAP value
-splitGap Use the SPLITGAP keyword in the constraint SPLITSTYLE RIVER | MESH
file to specify the minimum distance between
split wire segments. SPLITWID TH value
SPLITGAP value
-widthLimit Use the SPLITWIDTH keyword in the
constraint file to specify the maximum width SPLITKEEPTOTALWIDTH TRUE | FALSE
limit for each wire after the split :
11
Partitioning
Release 12.0 Enhancements
Support for Promoting Macro Pins
New Parameters for Specifying Offset
Pin Editor Capability Enhanced
Specify Partition GUI Form Updated
alignPtnClone Command Enhanced
checkPinAssignment Command Enhanced
New Parameter to Specify Keep Out Spacing
Pin Constraint Commands Consolidated
Multi-threading Support for savePartition Command
Support for Saving and Loading Selective Floorplan Data
New Parameter Added to the savePartition Command
New Parameter Added to the assembleDesign Command
New set_ptn_fplan_mode Command Added
New get_ptn_fplan_mode Command Added
Now, even if the floorplan is changed and the modules are moved to a different location, the pin
guides can easily be recreated by specifying the edge and offset instead of co-ordinates.
To accommodate this capability, the Pin Editor GUI form has been updated to allow assignment of
multiple layers:
Additionally, the editPin command has been updated to include the following new parameters:
-include_rectilinear_edge
Specifies that all the edges coming in the solution space should be included.
-layer_priority
-reverse_alternate
Specifies that the reverse of the multi-layer-spread-pattern must be followed by the set of
selected pins.
For more information, refer to the syntax of the editPin command in the Text Command Menu
Reference.
The following new parameters have been added to the alignPtnClone command:
-layer layerV layerH
Specifies a vertical and a horizontal layer for checking alignment with the power grid.
-track
Checks the alignment of partition clones with the master on track basis. This parameter
only generates a report and does not modify the design.
With enhancements in this release, the -ignore parameter has been added using which you
can choose to ignore any of the above mentioned violations while checking the pin assignment.
The following is the updated syntax of the checkPinAssignment command:
checkPinAssignment
[-help]
[topCellName | -ptn ptnName ]
[-pin { pinName | pinNameList }]
[-report_violating_pin ]
[-outFile fileName ]
[-ignore {bus_guide net_group pin_abutment pin_depth pin_group
pin_guide pin_layer pin_min_area pin_on_fence pin_on_track
pin_spacing pin_width clones}]
Additionally, the -report_violating_pin parameter has been added which reports the pins
with violations.
In this release, you can use the new -keep_out_spacing parameter to specify minimum keep
out spacing for a pin group or net group. All pins that are foreign to the pin/net group will be
placed beyond the specified keep out spacing of the pin group.
This parameter has been added to the createNetGroup and the createPinGroup
commands.
Note: These commands are now obsolete as the setPinConstraint command provides the
required functionality . Even though they continue to work in this release, they will be removed in
the next major release of the software.
getPinWidth
Earlier when constraints were specified for pin placement they got lost during the
saveDesign/restoreDesign cycle. With enhancements in this release, all the pin
constraints are retained even after the saveDesign/restoreDesign cycle and are honored
during pin assignment.
Impact on Other Commands, Parameters, and Globals: This change impacts commands
related to pin constraints.
A new –fplan parameter has been added to the savePartition command for pushing
down floorplan changes from a full chip level design to a partition block. This option allows you to
run the savePartition command for an uncommitted partition without running the
partition command. For committed partition savePartition –fplan reports an error.
A new –fplan parameter has been added to the assembleDesign command to bring back
the floorplan changes from a partition block to full-chip level design. The assembleDesign -
fplan command only supports un-committed partitions and replaces the top level uncommitted
partitions with updated block floorplan data.
Note: After assembleDesign –fplan command, any signal net at top-level design may be
overlapped with other floorplan objects. You may need to reroute or ECO route the design.
Additionally, PG net of CHIP, place, and route data may not be brought back.
You can now use the new set_ptn_fplan_mode command to set what floorplan objects will
be written-out and/or read back in. The set_ptn_fplan_mode command allows you to specify
which objects should be written out during savePartition –fplan or read back in during
assembleDesign –fplan.
You can use the new get_ptn_fplan_mode command to retrieve information about the option
values set using set_ptn_fplan_mode command.
12
Floorplanning
Release 12.0 Enhancements
createPGPin Command Enhanced
createObsAroundInst Command is now Obsolete
add_ndr Command Enhanced
Support for Reporting Narrow Channels
Support for Handling Master/Clones in Different Hierarchy
Enhanced Power Domain Placement Capability
Enhanced Auto-shaping for Placing Modules
Support for Virtual fence Option to Handle User-specified Seeds
New Command to Generate Partition Fences Around Flexmodels
Support for Bus Guides in Relative Floorplan
Blackblob Capability made Obsolete
createPGPin
[-help]
{-onDie {-selected | -net netName} [-width value] [-length value]} |
{pgPinName [-net netName] [-geom layerName llx lly urx ury]}
The createObsAroundInst still works in this release but will not be supported in future
releases. To ensure compatibility with future releases, update your scripts to use the
createPlaceBlockage command instead.
Changes have also been made to the syntax of the add_ndr command. You can now specify
the name of the non-default rule using the add_ndr –name parameter.
add_ndr
[-help]
{ ndrRuleName | -name ndrRuleName }
[-init ndrRuleName ]
[-hard_spacing]
[-width {layer1[:layer2] width ... }]
[-spacing {layer1[:layer2] spacing ... }]
[-min_cut {layer1[:layer2] min_cut ... }]
[-via {via_name1 via_name2 ... }]
[-add_via {via_name1 via_name2 ... }]
[-generate_via]
Even the macros belonging to the same guide were separated as the guide boundary was
ignored.
In this release, the –virtualFence parameter has been added to the setPlanDesignMode
command. This parameter enables planDesign to internally treat guide constraints as fences.
Thus, their boundaries are strictly honored. Now macros are packed on the guide boundary which
helps to achieve a better grouping of macros.
To have guide constraints, you can set the createFence constraint while using the
planDesign capability. In seed constraint creation:
BEGIN SEED
name = xxx [createFence = TRUE]
END SEED
When createFence constraint is not set, the seed will be treated as a guide. Also, auto seed
generation feature will group unconstrained macros into guides. When the –virtualFence
option is specified in setPlanDesignMode, the guide constraints will have their boundaries
honored.
In this release, a new generate_fence command has been introduced using which partition
fences, which enclose all their children flexModel guides, can be drawn automatically. This
capability improves the usability of the prototyping flow.
generate_fence
[-help]
[-min_gap float]
[-target_util float]
[ [-hInst {hInst(s)}] | [-module {module(s)}] | [-inst_group
{instGroup(s)}] ]
You can now use the autoGenRelativeFPlan -busGuide command to generate bus guide
segments connection.
Also, use the relativeFPlan command to generate a constraint, bind one bus guide
segment to one reference object. The following parameters have been added to the
relativeFPlan command:
relativeFPlan
[--masterSlave {-masterType masterType -masterName masterName -slaveType slaveType -
slaveName slaveName}]
loadBlackBlobNetlist
specifyBlackBlob
unplaceBlackBlob
unspecifyBlackBlob
13
Structured Data Path
Release 12.0 Enhancements
readSdpFile Command Enhanced To Support More Than 10 skipSpace Variables
Support Added for Reusing SDP Instantiations
New Buttons in the SDP Browser
To improve usability, the SDP file format in this release has been enhanced to support reuse
capability. The data path macro definition can be specified with the new define keyword. Once
specified, this macro definition can be instantiated or and then used multiple times in a data path
specification by using the use keyword.
The SDP reader has been enhanced to handle the new SDP syntax, including nested macro
definitions. The SDP reader can also handle SDP macro definitions that are in a separate SDP file
than the data path that references them.
data path quickly. In previous releases, you had to click the Previous button several times
or restart the browser to return to the top view of the SDP browser.
14
Multiple Supply Voltage (MSV)
Release 12.0 Enhancements
New Options for optPowerSwitch
New Options for reportPowerDomain
New Option for replacePowerSwitch
15
NanoRoute Router
For more information, see the “LEF Syntax” chapter of the LEF/DEF Reference.
-routeWithSiPostRouteFix
-timingEngine
Note: The obsolete command parameters have been removed in this release and have not been
replaced. Update your scripts to avoid warnings and to ensure compatibility with future releases.
The Nanoroute DRC markers are edge based markers which are in design view and Violation
Browser.
16
TrialRoute Router
For more information, see the Design Metrics chapter of the EDI System Text Command
Reference .
17
Timing Budgeting
Release 12.0 Enhancements
Power Pin Support in Budgeted Timing Models for Low Power Designs
Justify Budget Enhanced
Timing Budgeting has been enhanced to support PG pins in budgeting timing models. Therefore, if
a full-chip design has libraries defined with PG pins, timing libraries generated for each
instance/block will have voltage information. To support this enhancement, the budgeting timing
library now imports the following constructs from the full-chip library:
Voltage Maps - are written for all the voltages that are coming inside a partition/instance
for which the timing model is being written.
This information is at the library level. Every voltage has a name given and a value is
associated with it.
Cell Level PG Pin Information - For each voltage map, a related pg pin is defined for the
cell. It will have a pin name and the voltage name it is to be connected to.
pg_pin ( vdd ) {
voltage_name : vdd;
pg_type : primary_power;
direction : input;
physical_connection : device_layer;
}
This information is at the cell level. The pins described in this definition are global in the library
scope. All the pins in the library are considered to be connected to one of these pins.
Pin Level PG Information - At each port of the partition/instance, there will be a related
pg_pin construct that specifies from which power/ground pin is the port being driven.
pin (q) {
related_power_pin : vdd;
related_ground_pin : vss;
.....
For manual budgeting, the budget of the port can change in the following scenarios:
When you directly apply a constraint on the port, the justify report shows the location of the
file from which the constraint has been taken, the applied constraint, and the port on which
it was applied.
Partition: block
Port: sub_in
Budgeted constraint type: set_input_delay(setup rise)
Virtual Clock: clk1_setuphold
Budget Applied by modify budget statement (/../../modify.tcl:3) :
set_input_delay 1.9 -clock [get_clocks {clk1_setuphold}] -
max -rise [get_ports {sub_in}] -add_delay
Applied constraint = 1.900
Start clock: clk1 clock edge: rise
End clock: clk1 clock edge: rise
When you apply a constraint on a connected port, the budget of that port also changes.
The output port will be impacted due to modification at the input port as it is one continuous
path. Budgets are modified at the output port by adjusting the required time of the port with
the extra delta delay given to (or taken away from) the connected port. Therefore, the
modifications at the input port is reflected in the justify report for both the input port and the
output port, wherein, the budgets are being recalculated for the output port based on the
modification.
The justify report has information about the port, the delta and how that delta affected the
constraint value at the given port.
Budget Impacted by modify budget statement (location of the file in which the
applied constraint is specified) :
18
RC Extraction
Release 12.0 Enhancements
RCDB Reading Enhanced to Fix Errors
New Command for Providing Information about the Contents of the RCDB
Obsolete Command Parameters - Removed from the Software
TQRC/IQRC Enhanced to Complete Broken RC Networks
TQRC/IQRC Enhanced to Perform Incremental Extraction After defIn and Metal Fill
Commands
Accuracy of PreRoute Extraction Enhanced for Signal Nets
Reduction in Peak Memory Consumption by spefIn in Sequential Mode
This behavior is unlike that of the SPEF file-based flows that continue even if there is a
design/RCDB mismatch. In this release, the EDI System is enhanced so that the QRC-RCDB flow
also continues to run in such situations. For this, the command, read_parasitics, is
enhanced to do error checking and fixing during RCDB reading. This command fixes the data
when a single flat RCDB is read by using the -force parameter of this command.
report_rcdb
-help
<rcdb_dir_name>
In this release, TQRC/IQRC is enhanced to complete the RC networks of broken nets by adding
low value resistors. The timing value for such nets may not be as accurate as that for other nets
but it is better than when the extraction of broken nets was skipped entirely.
Although this runtime can be reduced by using the multiCPU mode, a much larger runtime
improvement comes from performing incremental extraction where extraction is either skipped or
performed on fewer nets depending on the design/route changes in flow runs.
Currently, incremental extraction capability of TQRC/IQRC is not available after running defIn and
metal fill commands. Therefore, TQRC/IQRC is forced to perform fullchip extraction after running
defIn and metal fill commands.
In this release, TQRC/IQRC incremental extraction support is extended to all types of gray data
changes (defIn) and metal fill changes. The performance, accuracy, and memory will remain the
same as that of the rest of the commands currently supported by incremental extraction.
In this release, the accuracy of preRoute extraction for signal nets is enhanced so that these large
scale factor variations are controlled and remain close to the signoff extraction results for
most designs.
Mode
Earlier, the peak memory consumption during sequential spefIn was almost double that
consumed during multiple-CPU spefIn .
In this release, the software is enhanced so that the peak memory consumption during
sequential s pefIn is as low as that during multiple-CPU spefIn .
19
Timing
Reporting Enhancements
Added New Global Variable to Track Reported Paths Limit
Impact on Other Commands, Parameters, and Globals: This variable is supported in clock
group-based non-statistical reporting flows only. The clock group-based reporting mode can be
enabled by setting timing_path_groups_for_clocks variable to true.
Data Path:
aocv_stage_count_data_early: Returns AOCV stage count values for a timing arc
on an early data path.
aocv_stage_count_date_late: Returns AOCV stage count values for a timing arc
on a late data path.
You can specify report_timing -format stage_count option to view “Aocv Stage Count”
column in the report output.
Impact on Other Commands, Parameters, and Globals: This enhancement impacts the following
property query commands:
get_property [get_arcs –from * -to *] propertyName
list_property –type timing_arc
report_property [get_arcs –from * -to *]
To enable this feature, you can set the timing_report_enable_markers global variable to true. By
default, this global is set to false.
The report contains details of all the cells and the worst derating applied on each cell for all the
reported paths. This command is supported in AOCV mode only.
Impact on Other Commands, Parameters, and Globals: Using this command might result in
increased runtime.
A cell with no timing arc data in a library that has any sensitivity information with respect to any
parameter defined in SPDF are considered as a corner object. All cells that do not qualify this
are considered to be statistical objects.
A net with parasitic data that has no sensitivity information with respect to any parameter
defined in SPDF is considered as a corner object. All nets that do not qualify this are
considered to be statistical objects.
-statistical: Applies derating on cells or nets that are modeled as statistical data
elements. The specified derating factor is applied to both the mean and sigma of delays.
For example,
The software uses this property during analysis for computing the stage count.
To display AOCV weight values in the timing report, you can specify report_timing –
format aocv_weight option. This enables reporting of column named “Aocv Weight” in
the timing report, which shows the respective AOCV weights on path elements.You can
also use the get_property command to return AOCV weight values.
For example, if a generated clock apll1/CLKI is created on pin apll1/CLKI, then the
following command will only display the valid paths:
Timing Modeling
Ability to Perform AOCV-Based ETM Extraction
The following global variable has been added to allow specification of AOCV derating mode:
timing_extract_model_aocv_mode
Other Enhancements
Ability to Perform AOCV Analysis on Data Paths
The timing_aocv_analysis_mode global variable has been enhanced to support the
capability of counting the number of stages of launch/capture clock and data paths separately in
the AOCV flow. The following new option has been added to support this feature:
separate_data_clock: Calculates the AOCV stage count for clock paths and data
paths separately. Both clock and data paths have related AOCV derating factors.
When set to false, the software uses the branch point closest to the register clock pins where
the clocks reconverge. When set to true, the software uses the farthest branch point from the
register clock pins (that is, the branch point closest to the clock root pin where the clocks diverge).
By default, this global is set to false.
20
Timing Debug
New Options for load_timing_debug_report
The command load_timing_debug_report has the following new options:
-additonal_slack_past_wns: Reports all the paths with slack worse than WNS and
the additional specified slack value.
-num_path: Specifies the number of paths to be reported in the detailed path violations.
-proto: Creates flex model categories and displays the top path of the top 8 (by default)
categories. This option can be used for design that has flexModels.
21
Verification
Release 12.0 Enhancements
New Command To Support 20nm and Lower DRC Rules
Verify Geometry Enhancements
Option -minPinArea Now Obsolete
Option -warning Now Obsolete
Violation Browser Enhancements
Auto Zoom Enhanced To Display Only Active Layers for Violations
Option Added for Limiting Number of Errors Displayed Per Type
Support Added for Complex Logical Expressions for Filtering Violations
New Forms Added for Loading and Saving DRC Markers
Impact on Other Commands, Parameters, and Globals: If you use verifyGeometry for a
20nm design, EDI System displays the following warning:
The verifyGeometry command does not support 20nm and below advanced rules. Use verify_drc instead.
layers related to the selected violation marker. The active layers for a violation includes the layer
on which the violation occurs and the adjacent layers. This enhancment makes it easier for you to
review a violation.
You can also specify the maximum number for each error type from the GUI by using the Error
Per Type option in the Violation Browser Settings form.
Here:
! refers to the NOT condition.
x specifies the AND condition.
+ specifies the OR condition.
Click Save to save the DRC file. This opens a form that allows you to specify the path and name
for saving the DRC file. This is equivalent to using the saveDRC command.
Click Load to load an existing database DRC file. This opens a form in which you can browse and
select the DRC file to be loaded. This is equivalent to using the loadDrc -incremental
command.
22
Power Calculation
Release 12.0 Enhancements
read_activity_file Parameters Consolidated
Multi-Threading Support for Dynamic Vector-Based Power Analysis Flow
Power Analysis Reporting Enhanced
Clock-Gating Efficiency Reports Improved
Variation in Switching Power Numbers when Running Power Analysis from EDI
The enhanced read_activity_file command provides the needed functionality for the
obsolete parameters. The obsolete parameters still work in this release but a warning message
will be displayed stating that these parameters will not be supported in a future release.
The Power Analysis engine has been enhanced to support multi-threading in the dynamic vector-
based flow. In the multi-threading mode, a job is divided into several threads, and multiple
processors in a single machine process them concurrently. The multi-threaded processing mode
can be specified using the following existing commands:
set_distribute_host –local
set_multi_cpu_usage -localCpu 4
These commands are used to control the number of CPUs to be used on a local machine for
multi-threading. Multi-threading provides better runtime for both the VCD/FSDB based dynamic
vector-based flows as compared to previous releases.
The enhanced log files contain detailed analysis information that can be used for debugging
purpose.
Clock-gating Efficiency Report - for each clock domain, it includes the toggle rate,
number of registers, number of clock gates, average clock toggle at registers, average
toggle savings at registers, and average toggle savings histogram.
Hierarchical View of Average Toggle Savings - number of clock gates and average
toggle savings for each hierarchical module in the design
23
Rail Analysis
Release 12.0 Enhancements
Simplification of Auto-Fetch DC Sources Commands
Body Bias Analysis Supported
On-Chip Voltage Regulator Analysis Supported
Support for Region-Based Snapping
Edit Pad Location Form Enhanced
view_esd_violation Enhanced to View Bumps Within a Resistor Range
Ability to Control Layer Processing
Rail Analysis Reporting Improved
Support for Non Zero Capacitance Filler Cells for Decap Optimization Flow
Sub_Via Support Added
Change in Extraction Results for Designs with Dangling Resistors
Block Level DEF Pin Checking Capability Enhanced
Via Clustering Enhanced
New Parameters to Ignore Filler and Decap Cells
The following table lists the obsolete commands, and the new command parameters that replace
the obsolete commands:
auto_fetch
display_pad_loc and Use the following command to fetch, save, and display the
load_pad_location voltage sources:
create_power_pads -net net_name –auto_fetch -
vsrc_file filename -display
Use the following command to display voltage sources on
GUI by loading a saved voltage source file:
create_power_pads -vsrc_file filename -
display
As part of this enhancement, the following changes have been made to auto-fetch DC sources'
behavior:
Automatically fetch voltage sources on all layer shapes. Previously,
the auto_fetch_dc_sources command would only fetch the voltage sources on the
top connected metal layer.
Fetch multiple voltage sources for large shapes based on multiple connections. Previously,
the auto_fetch_dc_sources command would only fetch one voltage source for large
shapes with multiple connections.
body bias pin definitions in liberty, the power and ground pins with type PWELL and NWELL
will be regarded as body bias pins. You can use the new parameter –bulk_pins of the
set_power_analysis_mode command when library cells have bulk pins defined in
LEF but the liberty file does not contain power associated with these pins. If a liberty file
does not have body bias definition, power analysis does not distribute power to the body
bias domain.
Rail Analysis - the -process_bulk_pins_for_body_bias parameter has been
added to the set_rail_analysis_mode command. When set to true, rail analysis
will process current sinks on the cell's bulk pin connections. This parameter is used during
body bias analysis, where a body bias net is connected to bulk pins of the cell.
The bulk pins for a cell is defined in the cell library using the
set_power_library_mode -generic_bulk_power_names -
generic_bulk_ground_names command parameter. If bulk pins are
defined using set_power_library_mode -generic_power_names
-generic_ground_names, then the -
process_bulk_pins_for_body_bias parameter must not be used.
For more information, refer to the "Body Bias Analysis" chapter in the Encounter Power
System User Guide.
During Vreg analysis, the tool captures the noise at the output of Vreg caused due to loading
current and RC effects, and uses this voltage waveform for rail analysis. In the following diagram,
the chip configuration has a Vreg that is connected to an input and output domain along with a
common ground. When you perform Vreg analysis, a reduced grid is created for both input and
output, and reduced ground resulting in a much concise RC netlist to do simulations of vectors
with these loadings. The noise at the output of Vreg is captured and used for rail analysis.
Range
Previously, the view_esd_violation command reported only those bumps with effective
resistance greater than the specified threshold value. Now, you can use the new -limit
parameter to report bumps that have a resistor value in the specified range, that is, between
value1 and value2. The -limit parameter must be used in conjunction with the -threshold
parameter. The -threshold parameter specifies value1 or the lower limit of the resistance
value, and the -limit parameter specifies value2 or the upper limit of the resistance value.
Resistance values must be specified in Ohm.
GUI Enhancement
The Process column has been added to the Power & Rail Results - Advanced form to control the
processing of individual layers interactively.
Previously, the following reports were generated by Rail Analysis for each net inside the state
directory (../state_dir/Reports):
net_name.disconnected_inst.asc
net_name .disconnected_pgv.asc
net_name .missing_pgv.asc
net_name .pwr_annotation.asc
net_name .reff_infiniti.asc
net_name .unconnected_sections.asc
With the current implementation, these fragmented reports have been consolidated to generate
the net_name.pg_integrity.asc and .html files for each net in the state directory
(../state_dir/<net>/Reports). The consolidated report will now also have information on
weakly connected power segments, for example, stripes not connected to top level layer.
In addition, the following parameter has been introduced to support layer-based custom via
clustering:
set_rail_analysis_mode –cluster_via_rule { {via_layer
number_of_equidistant_vias}… } - Controls the number of vias to cluster on a
layer basis. The VIA clustering rule specified using this parameter will override the default
clustering rule for a given accuracy mode.
The following command will cluster 100 equidistant VIA1 cuts, 200 equidistant VIA2 cuts, and 300
equidistant VIA7 cuts:
set_rail_analysis_mode –cluster_via_rule { {VIA1 100}} {VIA2
200} {VIA7 300}}
The rest of the VIAs will be clustered using the default clustering rule depending upon the rail
analysis accuracy mode.
–ignore_decaps {true | false} - Ignores decap cells during static analysis. It ignores
cells that are tagged as DECAP cells during library characterization or set as decap cells
using the set_rail_analysis_mode –decap_cell_list command parameter.
Ignoring decaps during dynamic analysis is not recommended.
Default: false
24
Early Rail Analysis
Release 12.0 Enhancements
New Parameter to Support Fast Mode Extraction
Power Gate Analysis Behavior Enhanced
25
Mixed Signal Interoperability
Release 12.0 Enhancements
run_vsr GUI Updated
setIntegRouteConstraint Command Enhanced
Integration Constraints Editor GUI Updated
Floating Shields Supported
[-help]
-rule <non-default-rule-name>
[-shieldNet name |
[-shieldType shieldType]
[-tolerance tolerance]
[-matchStyle style]
[-topLayer layerNumber]
[-bottomLayer layerNumber]
[-connectSupply value}]
[-layerMatch layerMatch]
Using the new Pull Block Constraint tab, you can pull the routing constraints stored on the
interface nets of blocks in a design, to their corresponding top-level nets.
26
Clock Concurrent Optimization
Release 12.0 Enhancements
setCCOptMode Command Enhanced to Set the Minimum Fanout Number for Top
Nets
All nets in a clock tree can be classified as "leaf" nets, "trunk" nets, or "top" nets. Leaf nets connect
directly to sinks. Top nets are nets that have a transitive fanout higher than the configured
threshold, and trunk nets are those nets that are not directly connected to sinks. Depending on the
total number of fanouts in a tree, you may not have any top nets at all – just leaf and trunk nets.
Top nets, trunk nets, and leaf nets can all use different routing rules. So if a net is determined to be
a top net because its transitive fanout is greater than the threshold set by the
top_net_min_fanout parameter then it will use the top net routing rules. If it is leaf net or a
trunk net then it will use leaf routing rules or trunk routing rules.
Changing the value of this parameter will change the nets that are considered as top nets.
27
Clock Tree Synthesis
Release 12.0 Enhancements
AssumeShielding Option in the Clock Specification File is Obsolete
clockDesign Parameters not Supported with CCOpt Engine
reportClockTree Command Enhanced to Write Out Information for Cell Types
When setCTSMode -engine is set to -ccopt, the EDI clock specification file is automatically
mapped to the Azuro clock specification. However, when you use the CCOpt engine, many
parameters of the clockDesign command are not supported. These parameters are only
supported when the engine specified is ck. You can use other EDI commands and options
instead.
For details of commands and parameters that can be used instead of the clockDesign
parameters that are not supported with the CCOpt engine, refer to the clockDesign command
28
OpenAccess
Release 12.0 Enhancements
New Command to Access the 5.x Library Structure
New Parameter to Add Voltage Information to the Nets
29
TSV
Release 12.0 Enhancements
Embedded Bump Flow Supported in Hierarchical Designs
New Parameter Added to Output Selected Bumps
The block-level LEF file with the embedded bump information is passed to the top-level design,
and the embedded bumps are treated as normal bumps in the top-level design. The embedded
bump information can also be exchanged between adjacent dies. As a result, a chip of the current
design could create and assign bumps according to embedded bumps in the adjacent die.
All the 3D IC commands have been enhanced to support embedded bumps, therefore, the output
files generated by these commands for the downstream tools also support embedded bumps.
30
Timing Optimization
Release 12.0 Enhancements
New Command Introduced
timeDesign Command Updated
reclaimArea Command Updated
setOptMode Command Updated
New Parameters Added
GigaOpt as the Default Optimization Engine
Obsolete Parameters
-timeDesignNumPaths number
Allows you to select the number of paths that should be reported per path group during
timeDesign or optDesign final summary reports.
Default : 50
-timeDesignExpandedView {true | false}
When set to true, it will force timeDesign or optDesign to print summary timing reports
as per the view in the log file.
Default : false
When set to true, this will force timeDesign or optDesign to print timing reports with the
net section.
Default : false
Using this engine, you need not run optDesign –si but rest of the use model is unchanged. The
reason for this is that GigaOpt post-route optimization will by default fix both the base timing and SI
timing at the same time.
Obsolete Parameters
In this release, the following parameters of setOptMode command are obsolete.
-congOpt {true | false}
-considerNonActivePathGroup {true | false}
-critPathCellYield {true | false}
-postRouteAllowOverlap {true | false}
-yieldEffort {none | low | high}
31
Placement
Release 12 Enhancements
New Commands
New Options for setPlaceMode
New Option for addFillerGap
Release 12 Enhancements
New Commands
The new commands added to EDI System are:
place_connected: Places the specified standard cells close to the specified attractor with
legal location. The attractor can be IOs or hard macros. The recommended flow is to run
this command before placeDesign.
The command setprerouteAsObs has been replaced with the option -prerouteAsObs.
The option's function remains the same, it returns the routing layers.
32
Yield Analysis
Release 12.0 Enhancements
Yield Analysis Discontinued
The associated GUI forms and documentation have also been discontinued from this release.
33
Delay Calculation
Release 12.0 Enhancements
Vectorized Delay Calculation Support in MMMC with AAE
When none is specified, the software does not combine any delay calculation runs. When
early_late is selected, the software combines early and late simulations of a single corner into
one delay calculation simulation.
34
Netlist-to-Netlist
Release 12.0 Enhancements
runN2NOpt -optimizeYield Parameter Now Obsolete
35
Prototyping Foundation Flow
Release 12.0 Enhancements
New Command to Control Initial Floorplan
New Command to Generate Floorplan for Prototyping
set_proto_mode Command Updated
set_proto_model Command Updated
load_timing_debug_report Command Updated
It is a super command and internally calls planDesign, placeDesign, and timeDesign -proto
commands.
Specifies an estimate of the average percentage of routing tracks which would be used by
the standard cells represented by flexFillers.
-create_characterize_percent_rt_blockage
Specifies the percentage of models being generated that will be used for characterizing the
default percentage of routing tracks that will be used by the standard cells represented by
flexFiller cells.
-identify_partition_min_inst and -identify_partition_max_inst
Specifies the minimum and maximum instance count per partition that will be used by
identify_flexmodel to identify flexModels.
Specifies an estimate of the percentage of routing tracks which would be used by the
standard cells represented by flexFillers of a specific flexModel.
-create_gate_area
Specifies total area of standard cell gates. This value does not include macro area.
-create_gate_count
Specifies number of gates per area. This value will be multiplied with the value of -
create_gate_area to come up the total area of standard cells for a specific module.
36
Signal Integrity Analysis
setSIMode Command Enhanced
In this release, following new parameters have been added to the setSIMode command:
-accumulated_small_attacker_mode {cap | current}
-accumulated_small_attacker_threshold value
-individual_attacker_threshold <value>
-switch_prob value
-receiver_peak_limit value
-input_glitch_thresh value