Academic Contest Buzzer

Part 2

The Clock

Materials needed: 2 10,000 ohm resistors

1 24,900 ohm resistor
1 1N4001 diode or equivalent
1 VN10LP FET or equivalent
1 CD4001 quad dual-input NOR gate
2 CD4029 presettable binary/decimal up/down counters
1 24 VAC center tapped transformer

The contest buzzer has to accurately time three intervals – 5, 10 and 15

seconds. Rather than try to tweak a 555 astable oscillator, or count down a high
frequency oscillator, I wanted to use the AC line. The frequency is held to 60 Hz
very tightly – something like 1 PPM. Therefore, it is a stable and convenient time
base. All you have to do is divide the line frequency by 60 and you have an
accurate 1-second timing signal.

R1 and 2 make a voltage divider between one leg of the transformer

secondary and its center tap. The 1N4001 half-wave rectifies the AC so the gate
of the 2N7000 FET sees a 60 HZ positive-going pulse. The FET “squares up” the
half-cycle sine wave for better triggering of the CMOS logic. R3 limits current to a
level acceptable by CMOS logic.
The 60 Hz signal would pass through the 4001 gate U1C and clock the
first 4029, but is blocked by the RUN-not being high. The NOR gate’s output will
stay low as long as RUN-not is high. In this static condition, the high on the RUN-
not also forces U1B low, and therefore U1A high. Pin 1 of the 4029’s is the
parallel enable, which forces the internal logic to load “0” in U2 and “6” in U3.
Thus, the counters are preset to count 60 pulses as soon as RUN-not goes low.
The RUN-not signal originates on the control logic board, which will be
covered next. When the operator has set the desired number of seconds into the
counter and presses the Start button, RUN-not goes low.
When RUN-not falls low, U1C can pass the 60 Hz pulses to the first
counter, U2. The various pins held low put the counter in decimal mode and force
it to count down. Every ten pulses will generate a CARRY OUT-not on pin 7,
which clocks the following counter U3.
The differences between U2 and 3 are in the two pins on U3 held high so
the counter is loaded to a state of “6” when pin 1 goes high. For a system
operating in a country using 50 Hz power, grounding pin 12 and tying pin 4 high
will cause the parallel load to be “5” rather than “6”.
When both counters generate a CARRY OUT-not after 60 pulses have
been counted, U1D goes high. This counts the logic down on the control board,
and also causes a parallel load of both counters, enabling them to run for another
period of 60 pulses. This will repeat until the RUN-not signal goes high. The next
lesson will show some of the control logic and the counters fed by the 1 Hz clock
pulses.