1

Outline
  Common Control Methods
 Why control?
 Control objectives
 Factors affecting control performances
 Common control techniques
  Design of Closed-Loop DC/DC Converters
  Controller design
  Regulator design
  Compensator design
  Other Control Methods

2
 Why Control?

A controller is to manage the power transfer process between the

source and load with the objectives of:
1.  Obtaining effective power conversion.
2.  Counteracting any deviations from nominal behavior.

3
 Control Objectives
To ensure the converters operates with:
1.  Small steady-state output error,
2.  Fast dynamical response,
3.  Low overshoot, and
4.  Low noise susceptibility
while maintaining high efficiency and low noise emission.

4
 Factors affecting Control Performances
  Switching frequency
The performance of a converter can always be improved with a
higher switching frequency. However, it is restricted by switching
losses, eddy current and hysteresis losses in magnetic components,
and ac power loss due to skin effect.
  Energy storage elements
The size of energy storage elements affects their ability to respond
to the load changes.
  Control gains
The choice of gain parameters determines the response of the
system.

5
 Common Control Techniques
  Hysteretic controllers
  The most commonly used control technique prior to the
introduction of fixed-frequency pulse-width modulation
(PWM) integrated-circuit (IC) controllers.
  Pulse-width modulation controllers
  The most popular control technique because of (1) the available
of low-cost highly sophisticated fixed-frequency PWM ICs in
the markets and (2) the growing need of minimizing the
spurious emissions in noise-sensitive applications.

6
 Hysteretic Controllers

  Two types: hysteretic voltage controller and hysteretic current controller

  They are simple to implement and can respond rapidly for sudden load changes.
  The frequency of operation is affected by the circuit parameters vi, rL, L, and C.
  The turn-on and turn-off of the relay are not fixed, hence can produce
unpredictable noise spectrum.
7
 Hysteretic Voltage-Mode Controllers

 A hysteretic relay compares the

actual output voltage with the
desired output voltage.
 This solution is effective for
buck-type converters only,
i.e., no phase lag between the
control action and the response
of the inductor current.

8
 Hysteretic Current-Mode Controllers

 The inductor current is

compared with the compensated
voltage error.
 A very tight regulation of the
inductor current, and hence the
output voltage, is possible.
 This solution is effective for
converters with RHPZ.

9
 Pulse-width Modulation Controllers
  Two types: voltage-mode control and current-mode control
  The most popular control technique because of
 The available of low cost sophisticated fixed-frequency PWM
Ics in the markets.
 Low noise emissions.

10
 PWM Voltage-Mode Control
 The output voltage is regulated by
closing a feedback loop between
the output voltage and the duty-
ratio signal.
 An input voltage feed-forward
scheme can be used to increase
the immunity of the output
voltage against any input voltage
variations by making the peak of
the ramp signal proportional to
the input voltage.

11
 PWM Current-Mode Control
1. The control uses an inner current loop to control the
inductor or switch current and an outer loop to control the
output voltage.
2. A nonlinear term is added into the system equations.
3. The control is mainly applied to boost and buck-boost types
converters which suffer an undesirable non-minimum phase
response.
4. The main advantage is its ability to increase the overall
system’s stability margin, and hence simplify the design of the
outer voltage feedback loop.

12
 PWM Peak Current-Mode Control
 The switch turns on periodically
as commanded by a fixed-
frequency clock signal.
 The peak inductor current is
forced to follow a reference signal
that is derived from the output
voltage.
 The switch turns off when the
peak of the instantaneous current
reaches the desired reference
Disadvantages: level.
1. Extremely susceptible to noise
2. Sub-harmonic oscillations for duty-cycle exceeding 0.5
3. Non-ideal loop response
13
 PWM Average Current-Mode Control
 The Zf1compensated output voltage
feedback compares with the inductor
to generate the current error.
 The PWM compares the Zf2
compensated current error to an
externally generated ramp to give the
desired control signal.

Disadvantage:
The analysis and optimal design of the two compensation
networks are non-trivial.
14
 Controller Design
There are two important characteristics in controllers:
1.  Capable of rejecting disturbances and variations.
2.  Stable in all operating conditions.

15
 Dependence of v on vg, d, and iload

Sources of disturbances and variations:

1. Input voltage variations due to, such as,
second harmonic of ac power system
produced by a rectifier circuit and
switching on and off of neighboring
power system loads.
2. The load current containing variations
of significant amplitude.
3. The component tolerances.

The use of negative feedback

16
 Functional Block
The idea behind the use of negative
feedback is to build a circuit that
automatically adjusts the duty cycle
as necessary, to obtain the desired
output voltage with high accuracy,
regardless of disturbances or
variations in component values.

17
 Network Transfer Functions

vˆ (s) = Gv d (s) dˆ (s) + Gv g (s)vˆ g (s) − Z out (s)iˆload (s)

where
vˆ (s)
Gv d (s) = converter control - to - output transfer function
dˆ (s) vˆg = 0,iˆload = 0

vˆ (s)
Gv g (s) = converter line - to - output transfer function
vˆ g (s)
dˆ = 0, iˆload = 0

vˆ (s)
Z out (s) = − converter output impedance
iˆload (s) dˆ = 0,vˆ
g=0
18
 Small-Signal Equations
Pertrubed and linearized :
v ref (t) = Vref + vˆ ref (t)
v e (t) = Ve + vˆ e (t)


Gc Gv d /VM Gv g Z out
vˆ = vˆ ref + vˆ g − iˆload
1+ HGc Gv d /VM 1+ HGc Gv d /VM 1+ HGc Gv d /VM
1 T Gv g Z
⇒ vˆ = vˆ ref + vˆ g − iˆload out
H 1+ T 1+ T 1+ T
where
T(s) = HGc Gv d /VM loop gain
This equation shows how the addition of a feedback loop modifies the
transfer functions and performance of the system.
19
 Reduction of Disturbances by Feedback
vˆ (s) Gv g (s)
=
vˆ g (s) vˆref = 0, iˆload = 0
1+ T(s)
1
The open - loop transfer function is reduced via feedback by .
1+ T(s)

vˆ (s) Z out (s)

=
−iˆload (s) vˆ 1+ T(s)
g = 0, vˆ ref =0

1
The output impedance is reduced by and the influence of load current
1+ T(s)
variations on the output voltage is reduced.

20
 Reduction of Gain Sensitivity
vˆ (s) 1 T(s)
=
vˆ ref (s) H(s) 1+ T(s)
vˆg = 0, iˆload = 0

vˆ (s) 1
⇒ ≈ which is independent of Gc (s),VM , and Gvd (s).
vˆ ref (s) vˆg = 0, iˆload = 0
H(s)
Generally, in the dc regulator applications, vˆ ref is constant and v ref = 0.

V 1 T (0) 1
= ≈ if the system is linear
Vref H (0) 1 + T (0) H (0)
The dc output voltage can accurately follow the dc reference if the dc sensor gain
and dc reference are accurate and well - known.

21
 Loop Gain
⎛ s ⎞
⎜1 + ⎟
⎝ ωz ⎠
T (s) = T0
⎡ s ⎛ s ⎞
2
⎤⎛ s ⎞
⎢1 + +⎜ ⎟ ⎜ ⎥ 1 + ⎟
⎢ Qω p1 ⎝ ω p1 ⎠ ⎥⎝ ω p2 ⎠
⎣ ⎦

⎧ =1 at f c
⎪ ⎧⎪ 1
⎪⎪ > 1 for f < f c T for T >> 1
⇒ ≈⎨
T ⎨>> 1 for f << f c 1 + T ⎪T for T << 1
⎪ < 1 for f > f ⎩
⎪ c

⎪⎩<< 1 for f >> f c

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 Construction of T/(1+T)
T ⎧⎪ 1 for T >> 1
≈⎨
1 + T ⎪T for T << 1
⎩

At low frequency
vˆ (s) 1 T(s) 1
= ≈
vˆ ref (s) H(s) 1+ T(s) H(s)

At high frequency
vˆ (s) 1 T(s) T(s) Gc (s)Gvd (s)
= ≈ =
vˆ ref (s) H(s) 1+ T(s) H(s) VM

  Athigh frequencies, the feedback loop is unable to reject disturbances because

the bandwidth of T is limited.
  The reference-to-output transfer function can be constructed by multiplying

23
the asymptotes by 1/H.
 Construction of 1/(1+T)
⎧1
1 ⎪ T (s) for T >> 1
≈⎨
1+ T ⎪ 1 for T << 1
⎩
At low frequency
vˆ (s) G (s) Gvg (s)
= vg ≈
vˆ g (s) 1+ T(s) T(s)
e.g. A loop gain of 20 (26dB) at 100 Hz can reduce
the transfer function by a factor of 20 at 100 Hz.

At low frequency
At high frequency ( f > f c ) vˆ (s) Z (s) Z out (s)
= out ≈
vˆ (s) G (s) −iˆload (s) 1+ T(s) T(s)
= vg ≈ Gvg (s)
vˆ g (s) 1+ T(s)
vˆ (s) Z (s)
= out ≈ Z out (s)
−iˆload (s) 1+ T(s)
The feedback loop has essentially no effect on the disturbance transfer functions at
frequencies above the crossover frequency.
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 Stability
N (s)
T (s) D(s) N (s)
= =
1 + T (s) N (s) N (s) + D(s)
1+
D(s)
1 1 D(s)
= =
1 + T (s) N (s) N (s) + D(s)
1+
D(s)

Stability can be tested by:

1. Evaluate N(s)+D(s) and factor the result to see whether any of
the roots have positive real parts.
2. Determine the number of right half-plane of N(s)+D(s).
(Nyquist theorem)
3. Perform the phase margin test.

25
 The Phase Margin Test
T ( j2πf c ) = 1 = 0 dB When ϕ m > 0, T (s) contains no RHP poles ⇒
ϕ m = 180 0 + ∠T ( j2πf c ) 1 1 + T and T 1 + T contain no RHP poles.

Stable system Unstable system

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 Phase Margin and Damping Factor
1
T (s) =
⎛ s ⎞⎛ s⎞
⎜ ⎟⎜ 1 + ⎟
⎝ ω 0 ⎠ ⎝ ω2 ⎠
f2 → ∞ ⇒ ϕ m → 90 0
f2 → 0 ⇒ ϕ m → 0 0
i.e. as f 2 is reduced, the phase
margin is also reduced.

T (s) 1 ωo ωo
= where ω c = ω oω2 = 2πf c and Q = =
1 + T (s) s ⎛ s⎞
2
ωc ω2
1+ +⎜ ⎟
Qω c ⎝ ω c ⎠

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Closed-loop Transfer Function (Low-Q Case)

Qω c = ω 0
ωc
= ω2
Q

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 Closed-loop Transfer Function (High-Q Case)

T f
The exact value of at frequency f c is equal to Q = 0 .
1+ T fc

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 Relationship between ϕm and Q

cosϕ m
Q=
sin ϕ m

−1 1 + 1 + 4Q 4
ϕ m = tan
2Q 4

This result gives good approximation for the cases:

1.  T approaches unity gain with a -20 dB/decade slope with an additional pole at f2.
2.  T approaches unity gain with a -40 dB/decade slope with an additional zero at f2.

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 Transient Response

T (s) 1 1 1
Unit - step response = =
1 + T (s) s s ⎛ s⎞ s
2

1+ +⎜ ⎟
Qω c ⎝ ω c ⎠

⇒ v(t ) = 1 +
2Qe −ω c t / 2Q
4Q2 − 1
sin
4Q2 − 1
2Q
ω ct + tan −1 ( )
4Q2 − 1 for Q > 0.5

ω2 ω1
⇒ v(t ) = 1− e −ω1 t − e −ω2 t for Q < 0.5
ω2 − ω1 ω1 − ω2
with Overdamped : when f2 > 4 f 0 , Q < 0.5
ω1,ω2 =
ωc
2Q
(1 ± 1− 4Q2 ) Critically damped : when f 2 = 4 f 0 , Q = 0.5
Underdamped : when f2 < 4 f 0 , Q > 0.

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 Typical dc regulator design specifications (1)
1. Effect of load current variations on the output voltage
regulation
If, over some frequency range, the open-loop output impedance has
magnitude that exceeds the limit, then the loop gain T must be
sufficiently large in magnitude over the same frequency range, such
that the magnitude of the closed-loop output impedance is less than
the given limit.

vˆ (s) Z out (s)

=
−iˆload (s) vˆ 1+ T(s)
g = 0, vˆ ref =0

32
 Typical dc regulator design specifications (2)
2. Effect of input voltage variations on the output voltage
regulation.
  Specific maximum limits are usually placed on the amplitude of
variations in the output voltage. If we know the magnitude of
voltage ripple which appears at the converter input, then we can
calculate the resulting output voltage ripple.
  The output voltage ripple can be reduced by increasing the
magnitude of the loop gain at the ripple frequency.

vˆ (s) Gv g (s)
=
vˆ g (s) vˆ 1+ T(s)
ref = 0, iˆload = 0

33
 Typical dc regulator design specifications (3)
3. Transient response time
  When a specified large disturbance occurs, such as a large step
change in load current or input voltage, the output voltage may
undergo a transient.
  During this transient, the output voltage typically deviates from its
specified allowable range. Eventually, the feedback loop operates to
return the output voltage within tolerance. The time required to do
so is the transient response time; typically, the response time can be
shortened by increasing the feedback loop crossover frequency.

34
 Typical dc regulator design specifications (4)
4. Overshoot and ringing.
The amount of overshoot and ringing allowed in the transient
response may be limited. Such a specification implies that the
phase margin must be sufficiently large.

Each of these requirements imposes constraints on the

loop gain T(s). Therefore, the design of the control
system involves modifying the loop gain.

35
 Compensator Design

The idea of compensation is

to modify the magnitude
and phase of a loop gain to
meet the design
specifications and give
stable operation.

36
Objective loop-gain and Required compensation

37
 Lead (PD) Compensator
  The lead compensator is also called a proportional-plus-
derivative controller.
  It is used to improve the phase margin by adding a zero is
into the loop gain, at a frequency fz far below the crossover
frequency fc.
  At high frequencies, the zero causes the compensator to
differentiate the error signal.
  It finds application in system containing a two-pole response.

38
 Magnitude and phase of a simplified PD compensator
⎛ s ⎞
⎜ 1 + ⎟
⎝ ωz ⎠
Gc (s) = Gc0
⎛ s ⎞
⎜1 + ω ⎟
⎝ p⎠

The compensator network should contain poles at a frequency less

than the switching frequency to attenuate the switching harmonics
and to ensure the loop gain equal to unity at the desired crossover
frequency.

39
 Compensation with a PD compensator
⎛ s ⎞
⎜1 + ⎟
⎝ ωz ⎠
Gc (s) = Gc0
⎛ s ⎞
1 +
⎜ ω ⎟
⎝ p⎠

fϕ max = f z f p = fc
⎛ fp fz ⎞
⎜ − ⎟
−1⎜
fz fp ⎟
∠Gc ( f ϕ max ) = tan
⎜ 2 ⎟
⎜⎜ ⎟⎟
⎝ ⎠

f p 1 + sin θ
= where θ = −Gc ( f ϕ max ) − a compensator phase lead at f c
f z 1− sin θ
1− sin θ 1 + sin θ
⇒ f z = fc and f p = f c
1 + sin θ 1− sin θ
fz
Gc0 = < 1 for T = 1 at f c
fp
Other choice of Gc0 can be selected when it is desired to shift the crossover frequency f c .
40
 Network with zero-pole pairs
( R3C2s + 1)( R1C1s + 1)
H=
( R1C2s)( R2C1s + 1)
Vref ( R1 + R2 )
Rbias =
Vin − Vref

41
 Lag (PI) Compensator
  The lag compensator is also called a proportional-plus-
integral controller.
  It is used to improve the low frequency loop gain by adding
an inverted zero into the loop gain, at a frequency fL
sufficiently lower than the crossover frequency fc.
  At low frequencies, the inverted zero causes the compensator
to integrate the error signal.
  It is a simple and effective approach for systems containing a
single pole.

42
 Magnitude and phase of a simple PI compensator

⎛ ωL ⎞
Gc (s) = Gc∞ ⎜1 + ⎟
⎝ s ⎠

The compensator high frequency gain Gc∞ is chosen to

obtain the desired crossover frequency fc.

43
 Compensation with a PI compensator
⎛ ω ⎞
Gc (s) = Gc∞ ⎜1 + L ⎟
⎝ s ⎠
Tu0
Tu (s) =
⎛ s⎞
⎜1 + ⎟
⎝ ω0 ⎠
T (s) = Tu (s)Gc (s)

TuoGc∞
T ≈ at high frequencies
⎛ f⎞
⎜ ⎟
⎝ f0⎠
⇒ f c ≈ TuoGc∞ f 0 at f = f c with T = 1
fc
Gc∞ = at f c
Tuo f 0
The corner frequency f L is then chosen to be sufficiently less then f c to maintain
44 an adequate phase margin.
 Zero-pole pair network

R2
Gain between f1 and f2 = AV =
R1
1 C1 + C2 1
f1 = f2 = ≈
2πR2C1 2πR2C1C2 2πR2C2

45
 Combined (PID) Compensator
  The compensator combines the advantages of the lead and lag
compensators to obtain both wide bandwidth and zero
steady-state error.
  At low frequencies, it integrates the error signal, leading to
low-frequency loop gain and accurate regulation of the
output voltage.
  At high frequencies, it introduces phase lead in the loop gain,
improving the phase margin.

46
 Magnitude and phase of a PID compensator

⎛ ωL ⎞ ⎛ s ⎞
⎜1 + ⎟ ⎜1 + ⎟
⎝ s ⎠⎝ ωz ⎠
Gc (s) = Gcm
⎛ s ⎞⎛ s ⎞
⎜1 + ω ⎟ ⎜1 + ω ⎟
⎝ p1 ⎠ ⎝ p2 ⎠

The loop gain crossover frequency fc is chosen to be greater

than fL and fz but less than fp1 and fp2.

47
 Two Zero-Pole Pairs Network

R2
Gain between f1 and f2 = AV1 =
R1
R2 ( R1 + R3 ) R2
Gain between f3 and f 4 = AV2 = ≈
R1R3 R3
1 1 1
f1 = f2 = ≈
2πR2C1 2π( R1 + R3 )C3 2πR1C3
1 C1 + C2 1
f3 = f4 = ≈
2πR3C3 2πR2C1C2 2πR2C2
48
 Design Example

Nominal Vg = 28 V
V = 15 V to a 5 A load
Vref = 5 V

49
 DC analysis
1. Selection of feedback gain H (s)
Vref 5 1
H= = =
V 15 3
2. Determination of duty cycle D
V 15
D= = = 0.536
Vg 28
3. Determination of quiescent control voltage Vc
Vc = DVm = 2.14 V

50
 AC analysis (1)
1. The open - loop control - to - output transfer function is
V 1
Gvd (s) =
D L
1+ s + s LC
R 2
and, in normalized form, is
1
Gvd (s) = Gd 0 2
s ⎛ s⎞
1+ +⎜ ⎟
Q0ω 0 ⎝ ω 0 ⎠
⇒
V
Gd 0 = = 28 V
D
ω 1
f0 = 0 = = 1 kHz
2π 2π LC
C
Q0 = R = 9.5 ⇒ 19.5 dB
L
51
 AC analysis (2)
2. The open - loop line - to - output transfer function is
1
Gvg (s) = D
L
1+ s + s2LC
R
and, in normalized form, is
1
Gvg (s) = Gv 0 2
⇒ Gv 0 = D = 0.536
s ⎛ s⎞
1+ +⎜ ⎟
Q0ω 0 ⎝ ω 0 ⎠

3. The open - loop output impedance is

1 sL
Zout (s) = R // // sL =
sC L
1 + s + s2LC
R

52
 AC analysis (3)
3. The loop gain of the system is
⎛ 1⎞
T (s) = Gc (s)⎜ ⎟ Gvd (s)H (s)
⎝ Vm ⎠

With Gvd (s) replaced by its normalized form

Gc (s)H (s) V 1
T (s) =
Vm D⎡ s ⎛ s⎞ ⎤
2

⎢1 + +⎜ ⎟ ⎥
⎢⎣ Q0ω 0 ⎝ ω 0 ⎠ ⎥⎦

53
 AC analysis (4)
The uncompensated loop gain, with unity compensator gain is
1
Tu (s) = Tu0 2
2 ⎛ s⎞
1+ +⎜ ⎟
Q0ω 0 ⎝ ω 0 ⎠
where the dc gain is
HV
Tu0 = = 2.33 ⇒ 7.4 dB
DVm
At f 0 ≈ 1.8 kHz, ϕ m < 50

54
 Compensator design (1)
1
Suppose f c = 5 kHz = f
20 s
2
⎛f ⎞
Tu ⎜ 0 ⎟ = 0.093 ⇒ −20.6 dB and a phase margin of nearly 1800
⎝ fc ⎠
To obtain unity gain at 5 kHz, the compensator should
have a 5 kHz gain of + 20.6 dB.
A lead compensator is chosen to design for a phase margin of 520.
This leads to
0
ϕ m = 520 ⇒ Q = 1 and a peak overshoot of 16%
1− sin 52
f z = (5 kHz ) = 1.7 kHz
1 + sin 520
1 + sin 520
f p = (5 kHz ) = 14.5 kHz
1− sin 520

55
 Compensator design (2)
To obtain a compensator gain of 20.6 dB (10.7) at 5 kHz,
the low - frequency compensator gain must be
2
⎛f ⎞ 1 fz
Gvo = ⎜ c ⎟ = 3.7 ⇒ 11.3 dB
⎝ f 0 ⎠ Tu0 fp

56
 Compensator design (3)
The loop gain is
⎛ s ⎞
⎜1 + ⎟
⎝ ωz ⎠
T (s) = Tu0Gc0
s ⎞⎛ ⎛ s⎞ ⎞
2
⎛ s
⎜1 + ω ⎟ ⎜1 + Q ω + ⎜⎝ ω ⎟⎠ ⎟
⎝ p⎠⎝ 0 0 0 ⎠

57
 Compensator design (4)
At f < 1 kHz, the feedback loop attenuates output
disturbances by 18.7 dB. For example,
Δvg = 1 V at 100 Hz
→ With no feedback, a 100 Hz variation of 0.536 V (D = 0.536)
will be observed at the output.
→ With feedback, the variation will be attenuated by 18.7 dB (8.6)
and the output variation is now 0.536/8.6 = 0.062 V.

58
 Other Control Methodologies
  Adaptive control
  Fuzzy logic control
  Artificial neural network control
  One-cycle control
  Sliding mode control

59
 Summary
1.  A controller is to provide an effective power transfer and
counteract any disturbance and variations.
2.  The most common control techniques are hysteretic
control and pulse-width modulation control.
3.  Negative feedback causes the system output to closely
follow the reference input. The influence on the output by
disturbances and variations is reduced.
4.  The stability can be assessed by the phase margin test.
5.  Three types of compensator can be used to shape the loop
gain to achieve desired performances.

60
 References
  S.C. Tan,Y.M. Lai, and C.K. Tse, Sliding Mode Control of Switching Power
Converters, CRC Press, 2011.
  R.W. Eriskson and D. Maksimovic, Fundamentals of Power Electronics, 2nd Ed.,
Kluwer Academic Publishers, 2001.
  M. Kazimierczuk, Pulse-width Modulated DC-DC Power Converters, Wiley, 2008.
  A.I. Pressman, Switching Power Supply Design, 2nd Ed., McGraw-Hill, 1999.
  D.M. Mitchell, DC-DC Switching Regulator Analysis, McGraw-Hill, 1988.
  Unitrode, Power Supply Design Seminar, 1986.

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