Analogue Electronics

ELEC 12154
 Course Content
Transistor Audio power amplifiers, Amplifiers with negative
feedback, Field effect transistors, CMOS devices, switching
circuits. Operational-amplifier characteristics. Typical
performance of selected op-amp types. Non-ideal behaviour,
saturation, frequency response, slew rate. Basic uses of op-
amp: integrator, differentiator, scalar changer, phase shifter,
filter, VC and CV converter, function generators and signal
conditioners. Other uses of op-amp: comparator, zero-crossing
detector, Clipping, clamping, waveform generators and wave-
shaping circuits, Precision rectifier, Schmitt triggers and
multivibrator. Electronic analogue computation: solution of
differential equation, time scaling and amplitude scaling of
differential equation, simulation of transfer function. Switching
and amplifying circuits. Regulators: basic series and shunt
regulators, series regulator with transistor feedback and with
op-amp, current limiting circuit, complete power supply.
Principle of power control. Power control systems: SCS alarm
circuit, SCR power control, triac light intensity control. 12 V
battery charger.
 Recommended Reading
1. Floyd, T. L. (2004). Electronic Devices, 6th Edition,
Prentice-Hall International.
2. Botkar, K. L. (1996). Integrated Circuits, Khanna
Publishers.
3. Millman, J. and Grabel, A. (1987). Microelectronics,
2nd Edition, McGraw-Hill Book Company.
4. Clayton, G. and Winder, S. (2003). Operational
Amplifiers, 5th Edition, Newnes Publications.
5. Horowitz, P. and Hill, W. (1997). The art of
electronics, 2nd Edition, Cambridge University Press.
 Field-Effect Transistors (FETs)

FETs are unipolar device because, they operate only with one type of
charge carrier (Unlike BJTs that use both electron and hole current).

BJTs – Current control device

FETs – Voltage control device

Two main types of FETs

1 Junction Field Effect Transistors (JFET)
2 Metal Oxide Semiconductor Field Effect Transistors (MOSFET)
Junction Field Effect Transistors (JFET)
n channel JFET p channel JFET
Drain Drain

n channel

p channel
Gate p p Gate n n
Basic Structure

Source Source

Drain (D) Drain (D)

Gate (G) Gate (G) Symbol

Source (S) Source (S)

 Basic operation
dc bias voltages applied to an n
RD channel JFET is shown in figure. VDD
D provides a drain to source voltage and
supplies current from drain to source
+ while VGG sets the reverse bias voltage
n channel

VDD between the gate and source. The

p p
_ JFET is always operated with the gate
_ G
source pn junction reversed biased.
VGG Reverse biasing of the gate source
+
S junction produces a depletion region
along the pn junction which extends
into the n channel and thus increases
its resistance by restricting the channel
width. Hence channel resistance can
be controlled by varying the gate
voltage, thereby control the amount of
drain current, ID.
JFET Characteristics and Parameters

RD

A ID
D
+
G
V VDS VDD
_ _
VGS V S
VGG
+
Consider the case when the gate to source voltage
(VGS) is zero. VDD (and thus VDS) is increased from 0V,
ID will increase proportionally between point A and B as
shown in figure. In this area, channel resistance is
essentially constant because the depletion region is not
large enough to have a significant effect. This is called
ohmic area because VDS and ID are related by Ohm’s
law. At point B, the curve levels off and ID becomes
essentially constant. As VDS increases from point B to
C, reveres bias voltage from the gate to drain (VGD)
produces a depletion region large enough to offset the
increase in VDS, thus keeping ID relatively constant.
Breakdown occurs at point C when ID begins to
increase very rapidly with further increase in VDS. As
VGS is set to increasingly more negative values by
adjusting VGG, family of drain characteristics curves is
produced as shown in figure. ID decreases as the
magnitude of VGS is increased. So amount of drain
current is controlled by VGS.
The JFET drain characteristic curves
ID (mA)
B IDSS C
VGS = 0

VGS = -1V

VGS = -2V

VGS = -3V

VGS = -4V
A VGS = VGS(off) = -5V
0 5 10 15 VDS (V)
VP (Pinch-off voltage) = +5V
Pinch-off when VGS = -1V
Pinch off voltage
For VGS = 0V, the value of VDS at which ID becomes essentially constant
(point B in figure) is the pinch off voltage, VP. A continued increase in VDS
above the pinch off voltage produces an almost constant drain current.
This value of drain current is labeled as IDSS (drain to source current with
gate shorted) and it is the maximum drain current.

Cutoff voltage
The value of VGS that makes ID approximately zero is the cutoff voltage,
VGS(off). JFETs must be operated between VGS = 0 and VGS(off). For this
range of gate to source voltages, ID will very from a maximum of IDSS to a
minimum of almost zero.
 Comparison of Pinch off and Cutoff

VGS(off) and Vp are always equal in magnitude but

opposite in sign. A data sheet usually will give
either VGS(off) or Vp, but not both. However, when
you know one, you have the other.
Ex: VGS(off) = - 5 V, Then VP = + 5 V
 n channel JFET transfer characteristics
The range of VGS values from zero to VGS(off) controls the amount
of drain current. For an n-channel JFET, VGS(off) is negative, and for a
p-channel JFET, VGS(off) is positive. Since VGS does control ID, the
relationship between these two quantities is very important. Graphical
relationship between VGS and ID is called transfer characteristic curve of
the JFET.
Notice that the bottom end of the curve is at a point on the VGS
axis equal to VGS(off), and the top end of the curve is at a point on the ID
axis equal to IDSS.
Operating limits of a JFET are
ID = 0 when VGS = VGS(off) and ID = IDSS when VGS = 0
n channel JFET transfer characteristics
ID (mA)

IDSS

-VGS (V)
VGS (off)
 Transfer characteristic curve can be developed from the drain
characteristic curves by plotting the values of ID for the values of VGS
taken from the family of drain curves at pinch off as shown in figure.

A JFET transfer characteristic curve is nearly parabolic in shape and can

be expressed as
2
 V 
I D  I DSS 1 - GS 
 V 
 GS(off) 

ID can be determined for any VGS if VGS(off) and IDSS are known. A parabolic
relationship is known as a square law, and therefore, JFETs and
MOSFETs are often referred to as square-law devices.
 ID (mA)

B IDSS C
12mA VGS = 0

7.68mA VGS = -1V

4.32mA VGS = -2V

1.92mA VGS = -3V

0.48mA VGS = -4V

0mA A VGS = VGS(off) = -5V
-5
-VGS (V) (mA) -4 -3 -2 -1 00 5 10 15 VDS (V) (mA)

VGS (off) (mA) VP (Pinch-off voltage) = +5V

Pinch-off when VGS = -1V

n channel JFET transfer characteristics The JFET drain characteristic curves

JFET forward transconductance
The forward transconductance (transfer conductance), gm, is the change
in drain current (ID) for a given change in gate to source voltage (VGS)
with the drain to source voltage constant. It is expressed as a ratio and
has the unit of siemens (S).

I D
gm 
VGS
gm is important in FET amplifiers as a major factor in determining the
voltage gain and it varies in value depending on the location on the curve
as set by VGS.

Approximate value of gm at any point on the transfer characteristics cure

can be calculated using following formula.

 VGS 

g m  g m0 1 -
 V 
 GS(off) 
2I DSS
Where gm0 is the value at VGS = 0 and it is equal to. g m0 
VGS(off)
n channel JFET transfer characteristics
ID

IDSS

ID2 I D2
g m2 
VGS

g m2  g m1
ID1 I D1
g m1 
-VGS VGS
VGS (off) VGS VGS VGS=0
 Input Resistance

A JFET operates with its gate source junction reverse biased,

which makes the input resistance at the gate very high. The high input
resistance is one advantage of the JFET over the BJT. (Recall that a BJT
operates with a forward biased base-emitter junction.)

VGS
R in 
I GSS
where IGSS is a value of the gate reverse current.
 JFET Biasing - Self Bias

+VDD -VDD

RD RD

VG = 0 VG = 0

RG + RG -
RS IS RS IS
- +

n channel p channel
 Self bias is the most common type of JFET bias. Recall that a
JFET must be operated such that the gate source junction is always
reverse biased. This condition requires a negative VGS for an n-channel
JFET and a positive VGS for a p-channel JFET. This can be achieved
using the self bias arrangements shown in figure. The gate resistor, RG,
does not affect the bias because it has essentially no voltage drop across
it; and therefore the gate remains at 0V. RG is necessary only to isolate an
ac signal from ground in amplifier applications.

For the n-channel JFET, IS produces a voltage drop across RS and makes
the source positive with respect to ground. Since IS = ID and VG = 0, and
VS = IDRS. The gate to source voltage is
VGS = VG – VS = 0 – IDRS = – IDRS
Thus VGS = – IDRS
For the p-channel JFET, the current through RS produces a negative
voltage at the source, making the gate positive with respect to the source.
Therefore IS = ID,
VGS = + IDRS
 In the following analysis, the n-channel JFET is used. Keeping in
mind that analysis of the p-channel JFET is the same except for opposite
polarity voltages. The drain voltage with respect to ground is determined
as follows:
VD = VDD – IDRD
Since VS = IDRS, the drain to source voltage is
VDS = VD – VS = VDD – ID(RD + RS) VDD
+15V
Ex: Find VDS and VGS in figure.
For the particular JFET in this circuit, ID RD
the internal parameter values such 5mA 1.0k
as gm, VGS(off), and IDSS are such that
VG = 0
a drain current (ID) of approximately 5
mA is produced. Another JFET, even
of the same type, may not produce RG
10M RS
the same results when connected in
220
this circuit due to the variations in
parameter values.
Setting the Q-Point of a Self Biased JFET
The basic approach to establishing a JFET bias point is to
determine ID for a desired value of VGS or vice versa. RS can be calculated
using the following relationship.
VGS
VGS  VG - VS  0 - ISR S  - I D R S  R S 
ID
For a desired value of VGS, ID can be determined in either of two
ways: from the transfer characteristic curve for the particular JFET or, or
more particularly, from following equation using IDSS and VGS(off) from the
data sheet.
2
 V 
I D  I DSS 1 - GS 
 V 
 GS(off) 
Midpoint bias
Under signal conditions, midpoint bias allows the maximum
amount of drain current swing between IDSS and 0.
ID(Q) = IDSS/2
2
 VGS  VGS(off)

I D  I DSS 1 -  VGS(Q) 
 V  3.4
 GS(off)  VDD
To set the drain voltage at midpoint, select the +12V
value of RD to produce the desired voltage drop. Choose
RG arbitrarily large to prevent loading on the driving stage
RD
in a cascaded amplifier arrangement.

Ex: Select RD and RS to set the

RG
approximate midpoint bias when IDSS =
10M RS
12mA and VGS(off) = -3 V
 Graphical Analysis of a Self Biased JFET
You can use the transfer characteristic curve of a JFET and certain
parameters to determine the Q point (ID and VGS) of a self biased circuit. If
a curve is not available, you can plot it using data sheet values for IDSS
and VGS(off).
ID
+VDD
IDSS=10mA

RD
1.0k

RG
10M RS
470 -VGS
-8V
VGS (off)
 To determine the Q point of the circuit in figure, a self bias dc load line is
established as follows. First calculate VGS when ID is zero.
VGS = -IDRS = (0)(470) = 0

This establishes a point at the origin on ID

the graph (ID = 0, VGS = 0). Next, get IDSS
IDSS
from the data sheet and calculate VGS 10mA
when ID = IDSS. From the curve IDSS = 10
mA.

VGS = -IDRS = -(10)(470) = -4.7 V Q 5.07mA

This establishes a second point on the

graph (ID = 10mA, VGS = -4.7V). Now, with -V
GS
two points, the load line can be drawn on -8V -4.7V -2.3V
the graph of the transfer characteristic VGS (off)
curve as shown. The point of the transfer
characteristic curve is the Q point of the
circuit.
 Voltage Divider Bias
An n-channel JFET with voltage divider bias is shown in figure. The
voltage at the source of the JFET must be more positive than the voltage
at the gate in order to keep the gate source junction reverse biased.
+VDD
The source voltage is
VS = IDRS
The gate voltage is set by resistors R1 and
R2 as expressed by the following equation R1 RD
using the voltage divider formula: ID
VG
 R2 
VG    VDD
 R1  R 2  R2 VS IS
RS
The gate to sorce voltage is
VGS  VG - VS
and the source voltage is
VS  VG - VGS
The drain current can be expressed as
VS
ID 
RS
Substititi ng for VS
VG - VGS
ID 
RS
 Graphical Analysis of a Voltage Divider Biased JFET
An approach similar to the one used for self bias can be used with
voltage divider bias to graphically determine the Q point of a circuit on the
transfer characteristic curve.
In a JFET voltage divider bias when ID = 0, VGS is not zero, as in the self
biased case, because the voltage divider produces a voltage at the gate
independent of the drain current. The voltage divider dc load line is
determined as follows.
For ID = 0,
VS = IDRS = (0)RS = 0
VGS = VG – VS = VG – 0 V = VG
Therefore, one point on the load line is at ID = 0 and VGS = VG.
For VGS = 0
VG - VGS VG
ID  
RS RS
A second point on the line is at ID = VG/RS and VGS = 0.
 ID

IDSS

dc load line

VG
Q RS

-VGS
VGS (off) VG
 Q Point Stability
The transfer characteristic of a JFET can differ considerably from one
device to another of the same type. If, for example, a 2N5459 JFET is
replaced in a given bias circuit with another 2N5459, the transfer
characteristic curve can very greatly. The maximum IDSS is 16 mA and the
minimum IDSS is 4 mA. Likewise the maximum VGS(off) is -8 V and the
minimum VGS(off) is -2 V. This means that the if you have a selection of
2N5459s and you pick one out, it can have values any where within the
these ranges. ID ID

IDSS
IDSS Voltage divider bias
ID much more stable
Self bias
Q2 ID2
Q2 ID2
ID1
Q1 ID1 Q1
-VGS -VGS
 The MOSFET
The MOSFET (metal oxide semiconductor field effect transistors) is the
second category of field effect transistor. The MOSFET differs from the
JFET in that it has no pn junction structure; instead, the gate of the
MOSFET is insulated from the channel by a silicon dioxide (SiO2) layer.
The two basic types of MOSFETs are depletion (D) and enhancement
(E). Because of the insulated gate, these devices are sometimes called
IGFETs.
 Depletion MOSFET (D-MOSFET)
n channel p channel
Drain Drain

SiO2 SiO2
n p

Gate Gate
p n
substrate substrate
n p

Channel Channel

Source Source
Drain (D) Drain (D)

Gate (G) Gate (G)

Source (S) Source (S)

 The drain and source are diffused into substrate
material and then connected by narrow channel adjacent to
the insulated gate.
The D-MOSFET can be operated in either of two
modes – the depletion mode or the enhancement mode –
and is sometime called a depletion/enhancement MOSFET.
Since the gate is insulated from the channel, either a positive
or negative gate voltage can be applied. The n-channel
MOSFET operates in the depletion mode when a negative
gate to source voltage is applied and in the enhancement
mode when a positive gate to source voltage is applied.
These devices are generally operated in the depletion mode.
Depletion and enhancement modes
Depletion mode:
The gate as one plate of a parallel plate capacitor and the
channel as other plate. The SiO2 insulating layer is the dielectric. With a
negative gate voltage, the negative charges on the gate repel conduction
electron from the channel, leaving positive ions in their place. Thereby,
the n channel is depleted of some of its electrons, thus decreasing the
channel conductivity. The grater the negative voltage on the gate, the
grater the depletion of n-channel electrons. At a sufficiently negative gate
to source voltage, VGS(off), the channel is totally depleted and the drain
current is zero. Like the n-channel JFET, the n-channel D-MOSFET
conducts drain current for gate to source voltages between VGS(off) and
zero. In addition, the D-MOSFET conducts for values of VGS above zero.

Enhancement mode:
With a positive gate voltage, more conduction electrons are
attracted into the channel, thus increasing (enhancing) the channel
conductivity as shown in figure.
 D-MOSFET Transfer Characteristics
The D-MOSFET can operate with either positive or negative gate voltages.
The point on the curves where VGS = 0 corresponds to IDSS. The point
where ID = 0 corresponds to VGS(off). As with the JFET, VGS(off) = -Vp.
The square-law for the JFET curve also applies to the D-MOSFET curve.
ID ID

IDSS IDSS

-VGS +VGS
VGS (off) 0 0 VGS (off)
n channel p channel
 Enhancement MOSFET (E-MOSFET)
Drain (D)

Gate (G)
Drain

SiO2 Source (S)

n
n channel
Gate
p
substrate
n Drain (D)

Source Gate (G)

Source (S)

p channel
The E-MOSFET operates only in the enhancement mode
and has no depletion mode. It differs in construction from the
D-MOSFET in that it has no structural channel. The
substrate extends completely to the SiO2 layer. For an n-
channel device, a positive gate voltage above threshold
value induces a channel by creating a thin layer of negative
charges in the substrate region adjacent to the SiO2 layer.
The conductivity of the channel is enhanced by increasing
the gate to source voltage and thus puling more electrons
into the channel area. For any gate voltage below the
threshold value, there is no channel.
 E-MOSFET Transfer Characteristics
The E-MOSFET uses only channel enhancement. Therefore, an n channel
device requires a positive gate to source voltage, and a p channel device
requires a negative gate to source voltage. In E-MOSFETs, there is no
drain current when VGS = 0. Therefore, the E-MOSFET does not have a
significant IDSS parameter, as do the JFET and the D-MOSFET. There is
ideally no drain current until VGS reaches a certain nonzero value called
the threshold voltage, VGS(th).
ID ID

+VGS -VGS
0 VGS(th) VGS(th) 0
n channel p channel
The equation for the parabolic transfer characteristic curve of the
E-MOSFET differs from that of the JFET and the D-MOSFET because the
curve starts at VGS(th) rather than VGS(off) on the horizontal axis and never
intersects the vertical axis. The equation for the E-MOSFET transfer
characteristic curve is
ID = K(VGS – VGS(th))2.
The constant K depends on the particular MOSFET and can be
determined from the data sheet by taking the specified value of ID, called
ID(on), at the given value of VGS and substituting the values into above
equation.
 MOSFET Biasing
D-MOSFET bias
D-MOSFETs can be operated with either
positive or negative values of VGS. Simple +VDD
bias method is to set VGS = 0 so that an ac
signal at the gate varies the gate to source
voltage above and below this 0 V bias point. RD
A D-MOSFE with zero bias is shown in figure.
Since VGS = 0, ID = IDSS as indicated. The
drain to source voltage is expressed as VG = 0 IDSS
follows:
RG VGS = 0
VDS = VDD – IDSSRD
The purpose of RG is to accommodate an ac
signal input by isolating it from ground. Since
there is no dc gate current, RG does not affect
the zero gate to source bias.
Zero biased D-MOSFET
 +VDD
E-MOSFET bias
E-MOSFET must have a VGS grater than the
threshold value, VGS(th), so zero bias can not R1 RD
be used. To make the gate voltage more
positive than the source by an amount
exceeding VGS(th), either the voltage divider or
drain feedback bias arrangement can be
used. R2
 R2 
VGS    VDD
 R1  R 2 
+VDD
VDS  VDD - I D R D
where I D  K VGS - VGS(th) 
2
RD
RG
In the drain feedback bias circuit, there is
negligible gate current and, therefore, no
voltage drop across RG. This makes VGS =
VDS
 FET Amplifiers

Common Source Amplifier

Common Drain Amplifier
Common Gate Amplifier
Analogous to the
Common Emitter Amplifier
Common Collector Amplifier
Common Base Amplifier
 Common Source Amplifier
JFET Self bias
+VDD Id
Vin  Vgs 
gm
Vout  Vds  I d R d
Vout Vout I d R d
Av    gmR d
Vin
Vin I d
gm
where R d  R D //R L
 VGS 
R in  R G // 
 I GSS 
 Common Drain Amplifier
JFET Self bias +VDD Vin  (Vgs  I d R s )  (Vgs  g m Vgs R s )
Vout  I d R s
Vout Id R s
Av  
Vin (Vgs  g m Vgs R s )
g m Vgs R s

(Vgs  g m Vgs R s )
Vin
gmR s

Vout
(1  g m R s )
where R s  R S //R L
 VGS 
R in  R G //  
 I GSS 
 Common Gate Amplifier
JFET Self bias +VDD Vout Vd
Av  
Vin Vgs
I d R d g m Vgs R d
Vout  
Vgs Vgs
 gmR d
Vin where R d  R D //R L
 1 
R in    // R S
 gm 