1132
6, JUNE 2005
Analysis of the Parasitic S/D Resistance in
Multiple-Gate FETs
Abhisek Dixit, Anil Kottantharayil, Member, IEEE, Nadine Collaert, Mike Goodwin, Member, IEEE,
Malgorzata Jurczak, and Kristin De Meyer, Senior Member, IEEE
Abstract—The multiple-gate field-effect transistor (FET) is a
promising device architecture for the 45-nm CMOS technology
node. These nonplanar devices suffer from a high parasitic
resistance due to the narrow width of their source/drain (S/D)
regions. We analyze the parasitic S/D resistance behavior of the
multiple-gate FETs using a novel, S/D geometry-based analyt-
ical model, which is validated using three-dimensional device
simulations and experimental results. The model predicts limits
to parasitic S/D resistance scaling, which reveal that the contact
resistance between the S/D silicide and Si-fin dominates the par-
asitic S/D resistance behavior of multiple-gate FETs. It is shown
that the selective epitaxial growth of Si on S/D regions alone may
be insufficient to meet the semiconductor roadmap target for
parasitic S/D resistance at the 45-nm CMOS technology node.
Index Terms—Analytical model, Fin field-effect transistors
(FinFETs), fully depleted, series resistance, silicon epitaxy, sil-
icon-on-insulator (SOI) MOSFET, small geometry, source/drain
(S/D), (110) transport.
I. INTRODUCTION
W ITH THE scaling of CMOS into sub-90-nm technology
nodes, control over short-channel effects (SCEs) be-
comes increasingly difficult in planar-bulk architecture. In order
to achieve the target subthreshold performance [1], high channel
doping concentrations are needed in planar bulk technologies.
This gives rise to significant dopant-induced fluctuations in
threshold voltage, and degradation in channel mobility [2].
A transition from planar bulk to the double-gate architecture
could facilitate the target subthreshold performance while also
keeping the channel-doping concentration low, if ultrathin Si
films and metal gates can be used to control SCEs and adjust
the threshold voltage [3], respectively.
One of the promising device architectures for sub-65-nm
CMOS technology nodes, originally proposed in 1980s as
XMOS [4], relies on multiple gates to control SCEs. More
refined members of this family of multiple-gate field-effect
transistors (MuGFETs) are FinFETs [5], tri-gate FETs [6],
Omega-FETs [7], Pi-gate FETs [8], and gate-all-around FETs
Manuscript received November 5, 2004; revised February 17, 2005. This
work was supported by the IMECs Industrial Affiliating Program under the
Industrial Affiliation Program (IIAP) on the Emerging Alternative Devices
(EMERALD). The review of this paper was arranged by Editor R. Singh.
A. Dixit and K. De Meyer are with the Inter-University Microelectronics
Center (IMEC) Leuven, Leuven B-3001, Belgium and also with the Depart-
ment of Electrical Engineering (ESAT), Katholieke Universiteit Leuven (KUL),
Leuven B-3001, Belgium (e-mail: Abhisek.Dixit@imec.be).
A. Kottantharayil, N. Collaert, and M. Jurczak are with the Inter-University
Microelectronics Center (IMEC) Leuven, Leuven B-3001, Belgium.
M. Goodwin is with Texas Instruments Inc., Dallas, 75243 TX USA.
Digital Object Identifier 10.1109/TED.2005.848098
0018-9383/$20.00 © 2005 IEEE
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO.
[9]–[11]. These devices have been reported to achieve the target
performance [12] with CMOS compatible processing.
For a CMOS technology to keep up with the downscaling,
improved carrier transport and low parasitic source/drain (S/D)
resistance are required [13]. As the device operation in
MuGFETs relies on the use of narrow fins, drive currents could
be severely degraded if special provisions are not made to mini-
mize [14]. The most commonly used model for series resis-
tance estimation in planar bulk MOSFETs [15] is inappropriate
for MuGFETs due to the three-dimensional (3-D) architecture
of these devices. The main shortcoming of the existing model is
its inability to capture series resistance issues arising from the
narrow width of S/D regions and current conduction on planes,
perpendicular to the S/D contacts. Although Kedzierski et al.
[16] have addressed this issue and proposed a technology solu-
tion, an analytical understanding of parasitic series resistance in
the MuGFETs is desirable.
This paper is organized in seven sections. In Section II, the
device structure is explained and details of the device simula-
tions are given. The analytical model for is described in
Section III. The process flow used for Omega-FET [7] fabrica-
tion is briefly described in Section IV. Both the procedure used
for extraction of the parasitic S/D resistance, and validation of
the analytical model using 3-D device simulations and experi-
mentally measured data are discussed in Section V. The key de-
vice parameters that dominate behavior of the MuGFETs
are identified in Section VI and their minimization is discussed.
The conclusions are given in Section VII.
II. DEVICE STRUCTURE AND SIMULATIONS
An n-channel double-gate MuGFET structure [5] has been
modeled using ISE-MESH [17] and is shown in Fig. 1(a). Cross
sections along the lines A-A and B-B are shown in Fig. 1(b)
and (1c), respectively. In the simulation mesh of the MuGFET
structure shown in Fig. 1(a), no grid points have been placed in
the S/D spacers. Abrupt, box-shaped S/D extensions and heavily
doped S/D (HDD) profiles have been defined analytically. The
S/D-silicide regions have been modeled as 3-D, area depen-
dent distributed resistances [17]. In the device simulations using
ISE-DESSIS [17], the contact resistivity of the S/D-silicide has
been set to a constant value of cm corresponding to
the target for 65-nm technology node [1]. Dashed rectangles in
Fig. 1(c) show the hypothetical location of the S/D-silicide. The
thickness of an additional Si layer on the HDD regions ,
has been included as one of the variables in the device structure.
This additional Si layer is used to mimic the Selective epitaxial
growth (SEG) of Si on the HDD regions with the assumption
DIXIT et al.: ANALYSIS OF THE PARASITIC S/D RESISTANCE 1133

TABLE I
NOMENCLATURE, SYMBOLS, AND VALUES OF THE PARAMETERS
USED IN THE SIMULATED DEVICE STRUCTURE

Fig. 1. MuGFET structure used in simulations: (a) 3-D view, (b) cross section
along the line A-A , and (c) cross section along the line B-B .

that is the same on the top surface and sidewalls of the Si

fin.
Drift-diffusion equations, coupled with the Continuity and
Poisson’s equations, have been solved for the device structure
shown in Fig. 1(a) using ISE-DESSIS [17]. In case of industry
standard (100) Si wafers, the mesa etch results in (110) fin side-
walls [16]. Due to this reason, the electron mobility has been
adjusted for conduction on (110) fin sidewalls in device sim-
ulations. The choice of a double-gate structure for this work
helps in avoiding mobility issues due to the current conduc-
tion on two different crystallographic planes, e.g., in case of a
triple-gate structure, the top surface is (100) whereas the side-
walls are (110). A double-gate operation has been ensured in
device simulations by the use of a thick oxide on the top surface
of the fin, as can be seen in Fig. 1(b) and (1c).
Device parameters used in the structure shown in Fig. 1(a) and Fig. 2. Schematic top view of a MuGFET with two fins. The contributions
to the parasitic resistance arising from different regions of the S/D geometry
their symbols are given in Table I. Two of the parameters listed are shown. Only one half of the device is shown as the device is symmetrical
in Table I, namely and have been used as the sim- about the center of the gate. The top surface of the fin is shown bare whereas
ulation variables. All of the device parameters have been kept it is always covered by the gate stack. The symbols shown in this figure are
explained in Table I.
fixed at their reference values shown in Table I, unless specified
otherwise.
shown in Fig. 2 is that the HDD regions can be wider than the
III. ANALYTICAL MODEL FOR THE PARASITIC S/D S/D extensions, only when an SEG of Si has been done in the
RESISTANCE IN MUGEFTS HDD regions. Thus, exists only in presence of this SEG
layer on the HDD regions. Resistance in Fig. 2 is the area
Parasitic series resistance in the S/D regions of a MuGFET
dependent contact resistance between the S/D-Si and S/D-sili-
has contributions from its components arising from different
cide regions.
parts of the S/D geometry. These components and their loca-
In the case of graded S/D extension doping profiles, is
tions in the S/D regions are shown schematically in Fig. 2. In
not easily separable from the active channel resistance, i.e.,
Fig. 2, is the accumulation resistance in the region of S/D
is considered as a part of [18]. As the device simulations
extensions overlapped by the gate. is the spread resistance
have been done with abrupt, box-shaped S/D extension doping
due to the spread of current from the thin accumulation layer
profiles, can be ignored. The resistivity of the accumulation
into the S/D extensions. is the resistance of the S/D exten-
layer can be expressed as [18]
sions beneath the S/D spacers (not shown in Fig. 2). is the
resistance due to the spread of current from the S/D extensions
into the wider HDD regions. An assumption made in the device (1)
1134
Fig. 3. Schematic illustration of the spread resistance model: (a) commonly
used model for planar-bulk MOSFETs (b) extended model for MuGFETs.
where is the gate-bias dependent electron mobility in the
accumulation layer present in the regions of S/D extensions un-
derneath the gate, is the gate oxide capacitance. It can be
seen from (1) that as becomes infinitely large, dimin-
ishes to zero. As is extracted at large values of , even
in cases when the S/D extension doping profiles are not abrupt,
e.g., in fabricated devices, can be safely ignored for the pur-
pose of modeling.
The most commonly used model for estimation of the spread
resistance in planar MOSFETs [19] is illustrated schematically
in Fig. 3(a). According to this model, the spread resistance is
given by
(2)
where is the sheet resistance of the source region, is the
source junction depth, W is the channel width, and is the
channel thickness. We have extended this model for the case
of double-gate MuGFETs as shown in Fig. 3(b). The modified
expression for this spread resistance can be written as
(3)
where is the resistivity of the S/D extensions. A constant ac-
cumulation layer thickness of 1.5 nm has been assumed for
in (3) [18]. The channel width (W) seen in (2) has been modified
to be the width per channel in (3), i.e., for the MuGFETs.
Further, the junction depth in (2) has been modeled by par-
titioning the fin into two identical halves and approximating the
spread resistance as a parallel combination of two identical re-
sistances, as seen in Fig. 3(b). Thus, has been replaced by
in (3) and a prefactor of 0.5 has been used to account
for the parallel combination of the two resistances. The model
in (3) is valid for MuGFETs with narrow fins only as will be
lesser than for the devices with wide fins. The validity
of the model for a particular fin width will then be governed by
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 6, JUNE 2005
Fig. 4. Contour plot of electron current density (A/cm ) simulated at V =
0:05 V and V = 1:0 V for n-channel MuGFETs. This reference device
assumes an overlayer of 20-nm Si on the HDD regions to mimic the SEG. Planes
A and B represent the interfaces between S/D silicide and HDD-Si, where the
drain current is collected.
the process conditions that determine the junction depth of the
S/D extensions.
The sheet resistance in the S/D extensions in Fig. 2 can
be modeled as
(4)
where is the length of the S/D extensions, which is as-
sumed to be equal to the S/D spacer bottom width in this model.
To model the parasitic resistance contributions arising from
the HDD regions and the S/D silicide contacts, 3-D nature of
current conduction in MuGFETs needs to be considered. In
order to trace the path of conduction current, a 3-D device sim-
ulation has been done using ISE-DESSIS [17] for the reference
device. This reference device assumes values of the constants
and variables same as those given in Table I, except for ,
which is assumed to be 20 nm. The electron current density
contours resulting from this device simulation are shown in
Fig. 4, where only the active layer (Si) has been shown for the
sake of clarity. It can be seen from Fig. 4 that the conduction
current is collected on the two planes A and B, where the S/D
silicide makes contact with the HDD regions.
The fraction of conduction current, collected on the plane A
in Fig. 4, goes directly into the S/D silicide and does not en-
counter any resistance other than the contact resistance, which
is modeled as
(5)
where is the thickness of the S/D silicide and is the
contact resistivity of the S/D silicide. The above equation is
valid only for . For the cases when ,
i.e., the contact between S/D silicide and Si fin on the plane A
vanishes, the model assumes . Another implicit as-
sumption in (5) is that , i.e., the fully
silicided S/D case is not considered.
DIXIT et al.: ANALYSIS OF THE PARASITIC S/D RESISTANCE 1135

The fraction of conduction current, collected on the plane B

in Fig. 4, first encounters an additional spread resistance .
The expression for this second spread resistance using our ex-
tended spread resistance model, as developed in (3), is given by

(6)

where is the resistivity of the HDD regions. The channel

width (W) in (2) is replaced by the width per channel, i.e.,
, in (6). Again, the device has been di-
vided in two halves and channel thickness in (2) has been
replaced by in (6). The junction depth in (2) has
been replaced by half the width of HDD regions after SEG, i.e.,
, in (6). Here, the width of the HDD regions after Fig. 5. Tilted SEM image of a multifin Omega-FET, taken after SEG process.
SEG of Si is given by Inset shows a transmission electron microscopy image of the cross section along
the line A-A .

(7)
two resistances arising from the division of conduction current
It should be noted here that (6) is valid only when in two fractions, i.e., one collected on the plane A and the other
, as for the values of the assumption of con- collected on the plane B. The resistance is given by
duction current spreading in only two directions is not valid and
it is expected to spread in all three directions.
In order to model the contact resistance for the fraction of (12)
conduction current collected on the plane ‘B’, transmission line
model [20] has been used. According to this model, in case of
the current conduction parallel to a semiconductor-metal inter- where the resistances and are given by
face, a minimum contact length exists before this conduction
current is actually transferred from the semiconductor to the
metal. This length is known as the transfer length (13)
and is given by (14)

(8) The right-hand sides of (13) and (14) can be evaluated using
(5)-(9). Thus, is given by (10), which is the resultant equa-
tion of this analytical model.
Using the transmission line model [21], contact resistance for
the fraction of conduction current collected on the plane B is
given by IV. DEVICE FABRICATION
N-channel Omega-FETs [7] have been fabricated on sil-
(9) icon-on-insulator (SOI) wafers. Starting with an SOI stack of
75-nm Si on 150-nm buried oxide, fins were patterned using
where is the physical length of the HDD regions. 193-nm optical lithography and dry etched. The devices were
To estimate the collective contribution of the planes A and annealed in an H ambient that helps with rounding the fin
B, has been modeled as a series combination of two resis- corners as well as smoothing the fin sidewalls, as is evident
tances and as from the inset in Fig. 5 [22], [23]. A thin, low-temperature
sacrificial oxide was then grown and used as a screen oxide
during -adjust implants. After well-anneal, this oxide was
(10) removed with wet etch. A stack of 2.5-nm nitrided oxide (phys-
ical thickness) and 100-nm-thick poly-Si was deposited. The
where the factor of two accounts for the resistance from both poly-Si gates were predoped and then patterned using 193-nm
the source and drain sides. In (10), is the resistance between optical lithography. Large tilt extension and halo implants were
the gate and S/D spacer edge, given by followed by a 950 C spike anneal. A low-temperature nitride
recessed spacer process was used and an SEG process was done
(11) on S/D regions. A tilted scanning electron microscope (SEM)
image of a multiple fin device, taken after the SEG process, is
where and are given by (3) and (4), respectively. Re- shown in Fig. 5. Low tilt HDD implants were followed by a
sistance in (10) is modeled as a parallel combination of the 1050 C spike anneal and a standard two-step NiSi process.
1136 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 6, JUNE 2005

Fig. 6. Measured gate characteristic curves for single-fin n-channel

Fig. 7. Total resistance as a function of gate voltage for the fabricated devices
Omega-FETs with 61-nm-high fins and 40-nm-long gates. Solid and dotted
with 18- and 120-nm-wide fins and 40-nm-long gates. The parasitic S/D
lines show the measurements on devices with 18- and 120-nm-wide fins,
resistance has been extracted from these curves at a gate voltage of 5 V. Squares
respectively.
and circles show measurements on devices with 18- and 120-nm-wide fins,
respectively. Solid and dotted lines have been fitted to the measurements on
devices with 18- and 120-nm-wide fins, respectively.
V. EXTRACTION OF THE PARASITIC S/D RESISTANCE AND
VALIDATION OF THE ANALYTICAL MODEL
The total resistance of a MOSFET can be written as [18]

(15)

The absolute source currents are plotted as a function

of the gate-to-source voltage in Fig. 6 for single fin
nm devices with 18-, 120-nm-wide fins and
40-nm-long gates. At low and infinitely large ,
diminishes asymptotically and becomes equal to .
The total channel resistance at low has been extracted as a
function of for the – curves shown in Fig. 6 and is
plotted in Fig. 7. A first-order exponential curve fitting on the
experimental data generates the asymptotic part of the curve.
It can be seen from Fig. 7 that for high values,
becomes constant, and is taken as .
In order to validate the analytical model, 3-D device simula-
tions have been done for the reference device with variable fin
Fig. 8. Parasitic S/D resistance as a function of fin width. The analytical model
widths. has been extracted from simulated – curves. has been compared with 3-D device simulations using ISE-DESSIS. Reference
A comparison of these extracted values and those calcu- case values of the device parameters have been used and R has been extracted
lated using the analytical model for the same set of device pa- at V = 50 mV for these n-channel MuGFETs.
rameters is shown in Fig. 8. A constant electron mobility of 37
cm in S/D extensions and HDD regions, corresponding of cm , and an as-measured S/D-HDD length
to the result of device simulation shown in Fig. 4, has been used of 150 nm have been used as inputs to the analytical model.
in the analytical model throughout this work. As can be seen The values of , extracted from experimentally measured
from Fig. 8, our analytical model is in good agreement with 3-D – curves, have been compared with the analytical model
device simulations. in Fig. 9 as a function of fin width. The analytical model data
For further validation of the analytical model using experi- in Fig. 9 shows values calculated using (10). It can be
mental results, a few input parameters have been modified from seen from Fig. 9 that the model agrees very well with the ex-
the previously used values. The S/D spacer bottom width perimental results within the range of validity of the analytical
has been set to a value of 53 nm as measured on the fabricated model, as imposed by the narrow fin width requirement, i.e.,
devices. A contact resistivity of cm has , in (3).
been assumed for the S/D nickel silicide on the heavily doped It should be noticed that even though the model was basi-
Si S/D regions in the fabricated devices. Also, an as-measured cally formulated for a double-gate MuGFET, i.e., (3), it agrees
SEG thickness of 23 nm, an extension doping well with the experimental data measured on fabricated Omega-
DIXIT et al.: ANALYSIS OF THE PARASITIC S/D RESISTANCE 1137

Fig. 9. Parasitic S/D resistance as a function of fin width. The analytical model
has been compared with experimental results. The experimental data shows
statistical mean of measurements over 5 dies and error bars show the standard
deviation of the results from the mean value. Fins wider than 60 nm do not meet
W
the criterion of narrow fins, i.e., < x 2 in S/D extensions, hence the
model (3) is not valid for the devices with fins wider than 60 nm. Fig. 11. Parasitic S/D resistance as a function of SEG thickness. Reference
case values of device parameters have been used as input to the analytical model
and 3-D device simulations.

VI. MINIMIZATION OF THE PARASITIC SOURCE/DRAIN

RESISTANCE
The short channel performance of a MuGFET is strongly de-
pendent on the width of the fin, necessitating the use of narrow
fins for shorter gate length technologies [7]. In order to
evaluate the performance of a MuGFET relative to a planar
MOSFET, effective width of the device must be taken
into consideration. In case of triple-gate devices, could
be written as

(16)

To compare values shown in Figs. 8 and 9 with those

projected by the semiconductor road map [1], could be
normalized as

Fig. 10. Parasitic resistance as a function of fin width. The contribution of m m (17)
spread resistance, present in the S/D extensions, to the total parasitic S/D
resistance is shown for double-gate and triple-gate cases for the models (3) and where can be calculated from (16). The gravity of the
(10).
problem of series resistance in MuGFETs can be clearly seen in
Fig. 8, where due to a reduction in the fin width from 65 to 20
FETs (triple-gate devices). From the perspective of the model nm, is seen to increase by a factor of three.
(10), the only difference expected in the behavior of a triple-gate For the minimization of , the S/D width , as given
device as compared to a double-gate device should be in by (7), must be increased. An SEG of Si on the HDD regions has
given by (3). This justifies the approximation, made in (3), of been reported as a technology solution for this [16]. In order to
modeling this spread resistance as a parallel combination of estimate the potential of SEG of Si on the HDD regions in over-
spread resistors distributed on all the current carrying faces of coming the parasitic S/D resistance, has been plotted as a
the fin. Thus, with an increasing number of current carrying function of thickness of the SEG layer in Fig. 11. To arrive at the
faces (three for the triple-gate device as compared to two for the results shown in Fig. 11, the reference values of device param-
double-gate device), is expected to decrease further. The eters as described in Table I with variable have been used
magnitudes of and for a double- and triple-gate device as input to the model (10) and the 3-D ISE-DESSIS simulations
are compared in Fig. 10 using the models of (3) and (10). As can [17]. It can be seen from Fig. 11 that improves drastically
be seen from Fig. 10, is much smaller than . Therefore, while going from no SEG device, i.e., , to a device
even for the case when (3) is not valid e.g., for a Omega-FET with SEG.
being a triple-gate device, results of the model (10) still show The parasitic S/D resistance along with its two main
good agreement with experimental results of Omega-FET de- components (11) and (12) has been plotted as a func-
vices in Fig. 9. tion of in Fig. 12. A device with a constant fin width
1138 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 6, JUNE 2005

Fig. 12. Parasitic resistance as function of S/D width. Components of R in
(10), i.e., R and R are shown. The S/D width is increased by SEG of Si in
HDD regions while keeping the fin width fixed at 20 nm. Over the whole range
of S/D widths, the parasitic S/D resistance of the device is determined by the
component R .
Fig. 13. Parasitic resistance as function of S/D width. The components of
resistance R are shown. The S/D width is increased by SEG of Si in HDD
regions while keeping the fin width fixed at 20 nm. The resistance R is almost
same as R and therefore the curve for R is not visible in this semi-log plot.
Over the whole range of S/D widths, component R is determined by the contact
resistance on plane B, i.e., R .

nm has been assumed in Fig. 12 and is in-

creased by increasing in (7). As can be seen from Fig. 12,
the use of SEG reduces only the component of whereas
component stays the same with increasing . This is ex-
pected as SEG is done in the HDD regions and the component
exists between the channel and HDD regions. An upper limit
on could be the spacing between adjacent fins (S2), as can
be seen from Fig. 2. Competitive pattern density demands S2
values which are less than 100 nm [24]. This means that the
maximum usable per fin is less than 120 nm and the max-
imum usable thickness of the Si SEG layer on the HDD regions
is less than 50 nm for a multifin MuGFET with 20-nm-wide fins.
For the device under consideration in Fig. 12, with this upper
limit on and hence on , is expected to be al-
ways dominated by the component .
Component of the parasitic S/D resistance is primarily
due to contact resistances encountered on the planes A and B
(Fig. 4). As can be seen from (12), component is the resul- Fig. 14. Parasitic resistance as a function of S/D silicide contact resistivity.
tant of the parallel combination of contact resistances and The parasitic resistance values shown in figure have been normalized using (17).
. Various components of as seen from (12), (13) and (14) The dash-dotted line without symbols represents ITRS R specification (160
have been plotted as a function of in Fig. 13. The device
0

m) for the low operating power 45 nm technology node. The solid- and
dashed-lines with different symbols represent total R and its R component
assumed in Fig. 13 is the same as that in Fig. 12. It can be visu- respectively. The dotted line without symbols represents R component of R .
alized from (13) and (14) that amongst the two of and , The square symbols represent the reference case device, as defined in Table I,
with T = 50 nm. Circles represent the same device as squares but with
has lesser potential for the minimization of as its area is 50% reduced spacer bottom width, i.e., W = 20 nm. Triangles represent the
actually limited by the narrow fin i.e., is a small number. same device as circles but with 5 times higher doping in S/D extensions, i.e.,
Therefore, the key to parasitic S/D resistance minimization in N 2
= 5 10 cm .
MuGFETs is the reduction of the resistance . It can be seen
from Fig. 13 that SEG on the HDD regions reduces via re- in presence of an SEG layer on the HDD regions, further min-
duction of , which is the dominating part in (14) as imization of could be achieved only by increasing
is expected to be much lower than . It is clear from (5), for the same . In this perspective, S/D silicide contacts
(13) and Fig. 13 that for a fixed silicide thickness, increasing wrapping around the HDD regions can be useful [25], i.e., addi-
increases until it is forced to zero in accordance with tional contact area from the HDD sidewalls, which are normal
validity condition for (5) i.e., for . to the plane B (Fig. 4), can bring further reduction in .
But since comes in parallel with while determining , Technology guidelines for the minimization of in
is seen to decrease with increasing in Fig. 13. Thus, MuGFETs are drawn from the analytical model by plotting
DIXIT et al.: ANALYSIS OF THE PARASITIC S/D RESISTANCE
parasitic resistance as a function of S/D silicide contact re-
sistivity in Fig. 14. For the reference device in Fig. 14, a S/D
silicide contact resistivity of cm is needed to meet the
International Technology Roadmap for Semiconductors (ITRS)
target for for the low operating power 45 nm technology
node [1]. Amongst the components of (10), dominated
by S/D extension resistance and contact resistance , Linton, A. Murthy, R. Rios, and R. Chau, “High performance fully-de-
is seen to dominate the parasitic S/D resistance for the
reference device in Fig. 14 for all the values of the contact
resistivity lower than cm . This implies that the
contact resistivity specification could be relaxed by reducing
the component . This has been illustrated in Fig. 14 by
reducing the spacer bottom width by 50%. It should be noticed
here that at low S/D-HDD lengths , local variations
in silicide resistivity may affect S/D silicide contact resistivity
[26]. However, this length dependence of contact resistivity has
not been taken into account in our model owing to the micro-
scopic nature of this phenomenon [27]. A further relaxation in
contact resistivity specification could be achieved by the use
of higher S/D extension doping, as can be seen from Fig. 14.
However, the realization of such heavily doped S/D extensions
might require integration of novel doping processes, such as
vapor phase doping, in the CMOS processing.
VII. CONCLUSION
An analytical model for the parasitic S/D resistance in
MuGFETs has been developed and validated with the help of
3-D device simulations and experimental results. The parasitic
S/D resistance has been seen to increase with decreasing fin
width. The contact resistance in the S/D-HDD regions has been
shown to dominate the parasitic S/D resistance behavior of the
narrow fin devices in the range of interest. The SEG of Si on
the S/D-HDD regions is shown to be a potential solution for
minimizing the parasitic S/D resistance of narrow fin devices.
Even in the presence of an SEG Si layer on the HDD-regions, it
was observed that the S/D silicide contact resistivity should be
lowered to meet the ITRS target for the low operating power 45
nm technology node. However, reducing the S/D spacer bottom
width and increasing the S/D extension doping, the requirement
of a very low S/D silicide contact resistivity could be relaxed.
ACKNOWLEDGMENT
The authors would like to thank the IMEC-Pilot line for
the device fabrication and AMSIMEC for the measurement
support, the CMOSDR/DIP group for encouraging discussions,
V. Vrankx for her secretarial support, and S. Biesemans for the
overall direction of the IIAP EMERALD.
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Abhisek Dixit was born in Kanpur, India. He
received the M.S. degree in physics, with a spe-
cialization in electronics, from the University of
Kanpur in 1997 and the M. Tech. degree in materials
science and engineering from the Indian Institute of
Technology (IIT) Bombay, Bombay, India, in 2002.
His thesis was on device engineering for sub-100-nm
CMOS technologies. He is currently pursuing his
Ph.D. degree at the Katholieke Universiteit Leuven
(KUL), Belgium.
He joined the Industrial Research and Consultancy
Center (IRCC), IIT, as a Junior Research Fellow in 1998, and worked on projects
sponsored by the Indian Space Research Organization (ISRO), Indo-French Col-
laboration for the Promotion of Advanced Research (IFCPAR), and Depart-
ment of Science and Technology (DST). In September 2002, he joined the De-
partment of Electrical Engineering (ESAT), KUL, as a Predoctoral Student.
He is now with the Inter University Microelectronics Center (IMEC), assigned
to the IMEC Industrial Affiliation Program on Emerging Alternative Devices
(IIAP-EMERALD) in the CMOS Device Research Department of the Silicon
Process and Device Technology (SPDT) division. His current research interests
include analytical modeling of MuGFET parasitics, and FEOL integration of
sub-45-nm multiple-gate devices and circuits.
Anil Kottantharayil (M’98) received the B. Tech.
degree in electronics and communication engi-
neering from the Regional Engineering College
Calicut, University of Calicut, Kerala, India, in
1993, the M. Tech. degree in electrical engineering
from the Indian Institute of Technology, Bombay,
India, in 1997, and the Dr. Ing. degree (summa cum
laude) from the Faculty of Electrical Engineering,
Universität der Bundeswehr, Munich, Germany, in
2002. His Ph. D. dissertation was on low-voltage
hot-carrier effects in MOS devices.
Since November 2001, he has been with the Inter University Microelectronics
Center (IMEC), Leuven, Belgium. His interests are in the areas of MOS device
physics, device integration, characterization, simulation, and modeling. He has
authored or coauthored more than 25 papers in peer-reviewed international jour-
nals and conference proceedings.
Dr. Kottantharayil was a recipient of the “Youth and Knowledge” fellowship
from Siemens AG during his stay in Germany.
Nadine Collaert was born in Dendermonde, Belgium, in 1972. She received the
M.S. and Ph.D. degrees in electrical engineering, both from the Katholieke Uni-
versiteit Leuven, Leuven, Belgium, in 1995 and 2000, respectively. Her Ph.D.
dissertation was on modeling and characterization of a novel vertical Si–SiGe
heterojunction MOSFET.
Currently, she is a Researcher in the CMOS device research department at
Inter University Microelectronics Center (IMEC). Her research interests include
the theory, design, and technology of multiple-gate devices.
Mike Goodwin (M’98) received the Ph.D. degree from the University of North
Texas, Dayton, in 1982.
He joined Texas Instruments (TI), Inc., Austin, TX, in 1982. For the next 12
years, he developed advanced infrared detector devices under various grants and
programs sponsored by the U.S. Government. He then transferred to the Silicon
Technology Development Department, TI, and as part of a team developed high-
performance transistors for the 180- and 90-nm nodes. For the last two years,
he has worked at Inter University Microelectronics Center (IMEC) Leuven,
Leuven, Belgium, as a TI assignee developing multigate transistor structures.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 6, JUNE 2005
Malgorzata Jurczak received the M.Sc. and Ph.D.
degrees in electrical engineering from the Warsaw
University of Technology (WUT), Warsaw, Poland
in 1991 and 1997.
In 1991, she joined WUT where she worked on
modeling of MOS SOI devices. In 1994, she was
with NMRC, Cork, Ireland and in 1997 with Kyung
Hee University, Seoul, Korea. In 1998, she joined
CNET Grenoble, France Telecom, Grenoble, France.
She was involved in the development of 0.18- and
0.12-m CMOS process and alternative approaches
for sub-0.1-mm CMOS. In 2000, she joined Inter University Microelectronics
Center (IMEC) Leuven, Leuven, Belgium. From 2000 to 2003, she was
the IMEC Coordinator of the JDP program with Philips on device process
integration for 90- and 65-nm CMOS. From 2003, she has been the Group
Leader of the CMOS Device Implementation Projects (45-nm CMOS, FUSI
gates, strained-Si, HK+MG integration, FD SOI, and MUGFET). She is also a
Project Manager of IMEC Industrial Affiliation Program (IIAP) on emerging
alternative devices (EMERALD). She has participated in several European
projects:, including ACE, ULTRA, MEDEA, and HUNT. She was the Project
Coordinator of the European IST ARTEMIS project. Currently, she is on the
Technical Advisory Committee of the IST Integrated project Nano-CMOS. She
holds 15 French and American patents and has authored and coauthored more
than 60 papers.
Dr. Jurczak received the Best Paper Award at the ESSDERC’2000 Con-
ference and the Paul Rappaport Award for the best paper published in IEEE
TRANSACTIONS ON ELECTRON DEVICES in 2000. She has been a member of
the scientific committees of IEDM in 2002 and 2003, and the ESSDERC
conferences in 2000, 2004, and 2005.
Kristin De Meyer (S’73–M’79–SM’00) received the
M.S. and the Ph.D. degrees from the Katholieke Uni-
versiteit Leuven (KUL) Leuven, Belgium, in 1974
and 1979, respectively.
From 1974 to 1975, she was a Fellow of the In-
stitute for Scientific Research in Industry and Agri-
culture (IWONL), Laboratory for Physics and Elec-
tronics of Semiconductors, KUL, working on CCD
filter design. From October 1975 through September
1979, she was a Research Assistant of the National
Fund for Scientific Research (NFWO) at the same
laboratory on the design, development, and characterization of two-phase buried
channel CCDs. From November 1979 to November 1980, she was granted an
IBM World Trade Post-Doctoral Fellowship and was with the IBM Thomas
J. Watson Research Center, Yorktown Heights, NY, researching the develop-
ment of EAROMs using Si-rich oxides. At the end of 1980, she returned to
KUL as a Senior Research Assistant of the NFWO, and in October 1982, as a
Research Associate of the NFWO. Her activities moved from KUL to the In-
teruniversity Microelectronics Center (IMEC), Leuven, where she initially re-
mained Research Associate of the NFWO. In October 1989, she became a reg-
ular employee of IMEC. From 1985 through 1992, she was Head of the Process
and Device Modeling and Simulation Group, working on process optimization
techniques, parameter extraction, analytical and numerical device modeling,
and computational physics. Also, Statistical Process Control Activities (SPC)
were monitored through her group. In January 1993, she was put in charge
of deep-submicrometer MOS technology and exploratory field-effect devices.
Since October 1986, she has also been a part-time Professor at KUL. She is
the Coordinator for IMEC in the ESPRIT 962 EVEREST, STORM, NOVA,
ULTRA, VAHMOS2000, FASEM, and ULIS projects. She was also involved
in the ESPRIT ACCESS Program, ADEQUAT, and ACE. She also managed
the HCM-SUSTAIN network on deep-submicrometer silicon technology with
21 partners from academia and research institutes. She authored or coauthored
over 200 publications and organized summer courses and the SISPAD’98 Con-
ference, and the ULIS 2004 workshop.
Dr. De Meyer is a member of the ITRS working Group on Process Integration,
Devices and Structures (PIDS). She is currently Editor of the IEEE ELECTRON
DEVICE LETTERS.