Basic Electronics by Bakshi PDF

As per Revised Syllabus of
Visvesvaraya Technological University
®
Basic Electronics - at a Glance
(One day Revision Book)
Atul P. Godse
M.S. Software Systems (BITS Pilani)
B.E. Industrial Electronics
Formerly Lecturer in Department of Electronics Engg.
Vishwakarma Institute of Technology
Pune
Uday A. Bakshi
M.E. (Electrical)
Formerly Lecturer in Department of Electronics Engg.
Vishwakarma Institute of Technology
Pune
® TM
TECHNICAL
PUBLICATIONS technical@vtubooks.com
An Up-Thrust for Knowledge www.technicalpublications.org
(i)
TT able of Contents
Module - 1
Chapter - 1 Semiconductor Diodes and Applications ®
(1 - 1) to (1 - 40 )
Chapter - 2 Bipolar Junction Transistor (2 - 1) to (2 - 22)
Module - 2
Chapter - 3 BJT Biasing (3 - 1) to (3 - 16)
Chapter - 4 Introduction to Operational Amplifiers (4 - 1) to (4 - 28)
Module - 3
Chapter - 5 Digital Electronics (5 - 1) to (5 - 34)
Module - 4
Chapter - 6 Flip-Flops (6 - 1) to (6 - 6)
Chapter - 7 Microprocessors and Microcontrollers (7 - 1) to (7 - 26)
Chapter - 8 Transducers (8 - 1) to (8 - 10)
Module - 5
Chapter - 9 Communication Systems (9 - 1) to (9 - 34)
Chapter - 10 Telephone Systems and Optical Fibre Communication

(10 - 1) to (10 - 8)
(ii)
Semiconductor Diodes
1 and Applications
Chapter at a Glance
1. Introduction to P-N Junction
The two types of materials namely n-type and p-type are chemically combined with a
special fabrication technique to form a p-n junction. Such a semiconductor p-n junction
forms a popular electronic device called diode.
2. Theory of P-N Junction
There exists a wall near the junction with negative immobile charge on p side and
positive immobile charge on n side. There are no charge carriers in this region. The region
is depleted off the charge carriers hence called depletion region, depletion layer or space
charge region.
Material Symbol Value of barrier potential

Silicon Si 0.6 V
Germanium Ge 0.2 V
3. The P-N Junction Diode

Direction of conventional current
Anode Cathode
p type n type
Fig. 1.1 Symbol of a diode
4. Reverse Biasing of Diode
If reverse voltage is increased beyond particular value, large reverse current can flow
damaging the diode. This is called reverse breakdown of a diode.
Such a reverse breakdown of a diode can take place due to the following two effects,
1. Avalanche effect and 2. Zener effect
(1 - 1)
TM
TECHNICAL PUBLICATIONS - An up thrust for knowledge

Basic Electronics 1-2 Semiconductor Diodes and Applications
5. V-I Characteristics of Diode
If(mA) Forward
characteristics
Normal
operating region
Reverse breakdown
voltage I
0 Knee
VBR
VR Vf
Vg
Knee I0 Cut in
Reverse voltage
Breakdown
saturation
region
current
Reverse
characteristics
IR(mA)
Fig. 1.2 Complete V-I characteristics of a diode
6. Diode Current Equation and Nature of Characteristics

The diode current equation is,
[
I = I 0 e V / hVT - 1 ]A
where I0 = Reverse saturation current in amperes, V = Applied voltage
h = 1 for germanium diode and = 2 for silicon diode
VT = Voltage equivalent of temperature in volts
VT = kT volts
–5
VT = 8.62 ´ 10 ´ 300 = 0.02586 V » 26 mV ... At 27 ºC
For forward biased, V must be taken positive and we get current I positive
which is forward current. For reverse biased, V must be taken negative and we
get negative current I which indicates that it is reverse current.
7. D.C. Equivalent Circuits of Diode
Sr. No. Diode approximation Behaviour D.C. Equivalent circuit
1. Ideal diode Rf = 0 W
Rr = ¥ W If
Short in forward bias.
TM

2. Vf = V g
Diode with constant The forward voltage drop + –
forward voltage drop is constant and it behaves
as d.c. battery of voltage If
Vf = Vg
3. Complete d.c. equivalent This assumes finite forward Vg rf

circuit resistance which is its + –
dynamic forward resistance
r f in series with battery of Ideal
If
voltage Vg .
Total diode drop is,

Vf = Vg + If rf
8. Rectifiers
A rectifier is a device which converts a.c. voltage to pulsating d.c. voltage, using one or
more p-n junction diodes.
9. Ripple Factor
\ Ripple factor g=
R. M. S. value of a.c. component of output
Average or d.c.component of output
I ac I 2RMS - I 2DC æI ö
2
Ripple factor = = = ç RMS ÷ - 1 …As per definition
I DC I DC I
è DC ø
10. Transformer Utilization Factor (T.U.F.)
D. C. Power delivered to the load

\ T.U.F. =
A. C. Power rating of the transformer
11. Voltage Regulation
(Vdc ) NL – (Vdc ) FL
%R= ´ 100
(Vdc ) FL
TM

12. Comparison of Rectifier Circuits

Circuit Diagrams
Half Wave Full Wave Bridge
RL
iL
RL RL
iL
iL
Sr. No. Parameter Half Wave Full Wave Bridge

1. Number of diodes 1 2 4
2. Average D.C. current ( IDC ) Im 2I m 2I m
p p p
3. Average D.C. voltage ( E DC ) E sm 2E sm 2E sm
p p p
4. RMS current ( IRMS ) Im Im Im
2 2 2
5. D.C. power output (PDC ) I2m R L 4
I2m R L
4
I2m R L
p2 p2 p2
6. A.C. power input ( PAC ) I2m ( R L + R f + R s) I2m ( R f + R s + R L) I2m ( 2R f + R s + R L)

4 2 2
7. Maximum rectifier efficiency ( h) 40.6 % 81.2 % 81.2 %

8. Ripple factor ( g) 1.21 0.482 0.482
9. Maximum load current ( I m ) E sm E sm E sm
Rs + R f + RL Rs + R f + RL R s + 2R f + R L
10. PIV rating of diode Esm 2 Esm Esm

11. Ripple frequency 50 Hz 100 Hz 100 Hz
12. T.U.F. 0.287 0.693 0.812
13. Filter Circuits
The filter is an electronic circuit composed of capacitor, inductor or combination of

both and connected between the rectifier and the load so as to convert pulsating d.c. to
pure d.c.
TM

14. Approximate Analysis of Capacitor Filter

Vr
Vr(rms) = … As triangular
2 3
E DC
Vr = = Peak to peak ripple voltage … For full wave
2 f C RL
Vr (rms) 1
Ripple factor = = … For full wave
E DC 4 3 f C RL
\ Ripple factor =
1
2 3 f C RL … For half wave
E DC = E sm - I DC é
1 ù
êë 4 fCúû … For full wave
E DC = E sm - I DC é
1 ù
êë 2 fCúû … For half wave
15. Expression for Ripple Voltage
\ Vr(rms) =
I DC
volts (For full wave) ... (a)
4 3f C
\ Vr (rms) =
I DC
volts (For half wave) ... (b)
2 3fC
16. Power Supply Performance
SR = VHL – VLL
SR
% SR = ´ 100 where Vnom= Nominal load voltage
Vnom
LR = VNL – VFL
VNL - VFL
\ % LR = ´ 100
VFL
TM

D Vout
Rout =
DI L Vin and temperature constant
D Vout
SV =
D Vin I L and temperature constant
D Vout
ST =
DT Vin and I L constant
Ripple content in output VR(out)

RR = =
Ripple content in input VR(in)
17. Zener Diode as a Shunt Regulator
R
+ +
I IL
L
Vin + O
D V Vo RL
Unregulated –Z A
Iz D
–
–
Fig. 1.3 Zener diode as a shunt regulator
Vin - VZ Vin - VZ
R= i.e. I=
I R
I = IZ + IL
18. Design of Zener Regulator
Vinmin - VZ Vinmin - Vo
Rmax = = … (1)
I Lmax + I Zmin I Lmax + I Zmin
Vinmax - VZ V - Vo
Rmin = = inmax … (2)
I Lmin + I Zmax I Lmin + I Zmax
PD P
I Zmax = or = Z
VZ VZ
TM

19. Series Negative Clipper Circuit

+ –
Input D
Vin Load RL Vo
Fig. 1.4 Negative series clipper

Vin Vo
Vm Vm
t t
0 p 2p 0 p 2p
Negative half is
clipped off
(a) Input voltage (b) Output voltage

Fig. 1.5 Waveforms of series negative clipper
20. Series Positive Clipper Circuit

– +
D
Input Vin Load RL Vo Output
Fig. 1.6 Positive series clipper

Vin Vin
Input Input
+Vm +Vm
t t
0 p 2p 0 p 2p
–Vm –Vm
Vo Vo
Positive is Positive is
clipped off Output clipped off Output
p t p t
0 2p 0 2p
–Vm –Vm
Voltage across Voltage across
VD ideal diode VD ideal diode
D D D D
OFF ON OFF ON
p t p t
0 2p 0 2p
–Vm –Vm
(a) Sinusoidal input (b) Triangular input

Fig. 1.7 Waveforms of series positive clipper
TM

21. Parallel Clipper with Positive Clipping

R1 A Vin
Input
+ –
+ t
I 0 p 2p
Input D RL Vo –Vm
D
– and RL
in parallel Vo
D D
ON OFF
p 2p
t
0
–VmRL
Fig. 1.8 Parallel positive clipper
R1+RL
Positive half cycle of
input clipped off
Fig. 1.9 Waveforms for parallel
positive clipper
22. Parallel Clipper with Negative Clipping
R1 A Vin
Input
Input Vin D RL Vo Output

p t
0 2p
Vo D D
(OFF) (ON)
Fig. 1.10 Basic parallel clipper
t
p 2p
Negative half cycle
of input clipped-off
Fig. 1.11 Waveforms for parallel
negative clipper
23. Clamper Circuits
The circuits which are used to add a d.c. level as per the requirements to the a.c. output
signal are called clamper circuits.
TM

Important Theory Questions and Answers
Ø What is a p-n junction ? + VTU : Aug.-01, Feb.-02, 04, Marks 3, Jan.-09, Marks 2
The two types of materials namely n-type and p-type are chemically combined with a
special fabrication technique to form a p-n junction. Such a semiconductor p-n junction
forms a popular electronic device called diode.
Ø Describe the physical mechanism of avalanche and zener breakdown in a p-n junction diode.
+ VTU : Aug.-99, 2000, 02, 05, March-01, 02, 05, Marks 5, Aug.-04, Marks 4
Breakdown Due to the Avalanche Effect :
· If reverse voltage is increased, at a particular value, velocity of minority carriers
increases.
· Due to the kinetic energy more minority carriers are generated. The collision make the
electrons to break the co-volent bonds.
· These electrons are available as minority carriers. They again collide with another atoms
to generate more minority carriers. This is called carrier multiplication.
· Finally large number of minority carriers move across the junction, breaking the p-n
junction. These minority carriers give rise to a very high reverse current.
· This effect is called avalanche effect and the mechanism of destroying the junction is
called reverse breakdown of a p-n junction.
Breakdown Due to the Zener Effect :
· When a p-n junction is heavily doped the depletion region is very narrow.
· Due to narrow depletion region and high reverse voltage, electric field is intense.
· Such an intense field is enough to pull the electrons out of the valence bands of the
stable atoms.
Such a creation of free electrons is called zener effect. These minority carriers constitute
very large current and mechanism is called zener breakdown.
Ø Draw and explain the V-I characteristics of a p-n junction diode.
+ VTU : Aug.-99, 2000, 01, 04, 05, March-2000, 01, Jan.-02, 04, 09, 13, Marks 8
· In forward biasing Vf is the voltage across the p-n junction and If is the forward
current.
· The forward characteristics of a diode is shown in the Fig. 1.12.
· Forward characteristics can be divided into two regions :
1. Region O to P : As long as Vf is less than cut-in voltage (Vg ) , the current flowing is
very small.
2. Region P to Q and onwards : As Vf increases towards Vg the width of depletion
region goes on reducing. When Vf exceeds Vg the depletion region becomes very thin
TM

Basic Electronics 1 - 10 Semiconductor Diodes and Applications
and current If increases suddenly. This If

in mA
increase in the current is exponential as
shown in the Fig. 1.12 by the region Q
P to Q. F
D
· The point P, after which the forward
DIf
current starts increasing exponentially is
E
called knee of the curve and the C
corresponding voltage is called knee
Knee
voltage.
· Forward characteristics is plotted in the P
DVf
first quadrant. O A B Vf
in volts
Cut-in
· The reverse voltage across the diode is VR voltage (vg)
and reverse current through the diode is IR
hence graph of IR against VR is called Fig. 1.12 Forward characteristics of a diode
reverse V-I characteristics of p-n junction.
· Reverse characteristics are plotted in the third quadrant.
· As the reverse voltage is
increased, reverse current
Reverse
increases initially but breakdown voltage (VBR)
after a small voltage – VR O
becomes constant equal A I0

P Reverse
to reverse saturation Sharp Knee I0 remains saturation
current I0. This point is increase point constant current
in current
shown as P, in the – IR
Fig. 1.13.
Fig. 1.13 Reverse characteristics of p-n junction diode
· After this, though reverse
voltage is increased, the reverse current remains constant till point A.
· At point A, reverse breakdown of the diode occurs and current increases sharply
damaging the diode. This point is called knee of the reverse characteristics.
· Reverse breakdown voltage of the p-n junction denoted as VBR.
· The complete V-I characteristics of p-n junction diode is the combination of its forward
as well as reverse characteristics. (Refer Fig. 1.2 on page 1-2)
Ø Write the diode current equation of a p-n junction and explain the V-I characteristics from it.
+ VTU : Aug.-03, 05, Marks 8, Aug.-99, 2000, 01, March-2000, 01,
Feb.-02, 04, Marks 5, Aug.-04, Marks 6, Jan.-09, Marks 8
TM

The diode current equation is,
[
I = I 0 e V / hVT - 1 ]A
V-I Characteristics from Equation of Diode :
· For a forward biased condition, the bias voltage V is considered positive and hence
exponential index has positive sign. Due to this, 1 << e V / hVT hence neglecting 1 we
get the equation for a forward current as,
If = I0 e V / hVT
· Once bias voltage exceeds cut in

V/hV
voltage, the forward current If If = I0e T
increases exponentially.
Exponential
· In reverse biased condition, the Reverse forward current
breakdown
bias voltage V is treated voltage
0
negative and due to this –V
I0
+V
Reverse saturation current (I0)
exponential index has negative
I » – I0
sign. So e - V / hVT << 1, hence
Breakdown
neglecting exponential term we region
get,
IR
aI R @ I0 (–1) @ – I0
Fig. 1.14 V-I characteristics of p-n junction diode
· Under reverse biased condition,
the current is reverse saturation current which is negative indicating that it flows in
opposite direction to that of forward current and almost constant.
Ø Draw the full wave rectifier circuit and explain its operation.
+ VTU : Aug.-07, 09, Jan.-13, Dec.-11, June-12, Marks 6
es=Esmsin wt D1
· The full wave rectifier conducts
A iL
during both positive and
negative half cycles of input a.c. +
id1
supply. EDC RL
· The full wave rectifier circuit is –
shown in the Fig. 1.15.
Operation of the Circuit : A. C. supply
es
Consider the positive half cycle of id2
ac input voltage in which terminal
Center tap B
(A) is positive and terminal (B) transformer D2
negative due to center tap Fig. 1.15 Full wave rectifier
transformer.
TM

D1, ON
· The diode D1 will be A +
forward biased and hence + Load
id1 voltage
will conduct; while diode D2 Load voltage RL
iL
will be reverse biased and
will act as an open circuit A.C.Supply
Load voltage –
and will not conduct. The
diode D1 supplies the load
–
current, i.e. iL = id1 . B D2, OFF
· In the next half cycle of ac
Fig. 1.16 Current flow during positive half cycle
voltage, polarity reverses
and terminal (A) becomes
negative and (B) positive. The diode D2 conducts, being forward biased, while D1 does
not, being reverse biased. The diode D2 supplies the load current, i.e. iL = id2 .
Load voltage
A D1, OFF
_
t
RL
iL
A.C.Supply
id2
+ Load current
B direction
D2, ON remains same
Fig. 1.17 Current flow during negative half cycle
Ø Derive the expressions for the average d.c. current, d.c. load voltage, rectifier efficiency, ripple
factor, PIV rating and ripple frequency for the full wave rectifier circuit with two diodes.
+ VTU : Feb.-01, 02, Aug.-01, 02, 03, 07, July-11, Marks 8
· Consider one cycle of the load current iL from 0 to Imsinwt
p to obtain the average value which is d.c. value of Load
current
load current.
iL = Im sin w t 0 £ wt £ p
p p t
1 1 o p 2p
pò L
· Iav = IDC = i d( wt) = ò I m sin wt dwt
p
0 0
2I m Fig. 1.18 Load current waveform

for full wave rectifier
\ I DC =
p
TM

Average DC Load Voltage (EDC) :

2I m R L 2E sm
· The d.c. load voltage is, E DC = I DC R L = =
p æ R + Rs ö
pç 1 + f ÷
è RL ø
Rf + Rs E sm
· But as Rf and Rs << RL hence << 1 and I m =
RL Rs + Rt RL
2E sm
\ E DC =
p
Rectifier Efficiency (h) :

4 2
Im R L
PDC output p2 8 RL
\ h = = =
PAC input I 2m (R f + R s + R L ) p 2 (R f + R s + R L )
2
· But if Rf + Rs << R L , neglecting it from denominator
8 RL 8
\ % h max = = ´ 100 = 81.2 %
p 2
(R L ) p2
Ripple Factor (g) :

2
é I RMS ù
Ripple factor = êI ú -1
ë DC û
· For full wave I RMS = I m 2 and IDC = 2I m p so substituting above,
2
é Im / 2 ù p2
\ Ripple factor = g = ê 2I / p ú - 1 = - 1 = 0.48
ë m û 8
Peak Inverse Voltage (PIV) :
D1 Forward Voltage
biased across
+
D1 p 2p 3p 4p
+ wt
Esm 0
– –2Esm
+ +
Esm RL Vo Voltage
– across
A B – D2 p 2p 3p 4p
– wt
0
D2
Reverse –2Esm
biased
Fig. 1.19 PIV Rating of Diodes
TM

· From Fig. 1.19, when D2 is reverse biased, point A is at – Esm with respect to ground
while point B is at + Esm with respect to ground, neglecting diode drop. Thus total
peak voltage across D2 is 2Esm.
\ PIV of diode = 2 E sm
Ripple Frequency
· The Fourier series for the load current is,
iL = i d + i d = I m é - cos 4wt Lù
2 4 4
cos 2wt -
1 2 êë p 3p 15p úû
· The lowest frequency of the ripple is 2f.
· Thus the ripple frequency in full wave rectifier is '2f" Hz.
Ø Draw the circuit of bridge rectifier and explain its operation. Give the input and output
waveforms. + VTU : Feb.-2000,04, Aug.-01, 06, July-08, Jan.-14, June-13, Marks 5
· The basic bridge rectifier circuit is shown in Fig. 1.20.
A
D4 D1
Single
phase es = Esm sin wt
50 Hz, +
A.C.Supply
D2 EDC RL
D3
–
B
Fig. 1.20 Bridge rectifier circuit
Operation of the Circuit : Consider the positive half of ac input voltage. The point A of
secondary becomes positive. The diodes D1 and D2 will be forward biased, while D3 and
D4 reverse biased. The two diodes D1 and D2 conduct in series with the load and the
current flows as shown in Fig. 1.21.
A
+ D1
A.C. supply
+
D2 RL
–
B –
Fig. 1.21 Current flow during positive half cycle

TM

· In the next half cycle, when the polarity of ac voltage reverses hence point B becomes
positive diodes D3 and D4 are forward biased, while D1 and D2 reverse biased. Now
the diodes D3 and D4 conduct is series with the load and the current flows as shown in
Fig. 1.22.
A
– Direction of
D4 load current
remains same
A.C. supply
+
D3 RL
+
B –
Fig. 1.22 Current flow during negative half cycle
· The waveforms of load current and voltage are shown in the Fig. 1.23.
(See Fig. 1.23 on next page)
Ø For a bridge rectifier, derive the expressions for the average d.c. load current, rectifier
efficiency, ripple factor and voltage regulation.
+ VTU : Feb.-03, Marks, 8, Aug.-04, Marks 10, Jan.-08, Marks 6, July-08, Marks 5
· From the equivalent circuit shown Rf
in the Fig. 1.24. In each half cycle
D1
two diodes conduct simultaneously. es = Esm sin wt
Hence maximum value of load Rs
current is,
Rf
E sm iL RL
Im = D2
R s + 2R f + R L
· The PIV rating of the diodes is E sm . Fig. 1.24

· The remaining expressions are
identical to those derived for two diode full wave rectifier.
2E sm 4
EDC = IDC RL = , PDC = I 2DC R L = I 2m R L
p p2
I 2m (2R f + R s + R L )
PAC = I 2RMS (R s + 2R f + R L ) =
2
8R L
h = , % h max = 81.2 %
p2 (R s + 2R f + RL )
g = 0.48 , T.U.F. = 0.812
TM

es
Esm
Transformer
secondary 3p
voltage p wt
0 2p
D1,D2
ON D3,D4
Current through
ON
D1,D2
Im
wt
Current through
D3,D4
Im
wt
Esm
Im=
Load i Rs+ 2Rf + RL
current L
Im
Iav = IDC
wt
Load
voltage
eL
Eav = EDC
wt
Voltage
across diode Decides PIV
rating of diode
D1
wt
0
–Esm PIV =Esm
Fig. 1.23 Waveforms of bridge rectifier
Important Solved Examples
Example 1.1 A germanium diode is used in a rectifier circuit and is operating at a temperature
of 25 ºC with a reverse saturation current of 1000 mA. Calculate the value of forward current
if it is forward biased by 0.22 V. Assume the value of h = 1 for Ge.
+ VTU : Feb.-05, Marks 8
–6
Solution : I0 = 1000 mA = 1000 ´ 10 A, h = 1, V = 0.22 V
T = 25 ºC + 273 = 298 ºC
VT = kT = 8.62 ´ 10–5 ´ 298 = 0.025 V ... k = Boltzman's constant
TM

Diode current equation,

h VT
I = I0 [e V -1] = 1000 ´ 10 -6 [e 0.22 / 1 ´ 0.025 - 1] = 6.6332 A
Example 1.2 Calculate the reverse saturation current for silicon diode which passes a current of
10 mA at 27 ºC, for a forward bias of 700 mV.
+ VTU : June-12, Marks 4
Solution : I = 10 mA, V = 700 mV, 'Si' hence h = 2, VT = 26 mV for 27 ºC
–3 /2 ´ 26 ´ 10 –3
I = I 0 [e V / hVT – 1] i.e. 10 ´ 10 –3 = I 0 [e700 ´ 10 - 1]
\ I 0 = 14.2471 nA … Reverse saturation current
Example 1.3 A half wave rectifier circuit is supplied from a 230 V, 50 Hz supply with a step
down ratio of 3:1 to a resistive load of 10 kW. The diode forward resistance is 75 W while
transformer secondary resistance is 10 W. Calculate maximum, average, RMS values of current,
D.C. output voltage, efficiency of rectification and ripple factor.
Solution : The circuit is shown
in the Fig. 1.25. Rf = 75 W
230 V, 50 Hz es Output
The given values are, 10k W
supply
iL
Rf = 75 W, RL = 10 kW, Rs = 10 W
The given supply voltages are N1: N2 is 3:1

always r.m.s. values. Fig. 1.25
E p ( RMS) = 230 V,
N1 3 N2 1
= i.e. =
N2 1 N1 3
N2 E s ( RMS)
=
N1 E p ( RMS)
1 E s ( RMS)
\ =
3 230
\ E s ( RMS) = 76.667 V
This is r.m.s. value of the transformer secondary voltage.
\ Esm = 2 E s ( RMS) = 2 ´ 76.667 = 108.423 V
E sm 108 .423
\ Im = = = 10.75 mA
Rs + Rf + RL 10 + 75 + 10 ´ 10 3
Im 10 . 75
\ Iav = IDC = = = 3.422 mA
p p
TM

Im 10 . 75
I RMS = for half wave = = 5.375 mA
2 2
EDC = D.C. output voltage = IDC RL = 3 . 422 ´ 10 -3 ´ 10 ´ 10 3 = 34.22 V
PDC = D.C. output power = EDC IDC = 34.22 ´ 3.422 ´ 10 -3 = 0.1171 W

This also can be obtained as,
I 2m (10 . 75 ´ 10 -3 ) 2
PDC = RL = ´ 10 ´ 10 3 = 0.1171 W
p2 p2
PAC = A.C. input power = I 2RMS[R s + R f + R L ]
= (5.375 ´ 10 -3 ) 2 [10 + 75 + 10 ´ 10 3 ] = 0.2913 W
PDC 0.1171
\ %h = ´ 100 = ´ 100 = 40.19 %
PAC 0.2913
The ripple factor is constant for half wave rectifier and is 1.21.
\ g = 1.21
Example 1.4 In a full wave rectifier, the input is from a 30 - 0 - 30 V transformer. The load
and diode forward resistance are 100 W and 10 W respectively. Calculate the average voltage,
rectification efficiency and percentage regulation.
+ VTU : Aug.-07, March-01, Marks 7
Solution : Transformer is 30 - 0 - 30 V.
It is full wave rectifier with input from center tap transformer. So r.m.s. value of secondary
across each half of secondary is 30 V
\ E sm = 2 ´ 30 = 42.4264 V and R f = 10 W, RL = 100 W
E sm 42.4264
Im = = = 0.3856 A
Rf + RL (100 + 10)
2 I m 2 ´ 0.3856
\ I DC = = = 0.2455 A
p p
\ E DC = I DC R L = 0.2455 × 100 = 24.55 V
PDC = I 2DC R L = 6.027 W
2
æI ö
PAC = I 2RMS (R f + R L ) = ç m ÷ (R f + R L ) = 8.1778 W
è 2ø
P 6.027
\ % h = D.C. × 100 = ´ 100 = 73.69 %
PA.C. 8.1778
VNL - VFL
% Regulation = × 100
VFL
2 2
VDC no load = VNL = ´ E sm = ´ 42.4264 = 27.0094 V
p p
TM

VDC full load = VFL = I DC ´ R L = 0.2455 ´ 100 = 24.55 V

27.0094 - 24.55
% Regulation = × 100 = 10.016 %
24.55
Example 1.5 A 5 kW load is fed from a bridge rectifier connected across a tranformer secondary
whose primary is connected to 460 V, 50 Hz supply. The ratio of number of primary turns to
secondary turns is 2:1.
Calculate d.c. load current, d.c. load voltage, ripple voltage and P.I.V. rating of diode.
Solution : R L = 5 kW = 5 ´ 10 3 W, N1 : N2 is 2:1, E p = 460 V RMS value
Es N2 1 1
\ = = i.e. E s = ´ E p = 230 V
Ep N1 2 2
\ E sm = 2 ´ E s = 230 ´ 2 = 325.269 V.
2 Im E sm
now I DC = where I m = neglecting R f .
p RL
2 E sm 2 ´ 325.269
\ I DC = = = 41.41 mA
p RL p ´ 5 ´ 103
D.C. load voltage E DC = I DC ´ R L = 41.41 ´ 10 –3 ´ 5 ´ 10 3 = 207.072 V
Ripple voltage = Ripple factor ´ VDC

Ripple factor for bridge rectifier is 0.482.
\ Ripple voltage = 0.482 ´ 207.072 = 99.8 V
P.I.V. rating of each diode = E sm for bridge rectifier = 325.27 V
Example 1.6 In a full wave bridge rectifier, the transformer secondary voltage is 100 sin wt. The
forward resistance of each diode is 25 W and the load resistance is 950 W. Calculate
i) D.C. output voltage ii) Ripple factor
iii) Efficiency of rectification and iv) P.I.V. across non-conducting diode
+ VTU : Aug.-2000, Feb.-03, Marks 6
Solution : E s = 100 sin wt V, R f = 25 W, R L = 950 W
Comparing E s with E s = E m sin w t,
Esm = 100 V
E sm
i) Im = ... R s = 0 W
2R f + R L
100
= = 0.09523 A = 95.238 mA
2 ´ 50 + 950
2 Im 2 ´ 0.09523
\ I DC = = = 0.0606 A = 60.63 mA
p p
TM

\ E DC = I DC R L = 0.0606 ´ 950 = 57.5985 V

2
éI RMS ù
ii) Ripple factor = êI ú -1
ë DC û
Im 0.09523
I RMS = = = 0.06734 A
2 2
2
Ripple factor = é 0.06734 ù - 1 = 0.4834
ëê 0.06063 ûú
2
iii) P = I DC R L = ( 0.0606) 2 ´ 950 = 3.4921 W
DC
P = I 2RMS (2 R f + R L ) = ( 0.06734) 2 ´ ( 2 ´ 50 + 950 ) = 4.7614 W

DC
PDC 3.4921
\ %h = ´ 100 = ´ 100 = 73.3417 %
PAC 4.7614
iv) P.I.V. rating = E sm for bridge rectifier = 100 V
Example 1.7 In a F.W.R. with a capacitor filter, the load current from the circuit operating from
230 V, 50 Hz supply is 10 mA. Estimate the value of capacitor required to keep the ripple
factor less than 1 %. + VTU : July-04, Marks 8
Solution :
Given, Es(rms) = 230 V, f = 50 Hz, IL = 10 mA, g = 1 % = 0.1.
Esm = 2 E s (rms) = 2 ´ 230 = 325.269 V
E DC 2E sm
RL = and EDC = for full wave
IL p
2E sm 2 ´ 325.269
\ RL = i.e. RL = = 20.7 k W
pI L p ´ 10 ´ 10 -3
1 1
To find capacitor value, g= i.e. 0.01 =
4 3f C R L 4 3 ´ 50 ´ C ´ 20.7 ´ 10 +3
C = 13.94 mF
Example 1.8 A full-wave bridge rectifier supplies a load of 400 W in parallel with a capacitor of
500 mF. If the a.c. supply voltage is 230 sin 314t V, find the
i) Ripple factor and ii) D. C. load current. + VTU : Feb.-07, Marks 6
Solution : Comparing given voltage with v = Vm sin wt,
Vm = 230 V, w = 314 rad/sec
\ E sm = Vm = 230 V ... As directly applied to rectifier
R L = 400 W, C = 500 mF
w 314
w = 2pf i.e. f = = » 50 Hz
2p 2p
TM

1 1
i) g = = = 0.01443
4 3 f CR L 4 3 ´ 50 ´ 500 ´ 10 - 6 ´ 400
ii) Output voltage with filter is,
E
E DC = E s m - I DC é
1 ù
and I DC = DC
êë 4 fC úû RL
I DC R L = E s m - I DC é
1 ù
\
êë 4fC úû
é 1 ù
\ I DC ´ 400 = 230 - I DC ê
-6ú
ë 4 ´ 50 ´ 500 ´ 10 û
\ I DC = 0.5609 A
Example 1.9 For a zener regulator shown in

R
the Fig. 1.26, calculate the range of input I IL +
2.2 k W IZ
voltage for which output will remain Constant
constant. Vin 1 kW R L Vo = V z
VZ = 6.1 V, IZmin = 2.5 mA, IZmax = 25

–
mA, rZ = 0 W
Fig. 1.26
Solution :
RL = 1 kW, VZ = 6.1 V
VZ 6 .1
\ IL = = = 6.1 mA constant
RL 1 ´ 10 3
For Vin(min), IZ = IZmin = 2.5 mA

\ I = IZmin + IL = 2.5 +6.1 = 8.6 mA
\ Vin(min) = VZ + IR = 6.1 + 8 . 6 ´ 10 -3 ´ 2 . 2 ´ 10 3 = 25.02 V
For Vin(max), IZ = IZmax = 25 mA

\ I = IZmax + IL = 25 + 6.1 = 31.1 mA
\ Vin(max) = VZ + IR = 6.1 + 31 . 1 ´ 10 -3 ´ 2 . 2 ´ 10 3 = 74.52 V
Thus the range of input voltage is 25.02 V to 74.52 V, for which output will be constant.
Example 1.10 A zener diode has a breakdown voltage of 10 V. It is supplied from a voltage
source varying between 20 - 40 V in series with a resistance of 820 W. Using an ideal zener
model obtain the minimum and maximum Zener currents.
+ VTU : Aug.-09, Jan.-14 Marks 8
TM

Solution : The circuit is shown in the Fig. 1.27.

R = 820 W Vo
IL
I
Vin
RL Vo = Vz = 10 V
20 - 40 V
IZ
Fig. 1.27
Vin - Vo
I =
R
Vin -10
\ I =
820
Vin (max) - 10 40 - 10
I max = = = 36.585 mA
820 820
I Z min = 0 A ...For ideal Zener diode
Now I = IZ +IL
\ I max = I Zmin + I L (max )
\ I L (max) = I max = 36.585 mA
when IL = IL (min) = 0 A ... Open load terminals
under this condition if Vin = Vin (max) then,
I = 36.585 mA
and IZ = IZmax = 36.585 mA
Multiple Choice Questions with Answers
Introduction to P-N Junction
Q.1 A p-n junction forms a popular semiconductor device called _____.

(a) rectifier (b) regulator (c) diode (d) triode (Ans. : c)
Theory of P-N Junction
Q.1 The charge movement due to nonuniform doping is called ____.

(a) convection (b) diffusion (c) radiation (d) displacement
(Ans. : b)
Q.2 In a step graded junction, there is __________ change in the concentrations of charge
carriers.
(a) abrupt (b) gradual (c) zero (d) none of these
(Ans. : a)
TM

Q.3 There are no _________ in the space charge region.

(a) atoms (b) charge carriers (c) magnetic charge (d) electronic charge
(Ans. : b)
Q.4 The depletion region penetrates more on the ______ doped region.
(a) lightly (b) heavily (c) equally (d) none of these
(Ans. : a)
Q.5 Due to diffusion large number of _____ are formed near the junction on p-side.
(a) negatively charged immobile ions. (b) positively charged immobile ions.
(c) negatively charged charge carriers. (d) positively charged charge carriers.
(Ans. : a)
Q.6 Due to diffusion, large number of _____ are formed near the junction on n-side.
(a) negatively charged immobile ions.
(b) positively charged immobile ions.
(c) negatively charged charge carriers.
(d) positively charged charge carriers.
(Ans. : b)
Q.7 The physical distance from one side to other side of the depletion region is called _____
of depletion region.
(a) height (b) width (c) depth (d) none of these
(Ans. : b)
Q.8 Practically width of the depletion region is of the order of _____.
(a) few nm (b) few mm (c) few cm (d) few mm
(Ans. : d)
Q.9 The potential difference across the p-n junction is called _____.
(a) barrier potential (b) photovoltaic potential
(c) cut-out voltage (d) none of these
(Ans. : a)
Q.10 The barrier potential of silicon diode is about _____ volts.
(a) 0.8 (b) 0.7 (c) 0.6 (d) 0.2
(Ans. : c)
Q.11 The barrier potential of germanium diode is about _____ volts.
(a) 0.8 (b) 0.7 (c) 0.6 (d) 0.2
(Ans. : d)
Q.12 The junction voltage decreases at a rate of ___________ for Si and Ge diodes.
(a) 0.7 V/ ºC (b) 2.5 mV/ ºC (c) 0.2 V/ ºC (d) none of these
(Ans. : b)
Q.13 _________ does not affect the barrier potential of a diode.
(a) Type of semiconductor material (b) Forward voltage
(c) Temperature (d) Level of doping
(Ans. : b)
TM

The P-N Junction Diode
Q.1 The contact between metal and heavily doped semiconductor is called _____.
(a) resistive contact (b) permanent contact
(c) ohmic contact (d) diffused contact
(Ans. : c)
Q.2 The device having two electrodes is called ________.
(a) transistor (b) diode (c) rectifier (d) none of these
(Ans. : b)
Q.3 A device which allows the current flow in one direction but does not allow it in the
opposite direction is called ________.
(a) transistor (b) filter (c) regulator (d) rectifier
(Ans. : d)
Q.4 The p-region in a diode acts as ______.
(a) cathode (b) electrode (c) anode (d) none of these
(Ans. : c)
Q.5 The n-region in a diode acts as _____.
(a) cathode (b) electrode (c) anode (d) none of these
(Ans. : a)
Q.6 Applying external voltage to any electronic device is called ______.
(a) powering (b) biasing (c) adjusting (d) none of these
(Ans. : b)
Q.7 The forward current capacity of a low current diode is _____.
(a) upto 200 mA (b) upto 500 mA (c) upto 1 A (d) upto 100 mA
(Ans. : d)
Q.8 The arrowhead in the diode symbol points the direction of ________ current .
(a) forward (b) reverse (c) electron (d) none of these
(Ans. : a)
Q.9 The ________current flows from cathode to anode in a diode.
(a) forward (b) reverse (c) conventional (d) none of these
(Ans. : b)
Q.10 The barrier potential of a silicon p-n junction is approximately.
a) 0.3 V b) 0.1 V c) 0.7 V d) 1.2 V.
+ VTU : Aug.-09
(Ans. : c)
Forward Biasing of Diode
Q.1 Which of the following is a forward biased diode ?

R
(a) (b) (c) (d) none of these
+ – (Ans. : c)
– + – +
V V
V
TM

Q.2 Due to forward biasing, the depletion region ______.

(a) widens (b) narrows (c) completely vanishes (d) none of these
(Ans. : b)
Q.3 Forward biasing means connecting n terminal of diode to ______.
(a) +ve of battery (b) –ve of battery (c) ground (d) none of these
(Ans. : b)
Q.4 The reciprocal of the slope of the forward characteristics is called ______.
(a) reverse resistance (b) static resistance
(c) saturation resistance (d) dynamic resistance
(Ans. : d)
Q.5 _________ represents an ideal diode in the conducting state. + VTU : June-13
(a) A closed switch (b) A resistor (c) A capacitance (d) An open switch
(Ans. : c)
Q.6 When forward-biased, a diode _______.
(a) blocks current (b) conducts current
(c) has a high resistance (d) drops a large voltage
(Ans. : b)
Reverse Biasing of Diode

Q.1 Reverse biasing means connecting n terminal of diode to ______.
(a) +ve of battery (b) –ve of battery (c) ground (d) none of these
(Ans. : a)
Q.2 The voltage at which breakdown of diode occurs is called ______.
(a) peak inverse voltage (b) average voltage
(c) reverse breakdown voltage (d) valley voltage
(Ans. : c)
Q.3 In the reverse breakdown region, the power dissipation is _____________.
(a) very high (b) very low (c) zero (d) none of these
(Ans. : a)
Q.4 Pulling of electrons from bonds due to intense electric field is called ______.
(a) zener effect (b) hall effect (c) avalanche effect (d) early effect
(Ans. : a)
Q.5 The diode gets damaged when operated in reverse breakdown region due to excessive
_________.
(a) voltage (b) current
(c) power dissipation (d) none of these
(Ans. : c)
Q.6 In p-n diode, as reverse bias voltage increases, the reverse saturation current _____.
(a) decreases (b) remains constant
(c) increases (d) none of these
(Ans. : b)
TM

Q.7 With increase in the reverse bias, the width of the depletion region _________.
(a) decreases (b) remains constant (c) increases (d) none of these
(Ans. : c)
Q.8 The reverse current flows due to _____ charge carriers.
(a) majority (b) minority (c) mobile (d) none of these
(Ans. : b)
Q.9 The reverse current does not depend upon _____.
(a) reverse voltage (b) reverse resistance
(c) temperature (d) none of these
(Ans. : a)
Q.10 For the normal p-n junction, reverse breakdown voltage is greater than ______.
(a) 25 V (b) 30 V (c) 50 V (d) 100 V
(Ans. : c)
Q.11 Reverse breakdown voltage for silicon diode is ______ that of the germanium diode of
comparable rating.
(a) less than (b) higher than (c) equal to (d) none of these
(Ans. : b)
Q.12 _________ represents an ideal diode in the off state.
(a) A closed switch (b) A resistor (c) A capacitance (d) An open switch
(Ans. : d)
Q.13 In reverse bias the diode can be represented as ________. + VTU : Aug.-09
(a) open circuit (b) short circuit
(c) a battery of 0.7 V (d) a current source with constant current.
(Ans. : a)
V-I Characteristics of Diode
Q.1 The normal forward biased operation of the diode is above the ______ of the
characteristics.
(a) cut-in point (b) Q point (c) breakdown point (d) knee point
(Ans. : d)
Q.2 The forward characteristics are plotted in ______ quadrant.
(a) first (b) second (c) third (d) fourth
(Ans. : a)
Q.3 The reverse characteristics are plotted in ______ quadrant.
(a) first (b) second (c) third (d) fourth
(Ans. : c)
Q.4 The forward resistance of the diode is ______.
(a) high (b) infinite (c) zero (d) very low
(Ans. : d)
Q.5 The ideal value of reverse resistance of the diode is ______.
(a) high (b) infinite (c) zero (d) very low
(Ans. : b)
TM

Q.6 The breakdown voltage of Si diode is _________ than that of the Ge diode.
(a) less (b) greater (c) same as (d) none of these
(Ans. : b)
Q.7 The reverse saturation current in silicon diode is of the order of _______.
(a) few microamperes (b) few nA
(c) few mA (d) none of these
(Ans. : c)
Q.8 The reverse saturation current in germanium diode is of the order of _________.
(a) few mA (b) few mA (c) few nA (d) none of these
(Ans. : b)
Q.9 A __________ is used to check the faulty diode.
(a) voltmeter (b) ammeter (c) oscilloscope (d) none of these
(Ans. : c)
Q.10 The resistance of a diode under d.c. conditions is called _______ resistance.
(a) constant (b) dynamic (c) static (d) none of these
(Ans. : c)
Q.11 The Knee voltage of a silicon diode is __________ volts. + VTU : June-13, Jan.-14
(a) 0.3 V (b) 0.5 V (c) 0.7 V (d) none of these
(Ans. : c)
Q.12 The voltage at which forward current through the diode starts increasing rapidly is called
as _________ . +
VTU : Dec.-11
(a) saturation voltage (b) breakover voltage
(c) cut in voltage (d) cut off voltage.
(Ans. : c)
Diode Current Equation and Nature of Characteristics
Q.1 The missing term in the forward diode current equation is ________.
[
I F = I 0 eV / VT - 1]
(a) VR (b) h (c) VS (d) e
(Ans. : b)
Q.2 The value of h = ______ for germanium.
(a) 2 (b) 4 (c) 1 (d) 0
(Ans. : c)
Q.3 The total forward voltage drop across a silicon diode is _____.
(a) 0.8 V (b) 0.5 V (c) 0.7 V (d) 0.3 V
(Ans. : c)
Q.4 The total forward voltage drop across germanium diode is _____.
(a) 0.8 V (b) 0.5 V (c) 0.7 V (d) 0.3 V
(Ans. : d)
TM

Q.5 The value of h = _________ for silicon.

(a) 2 (b) 4 (c) 1 (d) 0
(Ans. : a)
Q.6 The factor h is called ______.
(a) reflection coefficient (b) refraction coefficient
(c) recombination index (d) emission coefficient
(Ans. : d)
Q.7 The value of VT = _____ at 300 ºK.
(a) 26 mV (b) 30 mV (c) 15 mV (d) 5 mV
(Ans. : a)
Q.8 The VT is expressed as ______.
k qk T
(a) kT (b) (c) (d)
T T qk
(Ans. : a)
Q.9 In VT = kT, the k is _____.
(a) Hall coefficient (b) Planck's constant
(c) Maxwell's constant (d) Boltzmann's constant
(Ans. : d)
Q.10 The unit of Boltzmann's constant is ______.
(a) eV / º C (b) º C kg eV (c) eV / º K (d) eV
(Ans. : c)
Q.11 The value of VT at 40 º C is ______.
(a) 26 mV (b) 26.98 mV (c) 29.1 mV (d) 25.9 mV
(Ans. : b)
Q.12 The forward current for Ge diode at room temperature for a forward voltage of 0.3 V is
______.
(a) 1 mA (b) 1.098 mA (c) 2.188 mA (d) 0.1091 mA
(Ans. : d)
Q.13 The missing terms in the forward diode current is I F = Io [eV VT – 1] _________ .
+ VTU : Jan.-14
(a) VR (b) h (c) VS (d) e
(Ans. : b)
D.C. Load Line of Diode
Q.1 The slope of the d.c. load line is _______ the load resistance.
(a) equal to (b) twice (c) reciprocal (d) none of these
(Ans. : c)
Q.2 The intersection of the d.c. load line with x-axis is ________.
(a) output voltage (b) supply voltage (c) diode drop (d) none of these
(Ans. : b)
TM

Rectifiers
Q.1 A device converting a.c. to d.c. is called _____.

(a) inverter (b) comparator (c) rectifier (d) regulator
(Ans. : c)
Q.2 A device which allows the current flow in one direction but does not allow it in the
opposite direction is called _______. VTU : Jan.-13 +
(a) transistor (b) filter (c) regulator (d) rectifier
(Ans. : d)
Half Wave Rectifier

Vo
Q.1 The output voltage waveform of Fig. 1.28 corresponds to a
___ rectifier.
(a) negative FWR (b) positive FWR 0 p 2p t
(c) negative HWR (d) positive HWR

(Ans. : d) Fig. 1.28
Q.2 In half wave rectifier, the diode conducts for ______ of the input a.c. voltage cycle.
(a) 180º (b) 0º (c) 360º (d) 270º
(Ans. : a)
Q.3 For a half wave rectifier IDC = _________.
I 2I Im
(a) m (b) m (c) p Im (d)
2p p p
(Ans. : d)
Q.4 For a half wave rectifier I RMS = __________.
Im Im
(a) Im (b) (c) (d) 2 Im
2 2
(Ans. : b)
Q.5 The maximum efficiency of half wave rectifier is ______.
(a) 40.6 % (b) 60.4 % (c) 78.5 % (d) 81.2 %
(Ans. : a)
Q.6 The ripple factor of half wave rectifier is ______. + VTU : June-13
(a) 1.4 (b) 0.48 (c) 1.211 (d) 1.71
(Ans. : c)
Q.7 PIV rating of diode in half wave rectifier is ______.
Esm
(a) 2 Esm (b) Esm (c) (d) none of these.
2p
(Ans. : b)
Q.8 The peak current I m in a HWR is ____.
Em Em Em Em
(a) (b) (c) (d)
Rs + Rf + 2RL 2 Rs + Rf + RL RL Rs + Rf + RL
(Ans. : d)
TM

Q.9 The a.c. power input to a HWR is ____.

I 2m ´ (RL + Rf + Rs) I 2m ´ (2RL + Rf + Rs)
(a) (b)
4 4
I 2m ´ (RL + 2Rf + Rs) I 2m ´ (RL + Rf + Rs)
(c) (d)
2 2
(Ans. : a)
Q.10 The r.m.s. current in half wave rectifier is ____.
Im 2 Im Im Im
(a) (b) (c) (d)
2p p 2 2 + VTU : Jan.-11, July-11
(Ans. : c)
Q.11 The ripple frequency in a HWR is ____ Hz.
(a) 50 (b) 100 (c) 200 (d) 0
(Ans. : a)
Q.12 If the r.m.s. secondary voltage to half wave rectifier is 22.2144 V then its output voltage is
____.
10
(a) 20 V (b) 10 V (c) 10 2 V (d)
p
(Ans. : b)
Q.13 For having the ideal voltage regulation for a half wave rectifier, ____.
(a) RL = 0 (b) Rf = 0 (c) (Rs + Rf ) = 0 (d) none of these
(Ans. : c)
Q.14 In a power supply, the ripple factor is defined as ___.
2
é I 2RMS ù é I RMS ù é I 2RMS ù
(a) ê 2 ú -1 (b) -1 (c) ê 2 - 1ú (d) none of these
êë I DC úû ëê I DC ûú êë I DC úû
(Ans. : a)
Q.15 A half wave rectifier is fed from secondary of a transformer whose output voltage is
12.6 V. The DC voltage of the rectifier output is ----------.
(a) 12.6 V (b) 5.66 V (c) 17.8 V (d) 11.32 V
(Ans. : b)
Q.16 The average output voltage of half wave rectifier with an input of 300 sin 314t is
___________ .
(a) 100 V (b) 95.49 V (c) 90.49 V (d) 90.0 V
(Ans. : b)
Q.17 PIV in case of half wave rectifier for an input signal of Vm sin w t is _______.
+ VTU : June-12
V V
(a) Vm (b) 2Vm (c) m (d) m
2 2
(Ans. : a)
TM

Full Wave Rectifier
Q.1 The peak current I m in a FWR is ____.

Em Em Em Em
(a) (b) (c) (d)
Rs + Rf + 2RL 2 Rs + Rf + RL RL Rs + Rf + RL
(Ans. : d)
Q.2 The a.c. power input to a FWR is ____.
(a) (b)
4 4
(c) (d)
2 2
(Ans. : d)
Q.3 The r.m.s. current in full wave rectifier is ____.
Im 2 Im Im Im
(a) (b) (c) (d)
2p p 2 2
(Ans. : d)
Q.4 The ripple frequency in a FWR is ____ Hz.
(a) 50 (b) 100 (c) 200 (d) 0
(Ans. : b)
Q.5 The percentage of a.c. component in the rectifier output is measured by _____.
(a) ripple factor (b) regulation (c) TUF (d) load resistance
(Ans. : a)
Q.6 In full wave rectifier, the diode conducts for ______of the input a.c. voltage cycle.
(a) 180º (b) 0º (c) 360º (d) 270º
(Ans. : c)
Q.7 For a full wave rectifier IDC = _________.
Im 2Im Im
(a) (b) (c) p Im (d)
2p p p
(Ans. : d)
Q.8 For a full wave rectifier I RMS = _______.
Im Im
(a) Im (b) (c) (d) 2 Im
2 2
(Ans. : c)
Q.9 The maximum efficiency of full wave rectifier is ______. + VTU : Jan.-14
(a) 40.6 % (b) 60.4 % (c) 78.5 % (d) 81.2 %
(Ans. : d)
Q.10 The ripple factor of full wave rectifier is ______. + VTU : Jan.-13
(a) 1.4 (b) 0.48 (c) 1.211 (d) 1.71
(Ans. : b)
Q.11 PIV rating of diode in full wave rectifier is ______.
Esm
(a) 2 Esm (b) Esm (c) (d) none of these
2p
+ VTU : Jan-11
(Ans. : a)
TM

Q.12 The ideal value of voltage regulation is _____.

(a) 0 (b) ¥ (c) very high (d) none of these
(Ans. : b)
Q.13 Ideally the ripple factor should be _____.
(a) ¥ (b) 0 (c) 100 (d) none of these
(Ans. : b)
Q.14 The ideal value of the rectifier efficiency is _____.
(a) ¥ (b) 0 (c) 100 (d) none of these
(Ans. : c)
Q.15 The two secondary voltages of a centre tap transformer are _____.
(a) equal magnitude and 180º shifted in phase
(b) equal magnitude and 90º phase shifted
(c) equal magnitude and 0º phase shifted
(d) none of these
(Ans. : a)
Q.16 The expression for load regulation of a full wave rectifier is ______.
RL Rs + Rf Rs
(a) (b) (c) (d) none of these
Rs + Rf RL RL + Rf
(Ans. : b)
Q.17 The peak current I m of a full wave rectifier is ___ as that of a half wave rectifier if all the
parameters of diode, load and transformer are identical.
(a) half (b) twice (c) four times (d) same
(Ans. : d)
Q.18 The ripple factor of a power supply means a measure of ______.
(a) a.c. component of output waveform (b) amplitude of output waveform
(c) shape of output waveform (d) frequency of output waveform
(Ans. : a)
Q.19 The average load current of a full wave rectifier is ___ as that of half wave rectifier.
(a) twice (b) half (c) four times (d) same
(Ans. : a)
Q.20 The average output voltage of a full wave rectifier is ____ as that of half wave rectifier.
(a) four times (b) half (c) twice (d) same
(Ans. : c)
Q.21 The TUF indicates ___.
(a) efficiency of transformer.
(b) how effectively the transformer is utilized.
(c) regulation of transformer.
(d) loading of transformer.
(Ans. : b)
TM

Q.22 TUF is defined as the ratio of ___.

(a) d.c. output power to a.c. power rating of the transformer.
(b) a.c. input power to d.c. output power.
(c) d.c. output power and a.c. input power.
(d) a.c. power rating of the transformer to d.c. output power.
(Ans. : a)
Q.23 While selecting a diode for a rectifier circuit, the important voltage specification that is
considered is ____.
(a) junction potential (b) supply voltage
(c) reverse breakdown voltage (d) PIV
(Ans. : d)
Q.24 The efficiency of full wave rectifier is about __________ %.
(a) 40.6 (b) 0.46 (c) 1.21 (d) 81.2
(Ans. : d)
Q.25 If frequency of input is 60 Hz for a fullwave rectifier, the frequency of ripple is ________.
(a) 30 Hz (b) 60 Hz (c) 120 Hz (d) 180 Hz
(Ans. : c)
Q.26 If peak to peak voltage is 4 V then RMS voltage is _________.
(a) 2 Volts (b) 2 Volts (c) 2.82 Volts (d) both (A) and (C)
(Ans. : a)
Q.27 The rms value of a load current in case of a full wave rectifier is _______.
p Im Im Im
(a) (b) (c) (d)
2 2 2 p
(Ans. : c)
Bridge Rectifier
Q.1 The peak current Im in a bridge rectifier is ____.

Em Em Em Em
(a) (b) (c) (d)
Rs + Rf + 2RL Rs + 2 Rf + RL RL Rs + Rf + RL
(Ans. : b)
Q.2 The a.c. power input to a bridge rectifier is ____.
(a) (b)
4 4
(c) (d)
2 2
(Ans. : c)
Q.3 In a bridge rectifier, ______ diodes conduct in each half cycle.
(a) one (b) three (c) four (d) two
(Ans. : d)
TM

Q.4 PIV rating of a diode in a bridge rectifier is ______.

Esm
(a) Esm (b) 2Esm (c) (d) p Esm
p
+ VTU : July-11
(Ans. : a)
Q.5 The no load condition implies that _____.
(a) I L = ¥ (b) RL = 0 (c) RL = ¥ (d) none of these
(Ans. : c)
Q.6 In a bridge rectifier, the nput is from 230 V, 50 Hz; the DC output voltage is
(a) 200V (b) 207V (c) 315V (d) 220V + VTU : Jan.-11
(Ans. : b)
Q.7 The transformer utilization factor of a bridge type full wave rectifier is _______ .
(a) 0.287 (b) 0.812 (c) 0.864 (d) 0.48 (Ans. : b)
Capacitor Input Filter (C Filter)
Q.1 For a full wave rectifier with capacitor filter diode conducts for ___ half cycle.
(a) more than (b) less than (c) equal to (d) none of these
(Ans. : b)
Q.2 If looking from rectifier side, the first element in the filter is a capacitor then it is called
______ filter.
(a) choke input (b) capacitor (c) p (d) RC
(Ans. : b)
Q.3 If capacitor value increases in a capacitor filter then the ripple factor ______.
(a) increases (b) becomes zero (c) decreases (d) none of these
(Ans. : c)
Q.4 The ripple factor for the capacitor filter is _____ for full wave rectifier.
1 1 1 1
(a) (b) (c) (d)
4 3 f C RL 2fCRL 2pfCRL pfCRL
(Ans. : a)
Q.5 The filter removes _____ to obtain pure d.c.
(a) ripples (b) interference (c) noise (d) hum
(Ans. : a)
Q.6 In a filter circuit _____ is always connected in series with the load.
(a) capacitor (b) resistor (c) inductor (d) none of these
(Ans. : c)
Q.7 In a filter circuit _____ is always connected in parallel with the load.
(a) capacitor (b) resistor (c) inductor (d) none of these
(Ans. : a)
Q.8 The ripple factor _____ as the value of filter capacitor increases.
(a) remains same (b) decreases (c) increases (d) none of these
(Ans. : b)
TM

Q.9 The capacitor filter is suitable for ____.

(a) heavier loads (b) constant loads (c) lighter loads (d) none of these
(Ans. : b)
Q.10 In Fig. 1.29 a diode in full wave rectifier with capacitor A C
filter turns on at a point ___. B
(a) A (b) O
0 t
(c) B (d) C
(Ans. : c) Fig. 1.29
Q.11 A ____ type of capacitor is generally used as a filter.
(a) electrolytic (b) mica (c) polysterene (d) none of these
(Ans. : a)
Q.12 In the capacitor filter a resistance is used in series with C for :
(a) increasing efficiency (b) reducing surge current
(c) reducing the oscillations
(Ans. : b)
Q.13 The output voltage of a rectifier with filter at no load is :
(a) 2Vm (b) Vm 2 (c) Vm (d) none of these
(Ans. : c)
Q.14 The average output voltage of a capacitor filter with a full wave or bridge rectifier
is _______.
V I 4 f I DC I
(a) Esm - DC (b) Esm - DC (c) Esm - (d) Esm - DC
4fC 4fC C 2fC
(Ans. : b)
Q.15 The average output voltage of a capacitor filter with a half wave is _______.
VDC I DC 4 f I DC I DC
(a) Esm - (b) Esm - (c) Esm - (d) Esm -
4fC 4fC C 2fC
(Ans. : d)
Q.16 A bridge rectifier uses a capacitor of 100 mF as a filter with a load resistance of 1 kW . Its
ripple factor for frequency of 50 Hz is _____.
(a) 0.0288 (b) 0.288 (c) 0.144 (d) 0.0144
(Ans. : a)
Q.17 Smaller the ripple factor, the output will have higher _____components.
+ VTU : Dec.-11
(a) a.c. (b) d.c. (c) both a.c. and d.c. (d) pulse
(Ans. : b)
Power Supply Performance
Q.1 The output voltage of a zener regulator is equal to ____.

(a) VZ - I R (b) I Z max ´ rZ (c) VZ (d) none of these
(Ans. : c)
TM

Q.2 The output voltage of zener regulator shown is _____.
10 kW
20 V 2 kW
6V
(a) 20 V (b) 12 V (c) 6 V (d) 15 V

(Ans. : c)
Q.3 The maximum value of zener current in the circuit shown is ______.
2 kW
+
12 V
30-80 V 10 kW
–
(a) 1.2 mA (b) 32.8 mA (c) 35.2 mA (d) None of these

(Ans. : b)
Q.4 The minimum value of zener current in the above circuit is ____.
(a) 7.8 mA (b) 9 mA (c) 10.2 mA (d) none of these
(Ans. : a)
Q.5 Zener diode used as a voltage regulator when it is __________ biased.
(a) Forward (b) Reverse (c) Unbiased (d) None of these.
(Ans. : b)
Q.6 Zener diode regulates only when it is connected in ______ mode.
(a) Forward bias (b) Reverse bias (c) short (d) Open.
+ VTU : July-11
(Ans. : b)
Zener Diode as a Shunt Regulator
Q.1 Dynamic zener resistance is _________ in reverse breakdown condition.

+ VTU : Dec.-11
(a) very high (b) high (c) zero (d) very small
(Ans. : d)
Q.2 The zener power dissipation is given by the product of _______. + VTU : Jan.-13
(a) VR , IZ (b) VF , IZ (c) VZ IZ (d) none of these
(Ans. : c)
TM

Q.3 The zener diode is mainly used in _________ . + VTU : Jan.-14

(a) Comparator (b) Regulator (c) Multivibrator (d) None of these
(Ans. : b)
Clipper Circuits or Limiters
Q.1 The circuits used to remove unwanted portion of waveform without distorting the remaing
part are called _____.
(a) clippers (b) clampers (c) d.c. restorers (d) filters
(Ans. : a)
Q.2 ______ is the simplest type of clipper.
(a) Filter (b) Half wave rectifier (c) Chopper (d) Integrator
(Ans. : b)
Q.3 The clipper circuits are also called ______.
(a) filters (b) rectifiers (c) limiters (d) integrators
(Ans. : c)
Q.4 ______ is main element of a clipper.
(a) Diode (b) Transistor (c) Zener (d) Inductor
(Ans. : a)
Series Clippers
Q.1 In a series clipper, ________ is connected in series with the load.

(a) diode (b) inductor (c) transistor (d) capacitor
(Ans. : c)
Q.2 A negative clipper clips off ________ portion of the input waveform.
(a) positive (b) negative (c) peak (d) none of these
(Ans. : a)
Q.3 A positive clipper clips off ________ portion of the input waveform.
(a) positive (b) negative (c) peak (d) none of these
(Ans. : c)
Q.4 In a series clipper, for a clipping region, the diode must be in ________ condition.
(a) forward biased (b) reverse biased (c) none of these
(Ans. : b)
Q.5 In a series clipper, for a transmitting region, the diode must be in ________ condition.
(a) forward biased (b) reverse biased (c) none of these
(Ans. : c)
Q.6 In a series clipper, the slope of the transfer characteristics in transmitting region is ______ .
(a) zero (b) unity (c) infinite (d) negative
(Ans. : a)
Q.7 In a series clipper, the slope of the transfer characteristics in clipping region is ________ .
(a) zero (b) unity (c) infinite (d) negative
(Ans. : c)
TM

Q.8 In a series clipper, when diode is OFF, it produces ______ region of the clipper.
(a) transmitting (b) clipping (c) linear (d) none of these
(Ans. : b)
Q.9 In a series clipper, when diode is ON, it produces ______ region of the clipper.
(a) transmitting (b) clipping (c) linear (d) none of these
(Ans. : a)
Q.10 The graph of output variable against input variable is called ______ characteristics of the
circuit.
(a) linear (b) nonlinear (c) transfer (d) V-I
(Ans. : c)
Shunt or Parallel Clippers

Q.1 In a ________ clipper, a diode is connected in parallel with the load.
(a) series (b) combinational (c) parallel (d) two way
(Ans. : c)
Q.2 In a parallel clipper, Vo = Vin can be obtained in transmitting region by making ________.
(a) R1 >> RL (b) R1 = RL (c) R1 << RL (d) None of these
(Ans. : c)
Q.3 In a parallel clipper, the slope of the transfer characteristics in transmitting region is _____.
(a) unity (b) zero (c) depends on RL and R1 (d) infinite
(Ans. : c)
Q.4 In a parallel clipper, the slope of the transfer characteristics in clipping region is ______.
(a) unity (b) zero (c) depends on RL and R1 (d) infinite
(Ans. : b)
Two Way Clippers (Biased Shunt Clippers)

Q.1 A circuit producing both positive and negative clipping is called ______ clipper.
(a) series (b) parallel (c) two way (d) four way
(Ans. : c)
Clamper Circuits
Q.1 In a ________ clamper, the capacitor gets charged during first quarter of the positive
cycle of the input.
(a) negative (b) positive (c) combinational (d) two way
(Ans. : a)
Q.2 In a ________ clamper, the capacitor gets charged during first quarter of the negative
cycle of the input.
(a) negative (b) positive (c) combinational (d) two way
(Ans. : b)
Q.3 One charged to peak value, a capacitor acts as ________ in a clamper.
(a) filter (b) multiplier (c) battery (d) rectifier
(Ans. : c)
TM

Q.4 Due to large ________, capacitor holds its entire charge.

(a) charging current (b) time constant (c) discharging current (d) none of these
(Ans. : b)
Q.5 Due to the ________ time constant, the capacitor holds its entire charge.
(a) zero (b) negative (c) very large (d) unity
(Ans. : c)
Q.6 In a clamper, the analysis must start considering that part of the input which ________.
(a) reverse biases the diode (b) forward biases the diode
(c) discharges the capacitor (d) none of these
(Ans. : b)
Q.7 ________ is assumed in the clamper.
(a) Capacitor charges exponentially and discharges instantly
(b) Capacitor charges instantly and discharges instantly
(c) Capacitor charges instantly but does not discharge at all
(d) Capacitor charges exponentially and discharges exponentially
(Ans. : c)
Q.8 The circuits used to add a d.c. level to the output are called ______.
(a) clippers (b) slicers (c) limiters
(d) clampers
(Ans. : d)
Q.9 The clampers are also called ______ circuits.
(a) clipper (b) d.c. restorer (c) limiter (d) slicer
(Ans. : b)
Q.10 In a clamper, ______ is necessary in addition to a diode.
(a) inductor (b) transistor (c) capacitor (d) none of these
(Ans. : c)
Q.11 In a clamper, total swing of the output is ______ the total swing of the input.
(a) greator than (b) less than (c) equal to (d) none of these
(Ans. : c)
Q.12 In a cameras for the flash circuit ______ is used.
(a) clipper (b) clamper (c) limiter (d) rectifier
(Ans. : b)
qqq
TM

Notes
TM

2 Bipolar Junction Transistor
Chapter at a Glance
Important Definitions
1. Transistor is a three terminal device : Base, emitter and collector, can be operated in
three configurations common base, common emitter and common collector.
2. Unipolar transistor : The transistor in which current conduction is in only one type
of charge carriers, majority carriers.
3. Bipolar transistor : The transistor in which current conduction is due to two types of
carriers viz holes and electrons.
4. Doping : The process by which impurities are added to a pure semiconductor is
called doping.
5. Define a dc and b dc . + VTU : Mar.-2000, 05, Aug.-01, Feb.-10

a dc is the fraction of IE that crosses over from emitter to the collector region.
I -I
a dc = C CBO
IE
IC
a dc = a » when ICBO ® 0
IE
bdc : It is defined as the ratio of the collector current to the base current.
I
\ bdc = b = C
IB
Typical values : a = 0.9 to 0.99 b = 100 to 300
6. Current amplifier : In a transistor circuit, when output current is greater than input
current, the circuit is known as current amplifier.
7. Voltage amplifier : In a transistor circuit, when the output voltage is greater than the
input voltage, the circuit is known as voltage amplifier.
8. Active region : For the operation in the active region, the emitter-base junction (JE) is
forward biased while collector base junction (JC) is reverse biased.
(2 - 1)
TM

Basic Electronics 2-2 Bipolar Junction Transistor
9. Saturation region : In this region, the emitter-base junction (JE) and collector base
junction (JC) both are forward biased.
10. Cut-off region : The region below the curve I E = 0 is known as cut-off region,
where the collector current is nearly zero and the collector-base (JC) and emitter-base
(JE) junctions of a transistor are reverse biased.
11. Define current gain of CC configuration :
The current gain of CC configuration is given by
IE I +I I a 1
g = = B C = 1 + C = 1 +b= 1 + =
IB IB IB 1 -a 1 -a
Important Formulae
1. IE = IB + IC
IC
2. a dc = a »
IE
IC
3. b dc = b @
IB
a
4. b =
1 -a
b
5. a =
1 +b
Ic
6. b ac =
Ib
Vo
7. Av = ... Voltage gain
Vi
1 I
8. g = @ E
1 -a IB
Important Questions and Answers
Ø Explain the word transistor. + VTU : Feb.-02, Marks 5
· The amplification in the transistor is achieved by passing input current signal from a
region of low resistance to a region of high resistance. This concept of transfer of
resistance has given the name TRANSfer-resISTOR (TRANSISTOR).
Ø Clearly show the biasing arrangement of a NPN transistors for conduction.

TM

· The base to emitter junction is forward biased by the d.c. source VEE . Thus, the
depletion region at this junction is reduced. The collector to base junction is reverse
biased, increasing depletion region at collector to base junction as shown in Fig. 2.1.
· The forward biased EB junction causes the electrons in the n-type emitter to flow
towards the base. This constitutes the emitter current I E . As these electrons flow
through the p-type base, they tend to combine with holes in p-region (base).
· Due to light doping, very few of the electrons injected into the base from the emitter
recombine with holes to constitute base current, IB and the remaining large number of
electrons cross the base region and move through the collector region to the positive
terminal of the external d.c. source.
· This constitutes collector current I C . Thus the electron flow constitutes the dominant
current in an npn transistor.
· Since, the most of the electrons from emitter flow in the collector circuit and very few
combine with holes in the base. Thus, the collector current is larger than the base
current. The relationship between these current is given by
I E = IC + I B
Current BE BC Current
limiting depletion depletion limiting
resistor resistor
+ – – – – + + +
+ – – – – + + +
RE + – – – – + + + RC
E + – – – – + + + C
n p n
+ – – – – + + +
+ – – – – + + +
+ – – – – + + +
+ – – – – + + +
– BE Junction BC Junction
forward biased reverse biased +
VEE + VCC
–
Vb Barrier voltage
Vb
B
Fig. 2.1
Ø Write equations for collector current (I C ) in terms of emitter current (I E ) and a dc , and in terms
of base current (I B) and a dc . + VTU : Feb.-10, July-11, Marks 5
TM

Ø Draw a sketch to show the various current components in a NPN transistor and deduce the
relation between various current components. + VTU : Feb.-08, July-11, Marks 8
· The directions of conventional currents in an npn transistor are as shown in Fig. 2.2 (a)
and Fig. 2.2.5 (c) and those for a pnp are shown in Fig. 2.2 (b) and 2.2 (d). Figures show
the conventional currents using the schematic symbols of npn and pnp transistors,
respectively.
· It can be noticed that the arrow at the emitter of the transistor’s symbol points in the
direction of conventional current.
· Let us consider pnp transistor. The current flowing into the emitter terminal is referred
to as the emitter current and identified as I E . The currents flowing out of the collector
and base terminals are referred to as collector current and base current, respectively.
IC
n p n p n p
IE IE IC –
– + + IB
+ VEE IB VCC VEE V
– + CC
–
(a) (b)
IE IC IE IC
– +
–
+
+ VEE VCC VEE VCC
– – +
IB IB
(c) (d)
Fig. 2.2 Transistor conventional current directions
The collector current is identified as I C and base current as I B .
For both npn and pnp transistors.
IE = IB + IC
Ø Establish the relationship between a and b .
+ VTU : Mar.-2000 ,01, 05, Aug.-01, Feb.-09, Jan.-11, July-13, Marks 4
IC
We know that, b =
IB
We have, IE = IC + IB i.e. I B = I E – I C
IC
b = Q IB = IE – I C
IE – IC
Dividing the numerator and denominator of R.H.S. of above equation by I E , we get,
TM

IC IE
b =
IE IE – IC IE
\ a IC
b= Q a=
1– a IE
IC
We know that, a = and I E = I B + I C
IE
IC
a =
IB + IC
Dividing the numerator and denominator of R.H.S. of above equation by I B , we get,

IC IB
a =
IB IB + IC IB
\ b IC
a= Q b=
1+ b IB
Ø A transistor is capable of providing amplification; Explain the basic transistor amplifier with
suitable diagrams. + VTU : Aug.-03, Marks 6
Ø Show that a transistor could be used as an amplifier.
+ VTU : June-06, Aug.-08, Marks 5
Ø Explain how current amplification can be achieved in the transistor circuit.
· We have seen that b dc = I C / I B . It is the current gain from the base to collector. Since
I B is small and I C is large and they relate with a factor b dc , a small change in the
I B (D I B ) produces a large change in I C (D I C ). This is illustrated in the Fig. 2.3
RC +DIC
IC + DIC
–
+ IC
IB + DIB
– VCC
Q1 – –DIC
IB +DIB
+
VBB IE + DIE 0 –DIB 0
– –
Fig. 2.3 Illustration for the current amplification
· The increasing and decreasing levels of base and current currents due to change may be
defined as alternating quantities. The alternating current gain therefore, may be stated
as
TM

Ic
b ac =
Ib
where,
b ac : Alternating current gain
I c : a.c. collector current indicated by lower-case subscript
I b : a.c. base current indicated by lower-case subscript
The ac current gain is also denoted as h fe .
Ø With a neat circuit diagram explain the working of transistor used as voltage amplifier.
+ VTU : Jan.-14, Marks 4
· The Fig. 2.4 shows the transistor
circuit with a base bias and +
signal generator. Let us assume IC RC IC RC

that the transistor, Q 1 in the 10 K –
circuit has b dc = 100. The base +
RB +
bias of 0.7 V forward biases the Q1 VCC
base-emitter junction of transistor. IB –
An ac signal source, v i in series vi VCE
with VBB provides ± 10 mV input +
– 10 mV VB IE
+
voltage. VBB
(0.7 V) – –
· Now let us observe the changes
in I B and I C due to changes in v i Fig. 2.4
from the V-I characteristics of
transistor given in Fig. 2.5
IB(mA)
IB at VB = VBB+ vi
20
IB at VB = VBB
15
IB at VB = VBB – vi
10 VB = VBB – vi
VB = VBB
VB = VBB + vi
5
VBE(V)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Fig. 2.5 VBE versus I B characteristics of transistor
TM

Condition 1 : When v i = 0, VB = VBB = 0.7 and I B = 15 mA.

\ I C = 15 mA ´100 = 1.5 mA
Condition 2 : When v i = – 10 mV,
VB = VBB - v i = 0.7 – 10 mV = 0.69 V
I B = 10 mA
\ I C = 10 mA ´ 100 = 1 mA
Condition 3 : When v i = 10 mV
VB = VBB + v i = 0.7 + 10 mV = 0.71 V
I B = 20 mA
\ I C = 20 mA ´ 100 = 2 mA
· Therefore, change in I C (D I C ) = 2 mA – 1 mA = 1 mA due to ± 10 mV change in v i .
The change in the output voltage VC can be given by
D VC = D I C R C = 1 mA ´ 10 kW
= 10 V
· Therefore, the ac voltage gain which is the ratio of change in output voltage to change
in input voltage is given by
D VC D VC 10 V
Av = = = = 500
D VB D vi 20 mV
· Since the output voltage is greater than the input voltage, the circuit has a voltage gain
and it is a voltage amplifier.
· The voltage change across R C is an ac output voltage denoted as v o . Therefore, the
equation for ac voltage gain is given by
vo
Av =
vi
Ø Sketch and explain the input characteristics of transistor in CB mode.

+ VTU : Feb.-09, July-13
· It is the curve between and input voltage VEB (emitter-base voltage) and input current
I E (emitter current) at constant collector-base voltage VCB . The emitter current is taken
along Y-axis and emitter base voltage along X-axis. Fig. 2.6 shows the input
characteristics of a typical transistor in common-base configuration.
· From this characteristics we can observe the following important points :
1. The input resistance is a ratio of change in emitter-base voltage (DVEB ) to the
resulting change in emitter current (D I E ) at constant collector-base voltage (VCB ).
It is given by
D VEB
ri =
DI E VCB = constant
TM

|IE|(mA)
3.5
3.0 |VCB| = 10 V
Emitter-base current
2.5 |VCB| = 5 V
Note : While plotting input characteristics
2.0
the magnitudes of voltage and current are
1.5 |D IE| considered. Practically the voltage and
current polarities are opposite for pnp and
1.0 npn transistors
0.5
|D VEB|
|VEB|(V)
0.5 1.0 1.5 2.0
Emitter-base voltage
Fig. 2.6 Input characteristics of transistor in CB configuration
2. After the cut-in voltage (barrier potential, normally 0.7 V for silicon and 0.3 V for
germanium), the emitter current (I E ) increases rapidly with small increase in
emitter-base voltage (VEB ). Thus, the input resistance is very small.
3. It can be observed that there is slight increase in emitter current (I E ) with increase in
VCB . This is due to change in the width of the depletion region in the base region
under the reverse biased condition.
4. VCB is positive for npn transistor and it is negative for pnp transistor. On the other
hand VEB is negative for npn transistor and it is positive for pnp transistor.
Ø With a neat diagram explain the output characteristics of transistor in CB mode.
+ VTU : Feb.-02, 09, July-13, Marks 8
· It is the curve between collector current I C and collector base voltage VCB at constant
emitter current I E . The collector current is taken along Y-axis and collector-base voltage
magnitude along X-axis. Fig. 2.7 shows the output characteristics of a typical transistor
in common base configuration.
From this characteristics we observe following points :
1. The output characteristics has three basic regions : Active, cut-off and saturation.
2. Active Region :
n For the operation in the active region, the emitter-base junction (JE) is forward
biased while collector base junction (JC) is reverse biased.
n In this region, collector current I C is approximately equal to the emitter current ( I E )
and transistor works as an amplifier.
n In the active region, the collector current is essentially almost constant.
TM

|IC|(mA)
DIE Active region

|IE| = 5 mA
5 DVCB
4 |IE| = 4 mA
Note : While plotting output
characteristics the magnitudes
Saturation region
Collector current
3 |IE| = 3 mA of voltage and current are

considered. Practically the
voltage and current polarities
are opposite for pnp and npn
2 |IE| = 2 mA transistors
1 |IE| = 1 mA
|IE| = 0
–1 0 5 10 15 20 |VCB| (V)
Collector-base voltage Cut-off region
Fig. 2.7 CB output characteristics
n The Dynamic output resistance is the ratio of change in collector base voltage
( DVCB ) to the resulting change in collector current (DI C ) at constant emitter current
(I E ). It is given by
D VCB
Ro =
DI C I E = Constant
n The collector current I C is almost independent on collector-base voltage VCB and the
transistor can be said to work as constant-current source. This provides very high
dynamic output resistance.
3. Saturation Region : In this region, the emitter-base junction (JE) and collector base
junction (JC) both are forward biased. Here, the IC is independent of IE.
4. Cut-off Region : The region below the curve I E = 0 is known as cut-off region,
where the collector current is nearly zero and the collector-base (JC) and emitter-base
(JE) junctions of a transistor are reverse biased.
Ø Sketch and explain the input characteristics of transistor in CE mode.
+ VTU : Feb.-04, 08, Aug.-08, 09, Jan.-11
· It is the curve between and input voltage VBE (base-emitter voltage) and input current
I B (base current) at constant collector-emitter voltage, VCE . The base current is taken
along Y-axis and base emitter voltage VBE is taken along X-axis. Fig. 2.8 shows the
input characteristics of a typical transistor in common-emitter configuration.
TM

Basic Electronics 2 - 10 Bipolar Junction Transistor
From this characteristics we observe the following important points :

|IB|(mA)
80
|VCE| = 5 V
70 |VCE| = 20 V
Note : While plotting
60 input characteristics the
Base current
D IB magnitudes of voltage and

50
current are considered
40 Practically the voltage and
current polarities are
30 opposite for pnp and
npn transistors
20
10
D VBE
|VBE|(V)
0.5 1.0 1.5
Base-emitter voltage
Fig. 2.8 Input characteristics of the transistor in CE configuration
1. The input resistance is the ratio of change in base-emitter voltage (DVBE ) to the
resulting change in base current (DI B ) at constant collector emitter voltage VCE . It is
given by,
DVBE
ri =
D IB V
CE = Constant
2. As the input to a transistor in the CE configuration is between the base-to-emitter
junction, the CE input characteristics resembles a family of forward biased diode
curves.
3. After the cut-in voltage, the base current (I B ) increases rapidly with small increase in
base-emitter voltage (VBE ). Thus the dynamic input resistance is small in CE
configuration.
4. For a fixed value of VBE , I B decreases as VCE is increased.
5. Voltages VBE and VCE are positive for npn transistor and they are negative for pnp
transistor.
Ø With a neat diagram explain output characteristics of npn transistor in CE-configuration.
+ VTU : July-06, Aug.-2000, 02, 04, 05, 08, 09, Feb.-03, 04, 08, Jan.-11, Marks 5
Ø Draw the common emitter circuit and sketch the output characteristics, explain active region,
cutoff region and saturation region by indicating them on the characteristic curve.
1. This characteristics shows the relation between the collector current I C and collector
voltage VCE , for various fixed values of I B . This characteristics is often called
collector characteristics. A typical family of output characteristics for an n-p-n
transistor in CE configuration is shown in Fig. 2.9.
TM

|IC|(mA)
Active region
|IB| = 80 mA
Saturation 80 DIC
region DVCE
|IB| = 60 mA Note : While plotting output

60 characteristics the magnitudes
of voltage and current are
a DIC = 20 mA considered. Practically the
|IB| = 40 mA voltage and current polarities
Collector current
40 are opposite for pnp and npn

DIB = 20 mA
transistors
|IB| = 20 mA
20
|IB| = 0 mA
0 0.5 1.0 1.5 |VCE| (V)

Collector-emitter voltage Cut-off region
Fig. 2.9 Output characteristics of the transistor in CE configuration
2. The value of b dc of the transistor can be found at any point on the characteristics by
taking the ratio I C to I B at that point, i.e. b dc = I C / I B . This is known as D.C. beta
for the transistor.
3. From the output characteristics, we can see that change in collector-emitter voltage
( DVCE ) causes the little change in the collector current (DI C ) for constant base current
I B . Thus the output dynamic resistance is high in CE configuration.
D VCE
ro =
D I C I = Constant OR D I = 0
B B
4. The output characteristics of common emitter configuration consists of three regions :
Active, Saturation and Cut-off.
5. Active Region :
n For the operation in the active region, the emitter-base junction (JE) is forward
biased while collector base junction (JC) is reverse biased.
n The collector current rise more sharply with increasing VCE in the linear region
of output characteristics of CE transistor.
6. Saturation Region :
n In this region, the emitter-base junction (JE) and collector base junction (JC) both
are forward biased.
n The saturation value of VCE , designated VCE (sat ) , usually ranges between 0.1 V
to 0.3 V.
7. Cut-off Region : The region below I B = 0 is the cut-off region of operation for the
transistor. In this region, both the junctions of the transistor are reverse biased.
TM

IC
For saturation : IB >
b dc
For active region : VCE > VCE (sat)
Ø Compare CB, CE and CC transistor configurations.

+ VTU : Mar.-01, Aug.-01, Marks 10
Ø Write the special features of transistors in CE mode.
Sr.No. Characteristic Common Base Common Emitter Common Collector
1. Input resistance (Ri) Very low (20 W) Low (1kW) High (500 kW)
2. Output resistance (Ro) Very high (1 MW) High (40 kW) Low (50 W)
3. Input current IE IB IB
4. Output current IC IC IE
5. Input voltage applied Emitter and Base Base and Emitter Base and Collector
between
6. Output voltage taken Collector and Base Collector and Emitter Emitter and Collector
between
7. Current amplification IC IC IE
a = b= g=
factor IE IB IB
8. Current gain (Ai) Less than unity High (20 to few High (20 to few
hundreds) hundreds)
9. Voltage gain (Av) Medium Medium Less than unity
10. Applications As a input stage of Provides both voltage For impedance matching
multistage amplifier and current gain
greater than unity
and hence it is widely
used in audio signal
amplification
Table 2.1 Comparison of CB, CE, CC configurations
TM

Important Examples
Example 2.1 For a certain transistor, 99.6% of the carriers injected into the base cross the
collector-base junction. If the leakage current is 5 mA and the collector current is 20 mA,
calculate : i) The value of a ii) The emitter current. + VTU : Jan-14, Marks 4
Solution : 99.6 I E
I C(INJ) =
100
I C(INJ) + I CBO = I C
99.6 I E
\ + 5 ´ 10 – 6 = 20 ´ 10 –3
100
\ 0.996 I E + 5 ´ 10 –6 = 20 ´ 10 –3
20 ´ 10 –3 – 5 ´ 10 – 6
i) IE = = 20.07 mA
0.996
IC 20 mA
ii) a = = = 0.996
IE 20.07 mA
Example 2.2 A transistor has I B = 100 mA and I C = 2 mA. Find

i) b of the transistor,
ii) a of the transistor,
iii) Emitter current I E ,
iv) If I B changes by + 25 mA and I C changes by + 0.6 mA find the new value of b .
+ VTU : July-06, Marks 10
Solution :
Given : I B = 100 mA and I C = 2 mA
IC 2 mA
i) b = = = 20
IB 100 mA
b 20
ii) a = = = 0.952
1 + b 1 + 20
iii) I E = I B + I C = 100 mA + 2 mA = 2.1 mA
iv) New I B = 100 mA + 25 mA = 125 mA
New I C = 2 mA + 0.6 mA = 2.6 mA

2.6 mA
\ New b = = 20.8
125 mA
TM

Example 2.3 A transistor has a = 0.9. If IE = 10 mA, find the values of b, g, IB and IC.
+ VTU : Aug.-02, Marks 5
Solution :
a 0.9
b = = =9
1 -a 1 -0.9
g = 1 + b = 10
IC = a IE = 0.9 ´ 10 mA = 9 mA
IB = IE – IC = 10 mA – 9 mA = 1 mA
BJT Operation
Q.1 In a transistor the current conduction is due to _______ carriers.

(a) majority (b) minority (c) both a) and b) (d) none of these
(Ans. : c)
+ VTU : Jan.-11
Q.2 The transistor means ____.
(a) transfer-resistor (b) trans-resistor (c) tri-resistor (Ans. : a)
Q.3 Transistor is a ____ junction transistor.

(a) unipolar (b) bipolar (c) multipolar (Ans. : b)
Fig. 2.10
Q.4 The Fig. 2.10 shows the symbol of a ____ transistor.
(a) pnp (b) npn (c) field effect (Ans. : a)
Q.5 List the types of bipolar junction transistors.

(a) ppn, npn (b) pnp, npn (c) npp, ppn (d) nnp,pnp (Ans. : b)
Q.6 The process by which impurities are added to a pure semiconductor is ____ .
(a) diffusing (b) drift (c) doping (d) mixing (Ans. : c)
Q.7 Fig. 2.11 shows the equivalent circuit of the ____ transistor. E C
(a) pnp (b) npn (c) unijunction
(Ans. : a)
B
Q.8 The arrow in the transistor symbol indicates ____ terminal. Fig. 2.11
(a) base (b) collector (c) emitter
(Ans. : c)
Q.9 The arrow in the transistor symbol indicates the direction of ____.
(a) conventional emitter current (b) electron current in emitter
(c) supply current (d) ans (a) and (b) (Ans. : a)
TM

Q.10 Base of the transistor is always ____ and ___ doped.

(a) thick, lightly (b) thin, lightly (c) thin, heavily (Ans. : b)
Q.11 The collector of a transistor is _____ doped.

(a) heavily (b) moderately (c) lightly (Ans. : a)
Q.12 In transistors the collector region is larger than the emitter region for ____.
(a) better heat dissipation (b) higher value of b
(c) better amplification (Ans. : a)
Q.13 The ________region has highest thickness than all other regions in a BJT.
(a) base (b) collector (c) emitter (Ans. : b)
Q.14 The depletion region at emitter junction in an unbiased transistor extends more into
the____ region.
(a) collector (b) base (c) emitter (Ans. : b)
Q.15 The depletion region at collector junction in an unbiased transistor extends more into the
base region because it is ____ doped.
(a) heavily (b) moderately (c) lightly (Ans. : c)
Q.16 Doping concentration is highest in __________ and BJT.

(a) emitter region (b) collector region (c) base region (d) all of the above
(Ans. : a)
Q.17 The conduction in BJT is because of ___________.

(a) electrons (b) holes (c) both electrons and holes (Ans. : c)
Q.18 ______ of electrons and holes in the base region constitutes the base current.
(a) Ionization (b) Recombinations (c) Thermal agitation (Ans. : b)
Q.19 The largest current flow of a bipolar transistor occurs ________ .

(a) in the emitter (b) in the base (c) in the collector
(d) through the collector base (e) through the emitter collector (Ans. : a)
Q.20 A transistor ___________.

(a) is similar to a relay in that it uses a small amount of current to control a larger amount
of current flow.
(b) has three connections called the base, emitter and collector.
(c) is like a switch in that it is used to turn a circuit on and off.
(d) all of the above. (Ans. : d)
Q.21 The BJT is a ________ controlled device.

(a) current (b) voltage (c) field (Ans. : a)
Q.22 In BJT output current is controlled by _____ .

(a) input voltage (b) input current (c) input resistance (Ans. : b)
TM

Q.23 In a transistor the part heavily doped is ________.

(a) emitter (b) base (c) collector (d) all are equally doped
(Ans. : a)
+ VTU : Aug.-09
BJT Voltages and Currents
Q.1 In a reverse biased collector junction IC = _______ when the emitter is left open.
(a) 0 (b) I E (c) I CBO (Ans. : c)
Q.2 The _____ carriers constitute current I CBO .

(a) both minority and majority (b) minority (c) majority (Ans. : b)
Q.3 For a properly biased pnp transistor, let IC = 10 mA and IE = 10.2 mA. What is the level
of IB ?
(a) 0.2 A (b) 200 mA (c) 200 mA (d) 20.2 mA (Ans. : c)
Q.4 The value of a dc is always ________.

(a) unity (b) less than unity (c) greater than unity (Ans. : b)
Q.5 For a certain transistor a dc = 0.99 and I E = 2 mA. Calculate I B.

(a) 1.96 mA (b) 20 mA (c) 1.8 mA (Ans. : b)
Q.6 Typically the value of b dc is ________.

(a) 50 to 300 (b) 500 to 1000 (c) more than 1000 (Ans. : a)
Q.7 bdc = _______.
(a) I B / I E (b) I C / I E (c) I C / I B (d) None of the above
(Ans. : c)
Q.8 The ratio of which two currents is represented by b ?

(a) I C and I E (b) I C and I B (c) I E and I B (d) None of the above
(Ans. : b)
Q.9 The b in terms of a is given by ________.

a a 1+ a
(a) b = (b) b = (c) b =
(1+ a ) 1- a a (Ans. : b)
Q.10 b in a transistor when I B = 105 mA, I C = 2.05 mA is _________.
(a) 11.5 (b) 17.5 (c) 13.5 (d) 19.5 (Ans. : d)
Q.11 What is a equal to ?

(a) I B / I E (b) I C / I E (c) I C / I B (d) None of the above
(Ans. : b)
Q.12 Determine the value of a when b = 100.

(a) 1.01 (b) 101 (c) 0.99
(d) Cannot be solved with the information provided (Ans. : c)
TM

Q.13 The I CEO in terms of ICBO is given by _____.

(a) I CEO = (1 + b) I CBO
(b) I CEO = b I CBO + 1
(c) I CEO = I CBO (1 + b) (Ans. : a)
Q.14 The typical value of VBE (cut -off) for a Si transistor is ______.
(a) 0.7 V (b) 0 V (c) 0.3 V (Ans. : b)
Q.15 How much is the base-to-emitter voltage of a transistor in the "active" state ?
(a) 0 V (b) 0.7 V (c) 0.7 mV (d) Undefined
(Ans. : b)
Q.16 The value of V BE (active) for a Ge transistor is _____ V.

(a) 0.2 (b) 0.6 (c) 0.7 (Ans. : a)
Q.17 The typical value of V BE (sat) in CE configuration for a silicon transistor is _____.
(a) 0.8 V (b) 0.2 V (c) 0.9 V (Ans. : a)
Q.18 Which of the following voltages must have a negative level (value) in any npn circuit ?
(a) VBE (b) VCE (c) VBC (d) None of the above
(Ans. : c)
Q.19 The relation between a and b is given by ________ .

b b 1
(a) a = b (b) a = (c) a = (d) a = .
1- b 1+ b b (Ans. : c)
+ VTU : Aug.-09
Q.20 a of a transistor is 0.99. Calculate b.
(a) b = 0.9 (b) b = 90 (c) b = 99 (d) b = 0.09 (Ans. : c)
+ VTU : Jan.-14
BJT Amplification
Q.1 The output voltage of an amplifier is 5 V when an input voltage is 50 mV. Its voltage gain
is _____.
(a) 100 (b) 250 (c) 1000 (Ans. : a)
Common Base Characteristics
Q.1 The transistor acts as an amplifier in the _____ region .

(a) cut-off (b) active (c) saturation (Ans. : b)
Q.2 The dynamic output resistance of transistor in CB configuration is _______at constant I E.

(a) D VEB D I E (b) D VEB D IC (c) D VCB D IC (Ans. : c)
Q.3 a ac is the slope of _____ characteristics of transistor in CB configuration.

(a) input (b) output (c) transfer (Ans. : c)
TM

Q.4 The transfer characteristics of CB shows the relation between _____.

(a) I C and I E (b) I C and I B (c) I B and I E (Ans. : a)
Q.5 The transfer characteristics of a CB configuration is a graph of ______.

(a) VCB , I C (b) I E , I C (c) VEB , I E (Ans. : b)
Q.6 In the saturation region of the BJT _________.

(a) VCE = VCC (b) V CE @ 0 (c) VCE = 5 V (d) VCE = VCC + VBE
(Ans. : b)
Q.7 In _________ region the collector current is proportional to the base current.
(a) saturation (b) cut-off (c) active (Ans. : c)
Q.8 In _______ configurations there is phase shift of 0º between input and output.
(a) CB (b) CE (c) CC (d) CB and CC
(Ans. : d)
Q.9 In saturation region the collector current ___________.
(a) is independent of I B (b) is proportional to I B (c) is equal to I B (Ans. : a)
Q.10 For operating in the active region, the emitter junction should be ____ biased and
collector junction should be ____ biased.
(a) forward, forward (b) reverse, reverse (c) forward, reverse (d) reverse, forward
(Ans. : c)
Q.11 The emitter junction is ____ biased for operation in saturation region.
(a) forward (b) reverse (c) zero (Ans. : a)
Q.12 In which region are both the collector-base and base-emitter junctions forward biased ?
(a) Active (b) Cut-off (c) Saturation (d) All of the above
(Ans. : c)
Q.13 For the BJT to operate in the saturation region, the base-emitter junction must be _____ -
biased and the base-collector junction must be ______ - biased.
(a) forward, forward (b) forward, reverse
(c) reverse, reverse (d) reverse, forward (Ans. : a)
Q.14 At what region of operation is the base-emitter junction forward biased and the
base-collector junction reverse biased ?
(a) Saturation (b) Linear or active
(c) Cut-off (d) None of the above (Ans. : b)
Q.15 Which of the statement(s) for the Base-Emitter (B-E) and the Collector-Base (C-B)
junctions is/are true ?
(a) IC is independent of VCE in the active region. IC = 0 and VCE = VCC in the
cut-off region. IC = IC (sat) and VCE = 0 in the saturation region.
(b) The B-E should be forward-biased and the C-B should be reverse-biased in the active
region.
TM

(c) The base current I B controls the collector current IC in the active, cut-off and saturation
regions.
(d) All of the above. (Ans. : b)
Common Emitter Characteristics
Q.1 Which of the following regions is (are) part of the output characteristics of a transistor ?
(a) Active (b) Cut-off (c) Saturation (d) All of the above
(Ans. : d)
Q.2 The cut-off region is defined by I B ______ 0 A.
(a) > (b) < (c) £ (d) ³ (Ans. : c)
Q.3 The saturation region if defined by VCE ______ VCE sat.
(a) > (b) < (c) £ (d) ³ (Ans. : c)
Q.4 I CBO flows from _____ to _____ when emitter is open.
(a) collector, base (b) base, collector (c) collector, emitter (Ans. : a)
Q.5 The output characteristics of a CE configuration is the graph of _______.
(a) VCE , VEC (b) I C, V EC (c) VCE , I C (Ans. : c)
Q.6 For CE configuration, in the cut-off region, I C = ____.
(a) I CBO (b) I CEO (c) 0 (Ans. : b)
Q.7 The reverse saturation current of CE configuration with base open is _____.
(a) ICEO (b) ICBO (c) ICO (Ans. : a)
Q.8 The current gain of CE configuration is ______.
(a) b dc (b) a dc (c) g dc (Ans. : a)
Q.9 The value of dynamic output resistance in the CE configuration is _____ that in CB
configuration.
(a) low (b) high (c) moderate (Ans. : a)
Q.10 I CEO in a BJT ( a = 0.99), I CO = I CBO = 2 mA is _________.
(a) 2 mA (b) 99 mA (c) 198 mA (d) 200 mA (Ans. : d)
Q.11 For a BJT, under the saturation condition _________.
(a) I C = b I B (b) I C > b I B
(c) IC is independent of all other parameters (d) IC < b I B (Ans. : d)
Q.12 When a transistor is operated with the emitter diode forward biased and the collector
diode reverse biased, the collector current will be _________.
(a) almost zero (b) almost equal to the emitter current
(c) infinitely high (d) many times more than the emitter current (Ans. : b)
Q.13 In CE configuration, when collector current is zero, VCE equals ________ .
VCC VCC VCC
(a) (b) VCC (c) (d) .
RC + RE RC RE (Ans. : b)
+ VTU : Aug.-09
TM

Q.14 The input resistance of CE configuration is D VBE D I B at constant ______.

(a) VCE (b) VCB (c) I C (Ans. : a)
Q.15 A transistor is in saturation if _______.

IC IC
(a) I B > (b) > IB (c) I C = b I B
b b (Ans. : a)
Q.16 An amplifier is generally connected in ______ mode.
(a) saturation (b) cut-off (c) active (d) short (Ans. : c)
+ VTU : July-11
Common Collector Characteristics
Q.1 g = ________
(a) I C I B (b) I E I C (c) I E I B (Ans. : c)
Q.2 The ____ configuration is also called emitter follower.

(a) CB (b) CE (c) CC (Ans. : c)
Q.3 The output signal has approximately the same amplitude and phase as the input signal in
__________.
(a) CB (b) CC (c) CE (d) all of the above
(Ans. : b)
Q.4 In _______ configurations there is phase shift of 0º between input and output.
(a) CB (b) CE (c) CC (d) CB and CC
(Ans. : d)
Q.5 The phase difference between input and output of an emitter follower is _______.
(a) in-phase (b) out-of-phase (c) 90º (d) 45º (Ans. : a)
+ VTU : July-11
Q.6 Which of the following is (are) related to an emitter-follower configuration ?
(a) The input and output signals are in phase.
(b) The voltage gain is slightly less than 1.
(c) Output is drawn from the emitter terminal.
(d) All of the above. (Ans. : d)
Comparison of CB, CE, CC Configurations
Q.1 The _______ configuration is the most widely used.

(a) CB (b) CE (c) CC (Ans. : b)
Q.2 The _____ configuration is used as a input stage.

(a) CB (b) CE (c) CC (Ans. : a)
TM

Q.3 The input resistance of CC configuration is _____.
(a) very low (b) low (c) high (Ans. : c)
Q.4 The value of input resistance in the CE configuration is _____ that in CB configuration.
(a) lower than (b) higher than (c) same as (Ans. : b)
Q.5 Transistor has lowest output impedance in ____ configuration.

Q.6 Current gain of transistor amplifier is lowest in _____ configuration.
Q.7 The output resistance of CC configuration is _______.
(a) very low (b) low (c) high (Ans. : a)
Q.8 The _____ of CC configuration is less than unity.
(a) input resistance (b) current gain (c) voltage gain (Ans. : c)
Q.9 Identify which configuration has following characteristics. Voltage gain < 1, Input
impedance high and output impedance very low.
Q.10 ______ amplifier configuration provides both high current and voltage gain.
Q.11 As compared to a CB amplifier, a CE amplifier has __________.
(a) lower current amplification b) higher current amplification
(c) lower input resistance (d) higher input resistance (Ans. : b)
Q.12 In _______ configuration there is phase shift of 180º between input and output.
Q.13 ____ transistor configuration provides the highest input impedance.
Q.14 Which of the following is (are) the application (s) of a transistor ?
(a) Amplification of signal (b) Switching and control
(c) Computer logic circuitry (d) All of the above (Ans. : d)
Q.15 A _____ configuration does not need the thermal stabilization.
Q.16 Which of the following configurations can a transistor set up ?
(a) Common-base (b) Common-emitter
(c) Common-collector (d) All of the above (Ans. : d)
Q.17 The______ configuration is used as an output stage.
Q.18 The _____ transistor has the highest power gain.
(a) CE (b) CC (c) CB (d) None of these
(Ans. : b)
+ VTU : Jan.-11
TM

Q.19 For an emitter follower, the voltage gain is ________.

(a) unity (b) greater than unity
(c) less than unity (d) zero (Ans. : c)
+ VTU : Jan.-11
Q.20 Emitter follower is a ____.
(a) voltage amplifier (b) current amplifier
(c) attenuator (d) none of these (Ans. : b)
+ VTU : July-11
Q.21 Emitter follower has an input of 1 volt, then its output voltage is ____.
(a) 0.5 V (b) 10 V (c) 1 V (d) 5 V (Ans. : a)
+ VTU : July-11
Q.22 The _____ transistor is used for impedance matching.
(a) CB (b) CE (c) CC (d) None of these
(Ans. : c)
+ VTU : Jan.-11, 14
qqq
TM

3 BJT Biasing
Chapter at a Glance
1. Quiescent points / Operating points : For different values of IB, we have different
intersection points of the output curve and the dc load line. This points are called
quiescent points or operating points.
2. Define biasing of transistor : In order to operate transistor in the desired region we
have to apply external dc voltages of correct polarity and magnitude to the two
junctions of the transistor. This is nothing but the biasing of the transistor.
Important Formulae
1. For Fixed Bias Circuit
VCC - VBE
IB =
RB
VCE = VCC - I C R C
2. For Collector - Base Bias Circuit
VCC - VBE
IB =
R B + (1 + b) R C
VCE = VCC -(I B + I C ) R C

3. For Voltage Divider Bias
VT - VBE R2
IB = Where VT = V
R B + (1 + b) R E R 1 + R 2 CC
VCE = VCC - I C R C - I E R E
Ø Give the concept of d.c. load line. + VTU : Aug.-02, Marks 4

Ø Explain the d.c. load line and operating point, with example, related to the transistor.
(3 - 1)
TM

Basic Electronics 3-2 BJT Biasing
· For different values of IB, we have different intersection points of the output curve and
the dc load line. This points P, Q and R are called quiescent points or operating
points.
Ø Explain the effect of emitter resistance on dc load line.
· In Fig. 3.1 (a) the emitter resistance (RE) is connected in series with the transistor and
supply voltage (VCC) is directly connected to the collector terminal. Thus, here RE is d.c.
load.
· Applying KVL to the collector circuit of Fig. 3.1 (a) we have.
VCC – VCE – IERE = 0
\ VCE = VCC – IERE
· In Fig. 3.1 (b) collector resistance (RC) and emitter resistance (RE) both are present.
· Applying KVL to the collector circuit of +VCC +VCC

IC +
Fig. 3.1 (b) we have,
RC
VCC – ICRC – VCE – IERE = 0 C C –
+ +
\ VCE = VCC – ICRC – IERE B VCE B VCE
VCE = VCC – IC(RC + RE) Q IC » IE – –
E IE E +
+
· On the d.c. load line at VCE = 0, the value of
RE IE RE
IC in absence of RE will be
– –
V
IC = CC
RC
(a) RE = RL(dc) (b) (RC+RE) = RL(dc)
where as in presence of RE, this value will be
Fig. 3.1
VCC
IC =
RC + RE
Ø State the techniques used to stabilize operating point.
· The operating point of transistor varies due to change in temperature. To maintain the
operating point stable by keeping I C and VCE constant so that the transistor will always
work in active region, the following techniques are normally used.
n Stabilization techniques : Stabilization techniques refer to the use of resistive
biasing circuits which allow I B to vary so as to keep I C relatively constant with
variations in I CO , b , and VBE .
n Compensation techniques : Compensation techniques refer to the use of
temperature-sensitive devices such as diodes, transistors, thermistors, etc., which
provide compensating voltages and currents to maintain the operating point stable.
TM

Ø Explain collector-base bias circuit. + VTU : Feb.-07, Marks 8

Ø With a neat circuit diagram, explain the working of an collector-to-base bias circuit using an
npn transistor and derive the equation for IB.
· The Fig. 3.2 shows the dc bias with
+VCC
voltage feedback. It is called the
collector to base bias circuit. IC + IB
RC
· It is an improvement over the RB
fixed-bias method. Vo
IB
· In this the biasing resistor is connected B
Vi
between the collector and the base of +
VBE VCE
the transistor to provide a feedback –
E
path. Thus I B flows through R B and
(I C + I B ) flows through the R C .
Fig. 3.2 DC bias with voltage feedback
· Applying voltage law to the base
circuit we get,
VCC – (I B + I C ) R C - I B R B – VBE = 0
\ VCC = (R B + R C ) I B + I C R C + VBE = (R B + R C ) I B + bI B R C + VBE

VCC – VBE
IB =
R B + (1+ b ) R C
VCC – VBE
IB = Q b >> 1
RB + b RC
· Note that the only difference between the equation for I B and that obtained for the
fixed bias configuration is the term bR C . Thus we can say that the feedback path results
in a reflection of the resistance R C to the input circuit.
· Applying Kirchhoff’s voltage law to the collector circuit we get,
VCC – (I C + I B ) R C – VCE = 0
\ VCE = VCC – (I C + I B ) R C
· If there is a change in b due to piece to piece variation between transistors or if there is
a change in b and I CO due to the change in temperature, then collector current I C tends
to increase, since I C = b I B + I CEO .
· As a result, voltage drop across R C increases. Since supply voltage VCC is constant, due
to increase in I C R C , VCE decreases. Due to reduction in VCE , I B reduces.
· As I C depends on I B , decrease in I B reduces the original increase in I C . The result is
that the circuit tends to maintain a stable value of collector current, keeping the Q point
fixed.
TM

· In this circuit, R B appears directly across input (base) and output (collector). A part of
the output is fed back to the input, and increase in collector current decreases the base
current. Thus negative feedback exists in the circuit, so this circuit is also called voltage
feedback bias circuit.
Ø Explain with neat circuit the operation of voltage divider bias circuit.
+ VTU : Feb.-08, Marks 8; Jan.-11, July-11, Marks 4
· Fig. 3.3 shows the voltage divider bias VCC
circuit. In this circuit, the biasing is
provided by three resistors : R 1 , R 2 and
RE . IC
R1 I + IB RC
· The resistors R 1 and R 2 act as a
Vo
potential divider giving a fixed voltage IB
to point B which is base. Vi VCE
+
· If collector current increases due to VBE –
change in temperature or change in b,
the emitter current I E also increases and IE
R2 I RE
the voltage drop across R E increases,
reducing the voltage difference between
base and emitter (VBE ).
· Due to reduction in VBE , base current I B Fig. 3.3 Voltage divider bias circuit
and hence collector current IC also +VCC
reduces. Therefore, we can say that negative feedback
exists in the emitter bias circuit. RC IC
· This reduction in collector current I C compensates for
the original change in I C . RB = R1 || R2
· Fig. 3.4 shows simplified circuit of voltage divider IB

VBE
bias. Here, R 1 and R 2 are replaced by R B and VT ,
VT
where R B is the parallel combination of R 1 and R 2 RE IE
and VT is the Thevenin’s voltage. R B can be calculated
as
VCC R 2 R1 R 2 Fig. 3.4 Thevenin's equivalent
VT = RB = ... (3.1) circuit for voltage divider bias
R1 + R2 R1 + R 2
Applying KVL to the base circuit of Fig. 3.4 we get,
VT = I B R B + VBE + I E R E ... (3.2)
= IBRB + VBE + (1 + b) IBRE
VT - VBE
\ IB = …(3.3)
R B + (1 + b)R E
TM

Applying KVL to the collector circuit we get,

VCC – ICRC – VCE – IERE = 0
\ VCE = VCC – ICRC – IERE …(3.4)
Ø Give the comparison between various biasing circuits. + VTU : Aug.-08

Ø Compare base bias, collector to base bias and voltage divider bias with regard to stability of
the transistor collector voltage with spread in h FE value. + VTU : Feb.-10, Marks 10
· We have seen that the biasing circuit should provide the stability of Q point against the
change in device parameters.
· The VCE values calculated for each circuit for h FE ( min ) and h FE ( max ) are listed in
Table 3.1. Each circuit uses 12 V supply and has 2 kW collector (load) resistance. On the
basis of these similarities if we compare VCE values of these circuits. We can observe
following points.
· The collector to base bias provides more stability than the base bias circuit.
· Voltage divider bias provides the greatest stability against h FE variations.
Because of its excellent stability, voltage divider bias is the most commonly used biasing
circuit.
Biasing circuits Base bias Collector to base bias Voltage divider bias
VCE (min ) 3V 6.932 V 5.26 V
VCE (max ) 4.466 V 7.426 V 5.276 V
Table 3.1 VCE minimum and maximum values for similar bias circuits
The Table 3.2 gives the comparison between the biasing circuits.
Parameter Base bias Collector to base bias Voltage divider bias

VCC VCC VCC
Circuit
RC
RB (IC+IB) R1 RC
RC I1
RB IC
IB
IC
IB
IB IE
R2 RE
TM

Stability Less Medium Highest

provided
Feedback No Voltage shunt negative Current series negative

feedback feedback
Applications Used in circuits where Voltage shunt feedback It is most preferred

stability is not the from the collector biasing circuit the
important criteria. prevents. It is used in transistor from going into
switching circuits. saturation. It is used in
circuits where stability
requirements are
moderate.
Table 3.2 Comparison of basic biasing circuits
Important Examples
Example 3.1 Determine the operating point for a silicon transistor biased by base bias method
with b = 100, RB = 500 kW, RC = 2.5 KW and VCC = 20 V. Also draw the load line.
+ VTU : Jan.14, Marks 6
Solution : Apply KVL to base circuit +VCC = 20 V
– IBRB – VBE + VCC = 0 IB
V – VBE 20 – 0.7 IC
\ IB = CC = = 38.6 mA
RB + +
500 ´ 10 3 RC = 2.5 kW
RB
Q IC = bI B = 100 ´ 38.6 ´ 10 – 6 = 3.86 mA = 500 kW
– –
+
\ ICQ = 3.86 mA VCE
+
Apply KVL to collector circuit –
VBE = 0.7 V
–
– ICRC – VCE + VCC = 0
\ VCE = VCC – ICRC = 20 – (3.86 ´ 10 –3 ´ 2.5 ´ 10 3 )
= 10.35 V
Fig. 3.5 (a)
\ VCEQ = 10.35 V
To get two points on the load line,
i) VCE = VCC, IC = 0
\ A(20 V, 0)
VCC 20
ii) VCE = 0, IC = = = 8 mA
RC 2.5 ´ 10 3
\ B (0, 8 mA)
TM

The operating point is (10.35 V, 3.86 mA)

IC
(mA)
8 B
6
DC load line
5
4 Q(10.35 V, 3.86 mA)
1
A
0 5 10 15 20 25 VCE
(V)
Fig. 3.5 (b)

Example 3.2 The fixed biased circuit in VCC= 12 V
Fig. 3.6 is subjected to an increase in

junction temperature from 25 ° C to 75 ° C. RB
RC
IC
IB 600 W
If b = 100 at 25 º C and b = 125 at 75 º C, 100 kW
determine percent change in Q point values Si
(VCE , I C ) over the temperature range.

Neglect any change in VBE .
Fig. 3.6
Solution :
At 25 ° C :
Applying KVL to the base circuit we get,
VCC – I B R B – VBE = 0
VCC – VBE 12 – 0.7
IB = = = 113 mA
RB 100 ´ 10 3
\ I C = b I B = 100 ´ 113 ´ 10 –6 = 11.3 mA
Applying KVL to the collector circuit we get
VCC – I C R C – VCE = 0
TM

\ VCE = VCC – I C R C = 12 – 11.3 ´ 10 –3 ´ 600 = 5.22 V

At 75 ° C :
Since b = 125, IC = b I B = 125 ´ 113 ´ 10 –6 = 14.125 mA
VCE = VCC – I C R C = 12 – 14.125 ´ 10 –3 ´ 600
= 3.525 V
The percent change in I C is
I C (75° C) – I C (25 ° C) 14.25 ´ 10 – 3 – 11.3 ´ 10 – 3
% ¶ IC = ´ 100 % = ´ 100 %
I C (25° C) 11.3 ´ 10 – 3
= 25 % (an increase)
The percent change in VCE is
VCE (75° C) – VCE (25 ° C) 3.525 – 5.22
% ¶ VCE = ´ 100 % = ´ 100 %
VCE (25° C) 5.22
= – 32.47 % (a decrease)
Example 3.3 Calculate the minimum and maximum values of I C and VCE for the base bias when
hFE ( min ) = 50 and hFE ( max ) = 60. For circuit, VCC = 12 V, RC = 2 K and R B = 150 K.
Assume silicon transistor.
Solution :
For silicon transistor VBE = 0.7 V
VCC - VBE 12 V - 0.7 V
\ IB = = = 75.33 mA
RB 150 k W
For h FE ( min ) I C = h FE ( min ) ´ I B = 50 ´ 75.33 mA
= 3.767 mA
and VCE = VCC - I C R C = 12 - 3.767 mA ´ 2 kW
= 4.466 V
For h FE ( max ) I C = h FE ( max ) ´ I B = 60 ´ 75.33 mA
= 4.52 mA
and VCE = VCC - I C R C = 12 - 4.52 mA ´2 kW = 3 V
Example 3.4 For the circuit shown in Fig 3.7 Compute i) Three transistor currents ii) Voltage
drop across RC and RB. + VTU : Feb.-08, Marks 5
TM

VCC = 12 V
RC 100 W
RB = 12 kW
IC
b = 120
IE
Fig. 3.7
Solution :
i) Applying KVL to the base circuit we have,
VCC - (I B + I C )R C - I B R B - VBE = 0
VCC - VBE 12 - 0.7
\ IB = = = 468.88 mA
(1 + b) R C + R B (1 + 120) 100 + 12 ´ 10 3
IC = b´ I B = 120 ´ 468.88 mA
= 56.2656 mA
IE = IB +IC
= 56.7344 mA
ii) Drop across RC = (IB + IC) RC
= 56.7344 ´ 10 -3 ´ 100
= 5.67344 V
Drop across RB = IB RB
= 468.88 ´ 10 - 6 ´ 12 ´ 10 3
= 5.62656 V
Example 3.5 For the circuit shown in Fig. 3.8 b = 100 for the silicon transistor. Calculate VCE
and I C . + VTU : Feb.-08, Marks 5
TM

Basic Electronics 3 - 10 BJT Biasing
+10 V
R1 = 10 kW R C = 1 kW
Vo
C2
Vi
C1
R2 = 5 kW RE = 470 W
CE
Fig. 3.8
Solution :
Since (1 + b) R E = 47470 < 10R 2 = 50000
We use exact analysis
R2 5 ´ 103
VT = VCC = ´ 10 = 3.33 V
R1 + R 2 10 ´ 10 3 + 5 ´ 10 3
10 ´ 5
RB = = 3.33 kW
10 + 5
Applying KVL to the base circuit we get,
VT - I B R B - VBE - (1 + b) I B R E = 0
VT - VBE 3.33 - 0.7
\ IB = = = 51.77 mA
R B + (1 + b) R E 3.33 ´ 10 3 + (101) 470
I C = bI B = 100 ´ 51.77 mA = 5.177 mA

IE = IC +IB
= 5.23 mA
Applying KVL to collector circuit we get,
VCE = VCC - I C R C - I E R E
= 10 - 5.177 ´ 1 - 5.23 ´ 0.47
= 2.365 V
Example 3.6 Draw the d.c. load line for the voltage-divider biasing circuit shown in Fig. 3.9.
Find the collector current and the Q point. + VTU : Aug.-09, Marks 8
TM

+VCC = 30 V
3 kW
6.8 kW
1 kW
750 kW
Fig. 3.9
Solution : The various voltages and currents are shown in the Fig. 3.10 (a).
+ 30 V
VCC = 30 V
RC 3 kW
RC 3 kW IC
6.8 kW R1 +
IB RB
VCE
+
VBE –
+
VT –
RE 750 W
1 kW R2 –
RE 750 W
IE
(a) (b)
Fig. 3.10
The Thevenin's equivalent is shown in the Fig. 3.10 (a).
R2 30 ´ 1 ´ 10 3
VT = VCC ´ = = 3.8461 V
R1 + R2 1 ´ 10 3 + 6.8 ´ 10 3
1 ´ 10 3 ´ 6.8 ´ 10 3
R B = R 1|| R 2 = = 871.7948 W
1 ´ 10 3 + 6.8 ´ 10 3
Applying KVL to the base circuit we have,
- I B R B - VBE - I E R E + VT = 0 and I E = (1 + b) I B
Let b = 100
VT - VBE 3.8461 - 0.7
IB = =
R B + (1 + b) R E 871.7948 + (1 + 100) ´ 750
\ I B = 41.06 mA, I E = 4.14 mA
\ I C = b ´ I B = 100 ´ 41.06 ´ 10 - 6 = 4.106 mA
TM

Applying KVL to collector loop we have,

- 3 ´ 10 3 I C - VCE - 750 ´ I E + 30 = 0
\ VCE = 30 - 3 ´ 10 3 ´ 4.106 ´ 10 - 3 - 750 ´ 4.14 ´ 10 - 3 = 14.577 V
For drawing the d.c. load line,

For I C = 0, VCE = VCC = 30 V
VCC 30
For VCE = 0, IC = = = 8 mA
RC + RE 3000 + 750
Hence the load line is shown in the Fig. 10 (c).
IC(mA)
D.C. load line

8 mA
ICQ Q
= 4.106 mA
VCE(V)
0 VCEQ VCC = 30 V
14.577 V
Fig. 3.10 (c)
Example 3.7 Design a collector to base bias circuit to have VCE = 5 V and I C = 5 mA. When
the supply voltage is 15 V and b dc = 100, assume silicon transistor.
Solution : The circuit is shown in the Fig. 3.11. +VCC
I C = 5 mA, VCC = 15 V, VCE = 5 V, b = 100 +
IC + IB
RC
I 5 ´ 10 -3
IB = C = = 50 mA RB –
b 100
IB +
Applying KVL to collector circuit we have,
VCE
(I C + I B )R C + VCE = VCC +
VBE –
–
\ [5 ´ 10 -3 + 50 ´ 10 -3 ]R C + 5 = 15
\ R C = 1.9802 kW
Take R C = 2 kW standard value. Fig. 3.11
Applying KVL base circuit we have,
- I B R B - VBE + VCE = 0 ... VBE = 0.7 V for Si
TM

\ -50 ´ 10 -6 R B - 0.7 + 5 = 0
\ R B = 86 kW
Choose R B = 91 kW standard value.
DC Load Line and Bias Point
Q.1 The Q point is also known as _____.

(a) open point (b) operating point (c) d.c. point (Ans. : b)
Q.2 If the transistor is biased to place Q point in the saturation region, it will act as _____.
(a) amplifier (b) open switch (c) closed switch (Ans. : c)
Q.3 The slope of a d.c. load line represents ______.

(a) collector resistance
(b) reciprocal of d.c. load resistance
(c) reciprocal of a.c. load resistance (Ans. : b)
Q.4 The position of Q point on the d.c. load line should be ____. + VTU : Jan.-14
(a) stable (b) unstable (c) bistable (Ans. : a)
Q.5 The CE configuration, co-ordinates of Q point are _______.

(a) VCE , IB (b) VCB , IC (c) VCE , IC (Ans. : c)
Q.6 _____ has an important effect on shifting of the operating point.

(a) Voltage (b) Change in b (c) Current (Ans. : b)
Q.7 In CE configuration, the _____ half cycle of the output voltage will get distorted if the Q
point is near cut-off.
(a) positive (b) negative (c) none (Ans. : a)
Q.8 In order to avoid the distortion in the output waveform, the Q point has to be placed
_________. VCC
(a) near cut-off (b) at the centre of the d.c. load line
(c) near saturation
RC
(Ans. : b)
Q.9 The point of intersection on y-axis with d.c. load line indicates the C
value of _____.
(a) IC (max) (b) IC = 0 (c) IC (sat) (Ans. : a)
Q.10 Find the value of VCE when VCC = 20 V, RC = 5 kW and I C = 2 mA.

(a) 10 V (b) –10 V (c) 0.7 V E
(d) 20 V (Ans. : a)
TM

Q.11 The transistor is operated as a open switch in _____ region.

(a) cut-off (b) saturation (c) active (Ans. : a)
Q.12 The transistor may be used as a switch so that when it is in the saturated state its on
resistance is very ______ or in the cut-off state its off resistance is very ______.
(a) high, high (b) low, low (c) low, high (d) high, low (Ans. : c)
Q.13 We cannot operate the transistor in ________ region for the switching applications.
(a) cut-off (b) active (c) saturation (Ans. : b)
Q.14 The transistor is operated as a close switch in _____ region.

(a) cut-off (b) saturation (c) active (Ans. : b)
Q.15 The power dissipation in the transistor is a product of ______.

(a) I C and RC (b) VCE and I C (c) VCC and I C (Ans. : b)
Q.16 The transistor turn on and turn off time should be as _____ as possible.
(a) long (b) small (Ans. : b)
Q.17 If the operating point of an npn transistor amplifier is selected in saturation region, it is
likely to result in __________.
(a) thermal runaway of transistor
(b) clipping of output in the positive half of the input signal
(c) need for high d.c. collector supply
(d) clipping of output in the negative half of the input signal (Ans. : b)
Q.18 In CE configuration, the upper end of d.c. load line is called the _____ point and the
lower end is the ____ point.
(a) Q, base (b) base, Q (c) saturation, cut-off (d) cut-off, saturation
(Ans. : c)
Q.19 The transistor operating point is along the ____. + VTU : Jan.-11
(a) X-axis (b) resistance line (c) Load line (d) Y-axis (Ans. : c)
Q.20 The intersection of d.c. load line and the output characteristics of a transistor is called
______.
(a) Q-point (b) quiescent point (c) operating point (d) all of these
(Ans. : d)
Q.21 When a transistor is used as a switch, it works in the following region : + VTU : July-11
(a) Active and cut-off (b) Saturation and cut-off
(c) Saturation and active (d) None of these (Ans. : b)
Need of Biasing Circuit
Q.1 Which of the following factor affects the Q point stability ?

(a) Temperature (b) Bypass capacitors (c) Coupling capacitors (Ans. : a)
TM

Base Bias, Collector to Bias Configuration, Voltage Divider Bias,

Comparison of Basic Biasing Circuits
Q.1 In self bias or emitter bias circuit ____ is connected between emitter and ground.
(a) inductor (b) capacitor (c) resistor (Ans. : c)
Q.2 The self bias arrangement gives a better Q point stability when _________ .
(a) Re is small (b) b is small but Re is large
(c) both b and Re are large (d) none of these (Ans. : b)
+ Feb.-10
Q.3 Which transistor bias circuit has poor stability because its Q-point varies with bdc ?
(a) Collector feedback (b) Base
(c) Voltage divide (d) Emitter (Ans. : b)
+ Aug.-11
Q.4 The best biasing stability is achieved by using _____ biasing circuit.
(a) Fixed (b) Collector to base (c) Voltage divider (Ans. : c)
Q.5 Which of the following is assumed in the approximate analysis of a voltage divider
circuit ?
(a) IB is essentially zero amperes.
(b) R1 and R2 are considered to be series elements.
(c) bRE ³ 10 R2 (d) All of the above. (Ans. : d)
Q.6 For what value of b does the transistor enter the saturation region ?
VCC = + 12 V
RC
RB 2 kW
C2
200 kW
A.C.
output
C1 10 mF
A.C.
b = 50
input
10 mF
(a) 20 (b) 50 (c) 75 (d) 116 (Ans. : d)
qqq
TM

Notes
TM

Introduction to Operational
4 Amplifiers
Chapter at a Glance
1. Op-amp Symbol and Terminals

Positive
supply voltage
Inverting input terminal +VCC
– 7
2 6 Output terminal
Op-amps
3 +
4
Non-inverting input terminal –VEE
Negative
supply voltage
Fig. 4.1 Op-amp symbol
2. Differential Gain A d
\ Vo = A d Vd
Vo
Ad =
Vd
A d = 20 Log 10 (A d ) in dB
3. Common Mode Gain A c
V1 + V2
\ Vc =
2
\ Vo = A c Vc
\ Vo = A d Vd + A c Vc … Total output
(4 - 1)
TM

Basic Electronics 4-2 Introduction to Operational Amplifiers
4. Common Mode Rejection Ratio (CMRR)
Ad
\ CMRR = r =
Ac
Ad
\ CMRR in dB = 20 log dB
Ac
5. Ideal Op-amp Characteristics
Characteristics Symbol Values
Open loop voltage gain AO L ¥
Input impedance R in ¥
Output impedance Ro 0
Offset voltage V oo 0
Bandwidth B.W. ¥
C.M.R.R r ¥
Slew rate S ¥
Power supply rejection ratio PSRR 0
Table 4.1 Ideal op-amp characteristics

6. Voltage Levels and Saturating Property of Op-amp
Practically the op-amp output saturates at the voltages slightly less than the supply
voltages + VCC and - V EE .
7. Closed Loop Configuration of Op-amp
This introduces
negative feedback
Rf
Feedback resistor
–
V2
Op-amp Vo
+
V1
Overall finite gain
Fig. 4.2 Op-amp with negative feedback
TM

8. Characteristics of Practical Op-amp
Input bias current, | I b1 | + | I b2 |

Ib =
2
Input offset current, Iios = | Ib1 – Ib2|
9. Op-amp IC 741
Sr. No. Parameter Symbol Ideal Typical for 741 IC
1. Open loop voltage gain AOL ¥ 2 ´ 105
2. Output Impedance Z out 0 75 W
3. Input Impedance Z in ¥ 2 MW
4. Input offset current Iios 0 20 nA
5. Input offset voltage Vios 0 2 mV
6. Bandwidth B.W ¥ 1 MHz
7. CMRR r ¥ 90 dB
8. Slew rate S ¥ 0.5 V/ msec
9. Input bias current Ib 0 80 nA
10. Power Supply Rejection PSRR 0 30 mV/V

Ratio
Table 4.2
10. Realistic Simplifying Assumptions
· The steps of analysis based on these assumptions are,
Step 1 : Input current of the ideal op-amp is always zero. Using this, the current
distribution in the circuit is obtained.
Step 2 : The input terminals of the op-amp are always at the same potential. Thus if one
is grounded, the other can be treated to be virtually grounded. From this, the expressions
for various branch currents can be obtained.
Step 3 : Analyzing the various expressions obtained, eliminating unwanted variables, the
output expression in terms of input and circuit parameters can be obtained.
TM

11. Ideal Inverting Amplifier

Rf –
+
I
R1 I
+ – –
+
Vin A Ib = 0
– I Op-amp +
B + Vo
–
Fig. 4.3 Inverting amplifier
Vo R
\ AV = = – f (Gain with feedback)
Vin R1
12. Ideal Non-Inverting Amplifier
R1 A Rf
– + – + I
I
I
–
Vo
Op-amp +
B +
+ –
Vin
–
Fig. 4.4 Non-inverting amplifier
Vo R
AV = =1+ f
Vin R1
Important Point Regarding Non-inverting Amplifier :

· In non-inverting amplifier the input may not be applied directly to the
non-inverting terminal as considered while deriving the output expression but it
may be applied through some circuit.
· Let Vin is the input voltage applied to the non-inverting amplifier through some
resistive network such that the voltage available at the non-inverting input
terminal is VB which is different than Vin . Then the non-inverting amplifier
always amplifies voltage available to its non-inverting terminal by the factor
R æ R ö
(1 + f ). Hence V o = ç 1 + f ÷V B .
R1 è R1 ø
TM

13. Voltage Follower
–
A
Vo
+
+ B
Vin
–
Fig. 4.5 Voltage follower
Vo = Vin
14. Inverting Summing Amplifier

Rf
R1
+ I
V1
– I1
–
R2 A
Vo
+ B +
V2
– I2
Fig. 4.6 Inverting summer
éR R ù
\ Vo = – ê f V1 + f V2 ú
R
ë 1 R 2 û
If the two resistances are equal, R 1 = R 2 = R,
Rf
Vo = - ( V1 + V2 )
R
15. Non-inverting Summing Amplifier

Rf
I
R –
I A
R1 Vo
V1 I1
B +
V2 I2
R2
Fig. 4.7 Non-inverting summing amplifier
TM

R 2 (R + R f ) R (R + R f )
i.e. Vo = V1 + 1 V
R (R1 + R 2 ) R (R1 + R 2 ) 2
If the two resistances R 1 and R 2 are selected equal i.e. R 1 = R 2 then,

R + Rf
Vo = ( V1 + V2 )
2R
16. Average Circuit

R
R1 = R 2 = R 3 = … = R n = R and Rf =
n
17. Difference Amplifier or Subtractor
Rf
I1
R1
+ –
V1 I1 A Vo
R2
+
B
+
V2 I2
Rf
I2
Fig. 4.8 Subtractor circuit
Rf é R ù é Rf ù
\ Vo = – V + 1+ f V
R1 1 êë R1 úû êë R 2 + R f úû 2
18. Integrator
I
Cf
R1
–
Vin A
I Vo
B +
Fig. 4.9 Op-amp integrator
t
1
Vo = –
R1 Cf ò Vin dt + Vo (0)
0
TM

19. Differentiator
Rf
I1
C1
Vin
–
I1 A
Vo
B
+
Fig. 4.10 Op-amp differentiator
d Vin
Vo = – C1 R f
dt
Important Theory Questions and Answers
Ø List the various ideal op-amp characteristics.

+ VTU : Aug.-99, 2000, 01, 03, Feb.-03, 04, 05, July-08,09,
Jan.-07, 08,10,11,13,14, June-12, Marks 6
a) Infinite voltage gain : (A OL = ¥)
b) Infinite input impedance : (R in = ¥)
c) Zero output impedance : (R o = 0)
d) Zero offset voltage : (Vios = 0)
e) Infinite bandwidth
f) Infinite CMRR : ( r = ¥)
g) Infinite slew rate : (S = ¥)
h) No effect of temperature
i) Power Supply Rejection Ratio : (PSRR = 0)
Ø Draw an inverting amplifier using an op-amp and derive expression for its output voltage.
+ VTU : Aug.-2000, Mar.-2000, Marks 5 ; Feb.-03, Aug.-03, Marks 4;
Jan.-10, 11, Marks 6
· Refer basic circuit diagram of an inverting amplifier using op-amp on page 4-4.
· As node B is grounded, node A is also at ground potential, from the concept of virtual
ground, so VA = 0
V – VA V
\ I = in = in (as VA = 0) … (4.1)
R1 R1
TM

· The op-amp input current is always zero hence entire current I passes through the
resistance R f .
· From the output side, considering the direction of current I we can write,
V – Vo – Vo
I = A = (as VA = 0) … (4.2)
Rf Rf
Vin V R
· Equating (4.1) and (4.2) we get, = – o \ Vo = -Vin f
R1 Rf R1
Ø Draw non-inverting amplifier using op-amp and derive expression for its output voltage.
+ VTU : Mar.-99, 2000, Aug.-2000, 02, 04, Feb.-03, 05, Marks 5; Aug.-06, Marks 8
· Refer basic circuit diagram of a noninverting amplifier using op-amp on page 4-4.
· The node B is at potential Vin , hence the potential of point A is same as B which is Vin ,
from the concept of virtual ground.
\ VA = VB = Vin
Vo – VA Vo – Vin
I= = ( As VA = Vin ) … (4.1)
Rf Rf
· At the inverting terminal,
V –0 V
I = A = in ( As VA = Vin ) … (4.2)
R1 R1
Vo – Vin V æ R ö
· Equating equations (4.1) and (4.2), = in \ Vo = Vin ç 1 + f ÷
Rf R1 è R1 ø
Ø Draw the circuit of voltage follower and obtain expression for its output voltage. Where it is
used ? + VTU : Aug.-99, 02, 03, Mar.-01, Feb.-06, July-11, Marks 6
· Refer voltage follower circuit using op-amp on page 4-5.
· The node B is at potential Vin .
· The node A is also at the same potential as B i.e. Vin according to the concept of virtual
ground.
\ VA = VB = Vin … (4.1)
· Now node A is directly connected to the output. Hence we can write,
Vo = VA … (4.2)
Equating the equations (4.1) and (4.2),
Vo = Vin
TM

Ø Draw the circuit of an integrator and derive the expression for its output voltage.
+ VTU : Mar.-01,05, Jan.-08, 11, 13,July-09,11, Aug.-03, Feb.-03,04, June-13, Marks 5
· Refer the op-amp integrator circuit on page 4-6.

· The node B is grounded. The node A is also at the ground potential.
VA = VB = 0 V.
· From input side we can write,
V – VA V
I = in = in (VA = 0 V) … (4.1)
R1 R1
· From output side we can write,

d (VA – Vo ) dVo
I = Cf = – Cf (VA = 0 V) … (4.2)
dt dt
· Equating the two equations (4.1) and (4.2)
Vin dVo
= – Cf
R1 dt
· Integrating both sides, we get,

t
1
Vo = –
R1 Cf ò Vin dt + Vo (0)
0
Ø Draw the circuit of differentiator and derive the expression for its ouput voltage.
+ VTU : Aug.-02, Feb.-03, 04, Jan.-11, 14, July-11, Dec.-11, Marks 5
· Refer op-amp differentiator circuit on page 4-7.
· The node B is grounded.
· The node A is also at the ground potential, hence VA = 0.
· From the input side we can write,

d (Vin – VA ) d Vin
I 1 = C1 = C1 (VA = 0) … (4.1)
dt dt
(V – Vo ) V
· From the output side we can write, I = A =– o … (4.2)
Rf Rf
d Vin Vo
Equating the two equations, C1 =–
dt Rf
d Vin
Vo = – C1 R f
dt
TM

Basic Electronics 4 - 10 Introduction to Operational Amplifiers
Important Solved Examples
Example 4.1 An inverting amplifier circuit has input series resistor of 20 kW, feedback resistor of
100 kW and a load resistor of 50 kW. Draw the circuit and calculate the input current, load
current, and the output voltage when the applied input voltage is equal to + 1.5 V.
Solution : R1 = 20 kW, Rf = 100 kW, RL = 50 kW, Vin = 1.5 V
The circuit is shown in the Fig. 4.11.
Rf
I1 100 kW
I1
R1
Vin –
20 kW B
Vo
+
A
RL = 50 kW
IL
Fig. 4.11
The node A is grounded hence node B is at virtual ground.

\ V A = VB = 0 V
Vin - VB 1.5 - 0
\ I1 = = = 75 mA ... Input current
R1 20 ´ 10 3
The op-amp input current is zero hence same current I1 passes through the
resistance Rf.
VB - Vo 0 - Vo
\ I1 = i.e. 75 ´ 10 -6 =
Rf 100 ´ 10 3
\ Vo = -75 ´ 10 -6 ´ 100 ´ 10 3 = -7.5 V ... Output voltage
Vo -7.5
\ IL = = = - 0.15 mA ... Load current
R 50 ´ 10 3
L
The negative sign indicates that IL flows from ground to output terminal i.e. upwards as
Vo is negative.
TM

Example 4.2 Find Vo for the circuit shown in the Fig. 4.12
50 k W
10 k W
A –
Vo
Vin
1 kW B +
10 V
1 kW
Fig. 4.12
Rf
Solution : This is non-inverting amplifier but it will amplify VB by 1 + and not
R1
Vin =10 V. The op-amp input current is zero hence part of the circuit is as shown in the
Fig. 4.12 (a). 1 kW VB
Vin Iin = 0 A
Vin
\ I =
1 ´ 10 3 + 1 ´ 10 3 1 kW
and VB = I ´ ( 1 ´ 10 3 ) I
Vin Vin 10 Fig. 4.12 (a)

\ VB = ´ 1 ´ 10 3 = = =5V
2 ´ 10 3 2 2
æ R ö
\ Vo = ç 1 + f ÷ VB
è R1 ø
æ 50 ´ 10 3 ö
= ç1 + ÷ 5 = 30 V
ç 10 ´ 10 3 ÷
è ø
Example 4.3 A non inverting amplifier has input resistance 10 kW and feedback resistance
60 kW with load resistance 47 kW. Draw the circuit and calculate output voltage, voltage gain
and load current when input voltage is 1.5 V. + VTU : Feb.-08, Marks 8
Solution : R1 = 10 kW , Rf = 60 kW, RL = 47 kW, Vin = 1.5 V
The circuit is shown in the Fig. 4.13.
The node A is at Vin hence due to the concept of virtual ground, the node B is also at Vin.
\ VB = VA = Vin = 1.5 V
VB - 0 1.5
\ I1 = = = 0.15 mA
R1 10 ´ 10 3
As op-amp current is zero, the same current flows through Rf.
TM

Rf
60 kW
I1 R1 I1
–
10 kW B
Vo
A +
RL
Vin +
_ IL 47 kW
1.5 V
Fig. 4.13
Vo – VB Vo – 1.5
\ I1 = i. e. = 0.15 ´ 10 -3
Rf 60 ´ 10 3
\ Vo = 0.15 ´ 10 -3 ´ 60 ´ 10 3 + 1.5 = 10.5 V ... Output voltage
Vo 10.5
Voltage gain = = = 7
Vin 1.5
Rf 60
Cross check that voltage gain = 1 + = 1+ =7
R1 10
Vo 10.5
\ IL = = = 0.2234 mA ... Load current
R 47 ´ 10 3
L
Example 4.4 Design a scaling adder circuit using an OP-AMP to give the output -
Vo = - ( 3 V1 + 4V2 + 5 V 3 ), given the inputs V1 , V2 , V 3. .
+ VTU : Aug.-05, 08, Marks 8
Solution : The circuit of inverting Rf
R1
scaling adder is shown in the V1
Fig. 4.14. R2
V2
– +VCC
The output of this circuit is given
R3 Vo
by, V3 +
éR R R ù –VEE
Vo = - ê f V1 + f V2 + f V 3 ú
R
ë 1 R 2 R 3 û
The required output is,
Fig. 4.14
Vo = - [3 V1 + 4 V2 + 5 V 3 ]
Rf
\ = 3,
R1
Rf Rf
= 4, =5
R2 R3
Choose Rf = 100 kW
TM

\ R1 = 33.33 kW, R2 = 25 kW, R3 = 20 kW

The supply voltages may be selected as ± 15 V with IC 741 op-amp.
Example 4.5 Find the output voltage for the circuit below.
1 kW
1 kW
– 10 V
200 W –
+5V
Vo
+ 20 V +
400 W
Fig. 4.15
Solution : The circuit is inverting summing amplifier with,

R1 = 1 kW , R2 = 200 W, R3 = 400 W, Rf = 1 kW
V1 = – 10 V, V2 = 5 V, V3 = 20 V
éR R R ù
\ Vo = – ê f V1 + f V2 + f V 3 ú
R
ë 1 R 2 R 3 û
é 1000 1000 1000 ù
=–ê ´ ( -10) + ´ 5+ ´ 20ú = - 65 V
ë1 ´ 10 3 200 400 û
But op-amp can not produce output greater than the saturation voltages according to its
saturation property.
\ Vo = ± Vsat
Op-amp Symbol and Terminals
Q.1 An inverting input indicates _________ phase shift between input and output.
(a) 0º (b) 180º (c) 360º (d) 90º. (Ans. : b)
Q.2 The noninverting input indicates the phase shift of _____ between output and input of
op-amp.
(a) 0º (b) 180º (c) 90º (d) 270º (Ans. : a)
Q.3 The supply voltage range of an op-amp is ________.
(a) ± 5 to ± 22 V (b) ± 7 to ± 12 V
(c) ± 12 V to ± 25 V (d) none of these. (Ans. : a)
TM

Q.4 The output of an op-amp is measured with respect to ______ .

(a) negative supply (b) noninverting point
(c) positive supply (d) ground. (Ans. : d)
Ideal Op-amp
Q.1 The differential gain is expressed in dB as ______ .

1 1
(a) 10 log A (b) 20 log (c) 20 log A (d) 10 log .
A A
(Ans. : c)
Q.2 An op-amp has open loop gain of 105 and two inputs are 500 mV and 700 mV at inverting
and noninverting terminals respectively. Its output voltage is _______ .
(a) 10 V (b) 30 V (c) 25 V (d) 20 V. (Ans. : d)
Q.3 The gain with which differential amplifier amplifies the common signal is called ________ .
(a) common mode gain (b) differential gain
(c) constant gain (d) none of these (Ans. : a)
Q.4 The ideal value of common mode gain is _______.

(a) infinite (b) zero (c) very small (d) none of these.
(Ans. : b)
Q.5 The CMRR is given by _______. + VTU : June-13

A A Ac
(a) Ad × Ac (b) c (c) d (d) 20 log .
Ad Ac Ad
(Ans. : c)
Q.6 The ability of the op-amp to reject common mode signal is called _______.
(a) PSRR (b) open loop gain (c) closed loop gain (d) CMRR. (Ans. : d)
Q.7 If the input is applied between the two inputs it is called _______ input.
(a) common mode (b) subtractor (c) differential (d) essential
(Ans. : c)
Q.8 Op-amp is basically a ______ amplifier.

(a) power (b) differential (c) optical (d) current (Ans. : b)
Q.9 In the common mode operation the signals applied to the two inputs are ______.
(a) of same magnitude and same sign (b) of same magnitude and opposite sign
(c) of different magnitudes but different sign (d) of different magnitudes and same sign.
(Ans. : a)
Q.10 The common mode input signal will produce Vo = ______.

(a) + VCC (b) 0 (c) -VCC (d) infinite (Ans. : b)
TM

Q.11 The differential gain of a differential amplifier is defined as ______.

(a) Vo Vd (b) Vd Vo (c) Vo Vc (d) Vo Vin (Ans. : a)
Q.12 The common mode gain of a differential amplifier is defined as ______.

(a) Vo Vd (b) Vd Vo (c) Vo Vc (d) Vo Vin (Ans. : c)
Q.13 The ideal value of differential gain is ______.

(a) 2 ´ 105 (b) 0 (c) infinite (d) 12 ´ 105 (Ans. : c)
Q.14 Output voltage of a differential amplifier is ideally decided by ______.

(a) only Vc (b) only Vd (c) Vc and Vd (d) none of these
(Ans. : b)
Q.15 The ideal value of CMRR is ______.

(a) 90 dB (b) 2 ´ 105 (c) 0 (d) ¥ (Ans. : d)
Q.16 The differential amplifier amplifies _______ .

(a) the voltage only at inverting terminal.
(b) the voltage only at noninverting terminal.
(c) the difference between the two input voltages.
(d) none of these. (Ans. : c)
Q.17 The gain with which differential amplifier amplifies the difference between input signals is
denoted as _______ .
(a) A c (b) Ad (c) A F (d) none of these.
(Ans. : b)
Q.18 The units of CMRR are ______.

(a) dB (b) mV/V (c) mV V (d) V / ms (Ans. : a)
Q.19 An op-amp having Ac = 1 dB and Ad = 100 dB has CMRR = _______ .

(a) 100 dB (b) 99 dB (c) 10 dB (d) 1 dB (Ans. : b)
Q.20 The op-amp is basically a ---------- amplifier.

(a) positive feedback (b) differential
(c) common emitter (d) common-signal (Ans. : b)
Q.21 CMRR should be

(a) unity b) zero
(c) much larger than unity d) much smaller than unity (Ans. : c)
+ VTU : Jan.-11
Q.22 The differential amplifier has
(a) one input and one output b) two inputs and two outputs
(c) two inputs and one output d) one input and two outputs (Ans. : b)
+ VTU : July-11
Q.23 An op-amp has _________ o/p impedance. + VTU : June-12
TM

A) ¥ B) 0
C) 10000 W D) 600 W (Ans. : b)
Q.24 Ideally open loop gain of op-amp is _________

(a) 0 b) y
(c) ¥ d) negative (Ans. : c)
+ VTU : Jan-14
Q.25 For a differential amplifier Ad = 10000 and CMRR = 108 . What is the value of A c?
A) 10 -4 B) 10 -6 C) 10 4 D) 100 (Ans. : a)
+ VTU : Dec.-11
Ideal Op-amp Characteristics
Q.1 The slew rate of the op-amp is ________ .

(a) the maximum rate of change of output voltage.
(b) the maximum rate of change of input voltage.
(c) the maximum rate of change of feedback voltage.
(d) none of these. (Ans. : a)
Q.2 Ideal value of open loop gain of op-amp is ______ .

(a) unity (b) zero (c) 100 (d) infinite. (Ans. : d)
Q.3 The input current of an ideal op-amp is ______ .

(a) unity (b) zero (c) 100 (d) infinite. (Ans. : b)
Q.4 The input resistance of an ideal op-amp is _______..

(a) unity (b) zero (c) 1000 (d) infinite. (Ans. : d)
Q.5 For the ideal op-amp, the two input bias currents are ________.
(a) equal and opposite (b) zero
(c) of different magnitudes (d) infinite. (Ans. : b)
Q.6 The ideal op-amp does not load any source due to its _________.
(a) high CMRR (b) high open loop gain
(c) high slew rate (d) high input resistance (Ans. : d)
Q.7 An ideal op-amp can drive infinite number of circuits without difficulty because______.
(a) low output resistance (b) low input bias currents
(c) low common mode gain (d) CMRR = ¥ (Ans. : a)
Q.8 The bandwidth means frequency range over which _____ remains constant.
(a) resistance (b) CMRR (c) gain (d) slew rate
(Ans. : c)
TM

Q.9 An ideal op-amp has _______ gain, _______. input impedance and _____ output
impedance.
(a) 0, 0, ¥ (b) ¥ , 0, ¥ (c) ¥ , ¥ , ¥ (d) ¥ , ¥ ,0 (Ans. : d)
Q.10 The power supply rejection ratio (PSRR) is defined as ______.

D Vo D Vin DV D Vios
(a) (b) (c) (d)
DV DV D Vios DV (Ans. : d)
Q.11 The PSRR is generally measured in ______.
(a) dB (b) mV/V (c) mV V (d) no units (Ans. : c)
Q.12 The slew rate is generally measured in ______.

(a) dB (b) mV/V (c) mV V (d) V / ms (Ans. : d)
Q.13 The slew rate is generally specified at ______ gain.

(a) 10 (b) 1 (c) ¥ (d) 100 (Ans. : b)
Q.14 The highest frequency for which op-amp produces undistorted output depends on ______.
(a) input bias current (b) slew rate
(c) bandwidth (d) input offset voltage (Ans. : b)
Q.15 The effect of change in supply voltage on op-amp performance is judged by _______.
(a) CMRR (b) PSRR (c) slew rate (d) none of these
(Ans. : b)
Q.16 The maximum rate at which ampliifer output can change in volts per microsecond (V / ms )
is called ________
(a) over rate (b) slew rate (c) under rate (d) none (Ans. : b)
Q.17 The op-amp can amplify
(a) AC signal only (b) DC signal only
(c) Both AC and DC signals (d) None of these (Ans. : c)
+ VTU : Jan.-11
Q.18 An ideal OP-AMP has
(a) infinite input impedance (b) infinite voltage gain
(c) zero output resistance (d) all of these (Ans. : d)
+ VTU : July-11
Q.19 The ideal bandwidth of an op-amp is __________ . + VTU : Dec.-11
a) zero b) infinity c) high d) medium (Ans. : b)
Q.20 The ideal value of CMRR is _______. + VTU : Jan.-13

5
a) 90 dB b) 2 ´ 10 c) 0 d) ¥ (Ans. : d)
Q.21 The PSRR is generally measured in _______. + VTU : Jan.-13

a) dB b) mV/ V c) mV/ V d) V/ mS (Ans. : c)
TM

Voltage Levels and Saturating Property of Op-amp
Q.1 The output of op-amp can swing between ______due to its saturable property.
(a) 0 to + VCC (b) + VCC to -VEE (c) 0 to ¥ (d) none of these
(Ans. : b)
Q.2 Practically the maximum output voltage of op-amp is ______ supply voltage .
(a) more than (b) same as (c) less than (d) none of these.
(Ans. : b)
Closed Loop Configuration of Op-amp

Q.1 In most of the applications the op-amp is used in the ______ mode.
(a) open loop (b) closed loop (c) saturated (d) none of these.
(Ans. : b)
Q.2 The op-amp is used in the open loop mode for the ______ application.
(a) inverting amplifier (b) voltage follower
(c) integrator (d) comparator. (Ans. : d)
Q.3 When input and feedback signal are in phase, the feedback is called _______ feedback.
(a) negative (b) zero (c) infinite (d) positive (Ans. : d)
Q.4 When input and feedback signal are out of phase, then the feedback is called _______
feedback.
(a) negative (b) zero (c) infinite (d) positive (Ans. : a)
Q.5 Due to the negative feedback, the gain _______.
(a) increases (b) reduces (c) remains same (d) none of these
(Ans. : b)
Characteristics of Practical Op-amp

Q.1 To increase the input resistance of op-amp ______ is used .
(a) BJT (b) FET (c) transformer (d) diodes (Ans. : b)
Q.2 The input bias current is given by ________.

I b1 + I b2 I b1 - I b2
(a) (b) (c) I b1 - I b2 (d) I b1 + I b2
2 2
(Ans. : a)
Q.3 The input offset current is given by ________.

I b1 + I b2 I b1 - I b2
(a) (b) (c) I b1 - I b2 (d) I b1 + I b2
2 2
(Ans. : c)
Q.4 Ideal value of the input bias current is ______.

(a) 20 nA (b) 10 mA (c) 10 nA (d) 0 (Ans. : d)
TM

Q.5 The characteristics input offset voltage and input bias current of op-amp, depend on
______.
(a) RL (b) temperature (c) -VCC (d) + VCC (Ans. : b)
Q.6 The input bias current is ______ the input offset current.
(a) less than (b) greater than (c) same as (d) none of these
(Ans. : b)
Q.7 When both the inputs of op-amp are grounded, the voltage across the output is called
--------------------------.
(a) output offset voltage (b) output grounded voltage
(c) output bias voltage (d) output common voltage. (Ans. : a)
Q.8 The voltage gain of an OP-amp in the open loop condition is of the order of
1 2
(a) 10 b) 10
4 6
(c) 10 d) 10 (Ans. : d)
+ VTU : July-11
Block Diagram of Op-amp
Q.1 The function of level shifter stage is _______ .

(a) to produce exact sinusoidal signals. (b) to bring d.c. level down to zero.
(c) to suppress common mode signals. (d) all of the above. (Ans. : b)
Q.2 ______ is used as an input stage of IC op-amp.

(a) Single input single output differential amplifier
(b) Single input dual output differential amplifier
(c) Dual input dual output differential amplifier
(d) Dual input single output differential amplifier. (Ans. : c)
Q.3 ______ is used as an output stage of IC op-amp.

(a) CB amplifier (b) Class C amplifier
(c) Push pull amplifier with class B (d) None of these. (Ans. : c)
Q.4 _______ are used as an intermediate stage in IC op-amp.

(a) Feedback amplifier (b) Multistage amplifier
(c) Single stage amplifier (d) None of these (Ans. : b)
Q.5 The PSRR is the ratio of change in ________ to the change in the supply voltage
producing it.
(a) input offset current (b) input offset voltage
(c) input bias current (d) differential input voltage. (Ans. : b)
TM

Q.6 Buffer and level shifter is usually a ________ . + VTU : Dec.-11

a) current follower b) collector follower
c) resistance follower d) emitter follower (Ans. : d)
Op-amp IC 741
Q.1 The IC 741 uses a ______ polarity supply.

(a) single (b) dual (c) negative (d) unbalanced
(Ans. : b)
Q.2 The value of open loop voltage gain of IC 741 is ______ .

(a) ¥ (b) 2 ´ 105 (c) 0 (d) 2 ´ 109 (Ans. : b)
Q.3 The value of output impedance of IC 741 is ______ohms.

(a) 75 (b) 1000 (c) 0 (d) infinite (Ans. : a)
Q.4 The value of input impedance of IC 741 is ______ohms.

(a) 7500 (b) 2 ´ 106 (c) 0 (d) infinite (Ans. : b)
Q.5 The value of input offset current of IC 741 is ______amperes.

(a) 0 (b) 2 ´ 106 (c) 2 ´ 10-9 (d) 20 ´ 10-9 (Ans. : d)
Q.6 The value of input offset voltage of IC 741 is ______volts.

(a) 2 ´ 10-3 (b) 2 ´ 10-6 (c) 2 ´ 10-9 (d) 0 (Ans. : a)
Q.7 The value of bandwidth of IC 741 is ______Hz.

(a) 10 ´ 106 (b) 1´ 106 (c) 100 ´ 106 (d) infinite (Ans. : b)
Q.8 The value of slew rate of IC 741 is ______V/sec.

(a) 10 ´ 106 (b) 0.5 ´ 106 (c) 100 ´ 106 (d) infinite (Ans. : b)
Q.9 The value of CMRR of IC 741 is ______.

(a) 90 dB (b) 0 dB (c) infinite (d) 112 dB (Ans. : a)
Realistic Simplifying Assumptions
Q.1 Which of the following statement is true for the concept of virtual ground ?
(a) Both input terminals carry equal current.
(b) Both input terminals are directly grounded.
(c) Both input terminals are at same potential.
(d) None of these. (Ans. : c)
Q.2 According to ______ concept, the two input terminals are at same potential for the
op-amp.
(a) virtual short (b) positive feedback
(c) infinite Ro (d) none of these (Ans. : a)
TM

Ideal Inverting Amplifier
Q.1 The phase shift between input and output in an inverting amplifier is _____ .
(a) 0º (b) 180º (c) 90º (d) 270º. (Ans. : b)
Q.2 The gain of the inverting amplifier using Rf = 10 kW and R1 = 1 kW is _______ .

+ VTU : June-13
(a) –10 (b) –11 (c) 10 (d) 11. (Ans. : a)
Q.3 In an inverting amplifier if gain is one then the circuit is called _______ .
(a) Schmitt trigger (b) summer (c) phase inverter (d) rectifier (Ans. : c)
Q.4 Which of the following circuit is used as a scale changer ?

(a) Schmitt trigger (b) inverting amplifier
(c) phase shifter (d) noninverting integrator. (Ans. : b)
Q.5 Find the output voltage of the given circuit.

10 k W
2 kW
–
Vo
+
+
_
1V
(a) 5 V (b) 20 V (c) 6 V (d) – 5 V (Ans. : c)
Q.6 The circuit shown represents _______.

R
R –
(a) sign changer (b) differentiator (c) integrator (d) subtractor

(Ans. : a)
Q.7 In an inverting amplifier, R1 = 1 K and Rf = 2 K. If input voltage is 2 V, output voltage is

(a) - 2 V (b) - 0.5 V (c) 4 V (d) - 4 V. (Ans. : d)
Q.8 The inverting amplifier circuit has Ri = 1 kW and Rf = 3 kW. The output voltage is ____
when vi = 4V.
TM

(a) 6 V b) 16V (c) 12V d) 18V (Ans. : c)

+ VTU : Jan.-11
Q.9 In an inverting amplifier there is ____ phase shift between input and output.
(a) 0º b) 90º
(c) 180º d) 360º (Ans. : c)
+ VTU : Jan.-14
Q.10 For an inverting op-amp if R1 = R F then circuit is called _______ .
a) sign changer b) sign multiplier c) + ve sign d) none of these
(Ans. : a)
+ VTU : Dec.-11
Ideal Non-Inverting Amplifier
Q.1 The phase shift between input and output in a noninverting amplifier is _____ .
(a) 0º (b) 180º (c) 90º (d) 270º. (Ans. : a)
Q.2 The gain of the noninverting amplifier using Rf = 10 kW and R1 = 1 kW is _______ .

(a) –10 (b) –11 (c) 10 (d) 11 (Ans. : d)
Q.3 The closed loop gain of ______ circuit is always greater than 1.
(a) inverting amplifier (b) noninverting amplifier
(c) voltage follower (d) none of these (Ans. : b)
Q.4 The input resistance of noninverting amplifier is ______ that of a inverting amplifier.
(a) less than (b) greater than (c) equal to (d) none of these
(Ans. : b)
Q.5 An inverting amplifier using Rf = 10 kW and R1 = 1 kW has a gain of _______.
(a) – 0.1 (b) + 0.1 (c) – 10 (d) + 10. (Ans. : c)
Q.6 The output voltage of the amplifier shown in the Fig. 4.16 is _______V.
5 kW
1 kW
–
Vo
R
+
+2V
Fig. 4.16
(a) + 2 V (b) + 12 V (c) + 6 V (d) – 6 V (Ans. : c)
TM

Q.7 An op-amp non-inverting amplifier has R1 = 1kW and Rf = 3 kW when Vi = - 2 V, the output
is _________. +
VTU : June-12
a) – 4 V b) 4 V c) 8 V d) – 8 V (Ans. : d)
Voltage Follower
Q.1 The gain of the voltage follower is _______ . + VTU : Jan.-13, June-13
(a) zero (b) infinite (c) negative (d) unity. (Ans. : d)
Q.2 The voltage follower has _______ property.

(a) small bandwidth (b) large input resistance
(c) large output resistance (d) all the above. (Ans. : b)
Q.3 The voltage follower is practically used to _______ .

(a) reducing loading effect (b) increasing efficiency
(c) reducing offset error (d) none of these (Ans. : a)
Q.4 The closed loop gain of a voltage follower is ______ .

æ R ö
(a) 1 (b) -Rf R1 (c) ç1 + f ÷ (d) none of these
è R1 ø
(Ans. : a)
Q.5 The feedback factor b of the voltage follower circuit is ______.
(a) 1 (b) 0 (c) greater than 1 (d) less than 1
(Ans. : a)
Q.6 For a noninverting amplifier Rf = 10 kW and R1 = 1 kW then its gain is _______.
1
(a) +1.1 (b) –11 (c) (d) + 11.
11 (Ans. : d)
Q.7 The input resistance of voltage follower is _______ .
(a) very high (b) very low (c) zero (d) none of these.
(Ans. : a)
Q.8 The voltage follower is commonly used as _______.
(a) switch (b) isolator (c) regulator (d) none of these
(Ans. : b)
Q.9 An OP-AMP shorted between inverting terminal and output terminal is called
(a) adder (b) voltage follower (c) integrator (d) inverter (Ans. : b)
+ VTU : July-11
Q.10 Op-amp configuration used as buffer is _________. + VTU : June-12
(a) inverting amplifier (b) non inverting amplifier
(c) voltages follower (d) adder (Ans. : c)
TM

Summing Amplifier or Adder Circuit
Q.1 Find the output of the given circuit.
1 kW 1 kW
1V
1 kW
2V Vo
(a) 3 V (b) – 3 V (c) 2 V (d) –2 V (Ans. : b)
Q.2 The circuit shown represents _______ .
C
–
(a) sign changer (b) differentiator (c) integrator

(d) subtractor
(Ans. : b)
Q.3 For getting average circuit from the inverting summer, R1 = R2 = R and ______.
(a) Rf = R / 2 (b) Rf = 2R (c) Rf = R (d) none of these
(Ans. : a)
Difference Amplifier or Subtractor
Q.1 What is the output voltage of the following circuit ?

R
R
1V –
Vo
R
3V +
TM

(a) 2 V (b) –2 V (c) 4 V (d) none of these.

(Ans. : a)
R
–
R
+

(Ans. : d)
Q.3 __________ is the expression for output voltage of difference amplifier.

R1 Rf
(a) Vo = (V - V2 ) (b) Vo = (V + V2 )
Rf 1 R1 1
Rf
(c) Vo = (V - V2 ) (d) none of these.
R1 1 (Ans. : c)
Integrator

C
R
–

(Ans. : c)
Q.2 _______ is used in analog computers.
(a) Differentiator (b) Summer (c) Integrator (d) None of these
(Ans. : c)
Q.3 If we apply a sine wave to an integrator, then we get ______ at its output.
(a) cosine wave (b) negative cosine wave
(c) sine wave (d) triangular (Ans. : a)
TM

Q.4 If we apply a step waveform to an integrator, then we get ______ at its output.
(c) ramp (d) sine wave (Ans. : c)
Q.5 The integrator not using an op-amp is called ______ integrator.
(a) active (b) passive (c) hybrid (d) composite
(Ans. : b)
Q.6 The integrator using an op-amp is called ______ integrator.
(a) active (b) passive (c) hybrid (d) composite
(Ans. : a)
Q.7 In an inverting ideal integrator a ______ is connected in the feedback path.
(a) diode (b) resistor (c) capacitor (d) inductor (Ans. : c)
Q.8 At the ___________ frequency, gain of an integrator is maximum.
(a) 10 Hz (b) infinite (c) fH (d) 0 Hz (Ans. : d)
Q.9 The expression for output voltage of an inverting integrator is ______.
1 1
R1C f ò in R1C f ò in
(a) V dt + C (b) - V dt + C
dVin dVin
(c) - C1Rf (d) C1Rf
dt dt (Ans. : b)
Q.10 For a pure d.c. input, the integrator output is ______.
(a) triangular (b) zero (c) ramp (d) cannot be decided
(Ans. : c)
Q.11 An integrator acts as a ______ filter.
(a) high pass (b) band reject (c) bandpass (d) low pass(Ans. : d)
Q.12 The time constant of an op-amp integrator is _______.

R1 1 Cf
(a) (b) (c) (d) R1C f
Cf R1C f R1 (Ans. : d)
Q.13 When op-amp used as integrate with input as square wave the output will be ______.
(a) Ramp (b) Triangular wave
(c) Step (d) Cosine wave (Ans. : b)
+ VTU : Jan-14
Differentiator

R
C
–
TM


(Ans. : b)
Q.2 If input to an differentiator using R = 100 kW and C = 0.1 mF is 100 sin wt then the output
equation is _______ .
(a) – w cos wt (b) + w cos wt (c) –100 w cos wt (d) none of these
(Ans. : a)
Q.3 If we apply a sine wave to a differentiator, then we get ______ at its output.
(c) sine wave (d) triangular (Ans. : b)
Q.4 If we apply a square waveform to a differentiator, then we get ______ at its output.
+ VTU : Jan.-13
(c) ramp (d) train of impulses (Ans. : d)
Q.5 In an inverting ideal differentiator a ______ is connected in the feedback path.

(a) diode (b) resistor (c) capacitor (d) inductor (Ans. : b)
Q.6 The expression for output voltage of differentiatior is ______.

1 1
(a)
R1C f ò Vin dt + C (b) -
R1C f ò Vin dt + C
dVin dVin
(c) - C1Rf (d) C1Rf
dt dt (Ans. : c)
Q.7 A differentiator acts as a ______ filter.
(a) high pass (b) band reject (c) bandpass (d) low pass
(Ans. : a)
qqq
TM

Notes
TM

5 Digital Electronics
Chapter at a Glance
1. Digital/discrete signal : A digital/discrete signal is a signal that can have one of a
finite set of possible values at any time.
2. Analog/continuous signal : An analog/continuous signal is a signal that can have

one of an infinite number of possible values.
3. Binary signal : In digital systems, the most common digital signal is the signal that
has one of two possible values, like on or off (often represented as 1 or 0). Such
signal is known as binary signal.
4. If the higher of the two voltages represents a 1 and the lower voltage represents a 0,
the system is called a positive logic system.
5. If the lower voltage represents a 1 and the higher voltage represents a 0, we have a
negative logic system.
6. The 1’s complement : The 1’s complement of a binary number is the number that
results when we change all 1’s to zeros and the zeros to ones.
7. The 2’s complement : The 2’s complement is the binary number that results when
we add 1 to the 1’s complement. It is given as
2’s complement = 1’s complement + 1
8. Variable : The symbol which represent an arbitrary elements of an Boolean algebra is

known as variable.
(5 - 1)
TM

Basic Electronics 5-2 Digital Electronics
9. Constant : In expression Y = A + 1, the first term A is a variable and have value

either a 1 or 0. The second term has a fixed value 1. So 1 is a constant here. The
constant term may be 0 or 1.
10. Complement : A complement of a variable is represented by a "bar" over the letter.

Sometimes a prime symbol (’) is used to denote the complement.
11. Literal : Each occurrence of a variable in Boolean function either in a complemented

or an uncomplemented form is called a literal.
12. Boolean function : Boolean expressions are constructed by connecting the Boolean
constants and variables with the Boolean operations. These Boolean expressions are
also known as Boolean formulae.
13. Postulates and basic theorems of Boolean algebra.
Postulates (a) (b)
Postulate 1 Result of each operation is either 0 or 1 Î B
Postulate 2 (Identity) A+0=A A×1=A
Postulate 3 (Commutative) A+B =B+A AB = BA
Postulate 4 (Distributive) A (B + C) = AB + AC A + BC = (A + B) (A + C)
Postulate 5 (Complement) A+A =1 A×A=0
Theorems (a) (b)
Theorem 1 (Idempotency) A+A=A A×A=A
Theorem 2 A+1=1 A×0=0
Theorem 3 (Involution) A =A
Theorem 4 (Absorption) A + AB = A A (A + B) = A
Theorem 5 A + AB = A + B A × (A + B) = AB
Theorem 6 (Associative) A + (B + C) = (A + B) + C A (BC) = (AB) C
TM

14.
NOT gate (Inverter) : The output is a complement of input.
Logic Diagram (Symbol) Switch Equivalent Truth Table
A Y R
+
Pin Diagram V Input Output
–
S A Y
0 1
1 VCC 14
Input Output 1 0
2 13
Switch open (Low) Lamp ON (High)
Boolean Expression
Switch close (High) Lamp OFF (Low)
3 12
IC 7404 Y=A
4 11 VCC
Application :
5 10
R
Y Used to complement
6 9 R (invert) digital signal.
A
7 GND 8
Buffer : The output is same as input.

Symbol Boolean Expression Truth Table
Y=A
A Y Pin Diagram
Input Output
Application : It is used 14 13 12 11 10 9 8
to increase output driving VCC

A Y
capacity.
IC 7407 0 0
1 1
GND
1 2 3 4 5 6 7
TM

AND gate : The output is high only when all inputs are high.
A Input Output
Y
B + S1 S2
V A B Y
Pin Diagram –
0 0 0
1 VCC 14 Input 0 1 0
Output
S1 S2
2 13 1 0 0
Open (Low) Open (Low) Lamp OFF (Low)
3 12 Open (Low) Close (High) Lamp OFF (Low) 1 1 1
IC 7408 Close (High) Open (Low) Lamp OFF (Low)
4 11
Close (High) Close (High) Lamp ON (High)
5 10
Diode
6 9
Equivalent Boolean Expression
7 GND 8 +VCC
Y = A×B
R
Application :
A
Used to implement
B Y=A B
logical AND
operation.
TM

OR gate : The output is high when any of the inputs is high.

A S1
Y Input Output
B
Pin Diagram S2
+ A B Y
V
– 0 0 0
1 VCC 14
0 1 1
2 13
Input Output 1 0 1
3 12 S1 S2
IC 7432 Open (Low) Open (Low) Lamp OFF (Low) 1 1 1
4 11
Open (Low) Close (High) Lamp ON (High)
5 10 Close (High) Open (Low) Lamp ON (High) Boolean Expression
Close (High) Close (High) Lamp ON (High)
6 9 Y=A+B
Diode
7 GND 8 Application : Used to
Equivalent implement logical OR
operation.
A
B Y=A+B
NAND gate : The output is high only when one of the inputs is low.
Boolean Expression Truth Table
Symbol Y = A×B
Pin Diagram Input Output
A 14 13 12 11 10 9 8
Y A B Y
B VCC
0 0 1
IC 7400
Application : It can be used 0 1 1
to implement any digital
circuit. GND
1 0 1
1 2 3 4 5 6 7
1 1 0
TM

NOR Gate : The output is high when all the inputs are low.

Y=A+B
Pin Diagram Input Output
A 14 13 12 11 10 9 8 A B Y
Y
B VCC
0 0 1
0 1 0
IC 7402
Application : It can be used
1 0 0
to implement any digital
circuit. GND 1 1 0
1 2 3 4 5 6 7
Exclusive OR (EX-OR) gate : The output is high only when odd number of inputs
are high.
Symbol
Boolean Expression Truth Table
A
Y Y=AÅ B
B Input Output
Pin Diagram
Application : It is used to
14 13 12 11 10 9 8
implement magnitude A B Y
VCC
comparator, gray code 0 0 0
converter, adder/subtractor
IC 7486 0 1 1
circuits, parity generator,
modulo-2 adder, etc. 1 0 1
GND
1 1 0
1 2 3 4 5 6 7
Exclusive NOR (EX-NOR) gate : The output is high only when even number of ones at
the input or all inputs are high.

Y=AÅ B
Input Output
A Pin Diagram
Y
B 14 13 12 11 10 9 8 A B Y
VCC
Applications : It is used 0 0 1
to implement even parity IC 74266 0 1 0
generator, comparator, even
parity checker, etc. 1 0 0
GND
1 2 3 4 5 6 7 1 1 1
TM

15. The NAND and NOR gates are known as universal gates, since any logic function
can be implemented using NAND or NOR gates.
16. Half Adder : The logic circuit which adds two binary bits is called a half-adder.
17. Full Adder : The circuit which performs addition of three bits (two significant bits
and a previous carry) is a full-adder.
Ø Differentiate analog and digital signals.
Sr. Analog Signal Digital Signal

No.
1. An analog signal is a signal that can have A digital signal is a signal that can have one
one of an infinite number of possible values. of a finite set of possible values at any time.
2. Analog signal processing uses analog circuit Digital signal processing makes use of a
elements, such as resistors, capacitors, special purpose computer, which has three
inductors and active components such as basic elements, namely adders, multipliers,
operational amplifiers and non-linear and memory for storage.
devices.
3. Analog signal processing can be done in real There is no guarantee that the digital signal
time. It is more affected by noise. processing can be done in real time. It is less
affected by noise.
4. Analog signals consume less bandwidth than Digital signals consume more bandwidth
digital signals to carry the same information. than analog signals to carry the same
information.
5. They are best suited for transmission of They are best suited for transmission of
audio and video. computer data.
Ø Draw a block diagram of half adder. Write truth table. Draw logic diagram.
Ø Write a truth table for half adder, reduce the equation using K-map and design half adder
using logic gates.
The half-adder operation needs two binary inputs : augend and addend bits; and two
binary outputs : sum and carry. The truth table shown in Table 5.1 gives the relation
between input and output variables for half-adder operation.
Inputs Outputs
A Carry
A B Carry Sum Half
Inputs Outputs
adder
0 0 0 0 B Sum
0 1 0 1
1 0 0 1 Fig. 5.1 Block schematic of half-adder

1 1 1 0
Table 5.1 Truth table for half-adder
From the truth Table 5.1 we have
Carry = AB and
TM

Sum = AB + AB = A Å B Logic diagram

A
Limitations of Half-Adder : Sum
B
In multidigit addition we have to add two bits alongwith the
carry of previous digit addition. Effectively such addition Carry
requires addition of three bits. This is not possible with
Fig. 5.2 Logic diagram
half-adder. Hence half-adders are not used in practice. for half-adder
Ø Define full adder. Draw logic circuit and truth table of full adder.
A full-adder is a combinational circuit that forms the arithmetic sum of three input bits. It
consists of three inputs and two outputs. Two of the input variables, denoted by A and B,
represent the two significant bits to be added. The third input Cin, represents the carry
from the previous lower significant position. The truth table for full-adder is shown in
Table 5.2.
Cin
Inputs Outputs
A B Cin Carry Sum
0 0 0 0 0 A
Full
0 0 1 0 1 Sum
adder
0 1 0 0 1 B
0 1 1 1 0
1 0 0 0 1
Cout
1 0 1 1 0
1 1 0 1 0 Fig. 5.3 Block schematic of
full-adder
1 1 1 1 1
Table 5.2 Truth table for full-adder
From Table 5.2 we have
Carry = ABCin + ABCin + ABCin + ABCin
= ABCin + ABCin + ABCin + ABCin + ABCin + ABCin QA + A = A
= BCin (A + A) + ACin (B + B) + AB (Cin + Cin)
= BCin + ACin + AB
Logic diagram
A
A B
Cin
B A
B
A Cin
Cin Cout Sum
A
B
Cin
B
A
Cin B
Cin
Fig. 5.4 Sum of product implementation of full-adder
TM

The Boolean function for sum can be further simplified as follows :

Sum = A B Cin + A B Cin + A B Cin + A B Cin
= Cin (A B + AB) + Cin (A B + A B) = Cin (A 8 B) + Cin (A Å B)
= Cin (A Å B) + Cin (A Å B)
= Cin Å ( A Å B)
With this simplified Boolean function circuit for full-adder can be implemented as shown
in the Fig. 5.5.
A
B Sum
Cin
B
A
A
Cout
Cin
Cin
Fig. 5.5 Implementation of full-adder
Ø Implement full adder using two half adders and one OR gate. Write the equations for sum
and C out . + VTU : Jan. 14, Marks 6
A full-adder can also be implemented with two half-adders and one OR gate, as shown in
the Fig. 5.6. The sum output from the second half-adder is the exclusive-OR of Cin and the
output of the first half-adder, giving
Cout = AB + A C in + B C in
= AB + A C in (B + B) + B C in (A + A)
= AB + ABC in + A B C in + ABC in + A BC in
= AB (1 + C in + C in ) + A BC in + A BC in
= AB + ABC in + ABC in
= AB + C in (AB + AB)
= AB + C in (A Å B)
First half-adder Second half-adder
A Cin Å (A Å B)
B Sum
Cin (A Å B)
Cout
Cin
AB
Fig. 5.6 Implementation of a full-adder with two half-adders and an OR gate

TM

Basic Electronics 5 - 10 Digital Electronics
Important Examples
Example 5.1 Convert (125.62) 8 to binary.
Solution :
Step 1 : Write equivalent 3-bit binary number for each octal digit.
Step 2 : Remove any leading or trailing zeros.
1 2 5 6 2 Octal (Base 8)
Step 1. 0 0 1 0 1 0 1 0 1 1 1 0 0 1 0
Step 2. 1 0 1 0 1 0 1 1 1 0 0 1
Leading zeros Trailing zero
\ (125.62) 8 = (1010101.11001) 2
Example 5.2 Convert ( 8 A 9. B4 )16 to binary.
Solution :
Step 1 : Write equivalent 4-bit binary number of each hexadecimal digit.
Step 2 : Remove any leading or trailing zeros.
8 A 9 B 4
Step 1. 1 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 0 1 0 0
Step 2. 1 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 0 1
Trailing zeros
\ (8A9. B4) 16 = (1000 1010 1001.101101) 2

Example 5.3 Convert (BC 66.AF)16 to its octal equivalent.
Solution :
Step 1 : Write equivalent 4-bit binary number for each hexadecimal digit.
Step 2 : Make group of 3-bits starting from LSB for integer part and MSB for fractional
part by adding 0s at the end, if required.
Step 3 : Write equivalent octal number for each group of 3-bits.
B C 6 6 A F Hex (Base 16)
Step 1. 1 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 Binary (Base 2)
Step 2. 0 0 1 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 Binary (Base 2)
Step 3. 1 3 6 1 4 6 5 3 6 Octal (Base 8)
Adding 0s to make Adding 0 to make

a group of 3-bits a group of 3-bits
TM

Example 5.4 Convert 658.825 decimal into octal.
Solution :
Integer part : Conversion of integer part by successive division method.
Q R Q R
¸ LSD
658 8 = 82 2 8 658 2 LSD
82 ¸ 8 = 10 2 8 82 2
10 ¸ 8 = 1 2 8 10 2
¸ 8 1 1 MSD
1 8 = 0 1
0
MSD 1 2 2 2
(658)10 = (1222) 8
Fractional part : Conversion of fractional part by successive multiplication method.

Fraction Base Product
6 MSD
0.825 × 8 = 6 . 6
4
0.6 × 8 = 4 . 8
6 LSD
0.8 × 8 = 6 . 4
(0.825)10 = (0.646) 8 \ (658.825)10 = (1222.646) 8
Example 5.5 Convert 5386.345 decimal into hexadecimal.
Solution :
Integer part : Conversion of integer part by successive division method.
Q R Q R
LSD
5386 ¸ 16 = 336 10 16 5386 10(A) LSD
336 ¸ 16 = 21 0 16 336 0
21 ¸ 16 = 1 5 16 21 5
¸ 1 16 1 1 MSD
1 16 = 0
0
MSD 1 5 0 A
(5386)10 = (150A) 16
TM

Fractional part : Conversion of fractional part by successive multiplication method.
Fraction Base Product

5 MSD
0.345 × 16 = 5 . 52
8
0.52 × 16 = 8 . 32
5 LSD
0.32 × 16 = 5 . 12
(0.345)10 = (0.585) 16 \ (5386.345)10 = (150A.585) 16
Example 5.6 Convert the following binary numbers to decimal numbers.

Solution :
i) (1101)2 = (1 ´ 2 3 ) + (1 ´ 2 2 ) + (0 ´ 2 1) + (1 ´ 2 0 )
= 8 + 4+ 1 = (13)10
ii) (10001)2 = (1 ´ 2 4 ) + (0 ´ 2 3 ) + (0 ´ 2 2 ) + (0 ´ 2 1) + (1 ´ 2 0 )
= 16 +1 = (17)10
iii) (10101) = (1 ´ 2 4 ) + (0 ´ 2 3 ) + (1 ´ 2 2 ) + (0 ´ 2 1) + (1 ´ 2 0 )
= 16 +4 +1 = (21)10
Example 5.7 Convert (725.25)8 to its decimal and binary equivalent.

Solution :
(725.25)8 = ( ) 10
= ( )2
(725.25)8 = 7 ´ 8 2 + 2 ´ 8 1 + 5 ´ 8 0 + 2 ´ 8 -1 + 5 ´ 8 -2
2 5
= 7 ´ 64 + 2 ´ 8 + 5 ´ 1 +
+
8 64
= 448 + 16 + 5 + 0.25 + 0.0781
= ( 469. 328) 10
(725.25) 8 = (111 010 101 . 010 101) 2
TM

Example 5.8 Convert ( 3576) 8 to hexadecimal. + VTU : Feb.-07, Marks 5
Solution :
( 3576) 8 = ( ) 16 or H
3 5 7 6 Octal
0 1 1 1 0 1 1 1 1 1 1 0 Binary
7 7 E Hex
\ ( 3576) 8 = (7 7 E)16
Example 5.9 Determine the value of base x, if i) (225)x = (341)8; ii) (211)x = (152)8
Solution : i) (225)x = (341)8
Converting octal into decimal.
(341)8 = 3 ´ 8 2 + 4 ´ 8 + 1 = (225)10
\ (225)x = (341)8 = (225)10

\ x = 10 i.e. (225)10 = (341)8
ii) (211)x = (152)8
Converting octal into decimal
(152)8 = 1 ´ 8 2 + 5 ´ 8 + 2 = (106)10
\ (211)x = 2 ´ x 2 + 1 ´ x + 1 ´ x 0 = (106)10
\ 2x 2 + x + 1 = 106
\ x = 7 or x = – 7.5
x = – 7.5 is invalid
\ x = 7
\ (211)7 = (152)8
Example 5.10 (101010111100)2 = (?)8 = (?)16 + VTU : July-11, Marks 8
Solution :
1 0 1 0 1 0 1 1 1 1 0 0 Binary Number
5 2 7 4 Octal Number
\ (101010111100)2 = (5274)8 = (ABC)16
1 0 1 0 1 0 1 1 1 1 0 0 Binary Number
A B C Hex Number
TM

Example 5.11 (240)10 (?)2 = (?)BCD + VTU : July-11, Marks 8
Solution :
2 240 0 LSD
\ (240)10 = (11110000)2
2 120 0
(240)10 = (0010 0100 0000)BCD
2 60 0
2 30 0
2 15 1
2 7 1
2 3 1
2 1 1 MSD
Example 5.12 Add (28)10 and (15)10 by converting them into binary.
Solution : Using decimal to binary conversion technique we have,
1 1 1 Carry (28)10
0 0 1 1 1 0 0 Binary equivalent of (28)10 + (15)
Sign Extension + 10
0 0 0 1 1 1 1 Binary equivalent of (15)10
Sign (43)10
0 1 0 1 0 1 1 Result : Binary equivalent of (43)10
(28) 10 = (011100) 2 and (15) 10 = (01111) 2

Example 5.13 Perform (28)10 - (19)10 using 1's complement representation.

Solution :
(28) 10 = (011100) 2
(19) 10 = (010011) 2
0 1 0 0 1 1 (19)10
Carry
1 0 1 1 0 0 1's complement of (19)10
1 1 1 1 Carry (28)10
0 1 1 1 0 0 Binary equivalent of (28)10 +
+ (–19)10
1 0 1 1 0 0 1's complement of 19, i.e. (–19)10
1 0 0 1 0 0 0 Result (9)10
+ 1
0 0 1 0 0 1 Final result : Binary equivalent of (9)10
TM

Example 5.14 Perform (28)10 - (19)10 using 2's complement representation.

Solution :
(28) 10 = (011100) 2
(19) 10 = (010011) 2
0 1 0 0 1 1 (19)10
Carry
1 0 1 1 0 0 1's complement of (19)10
+ 1 Add 1
1 0 1 1 0 1 2's complement of 19, i.e., (–19)10
1 1 1 1 Carry (28)10
0 1 1 1 0 0 Binary equivalent of (28)10 +
+ (–19)10
1 0 1 1 0 1 2's complement of 19, i.e. (–19)10
Ignore Carry 1 0 0 1 0 0 1 Result : Binary equivalent of (09)10 (09)10
Example 5.15 State the identities of Boolean addition and Boolean multiplication.
Solution :
Identities of Boolean addition
1. A+0 = A
2. A+1 = 1
3. A+A = A
4. A+A = 1
Identities of Boolean multiplication
1. A×0 = 0
2. A×1 = A
3. A×A = A
4. A×A = 0
Example 5.16 Prove that AB + A + AB = 0 + VTU : Feb.-07, 09, Marks 5
Solution :
AB + A + AB = 0
L.H.S. = AB × A × AB DeMorgan's theorem
A B × A × (A + B) A + B+ C = A B × C
A B (A + B) AA = A
AA B+ABB A A = 0, B B = 0
0 + 0 = 0 = R.H.S.
TM

Example 5.17 i) Prove that AB + A + AB = 0

ii) Simplify X Y Z+ X Y Z+ X Y+ XY + VTU : Aug.-08, Marks 3
Solution :
i) AB + A + AB = 0 is not true.
AB + A + A B = A (B + 1 + B)
= A Q 1 + A =1
ii) X Y Z + X Y Z + X Y + X Y
= X Y (Z + Z + 1 ) + X Y
= X Y+X Y Q 1 + A =1
= Y (X + X) Q A + A=1
= Y
Example 5.18 Simplify ABC + ABC + ABC + ABC and realize using basic gates.
+ VTU : Aug.11, Marks 8
Solution : Simplification
ABC + ABC + ABC + ABC = AC (B + B) + AB (C + C) + BC (A + 1) = AC + AB + BC
Realization
A
C
A
Y
B
B
C
Fig. 5.7
Example 5.19 Implement EX-OR gate using only NAND gates. + VTU : July-11, Marks 4
Solution : The Boolean expression for EX-OR gate is : Y = AB + AB
A
B
A
B
Fig. 5.8 (a)
TM

We can implement AND-OR logic by using NAND-NAND logic as shown in Fig. 5.8 (b).
A
A A A×B
B
B B
º Y
A A
B
B
A×B
Fig. 5.8 (b)
Example 5.20 Implement EX-NOR gate using only NAND gates.
Solution : We have,
A A
Y Y
B B
EX-NOR EX-OR Inverter
Fig. 5.9 (a)
Thus using result in previous example we have EX-NOR gate using only NAND gates as
shown in the Fig. 5.9 (b)
A
A A×B
B
B
A
A×B
B
Fig. 5.9 (b)

Example 5.21 Implement EX-OR gate using only NOR gates.
Solution : Boolean expression of EX-OR gate F = AB + AB

F = F = AB + AB
A
B
F
A
B
Fig. 5.10 (a)

TM

= (A + B) × (AB)
= (A + B) × (A + B)
· Note : We can implement OR-AND logic by NOR-NOR logic.
A
B
º F
A
B
A
A
B
B
º A F
A
B
B
Fig. 5.10 (b)

Example 5.22 Simplify the following 4 variable function using K-map and represent using NAND
gate only :
F(A, B, C, D) = ( ABC D + ABCD + ABCD + ABCD
+ AB C D + ABC D ) + d ( A B C D + A B CD
+ A B CD + AB C D + ABCD + ABCD )
Solution :
F (A, B, C, D) = ( AB C D + ABC D + ABCD + ABCD
+ AB C D + ABC D) + d ( A B C D + A B C D)
+ A B C D + A B C D + A B C D + A B C D)
f (A, B , C, D) = Sm ( 4,5,6,7,8,12) + d (1, 2, 3, 9, 11, 14).
K-map simplification :
AB CD 00 01 11 10
00 X X X
01 1 1 1 1 AB
11 1 X
ACD 10 1 X X
Fig. 5.11
\ f = AB +AC D
TM

Implementation using basic gates Implementation using only NAND gates
A
A
B
B
f
A
A
C
C
D
f = (A B) (A C D)
D =AB+ACD
=AB+ACD
Fig. 5.12 (a)
Note : AND-OR logic can be implemented by NAND-NAND logic.
Example 5.23 Simplify and realize the following using NAND gates A B C + A B C + A B + AC.
Solution : A B C + A B C + A B + AC = B C (A + A ) + A B + A C = B C+ A B+ A C
We can implement AND-OR logic using NAND-NAND logic
A
A
B
B
Y
C
C
Fig. 5.13
Example 5.24 Draw half adder using NAND gates.
Solution : For half adder :

Sum = AB + AB C out = AB = AB
= AB + AB
= A B×A B
TM

A AB
B A B × A B = Sum
AB
AB A B = A B = Cout
Fig. 5.14
Example 5.25 Realize full adder circuit using NAND gate and write its truth table.
Solution :
We have,
Cout = AB + ACin + BCin
Sum = A B C in + A B C in + A B C in + A B C in
We can implement AND-OR logic using NAND-NAND logic.
A
Cout
Cin
B
Cin
Cin
B
B
Cin Sum
A
A
B
Cin
Fig. 5.15
TM

Introduction
Q.1 The binary logic used in binary system uses _____ value.
(a) only one (b) only two (c) three (d) more than three
(Ans. : b)
Switching and Logic Levels
Q.1 In ______ logic system, high voltage level is represented by 1 and low voltage level is
represented by 0.
(a) positive (b) negative (c) zero (d) none of these
(Ans. : a)
Digital Waveform
Q.1 A _____ is a signal that can have one of a finite set of possible values at any time.
(a) digital signal (b) analog signal (c) continuous signal (d) none of these
(Ans. : a)
Q.2 An analog signal can have ____ number of possible values.

(a) finite (b) only one (c) one of an infinite (d) cannot be predicted
(Ans. : c)
Q.3 In digital systems number formed by ____ values are used to represent the levels of
discrete signal.
(a) decimal (b) octal (c) hexadecimal (d) binary (Ans. : d)
Introduction to Number Systems
Q.1 Which numbering system employs only ten digits ?

(a) Binary (b) Hexadecimal (c) Decimal (d) Octal (Ans. : c)
Q.2 The digits that may be used in the unit column of the octal numbering system are :
(a) 0 through 15 (b) 0 through 7 (c) 1 through 10 (d) 1 through 8
(Ans. : b)
Q.3 To distinguish between numbering systems, one may refer to the :

(a) Reset and carry action (b) Radix
(c) Positional weight (d) Significant digits (Ans. : b)
Q.4 What is the radix for the binary numbering system ?

(a) 16 (b) 10 (c) 8 (d) 2 (Ans. : d)
TM

Q.5 The positional weight of the binary one in the binary number 001000 is represented by :
1 2 3 4
(a) 2 (b) 2 (c) 2 (d) 2 (Ans. : c)
Q.6 What is a base 16 numbering system called ?

(a) Binary (b) Octal (c) Coded decimal (d) Hexadecimal
(Ans. : d)
Q.7 Hexadecimal and octal numbering systems are similar for the first :
(a) 9 digits (b) 8 digits (c) 7 digits (d) 6 digits (Ans. : b)
Q.8 The base of the octal system is :

(a) Eight (b) Seven (c) Ten (d) Two (Ans. : a)
Q.9 Which is the longest: bit, byte, nibble, word ?

(a) Bit (b) Byte (c) Nibble (d) Word (Ans. : d)
Q.10 In hexadecimal number system, A is equal to decimal number _______ .

(a) 10 (b) 11 (c) 17 (d) 18 (Ans. : a)
0
Q.11 In a binary number, the column for the LSB is represented by 2 , which has a value of :
(a) 8 (b) 4 (c) 2 (d) 1 (Ans. : d)
Q.12 Hexadecimal number E is equal to binary number _______ .

(a) 1110 (b) 1101 (c) 1001 (d) 1111 (Ans. : a)
Q.13 Hexadecimal letters A through F are used for decimal equivalent values of :
(a) 1 through 6 (b) 9 through 14 (c) 10 through 15 (d) 11 through 17
(Ans. : c)
Q.14 Hexadecimal number F is equal to octal number _______ .
(a) 15 (b) 16 (c) 17 (d) 18 (Ans. : c)
Q.15 Binary number 1101 is equal to octal number _______ .
(a) 15 (b) 16 (c) 17 (d) 14 (Ans. : a)
Q.16 Convert binary 1001 to octal _______ .
(a) 98 (b) 118 (c) 11 (d) 108 (Ans. : c)
Q.17 Octal number 12 is equal to decimal number _______ .
(a) 8 (b) 11 (c) 9 (d) none (Ans. : d)
Q.18 The binary equivalent of the decimal member 5 is _______ .
A) 100 B) 101 C) 110 D) 1001. (Ans. : c)
+ VTU : Feb.-10
Conversion between Decimal, Octal, Hexadecimal and

Binary Numbers
Q.1 What is 3110 converted to binary ?

(a) 110001 (b) 011111 (c) 101011 (d) 111110 (Ans. : b)
TM

Q.2 What is the decimal value of the binary number 111110 ?

(a) 30 (b) 62 (c) 64 (d) 126 (Ans. : b)
Q.3 With the number 8BF16, what is the positional weight of the 8 ? + VTU : Jan.-14
(a) 16 (b) 256 (c) 4096 (d) 8192 (Ans. : b)
Q.4 What would be the binary result if a HEX value of F9 is added to a HEX 1 ?
(a) 011111001 (b) 011111101 (c) 011111010 (d) 100000000
(Ans. : c)
Q.5 What is the result when a decimal 5238 is converted to base 16 ?
(a) 327.375 (b) 12.166 (c) 1388 (d) 1476 (Ans. : d)
Q.6 What is the binary value of 12316 ?
(a) 100100011 (b) 001100011 (c) 111011111 (d) 110011100
(Ans. : a)
Q.7 What is the HEX value of a binary 1111111111 ?
(a) 3FF (b) 400 (c) 200 (d) FFF (Ans. : a)
Q.8 What is the binary equivalent of octal number 1126 ?
(a) 10110011000 (b) 010 101 110 (c) 1001010110 (d) 10010101110
(Ans. : c)
Q.9 Convert hexadecimal C0B to binary.
(a) 110000001011 (b) 110000001001 (c) 110000001100 (d) 110100001011
(Ans. : a)
Q.10 What is the resultant in binary of the decimal problem 49 + 01 = ?

(a) 01010101 (b) 00110101 (c) 00110010 (d) 00110001
(Ans. : c)
Q.11 The binary equivalent of decimal number 6 is _______ .
(a) 100 (b) 011 (c) 110 (d) 1001 (Ans. : c)
+ VTU : Jan.11
Q.12 (ABC)16 = (?)10
(a) 3000 (b) 4230 (c) 2748 (d) 2250 (Ans. : c)
+ VTU : Jan.11
Q.13 (11011)2 = (?)8
(a) (33)8 (b) (17)8 (c) (25)8 (d) (28)8 (Ans. : a)
+ VTU : Jan.11
Q.14 The decimal number 20 in hexadecimal code is _______ .
(a) 41 (b) 14 (c) 140 (d) 410 (Ans. : b)
+ VTU : July-11
Q.15 (25)10 = (?)2
(a) (00111)2 (b) (11001)2 (c) (11000)2 (d) (00011)2 (Ans. : b)
+ VTU : Feb-11
TM

Q.16 (10101111001
. )2 = (?)16
(a) (AB.2C)16 (b) (2C.B8)16 (c) (2B.C8)16 (d) (2C.2D)16 (Ans. : c)
+ VTU : Feb.-09
Q.17 2's complement of binary number 10110 is __________.
(a) 00011 (b) 01010 (c) 11100 (d) 11111 (Ans. : b)
+ VTU : Feb.-09
Q.18 (763.634)8 = (?)2
(a) (111110011110011100
. )2 (b) (101011001110011001
. )2
(c) (000011110.111100001)2 (d) (010101010.001100110)2 (Ans. : a)
+ VTU : Feb.-09
Q.19 (11011)2 = ( )8
(a) (33)8 (b) (17)8 (c) (25)8 (d) (28)8 (Ans. : a)
+ VTU : Feb.-09
Q.20 The 2's complement of 1100110 is
(a) 0011001 (b) 0011010 (c) 1100001 (d) 1100010. (Ans. : b)
+ VTU : Aug.-09
Q.21 The BCD representation of decimal 10 is _______ .
(a) 00001010 (b) 00001001 (c) 00010000 (d) 10100000. (Ans. : c)
+ VTU : Aug.-09
Q.22 The binary of (A5)16 is _______ .
(a) 00100111 (b) 00100101 (c) 10100101 (d) 10100011 (Ans. : c)
+ VTU : Aug.-09
Complement of Binary Numbers
Q.1 The two's complement of (1 0 0 1)2 is ____.

(a) 1001 (b) 0010 (c) 0110 (d) 0111 (Ans. : d)
+ VTU : July-11
Binary Arithmetic
Q.1 F16 + 1F16 in binary is ______.

(a) 101111 (b) 101110 (c) 111111 (d) 011111 (Ans. : b)
Q.2 (31)8 – (25)8 in binary is ______.

(a) 10000 (b) 01000 (c) 00100 (d) 00001 (Ans. : c)
Q.3 (64)16 – (46)8 in binary is _______. + VTU : Jan.-14

(a) 111101101 (b) 111101100 (c) 111110 (d) 1100110 (Ans. : c)
TM

Boolean Algebra Theorems
Q.1 _____________ is the mathematical representation used to show the relation between
the inputs and the outputs of a gate.
(a) Boolean expression (b) Characteristic equation (c) Both (Ans. : a)
Q.2 ______ is the Boolean expression for the EX-NOR gate.

(a) Y = A B + A B (b) Y = A B + A B (c) Y = A + B (Ans. : a)
Q.3 ______ is the Boolean expression for the EX-OR gate.

(a) Y = A B + A B (b) Y = A B + A B (c) Y = A B + AB (Ans. : a)
Q.4 The Boolean expression for ______ gate is Y = AB .
(a) NAND gate (b) NOR (c) NOT (Ans. : a)
Q.5 Y = A B + A B represents ______ gate.

(a) OR (b) EX-OR (c) EX-NOR (Ans. : b)
Q.6 The output expression of EX-NOR with inputs A and B is ______.

(a) A B + A B (b) A B + A B (c) AB + A B (Ans. : a)
Q.7 Y = A + B represents a ______ gate.
(a) NAND (b) NOR (c) OR (Ans. : a)
Q.8 Y = AB + A B represents ______ gate.

(a) OR (b) EX-NOR (c) EX-OR (Ans. : b)
Q.9 The analysis and simplification of the digital circuits are done using _______algebra.
(a) Boolean (b) canonical (c) none of these (Ans. : a)
Q.10 Only _______possible values are allowed in Boolean algebra.

(a) one (b) two (c) three (Ans. : b)
Q.11 A × A = ______.
(a) 0 (b) A (c) 1 (Ans. : a)
Q.12 A × 1 = ______.
(a) 0 (b) A (c) 1 (Ans. : b)
Q.13 0 × A = ______.
(a) 0 (b) A (c) 1 (Ans. : a)
Q.14 A× ______ = 0.
(a) 0 (b) A (c) 1 (Ans. : a)
Q.15 A + ______ = A .
(a) 1 (b) A (c) 0 (Ans. : c)
Q.16 A + AB = ______.
(a) 0 (b) A+B (c) A + B (Ans. : c)
TM

Q.17 A + A B = _________ .
(a) A + B (b) A + B (c) A + B (Ans. : b)
Q.18 A + AB = __________ .
(a) A + B (b) B (c) A + B (Ans. : a)
Q.19 A = A represents __________ law.
(a) commutative (b) associative (c) distributive (d) inversion
(Ans. : d)
Q.20 DeMorgan's first theorem is _________.
(a) A × A = 0 (b) A = A (c) A + A = A (d) ( AB) = A + B
(Ans. : d)
Q.21 DeMorgan's second theorem is _________.

(a) A × A = 0 (b) A = A (c) (A + B) = A × B (d) ( AB) = A + B
(Ans. : c)
Q.22 According to Boolean algebra which of the following relation is not valid ?
(a) X(YZ) = (XY) Z (b) X(Y+Z) = XY+XZ (c) X+XZ = X (d) X(X+Y) = 1
(Ans. : d)
Q.23 Simplify the following expression : F = ABC + AB C + ABC.

(a) F = AC + AB (b) F = AC + AB (c) F = AC + AB (d) F = AC + AB
(Ans. : a)
Q.24 It is required to determine the logical output of the circuit shown in figure, built using
NAND gates. Pick up the correct answer.
Output
(a) A × B (b) A + B (c) A + B (d) AB + AB

(Ans. : b)
Q.25 The expression AB + BC + BC when simplified is ______.

(a) A × B (b) C (c) AB + C (d) none (Ans. : c)
Q.26 Complement of expression AB + CD is _______.

(a) A + B (b) C + D (c) ( A + B ) × ( C + D) (d) none (Ans. : c)
Q.27 Simplify (A + B) (A + B).
(a) A (b) B (c) 1 (d) 0 (Ans. : b)
TM

Q.28 Simplify ABC + ABC + ABC + ABC.

(a) A (b) B (c) C (d) none (Ans. : c)
Q.29 Simplify Y = AB + AB.

(a) A (b) B (c) A+B (d) A–B (Ans. : a)
Q.30 The logic expression AB + A B can be implemented by given inputs A and B to a two
input _________.
(a) NOR (b) exclusive NOR gate
(c) exclusive OR gate (d) NAND gate (Ans. : b)
Q.31 A + AB = ________.
(a) AB (b) A (c) B (d) 1 + A (Ans. : b)
+ VTU : Jan.-11
Q.32 The complement of A + B + 1 is ________ .
(a) 0 (b) A + B + 1 (c) AB + 1 (d) 1 (Ans. : a)
+ VTU : Jan.-11
Q.33 Simplified form of Boolean expression of 1 + AB is
(a) 1 (b) AB (c) AB (d) A + B (Ans. : a)
+ VTU : Aug.-11
Q.34 Simplified of AB is ______.
(a) A + B (b) A + B (c) A + B (d) A + B (Ans. : b)
Q.35 DeMorgan theorem states that A + B = _________ . + VTU : Jan.-14

(a) A + B (b) A × B (c) AB (d) None. (Ans. : b)
Q.36 A + AB + A = _________ .
A) AB B) A + B C) A D) 0. (Ans. : c)
Q.37 The Boolean expression Y = A.B represents ________ .

A) OR gate B) XNOR gate C) AND gate D) NOT gate (Ans. : c)
Logic Gates
Q.1 The logical inversion or complement is presented by the _________operator.

(a) NOT (b) NAND (c) NOR (Ans. : a)
Q.2 The logical addition is presented by the __________ operator.

(a) AND (b) OR (c) NAND (Ans. : b)
Q.3 The logical ________is presented by the "AND" operator.

(a) multiplication (b) addition (c) subtraction (Ans. : a)
Q.4 ______ are the basic building blocks of all the digital circuits.
(a) MUX (b) Logic gates (c) Encoders (Ans. : b)
TM

Q.5 The electrical symbol illustrated below represents a : _______.
(a) OR gate (b) AND gate (c) NOR gate (d) NAND gate
(Ans. : b)
Q.6 The electrical symbol illustrated below represents a : ________.
(a) OR gate (b) Op-amp (c) NOR gate (d) NOT gate
(Ans. : d)
Q.7 The electrical symbol illustrated below represents a : _________.
(a) OR gate (b) Op-amp (c) NOR gate (d) NOT gate
(Ans. : c)
Q.8 For the electrical symbol illustrated below to represent "0" as it's output, the inputs must
be : _________.
(a) one input "on", the other "off". (b) both inputs "on".
(c) both inputs "off". (d) first input "off", the second "on".
(Ans. : c)
Q.9 For the electrical symbol illustrated below to represent "0" as it's output, the inputs must
be : _________.
(a) one input "1", the other "0". (b) both inputs "1".
(c) both inputs "0". (d) the top input "0", the bottom input "1".
(Ans. : b)
Q.10 For the electrical symbol given below to represent "1" as it's output, the inputs must be :
_________.
(a) one input "1", the other "0". (b) both inputs "1"
(c) both inputs "0". (d) the top input "0", the bottom input "1".
(Ans. : c)
TM

Q.11 The output of OR gate is logic zero when _________.

(a) any one input is logic 1 (b) two inputs are logic 1
(c) all inputs are logic 0 (Ans. : c)
Q.12 When all the inputs of a NAND gate are zero, the output of it is ______.
(a) high (b) low (c) none (Ans. : a)
Q.13 For a three input NAND gate the output is 0 only when _______ .
(a) all inputs logic 1 (b) all inputs logic 0
(c) any one input logic 1 (Ans. : a)
Q.14 For EX-NOR gate the output is 1 if ________ .

(a) even number of inputs is 0 (b) even number of inputs is 1
(c) odd number of inputs is 0 (d) odd number of inputs is 1 (Ans. : b)
Q.15 ______ gate output is logic 1 if and only if all its inputs are logic 0.
(a) OR (b) NOR (c) NAND (Ans. : b)
Q.16 A ______ gate represents a complement function.

(a) NOT (b) NOR (c) NAND (Ans. : a)
Q.17 The output of a logic gate can be one of two ______ .

(a) inputs (b) gates (c) states (d) none (Ans. : c)
Q.18 A NOT gate has _________.

(a) two inputs and one output (b) one input and one output
(c) one input and two outputs (d) none of above (Ans. : b)
Q.19 An OR gate has _________.

(a) two inputs and one output (b) one input and one output
(c) one input and two outputs (d) none of above (Ans. : a)
Q.20 Logic states can only be _____ or 0.

(a) 3 (b) 2 (c) 1 (d) 0 (Ans. : c)
Q.21 The output of a _____ gate is only 1 when all of its inputs are 1.
(a) NOR (b) EX-OR (c) AND (d) NOT (Ans. : c)
Q.22 The output of a two-input NOR gate is high _________.

(a) only if both the inputs are high
(b) only if both the inputs are low
(c) only if one input is high and the other is low
(d) if at least one of the inputs is high (Ans. : b)
Q.23 An XOR gate gives a high output _________.

(a) if there are odd number of 1's in the input
(b) if there are even number of 1's in the input
(c) if there are odd number of 0's in the input
(d) if there are even number of 0's in the input (Ans. : a)
TM

Q.24 An exclusive NOR gate is logically equal to _________.

(a) inverter followed by an XOR gate
(b) NOT gate followed by an exclusive OR gate
(c) exclusive OR gate followed by an inverter
(d) complement of a NOR gate (Ans. : c)
Q.25 The gate ideally suited for bit comparison is a _________.
(a) two input exclusive NOR gate (b) two input NOR gate
(c) two input NAND gate (d) two input exclusive OR gate (Ans. : a)
Q.26 Two input exclusive NOR gate gives high output _________.
(a) when one input is high and the other is low
(b) only when both the inputs are low
(c) when both the inputs are same
(d) only when both the inputs are high (Ans. : c)
Q.27 A table that contains all the possible combinations of the inputs and the corresponding
state of output of a logic gate is called ___________.
(a) truth table (b) excitation table (c) transition table (Ans. : a)
Q.28 Which logic gate has the following truth table ?
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
(a) An exclusive OR gate (b) A two-input AND gate

(c) A two-input OR gate (d) An exclusive NOR gate (Ans. : c)
Q.29 For a two input EX-OR gate the output is 1 when _______ .
(a) AB = 00 (b) AB = 11 (c) AB = 01 (Ans. : c)
Q.30 For a two input EX-OR gate the output is 0 when ________ .
(a) both inputs are equal (b) both inputs are not equal (Ans. : a)
Q.31 For EX-OR gate Y = 1 if ––––––– .

(a) odd number of inputs are 1 (b) even number of inputs are 1
(c) odd number of inputs are 0 (d) even number of inputs are 0 (Ans. : a)
Q.32 The output is high only when both the inputs are zero to a gate. The gate is
(a) AND (b) NOR (c) OR (d) NAND (Ans. : b)
+ VTU : Jan.-11
TM

Q.33 Universal gate is _______.

(a) NOT (b) AND (c) OR (d) NAND (Ans. : d)
+ VTU : Jan.-11
Q.34 Expression for EX-OR gate with inputs 'A' and 'B' is _______.
(a) A + B (b) AB + BA (c) A B (d) none of these
(Ans. : d)
Q.35 The output is high when all the inputs are high, such a gate is called ______ .
(a) NAND (b) NOR (c) AND (d) OR. (Ans. : c)
Q.36 For which gate when the two inputs A and B are equal the output is zero and otherwise
one ? +
VTU : Jan.-14
(a) NAND (b) NOR (c) EXNOR (d) EXOR (Ans. : d)
NAND and NOR Implementation
Q.1 The logical addition is presented by the __________ operator.

(a) AND (b) OR (c) NAND (Ans. : b)
Q.2 Y = A × B × C represents a ______ gate.

(a) AND (b) OR (c) NOR (Ans. : a)
Q.3 A NAND gate is equivalent to an AND gate plus a _____ gate put together.
(a) NOR (b) NOT (c) EX-OR (d) None (Ans. : b)
Q.4 The ______ and ______ gates are known as "Universal Gates".
(a) NAND, NOR (b) NAND, EX-OR (c) OR, AND (Ans. : a)
Q.5 A NAND gate is called a universal logic element because _________.
(a) it is used by everybody
(b) any logic function can be realized by NAND gates alone
(c) all the minimization techniques are applicable for optimum NAND gate realization
(d) many digital computers use NAND gates (Ans. : b)
Q.6 In order for output 'Y' to be a "1", inputs A, B and C must be :
A
B
Y
C
(a) A = 1, B = 0, C = 0 (b) A = 0, B = 0, C = 0
(c) A = 1, B = 0, C = 1 (d) A = 0, B = 1, C = 0 (Ans. : c)
Q.7 Which of these are universal gates ?

(a) Only NOR (b) Only NAND
(c) Both NOR and NAND (d) NOT, AND, OR (Ans. : c)
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Q.8 Universal gates are _____ and ________ . + VTU : Jan.-14

(a) NOT and NOR B) AND and OR
C) NAND and NOR D) EXOR and EX-NOR (Ans. : c)
NAND-NAND Implementation
Q.1 The NAND-NAND logic is equivalent to _______.

(a) AND-NOT logic (b) AND-OR logic (c) OR-AND logic (d) NOT-OR logic
(Ans. : b)
NOR-NOR Implementation
Q.1 The NOR-NOR logic is equivalent to ___________.

(a) AND-OR logic (b) NOT-AND logic (c) OR-NOT logic (d) OR-AND logic
(Ans. : d)
Half Adder and Full Adder
Q.1 To add two m-bit number, the number of required half adders is __________ .
m
(a) 2m – 1 (b) 2m (c) 2 – 1 (d) 2m + 1 (Ans. : a)
Q.2 The result of binary addition 1 + 1 is ––––––– .
(a) carry 0, sum 0 (b) carry 0, sum 1 (c) carry 1, sum 0 (d) carry 1, sum 1
(Ans. : c)
Q.3 The result of binary addition 1 + 1 + 1 is ––––––– .
(a) carry 0, sum 0 (b) carry 0, sum 1 (c) carry 1, sum 0 (d) carry 1, sum 1
(Ans. : d)
Q.4 Half adder circuit is ______ .
(a) half of an AND gate (b) a circuit to add two bits together
(c) half of a NAND gate (d) none of above (Ans. : b)
Q.5 A half adder has ––––––– inputs and –––––––– outputs. + VTU : Jan.-14
(a) 1, 1 (b) 1, 2 (c) 2, 1 (d) 2, 2 (Ans. : d)
Q.6 The addition of two bits is performed by using a ______ adder.
(a) half (b) full (c) parallel (Ans. : a)
Q.7 The sum and carry output of H.A. are 1 and 0, then its inputs are_______.
(a) both (b) and (c) (b) 0, 1 (c) 1, 0 (d) 1, 1 (Ans. : a)
Q.8 The addition of three bits is performed by using a ______ adder.
(a) half (b) full (c) flip-flop (Ans. : b)
Q.9 In half adder the addition is limited to ___ bits.
(a) 2 (b) 3 (c) 4 (Ans. : a)
Q.10 Sum output of half adder is = ___________ .
TM

(a) A B + A B (b) AB (c) A B + AB (Ans. : a)

Q.11 Carry output of half adder is = ____________ .
(a) A B + A B (b) A B (c) A B + AB (Ans. : b)
Q.12 The full adder can perform addition of ________ bits.
(a) 2 (b) 3 (c) 4 (Ans. : b)
Q.13 A half addition i.e. addition of two-bits can be achieved using ______ gate.
(a) EX-OR (b) EX-NOR (c) OR (Ans. : a)
Q.14 A half adder circuit is constructed by using 2-input EX-OR gate and 2-input _____ gate.
(a) EX-NOR (b) EX-OR (c) AND (Ans. : c)
Q.15 A 3 bit binary adder should be _________.
(a) 3 full adders (b) 2 full adders and 1 half adder
(c) 1 full adder and 2 half adders (d) 3 half adders (Ans. : b)
Q.16 The number of inputs and outputs in a full adder are _________.
(a) 2 and 1 (b) 2 and 2 (c) 3 and 3 (d) 3 and 2 (Ans. : d)
Q.17 A full adder can be realized using : _________.
(a) one half-adder, two OR gates (b) two half-adders, one OR gate
(c) two half-adders, two OR gates (d) none of these (Ans. : b)
Q.18 Which of the following is known as half-adder ?
(a) EX-OR gate (b) EX-NOR gate
(c) NAND gate (d) NOR gate (Ans. : a)
Q.19 The half adder circuit has input AB = 11. The logic levels of the S and C outputs will be
_________.
(a) S = 1, C = 1 (b) S = 0, C = 0 (c) S = 1, C = 0 (d) S = 0, C = 1
(Ans. : a)
Q.20 Full adder has _______ inputs.
(a) 1 b) 2 (c) 3 (d) 4 (Ans. : c)
+ VTU : Aug.-11
qqq
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Notes
TM

6 Flip-Flops
Chapter at a Glance
1. What is flip-flop ? One or
Q
more inputs
· Flip-flop is a bi-stable digital circuit, i.e., its
outputs have two stable states : logic 1 and Outputs
CLK input
logic 0.
· It is a sequential circuit; it requires a clock Q
signal to be applied at its inputs for operation.

Fig. 6.1 Flip-flop
· The Fig. 6.1 shows the block diagram of a
flip-flop. It has one or more inputs, two
outputs and a clock input. High
Leading Falling
· The Fig. 6.2 shows the clock signal. It is a edge Low edge
rectangular signal with 50 % duty cycle.
Time
· The flip-flop changes its outputs either at
the leading edge of the clock signal or at Fig. 6.2
the falling edge of the clock signal
according to the status of flip-flop input present at that time.
· The two outputs of flip-flop Q and Q always complements of each other.
2. Gated SR latch :
· It can easily be modified to create a latch that is sensitive to these inputs only when an
enable input is active. Such a latch with enable input is known as gated SR latch.
Ø Explain the working of NAND gate latch and NOR gate latch.
One-Bit Memory Cell
· The Fig. 6.3 shows the basic bistable element used in latches and flip-flops.
· The basic bistable element has two outputs Q and Q.
(6 - 1)
TM

Basic Electronics 6-2 Flip-Flops
A Q A Q A Q
A 1 1 1
B 2 Q B 2 Q B 2 Q
B
(a) NOT gate latch (b) NAND gate latch (c) NOR gate latch
Fig. 6.3 Gated Latch
· It has two cross-coupled inverters, i.e., the output of the first inverter is connected as an
input to the second inverter and the output of second inverter is connected as an input
to the first inverter.
· The basic bistable element circuit has two stable states logic 0 and logic 1, hence the
name 'bistable'.
· When A = 0, the output of inverter 1 is 1 (A), i.e., Q = 1.
· Since the output of inverter 1 is the input to the inverter 2, A = B = 1. Consequently,
the output of inverter 2, i.e., B is 0.
· Since the output of the inverter 2 is connected to the input of the inverter 1,
Q = B = A = 0.
· We have assumed same value for A. Thus, the circuit is stable with Q = A = B = 0 and
Q = A = B = 1.
· Using similar explanation it is easy to show that if it is assumed that A = 1, the basic
bistable element is stable with Q = A = B = 1 and Q = A = B = 0. This is a second
stable condition of the basic bistable element.
· The two stable states of basic bistable elements are used to store two binary elements, 0
and 1.
· In positive logic system, state Q = 1 is used to store logic 1, and state Q = 0 is used to
store logic 0.
· Two outputs are complementary. That is when Q = 0, Q = 1; and when Q = 1, Q = 0.
Important Points
1. The outputs Q and Q are always complementary.
2. The circuit has two stable states. The state corresponds to Q = 1 is referred to as 1
state or set state and state corresponds to Q = 0 is referred to as 0 state or Reset
state.
3. If the circuit is in the set (1) state, it will remain in the set state and if the circuit is
in the reset (0) state, it will remain in the reset state. This property of the circuit
TM

shows that it can store 1-bit of digital information. Therefore, the circuit is called a
1-bit memory cell.
4. The 1-bit information stored in the circuit is locked or latched in the circuit.
Therefore, this circuit is also referred to as a latch.
Ø Differentiate between latches and flip-flops.
· Latches and flip-flops are the basic building blocks of the most sequential circuits.
· The main difference between latches and flip-flops is in the method used for changing
their state.
· A simple latch forms the basis for the flip-flop.
· Latches are controlled by enable signal, and they are level triggered, either positive
level triggered or negative level triggered.
· The output state is free to change according to the S and R input values, when active
level is maintained at the enable input.
· Flip-flops are pulse or clock edge triggered instead of level triggered.
Introduction
Q.1 Which of the following is a bistable logic circuit ?

(a) Decoder (b) Multiplexer (c) De-Multiplexer (d) Flip-Flop
(Ans. : c)
Q.2 How many stable states do flip flops have ?
(a) 0 (b) 1 (c) 2 (d) 3
(Ans. : c)
Q.3 NAND gates act as _______ in the circuit shown in Fig. 6.4.
Fig. 6.4
(a) AND gate (b) OR gate (c) INV gate (d) none of these
(Ans. : c)
TM

Q.4 Fig. 6.5 shows _______ .
Fig. 6.5
(a) inverter (b) cross-coupled inverter
(c) flip-flop (d) none of these
(Ans. : b)
Q.5 The basic bistable element stores ______ bit information.
(a) 0 (b) 1 (c) 2 (d) 3
(Ans. : b)
SR Latch / RS Latch
Q.1 What does Fig. 6.6 show ?
S
(set) 1 3 Q
R 4 Q
(Reset) 2
Fig. 6.6
(a) Cross coupled inverter (b) 1-bit memory cell
(c) SR Latch (d) SR flip-flop
(Ans. : c)
Q.2 In SR latch S = R = 0 ______ .
(a) 1 and 0 (b) 0 and 1
(c) no change in states (d) undefined
(Ans. : c)
Q.3 Which of the following condition is avoided in SR latch ?
(a) S = R = 0 (b) S = R = 1 (c) S = 1 and R = 0 (d) None of these
(Ans. : b)
Q.4 If enable input EN = _______ , gated SR latch will operate otherwise there is no change.
(a) 1 (b) 0 (c) 1 or 0 (d) None of these
(Ans. : a)
TM

Q.5 In gated SR latch if S = _______, R = _______ and E = _______, indeterminate state

occurs.
(a) 1, 1, 1 (b) 1, 0, 1 (c) 0, 1, 1 (d) 1, 0, 0
(Ans. : a)
Gated SR Latch
Q.1 A latch with _____ input is known as gated RS latch.

(a) disable (b) clock (c) enable (d) both (a) and (b)
(Ans. : c)
Latches Vs. Flip-flops
Q.1 A flip-flop is a _________.

(a) combinational circuit (b) memory element
(c) arithmetic element (d) memory or arithmetic
(Ans. : b)
Q.2 –––––– is also known as 1-bit memory cell.
(a) Flip-flop (b) Register (c) Gate
(Ans. : a)
Q.3 The condition S = 0, R = 1 _______ the output of flip-flop.
(a) resets (b) sets (c) no change in
(Ans. : a)
qqq
TM

Notes
TM

Microprocessors and
7 Microcontrollers
Chapter at a Glance
1. Introduction to Microprocessor
1. Program Counter : The program counter gives the address of memory location from
where the next instruction is to be fetched.
2. Instruction Register : Instruction read from memory is loaded into the instruction
register. It is then send to the instruction decoder. The instruction decoder decodes
the instruction and gives decoded signals as an input to the control unit.
3. Arithmetic Logic Unit (ALU) : The ALU of the microprocessor performs arithmetic
and logic operations such as add, subtract, AND, OR, exclusive-OR, complement,
shift right, shift left and so on.
4. A Register (Accumulator) : In most of the microprocessors register A gives data for
the ALU and after performing the operation, the resulting data word is sent to the
register A and stored there. This special register, where the result is accumulated is
commonly known as accumulator.
5. Status Register : The status register is used to store the results of certain condition
such as result is zero, negative etc., when certain operations are performed during
execution of the program. The status register is also referred to as flag register.
6. Control Unit : The control unit is responsible for working of all other parts of the
microprocessor together. It maintains the synchronization in operation of different
parts in the microprocessor. The control unit receives the signal from instruction
decoder and generates the control signals necessary to carry out the instruction
execution.
7. Bus : A microprocessor communicates with memory and I/O devices with a common
communication path called bus. There are three types of buses : address bus, data
bus and control bus.
(7 - 1)
TM

Basic Electronics 7-2 Microprocessors and Microcontrollers
8. Stack Pointer (SP) : The stack is a reserved area of the memory in the RAM where
temporary information may be stored. A 16-bit stack pointer is used to hold the
address of the most recent stack entry in 8085 microprocessor.
9. Special Function Registers (SFRS) : The group of registers, implemented to perform
special functions and are located immediately above the 128 bytes of RAM are called
special function registers.
10. Stack : The stack refers to an area of internal RAM that is used to store and retrieve
data quickly.
11. Top of Stack : The stack pointer register is used by the 8051 to hold an internal
RAM address that is called top of stack.
Ø Explain architectural features of 8085.

The features of 8085 include :
1. It is an 8-bit microprocessor i.e. it can accept, process, or provide 8-bit data
simultaneously.
2. It operates on a single + 5 V power supply connected at VCC; power supply ground

is connected to Vss.
3. It operates on clock cycle with 50 % duty cycle.
4. It has on chip clock generator. This internal clock generator requires tuned circuit like
LC, RC or crystal. The internal clock generator divides oscillator frequency by 2 and
generates clock signal, which can be used for synchronizing external devices.
5. It can operate with a 3 MHz clock frequency. The 8085A-2 version can operate at the
maximum frequency of 5 MHz.
6. It has 16 address lines, hence it can access (2 16 ) 64 kbytes of memory.
7. It provides 8-bit I/O addresses to access (28 ) 256 I/O ports.
8. In 8085, the lower 8-bit address bus (A 0 - A 7 ) and data bus (D0 - D7 ) are multiplexed
to reduce number of external pins. But due to this, external hardware (latch) is
required to separate address lines and data lines.
9. It supports 74 instructions with the following addressing modes :
a) Immediate b) Register c) Direct d) Indirect e) Implied.
TM

10. The Arithmetic Logic Unit (ALU) of 8085 performs :
a) 8-bit binary addition with or without carry.
b) 16-bit binary addition. c) 2 digit BCD addition.
d) 8-bit binary subtraction with or without borrow.

e) 8-bit logical AND, OR, EX-OR, complement (NOT), and bit shift operations.
11. It has 8-bit accumulator, flag register, instruction register, six 8-bit general purpose
registers (B, C, D, E, H and L) and two 16-bit registers (SP and PC). Getting the
operand from the general purpose registers is more faster than from memory. Hence
skilled programmers always prefer general purpose registers to store program
variables than memory.
12. It provides five hardware interrupts : TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.
13. It has serial I/O control which allows serial communication.
14. It provides control signals (IO/M, RD, WR) to control the bus cycles and hence
external bus controller is not required.
15. The external hardware (another microprocessor or equivalent master) can detect
which machine cycle microprocessor is executing using status signals (IO/M, S0, S1).
This feature is very useful when more than one processors are using common system
resources (memory and I/O devices).
16. It has a mechanism by which it is possible to increase its interrupt handling capacity.
17. The 8085 has an ability to share system bus with direct memory access controller.
This feature allows to transfer large amount of data from I/O device to memory or
from memory to I/O device with high speeds.
18. It can be used to implement three chip microcomputer with supporting I/O devices
like IC 8155 and IC 8355.
Ø Give the comparison between microprocessor and microcontroller.
Sr. No. Microprocessor Microcontroller
1. Microprocessor contains ALU, control unit Microcontroller contains microprocessor,

(clock and timing circuit), different register memory (ROM and RAM), I/O interfacing circuit
and interrupt circuit. and peripheral devices such as A/D converter,
serial I/O, timer etc.
2. It has many instructions to move data It has one or two instructions to move data
between memory and CPU. between memory and CPU.
TM

3. It has one or two bit handling instructions. It has many bit handling instructions.
4. Access times for memory and I/O devices Less access times for built-in memory and I/O
are more. devices.
5. Microprocessor based system requires Microcontroller based system requires less

more hardware. hardware reducing PCB size and increasing the
reliability.
6. Microprocessor based system is more Less flexible in design point of view.

flexible in design point of view.
7. It has single memory map for data and It has separate memory map for data and
code. code.
8. Less number of pins are multifunctioned. More number pins are multifunctioned.
Ø What are the main features of 8051 microcontroller ?
The features of the 8051 family are as follows :

1. 4096 bytes on - chip program memory.
2. 128 bytes on - chip data memory.
3. Four register banks.
4. 128 user-defined software flags.
5. 64 kilobytes each program and external RAM addressability.
6. One microsecond instruction cycle with 12 MHz crystal.
7. 32 bidirectional I/O lines organized as four 8-bit ports (16 lines on 8031).
8. Multiple mode, high-speed programmable serial port.
9. Two multiple mode, 16-bit timers/counters.
10. Two-level prioritized interrupt structure.
11. Full depth stack for subroutine return linkage and data storage.
12. Direct byte and bit addressability.
13. Binary or decimal arithmetic.
14. Signed-overflow detection and parity computation.
15. Hardware multiple and divide in 4 msec.
16. Integrated boolean processor for control applications.
17. Upwardly compatible with existing 8084 software.
TM

Ø 1. Explain the operation of stack in 8051.
Ø 2. Define SP.
The stack refers to an area of internal RAM that is used to store and retrieve data quickly.
The stack pointer register is used by the 8051 to hold an internal RAM address that is
called top of stack. The stack pointer register is 8-bit wide. It is increased before data is
stored during PUSH and CALL instructions and decremented after data is restored during
POP and RET instructions.
The stack array can reside anywhere in on-chip RAM. The stack pointer is initialized to
07H after a reset. This causes the stack to begin at location 08H. The operation of stack
and stack pointer is illustrated in Fig. 7.1.
On-chip RAM On-chip RAM On-chip RAM
08 09
09
SP 07 08
Data 08
06 SP 07
Stack pointer SP SP+1 07
(a) Status of stack and (b) Store operation

stack pointer of reset
Data 1 09 Data 2 09
SP Data 2 08 Read 08
Data 3 07 SP SP–1 07
Stack pointer
(c) Read operation

Fig. 7.1
The stack may overwrite data in the register banks, bit-addressable RAM and scratch-pad
RAM. Thus to avoid conflict with the register, bit-addressable RAM and scratch-pad RAM
data, the stack is initialized at a higher location in the internal RAM.
Introduction to Microprocessor
Q.1 The microprocessor consists of __________ .

(a) SP (b) ALU (c) PC (d) All of these
(Ans. : d)
Q.2 ___________ is not a part of microprocessor.
(a) ALU (b) Control unit (c) Memory and I/O devices
(Ans. : c)
TM

Q.3 A microprocessor chip performs the function of _________.

(a) ROM (b) RAM
(c) peripheral devices (d) control unit and ALU
(Ans. : d)
Q.4 A microprocessor is called an n-bit microprocessor depending on _________.
(a) number of registers (b) size of data bus
(c) size of address bus (d) none of these
(Ans. : b)
Q.5 ALU stands for_________ .
(a) arithmetic logic unit (b) array logic unit
(c) none of these.
(Ans. : a)
Q.6 Which parts of the computer perform arithmetic calculations ?
(a) ALU (b) Registers (c) Logic bus (d) None of above
(Ans. : a)
Q.7 The _______ performs all the computations in a microprocessor.
(a) ALU (b) control unit (c) register array
(Ans. : a)
Q.8 The accumulator's main purpose is _________.
(a) temporary data storage
(b) keeping track of the next instruction to be executed
(c) selecting which peripheral should be addressed
(d) storing instructions
(Ans. : a)
Q.9 Generally result is accumulated in _______ register.
(a) accumulator (b) SP (c) PC
(Ans. : a)
Q.10 The CPU stands for ________ .
(a) central processing unit (b) control processing unit (c) central process unit
(Ans. : a)
Q.11 Microprocessor communicates with the outside world through the __________ .
(a) memory (b) I/O devices (c) ALU
(Ans. : b)
Q.12 _________ register gives the address of the memory location from where the next
instruction is to be fetched.
(a) Accumulator (b) SP (c) PC
(Ans. : c)
Q.13 Program counter is used to _________.
(a) store address of the next instruction to be executed
(b) store temporary data to be used in arithmetic operations
TM

(c) store the status of the microprocessor

(d) none of these
(Ans. : a)
Architecture of 8085
Q.1 8085 is an ____ bit microprocessor.

(a) 8 (b) 12 (c) 16 (d) 32
(Ans. : a)
Q.2 8085 is a microprocessor _____.
(a) single chip (b) double chip (c) multi chip (d) both (a) and (c)
(Ans. : a)
Q.3 8085 is a _____ device.
(a) CMOS (b) PMOS (c) NMOS (d) None of these
(Ans. : c)
Q.4 8085 microprocessor is ____ pin dual-in-line package.
(a) 40 (b) 20 (c) 30 (d) 28
(Ans. : a)
Q.5 For 8085, VCC is ______.
(a) + 5 V (b) – 5 V (c) ± 5 V (d) + 6 V
(Ans. : a)
Q.6 For 8085, VSS is ______.
(a) + 5 V (b) – 5 V (c) GND (d) – 6 V
(Ans. : c)
Q.7 Which of the following microprocessor is an 8 bit microprocessor ?
(a) 8051 (b) 8086 (c) 68000 (d) 8085
(Ans. : d)
Q.8 An 8-bit microprocessor signifies that it has ____.
(a) an 8 bit address bus (b) an 8 bit control bus
(c) 8 interrupt lines (d) an 8 bit data bus
(Ans. : d)
Q.9 A microprocessor is capable of addressing 64 kbytes of memory. Its address bus width is
____.
(a) 8 (b) 12 (c) 16 (d) 20
(Ans. : c)
Q.10 8085 has a clock cycle with ____ duty cycle.
(a) 20 % (b) 40 % (c) 50 % (d) 60 %
(Ans. : c)
Q.11 8085 has ____ address lines.
(a) 14 (b) 15 (c) 16 (d) 18
(Ans. : c)
TM

Q.12 8085 can access ____ of memory.

(a) 64 kbits (b) 64 kbytes (c) 64 Mbits (d) 64 Mbytes
(Ans. : b)
Q.13 8085 has _____ I/O addresses.
(a) 8 bit (b) 16 bit (c) 8 byte (d) 16 byte
(Ans. : a)
Q.14 8085 can access ____ I/O ports.
(a) 252 (b) 254 (c) 255 (d) 256
(Ans. : d)
Q.15 8085 supports ____ instructions.
(a) 76 (b) 75 (c) 72 (d) 74
(Ans. : d)
Q.16 If a processor is capable of addressing 2 Mbytes of memory, its data bus width is ____.
(a) 8 (b) 16 (c) 16 (d) cannot be predicted
(Ans. : d)
Q.17 A number of 1 bit registers used in 8085 to indicate certain conditions are usually referred
to as _____.
(a) flags (b) shift registers (c) counters (d) latches
(Ans. : a)
Q.18 A microprocessor performs the same functions as ____.
(a) memory of a computer (b) CPU of a computer
(c) output device of a computer (d) input device of a computer
(Ans. : b)
Q.19 A microprocessor is a ___.
(a) LSI device (b) MSI device (c) both (a) and (b) (d) none of these
(Ans. : a)
Q.20 W and Z registers of 8085 are _____ registers.
(a) temporary (b) general purpose (c) special purpose (d) sixteen bit
(Ans. : a)
Q.21 _______ is temporary register.
(a) Accumulator (b) Flag registers
(c) Temporary data register (d) Stack pointer
(Ans. : c)
Q.22 Accumulator is a ____ register.
(a) general purpose (b) temporary (c) special purpose (d) 16 bit
(Ans. : c)
Q.23 Flag register is a _____ register.
(a) 16 bit (b) general purpose (c) temporary (d) special purpose
(Ans. : d)
Q.24 PC in a microprocessor ____.
(a) counts the number of programs being executed by the microprocessor.
(b) counts the number of interrupts handled by the microprocessor.
TM

(c) holds the address of next instruction that is to be executed.

(d) all of the above
(Ans. : c)
Q.25 If a microprocessor has an 8 bit opcode. The maximum possible number of opcodes for
this microprocessor will be ____.
(a) 266 (b) 200 (c) 256 (d) 486
(Ans. : c)
Q.26 PC is a _____ register.
(a) general purpose (b) 16 bit (c) special purpose (d) b and c
(Ans. : c)
Q.27 _____ is a 16 bit register.
(a) Temporary data register (b) W register
(c) Stack pointer (d) Flag register
(Ans. : c)
Pin Diagram of 8085
Q.1 SOD means _____.

(a) Single Output Data (b) Serial Output Data
(c) Standard Output Data (d) none of the above
(Ans. : b)
Q.2 SID means _____.
(a) Single Input Data (b) Serial Input Data
(c) Standard Input Data (d) none of the above
(Ans. : b)
Q.3 ______ is used to send data serially.
(a) SOD (b) SD (c) SID (d) SRD
(Ans. : a)
Q.4 _____ is used to receive data serially.
(a) SOD (b) SID (c) STD (d) SD
(Ans. : b)
Q.5 In 8085, internal clock generator divides the oscillator frequency by _____.
(a) 4 (b) 6 (c) 2 (d) 8
(Ans. : c)
Q.6 _____ signal of 8085 is used as a system clock for other devices.
(a) X1 (b) X2 (c) CLK OUT (d) None of these
(Ans. : c)
Q.7 CLK OUT frequency is ____ of the oscillator frequency.
(a) half (b) double (c) quadraple (d) thrice
(Ans. : a)
TM

Basic Electronics 7 - 10 Microprocessors and Microcontrollers
Q.8 ALE means _____.

(a) Address Latch Enable (b) Access Latch Enable
(c) Address Latch Error (d) Access Latch Error
(Ans. : a)
Q.9 When ____ , data is read from the selected memory location or I/O device port via data
bus.
(a) RD = 1 (b) RD = 0 (c) WR = 1 (d) WR = 0
(Ans. : b)
Q.10 The data bus in a mP based system is used for data transfer _____.
(a) between the mP and I/O devices (b) between the mP and memory
(c) between the I/O devices and memory (d) for all of the above
(Ans. : d)
Q.11 When _____ , the data is written into the selected memory location or I/O port via data
bus.
(a) WR = 1 (b) RD = 1 (c) WR = 0 (d) RD = 0
(Ans. : c)
Q.12 In 8085, _____ indicates whether I/O operation or memory operation is carried out.
(a) RD (b) WR (c) IO M (d) READY
(Ans. : c)
Q.13 In 8085, _____ signal is used to check whether the peripherals are ready or not for data
transfer.
(a) IO M (b) S0 and S1 (c) RD (d) READY
(Ans. : d)
Q.14 INTA means ____.
(a) Interrupt Address (b) Interrupt Accept
(c) Interrupt Access (d) Interrupt Acknowledge
(Ans. : d)
Q.15 In 8085, _____ signal indicates that another master is requesting for access of address
bus, data bus and control bus.
(a) HLDA (b) RESET IN (c) HOLD (d) SID
(Ans. : c)
Q.16 In mP 8085, HLDA is active _____ signal.
(a) High (b) Low (c) not defined (d) none of these
(Ans. : a)
Q.17 _____ is used to acknowledge HOLD request.
(a) INTA (b) HOLD (c) HLDA (d) SOD
(Ans. : c)
Q.18 PC = 0000H when _____.
(a) RESET IN = 1 (b) RESET OUT = 1 (c) RESET IN = 0 (d) RESET OUT = 0
(Ans. : c)
TM

Q.19 In 8085, for proper reset operation, reset signal must be held low for at least ____ clock
cycles.
(a) 4 (b) 3 (c) 2 (d) 1
(Ans. : b)
Q.20 RESET OUT is active ____ signal.
(a) High (b) Low (c) input (d) none of these
(Ans. : a)
Q.21 ____ signal indicates that 8085 is being reset.
(a) HOLD (b) HLDA (c) RESET IN (d) RESET OUT
(Ans. : d)
Bus Organization
Q.1 The built-in clock generator of 8085 consist of internal T flip-flop that ____.
(a) divides frequency by 2 (b) divides frequency by 4
(c) multiplies frequency by 2 (d) multiplies frequency by 4
(Ans. : s)
Q.2 The operating frequency of 8085 is always _____ the oscillator frequency.
(a) thrice of (b) twice of (c) same as (d) half of
(Ans. : d)
Q.3 IC 74LS373 is _______ latch.
(a) an 8 bit (b) 16-bit (c) 32 bit (d) 64 bit
(Ans. : a)
Q.4 In the reset circuit of 8085, at power on, ______ pin goes low.
(a) RESET IN (b) RESET OUT (c) RESET IN (d) RESET OUT
(Ans. : c)
Introduction to Microcontroller
Q.1 The __________ includes microprocessor, memory and I/O on a single chip.
(a) microprocessor (b) microcomputer (c) microcontroller
(Ans. : c)
Q.2 _________ holds the opcode of the instruction.
(a) IR (b) SP (c) PC
(Ans. : a)
Q.3 In _____________, more number of pins are multifunctional.
(a) microprocessor (b) microcontroller (c) none of these
(Ans. : b)
Q.4 The microcontroller has built-in ______________.
(a) ROM (b) parallel I/O (c) serial I/O (d) all of these
(Ans. : d)
TM

Introduction to 8051 Microcontroller
Q.1 The 8051 is _____ microcontroller.

(a) 32 bits (b) 16 bits (c) 12 bits (d) 8 bits
(Ans. : d)
Q.2 The 8051 microcontroller was designed by _____.
(a) Intel (b) Microsoft (c) Motorola (d) IBM
(Ans. : a)
Q.3 8051 has ______ on-chip program memory.
(a) 1024 bytes (b) 4096 bytes (c) 2048 bytes (d) 4096 bits
(Ans. : b)
Q.4 8051 has ______ on-chip data memory.
(a) 256 bytes (b) 256 bits (c) 128 bytes (d) 128 bits
(Ans. : c)
Architecture of 8051
Q.1 8051 has ______ register banks.

(a) 2 (b) 6 (c) 8 (d) 4
(Ans. : d)
Q.2 8051 has ______ user defined software flags.
(a) 128 (b) 8 (c) 16 (d) 256
(Ans. : a)
Q.3 8051 has ______ program and external RAM addressability.
(a) 16 kBytes (b) 64 kBytes (c) 32 kBits (d) 64 kBits
(Ans. : b)
Q.4 8051 has one microsecond instruction cycle with ______ crystal.
(a) 12 kHz (b) 12 mHz (c) 12 MHz (d) 12 Hz
(Ans. : c)
Q.5 8051 has 32 ______ I/O lines.
(a) multidirectional (b) unidirectional (c) bidirectional (d) none of these
(Ans. : c)
Q.6 8051 has ______ 8 bit ports.
(a) 4 (b) 6 (c) 2 (d) 8
(Ans. : a)
Q.7 8052 has an extra ______ of RAM than the 8051 microcontroller.
(a) 128 bits (b) 256 bytes (c) 512 bits (d) 128 bytes
(Ans. : d)
Q.8 8052 has an extra ______ of ROM than the 8051 microcontroller.
(a) 4K (b) 2K (c) 4M (d) 2M
(Ans. : a)
TM

Q.9 8751 microcontroller has 4K of ______ instead of ROM.

(a) EEPROM (b) EPROM (c) PROM (d) Both (b) and (c)
(Ans. : b)
Q.10 The CPU of 8051 consists of ______ arithmetic and logic unit.
(a) 8 bit (b) 16 bit (c) 14 bit (d) 12 bit
(Ans. : a)
Q.11 The CPU of 8051 has ______ PC and DPTR.
(a) 16 byte (b) 16 bit (c) 8-bit (d) 24-bit
(Ans. : b)
Q.12 8051 has an accumulator of ______ bit.
(a) 8 (b) 12 (c) 4 (d) 16
(Ans. : a)
Q.13 Register B of 8051 is a ______ register.
(a) flag (b) special function (c) general purpose (d) none of these
(Ans. : c)
Q.14 The internal address of DPH is ______.
(a) 83 H (b) 82 H (c) 81 H (d) 80 H
(Ans. : a)
Q.15 The internal address of DPL is ______.
(a) 83 H (b) 82 H (c) 81 H (d) 80 H
(Ans. : b)
Q.16 PSW means ______.
(a) Program Standard Word (b) Program Select Word
(c) Program Status Word (d) None of the above
(Ans. : c)
Q.17 PSW of 8051 is known as ______.
(a) general purpose register (b) serial register
(c) flag register (d) special function register
(Ans. : c)
Q.18 ______ flag of 8051 is set if there is an overflow out of bit 7.
(a) P (b) OV (c) FO (d) CY
(Ans. : d)
Q.19 ______ flag also serves as a borrow flag for subtraction.
(a) AC (b) FO (c) CY (d) OV
(Ans. : c)
Q.20 ______ flag is set when there is an overflow out of bit 3.
(a) CY (b) AC (c) FO (d) OV
(Ans. : b)
Q.21 CY means ______.
(a) carry flag (b) auxiliary carry flag
(c) overflow flag (d) both (a) and (b)
(Ans. : a)
TM

Q.22 AC means ______.

(a) carry flag (b) auxiliary carry flag
(c) overflow flag (d) both (a) and (b)
(Ans. : b)
Q.23 ______ select the working register bank.
(a) CY (b) RS1 – RS0 (c) FO (d) P
(Ans. : b)
Q.24 Bank 0, of register bank is selected when ______.
(a) RS1 = RS0 = 0 (b) RS1 = 0, RS0 = 1
(c) RS1 = 1, RS0 = 0 (d) RS1 = RS0 = 1
(Ans. : a)
Q.25 Bank 1, of register bank, is selected when ______.
(a) RS1 = RS0 = 0 (b) RS1 = 1, RS0 = 0
(c) RS1 = 0, RS0 = 1 (d) RS1 = RS0 = 1
(Ans. : c)
Q.26 When RS1 = 1 and RS0 = 0, ______ of register bank is selected.
(a) bank 3 (b) bank 2 (c) bank 1 (d) bank 0
(Ans. : b)
Q.27 When RS1 = 1 and RS0 = 1, ______ of register bank is selected.
(Ans. : d)
Q.28 ______ flag is set, when the result of signed number operation is too large which causes
high-order bit to overflow into the sign-bit.
(a) AC (b) OV (c) P (d) CY
(Ans. : b)
Q.29 P flag is defined by number of ones present in the ______.
(a) DPH (b) register b (c) accumulator (d) DPL
(Ans. : c)
Q.30 P = ___ , if number of 1's are even.
(a) 0 (b) 1
(c) cannot be predicted (d) none of the above
(Ans. : a)
Q.31 ______ are located immediately above 128 bytes of RAM, in 8051.
(a) Special function register. (b) Flag register
(c) General purpose registers (d) Accumulator
(Ans. : a)
Q.32 Special function registers are between ______ and ______.
(a) 00 H and FF H (b) 71 H and F0 H (c) 80 H and FF H (d) 00 H and 80 H
(Ans. : c)
Q.33 SFR means ______.
(a) Special Function Registers (b) Special Flag Registers
TM

(c) Standard Function Registers (d) Standard Flag Registers

(Ans. : a)
Q.34 ______ are a sort of control table used for running and monitoring the operation of the
microcontroller.
(a) General Purpose Registers (b) Flag registers
(c) Special Function Registers (d) Both (a) and (b)
(Ans. : c)
Q.35 Address of accumulator is ______, in 8051.
(a) 82 H (b) 81 H (c) F0 H (d) E0 H
(Ans. : d)
Q.36 Address of register B is ______, in 8051.
(a) E0 H (b) F0 H (c) D0 H (d) 81 H
(Ans. : b)
Q.37 Address of PSW is ______, in 8051.
(a) E0 H (b) F0 H (c) D0 H (d) 81 H
(Ans. : c)
Q.38 Address of stack pointer is ______.
(a) E0 H (b) F0 H (c) D0 H (d) 81 H
(Ans. : d)
Q.39 Port 0 is located at ______, in 8051.
(a) 80 H (b) 81 H (c) 82 H (d) 83 H
(Ans. : a)
Q.40 P1 is located at ______, in 8051.
(a) 80 H (b) 90 H (c) A0 H (d) B0 H
(Ans. : b)
Q.41 P2 is located at ______, in 8051.
(a) 80 H (b) 90 H (c) A0 H (d) B0 H
(Ans. : c)
Q.42 Port 3 is located at ______, in 8051.
(a) 80 H (b) 90 H (c) A0 H (d) B0 H
(Ans. : d)
Q.43 IP is located at ______, in 8051.
(a) B0H (b) B8H (c) A8H (d) A0H
(Ans. : b)
Q.44 IE is located at ______, in 8051.
(a) B0 H (b) B8 H (c) A8 H (d) A0 H
(Ans. : c)
Q.45 ______ is located at 99 H.
(a) PCON (b) TH0 (c) TL0 (d) SBUF
(Ans. : d)
TM

Q.46 ______ is located at 87 H.

(a) RCAP2L (b) RCAP2H (c) PCON (d) SCON
(Ans. : c)
Q.47 Which of the following statement is true for 8051 mC ?
(a) 8051 has same data and program memory.
(b) 8051 has separate data and program memory.
(c) 8051 has only data memory.
(d) None of these.
(Ans. : b)
Q.48 The unique feature of 8051 is that ___ can manipulate one bit as well as 8 bit data types.
(a) SP (b) PC (c) ALU (d) PSW
(Ans. : c)
Q.49 Which of the following statement is true for 8051 ?
(a) Register B is used for the hardware multiply/divide operation.
(b) DPTR is used to perform arithmetic operation.
(c) SP is used to hold address of next instruction to be executed.
(d) All of the above.
(Ans. : a)
Q.50 _____ serves as a base register in indirect jumps, lookup table instructions and external
data transfer.
(a) SP (b) PC (c) DPTR (d) Accumulator
(Ans. : c)
Q.51 ____ holds the address of memory location from which the next instruction is to be
fetched.
(a) SP (b) PC (c) DPTR (d) Accumulator
(Ans. : b)
Q.52 B7 bit of PSW register is _____.
(a) CY (b) AC (c) F0 (d) RS1
(Ans. : a)
Q.53 P is ___ bit of PSW register.
(a) B0 (b) B1 (c) B2 (d) B3
(Ans. : a)
Q.54 B2 bit of PSW register is ____.
(a) RS1 (b) RS0 (c) 0V (d) P
(Ans. : c)
Q.55 AC is ____ bit of PSW register.
(a) B7 (b) B6 (c) B5 (d) B4
(Ans. : b)
Q.56 B3 bit of PSW register is ___.
(a) RS1 (b) RS0 (c) AC (d) CY
(Ans. : b)
TM

Q.57 F0 is ___ bit of PSW register.

(a) B7 (b) B6 (c) B5 (d) B4
(Ans. : c)
Q.58 B4 bit of PSW register is ___.
(a) AC (b) F0 (c) RS0 (d) RS1
(Ans. : d)
Q.59 Bank 0 of 8051 has a range ___.
(a) 00 H - 07 H (b) 08 H - 0F H (c) 10 H - 17 H (d) 18 H - 1F H
(Ans. : a)
Q.60 Bank 1 of 8051 has a range ___.
(a) 00 H - 07 H (b) 08 H - 0F H (c) 10 H - 17 H (d) 18 H - 1F H
(Ans. : b)
Q.61 10 H - 17 H is range for ____.
(Ans. : c)
Q.62 18 H - 1F H is range for ____.

(Ans. : d)
Q.63 Which statement is false for 8051 ?
(a) All 4 ports are bidirectional.

(b) All port pins are multiplexed except the pins of port 1.
(c) All 4 ports are unidirectional.
(Ans. : c)
Q.64 ____ can be used as a multiplexed address/data bus.
(a) Port 0 (b) Port 1 (c) Port 2 (d) Port 3
(Ans. : a)
Q.65 For proper RST operation ____.
(a) reset signal must be low
(b) reset signal must be high at least for two machine cycles, while oscillator is running
(c) reset signal must be high and then low for one machine cycle
(d) none of these
(Ans. : b)
Pin Description of 8051
Q.1 8051 is a ______ IC.

(a) 40 pin DIP (b) 60 pin DIP (c) 40 pin SIP (d) none of these
(Ans. : a)
Q.2 The ______ is used to access data bus of external memory.
(a) port 0 (b) port 1 (c) port 2 (d) port 3
(Ans. : a)
TM

Q.3 ______ outputs the lower order byte of the external memory address.
(Ans. : a)
Q.4 ______ outputs the higher order byte of external memory address.
(Ans. : c)
Q.5 All port pins of ______ are multifunctional.
(a) port 0 (b) port 1 (c) port 2 (d) port 3
(Ans. : d)
Q.6 Pin P3.7 is ______.
(a) RD (b) WR (c) T1 (d) T0
(Ans. : a)
Q.7 WR is ______.
(a) P3.7 (b) P3.6 (c) P3.5 (d) P3.4
(Ans. : b)
Q.8 Pin P3.5 is ______.
(a) T0 (b) T1 (c) RD (d) WR
(Ans. : b)
Q.9 Pin P3.4 is ______.
(a) T0 (b) T1 (c) RD (d) WR
(Ans. : a)
Q.10 INT1 pin number is ______.
(a) P3.4 (b) P3.3 (c) P3.2 (d) P3.1
(Ans. : b)
Q.11 INT0 pin number is ______.
(a) P3.4 (b) P3.3 (c) P3.2 (d) P3.1
(Ans. : c)
Q.12 Pin P3.1 is ______.
(a) INT1 (b) RD (c) WR (d) TXD
(Ans. : d)
Q.13 Pin P3.0 is ______.
(a) RXD (b) TXD (c) INT0 (d) INT1
(Ans. : a)
Q.14 For generating internal clock signal, external oscillator is connected to ______.
(a) XTAL1, XTAL2 (b) Reset (c) VCC (d) ALE
(Ans. : a)
Q.15 For proper reset operation, RST must be held high at least for ______ machine cycles,
while oscillator is running.
(a) 6 (b) 4 (c) 2 (d) 8
(Ans. : c)
Q.16 While reading external memory, PSEN is activated every ______ oscillator periods.
(a) 6 (b) 5 (c) 4 (d) 3
(Ans. : a)
TM

Q.17 ______ act as a read strobe to external program memory.

(a) ALE (b) EA (c) PSEN (d) RST
(Ans. : c)
Q.18 When EA = 1, the address range for internal program memory is ______ through ______.
(a) 0000H, 0FFFH (b) 0000H, FFFFH (c) 1000H, 0FFFH (d) 1000H, FFFFH
(Ans. : a)
Q.19 When EA = 1, the address range for internal program memory is ______ through ______.
(a) 0000H, 0FFFH (b) 0000H, FFFFH (c) 1000H, 0FFFH (d) 1000H, FFFFH
(Ans. : d)
Q.20 The alternate use of TXD pin is ____.
(a) serial data input (b) serial data output
(c) parallel data input (d) parallel data output
(Ans. : b)
Q.21 The alternate use of RXD pin is _____.
(a) serial data input (b) parallel data input
(c) serial data output (d) parallel data output
(Ans. : a)
Internal and External Memories
Q.1 8051 can access ____ program memory and _____ data memory.
(a) 32 K, 32 K (b) 32 K, 64 K (c) 64 K, 32 K (d) 64 K, 64 K
(Ans. : d)
Q.2 8051 has _____ of internal program memory and _____ of internal data memory.
(a) 4 kbytes, 256 bytes (b) 8 kbytes, 256 bytes
(c) 4 kbytes, 255 bytes (d) 8 kbytes, 255 bytes
(Ans. : a)
Q.3 In 8051 if RS1 = 0, RS0 = 1 then ______ is selected.
(Ans. : b)
Q.4 General purpose RAM is above bit addressable area from _____.
(a) 20H to 2FH (b) 30H to 37H (c) 30H to 7FH (d) 00H to 7FH
(Ans. : c)
Q.5 8051 has internal ROM with address space from ______.
(a) 000FH to 00FFH (b) 0000H to 0FFFH (c) 1000H to 1FFFH (d) 0010H to 0FFFH
(Ans. : b)
Stack and Stack Pointer
Q.1 Stack pointer is _____ wide.

(Ans. : b)
TM

Q.2 ______ is the area of internal RAM that is used to store and retrieve data immediately.
(a) Stack (b) Stack pointer (c) Queue (d) Program counter
(Ans. : a)
8051 Timers
Q.1 8051 has ____ timers.

(a) 2 (b) 4 (c) 6 (d) 8
(Ans. : a)
Q.2 Both T0 and T1 are ___ bit registers.
(a) 8 (b) 16 (c) 32 (d) 64
(Ans. : b)
Q.3 When M1 = 0, M0 = 0 timer ____ is selected.
(a) mode 0 (b) mode 1 (c) mode 2 (d) mode 3
(Ans. : a)
Q.4 For 8-bits timer (not autoreload) bits M1 M0 = ____.
(a) 0, 0 (b) 0, 1 (c) 1, 0 (d) 1, 1
(Ans. : a)
Q.5 When M1 = 1 and M0 = 0, ____ mode is selected.
(a) 8-bit timer (b) 16-bit timer (c) 8-bit auto-reload (d) none of these
(Ans. : c)
Q.6 For mode 3, M1 = ____ and M0 = ____.
(a) 0, 0 (b) 0, 1 (c) 1, 0 (d) 1, 1
(Ans. : d)
Q.7 If C T = 1, ____ operation is selected.
(a) read (b) write (c) timer (d) counter
(Ans. : d)
Q.8 Position of TF1 in TCON register is ___.
(a) TCON.4 (b) TCON.5 (c) TCON.6 (d) TCON.7
(Ans. : d)
Q.9 In TCON register, TR1 is at ___ position.
(Ans. : c)
Q.10 In TCON register, TCON.5 is ___.
(a) TF1 (b) TR1 (c) TF0 (d) TR0
(Ans. : c)
(a) TR0 (b) TR1 (c) TF0 (d) TF1
(Ans. : a)
Q.12 IE1 of TCON register is at ___ position.
(Ans. : b)
TM

Q.13 IT1 of TCON register is at ___ position.

(Ans. : b)
(a) IE1 (b) IT1 (c) IE0 (d) IT0
(Ans. : c)
(a) IE1 (b) IT1 (c) IE0 (d) IT0
(Ans. : d)
Q.16 Both timers in mode 0 are ___ counters.
(Ans. : a)
Q.17 Both timers in mode 1 are ____ counters.
(Ans. : c)
8051 Serial Port
Q.1 The serial port of 8051 is ____.

(a) half duplex (b) full duplex (c) simplex (d) none of these
(Ans. : b)
Q.2 In 8051, serial port uses register ___ to hold data.
(a) SCON (b) PCON (c) SBUF (d) none of these
(Ans. : c)
Q.3 Serial port of 8051 uses register SCON to ________.
(a) control data communication (b) control data rates
(c) hold data (d) all of the above
(Ans. : a)
Q.4 In 8051, register ____ is used by serial port to control data rates.
(a) SCON (b) PCON (c) SBUF (d) both (b) and (c)
(Ans. : b)
Q.5 Which of the following statements are true for serial port of 8051 ?
i) SBUF is located at 80H.
ii) Writing to SBUF loads data to be transmitted.
iii) Reading and writing SBUF done in same register.
iv) Reading SBUF accesses received data.
(a) i), iii) (b)ii), iv) (c) all (d) none
(Ans. : b)
Q.6 In 8051, serial data enters and exits through R ´ D in ___.
(a) mode 0 (b) mode 1 (c) mode 2 (d) mode 3
(Ans. : a)
Q.7 In mode 0 of 8051's serial port, the baud rate is fixed at ____.
TM

1 1
(a) the oscillator frequency (b) the oscillator frequency
32 12
1
(c) the clock frequency (d) none of these
8
(Ans. : b)
Q.8 In mode 1 of 8051 serial port, ____ bits are transmitted or received.
(a) 8 (b) 10 (c) 11 (d) cannot be predicted

(Ans. : b)
Q.9 The baud rate of mode 1 of 8051 serial port is ____.
(a) fixed (b) variable (c) cannot predict (d) none of these
(Ans. : b)
Q.10 In mode 2 of 8051 serial port, ____ bits are transmitted or received.
(a) 8 (b) 10 (c) 11 (d) variable
(Ans. : c)
Q.11 The baud rate of mode 2 of 8051 serial port is _____.
1
(a) programmable to the oscillator frequency
32
1
(b) programmable to the oscillator frequency
64
(c) fixed (d) either (a) or (b)
(Ans. : d)
Q.12 The baud rate of mode 3 of 8051 serial port is _____.
(a) fixed (b) variable
1 1
(c) the oscillator frequency (d) the oscillator frequency
12 64
(Ans. : b)
Q.13 In case of 8051 serial port, reception is initiated in mode 0 when ______.
(a) RI = 0, REN = 1 (b) RI = 1, REN = 0 (c) RI = 1, REN = 1 (d) RI = 0, REN = 0
(Ans. : a)
Q.14 Using Timer 1 to generate baud rate of 8051 serial port in mode 2, baud rate obtained is
_____.
K ´ Oscillator frequency K ´ Oscillator frequency
(a) (b)
32 ´ 12 ´ [(256 - TH1)] 32 ´ 64 ´ [(256 - TH1)]
K ´ Oscillator frequency
(c) (d) none of these
32 ´ 12 ´ [(260 - TH1)]
(Ans. : a)
Q.15 The equation to calculate TH1 for 8051 serial port in mode 1 is _____.
K ´ Oscillator frequency K ´ Oscillator frequency
(a) TH1 = 256 - (b) TH1 = 384 -
384 ´ Baud rate 256 ´ Baud rate
K ´ Oscillator frequency
(c) TH1 = 256 - (d) none of these
Baud rate
(Ans. : a)
TM

Q.16 Which of the following statements are false for 8051 serial port ?
i) Value of TH1 must be integer value.
ii) PCON is bit addressable
iii) The address of PCON is 97 H.
iv) When TH1 is FAH, for SMOD = 1,
the baud rate = 9600.
(a) i), iv) (b) ii), iii) (c) i), ii) (d) iii), iv)
(Ans. : b)
Q.17 For 8051 serial port mode 1, the baud rate using timer 2 is ___.
Oscillator frequency Osciallator frequency
(a) (b)
32 ´ [65536 - (RCAP2H, RCAP2L)] 64 ´ [65536 + (RCAP2H, RCAP2L)]
Osciallator frequency Osciallator frequency
(c) (d)
12 ´ [65536 - (RCAP2H, RCAP2L)] 32 ´ [65536 + (RCAP2H, RCAP2L)]
(Ans. : a)
Q.18 For 8051 serial port in mode 2, when SMOD = 1, baud rate = ___.
1
(a) oscillator frequency (b) oscillator frequency
12
1 1
(c) oscillator frequency (d) oscillator frequency
32 64
(Ans. : c)
Q.19 For 8051 serial port in mode 2, when SMOD = 0, baud rate = _____.
1
(a) oscillator frequency (b) oscillator frequency
12
1 1
(c) oscillator frequency (d) oscillator frequency
32 64
(Ans. : d)
Q.20 For 8051 serial port in mode 2, when SMOD bit is set by _____.
(a) ORL PCON, #80H (b) ORL PCON, #08H
(c) ORL PCON, #10H (d) ORL PCON, #01H
(Ans. : a)
Q.21 Which of the following statements are true for serial port of 8051 ?
i) During the transmission of stop bit,
8051 clears the TI flag, i.e. TI = 0.
ii) During the reception of stop bit, 8051
sets the RI flag, i.e. RI = 1.
iii) Baud rate in 8051 can be doubled by
doubling crystal frequency.
iv) Baud rate in 8051 can be doubled by
making SMOD bit in the PCON
register from 0 to 1.
(a) ii), iii), iv) (b) i) (c) all (d) none
(Ans. : a)
TM

8051 Interrupt Structure
Q.1 In ______ method, the microcontroller's program checks each of the I/O devices to see if
any device needs service and if so, provides the required service.
(a) polling (b) interrupt (c)calling (d) jump
(Ans. : a)
Q.2 In ______ method, the device that needs service, from microcontroller, sends an interrupt
signal to the microcontroller.
(a) polling (b) interrupt (c) calling (d) jump

(Ans. : b)
Q.3 An interrupt caused by an ______ signal is referred as a hardware interrupt.
(a) external (b) internal (c) both (a) and (b) (d) vector interrupts
(Ans. : a)
Q.4 Conditional interrupts or interrupts caused by special instructions are called ______.
(a) software interrupts (b) hardware interrupts
(c) both (a) and (b) (d) maskable interrupts
(Ans. : a)
Q.5 ______ interrupts are enabled and disabled under program control.
(a) Maskable (b) Non-maskable (c) Vectored (d) Non-vectored
(Ans. : a)
Q.6 When masked, processor ______ to activated interrupt.
(a) responds (b) does not respond (c) resets (d) None of these
(Ans. : b)
Q.7 Interrupts that cannot be masked under software control are called ______ interrupts.
(a) maskable (b) non-maskable (c) vectored (d) non-vectored
(Ans. : b)
Q.8 The interrupt for which starting address of the ISR is predefined is called ______.
(a) vectored interrupts (b) non-vectored interrupts
(c) maskable interrupt (d) none of the above
(Ans. : a)
Q.9 Response time for vectored interrupts is ______ than non-vectored interrupts.
(a) more (b) same (c) less (d) does not matter
(Ans. : c)
Q.10 ______ interrupt do not have a predefined starting address.
(a) Vectored (b) Non-vectored (c) Maskable (d) None of these
(Ans. : b)
Q.11 When 8051 is reset, the status of interrupts is ______.
(a) enabled (b) disabled (c) cannot predict (d) none of these
(Ans. : b)
Q.12 Bit position of EA is ______.
(a) IE.4 (b) IE.5 (c) IE.6 (d) IE.7
(Ans. : d)
TM

Q.13 IE.5 is ______.

(a) EA (b) ET2 (c) ES (d) ET1
(Ans. : b)
Q.14 Bit position of ES is ______.
(a) IE.1 (b) IE.2 (c) IE.3 (d) IE.4
(Ans. : d)
Q.15 IE.3 is ______.
(a) EA (b) ES (c) ET1 (d) ET2
(Ans. : c)
Q.16 IE.2 is ______.
(a) EX0 (b) EX1 (c) EX2 (d) ET1
(Ans. : b)
Q.17 Bit position of ET0 is ______.
(a) IE.0 (b) IE.1 (c) IE.2 (d) IE.3
(Ans. : b)
Q.18 Bit position of EX0 is ______.
(a) IE.0 (b) IE.1 (c) IE.2 (d) IE.3
(Ans. : a)
Q.19 ______ SFR is used to enable and disable the interrupt.
(a) IP (b) IE (c) P3 (d) PSW
(Ans. : b)
Q.20 By setting or clearing bits in ____, the priority of any interrupt can be decided.
(a) IP (b) IE (c) P3 (d) PSW
(Ans. : a)
Q.21 ____ are reserved bits of IP register.
(a) IP.7, IP.6, IP.5 (b) IP.7, IP.4, IP.3 (c) IP.5, IP.4, IP.3 (d) IP.6, IP.5, IP.4
(Ans. : a)
Q.22 IP.4 is ____.
(a) PS (b) PT1 (c) PX1 (d) PT0
(Ans. : a)
Q.23 Bit position of PT1 in IP is ____.
(a) IP.6 (b) IP.4 (c) IP.3 (d) IP.1
(Ans. : c)
Q.24 Bit position of PX1 is ____.
(a) IP.4 (b) IP.3 (c) IP.2 (d) IP.1

(Ans. : c)
Q.25 IP.1 is ___.
(a) PT1 (b) PX1 (c) PT0 (d) PX0

(Ans. : c)
Q.26 IP.0 is ___.
(a) PT1 (b) PX1 (c) PT0 (d) PX0

(Ans. : d)
TM

Q.27 Vector location of INT0 is ____.

(a) 0003H (b) 000BH (c) 0013H (d) 001BH
(Ans. : a)
Q.28 000B H is vector location of ___.
(a) INT0 (b) TF0 (c) INT1 (d) TF1
(Ans. : b)
Q.29 Vector location of TF1 is ____.
(a) 000BH (b) 0013H (c) 001BH (d) 0023H

(Ans. : c)
Q.30 0013H is vector location of ___.
(a) TF0 (b) INT0 (c) TF1 (d) INT1

(Ans. : d)
Q.31 Vector location of RI and TI is ____.
(a) 0013H (b) 001BH (c) 0023H (d) 002BH

(Ans. : c)
Q.32 INT0 has ___ priority.
(a) highest (b) lowest (c) medium (d) cannot be predicted

(Ans. : a)
Q.33 RI and TI has ____ priority.
(a) highest (b) lowest (c) medium (d) cannot be predicted
(Ans. : b)
Q.34 Pin P3.2 is ____.
(a) INT0 (b) INT1 (c) TF0 (d) TF1
(Ans. : a)
Q.35 The method in which microcontroller's program simply checks each of the I/O devices to
see if any device needs servicing is called ____.
(a) Pipelining (b) Polling method
(c) Interrupt method (d) Round Robin method
(Ans. : b)
Q.36 With help of _____, the interrupt transfers the program control to ISR.
(a) interrupt service routine (b) interrupt vector table
(c) accumulator (d) none of these
(Ans. : b)
Q.37 Interrupt caused by an external signal is referred as _____.
(a) software interrupt (b) hardware interrupt
(c) non-maskable interrupt (d) none of these
(Ans. : b)
Q.38 When _____ of interrupt is done, processor does not respond to the interrupt even though
the interrupt is activated.
(a) masking (b) unmasking (c) either (a) or (b) (d) none of these
(Ans. : a)
qqq
TM

8 Transducers
Chapter at a Glance
1. Transducer : A transducer is a device which converts a physical quality such as
temperature, pressure, displacement, force, etc., into equivalent electrical signal either
voltage or current.
2. Active Transducers : Active transducers are self generating type of transducers.
These transducers develop an electrical parameter (i.e. voltage/current) which is
proportional to the quantity under measurement. These transducers do not require
any external source or power for their operation.
3. Passive Transducers : Passive transducers do not generate any electrical signal by
themselves. To obtain an electrical signal from such transducers, an external source
of power is essential. Passive transducers depend upon the change in an electrical
parameter (R, L or C). They are also known as externally power driven transducers.
4. Primary Transducer : A transducer which converts physical quantity into mechanical
signal is called primary transducer.
5. Secondary Transducer : A transducer which converts mechanical signal into an
electrical signal is called secondary transducer.
6. Electrical Transducer : A transducer which gives output in electrical form it is
known as electrical transducer.
7. Sensor : Sensor is a device that produces a measurable response to a change in a
physical condition, such as temperature or thermal conductivity, or to a change in a
chemical concentration.
8. RTD : Electrical resistance of any metallic conductor varies according to temperature
changes. The primary electrical transducer which measures the temperature using
this phenomenon is called Resistance Temperature Detector (RTD) or Resistance
Thermometer.
9. Thermistor : Thermistors are semiconductor device which behave as thermal resistors
having negative temperature coefficient [NTC]; i.e. their resistance decreases as
temperature increases.
(8 - 1)
TM

Basic Electronics 8-2 Transducers
10. LVDT : LVDT (Linear Variable Differential Transducer) is a variable inductance

displacement transducer in which the inductance is varied according to the
displacement.
11. Photoelectric Effect : When the ray of light is incident on metal surface, the quantum
energy of electron is converted to kinetic energy causing the electrons to move and
thus resulting into flow of current in the metal. This phenomenon is known as
photoelectric effect.
Ø Draw the block diagram of instrumentation system and state the function of each block.
· Instrumentation plays an important role in industrial automation. The Fig 8.1 shows the
block diagram of a instrumentation system. It indicates the necessary elements and their
functions in a general measuring system.
Recorder
Printer
Signal Data Data
Measurand Transducer conditioning transmission presentation Display
elements element element
Controller
Fig. 8.1 Block diagram of an instrumentation system
· The functional elements in the block diagram can be grouped as

1. Transducer
2. Signal conditioning elements
3. Data presentation element
· Each element is made up of number of distinct components which perform a particular
function in the measurement procedure.
Measurand : Most of the times input to the instrumentation system is the physical
quantity such as temperature, pressure, displacement, force, etc. Such non-electrical input
quantity is called measurand.
Transducer : A transducer converts the non-electrical input measurand into a

proportional electrical signal such as voltage or current.
Signal Conditioning Element : The signal conditioning element processes the output of
the transducer and makes it suitable for control, recording and display.
The signal conditioning element performs one or more of the following functions :
1. Amplification of input signal 2. Analog to digital conversion
3. Filtering to remove noise 4. Modulation
TM

Data Transmission Element : The data transmission element provides the transmission
path required for sending the signal from signal conditioning element to the other stages
of the instrumentation system.
The examples of data transmission elements are :
1. Electrical cables/wires 2. Fiber optics cables 3. Radio links
Data Presentation Element : The transmitted data may be used for monitoring,
controlling or analysing purposes. So to get the information in proper form, according to
the purpose for which it is intended for, the data presentation element does the following
functions :
1. Amplification/attenuation 2. Demodulation 3. A/D or D/A conversion
4. Data conversion to make it suitable for controlling printing and display.
Controller, Recorder, Printer and Display Units : Controllers are used to make the
corrective action and control certain parameters. On the other hand, recorder, printer and
display units are used to monitor the variations in the certain parameters.
Ø Compare active and passive transducers.
Sr. Active Transducers Passive Transducers

No.
1. They do not require any external source or They require an external source of power for
power for their operation. their operation.
2. They are self generating type transducers. They are not self generating type transducers.
3. They produce electrical parameter such as They produce change in the electrical
voltage or current proportional to the physical parameter such as inductance, resistance or
parameter under measurement. capacitance in response to the physical
parameter under measurement.
4. Examples : Thermocouple, photocell, Examples : Thermistor, RTD, LDR, LVDT,

piezoelectric transducers. phototransistor.
Ø With neat diagram compare primary and secondary transducer.
Sr. No. Primary Transducer Secondary Transducer
1. A transducer which converts physical A transducer which converts mechanical

quantity into mechanical signal is signal into an electrical signal is called
called primary transducer. secondary transducer.
2. They do not require any electrical They require electrical power for their
power for their operation. operation.
Table 8.1
TM

Ø What is electrical transducer ?

· A transducer which gives output in electrical form it is known as electrical transducer.
· Actually, electrical transducer consists of two parts which are very closely related to
each other. These two parts are sensing or detecting element and transduction element.
The sensing or detecting element is commonly known as sensor.
· Definition states that sensor is a device that produces a measurable response to a
change in a physical condition, such as temperature or thermal conductivity, or to a
change in a chemical concentration.
· The transduction element transforms the output of the sensor to an electrical output, as
shown in the Fig. 8.2.
Non-electrical Sensor Electrical

Sensing Transduction
quantity element response element signal
Fig. 8.2 Electrical Transducer
Ø Explain the principle used in the resistive transducer.
· In general, the resistance of a metal conductor is given by,

rL
R =
A
where r = Resistivity of conductor (W m)
L = Length of conductor (m)
A = Area of cross-section of conductor (m 2 )
· The electrical resistive transducers are designed on the basis of the methods of variation
of any one of the quantities in above equation; such as change in length, change in area
of cross-section and change in resistivity.
· The resistance change due to the change in the length of the conductor is used in
translational or rotational potentiometers to measure linear or rotational displacement.
The change in resistance of conductor or semiconductor due to the strain applied is the
working principle of the strain gauge which is used to measure various physical
quantities such as pressure, displacement and force. The change in resistivity of
conductor due to the temperature variations causes change in resistance. This principle
is used to measure temperature.
Ø Explain the principle of operation of RTD.
· The resistance of a conductor changes when its temperature changes. This property is
used for the measurement of temperature. The resistance thermometer determines the
change in the electrical resistance of the conductor to determine the temperature.
TM

· The relationship between temperature and resistance of conductor is given by equation :

Rt = Rref [ 1 + a D t ]
Where
Rt : Resistance of the conductor at temperature t ºC,
Rref : Resistance of the conductor at the reference temperature, usually 0 ºC,
a : Temperature coefficient of the resistance,
D t : Difference between the temperature to be measured and reference temperature.
· Almost all metallic conductors have a positive temperature coefficient so that their
resistance increases with an increase in temperature.
· A high value of a is desirable in a temperature sensing element so that a substantial
change in resistance occurs for a relatively small change in temperature.
· This change in resistance [D R] can be measured with a Wheatstone bridge, the output
of which can be directly calibrated to indicate the temperature which caused the change
is resistance.
· At 0 ºC, the resistance of RTD is usually 100 W. By choosing R3 = 100 W and R1= R2, the
bridge is balanced at 0 ºC. Therefore, at 0 ºC voltage across B and D is zero and hence
the output voltage is zero.
· Any change in the RTD resistance due to change in temperature unbalances the bridge
circuit resulting voltage across B and D terminal. This voltage is proportional to the
change in the resistance and hence to the change in the temperature.
Amp Output
R2
R1
+ B
VCC D
–
RTD
R3
C
Fig. 8.3 RTD resistance measurement
Ø State the advantages of RTD.

1. High accuracy.
2. They can be calibrated to detect the actual temperatures to within ± 0.25 ºC up to
120 ºC and ± 0.5 ºC from 120 ºC to 550 ºC. Therefore they have wide temperature
range.
TM

3. Does not require temperature compensation. 4. Designed for fast response.

5. Excellent stability. 6. Good sensitivity.
7. High reproducibility.
Ø State the disadvantages of RTD.

1. Requires bridge circuit and external power source for measurement.
2. Chances of self heating due to current through RTD and thus the change in
resistance.
3. Large size as compared to thermocouples.
4. High cost.
Ø Compare types of temperature transducers or compare RTD with thermistors.
Parameter Resistance Thermometer Thermistor
Principle of operation Resistance increases with increase in Resistance decreases with increase in
temperature temperature.
Temperature coefficient Positive Negative
Characteristic Linear Nonlinear
Sensitivity Medium High
Speed of Response High High over narrow temperature range
Operating temperature – 200 ° C to + 650 ° C – 100 ° C to + 200 ° C

range
Type of transducer Passive Passive
Accuracy High Moderate
Size Large Small
Cost High Low
Material used Nickel, Copper, Platinum etc. Manganese, Nickel, Cobalt, Copper,
iron and uranium
Compensation Not required Not required
Applications Suitable for applications where Suitable for applications where

speed of response and accuracy are required temperature range is small
more important. and sensitivity requirement is high.
Ø State the advantages of LVDT.

A) Mechanical
1. Wide range of displacement : ± 0.005 to ± 25 inch.
2. Frictionless operation : No physical contact exists between the core and coil structure.
TM

3. Ruggedness : Good mechanical life.

4. Insensitive to temperature changes.
5. Highly repeatable response (performance).
B) Electrical
1. Linearity : Better (Output voltage is a linear function of mechanical displacement).
2. High sensitivity.
3. Resolution : Infinite.
4. Electrical isolation is better.
Ø State the disadvantages of LVDT.

1. Comparatively large displacements are necessary for appreciable differential output.
2. They are sensitive to stray magnetic fields. However, this interference can be reduced
by shielding.
3. The dynamic response is limited by the mass of the core.
4. Temperature affects the transducer.
Ø State the applications of LVDT.

1. The LVDT can be used in all applications where displacement ranging from fractions
of a few mm to a few cm have to be measured.
2. Acting as a secondary transducer, LVDT can be used as a device to measure force,
weight, and pressure etc. The force or pressure to be measured is first converted into
a displacement using primary transducers. Then this displacement is applied to an
LVDT, that acts as a secondary transducer, and converts the displacement into
proportional output voltage. In these applications the high sensitivity of LVDT is a
major attraction.
Ø Write a note on piezoelectric transducers.

The construction of the piezoelectric transducer is as shown in the Fig. 8.4.
Pressure
Force summing
member
Crystal Vo
Base
Fig. 8.4 Piezoelectric transducer
TM

A crystal is placed between solid base and force summing member. Metal electrodes plated
on to faces of piezoelectric crystal are taken out to measure output. The electrodes become
plates of the parallel plate capacitor. Thus it can be considered as charge generator. The
output voltage is given by
Q
Vo =
C
Ø Write a note on photoelectric transducers.

· The principle of photoelectric transducers is the physical radiation on matter.
· When the ray of light is incident on metal surface, the quantum energy of electron is
converted to kinetic energy causing the electrons to move and thus resulting into flow
of current in the metal. This phenomenon is known as photoelectric effect.
Photoelectric effects
Photoemissive Photoconductive Photovoltaic

(resistive)
Fig. 8.5
· Photo-emissive Transducer consist of a metallic cathode and an anode in an evacuated

tube. The electrons emitted by the cathode are attracted by the anode, causing the
current to flow which is proportional to the amount of light incident on the metal
surface. The optical radiation affects either the current developed voltage or resistance.
· Photovoltaic cells are self generating and are favoured for use in exposure meters.
· In photoresistive cells the resistance value change according to the illumination of
light. Photoresistive cells, are passive in nature. Photoresistive cell is also known as
Light Dependent Resistor (LDR).
· Photodiodes and photo transistors work in both photoemissive and photovoltaic modes.
Introduction
Q.1 _____ converts the non-electrical input measurand into a proportional electrical signal.
(a) Data presentation element (b) Data transmission element
(c) Signal conditioning elements (d) Transducer
(Ans. : d)
TM

Transducers
Q.1 Which of the following transducers are self generating type of transducers ?
(a) Active transducers (b) Passive transducers
(c) both (a) and (b) (d) none of these
(Ans. : a)
Resistive Transducers
Q.1 R = _______.
rA A rL
(a) (b) (c) (d) rLA
L L A
(Ans. : c)
Q.2 The working principle of _____ is, the change in resistance of conductor or semiconductor
due to the strain applied.
(a) Temperature transducer (b) Strain gauge
(c) RTD (d) Thermocouple
(Ans. : b)
Q.3 In _____, resistance of metallic conductor varies according to temperature changes.
(a) LVDT (b) strain guage
(c) piezoelectric transducer (d) resistance thermometer
(Ans. : d)
Q.4 For RTD, Rt = _______.
Rref
(a) Rref [ a D t ] (b) Rref [1 + a D t ] (c) Rref [1 – a D t ] (d)
1+ aDt
(Ans. : b)
Q.5 At 0°C what is the value of RTD ?
(a) 1 k W (b) 10 k W (c) 100 W (d) 100 k W
(Ans. : c)
Q.6 Which of the following statements are true for RTD ?
(a) RTD has low accuracy (b) RTD has excellent stability
(c) RTD requires temperature compensation (d) None of these
(Ans. : b)
Q.7 RTD cost is ______.
(a) high (b) low (c) moderate (d) varying
(Ans. : a)
Thermistors
Q.1 Thermistors have _____ temperature coefficient.

(a) negative (b) positive (c) variable (d) none of these
(Ans. : a)
TM

Basic Electronics 8 - 10 Transducers
Q.2 Which of the following are advantages fo thermistor ?

(i) Low cost (ii) Not suitable for wide temperature range
(iii) For narrow temperature range, response is fast
(iv) Small size
(v) Requires Wheatstone bridge for measurement.
(a) (i), (iii), (iv) (b) (ii), (iv) (c) (i), (ii), (iii), (iv) (v) (d) none of the above
(Ans. : a)
Q.3 Thermistor is used as ________.
(a) Strain gauge (b) Pressure transducer
(c) temperature transducer (d) none of these
(Ans. : c)
Comparison between Resistance Thermometer and Thermistor
Q.1 The operating temperature of resistance thermometer ranges from _____.

(a) – 300 ° C to + 600 ° C (b) – 200 ° C to + 600 ° C
(c) – 200 ° C to + 650 ° C (d) – 100 ° C to + 500 ° C
(Ans. : c)
Linear Variable Differential Transducer (LVDT)
Q.1 LVDT stands for ______.

(a) Linear variable differential transducer (b) Linear variable derivational transducer
(c) Linear variable division transducer (d) none of these
(Ans. : a)
Q.2 The core of LVDT is made up of _______.
(a) zinc alloy (b) nickel-iron alloy (c) aluminum (d) copper
(Ans. : b)
Active Electrical Transducers
Q.1 ________ transducer consist of a metallic cathode and an anode in an evacuated tube.
(a) Photo-emissive (b) LVDT
(c) Resistance thermometer (d) Thermistor
(Ans. : a)
Q.2 LDR means _______.
(a) Liquid display resistor (b) Linear differential resistor
(c) Light dependent resistor (d) Linear display resistor
(Ans. : c)
qqq
TM

9 Communication Systems
Chapter at a Glance
1. Baseband Signal : Regardless of whether the original information signals are analog
or digital, they are all referred to as “baseband signals”.
2. Baseband Transmission : In a communication system, the original information
signals (baseband signals) may be transmitted over the medium. Putting the original
signal directly into the medium is referred to as “baseband transmission”.
3. Modulation : The process by which the baseband signal modifies the carrier signal is
called modulation.
4. Amplitude Modulation : Amplitude Modulation (AM) is defined as system of
modulation in which the instantaneous value of the carrier amplitude changes in
accordance with the amplitude of the modulating signal.
5. Modulation Index : Relationship between the amplitudes of the modulating and
carrier signals is important and it is expressed in terms of their ratio, commonly
known as modulation index (m). It is also called modulation factor, modulation
coefficient or the degree of modulation.
6. Percentage Modulation : The modulation index is a number lying between 0 and 1,
and it is very often expressed as a percentage and called the percentage modulation.
7. Overmodulation in AM : In AM wave overmodulation takes place when modulation
index exceeds 1, i.e. when Vm > Vc . In overmodulated AM wave for some part of
time, amplitude of wave is zero and during this time, the amplitude of the carrier
signal is not proportional to the amplitude of modulating signal. This results loss of
information in the AM wave and hence the overmodulation must be avoided.
8. Detector : The detector, also called the demodulator, is the part of the receiver that
recovers the baseband signal or original modulating signal. It performs the inverse
operation to the transmitter modulator.
9. Frequency Modulation : When frequency of the carrier varies as per amplitude
variations of modulating signal, then it is called Frequency Modulation (FM).
Amplitude of the modulated carrier remains constant.
(9 - 1)
TM

Basic Electronics 9-2 Communication Systems
10. Frequency Deviation : The amount of change in carrier frequency produced by the
modulating signal is known as frequency deviation.
11. Modulation index for FM : The modulation index is the ratio of the frequency
deviation to the modulating frequency.
Frequency deviation
m f = Modulation index =
Modulating frequency
Important Formulae
c
1. l = ... wavelength
f
2. Modulation index for AM
Vm V - Vmin
m = = max
Vc Vmax + Vmin
3. Expression for AM wave

v m = Vm sinwm t
4. Frequency Spectrum of AM wave
fUSB = fc + fm
fLSB = fc - fm
mVc mVc
v AM = Vc sin wc t + cos ( wc - wm ) t - cos (wc + wm ) t
14243 2
144424443 1244424443 … (9.1)
carrier Lower side band Upper side band
mVc mVc
v AM = Vc cos wc t + cos ( wc - wm ) t + cos (wc + wm ) t
14243 1244424443 1244424443 … (9.1 (a))
carrier Lower side band Upper side band
5. Bandwidth of AM wave
BW = 2fm
6. Carrier power of AM wave
Vc2
Pc =
2R
7. Power in sideband of AM wave
m 2 Vc2 m2
PLSB = PUSB = = P
8R 4 c
8. Total power in AM wave
æ m2 ö
Ptotal = Pc ç 1 + ÷
ç 2 ÷
è ø
TM

9. Modulation index of AM wave interms of Ptotal and Pc
æP ö
m = 2 ç total - 1 ÷
è cP ø
10. Transmission efficiency of AM wave

m2
h =
2 + m2
11. Percentage transmission efficiency of AM wave
m2
%h = ´ 100 %
2 + m2
12. Total power of AM in case of simultaneous modulation
æ m2 ö
Ptotal = Pc ç 1 + t ÷
ç 2 ÷
è ø
13. Total modulation index of AM in case of simultaneous modulation
mt = m 21 + m 22 +.....+ m 2n
14. Bandwidth of AM with several modulation signals

BW = 2fmax
15. For practical diode detector
R 1 series with (R 2||R 3||R 4 )
Mmax =
R1 + R2
16. Expression for FM

Df
v = A sin éêwc t + sin wm t ùú
ë fm û
= A sin [wc t + m f sin wm t ]
17. Modulation index for FM
Df d
mf = =
fm fm
18. Bandwidth for FM

BWFM = 2[Df + fm ]
19. Expression for PM wave
v = A sin [wc t + m p sinwm t]
TM

Ø Explain the elements of communication system with the help of block diagram.
· Any electronic communication system can be represented in its basic form, as shown in
the Fig. 9.1.
Communication
Information
Transmitter channel or Receiver Destination
source
medium
Noise
source
Fig. 9.1 Block diagram of communication system

The basic components of communication systems are transmitter, a communication channel
or medium, and a receiver. Noise is inherently present in the channel or medium. It gets
added to the information being communicated.
The elements of communication system are as follows :
n Information
n Transmitter
n Communication channel or medium
n Noise
n Receiver
Information
· The communication systems communicate messages. The message comes from the
information sources. The two main sources of information are the ideas emanating from
the human brain and changes in any physical environment. It may contain human
voice, picture, code, data, music and their combinations.
· To have a better communication system, selective, but all information must be
communicated with no redundancy since we know no real information can be conveyed
by a redundant message.
Transmitter
· The transmitter is a collection of electronic circuits designed to convert the information

into a signal suitable for transmission over a given communication medium.
· Most of the times message that comes from information source is non-electrical and
therefore it is not suitable for immediate transmission.
· Such messages need to be coded or processed before transmission and also require
suitable transducers to convert them into electrical signals. The built-in circuitry such as
TM

decoders, encoders, transducers, etc. in the transmission makes incoming information

suitable for transmission and subsequent reception.
· The most of the transmitters have built-in amplifier circuits. These circuits amplify the
incoming signals (information) before transmission which help in faithful reception of
the transmitted information at the receiver end.
Communication channel
· The communication channel is the medium by which the electronic signal is transmitted
from one place to another. The communication medium can be a pair of conducting
wire, coaxial cable, optical fibre cable or free space.
Noise
· Noise is random, undesirable electric energy that enters the communication system via
the medium and interferes with the transmitted message. Some noise is also produced
in the receiver.
· Noise can be either natural or man-made. Natural noise includes noise produced in
nature, e.g. from lighting during rainy season, or noise due to radiations produced by
the sun and the other stars.
· Man-made noise is the noise produced by electric ignition systems of cars, electric
motors, fluorescent lights, etc.
· Noise is one of the serious problems of electronic communication. It cannot be
completely eliminated. However, there are ways to deal with noise, and reduce the
possibility of degradation of signal due to noise.
Receiver
· A receiver is a collection of electronic circuits designed to convert the signal back to the
original information. It consists of amplifier, detector, mixer, oscillator, transducer and
so on.
Ø Explain the need for modulation.

+ VTU : Feb.-2000, 09, Aug.-01, 02, 04, 05, 08, Jan.-11
· We have seen that baseband signals are incompatible for direct transmission over the
medium and therefore we have to use modulation technique for the communication of
baseband signal. The advantages of using modulation technique are as given below :
n Reduces the height of antenna
n Avoids mixing of signals
n Increases the range of communication
n Allows multiplexing of signals
n Allows adjustments in the bandwidth
n Improves quality of reception.
TM

1. Reduces the height of antenna

· The height of the antenna required for transmission and reception of radio waves in
radio transmission is a function of wavelength of the frequency used. The minimum
height of the antenna is given as l/4. The wavelength l is given as,
c
l =
f
where c is the velocity of light and

f is the frequency.
· From the above equation it can be easily noticed that at low frequencies wavelength is
very high and hence the antenna height. For example, consider the baseband signal
with f = 15 kHz. Then
l c 3 ´ 10 8
· Height of antenna = = = = 5000 meters
4 f ´ 4 15 ´ 10 3 ´ 4
· This 5000 meters height of a vertical antenna is unthinkable and unpractical. On the
other hand, if we consider a modulated signal with 1 MHz frequency in the broadcast
band the height of antenna is given as,
l c 3 ´ 10 8
· Height of antenna = = = = 75 meters
4 f ´ 4 1 ´ 10 6 ´ 4
· This height of antenna is practical and such antenna can be installed.

2. Avoids mixing of signals
· All sound signals are concentrated within the range from 20 Hz to 20 kHz. The
transmission of baseband signals from various sources causes the mixing of signal and
then it is difficult to separate at the receiver end.
Signal 1 Modulated Signal 2 Modulated Signal 3 Modulated

Signal 1 with carrier of with carrier of with carrier of
100 kHz 200 kHz 300 kHz
Frequency
0 20 kHz
Signal 2
Frequency
0 20 kHz Frequency
Signal 3 80 kHz 120 kHz 180 kHz 220 kHz 280 kHz 320 kHz
Frequency
0 20 kHz
Channel 1 Channel 2 Channel 3
bandwidth bandwidth bandwidth
Fig. 9.2 Modulation avoids mixing of signals
TM

· In order to separate the various signals, it is necessary to translate them all to different
portions of the electromagnetic spectrum (channel); each must be given its own
bandwidth commonly known as channel bandwidth. This can be achieved by taking
different carrier frequency for different signal source as shown in the Fig. 9.2. Once the
signals have been transmitted, a tuned circuit at the receiver end selects the portion of
the electromagnetic spectrum it is tuned for. Therefore modulating different signal
sources by different carrier frequencies avoid mixing of signals.
3. Increases the range of communication
· At low frequencies radiation is poor and signal gets highly attenuated. Therefore
baseband signals cannot be transmitted directly over long distance. Modulation
effectively increases the frequency of the signal to be radiated and thus increases the
distance over which signals can be transmitted faithfully.
4. Allows multiplexing of signals
· The modulation permits multiplexing to be used. Multiplexing means transmission of
two or more signals simultaneously over the same channel. The common examples of
multiplexing are the number of Television channels operating simultaneously or number
of radio stations broadcasting the signal in MW and SW band, simultaneously.
· The different signals from different stations can be separated in the receiver since the
carrier frequencies for these signals are different. It is commonly known as tuning the
receiver to the desired station. By tuning process, the desired signal is selected and at
the same time, other unwanted signals are rejected.
5. Allows adjustments in the bandwidth
· Bandwidth of a modulated signal may be made smaller or larger than the original
signal. Signal to noise ratio in the receiver which is a function of the signal bandwidth
can thus be improved by proper control of the bandwidth at the modulating stage.
6. Improves quality of reception
· The signal communication using modulation techniques such as frequency modulation,
pulse code modulation reduce the effect of noise to great extent. Reduction in noise
improves the quality of reception.
Ø Derive the expression for AM wave. + VTU : Aug.-04, 06, Feb.-10
Ø Write the expression for AM wave + VTU : Feb.-99, 03, Marks 2
The instantaneous values of modulating signal and carrier signal can be represented as
given below.
Instantaneous value of modulating signal
v m = Vm sin wm t
where v m = Instantaneous amplitude
Vm = Maximum amplitude
wm = 2p fm = Angular frequency and
TM

fm = Frequency of modulating signal

Instantaneous value of carrier signal
vc = Vc sin wc t
where v c = Instantaneous amplitude
Vc = Maximum amplitude
wc = 2p fc = Angular frequency and
fc = Frequency of carrier signal
Instantaneous value of amplitude modulated signal

Using above given mathematical expressions for modulating and carrier signals, we can
create a new mathematical expression for the complete modulated wave, as given below
VAM = Vc + v m
= Vc + Vm sin wm t Q v m = Vm sin wm t
\ The instantaneous value of the amplitude modulated wave can be given as
v AM = VAM sin q = VAM sin wc t
= (v c + Vm sin wm t) sin wc t
Ø Derive an expression for modulation index in AM. + VTU : Aug.-2000, 02, Marks 4
Ø Define modulation for AM.

· Looking at Fig. 9.3 we can visualize that something unusual (distortion) will occur if Vm
is greater than Vc. Therefore, the modulating signal voltage Vm must be less than the
carrier voltage Vc for proper amplitude modulation. This relationship between the
amplitudes of the modulating and carrier signals is important and it is expressed in
terms of their ratio, commonly known as modulation index (m). It is also called
modulation factor, modulation coefficient or the degree of modulation. The m is the
ratio of the modulating signal voltage to the carrier voltage :
Vm
m=
Vc
· The modulation index is a number lying between 0 and 1, and it is very often
expressed as a percentage and called the percentage modulation.
Ø Define modulation index in terms of Vmax and Vmin. + VTU : May-10, Marks 5
· Fig. 9.3 shows the amplitude modulated wave in time domain. Here, horizontal axis
represents time, and the vertical axis represents the amplitude of the signals.
Looking at Fig. 9.3 we can write,
Vmax – Vmin
Vm = K (9.1)
2
TM

+ Vc
(Vc+Vmsin wmt) Vm
Vmin Vmax
Vm
V
0 t
–(Vc+Vmsin wmt)
–
Fig. 9.3 Amplitude modulated wave

and Vc = Vmax – Vm K (9.2)
By substituting value of Vm in equation (9.2) we get,
æV – Vmin ö
= Vmax – ç max ÷
è 2 ø
2 Vmax – Vmax + Vmin
=
2
Vmax + Vmin
Vc = K (9.3)
2
Now dividing equation (9.1) by equation (9.3),
V (V – Vmin ) / 2
We have, m = m = max
Vc (Vmax + Vmin ) / 2
Vm
\ m =
Vc
Vmax – Vmin
m = K (9.4)
Vmax + Vmin
· The equation (9.4) gives the standard method for calculating modulation index from the
amplitude modulated waveform which may be displayed on the screen of the
oscilloscope.
Ø Explain the working of envelope detector.
· The simplest, and most popular, demodulator for full-carrier AM is the envelope
detector. This form of demodulator takes advantage of the simplicity of the AM signal.
TM

Basic Electronics 9 - 10 Communication Systems
All that is necessary to recover the baseband signal is to rectify the incoming signal to
remove half of the envelope, and then use a low-pass filter to remove the
high-frequency components of the signal.
· The Fig. 9.4 shows the envelope detector circuit. It consists of diode as a half wave
rectifier and RC circuit as a low pass filter. This circuit is also known as diode detector.
· As shown in the Fig. 9.4 the AM D
signal is transformer coupled and
applied to a basic half wave rectifier Vo
AM
circuit consisting of D and R. In the signal
C R Demodulated
positive half cycle of the AM signal output
diode conducts and current flows
through R whereas in the negative
half cycle diode is reverse biased Fig. 9.4 Diode detector
and no current flows through R. As
a result only positive half of the AM wave appears across resistor R as shown in the
Fig. 9.5 (b). The capacitor connected in parallel with resistance R provides very low
impedance at the carrier frequency and a much higher impedance at the modulating
frequency. As a result capacitor effectively shorts or filters out the carrier, thereby
leaving the original modulating signal. (See Fig. 9.5 on next page.)
Ø Explain the working of practical diode detector.

· Number of additions have been done in the simple diode circuit to improve the
performance. Fig. 9.6 shows the practical envelope detector circuit.
IF in
AGC out
C3
R3
R1 C2
C C1 R2 R4 AF out
Fig. 9.6 Practical diode detector
· Here, diode is connected reverse and due to reverse connection negative envelope is
demodulated instead of positive. This has no effect on detection, but it gives negative
AGC voltage. The resistor R of the simple diode detector is split into two parts (R1 and R 2 ).
R1 and C1 forms a low pass filter and R 2 provides series d.c. path to ground for the
diode. Capacitor C2 acts as a coupling capacitor and prevents the diode dc output from
TM

t
0
(a) AM signal
t
0
(b) Current pulses through diode D
t
0
(c) Demodulating signal
Fig. 9.5 Demodulator waveforms

TM

reaching the volume control R 4 . The R 3 and C3 forms another low pass filter, whose
main function is to remove AF components, thus providing a d.c. voltage whose
amplitude is proportional to the carrier strength. This d.c. voltage is used to control the
gain of the RF and IF amplifiers.
· For the practical diode detector shown in the Fig. 9.6, diode has d.c. load equal to
R1 + R 2 , and the audio load impedance Z m equal to R1 in series with the parallel
combination of R 2 , R 3 and R 4 , ignoring the capacitor reactance.
Therefore, for practical envelope detector circuit maximum allowable modulation index can
be given as
R1 series with (R2 || R3 || R4 )
M max =
R1 + R2
Ø Derive the expression for FM. + VTU : March-2000, Marks 6

Df
v = A sin éêwc t + sin wm t ùú = A sin [wc t + mf sin wm t]
ë fm û
where, wc = 2 p fc, wm = 2 p fm
D f : Frequency deviation
A : Amplitude of FM signal
mf : Modulation index of FM
Ø Define modulation index for FM.
Modulation in FM is generally expressed in terms of the modulation index. The

modulation index is the ratio of the frequency deviation to the modulating frequency.
Frequency deviation
m f = Modulation index =
Modulating frequency
Df d
\ mf = =
fm fm
Ø What is Carson's rule ?

· It is a matter of experience that the bandwidth requirements are determined by the
maximum frequency deviation and maximum modulation frequency present in the
complex modulating wave.
We have, BW = 2 (m f + 1) f m
\ BW = 2 (D f + fm max)
In commercial FM broad casting,
Maximum frequency deviation permissible = 75 kHz
and Maximum modulating frequency = 15 kHz,
then Max BW FM = 2 [75 + 15] = 180 kHz.

TM

The above equation for calculating maximum bandwidth required to transmit the FM wave
is known as Carson’s rule.
Ø State the merits of FM over AM. + VTU : July-06, March-02, Aug.-04, 01, Marks 4
Frequency Modulation has the following advantages :

1. The amplitude of FM wave is constant, and hence transmitted power is constant,
independent of modulation depth; whereas in A.M, modulation depth controls the
transmitted power. This means that low level modulation can be employed in FM
transmitters. Since the power is constant, the FM calculated signal, after low level
modulation, can be amplified by more efficient class-C amplifiers.
2. In AM, 67 % of transmitted power is in the carrier, for maximum modulation depth,
which is totally wasted as carrier does not carry any intelligence. In FM, all the
transmitted power is useful.
3. FM receivers use amplitude limiter circuits to eliminate the amplitude variations caused
by noise. Due to this, FM reception is more immune to noise than AM reception.
4. By increasing the frequency deviation in FM, it is possible to improve signal-to-noise
ratio AM does not have this feature since in AM, modulation depth cannot be
increased beyond 100 %.
5. For commercial FM transmitting stations a guard band of frequencies is allocated,
this reduces adjacent channel interference, as compared to AM.
6. FM broadcasting is in the upper VHF and UHF frequency ranges. In these frequency
ranges, there is inherently less noise than in the MW and SW ranges allotted to AM
broadcast.
7. Since FM operates in VHF and UHF range, the propagation is line of sight
propagation by space wave.
The radius of operation of an FM transmitter is limited to radio horizon. This allows
several independent FM transmitters to work on the same carrier frequency with
very little interference than would be possible with AM.
Ø State the demerits of FM over AM. + VTU : June-06, Marks 4
The following are some of the disadvantages of FM :

1. For transmission of FM signal, a much larger bandwidth is required than that
required to transmit AM signal.
2. FM transmitter and receiver are quite complicated, especially from the point of view
of servicing and fault finding/repairing of FM receivers.
3. Since FM reception is limited to radio horizon up to line of sight, the service area of
FM transmitter is much less than that for AM.
TM

Although this is advantageous for reduction of adjacent channel interference, it is a

disadvantage for FM mobile communication over a wide area.
Ø Give comparison between FM and PM.
Sr. No. FM PM
1. The equation for FM wave is : The equation for PM wave is

v = A sin [wc t + m f sin wm t ] [
v = A sin wc t + m p wm t ]
2. The frequency deviation is linearly The phase shift of the carrier is linearly
proportional to instantaneous amplitude of proportional to instantaneous amplitude of
the modulating signal. the modulating signal.
3. Frequency modulation is direct method of Phase modulation is indirect method of

producing FM signal. producing FM.
4. The modulation index of an FM signal is The modulation index is proportional to

the ratio of the frequency deviation to the the maximum amplitude of the modulating
modulating frequency. signal.
5. To have better quality of transmission and The amount of frequency shift produced
reception of higher audio frequencies, by a phase modulator increases with the
pre-emphasis and de-emphasis circuits are modulating frequency. Hence an audio
used. equalizer is required to compensate this.
6. Amplitude of the FM wave is constant. Amplitude of the PM wave is constant.
7. Noise is better suppressed in FM systems Noise immunity is inferior to that of FM.

as compared to PM system.
8. FM is mainly used for FM broadcasting PM is used in mobile communication

used for entertainment purposes. system.
Ø Give the comparison between FM and AM. + VTU : Nov.-10, Marks 5
Sr. FM AM
No.
1. The equation for FM wave is The equation for AM wave is

v = A sin [wc t + m f sin wm t ]. v = Vc [1 + m sin wm t ] sin wc t.
2. The modulation index can have value either The value of modulation index is always
less than one or more than one. between zero and one.
3. Since in FM, amplitude of the carrier is Transmitted power is dependent upon
constant, the transmitted power is constant, é m2 ù
modulation index PT = Pc ê1 + .
independent of the modulation index. 2 ú
ë û
4. The modulation index determines the In an AM signal, only two sidebands are
number of significant pairs of sidebands in produced, for any value of modulation
an FM signal. index.
TM

5. The amplitudes of the carrier and side bands The amplitudes of the sidebands is
vary with the modulation index and can be dependent on the modulation index, and is
calculated with Bessel functions. always less than the amplitude of carrier.
6. The carrier or sideband amplitudes are zero The sideband amplitude is never zero for
at some modulation indices. any value of modulation index greater than
zero.
7. The bandwidth of an FM signal is The bandwidth of an AM signal is twice the
proportional to the modulation index. highest modulating frequency.
8. For FM, the % of modulation is the ratio of For AM, % modulation is the ratio of
the actual frequency deviation and the amplitude of modulating voltage to the
maximum permissible frequency deviation amplitude of the carrier multiplied by 100.
multiplied by 100.
9. The main advantage of FM over AM is its The AM system is more susceptible to noise
noise immunity, as limiter stage in FM and more affected by noise than FM.
receiver clips off noise signals.
10. The capture effect in FM allows the When two AM signals occupy the same
strongest signal on a frequency to dominate frequency, both signals will generally be
without interference from the other signal. heard regardless of their relative signal
strength.
11. In FM, greater transmitter efficiency can be The efficiency of AM is less than that of FM
realized using class-C amplifiers, as due to use of class-B amplifier.
amplitude of FM signal is constant.
12. The bandwidth of FM signal is much under The bandwidth required to transmit AM
than the bandwidth of AM. The bandwidth signal is much less than that of FM typically
of a typical FM channel is 200 kHz. 10 kHz in AM broadcasting.
13. The circuits to produce and demodulate FM The demodulation of AM signal is very easy
are usually more complex and expensive practically by use of a diode; which is very
than AM circuits. simple in operation and economical.
Important Examples
Example 9.1 An audio frequency signal 10 sin 2 p ´ 500 t is used to amplitude modulate a
carrier of 50 sin 2 p ´ 105 . Calculate
i) Modulation index. ii) Sideband frequencies.
iii) Amplitude of each sideband frequencies. iv) Bandwidth required.
v) Total power delivered to the load of 600 W. vi) Transmission efficiency.
Solution :
i) Modulation index :
Given Vm = 10 sin 2 p ´ 500 t
Vc = 50sin 2 p ´ 105 t
\ Vm = 10 and Vc = 50
TM

We know that,
Vm 10
Modulation index m = = = 0.2
Vc 50
and percentage modulation = 0.2 ´ 100 = 20 %

ii) Sideband frequencies
Given wm = 2 p ´ 500
\ fm = 500 Hz
and wc = 2 p ´ 105
\ fc = 100 kHz
f USB = f c + f m = 100 kHz + 500
= 100500 Hz = 100.5 kHz
and f LSB = f c – f m = 100 kHz – 500
= 99500 Hz = 99.5 kHz
iii) Amplitude of each sideband frequencies
mVc 0.2 ´ 50
Amplitude of upper and lower sidebands = = =5V
2 2
iv) Bandwidth required

BW = f USB – f LSB = 100500 – 99500 = 1000 Hz
v) Total power delivered into a load of 600 W
Vc 2 æ 2 ö (50) 2 æ 2 ö
We know that, PTotal = ç 1+ m ÷ = ç 1+ (0.2) ÷ = 2.125 watts
2R ç 2 ÷ 2 ´ 600 ç 2 ÷
è ø è ø
vi) Transmission efficiency
m2 (0.2) 2
h = = = 0.0196
2 + m2 2 + (0.2) 2
\ % h = 0.0196 ´ 100 = 1.96 %
Example 9.2 A broadcast transmitter radiates 20 kilowatts when the modulation percentage is
75. How much of this is carrier power ? Also calculate the power of each sidebands.
Solution :
We know that
æ m 2 ö÷
PTotal = Pc ç 1+
ç 2 ÷
è ø
PTotal 20 20
\ Pc = = = = 15.6 kW
æ ö
m2 1 + (075
. )2 1.28
ç1 + ÷
ç 2 ÷ 2
è ø
TM

Sideband power is given as

æ m2 ö æ (0.75) 2 ö
PSB = Pc ç ÷ = 15.6 ç ÷ = 2.2 kW
ç 4 ÷ ç 4 ÷
è ø è ø
\ PUSB = PLSB = 2.2 kW
Example 9.3 A carrier of 1 MHz with 400 W of its power is amplitude modulated with a
sinusoidal signal of 2500 Hz. The depth of modulation is 75 %. Calculate the sideband
frequencies, the bandwidth, the power in the sidebands and the total power in the modulated
wave. + VTU : March-01, Feb.-04, Marks 5
Solution : Given : carrier frequency fc = 1 MHz = 1000 kHz and signal frequency
fm = 2500 Hz = 2.5 kHz.
\ Sideband frequencies
fSB = fc + fm = 1000 + 2.5 and 1000 – 2.5
= 1002.5 kHz and 997.5 kHz

Bandwidth = 1002.5 – 997.5 = 5 kHz
Also power in carrier, Pc = 400 W
Depth of modulation = m = 0.75
æ m2 ö æ (0.75) 2 ö
Now, Pt = Pc ç 1 + ÷ = 400 ç 1 + ÷
ç 2 ÷ ç 2 ÷
è ø è ø
Pt = 512.5 watts
We know that,
Power in sidebands = Total power – Carrier power

= Pt – Pc = 512.5 – 400 = 112.5 watts
Sideband frequencies are 1002.5 kHz and 997.5 kHz
Bandwidth = 5 kHz
Sideband power = 112.5 watts.
Total power in the modulated wave = 512.5 watts.
Example 9.4 Calculate the maximum allowable modulation index which may be applied to the
practical envelope detector circuit with following component values :
R 1 =100 k W , R 2 = 200 k W, R 3 = 510 k W and R 4 = 1 M W.
Solution : D.C. load for diode = R1 + R 2 = 100 k W + 200 k W = 300 k W
TM

Z m = R1 + (R 2 | | R 3 | | R 4 ) = 100 + (200|| 510|| 1000) = 225.6 k W

Zm 225.6
\ M max = = = 0.752
Rc 300
Example 9.5 In an F.M. system, the frequency deviation constant is K = 5 kHz/V. If a

sinusoidal modulating signal of 15 V, 10 kHz is applied, calculate the peak frequency deviation
and the modulating index.
Solution : Given : 1) fm = 10 kHz
2) Frequency deviation constant = 5 kHz/V
3) AF voltage = 15 V
\ Frequency deviation = 15 ´ 5 kHz = 75 kHz

Df 75 kHz
Modulation index = = = 7.5
fm 10 kHz
Introduction
Q.1 Which of the following statements are true ?

(a) Communication is the basic process of exchanging information.
(b) Language and distance are the main limitations of human communication.
(c) The first communication satellite was launched in 1962.
(Ans. : d)
Elements of Communication Systems
Q.1 In a communication system, noise is most likely to affect the signal _______.
(a) at the transmitter (b) in the channel
(c) in the information source (d) at the destination
(Ans. : b)
Q.2 The information signal from information source is converted into _____ signal by the
transmitter.
(a) mechanical (b) physical (c) optical (d) electrical
(Ans. : d)
Q.3 The undesirable electric signal which interferes with transmitted signal and may disturb the
received signal is _____ .
(a) noise signal (b) voice signal (c) modulating signal (d) audio signal
(Ans. : a)
TM

Q.4 Baseband signals can also be referred as _____ .

(a) modulating signals (b) carrier signals (c) modulated signals (d) none of above.
(Ans. : a)
Q.5 Transducers which converts voice, picture or other form of signals into electrical signals
forms part of _____ .
(a) receiver (b) transmitter (c) mixer (d) filters
(Ans. : b)
Q.6 Baseband signals can be _____ .
(a) only digital signals (b) only analog signals
(c) analog or digital signals (d) none of above
(Ans. : b)
Modulation
Q.1 In baseband transmission ______ signal is used for transmission.

(a) original (b) modulated (c) carrier
(Ans. : a)
Q.2 The transmission without modulation is called ______ transmission.
(a) half duplex (b) radio (c) baseband
(Ans. : c)
Q.3 Distance traveled by an electromagnetic wave during the time of one cycle is _______.
(a) wavelength (b) channel length (c) wave distance
(Ans. : a)
Q.4 Putting voice, video or information signal directly onto the communication medium is
referred to as ______ transmission.
(a) baseband (b) broadband (c) midband
(Ans. : a)
Q.5 The spectrum space occupied by a signal is called ______.
(a) bandwidth (b) wavelength (c) frequency band
(Ans. : a)
Q.6 Unit of ________________ is angstrom.
(a) wavelength of light (b) frequency of light (c) speed of light
(Ans. : a)
Q.7 Indicate the false statement. Modulation is used to __________.
(a) reduce the bandwidth used (b) allows multiplexing of signals
(c) ensure that signal may be transmitted over long distances
(d) allow the use of practicable antennas
(Ans. : a)
Q.8 In modulation, the information signal is called ______ and the high frequency signal is
called ______.
(a) modulating signal, carrier (b) carrier, modulated signal
(c) modulating, baseband signal
(Ans. : a)
TM

Q.9 Attenuation in the baseband signals is ______ as compared to modulated signals.

(a) small (b) same (c) large
(Ans. : c)
Q.10 Which of the following is not true in case modulation ?
(a) It reduces antenna height. (b) It avoids mixing of signals.
(c) It decreases range of communication. (d) Improves quality of reception.
(Ans. : c)
Q.11 The minimum antenna height is ______.
(a) l/2 (b) l/4 (c) 4/l (d) l
(Ans. : b)
Q.12 The modulated signals can travel ______ distance as compared to baseband signals.
(a) longer (b) shorter (c) same
(Ans. : a)
Q.13 PAM is a type of ______ modulation.
(a) pulse (b) analog (c) digital
(Ans. : a)
Q.14 The height of antenna is_____ proportional to frequency used for the transmission.
(a) not (b) directly (c) equally (d) inversely
(Ans. : d)
Q.15 The antenna height is given by _____ .
(a) l 4 (b) 4l (c) 2l (d) l/2
(Ans. : a)
Q.16 _____ cannot be transmitted directly over long distance faithfully.
(a) AM signals (b) FM signals (c) Carrier signals (d) Baseband signals.
(Ans. : d)
Q.17 To transmit baseband signal of frequency 15 kHz directly _____ meters of antenna height
is required.
(a) 7500 (d) 50 (c) 5000 (d) 10000
(Ans. : c)
Q.18 In amplitude modulation technique _____ of carrier signal is varied in accordance with the
modulating signal.
(a) frequency (b) amplitude (c) phase (d) all of above
(Ans. : b)
Amplitude Modulation
Q.1 The AM signal that occupies the greatest bandwidths is the one modulated by
________ .
(a) 1 kHz sine wave (b) 10 kHz sine wave
(c) 1 kHz square wave (d) 5 kHz square wave
(Ans. : d)
Q.2 The carrier frequency is ______ the modulating frequency.
TM

(a) lower than (b) higher than (c) same as

(Ans. : b)
Q.3 When amplitude of carrier is varied in proportion with the instantaneous amplitude of
modulating signal, we have_________ modulation.
(a) amplitude (b) frequency (c) phase
(Ans. : a)
Q.4 The outline of the peaks of the carrier signal is called ______ and it has the same shape
as the ______.
(a) carrier, modulating signal (b) envelope, carrier
(c) envelope, modulating signal
(Ans. : c)
Q.5 Which of the following modulating signal will occupy maximum bandwidth in AM ?
(a) 5 kHz sine wave (b) 2 kHz square wave (c) 10 kHz sine wave
(Ans. : b)
Q.6 AM broadcast takes place in the frequency range ______.
(a) 535 - 1605 kHz (b) 0 - 3 kHz (c) 30 - 3 MHz
(Ans. : a)
Q.7 In AM fc is ______ fm .
(a) greater than (b) lower than (c) equal to
(Ans. : a)
Q.8 Amplitude modulation is the process of ________.
(a) superimposing a low frequency on a high frequency
(b) superimposing a high frequency on a low frequency
(c) carrier interruption
(d) frequency shift and phase shift
(Ans. : a)
Q.9 The depth of modulation is given by ______.
(a) modulation index (b) bandwidth (c) deviation
(Ans. : a)
Q.10 In AM the shape of ______ is same as that of the modulating signal.
(a) carrier (b) envelope (c) information
(Ans. : b)
Q.11 The modulation index is unitless.
(a) True (b) False
(Ans. : a)
Q.12 If Em = 8 V, Ec = 10 V, the value of m is ______ for AM.
(a) 0.8 (b) 8 (c) 0.2
(Ans. : a)
m Ec
Q.13 In AM, the term cos ( wc + wm ) represents ______.
2
(a) carrier (b) LSB (c) USB
(Ans. : c)
TM

m Ec
Q.14 In AM, the term cos ( wc - wm ) represents ______.
2
(a) carrier (b) LSB (c) USB

(Ans. : b)
Q.15 The amplitude of both the sidebands in an AM wave is ______.
(a) Ec2 / 2m (b) m 2 Ec 2 (c) m Ec / 2
(Ans. : c)
Q.16 The modulation index of an AM wave is changed from 0 to 1. The transmitted power is
_________.
(a) unchanged (b) halved
(c) doubled (d) increased by 50 percent
(Ans. : d)
Q.17 An amplitude modulated wave is __________.
(a) the sum of the carrier and the modulating wave
(b) the difference between the carrier and the modulating wave
(c) the product of the carrier and the modulating wave
(d) the sum of the carrier and its product with modulating signal.
(Ans. : a)
Q.18 In an amplitude modulated waveform, the amplitude of sidebands is ______.
(a) independent of the carrier amplitude
(b) independent of the modulation index
(c) carrier amplitude ´ modulation index
1
(d) carrier amplitude ´ modulation index
2
(Ans. : d)
Q.19 Overmodulation exists when modulation index is _____.
(a) 1 (b) 0 (c) > 1
(Ans. : c)
Q.20 Indicate the correct statement. _______ in AM.
(a) Lower sideband power is constant (b) Total transmitted power is constant
(c) Carrier power is constant (d) Upper sideband power is constant
(Ans. : c)
Q.21 To achieve 80 percent modulation index with carrier ec = 20 cos wc t, the modulating signal
amplitude Em should be ______.
(a) 8 V (b) 16 V (c) 4 V
(Ans. : b)
Q.22 To achieve faithful AM transmission ________________.
(a) Em should be equal to Ec (b) Em should be greater than Ec
(c) Em should be less than or equal to Ec
(Ans. : c)
TM

Q.23 For a carrier signal of 1 MHz and modulating signal of 20 kHz, what is the frequency
range occupied by the AM signal ?
(a) 980 kHz to 1020 kHz (b) 0 kHz to 20 kHz (c) 1000 kHz to 1020 kHz
(Ans. : a)
Q.24 For an AM wave represented by 20 [1+ 0.8 sin (2p ´ 2000 t) sin (2p ´ 106 t)] the sideband
frequencies are :
(a) 998 kHz and 1002 kHz (b) 999 kHz and 1001 kHz
(c) 0.998 MHz and 1.002 MHz (d) None of the above
(Ans. : d)
Q.25 Expression of an AM wave is eAM = 50 [1+ 0.8 cos (400 p t)] cos 2 p ´ 105 t then the
Em = ______.
(a) 40 V (b) 20 V (c) 80 V
(Ans. : a)
modulation index m = ______.
(a) 0.8 (b) 0.4 (c) 1
(Ans. : a)
Q.27 Number of frequency components in an AM wave are______.
(a) 2 (b) 3 (c) 4
(Ans. : b)
Q.28 In AM the ______ does not carry any information.
(a) carrier (b) USB (c) LSB
(Ans. : a)
Q.29 The bandwidth of AM wave is ______.
(a) fm (b) 2 fm (c) fm / 2
(Ans. : b)
Q.30 Expression of an AM wave is eAM = 50 [1+ 0.8 cos (400 p t)] cos 2 p ´ 105 t then the carrier
frequency fc = ______.
(a) 105 Hz (b) 200 Hz (c) 400 Hz
(Ans. : a)
modulating frequency fm = ______.
(a) 105 Hz (b) 200 Hz (c) 400 Hz
(Ans. : b)
Q.32 The relation between carrier power and total power in an AM wave is _______.
+ VTU : Jan.-14
æ m2 ö æ m2 ö
(a) Pc = PT çç1+ ÷ (b) Pc = PT çç1+ ÷
4 ÷ 2 ÷
è ø è ø
æ m2 ö æ m2 ö
(c) PT = Pc çç1+ ÷ (d) PT = Pc çç1+ ÷
4 ÷ 2 ÷
è ø è ø
(Ans. : d)
TM

Q.33 A single sideband signal contains 1 kW. Power contained in the sidebands is _______.
(a) 0.25 kW (b) 0.5 kW
(c) 1 kW (d) none of the above
(Ans. : c)
Q.34 For a 100 % AM modulated wave with carrier suppressed, the percentage power saving
will be ___________.
(a) 100 (b) 50 (c) 150 (d) 66.66
(Ans. : d)
Q.35 A carrier is simultaneously modulated by 2 sine waves with modulation indices of 0.6 and
0.8 ; the total modulation index __________.
(a) 0.5 (b) cannot be calculated unless phase relations are known
(c) 1 (d) 0.7
(Ans. : c)
Q.36 For a signal amplitude modulated to a depth of 100 % by a sinusoidal signal, the power
is _________.
(a) same as the power of unmodulated signal
(b) twice as the power of unmodulated signal
(c) four times the power of unmodulated signal
(d) one and a half times the power of unmodulated carrier
(Ans. : d)
Q.37 An amplitude modulated voltage in volts is given by
v = 20 (1 + 0.5 sin 6280 t) sin (6.28 ´106 ) t. The r.m.s. value of the unmodulated carrier
voltage in volts is _______.
(a) 20 (b) 20/ 2 (c) 10 (d) 10/ 2
(Ans. : b)
Q.38 In case the carrier of a 100 percent modulated AM wave is suppressed, the percentage
power saving will be ________.
(a) 33.33 (b) 66.66 (c) 100 (d) 150
(Ans. : b)
Q.39 A carrier is simultaneously modulated by two sine waves with modulation indices of 0.3
and 0.4. The total modulation index will be ________.
(a) 0.5 (b) 0.7
(c) 1 (d) cannot be ascertained unless phase relations are known.
(Ans. : a)
Q.40 A 200 W carrier is modulated to a depth of 75 percent. The total power of the modulated
wave is given by _________.
(a) 128 W (b) 156.3 W (c) 256.25 W (d) 288.33 W
(Ans. : c)
Q.41 A broadcast radio transmitter radiates 20 kW when the modulation percentage is 50. How
much of this is carrier power ?
(a) 4.23 W (b) 8.47 W (c) 12.7 W (d) 16.94 W
(Ans. : d)
TM

Q.42 When E1, E2 ,E3 and E4 are the simultaneous modulating voltages, then the total
modulating voltage will be _________.
E1 + E2 + E3 + E4
(a) E1 + E2 + E3 + E4 (b)
4
(c) E1E2 + E2E4 (d) E12 + E22 + E23 + E24

(Ans. : d)
Q.43 A 1000 kHz carrier is simultaneously modulated with 300 Hz, 800 Hz and 2 kHz audio
sine waves. The frequencies present in the output will be _______.
(a) 1000 kHz, 300 Hz, 800 Hz and 2 kHz
(b) 1800 kHz, 1300 kHz and 1002 kHz
(c) 200 kHz, 1800 kHz, 700 kHz, 1300 kHz, 1002 kHz, 998 kHz and 1000 kHz
(d) 998.0 kHz, 999.2 kHz, 999.7 kHz, 1000.3 kHz, 1000.8 kHz and 1002.0 kHz
(Ans. : d)
Q.44 The principle used to transmit the signal is ________.
(a) modulation (b) de-modulation (c) amplification (d) attenuation
(Ans. : a)
Q.45 The frequency of amplitude modulated signal is _____ the carrier signal.
(a) less than (b) more than (c) same as (d) none of above
(Ans. : c)
Q.46 AM wave have following components.
(a) carrier, LSB and USB (b) LSB and USB
(c) either LSB or USB (d) one SB and vestige of other SB
(Ans. : a)
Q.47 The amplitude of LSB and USB generated in AM signal is _____ .
(a) zero (b) same
(c) different (d) equal to amplitude of carrier
(Ans. : b)
Q.48 The value of modulation index m is given as _____ .
Vc + Vm
(a) Vc / Vm (b) (c) Vc + Vm (d) Vm / Vc
2
(Ans. : d)
Q.49 The frequency of signals in AM technique ranges from _____ .
(a) fc to (fc + fm ) (b) (fc – fm) to fc
(c) (fc – fm) to (fc + fm) (d) fm to fc
(Ans. : c)
Q.50 The peak voltage of carrier signal and modulating signal are given as 2 V and 1 V
respectively, the modulation index m is _____ .
(a) 0.5 (b) 2 (c) 1 (d) 0.25
(Ans. : a)
Q.51 Bandwidth of AM signals can be calculated if _____ .
(a) value of only carrier frequency is known
TM

(b) value of only modulating frequency is known

(c) value of only sideband frequency is known
(d) none of above
(Ans. : b)
Q.52 If the amount of information is lost in particular AM signal then m for that signal is _____ .
(a) more than 1 (b) less than 1 (c) zero (d) none of above
(Ans. : a)
Q.53 Bandwidth of AM signal is given as _____ the frequency of modulating signal.
(a) half of (b) same as (c) twice of (d) four times
(Ans. : c)
Q.54 If sine wave of 4 V peak with frequency of 1000 Hz amplitude modulates the carrier wave
of 10 V peak with 100 kHz frequency, the bandwidth of AM wave is _____ .
(a) 200 kHz (b) 99 kHz (c) 101 kHz (d) 2 kHz
(Ans. : d)
Q.55 The modulation index m in AM interms of maximum and minimum voltages in resultant
AM wave is given as _____ .
V + Vmin V - Vmin V V
(a) max (b) max (c) max (d) min
Vmax - Vmin Vmax + Vmin Vmin Vmax
(Ans. : b)
Q.56 If maximum and minimum value of voltages in amplitude modulated wave are 6 V and
2 V respectively the value of m is _____ .
(a) 0.5 (b) 2 (c) 3 (d) 0.33
(Ans. : a)
Q.57 We can refer information power as _____.
(a) power in carrier (b) total power of AM wave
(c) power of two side bands (d) none of above.
(Ans. : c)
Q.58 If broadcast transmitter radiates 20 kW out of which carrier power is 12 kW what will be
the power of each side band ?
(a) 8 kW (b) 2 kW (c) 32 kW (d) 4 kW
(Ans. : d)
Q.59 For 100 % modulation the maximum total power of AM wave is _____ of carrier power Pc .
(a) same as (b) twice of (c) 1.5 times (d) half
(Ans. : c)
Q.60 A 400 watt carrier is modulated with modulation index m = 1, the total power in AM wave
is _____ .
(a) 800 watt (b) 600 watt (c) 200 watt (d) 400 watt
(Ans. : b)
Q.61 The modulation index of an amplitude modulated wave is changed from 0 to 1. The
transmitted power is _____ .
(a) unchanged (b) halved (c) doubled (d) increased by 50 %.
(Ans. : d)
TM

Q.62 If carrier is simultaneously modulated by 2 sine waves with modulation indices of 0.3 and
0.4 total modulation index will be _____ .
(a) 0.5 (b) 0.7 (c) 0.25 (d) 1
(Ans. : a)
Q.63 Total modulation index m t is determined as _____ when one or more sine waves
amplitude modulates the carrier wave.
m12 + m 22 + ...
(a) m12 + m 22 + ... (b) (m1 + m 2 + .... )2 (c) (d) m12 + m 22 + ...
2
(Ans. : d)
Q.64 Which type of amplifier is used for collector modulator to generate AM signal ?
(a) Class B push-pull amplifier. (b) Class A-B amplifier.
(c) Class C amplifier (d) None of the above.
(Ans. : c)
Q.65 In low level AM systems amplifiers next to the modulating stages must be _____ .
(a) non linear amplifier (b) class A linear amplifiers
(c) class C amplifiers (d) none of above
(Ans. : b)
Q.66 In high level AM modulation circuitry has to handle _____ power.
(a) high power (b) low power (c) very low power (d) none of above
(Ans. : a)
Q.67 Normal AM system can be referred as _____ .
(a) DSBSC (b) SSB (c) DSB (d) DSBFC
(Ans. : d)
Q.68 In normal AM wave the information is present _____ .
(a) in carrier component (b) only in LSB component
(c) in LSB and USB component (d) only in USB component
(Ans. : c)
Q.69 In AM for faithful reception of original information signal atleast _____ has to be
transmitted.
(a) single SB (b) single SB and carrier
(c) both SB (d) both SB and carrier
(Ans. : a)
AM Detection (Demodulation)
Q.1 In diode detector circuit diode acts as ________.

(a) full wave rectifier (b) half wave rectifier (c) switch (d) amplifier
(Ans. : b)
Q.2 In practical diode detector _______ of modulated wave is detected.
(a) both positive and negative envelope (b) positive envelope
(c) negative envelope (d) none of above
(Ans. : c)
TM

Frequency Modulation
Q.1 The noise immunity of AM system is _________.

(a) poor (b) moderate (c) excellent
(Ans. : a)
Q.2 When frequency of carrier is varied in proportion with the instantaneous amplitude of
modulating signal, we have_________ modulation.
(Ans. : b)
Q.3 The ________ of FM or PM wave is constant.
(a) frequency (b) phase (c) amplitude (d) bandwidth
(Ans. : a)
Q.4 The maximum frequency of FM wave is _________.
(a) fc (b) fc - d (c) fc + d
(Ans. : c)
Q.5 The modulation index of FM is given by _________.
(a) m f = fm d (b) m f = fm ´ d (c) m f = d fm
(Ans. : c)
Q.6 The BW of FM system is ________ that of AM.
(a) lower than (b) higher than (c) same as
(Ans. : b)
Q.7 According to Carlson's rule the BW of FM is_________.
(a) BW = 2 [d + fm ] (b) BW = [2d + fm ] (c) BW = [d + 2 fm ]
(Ans. : a)
Q.8 In FM, the BW depends on ________.

(a) m, fm (b) fc , fm (c) m, Em
(Ans. : a)
Q.9 The advantage of FM is _________.
(a) its amplitude is constant (b) it requires large BW
(c) its transmitter and receiver circuitry is quite complicated
(Ans. : a)
Q.10 In AM all transmitted power is useful.
(a) True (b) False
(Ans. : b)
Q.11 In frequency modulation, the modulation index is proportional to ________.
1 1
(a) w m (b) (c) (d) w2m
wm w2m
where wm is the modulation frequency in radians/second.

(Ans. : b)
Q.12 A 4 volt peak audio modulating signal changes the carrier frequency from 200 kHz to
210 kHz, the frequency deviation is _________.
TM


(Ans. : b)
Q.13 Bandwidth in FM transmission with Df = 75 kHz, fm = 15 kHz is ________.
(Ans. : d)
Q.14 In an FM system, when the audio frequency is 500 Hz and AF voltage is 2.4 V, the
deviation is 4.8 kHz. If the AF voltage is now increased to 7.2 V, the new deviation will
be _________.
(a) 10.2 kHz (b) 14.4 kHz (c) 16.6 kHz (d) 18.8 kHz
(Ans. : b)
Q.15 A 25 MHz carrier is modulated by a 400 Hz audio sine wave. The carrier voltage is 4 V
and the maximum deviation is 10 kHz. The modulation index will be ________.
(a) 2.5 (b) 5 (c) 15 (d) 25
(Ans. : d)
Q.16 In frequency modulation for a given frequency deviation, the modulation index varies
________.
(a) inversely as the modulating frequency
(b) directly as the modulating frequency
(c) independent of the changes in modulating frequency
(Ans. : a)
Q.17 In FM, the frequency deviation is _________.
(a) proportional to modulating frequency (b) proportional to amplitude of modulating signal
(c) constant (d) zero
(Ans. : b)
Q.18 In the spectrum of a frequency modulated wave
(a) the carrier frequency cannot disappear
(b) the total number of sidebands depends on the modulation index
(c) the carrier frequency disappears when the modulation index is large
(d) the amplitude of any sideband depends on the modulation index
(Ans. : d)
Q.19 In which of the following modulation system when the modulating frequency is doubled,
the modulation index reduces to half while modulating voltage remains constant ?
(a) Phase (b) Amplitude (c) Frequency (d) None of the above
(Ans. : c)
Q.20 In FM signal, the power _________.
(a) increases as the modulation index increases
(b) reduces as the modulation index increases
(c) increases as the modulation index decreases
(d) remains constant when the modulation index increases
(Ans. : d)
TM

Q.21 A FM signal with modulation index Mf is passed through a frequency doubler. The wave
in the output of the doubler will have a modulation index of _______.
M
(a) M f (b) f (c) 2 M f (d) 4 M f
2
(Ans. : c)
Q.22 A 500 Hz modulating voltage fed into an FM generator produces a frequency deviation of
2.25 kHz.
The modulation index will be _______.
(a) 2.25 (b) 4.5 (c) 6.77 (d) 8.00
(Ans. : b)
Q.23 If the amplitude of the voltage is kept constant, but its frequency is raised to 6 kHz, the
new deviation will be _________.
(a) 13.5 kHz (b) 27 kHz (c) 54 kHz (d) 108 kHz
(Ans. : c)
Q.24 In an FM waveform, the sidebands are spaced at interval equal to ________.
(a) four times the modulating frequency (b) twice the modulating frequency
(c) half the modulating frequency (d) equal to the modulating frequency
(Ans. : c)
Q.25 An FM signal with a modulation index m is passed through a frequency triple. The wave
in the output of the tripler will have a modulation index of ________.
(a) m/3 (b) m (c) 3 m (d) 9 m
(Ans. : c)
Q.26 A 4 volt peak audio modulating signal changes the carrier frequency from 200 kHz to
210 kHz, the frequency deviation is _________.
(Ans. : b)
Q.27 In FM system, if the depth of modulation is doubled, the output power _______.
(a) increases by factor of 2 (b) increases by factor of 3
(c) increases by factor of 2 (d) remains at unmodulated value
(Ans. : d)
Q.28 In FM wave the information is contained in _________.
(a) amplitude variations (b) frequency variations (c) carrier
(Ans. : b)
Q.29 The amount of deviation in FM is directly proportional to ________ of the modulating
signal.
(Ans. : a)
Q.30 The number of significant sidebands in FM depends on _________.
(a) modulation index (b) deviation (c) carrier frequency
(Ans. : a)
TM

Q.31 The equation of the FM signal is 10 sin [2 p ´ 106 t + 5 sin (4 p ´ 103 t)]. The modulating
frequency is _________.
(a) 106 Hz (b) 5 Hz (c) 2000 Hz
(Ans. : c)
Q.32 The drawback of FM is _________.
(a) its amplitude is constant (b) it requires large BW
(c) it allows to improve S/N ratio
(Ans. : b)
Q.33 The main disadvantage of FM is ________.
(a) adjacent channel interference (b) limited line of sight range
(c) complex circuitry (d) low operating range
(Ans. : b)
Q.34 In FM transmission, if frequency of modulating signal is doubled, the modulation index will
_________.
(a) be halved (b) be doubled (c) be 4 times (d) remain unchanged
(Ans. : a)
Q.35 Carrier frequency is __________ in FM wave
e = 12 sin (6 ´108 t + 5 sin 1250 t)
(a) 75.5 MHz (b) 85.5 MHz (c) 95.5 MHz (d) 180 kHz
(Ans. : c)
Q.36 Which of the following is the advantage of frequency modulation over amplitude
modulation ?
(a) Noise can be reduced by increasing deviation.
(b) The amplitude of the FM wave in FM is independent of the depth of modulation,
whereas in AM it is dependent on this parameter.
(c) There is a large increase in noise to signal ratio in FM.
(Ans. : d)
Q.37 Which one of the following is not necessarily an advantage of FM over AM ?
(a) Lower bandwidth is required. (b) Less modulating power is required.
(c) Better noise immunity is provided. (d) The transmitted power is more useful.
(Ans. : a)
Q.38 On an FM signal, maximum deviation occurs at __________ .
(a) zero crossing point (b) peak positive amplitude
(c) peak negative amplitude (d) both (A) and (B).
(Ans. : b)
Phase Modulation
Q.1 In PM _________ of carrier signal is varied in accordance with instantaneous value of

modulating signal.
(a) frequency (b) amplitude (c) phase (d) none of above
(Ans. : c)
TM

Q.2 For phase modulated signal maximum frequency deviation takes place ______of
modulating signal.
(a) at positive peak (b) at negative peak
(c) at positive and negative peak (d) near zero crossing
(Ans. : d)
Q.3 Modulation index m p in phase modulation is proportional to _____________.
(a) maximum amplitude of modulating signal
(b) minimum amplitude of modulating signal
(c) instantaneous value of modulating signal
(d) none of above
(Ans. : a)
Q.4 In phase modulation carrier frequency deviation is proportional to ____________.
(a) only modulating voltage (b) only modulating frequency
(c) modulating voltage and modulating frequency both
(d) none of above
(Ans. : c)
Q.5 The unit of modulation index mp in phase modulation is ________.
(a) radians (b) kHz / volts (c) kHz (d) volts
(Ans. : a)
Q.6 The equation of the modulated wave for PM will be__________.
6 6
(a) 4 sin (1.57 ´ 10 t) (b) 4 sin 800 t + 4 sin 50 ´ 10 t
6 6
(c) 4 sin (1.57 ´ 10 t + 25 sin 2513 t) (d) 4 sin (1.57 ´ 10 t – 25 sin 2513 t)
(Ans. : c)
Q.7 The difference between PM and FM is_________.
(a) in the poorer audio response of phase modulation
(b) purely theoretical otherwise the two are modulation
(c) merely in the different modulation indices
(d) too great to make the two systems compatible
(Ans. : c)
Q.8 The frequency deviation of FM signal produced from PM is ___________.
(a) same as that of FM signal produced by direct method
(b) more than that of FM signal produced by direct method
(c) directly proportional to peak amplitude and the frequency of modulating signal
(d) directly proportional to peak amplitude of modulating signal
(Ans. : c)
Q.9 One way to derive FM from PM :
(a) Integrate the modulating signal before applying to PM oscillator.
(b) Integrate signal out of PM oscillator.
(c) Differentiate the modulating signal before applying to the PM oscillator.
(d) Differentiate the signal out of PM oscillator.
(Ans. : a)
TM

Q.10 In PM system maximum frequency deviation results at __________.

(a) zero crossing (b) peak negative amplitude
(c) peak positive amplitude (d) all of above
(Ans. : a)
Q.11 In PM signal frequency deviation of carrier is not proportional to ________.
(a) modulator phase shift (b) modulating signal frequency
(c) modulating signal amplitude (d) carrier amplitude and frequency
(Ans. : d)
Q.12 Compensation for 'increase in carrier frequency deviation with an increase in modulating
signal frequency is achieved by _______ circuit between modulating signal and phase
modulator.
(a) low pass filter (b) high pass filter (c) phase shifter (d) bandpass filter
(Ans. : a)
Q.13 If the amplitude of modulating signal given to the phase modulator circuit is constant, the
output signal will be ______.
(a) zero (b) carrier frequency itself
(c) above carrier frequency (d) below carrier frequency
(Ans. : b)
Q.14 A phase modulator varies the phase shift of the _________.
(a) carrier (b) modulating signal
(c) both carrier and modulating signal (d) none of above
(Ans. : a)
Q.15 The small change in frequency produced by phase modulator can be increased by using
________.
(a) amplifier (b) mixer
(c) frequency multiplier (d) frequency divider
(Ans. : c)
Q.16 The oscillator whose frequency is varied by an input voltage is called as ________.
(a) VXO (b) VCO (c) VFO (d) VHF
(Ans. : b)
Q.17 Which type of oscillators are preferred for carrier generation because of their good
frequency stability ?
(a) LC (b) RC (c) LR (d) Crystal
(Ans. : d)
Comparison between FM and AM
Q.1 The AM system is _________ immune to noise than the FM.

(a) more (b) less (c) equally
(Ans. : b)
TM

Q.2 Which of the following is the disadvantage of FM over AM ?

(a) A much wider channel is required by FM as compared to that for AM.
(b) The area of reception is limited.
(c) The modulating and demodulating equipment is complex.
(Ans. : d)
Q.3 Which of the following is the advantage of frequency modulation over amplitude
modulation ?
(a) Noise can be reduced by increasing deviation
(b) The amplitude of the FM wave in FM is independent of the depth of modulation,
whereas in AM it is dependent on this parameter
(c) There is a large increase in noise to signal ratio in FM
(d) All of the above
(Ans. : d)
Q.4 The main disadvantage of FM is _______.
(a) expensive and complex (b) excessive use of spectrum space
(c) less noise immunity (d) lower efficiency
(Ans. : b)
Q.5 Main disadvantage of FM over AM is________.
(a) very high modulating power is needed (b) high output power is required
(c) large bandwidth is required
(d) for high frequency signals noise is very high
(Ans. : c)
Q.6 Which of the following is not a major benefit of FM over AM ?
(a) Capture effect (b) Greater efficiency
(c) Better noise immunity (d) Reduced complexity and cost
(Ans. : a)
Q.7 Bandwidth of FM signal is _____ than AM signal.
(a) lesser (b) either lesser or larger
(c) larger (d) none of above
(Ans. : c)
qqq
TM

Telephone Systems and
10 Optical Fibre Communication
Chapter at a Glance
1. Full-duplex system : Both parties can communicate simultaneously.
2. Tandem office : Tandem office connects the central offices that do not have any
trunk line connection between them.
3. Pulse dialing : Initially, the telephone system used to dial a call by breaking the loop
circuit at a 10 Hz rate with the number of interruptions equal to the number dialed.
This method is known as pulse dialing.
4. Dual Tone Multi-Frequency (DTMF) : To dial a call Dual Tone Multi-Frequency
(DTMF) dialing method is used. In this method, a particular number is represented
by two different tones/frequencies. Thus, when predefined combination of two
frequencies occur, the corresponding number is dialed.
5. Cell in a mobile communication system : The basic concept behind the cellular radio
system is that rather than serving a given geographical area within a single
transmitter and receiver, the system divides the service area into many small areas
known as cells.
6. Fiber Optic Communication : The communication method in which transmission of
information takes place in the form of light signal with the help of optical fiber is
called fiber optic communication.
Ø Write a note on ISDN.
· ISDN was developed by ITU-T in 1976. ISDN is a protocol that combines both digital
telephony and data transport services.
· ISDN is a digital communication interface designed to replace the existing local analog
Public Switched Telephone Networks (PSTN).
(10 - 1)
TM

Basic Electronics 10 - 2 Telephone Systems and Optical Fibre Communication
· ISDN incorporates voice, data, video and fascimile information on the same common
carrier. It is an advanced set of telecommunication series based on existing telephone
networks. ISDN is an infrastructure to support a wide variety of services. The data
format is totally digital.
· The voice and data transmission is integrated over one system.
Ø Explain the types of services.
· The services available through ISDN include
1. Bearer services
2. Teleservices
3. Supplementary services
Services
Bearer services Teleservices Supplementary

services
Circuit Telephony Call waiting
switching
Telefax Reverse
Packet charging
switching Teletex
Message
Frame Telex handling
switching
Teleconferencing
Cell
switching
Fig. 10.1
Ø Explain BRI channel.
· BRI channel consists of 2 bearer channels (B) and 1 data control (D) channel. These
channels are time multiplexed on line. The BRI channel denoted by (2B + D). Fig. 10.2
shows BRI channel.
2B
Basic rate +
D
Fig. 10.2 BRI channel

· B-channel supports data rate of 64 kbps and D-channel supports data rate of 16 kbps.
The total data rate of (2B + D) channel can be 144 kbps. With framing control, the data
rate can be 192 kbps.
· All configurations of communication are possible i.e. simplex, half duplex and duplex.
The standard allows the B channels to be further multiplexed in sub-channels.
TM

Ø Explain PRI channel.

· The PRI channel consists of 23 bearer (B) and 1 data control (D) channel. These
channels are time multiplexed on line. The PRI channel is denoted by 23 B + D.
Fig. 10.3 shows PRI channel.
1 23B+D
2
Primary rate
23 D
Fig. 10.3 PRI channel
· Total bandwidth of PRI channel is 1.536 Mbps. The primary rate service is T 1
compatible.
Ø What are the disadvantages of fiber optic system ?

1. High initial cost : The initial installation or setting up cost is very high compared to
all other systems.
2. Maintenance and repairing cost : The maintenance and repairing of fiber optic
systems is not only difficult but expensive also.
The Telephone Systems
Q.1 Which of the following statements are true ?

(a) Telephone and broadcastings systems are same.
(b) The telephone signaling and current, voltage levels in subscriber line vary according to
the transmission system used.
(c) Compatibility of two different telephone systems is maintained by keeping consistency in
telephone signaling and current, voltage levels in the subscriber line
(d) None of these
(Ans. : c)
Q.2 In a telephone system, subscribers are connected to ______ so as to communicate with

other subscribers.
(a) central office (b) control office (c) tandem office (d) exchange office
(Ans. : a)
Q.3 In a telephone system ____ is used for communication between two subscribers connected
to same central office.
(a) trunk line (b) local loop (c) tandem office (d) central office switch
(Ans. : d)
Q.4 The two central offices of a telephone system are interconnected with the help of _____.
(a) central office switch (b) trunk line
TM

(c) central office (d) subscriber

(Ans. : b)
Q.5 In a telephone system, ____ acts as a connecting media when there is no trunk line
connection between two central offices.
(a) tandem office (b) subscriber (c) local loop (d) central office
(Ans. : a)
Q.6 Subscribers of a telephone system are connected to central office with the help of a
single ______.
(a) twisted pair cable (b) coaxial cable (c) fiber optic cable (d) all of these
(Ans. : a)
Q.7 Use of twisted pair cable eliminates ______ in a telephone communication.
(a) crossover dialing (b) crosstalk dialing (c) pulse dialing (d) none of these
(Ans. : b)
Q.8 In pulse dialing method, the breaking of loop circuit was done at _____ rate.
(a) 10 Hz (b) 20 Hz (c) 10 KHz (d) 20 KHz
(Ans. : a)
Q.9 DTMF stands for _____.
(a) Dial Tone Multi-Frequency (b) Dial Terminal Multi-Frequency
(c) Dual Tone Multi-Frequency (d) Dual Time Multi-Frequency
(Ans. : c)
Q.10 Telephone instruments use _____ as transmitter and ____ as receiver.
(a) magnetic earphones, carbon microphones
(b) magnetic microphones, carbon earphones
(c) carbon microphones, magnetic earphones
(d) carbon earphones, magnetic microphones
(Ans. : c)
Q.11 Telephone communication is ______ communication.
(a) simplex (b) half duplex (c) full duplex (d) none of these
(Ans. : c)
Principle of Operations of Mobile Phone
Q.1 In mobile communication, the system divides the service area into many small areas
known as ______.
(a) unit (b) cell (c) MSC (d) MTSO
(Ans. : b)
Q.2 In mobile communication MSC means _____.
(a) Mobile Service Center (b) Mobile Switching Center
(c) Mobile Service Control (d) Mobile Switching Control
(Ans. : b)
TM

Q.3 In mobile communication, MSC is also known as ______.

(a) MSTO (b) MTSO (c) MISO (d) none of these
(Ans. : b)
Q.4 The cellular system operates in the _____ range.
(a) 600 - 800 MHz (b) 800 - 900 MHz (c) 600 - 800 kHz (d) 800 - 900 kHz
(Ans. : b)
Q.5 In a cellular transmitter there are _____ transmit channels.
(a) 666 30 KHz (b) 500 20 KHz (c) 666 30 MHz (d) 500 30 MHz
(Ans. : a)
Q.6 In a cellular transmitter ____ circuit sets the transmitter to one of 8 power output levels.
(a) phase modulator (b) directional coupler (c) APC (d) Duplexer
(Ans. : c)
Q.7 In a cellular transmitter, for proper isolation the transmit and receive frequencies are
spaced _____ apart from each other.
(a) 40 Hz (b) 45 KHz (c) 45 MHz (d) none of these
(Ans. : c)
Q.8 What is the range of cellular receiver ?
(a) 825.03 MHz to 844.98 MHz (b) 870.03 MHz to 889.98 MHz
(c) 825.03 kHz to 844.98 MHz (d) 870.03 kHz to 889.98 kHz
(Ans. : b)
Integrated Services Digital Network (ISDN)
Q.1 ISDN stands for _____.

(a) Integrated Services Digital Network (b) International Subscribers Digital Network
(c) Integrated Subscribers Digital Network (d) International Services Digital Network.
(Ans. : a)
Q.2 ISDN has ___ types of services.
(a) two (b) three (c) four (d) six
(Ans. : b)
Q.3 In _____ of ISDN, the information content remains unchanged.
(a) bearer services (b) teleservices
(c) supplementary services (d) both (a) and (b)
(Ans. : a)
Q.4 Teleconferencing is an example of _____.
(a) supplementary services (b) bearer services
(c) teleservices (d) all of these
(Ans. : c)
Q.5 Call waiting, reverse charging come under ______.
(a) bearer services (b) supplementary services
(c) teleservices (d) all of these
(Ans. : b)
TM

Q.6 In ISDN, each user is linked to the central office through _____.
(a) trunk lines (b) digital pipes (c) both (a) and (b) (d) none of these
(Ans. : b)
Q.7 What is the data rate of B channels in ISDN ?
(a) 16 kbps (b) 64 kbps (c) 384 kbps (d) 74 kbps
(Ans. : b)
Q.8 In ISDN, D channels have data rate _____.
(a) 16 kbps (b) 64 kbps (c) 74 kbps (d) both (a) and (b)
(Ans. : d)
Q.9 ______ channels are available with data rates of 384 kbps, 1536 kbps or 1920 kbps.
(a) B (b) D (c) H (d) all of the above
(Ans. : c)
Q.10 PSTN stands for _____.
(a) Public Switched Telephone Networks.
(b) Priority Switched Telephone Networks.
(c) Public Switched Telecommunication Networks.
(d) Public Subscribed Telephone Network.
(Ans. : a)
Q.11 NT2 and NT1 are interconnected by ______ and is then known as ISDN interface.
(a) T-bus (b) S-bus (c) U-bus (d) none of these
(Ans. : a)
Q.12 In ISDN interface, communication devices are connected to NT2 by _____.
(a) T-bus (b) S-bus (c) U-bus (d) N-bus
(Ans. : b)
Q.13 BRI channel of ISDN interface consists of _______ B channel and _____ D channel.
(a) 1, 2 (b) 2, 1 (c) 3, 1 (d) 1, 3
(Ans. : b)
Q.14 BRI channel of ISDN interface is denoted by _____.
(a) 2B + D (b) 2D + B (c) B + D (d) 2B – D
(Ans. : a)
Q.15 For ISDN interface, total data rate of BRI channel can be ______.
(a) 124 kbps (b) 120 kbps (c) 140 kbps (d) 144 kbps
(Ans. : d)
Q.16 In ISDN interface, PRI channel consist of ______ B channel and ____ D channel.
(a) 23, 1 (b) 1, 23 (c) 2, 1 (d) 1, 2
(Ans. : a)
Q.17 BRI and PRI channels of ISDN interface are ______ multiplexed on line.
(a) time (b) frequency (c) code (d) all of the above
(Ans. : b)
Q.18 The PRI channel of ISDN interface is denoted by ____.
TM

(a) 23B + D (b) B + 23D (c) 2B + D (d) B + 2D

(Ans. : a)
Q.19 Total bandwidth of PRI channel of ISDN interface is ______.
(a) 1.536 Mbps (b) 1.536 kbps (c) 1.536 bps (d) none of these
(Ans. : a)
Fiber Optic Communication
Q.1 The transmission medium in optical fiber communication system is ______.

(a) twisted pair cable (b) coaxial cable (c) optical fiber cable (d) all of the above
(Ans. : c)
Q.2 In optical communication system, ______ converts the electrical analog or digital signal
into its corresponding optical signal.
(a) optical transmitter (b) optical receiver (c) light detector (d) light source.
(Ans. : a)
Q.3 In fiber optic communication, _______ regenerates the signal by restoring its power and
removing noise.
(a) regenerator (b) repeater (c) receiver (d) regulator
(Ans. : b)
Q.4 Fiber cables are made up of _____.
(a) copper cables (b) aluminum cable (c) silica glass (d) all of the above
(Ans. : c)
qqq
TM

Notes
TM

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As per Revised Syllabus of

Visvesvaraya Technological University

Chapter - 2 Bipolar Junction Transistor (2 - 1) to (2 - 22)

Chapter - 4 Introduction to Operational Amplifiers (4 - 1) to (4 - 28)

Chapter - 7 Microprocessors and Microcontrollers (7 - 1) to (7 - 26)

Chapter - 8 Transducers (8 - 1) to (8 - 10)

Chapter - 10 Telephone Systems and Optical Fibre Communication

1. Introduction to P-N Junction

2. Theory of P-N Junction

Material Symbol Value of barrier potential

3. The P-N Junction Diode

TECHNICAL PUBLICATIONS - An up thrust for knowledge

5. V-I Characteristics of Diode

Fig. 1.2 Complete V-I characteristics of a diode

6. Diode Current Equation and Nature of Characteristics

7. D.C. Equivalent Circuits of Diode

Sr. No. Diode approximation Behaviour D.C. Equivalent circuit

TECHNICAL PUBLICATIONS - An up thrust for knowledge

3. Complete d.c. equivalent This assumes finite forward Vg rf

Total diode drop is,

10. Transformer Utilization Factor (T.U.F.)

D. C. Power delivered to the load

11. Voltage Regulation

TECHNICAL PUBLICATIONS - An up thrust for knowledge

12. Comparison of Rectifier Circuits

Half Wave Full Wave Bridge

Sr. No. Parameter Half Wave Full Wave Bridge

6. A.C. power input ( PAC ) I2m ( R L + R f + R s) I2m ( R f + R s + R L) I2m ( 2R f + R s + R L)

7. Maximum rectifier efficiency ( h) 40.6 % 81.2 % 81.2 %

10. PIV rating of diode Esm 2 Esm Esm

13. Filter Circuits

The filter is an electronic circuit composed of capacitor, inductor or combination of

TECHNICAL PUBLICATIONS - An up thrust for knowledge

14. Approximate Analysis of Capacitor Filter

15. Expression for Ripple Voltage

16. Power Supply Performance

TECHNICAL PUBLICATIONS - An up thrust for knowledge

Ripple content in output VR(out)

17. Zener Diode as a Shunt Regulator

Fig. 1.3 Zener diode as a shunt regulator

18. Design of Zener Regulator

TECHNICAL PUBLICATIONS - An up thrust for knowledge

19. Series Negative Clipper Circuit

Fig. 1.4 Negative series clipper

(a) Input voltage (b) Output voltage

20. Series Positive Clipper Circuit

Fig. 1.6 Positive series clipper

(a) Sinusoidal input (b) Triangular input

TECHNICAL PUBLICATIONS - An up thrust for knowledge

21. Parallel Clipper with Positive Clipping

Input Vin D RL Vo Output

23. Clamper Circuits

TECHNICAL PUBLICATIONS - An up thrust for knowledge

Important Theory Questions and Answers

TECHNICAL PUBLICATIONS - An up thrust for knowledge

and current If increases suddenly. This If

becomes constant equal A I0

TECHNICAL PUBLICATIONS - An up thrust for knowledge

The diode current equation is,

· Once bias voltage exceeds cut in

TECHNICAL PUBLICATIONS - An up thrust for knowledge

Fig. 1.17 Current flow during negative half cycle

2I m Fig. 1.18 Load current waveform