MICRO EXIT EXAM REVIEWER: TEAM ECE 2K13

1. Signal that has I/O clk

Answer: CLK ?

2. Prevent changing the location POPA which register is not loaded with data
Answer: SP or ESP
*note: POPA Pop All Registers; Intel 80x86; move memory pointed to by stack pointer to all 16-bit general
purpose registers (except for ​SP​); does not affect flags

3. Machine code for LAHF

Answer: 9F
*note: 9E kapag SAHF sabi ni james

4. Pushes all registers to the stack

Answer: PUSHA
*note: PUSH - push data onto stack
PUSHW - push word onto stack
PUSHD - push double word onto stack
PUSHA - push all registers to stack (60)
Order: AX, CX, DX, BX, SP, BP, SI, DI
PUSHF - push flags onto stack (9C)

5. How many additional control reg are activated based from Pentium’s protected mode
Answer: 5

6. 8088 I/O ad space, number of I/O ports?

Answer: 4096
*note: The 8088's I/O addressing space contains 65 536 (2^16)

7. Machine code ROL BYTE PTR[SI], 1

Answer: final value = 82H → D004 - ​1101 0000 0000 0100 ​(Ryan) pano to nakuha?

8. Result of executing RCR, AX, CL if CL contains 2 and AX contains ABCDh

Answer: AAF3 Machine Code: D3D8

9. Machine code XOR AX, CX -

Answer: 31C8 or 0011 00011100 1000

10. AX, BX, CX = 1234H, 5678H, 9ABCH ; result of SHRD BX, CX, 8?
Answer: BC56; Machine Code: 0FAC CB08
*note: 9ABC -> 5678 ??? waz diz
11. Lower byte of flag reg = 83H. Which flag registers are set as a result of LAHF instruction?
Answer: SF​ (James)

12. Instruction that sets carry flag to 1

Answer: STC
*note: Sets carry flag to 0 - CLC

13. Based from order, when PUSHA is applied which register is PUSHED first?
Answer: AX
*note: Processors pushed the registers in the order: AX, CX, DX, BX, SP, BP, SI and DI. The SP word
pushed is the value before the first register is pushed.

14. What does the command IN AL, DX mean?

Answer: IN Al,DX : Input byte from I/O port in DX into AL

15. Based from order, when PUSHA is applied which register is PUSHED last?
Answer: DI
*note: Processors pushed the registers in the order: AX, CX, DX, BX, SP, BP, SI and DI. The SP word
pushed is the value before the first register is pushed.

16. Standard bus connector agreed by PC bus connector agreed upon by the PC business
comprising of 62 pins found in early PC motherboards that allow expansion with the 8088
microprocessor
Answer: ISA connector - RYAN

17. Which is false for r/m

a. r/m register enclosed in brackets (tama to)
b. r/m used for addressing mode (tama din to)
c. r/m specifies addressing mode
d. Mode = 11; r/m = register field

18. ARM stands for

Answer: Advanced RISC Machines

19. Which is a valid conclusion?

Choices:
(a) All hummingbirds are richly colored
(b) No large birds live on honey
(c) Birds that do not live on honey are dull in color
(d) Hummingbirds are small

Answer: (c) Birds that do not live on honey are dull in color
20. Determine in-degree in vertex b? ​Answer: 5
Matrix: a b c d
a 0 ​2​ 3 0
b 1​ 2​ 2 1
c 2 ​1​ 1 0
d 1 ​0​ 0 2
*note: the number of head ends adjacent to a vertex is called the indegree of the vertex and the number
of tail ends adjacent to a vertex is its outdegree

Ex.

21. Which of the ff correctly describes the graph

Matrix: a b c
a101
b001
c111
a. Simple directed graph with 3 vertices
b. Pseudograph with 3 vertices
c. Directed multigraph with 3 vertices
d. Simple multigraph with 3 vertices
22. Consider the symbolic logic taken from Lewis Caroll illustrating how quantifiers are used in
statements. Which of the following is/are premises?
I. All lions are fierce
II. Some lions dont drink coffee
III. Some fierce creatures do not drink coffee
Answer: ​I and II

23. GIven the undirected graph V = {a,b,c,d,e} with E = {(a,b).(a,d),(b,c),(c,d),(d,e)} is classified

as?
Answer: Eulerian Path ( visits every edge exactly once )

Note: Eulerian circuit - visits every edge exactly once and starts and ends on the same vertex
Hamiltonian path - visit every vertex only once

24. Under precedence of logical operators which is performed last?

Answer: BICONDITIONAL
*note: precedence of logical operators → NOT(Negation), AND(Conjunction), OR(Disjunction), IMPLIES
(Conditional), IFF (Biconditional)

25. Which of the ff relation from Set A {integer numbers} is considered as equivalence relation?
a. R = {(a,b) | a > b or a = b }
b. R = {(a,b) | a b (mod m) with m > 1}
c. R = {(a,b) | a + b = 3}
d. R = {(a,b) | a < b}

26. Set A = {integer numbers}, which is ​anti​symmetric

 a. R = {(a,b) | a > b}
b. R = {(a,b) | a + b = 3}
c. R = {(a,b) | a - b = -4}
d. R = {(a,b) | a = b or a = -b}

27. Which of the ff logical operator is performed first?

Answer: AND
*note: precedence of logical operators → NOT(Negation), AND(Conjunction), OR(Disjunction),
IMPLICATION, BICONDITIONAL(Equivalence)
P. S. Wala sa choices yung NOT so AND ang sagot :)

28. Which of the following relations from Set A = [1,2,3,4] to Set A is considered transitive?
Answer: {(1,1),(1,2),(2,1)}

29. V = {a,b,c,d,e}, E = {(a,b),(a,c),(b,c),(c,d),(c,e),(d,e)} is classified as? [Hamiltonian but not

Eulerian; neither H or E; H and E; E but not H]
Answer: Eulerian cycle but not Hamiltonian

30. The expression below is regarded as (p ^ q) -> (p v q)

Answer: TAUTOLOGY

p q p^q pvq (p ^ q) -> (p v q)

0 0 0 0 1

0 1 0 1 1

1 0 0 1 1

1 1 1 1 1
31. Give the adjacency matrix of the graph G {a,b,c,d}, How many number of paths from a to d
has a length exactly equal to 4?
a b c d
a 0 1 1 0
b 1 0 0 1
c 1 0 0 1
d 0 1 1 0
Answer: 8

32. A u A’ = U
ANSWER: COMPLEMENT LAW - DAN

33. WHich of the propositional expression is contradiction?

a. (p ^ q)’ -> p
b. (p -> q)’ -> q’
c. (p -> q)’ -> p
d. (p->(p v q))’ - room 303

34. GIven a synchronous sequential circuit what is the next state with input = 0, if the current
state is 010?
Answer: 100

35. Decimal parallel adder that adds 5 decimal digits requires how many BCD adder stages?
Answer: 5​ ​- in parallel adder n digits need n stages (pag multiplier n-1)

36. Simplify the Boolean function to a minimum number of literals

A B C T1
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0

A'(B' + C) ----> A’(B’+C’) dapat

A + BC

A'B + C
ABC + A'B'C'

37. How many base theorems and postulates to prove x + xy = x

Answer: 3
*note: ( X(1+Y)) 3 namely; LAW OF UNION, DISTRIBUTIVE, LAW OF INTERSECTION)
- james
Eeewwww i don’t like this question xD

38. 10110 - 01101 using 1’s complement

Answer: 01001
*note:
10110
+ 10010 (1’s complement of minuend)
​1 ​ 01000 (There is an overflow, Add 1 to Result)
+ ​ 1
​01001

39. 10 - 1000 gates in a single package:

Answer: LSI
*note: (if more than 100 gates, matic LSI)
SSI - less than 100, about 10 gates
MSI - less than 500 or more than 10 but less than 100 gates
LSI - 500 to 300000 or have more than 100 gates

40. 4 input (D0-D3) priority encoder circuit contain 3 output (x,y) pertaining to arbitrary values.
What is the function for least significant bit x?
Answer: D2 + D3

41. If an ASCII of A is used with odd parity, the results is

Answer: 11000001

42. F = xy + x’z express as product of maxterms

Answer: M(0,2,4,5)

43. Master slave D-flip flop is similar to a synchronous edge triggered flip flop, therefore it
should have the ff behavior except?
Answer: a change in output is activated by a clock pulse.
44. GIven a synchronous sequential circuit what is the next state with input = 1, if the current
state is 001?
Answer: 010 - room 304

45. Product term wherein which all variables appear once rather complement or
uncomplemented
Answer: ​ ​minterm

46. 74LS83 is an example 4-bit parallel adder to expant to 8-bit you must
Answer: Two half adders with the carry output of one connected to the input of the other

47. Race condition in R-S Latch

Answer: R =1 S=1

48. 3x8decoder D0 to D7 which output is activated high if input x’yz’

Answer: D2

010 = 2

49. The complement of F = [x(y’z’ + yz)]

Answer:

F=xy’z’ + xyz
x\yz 00 01 11 10
0 0 ​0 0 ​0
1 1 ​0 1 ​0

F’ = x(y+z’)(y’+z)

50. If an ASCII of A is used with even parity the results is

Answer: 0100 0001

51. What law: p v p = p

Answer: idempotent law
*note if: ​pwede din daw p^p = p
p ^ 1 or p v 0 - identity law
p ^ (pvq) = p or p v (p^q) = p - absorption law

52. Which of the ff vertex is called a pendant?

Answer: ​Leaf
I think the question is from a graph

53. Using 2’s complement, what is the binary equivalent of -7?

Answer: 1001

54. What is the highest privilege (RPL) in protected mode?

Answer: 00
*note: 00 - highest
01
10
11- lowest

55. System signal used in troubleshooting techniques for 8088 hardware architecture?
Answer: INTR

56. Addressing mode executes its instructions within CPU without the necessity of reference
memory for operands?
Answer: Register Mode

57. The ____ part specifies the addressing mode for the selected instruction
a. MOD
b. Addr-low
c. REG
d. R/M
Answer: MOD

58. Flag register contains 10000011 on its lower byte which flag registers are set as a result of
executing LAHF instruction?
Answer: SF and CF

59. Which technique does the Pentium Pro employs where the processor looks ahead into the
instruction stream pipeline can be kept busy?
Answer: Speculative execution

60. Result of executing RCL DL, 1; cleared flags; DL contains 93h

Answer: 26h. Machine code: D0D2

61. 2 to 4 line decoder, made of NAND gates which input would produce an output of 1011 from
D0 to D3
a. 1XX
b. 001 ← this was my guess
c. 011
d. 010

Guess:
D0 0111
D1 1011
D2 1101
D3 1110

62. If the function v(w+x+y)z would be implemented using NOR gates?

Answer: Six NOR gates will be used

63. 2 bit by 2 bit multiplier can be constructed by using:

Answer: 2 Half Adders and 4 AND gates

64. How many 4-binary adders are needed to create a single digit binary adder?
Answer: 4? idk

65. 4-bit magnitude comparator combinational circuit A < B what logic gate?
Answer: 4-input OR gate
*note: if A = B, 4 input AND logic gate

66. Which of the ff is a bit manipulation instruction?

a. SHL DL, 2
b. Any
c. ROL AX,1
d. NOT AL
*note: Bit Manipulation: NOT, AND, OR, XOR, TEST, BT, BTC, BTR, BTS, SHL/SAL,
SHR/SAR, ROL/ROR, RCL/RCR,
Arithmetic: ADD, ADC, INC, DEC, SUB, SBB, DEC, CMP, MUL, IMUL, DIV, IDIV, NEG, CBW,
CWD, DAA, DAS, AAA, AAS, AAM, AAD

67. What segment is used for store destination string?

a. ES
b. Any
 c. DS
d. CS

68. If 8088 has frequency of 4MHz, the time of one T state? [200 ns; 80 ns, 250 ns; 300 ns]
Answer: 250 ns

69. The adjacency matrix of the graph is seen below, determine how many edges are in the
graph.

Answer: 10

70. SHLD AX, BX, 4

Answer: AX = 2345H; Machine Code: 0FA4 D804

71. Which of the following is a logical instruction?

Answer: TEST

72. This input is used to force the Pentium to limit addressable memory to 1 Mb to emulate the
memory space of the 8086.
Answer: A20M

73. mm = __ is automatically used for direct addressing

Answer: 00

74. The binary value 0111 represent a decimal value of 1 in this decimal code
Answer: 8 4-2-1
 75. given the following point below
Gr to SW 113 mi
Gr to Kal 56 mi
Gr to Det 147 mi
Gr to Tol 167 mi
Kal to SW 137 mi
Kal to Det 135 mi
Kal to Tol 133 mi
Tol to Det 58 mi
Tol to SW 142 mi
Det to SW 98 mi

a.) Det- Tol- Kal- GR-Sw – Det = 458 - SHORTEST

b.) Det – Tol-Gr-Kal-Sw-Det = 516
c.) Det-GR-Sw-Tol-Kal-Det = 670 - LONGEST
d.)Det-Sw-Tol-GR-Kal-Det = 598

76. A parity bit is used in error detecting codes, if an ASCII of T is used with odd parity the result
is
Answer: 0101 0100

77. ROR AX, 1

Answer: AX = 4FA5H Machine Code:D1C8

78. Direction flag is set to 0 using this instruction.

Answer: CLD

79. These instructions are used to preserve the contents of the outer loop counter
Answer: PUSH and POP
80. Digital integrated circuits are classified not only by their complexity or logical operation, but
also by the specific circuit technology to which they belong. The circuit technology is referred to
as ____.
Answer: digital logic family

81. Simplify F(v, w, x, y, z) = Σm (0, 1, 2, 4, 5, 8, 9, 10, 12, 16, 17, 18, 20, 21, 24, 26, 29) using
Karnaugh map.
a. v’w’y’ + v’x’z’ + vxz + v’y’z’ + v’x’y’ + vxy’z
 b. w’y’ + x’z’ + v’y’z’ + v’x’y’ + vxy’z
c. none of the choices
d. vw’y’+ v’x’z’ + vxz + v’y’z’ + v’x’y’ + v’xy’z

82. The 74LS83 is an example of a 4-bit parallel adder. To expand this device to an 8-bit adder,
you must
Ans: Use two adders with the carry output of one connected to the carry input of the
other

83. A processor running in this mode can exploit only the lowest 20 bits of its address bus and is
therefore limited to the meager 1MB memory space.
Answer: Real mode

84. This method of storing 16-bit numbers in memory, wherein the lower byte is already
read/write to the lower memory address
Answer: Little Endian

85. . Intel introduced cache memory for this microprocessor when it was launched. The Western
Design Center, Inc (WDC) introduced this microprocessor in 1982 and was used as the CPU in
the Apple IIe and IIc personal computers.
Answer: CMOS 8502

86. Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
Answer: AND gates, OR gates, and NOT gates
p xor q = -(p ^ q) ^ (p v q)

87. The following is true for r/m except for

Ans. r/m specifies addressing mode

88. The 2-4-2-1 code of 7 is:

Answer: 1101

89. What is the canonical form of the simplified function F = C ‘D + ABC ‘+ ABD ‘+ A ‘B ‘D
a. M (0,1,2,3,5,9,11,12,14)
b. M (1,3,4,5,6,7,9,10,12,14,15)
c. M (0,2,4,6,7,8,10,11,15)
d. M (1,3,5,9,12,13,14)

90. Determine the canonical form of the simplified Boolean expression F = x‘y‘z + xy
a. m (0,5,7)
b. m (2,4,7)
c. m (2,3,7)
d. m (1,6,7)
91. Determine the canonical form of the simplified Boolean expression F=x‘y‘z‘ + xz
a. m (0,5,7)
b. m (2,4,7)
c. m (0,2,3,7)
d. m (1,6,7)

92. Determine the canonical form of the simplified Boolean expression F2 = xy‘z‘ + x‘y
a. m (0,5,7)
b. m (2,4,7)
c. m (2,3,4)
d. m (1,6,7)

93. How many pass will it take in order to sort the single digit array 3 5 4 1 2 using selection
sort?
a.) 5
b.) 4
c.) 6
d.) 10

94. 4 input (D0-D3) priority encoder circuit contain 3 output (x,y) pertaining to arbitrary values.
What is the function for least significant bit y?
Answer: D2 + D3
(MSB - D3 + D1D2’)

96. The higher byte of the flag register contains 83h. Which flag registers are cleared as a result
of executing LAHF instruction?
Answer: AF

97. The graph is represented by the adjacency matrix below. Determine the out-degree in vertex
d

Answer: 3

98. Simplify the Boolean function.

A B C T

0 0 0 1
 0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 0

1 0 1 0

1 1 0 0

1 1 1 0

Answer: T=A’B’C’+A’B’C+A’BC’

99. A 2 by 2 bit multiplier is simply implemented using which of the following combinational
circuit?
Answer: 2 Half Adders and 4 AND gates

100. The 2’s complement representing the value -12 is

Answer: 10100

101. This is the time needed by a gate in processing its input signals before the output signal
can be generated
Answer: propagation delay time

102. An algorithm that uses Hamiltonian cycle to solve uses a Big-O notation of
Answer:logarithmic complexity

103. What is the result of NEG AX if AX contains FFECh?

Answer: 0014h machine code: F7D8h

104. Express the function below as a standard form product of maxterms. F = xy + x'z

(x + y + z)(x + y' + z)(x' + y + z')

(x + y + z)(x + y' + z)(x' + y + z)
(x' + y)(x + z)(y + z)
(x + y + z)(x + y' + z)(x' + y + z)(x' + y + z')

105. Express the following function as a sum of minterms: (xy + z)(y + xz)
x’yz + xy’z + xyz’ + xyz
x’y’z + xy’z + xyz
x’yz + x’y’z + xyz’+ xyz
x’y’z + xyz’ + x’y’z’

106. Simplify the Boolean function to a minimum number of literals.

AB C T2
00 0 0
00 1 0
01 0 0
01 1 1
10 0 1
10 1 1
11 0 1
11 1 1

A + BC
ABC + A'B'C'
A'(B' + C')
AB + C

A\BC 00 01 11 10
0 0 0 1 0
1 1 1 1 1

107. there exists x not P(x)

there is an x for which P(x) is false

P(x) is true for every x
there is an x for which P(x) is true
every x, P(x) is false ← “negation law” - lodi

108. A union not A = U

Answer: complement law

109. Determine which of the given relations on the set of all integers is an antisymmetric relation
where (x, y) is an element of R.
x is not equal to y
x is greater than or equal to y2
x is a multiple of y
xy is greater than or equal to 1
110. Determine which of the given relations on the set of all integers is an equivalence relation
where (x, y) is an element of R.

x is a multiple of y
x greater than or equal to y2
x = y2
x and y are both negative or both nonnegative

111. An algorithm that uses Hamiltonian cycle to solve uses a Big-O notation of
Answer: logarithmic complexity
Eulerian Path/bubble sort ----> Linear Complexity
Selection ----> quadratic

112. Simplify the Boolean function

F(A,B,C,D) = m(0,2,3,5,7,8,10,11,13,15)

B'C + CD + BD
B'D' + BD +B'C
B'D' + BD + A'C'D
A'B'D' + AB'D' + CD

surjective (onto) ----> domain (x) >= range (y)

injective (one-to-one) ----> domain (x) <= range (y)
bijective ----> domain (x) = range (y)

Order:
Not - Negation
And - Conjunction
Or - Disjunction
Implication
Equivalence

For reference ng mga namomodify na flags sa mga instructions

http://www.mathemainzel.info/files/x86asmref.html

Opcode of Common Instructions

● Convert Byte to Word - CBW - 98
● Clear Carry - CLC - F8
● Clear Direction Flag - CLD - FC
● Clear Interrupt Flag - CLI - FA
● Convert Word to Doubleword - CWD - 99
 ● Decrement - DEC - 48
● Halt - HLT - F4
● DIV, IDIV - F6 or F7
● Interrupt - INT - CC or CD
● Load Effective Address - LEA - 8D
● No Operation - NOP - 90
● Set Direction Flag - FD
● Set Interrupt Flag - FB

Modifies flags
● NOT -> None
● OR -> CF OF PF SF ZF (AF undefined)
● PUSHA -> None
● PUSHF -> None
● SAL/SHL -> CF OF PF SF ZF (AF undefined)
● XOR -> CF OF PF SF ZF (AF undefined)

ASCII Code Table

1. execution time for an ALU instruction going from memory to immediate -> 16 + EA
Mem → imm 17 + EA
Imm → mem 17 + EA
Mem → reg 9 + EA
Reg → mem 16 + EA
2. Segment address -> located within one of the segment registers, beginning address
3. NVM -> store most important; non-volatile memory, stores memory even if power is lost
4. XOR -> Parity Flag
5. Processor status is described as condition codes, or status flags.
6. Overflow occurs with respect to the size of the data type that must accommodate the result.
7. To perform a decrement operation that does update the CF flag, use a SUB instruction with
an immediate operand of 1.
8. The instructions affect the OF, SF, ZF, AF, and PF flags just like addition and subtraction of
one., INC & DEC
9. XOR instruction always clears OF and CF flags.
10. LAHF instruction loads lower byte of the EFLAGS register into AH register.
11. The lowest 8 bits of the flags are transferred:
Sign
Zero
Auxiliary Carry
Parity
Carry
12. SHL affect the CF
13. SHL is very useful for computing powers of 2 and multiplication by 2, since each time binary
number is shifted left, its numeric value doubles.
14. XTs -> Intel 80186; ATs -> Intel 80486
15. lower 12 bits of physical address are the same with the virtual address.
16. 3 variable odd function -> 2 AND and 1 OR dual input gates
17. 8008 - 11 registers