2018 2nd IEEE Advanced Information Management,Communicates,Electronic and Automation Control Conference(IMCEC 2018)

Prioritization Design and Implementation of ADC

Baesd on State Machine
Jing Wu
Intelligent Science and Information Engineering College
Xi’an Peihua University, Xi’an, China
448737641@qq.com

Abstract—Analog to Digital Converter is widely used in many Fig. 1. The overall system block diagram.
fields. Using the design methods of Moore state machine and Mealy
state machine, design and realization of ADC based on FPGA is
presented. And the FPGA system is designed, compiled and III. SAMPLING STATE DIAGRAM OF ADC0809
simulated in QuartusII. The improved method has high speed In order to have high extensibility and versatility, the input
characters of state machine, real-time characters built by FPGA interface uses the ADC0809 controlled by the signal process
and flexibility of software. By the VHDL simulation, there are the
state machine. The working state of ADC0809 is described as
two improved methods are is improved to be effective.
follows. ALE is address latch signal of input and it is effective
Keywords—Analog to digital converter (ADC);Field in the rising edge of the effective. START is control signal to
programmable gate array(FPGA); State machine start converting and it is effective in high level. When EOC is
an analog signal and low level, it means being conversion.
When it finishes conversion, EOC turns into high level. Then
I. INTRODUCTION EOC changes from low level to high level which is controlled
Analog to digital converter(ADC[1]) is a circuit or device by outside signal. Now, the data bus of output of 0809 change
that converts an analog input signal[2] to a digital signal which from the high impedance state to effectiveness of output data.
is easier to store and process. ADC has been widely used in Mealy state diagram is made from its working state. Sampling
mechanical, electromechanical, metallurgy, chemical industry state diagram of ADC0809 is shown in Figure2.
and so on. However, in the case of high speed motion control,
the performance of ADC is not ideal. The single process Mealy ALE<='0'; START<='0';
ALE<='1'; START<='1';
LOCK<='0'; OE<='0'
state machine and it’s design technique can realize the high LOCK<='0';OE<='0'
Initialization of ADC0809 Start ADC conversion
efficiency and reliability of the practical digital system. The
superiority of this system could scarcely be surpassed by st0 st1
central processing unit (CPU[3]) which can realize the same
function. At the same time, Field programmable gate
array(FPGA[4]) can adjust the desired system on the electronic
design automation (EDA[5]) platform, so it has the advantages
of flexibility, reusability, low cost, and adjusting data in time
by software. Therefore, ADC based on FPGA is designed using ';
st4 st3 st2
single process Mealy state machine. EOC='0'
ALE<='0'; START<='0'; ALE<='0'; START<='0 Being conver
sion
LOCK<='1'; OE<='1' LOCK<='0'; OE<='1'
II. DESIGN PRINCIPLE Latching coverted dates data output valid EOC='1'
Ending conversion
The overall system block diagram of ADC based on FPGA
is shown as follows.
Fig. 2. Sampling state diagram of ADC0809.

IV. ADC0809 DESIGNED AND REALIZED BY MOORE STATE

Moore state Mealy state MACHINE WITH FOUR PROCESSES
machine machine
comparison In QuartusII, according to Sampling state diagram of
ADC0809, ADC0809 is designed and realized based on Moore
State Machine with Four Processes. The corresponding VHDL
ADC0809 DAC0809 code is synthesize and simulated on programmable logic
controller controller device, EP2S15F484C3 device of Stratix ϩ. Using the design
method of Moore state machine, design and realization of ADC
based on FPGA is presented.
Implementation based on FPGA

978-1-5386-1803-5/18/$31.00 ©2018 IEEE 2601

 A. Design and Realizationof ADC0809 based onMoore
state machine with four processes
The corresponding VHDL code of ADC0809is written, in
which one timing process, two combinational processes, and
one flip-latch process are all designed by Moore state machine.
The VHDL code is omitted.

B. Synthesization of ADC0809 based onMoore state

machine with four processes
The design of ADC0809 is synthesized and hardware
circuit of ADC0809 is shown as follow. Fig. 3. Hardware circuit of ADC0809 based on Moore state machine with
four processes.

The hardware circuit of ADC0809 only have one register.

C. Simulation of Universal ADC0809 based onMoore

state machine with four processes
In QuartusII it is designed, compiled and emulated.
Simulation waveform of ADC0809 is shown in Figure4.

Fig. 4. Simulation waveform of ADC0809 based on Moore state machine with four processes.

QuartusII, according to Sampling state diagram of ADC0809,

LOCK and REGL are internal signals, CLK and EOC are
control signals. The rules of states are as
follows:cst.st0=>ALE<='0';START<='0';LOCK<='0';OE<='0';
cst.st1=>ALE<='1';START<='1';LOCK<='0';OE<='0';cst.st2=
>ALE<='0';START<='0';LOCK<='0';OE<='0';cst.st3=>ALE<
='0';START<='0';LOCK<='0';OE<='1';cst.st4=>ALE<='0';ST
ART<='0';LOCK<='1';OE<='1'.According to the rules of states,
the cst which is the output of states is got. When cst.st3 and clk
are obtained, Q that is output signal export 07 ࠊ 2A
corresponding analog input values in real time. It shows that
the function of ADC0809 is well simulated and there are few
burrs in the simulation waveform. So ADC0809 is designed
and realized based on Moore State Machine with Four
Processes is effective.
V. ADC0809 DESIGNED AND REALIZED BY MEALY STATE
MACHINE
Using the design method of Mealy state machine, design
and realization of ADC based on FPGA is presented. In
ADC0809 is designed and realized respectively based on
Mealy state machine with one Process and Mealy state
machine with Four Processes. The two methods corresponding
VHDL codes are synthesize and simulated on programmable
logic device, EP2S15F484C3 device of Stratix ϩtoo.
A. Design and Realizationof ADC0809 based onMealy
state machine with one process
The corresponding VHDL code of ADC0809 is written, in
which timing process, combinational process, and flip-latch
process all designed in one process based on Mealy state
machine. The core VHDL code is omitted.
B. Synthesization of ADC0809 based onMealy state
machine with one process

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Fig. 5. Hardware circuit ofADC0809 based on Mealy state machine with one process.

The hardware circuit of ADC0809 has four registers.

C. Simulation of Universal ADC0809based onMealy state
machinewith one process
In QuartusII it is designed, compiled and emulated.
Simulation waveform of ADC0809 is shown in Figure6.

Fig. 6. Simulation waveform of ADC0809 based on Mealy state machine with one process.

According to the rules of states, the cst which is the output time. It shows that the function of ADC0809 is well simulated
of states is got, When cst.st3 is obtained, Q that is output signal and there are some burrs in the simulation waveform. So
export83, 17and 53corresponding analog input values in real

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ADC0809 is designed and realized based on Mealy State
Machine with one process is not effective.

D. Design and Realizationof ADC0809 based onMealy

state machine with four processes
The corresponding VHDL code ofADC0809is written, in
which timing process, two combinational processes and one
flip-latch process are all designed in four processes by Mealy
state machine. The core VHDL code is omitted.
Fig. 7. Hardware circuit of ADC0809 based on Mealy state machine with
E. Synthesization of ADC0809based on Mealy state four processes..
machine with four processes
The hardware circuit of ADC0809 is shown as follow.
The hardware circuit of ADC0809 only have one register.
F. Simulation of Universal ADC0809 based on Mealy
state machine with four processes
In QuartusII it is designed, compiled and emulated.
Simulation waveform of ADC0809 is shown in Figure8.

Fig. 8. Simulation waveform of ADC0809 based on Mealy state machine with four processes..

This work was supported by the Shaanxi Province

According to the rules of states, When cst.st3 and clk Science Foundation under Grant No.17JK1056.
are obtained, Q that is output signal export 7F and A9
corresponding analog input values in real time. It shows that
the function of ADC0809 is well simulated and there are few REFERENCES
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ACKNOWLEDGMENT

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