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a)
library ieee;
use ieee.std_logic_1164.ALL;
entity problema1 IS
PORT(
A,B,C,D : IN STD_LOGIC;
F : OUTSTD_LOGIC);
end problema1 ;
begin
F <= (A AND NOT(C)) OR (B AND NOT(C)) OR (NOT(C) AND NOT(D)) OR (A AND B) OR (A AND
NOT(D)) ;
end solucion;
b)
library ieee;
use ieee.std_logic_1164.ALL;
entity problema1 IS
port(
A,B,C,D : IN STD_LOGIC;
F : OUTSTD_LOGIC);
end problema1 ;
begin
end solucion;
2)
a)
library ieee;
use ieee.std_logic_1164.ALL;
entity problema1 IS
PORT(
A,B,C,D : IN STD_LOGIC;
F : OUTSTD_LOGIC);
end problema1 ;
begin
F <= ((x I AND x3) OR (NOT xl AND NOT x3)) OR {R2 AND x4) OR (NOT x2 AND NOT x4));
end solucion;
b)
library ieee;
use ieee.std_logic_1164.ALL;
entity problema1 IS
port(
A,B,C,D : IN STD_LOGIC;
F : OUTSTD_LOGIC);
end problema1 ;
begin
F <= (x 1 AND x2 AND NOT x3 AND NOT x4) OR (NOT x 1 AND N-OT x2 AND x3 AND x4) (xl AND NOT
x2 AND NOT AND x4) OH (NOT x 1 AND x2 AND x3 AND NOT x4);
END solucion;
library ieee;
use ieee.std_logic_1164.all;
entity obligatorio1 is
port (x1 : in std_logic;
x2 : in std_logic;
x3 : in std_logic;
x4 : in std_logic;
f : out std_logic);
end obligatorio1;
library ieee;
use ieee.std_logic_1164.all;
entity obligatorio2 is
port (x1 : in std_logic;
x2 : in std_logic;
x3 : in std_logic;
x4 : in std_logic;
f : out std_logic);
end obligatorio2;
library ieee;
use ieee.std_logic_1164.all;
entity obligatorio3 is
port (x1 : in std_logic;
x2 : in std_logic;
x3 : in std_logic;
x4 : in std_logic;
f : out std_logic);
end obligatorio3;
library ieee;
use ieee.std_logic_1164.all;
entity obligatorio4 is
port (x1 : in std_logic;
x2 : in std_logic;
x3 : in std_logic;
x4 : in std_logic;
f : out std_logic);
end obligatorio4;