Anil Kumar Maini, Varsha Agrawal, Nakul Maini-Wiley Acing The GATE Examination For Electronics and Communication Engineering-Wiley

WILEY ACING THE GATE
ELECTRONICS AND COMMUNICATION ENGINEERING

ELECTRONICS AND
COMMUNICATION ENGINEERING
Dr Anil Kumar Maini

Senior Scientist and former Director of Laser Science and Technology Centre
Defence Research and Development Organization, New Delhi
Varsha Agrawal
Scientist, Laser Science and Technology Centre
Defence Research and Development Organization, New Delhi
Nakul Maini
Copyright 2015 by Wiley India Pvt. Ltd., 4435-36/7, Ansari Road, Daryaganj, New Delhi-110002.
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First Edition: 2015

ISBN: 978-81-265-4543-8
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Printed at:
edicated with love to my wife Renuka, daughter Nupur,
D
son-in-law Karan and my son and co-author Nakul.
Dr Anil K. Maini
Dedicated to my loving mom, Mrs Kussum Agrawal

I hold you close within my heart and there you will remain
To walk with me throughout my life, until we meet again
I miss you so much.
Varsha Agrawal
In the memory of my grandparents for their countless blessings

Shri Sukhdev Raj Maini
Shrimati Vimla Maini
Shri Ramji Bazaz
Shrimati Sarla Bazaz
Also dedicated to my mother Shrimati Renuka Maini
and my sister Nupur Maini for their love and support.
Nakul Maini
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FM.indd 6 6/30/2015 1:23:52 PM
PREFACE
Wileys Acing the GATE Examination in Electronics and Communication is intended to be the complete
book for those aspiring to compete in the Graduate Aptitude Test in Engineering (GATE) in Electronics and
Communication discipline, comprehensively covering all topics as prescribed in the syllabus in terms of study material,
quick reference support material and an elaborate question bank. There are host of salient features offered by the book
as compared to the content of the other books already published for the same purpose. Some of the important ones
include the following.
One of the notable features of the book includes presentation of study material in simple and lucid language and
in small sections while retaining focus on alignment of the material in accordance with the require-
ments of GATE examination. While it is important for a book that has to cover the whole gamut of subjects in
electronics and communication engineering to be precise in the treatment of different topics; the present book achieves
that goal without compromising completeness. The study material and also the question bank have all the three
important `C qualities for effective communication across to the examinees including Conciseness, Completeness and
Correctness.
Another notable feature of the book is inclusion of summary of important mathematical expressions and
formulas towards the end of each topic. It is pertinent to mention that based on analysis of GATE examination
questions in the last ten years reveals that more than 30 per cent of GATE questions were based on important
mathematical formulations and their interpretation. While the study material would help examinees understand the
concepts; the summary of mathematical formulations would provide to them a ready reference close to the examination
day to ace the examination.
The third important feature of the book is its comprehensive question bank. The question bank is organized in
three different categories namely the Solved Problems, Practice Exercise and GATE Previous Years Questions. Solved
problems contain a large number of multiple choice questions and numerical answer questions of varying complexity.
Each question in this category is followed by its solution. Under the Practice Exercise, again there are multiple choice
and numerical answer questions with marks allocated for each question. The answers to these questions are given at the
end of the section. Each of the answers is supported by an explanation or a solution hint unlike other books where solu-
tions to only selected questions are given. The third category contains questions from previous years GATE examinations
from 2003 onwards. Each question is followed by a complete solution and is marked for year of examination and marks.
Briefly outlining the length and breadth of the material presented in the book, it is divided into eight broad sections
in line with the prescribed syllabus. Each of the sections comprises more than one chapter. In all, there are fifty two
chapters spread out in eight different sections. The book begins with the section on Networks (Section-I). The section
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viii PREFACE
is divided into seven chapters covering network graphs, solution methods, network theorems, steady state sinusoidal
analysis, linear constant coefficient differential equation analysis of networks, two-port networks and state equation
analysis of networks. It is followed by second section on Electronic Devices (Section-II) covering semiconductor
physics, semiconductor diodes, three-terminal devices including bipolar transistors, field effect transistors and so on,
lasers and device technology in five different chapters. Analog Circuits (Section-III), covered in ten different
chapters, comprehensively covers analysis and applications of important electronic devices. The study material in this
section is spread out in ten chapters including small signal equivalent circuits of electronic devices, semiconductor diode
circuits, biasing and bias stability, amplifiers and their frequency response, operational amplifiers, filters, oscillators,
wave shaping circuits and power supplies. Digital Electronics (Section-IV) is the next section. It covers all impor-
tant topics of digital electronics including Boolean algebra, logic gates and logic families, combinational logic, sequen-
tial logic, D/A and A/D converters and memory devices and microprocessors. Topics covered in the section on Signals
and Systems (Section-V) that follows the section on digital electronics include Laplace transform, Fourier series,
Fourier transform, z-transform and linear time invariant (LTI) systems. Section-VI deals with Control Systems.
Different topics covered in this section include control system basics, block diagram and signal flow graphs, error con-
stants and sensitivity parameters, stability and stability analysis, control system compensators, root locus analysis,
frequency response analysis and state variable analysis of control systems. Communication Systems (Section-VII)
covers random signals and noise, analog communication systems, digital communication systems, information theory
and multiple access techniques. The final section on Electromagnetics (Section-VIII) covers elements of vector
calculus, Maxwells equations, plane waves, transmission lines, waveguides and antennas.
GATE is an All-India level competitive examination for engineering graduates aspiring to pursue Masters or Ph.D.
programs in India. The examination evaluates the examinees in General Aptitude, Engineering Mathematics and the
subject discipline. It is a competitive examination where close to ten lakh students appear every year. The level of
competition is therefore very fierce. While admission to a top institute for the Masters programme continues to be the
most important reason for working hard to secure a good score in the GATE examination; another great reason to
appear and handsomely qualify GATE examination is that many Public Sector Undertakings (PSUs) are and probably
in future almost all will be recruiting through GATE score. And it is quite likely that even big private sector companies
may start considering GATE seriously for their recruitment, as GATE score can give a bigger clue about who they
are recruiting. The examination today is highly competitive and the GATE score plays an important role. This only
reiterates the need to have a book that prepares examinees not only to qualify the GATE examination by getting a
score just above the threshold but also enabling them to achieve a competitive score.
The present book is written with the objective of fulfilling this requirement. The effort is intended to offer to the
large cross-section of GATE aspirants a self-study and do-it-yourself book providing comprehensive and step-by-step
treatment of each and every aspect of the examination in terms of concise but complete study material and an exhaus-
tive set of questions with solutions. The authors would eagerly look forward to the feedback from the readers through
publishers to help them make it better in subsequent editions.
Dr ANIL KUMAR MAINI
VARSHA AGRAWAL
NAKUL MAINI
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ABOUT THE AUTHORS
Dr Anil Kumar Maini is a senior scientist and former Director of Laser Science and Technology Centre, a premier
laser and optoelectronics research and development laboratory of Defence Research and Development Organisation
of Ministry of Defence. He has worked on a wide range of electronics, optoelectronics and laser systems and his areas
of expertise include optoelectronic sensor systems, laser systems, power electronics, digital electronics and related
technologies.
He has twelve books to his credit, which include, Lasers and Opto-electronics, Digital Electronics: Principles and
Applications, Satellite Technology: Principles and Applications, Microwaves and Radar, Handbook of Electronics,
Electronics and Communication Simplified, Electronics for Competitions, Electronic Devices and Circuits, Electronics
Projects for Beginners and Technical Interviews: Excel with Ease, to name a few. He has also authored about 150 tech-
nical articles and papers in national and international journals and conferences and has eight patents including a U.S.
patent (Granted: 2, Pending 6) to his credit. He is Life Fellow of Institution of Electronics and Telecommunication
Engineers (IETE) and Life Member of Indian Laser Association.
Varsha Agrawal is a scientist at the Laser Science and Technology Centre. She is with the Defence Research and
Development Organization (DRDO) under the Government of India since the past fifteen years and has been working
on the design and development of a variety of electronics sub-systems for a range of defence-related applications.
She has authored three books, which include, Satellite Technology: Principles and Applications, Satellite
Communications and Electronic Devices and Circuits. She has to her credit more than twenty five research papers and
technical articles.
Nakul Maini is currently pursuing Masters at University of Bristol, U.K. He has to his credit more than ten research
papers and technical articles.
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ACING THE GATE
ABOUT GATE EXAMINATION
The Graduate Aptitude Test in Engineering (GATE) is an All-India level competitive examination for engineering
graduates interested in pursuing Masters or Ph.D. programs in India. The examination tests the examinees in General
Aptitude, Engineering Mathematics and the discipline (subject) of study in the undergraduate course. The level of
competitiveness can be gauged from the fact that close to ten lakh students appear in this competitive examination
every year.
Admission to Higher Learning Courses
A valid GATE score is essential to become eligible for admission to the post- graduate course in engineering , that is,
M.Tech , M.E. or direct doctoral programme in the Indian higher education institutes. Although qualifying the GATE
examination entitles you to apply for the higher qualification; achieving qualifying score is definitely not enough if one
is aspiring for admission to top institutes like the IITs, the NITs, the Indian Institute of Science (IISc) and some of the
high ranked universities. For this, a high GATE score is important. Needless to say, a percentile of greater than 95 is
perhaps the least one needs to secure if one were eying for admission to a top institute. A total of 8.04 lakh students
competed in GATE during 2015 out of which about 1.72 lakh students belonged to ECE category. It is important to
mention here that only 15.05% of those who appeared could qualify according to the qualifying marks set by the GATE
examination committee.
Financial Assistance
Selected GATE qualified candidates admitted to M.Tech programmes in Colleges/Universities all over India are eli-
gible for obtaining financial assistance. The financial assistance is awarded to Indian nationals doing the M.Tech pro-
grammes, subject to Institute rules. It is also available the form of Half-Time Teaching Assistantship (HTTA) and is
tenable for a maximum period of 24 months. HTTA students are required to assist the department for 8 hours of work
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xii Acing The Gate
per week related to academic activities of the department such as laboratory demonstration, tutorials, evaluation of
assignments, test papers, seminars, research projects, etc.
Jobs in Public Sector Undertakings
While admission to a top institute for the Masters programme continues to be the most important reason for working
hard to secure a good score in the GATE examination; another great reason to appear and handsomely qualify GATE
examination is that many Public Sector Undertakings (PSUs) are and probably in future almost all will be recruiting
on the basis of GATE score. And it is quite likely that even big private sector companies may start considering GATE
seriously for their recruitment as GATE score can give a better idea about capabilities of candidate they are recruit-
ing. A large number of PSUs have already started recruiting on the basis of GATE score. These include companies
like, Power Grid, Delhi Development Authority (DDA), Indian Oil, Bharat Electronics (BE), Bharat Heavy Electricals
Limited (BHEL), National Thermal Power Corporation (NTPC), HPCL, DVC, NALCO, NLC, Central Electronics
Limited (CEL), BSPHCL, Vizag Steel and Gas Authority of India Limited (GAIL).
APPLYING FOR THE EXAMINATION
Eligibility
The candidates applying for GATE examination must meet the under mentioned requirements.
1. A candidate is allowed to appear only in one paper. The first step therefore is to select the paper you wish to
appear for.
2. The next step is to choose the city of choice for appearing in the examination. There are three choices to be
given in the order of preference. The candidate can choose a particular city as the first choice for appearing in
GATE examination. Having done that, the candidate would know the zone to which the chosen first preference
city belongs to. The candidate can then choose his/ her second choice only from the cities available in that zone.
As an additional option, a third choice was also introduced from GATE 2014. The list of third choice cities will
be as specified by each zone. Note that this third choice city may either be from the zone to which the first and
second choice cities belong or from some other zone. The third choice will be considered only when the candidate
cannot be accommodated either in first or second choice cities. The tentative zone-wise list of cities for GATE
every year is given in Examination Cities. However, the GATE Committee reserves the right to add a new city
or remove an existing city and allot a city that may not be any of the choices of a candidate.
3. Minimum qualification for appearing in GATE ECE examination of a given year is B.E/B.TECH (currently in
4th year or already completed), Integrated M.E/M.TECH Post B.Sc. (currently in 2nd, 3rd or 4th year or already
completed), Integrated M.E/M.TECH or Dual degree post 10 + 2 or Diploma (currently in 4th or 5th year or
already completed) and Professional Society Examinations equivalent to B.E/B.TECH (completed Section-A or
equivalent of such courses).
4. Candidates who are likely to complete the qualifying examination during the year of the GATE examination or
later have to submit a certificate from their college Principal. They have to obtain a signature from their princi-
pal along with the seal on the Certificate from the Principal format that will be printed on the application PDF
file which is generated after completion of the online application submission.
5. Candidates who have appeared in the final semester/year exam in the year immediately preceding the year of
GATE examination (for GATE-2016, it will be 2015), but with a backlog (arrears/failed subjects) in any of the
papers in their qualifying degree should (a) submit a copy of any one of the marks sheets of the final year, or (b)
have to obtain a signature from their Principal along with the seal on the Certificate from the Principal format
that will be printed on the application PDF file which will be generated after completion of the online application
submission.
Official Website
All announcements regarding GATE can be seen on the official website of the current organizing institute. There are
a large number of other websites that contain GATE relevant information.
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Acing The Gate xiii
STRUCTURE OF THE EXAMINATION
The GATE examination is conducted for 22 disciplines (papers) that are listed in GATE brochure and also available
on official GATE website. The syllabus for each of these is also given separately in detail. The candidate is expected to
select and appear in the appropriate paper as per the discipline of his qualifying degree. However, he is free to choose
any paper, depending on the plan for admission into higher degree and the eligibility requirements of the same.
Examination Pattern
GATE examination consists of a single paper of 3 hour-duration. There are a total of 65 questions for 100 marks belong-
ing to the following sections:
General aptitude: Comprises of 10 questions, out of which five questions are of 1 mark each and five for 2
marks each. These are designed to check the language and analytical skills of the aspirants.
Subject paper: Comprises of 25 questions of 1 mark each and 30 questions of 2 marks each with Engineering
Mathematics constituting 13% of the total marks. These are designed to check the subject knowledge of the aspirants.
The questions are a mix of multiple choice and numerical answer type:
Multiple choice questions (MCQs): These questions will have single option correct
Numerical answer questions (NAQs): These come with no choices and candidates are expected to answer using
a virtual keypad. The numerical answer will a real number, signed or unsigned, e.g. 25.06, 25.06, 25, 25, etc.
with due consideration being given for a range during the answer evaluation.
Marking Scheme
For 1 mark questions, 1/3 mark is deducted for a wrong answer. For a 2 mark question, 2/3 mark is deducted for a
wrong answer. There is no negative marking for numerical answer type questions.
Mode of Examination
The GATE examinations for the papers of all streams are held on-line. These include papers with codes AE, AG, AR,
BT, CE, CH, CY, GG, MA, MN, MT, PH, TF, XE, XL, CS, EC, EE, IN, ME and PI.
Majority of questions asked in GATE examination are designed to test the ability of the candidates to understand
the fundamental concepts behind important laws and theorems and their ability to correctly interpret and apply vari-
ous laws to solve problems. It is also important that the candidates are able to recall important mathematical expres-
sions with particular reference to those relevant to circuit analysis, electromagnetics and communication techniques.
Clarity in fundamental concepts also helps in identifying the only wrong or the only right statement out of the given
four statements. A good number of questions are designed in a manner in which the candidate is asked to pick the
right or wrong mathematical expression or statement. Understanding of interpretation of mathematical expressions is
equally important. Sometimes the questions are designed in such a way that the given statements represent a math-
ematical expression in words. Knowledge of basic analogue and digital circuits is also important. Candidates are often
asked to identify the correct Opamp circuit or correct digital circuit. In such cases, only basic circuits are included.
Writing Boolean expression of a given digital circuit or identifying the correct digital circuit for a given Boolean expres-
sion is another commonly asked GATE question.
UNDERSTANDING GATE RELATED INFORMATION
Pre-Examination
Pre-examination related information is covered in detail under different headings in the previous pages. Before starting
the application process, you must:
1. Ensure you areeligiblefor the relevant GATE examination.
2. Determine theGATE paperyou wish you appear for (You can appear in only one paper).
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xiv Acing The Gate
3. Choose at least two citiesthat are convenient for you to write the exam.
4. Application for appearing in GATE has to be made online only.
5. All supporting documents should be sent online only. No hard copy will be accepted.
6. Payments have to be made through debit/ATM cards, credit cards or internet banking and e-challan only.
7. Your choice of exam paper will determine date, and choice of available cities.
8. Speed and accuarcy can also be improved by taking mock test available online.
Post-Examination (Normalization of GATE score)
Examination for CE, CS, EC, EE and ME papers is generally held in multi-sessions. Hence, for these papers, a suit-
able normalization is applied to take into account any variation in the difficulty levels of the question papers across
different sessions. The normalization is done based on the fundamental assumption that in all multi-session GATE
papers, the distribution of abilities of candidates is the same across all the sessions. This assumption is justified since
the number of candidates who appeared in multi-session papers in GATE 2015 is large and the procedure of allocation
of session to candidates is random. Further it is also ensured that for the same multi-session paper, the number of
candidates allotted in each session is of the same order of magnitude. For the above mentioned papers; GATE score
will be computed based on the normalized marks and not the actual mark obtained in the examination. For all other
papers, actual marks obtained in the examination will be used for computation of GATE score.
ATTRIBUTES FOR SUCCESS IN GATE EXAMINATION
Preparing for a competitive examination such as the GATE examination is different from preparing for an academic
examination on many counts. One: In the case of latter, one needs to focus on one subject paper at a time; in the case
of GATE examination, one has to simultaneously study and grasp all important subjects that one would have studied
during the course of four year degree course. Two: In an academic examination, one is generally given a choice of ques-
tions where as in a competitive examination; one has to answer the entire question paper. Three: There is no negative
marking in academic examinations, which allows the examinees to do lot of guess work. Such a luxury is not there in
competitive examinations. Four: The time duration of a given academic examination is generally sufficient for all cat-
egories of students from weak to very bright students. Time management plays a key role in competitive examinations,
which also indirectly test the speed with which one is able to solve the questions. Of the two given students knowing
the solutions of all the questions of a certain competitive examination; one may score more than the other if the other
fails to attempt all questions due to his relatively slower speed.
Preparing for the Examination
Effective preparation means knowing the examination pattern, understanding fundamental concepts, having good
problem solving skills, remembering important formulae and lot of problem solving practice. It also means eating
healthy, sleeping well and taking short breaks at regular intervals.
Knowing Your Subject
Subject knowledge is the single most important thing that can see you through the GATE examination with a good
score. It is advisable to pay attention to the following points, particularly for GATE EC:
1. Each topic and sub-topic should be thoroughly studied and understood with particular emphasis on fundamental
concepts underlying those topics.
2. Special attention should be paid to schematics and circuit diagrams wherever applicable as a large number of
questions, particularly from electronic devices and circuits, digital electronics, control systems and networks, are
based on understanding of circuit and block schematics.
3. Important mathematical expressions should be remembered and their interpretation clearly understood. This is
particularly applicable to electromagnetics, signals and systems and communication.
4. Important terms and definitions of theorems and laws should be remembered. This is particularly relevant to
networks, electromagnetics and communication.
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Acing The Gate xv
Preparation of a Study Plan
A carefully drawn out study plan helps focusing on the subject matter and monitors the progress made during the
course of preparation. A structured study plan also allows you to make mid-course corrections, if required, before it
istoo late.
1. The first important task towards preparation for the GATE examination is to study the prescribed syllabus of the
examination in detail. The syllabus should be examined and analyzed in micro level detail in terms of the subjects
to be covered, topics to be addressed in each of those subjects and sub-topics to be included in each of the topics.
The prescribed syllabus gives this information. There is sometimes some ambiguity in the sub-topics mentioned
in the syllabus. In the past, questions have sometimes been asked from sub-topics not listed in the syllabus. It is
therefore recommended that the examinees analyze question papers of past five years at least while drawing up
the plan of the topics and sub-topics that they would need to cover.
2. The second obvious task would be to choose the resources in terms of the books, notes and any other study mate-
rial that you would like to use for preparation. Make sure that you choose the right books. You may consult an
expert or a friend or acquaintance who has cleared GATE earlier for the purpose. If you are currently in the final
year of your degree examination or have recently cleared your degree examination; the books that you studied
or referred to during your degree course should be given preference as you would have read those books earlier
and reading them second time for GATE preparation would make it easy for you. Try new books only on need
basis. In addition to the text books and notes, it is essential to always keep one comprehensive book that has been
designed specifically for the examination.
3. From the knowledge of the prescribed syllabus, prepare your own detailed syllabus after analyzing the pattern
of the previous years question papers. Highlight the topics that have been given more weightage in the previous
papers.
4. The topics important within each unit from GATE EC perspective are tabulated at the beginning of each
unit along with graphical representation of number of questions asked from these over the past seven GATE
examination.
5. Plan your study in such a manner as to complete the syllabus one month before the scheduled examination. Leave
last one month for revision.
6. One school of thought advocates devoting last one month to solving model test papers and also previous years
GATE papers in addition to the exercise of revision. We strongly recommend that questions asked in the previ-
ous GATE examinations should be addressed concurrently with the study of that subject lest you are surprised
to find towards the close that you are unable to solve those questions. Some model test papers may be attempted
in the last one month as a practice exercise for the purpose of time management.
7. You may devote on an average six to eight hours a day other than the time you spend in college if you are in
final year of your degree course or at the coaching institute if you have joined one. You may choose any time of
day/night that suits you the best or when you can concentrate the most, though studying in the early morning
hours is strongly recommended.
8. Speed and accuracy can also be improved by taking mock tests available online.
Refining Problem-Solving Skills
1. Problem-solving skill plays a key role in any competitive examination. It is directly related to the number of
questions you would be able to successfully solve in the allotted time.
2. It is important for the examinee to sharpen his/her problem-solving skills. Understanding of fundamental con-
cepts helps developing skills to quickly arrive at the solution or the shortest route to finding the solution.
3. It is recommended that all problems other than those having obvious solutions are practiced at least once by
the examinee by actually solving them on paper. This helps in improving problem-solving skills. This habit also
helps in developing the skill to quickly arrive at the most optimum route for solving any given problem. It is
advised to shun the habit of just going through the problems and solutions and considering them having been
done.
4. It is also pertinent to memorize all important formulae and definitions of all important concepts. A large number
of questions are directly based on mathematical formulae and fundamental concepts. It helps saving precious time
during the examination. Time saved can be utilized in solving relatively more difficult questions.
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xvi Acing The Gate
Taking the Examination
Effective Approach to Attempting Questions and Time Management
Importance of having an effective approach to attempting questions cannot be undermined. After subject knowledge,
effective time management is the next most important element of success in a competitive examination and GATE is
no exception. One school of thought recommends allotting equal time to all sections. Some experts recommend allot-
ting less time to sections that you are strong in so that you get more time for other sections where you are relatively
weak. The most optimal strategy would be divide the question paper on the basis of what questions you consider as
easily doable without much effort and what you consider as teasers. What is difficult and what is easy can vary from
examinee to examinee. It is not unlikely that a 2 mark question looks easy to you than a certain 1 mark question. The
highest speed is achieved by adopting the following pattern.
Attempt those questions first whose answers come to you instantly or with a little thought. These are usually the
theoretical and logical questions.
In the second attempt, try those questions that you do fully understand but need some time. These are generally
mathematical questions.
In the last attempt, look at the questions you are not very sure of but you do have an idea. Try to solve these
questions by process of elimination and your understanding.
Dont ever attempt questions you have no idea of.
Maximize your Exam-taking Efficiency
Maximizing exam taking efficiency should be the key objective of every examinee. How do we do that? Some important
points are outlined as follows:
1. Make sure that the night before the examination you sleep really well.
2. Be positive. Believe in yourself. You would get this confidence if you would have prepared well during the previ-
ous months. A thorough revision of all topics and taking a couple of online mock tests in the last one week would
tremendously boost your confidence level.
3. Aim realistically high. Stay calm and composed just before the examination.
4. Before you leave home for the examination centre; make sure that you have taken all required documents and
permitted accessories such as pen, pencil, scale, etc.
5. Never ever get panicky on seeing the question paper. It happens sometimes that first couple of questions that you
read, you think you dont know. Stay calm. Give yourself a pause and start looking at the paper again.
Authors
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SYLLABUS OF GATE ELECTRONICS AND COMMUNICATION
ENGINEERING
ENGINEERING MATHEMATICS
Linear Algebra: Matrix algebra, Systems of linear equations, Eigen values and eigen vectors.
Calculus: Mean value theorems, Theorems of integral calculus, Evaluation of definite and improper integrals, Partial
Derivatives, Maxima and minima, Multiple integrals, Fourier series. Vector identities, Directional derivatives, Line,
surface and volume integrals, Stokes, Gauss and Greens theorems.
Differential Equations: First order equation (linear and non-linear), Higher order linear differential equations with
constant coefficients, Method of variation of parameters, Cauchys and Eulers equations, Initial and boundary value
problems, Partial differential equations, Variable separable method.
Complex Variables: Analytic functions, Cauchys integral theorem and integral formula, Taylors and Laurent
series, Residue theorem, solution integrals.
Probability and Statistics: Sampling theorems, Conditional probability, Mean, median, mode and standard
deviation, Random variables, Discrete and continuous distributions, Poisson, Normal and Binomial distribution,
Correlation and regression analysis.
Numerical Methods: Solutions of non-linear algebraic equations, Single and multi-step methods for differential equations.
Transform Theory: Fourier transform, Laplace transform, z-transform.

Networks: Network graphs: matrices associated with graphs; incidence, fundamental cut set and fundamental cir-
cuit matrices. Solution methods: nodal and mesh analysis. Network theorems: superposition, Thevenin and Nortons
maximum power transfer, Wye-Delta transformation. Steady state sinusoidal analysis using phasors. Linear constant
coefficient differential equations; time domain analysis of simple RLC circuits, Solution of network equations using
Laplace transform: frequency domain analysis of RLC circuits. Two-port network parameters: driving point and trans-
fer functions. State equations for networks.
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xviii Syllabus of gate Electronics and Communication Engineering
Electronic Devices: Energy bands in silicon, intrinsic and extrinsic silicon. Carrier transport in silicon: diffu-
sion current, drift current, mobility, and resistivity. Generation and recombination of carriers. P-N junction diode,
Zener diode, tunnel diode, BJT, JFET, MOS capacitor, MOSFET, LED, P-I-N and avalanche photo diode, Basics of
LASERs. Device technology: integrated circuits fabrication process, oxidation, diffusion, ion implantation, photolithog-
raphy, N-tub, P-tub and twin-tub CMOS process.
Analog Circuits: Small signal equivalent circuits of diodes, BJTs, MOSFETs and analog CMOS. Simple diode
circuits, clipping, clamping, rectifier. Biasing and bias stability of transistor and FET amplifiers. Amplifiers: single-
and multi-stage, differential and operational, feedback, and power. Frequency response of amplifiers. Simple op-amp
circuits. Filters. Sinusoidal oscillators; criterion for oscillation; single-transistor and op-amp configurations. Function
generators and wave-shaping circuits, 555 Timers. Power supplies.
Digital Circuits: Boolean algebra, minimization of Boolean functions; logic gates; digital IC families (DTL, TTL,
ECL, MOS, CMOS). Combinatorial circuits: arithmetic circuits, code converters, multiplexers, decoders, PROMs and
PLAs. Sequential circuits: latches and flip-flops, counters and shift-registers. Sample and hold circuits, ADCs, DACs.
Semiconductor memories. Microprocessor(8085): architecture, programming, memory and I/O interfacing.
Signals and Systems: Definitions and properties of Laplace transform, continuous-time and discrete-time Fourier
series, continuous-time and discrete-time Fourier transform, DFT and FFT, z-transform. Sampling theorem. Linear
Time-Invariant (LTI) systems: definitions and properties; causality, stability, impulse response, convolution, poles and
zeros, parallel and cascade structure, frequency response, group delay, phase delay. Signal transmission through LTI
systems.
Control Systems: Basic control system components: block diagrammatic description, reduction of block diagrams.
Open loop and closed loop (feedback) systems and stability analysis of these systems. Signal flow graphs and their
use in determining transfer functions of systems; transient and steady state analysis of LTI control systems and fre-
quency response. Tools and techniques for LTI control system analysis: root loci, Routh-Hurwitz criterion, Bode and
Nyquist plots. Control system compensators: elements of lead and lag compensation, elements of Proportional-Integral-
Derivative (PID) control. State variable representation and solution of state equation of LTI control systems.
Communications: Random signals and noise: probability, random variables, probability density function, autocor-
relation, power spectral density. Analog communication systems: amplitude and angle modulation and demodulation
systems, spectral analysis of these operations, superheterodyne receivers; elements of hardware, realizations of analog
communication systems; signal-to-noise ratio (SNR) calculations for amplitude modulation (AM) and frequency modu-
lation (FM) for low noise conditions. Fundamentals of information theory and channel capacity theorem. Digital com-
munication systems: pulse code modulation (PCM), differential pulse code modulation (DPCM), digital modulation
schemes: amplitude, phase and frequency shift keying schemes (ASK, PSK, FSK), matched filter receivers, bandwidth
consideration and probability of error calculations for these schemes. Basics of TDMA, FDMA and CDMA and GSM.
Electromagnetics: Elements of vector calculus: divergence and curl; Gauss and Stokes theorems, Maxwells equa-
tions: differential and integral forms. Wave equation, Poynting vector. Plane waves: propagation through various
media; reflection and refraction; phase and group velocity; skin depth. Transmission lines: characteristic impedance;
impedance transformation; Smith chart; impedance matching; S parameters, pulse excitation. Waveguides: modes in
rectangular waveguides; boundary conditions; cut-off frequencies; dispersion relations. Basics of propagation in dielec-
tric waveguide and optical fibers. Basics of antennas: Dipole antennas; radiation pattern; antenna gain.
FM.indd 18 6/30/2015 1:23:53 PM

CONTENTS
Preface vii
About the Authors ix
Acing the Gate xi
PART I: NETWORKS 1
1 Network Graphs 3
1.1 Network Graphs - An Introduction 3
1.2 Incidence Matrix 4
1.3 Fundamental Cut-Set Matrix 5
1.3.1 Fundamental or f-Cut-Set Matrix 6
1.3.2 Circuit Matrix 6
1.4 f-Circuit or Tie-Set Matrix 6
1.5 Inter-Relationships Between Different Matrices 7
Important Formulas 7
Solved Examples 7
Practice Exercise 9
Answers to Practice Exercise 10
Solved GATE Previous Years Questions 11
2 Nodal and Mesh Analysis 13
2.1 Kirchhoffs Circuit Laws 13

2.1.1 Kirchhoffs Voltage Law 13
2.1.2 Kirchhoffs Current Law 13
2.2 Series, Parallel and Series-Parallel Networks 13
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xx CONTENTS
2.2.1 Resistors in Series 13

2.2.2 Resistors in Parallel 14
2.2.3 Capacitors in Series 14
2.2.4 Capacitors in Parallel 14
2.2.5 Inductors in Series 14
2.2.6 Inductors in Parallel 14
2.3 Source and Network Transformations 14
2.3.1 Source Transformation 14
2.3.2 Network Transformations 15
2.4 Mesh Analysis 15
2.5 Nodal Analysis 15
Solved Examples 17
Practice Exercise 21
3 Network Theorems 35
3.1 Superposition Theorem 35

3.2 Thevenins Theorem 35
3.3 Nortons Theorem 36
3.4 Maximum Power Transfer Theorem 36
3.5 Reciprocity Theorem 36
3.6 Millmans Theorem 37
3.7 Substitution, Compensation and Tellegens Theorems 37
3.7.1 Substitution Theorem 37
3.7.2 Compensation Theorem 37
3.7.3 Tellegens Theorem 37
3.8 Wye-Delta Transformations 38
3.8.1 Delta-to-Wye Transformation 38
3.8.2 Wye-to-Delta Transformation 38
Solved Examples 39
4 Steady-State Sinusoidal Analysis 63
4.1 Introduction 63
4.2 Sinosoidal Steady-State Response in Time Domain 64
4.2.1 Element Steady-State Sinusoidal Response 64
4.2.2 Series RC Steady-State Sinusoidal Response 64
4.2.3 Series RL Steady-State Sinusoidal Response 65
4.3 Phasors 65
4.4 Impedance and Admittance Parameters in Frequency Domain 65
Solved Examples 67
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CONTENTS xxi
5 RLC Circuits 83
5.1 Time Domain Analysis of RLC Circuits 83

5.1.1 First-Order RC and RL Circuits 83
5.1.2 Initially Charged Source-Free RC Circuit 83
5.1.3 Source-Free RL Circuit with Initial Current 84
5.1.4 Singularity Functions 85
5.1.5 Step Response of an RC Circuit 86
5.1.6 Step Response of an RL Circuit 86
5.1.7 Series RLC Circuit 87
5.2 Resonance in RLC Circuits 87
5.2.1 RLC Series Circuit: Series Resonance 87
5.2.2 RLC Parallel Circuit: Parallel Resonance 88
5.3 Laplace Transform Method for RLC Circuits 88
Solved Examples 90
6 Two-Port Networks 107
6.1 Introduction 107

6.2 Open-Circuit Impedance Parameters 107
6.2.1 Condition for Reciprocity and Symmetry 108
6.3 Short-Circuit Admittance Parameters 108
6.4 Transmission Parameters 109
6.5 Inverse Transmission Parameters 109
6.6 Hybrid Parameters 110
6.7 Inverse Hybrid Parameters 110
6.8 Interrelation Between Different Parameters 111
6.9 Interconnection of Two-Port Networks 112
6.9.1 Cascade Connection 112
6.9.2 Series Connection 112
6.9.3 Parallel Connection 112
Solved Examples 113
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xxii CONTENTS
7 State Equations for Networks 131
7.1 Network Functions 131

7.1.1 Necessary Conditions for Driving-Point Functions 132
7.1.2 Necessary Conditions for Transfer Functions 132
7.2 Analysis of a Network Using State Equations 132
7.2.1 State Equations in Normal Form 132
7.2.2 State Matrix Differential Equation 133
Solved Examples 133
PART II: ELECTRONIC DEVICES 145
8 Semiconductor Physics 147

8.1 Semiconductor Materials 147
8.1.1 Insulators 147
8.1.2 Conductors 148
8.1.3 Semiconductors 148
8.2 Semiconductor Types 149
8.2.1 Intrinsic Semiconductors 149
8.2.2 Extrinsic Semiconductors 152
8.3 Law of Mass Action 155
8.4 Hall Effect 156
8.5 Drift and Diffusion Carriers 156
Solved Examples 158
9 Semiconductor Diodes 169
9.1 PN Junction 169

9.1.1 Forward-Bias Condition 170
9.1.2 Reverse-Bias Condition 171
9.2 Ideal and Practical Diodes 171
9.2.1 Ideal Diode 171
9.2.2 Practical Diode 171
9.3 VoltAmpere (VI) Characteristics of a Diode 172
9.3.1 Temperature Dependence of the VI Characteristics 173
9.4 Diode Resistance 173
9.4.1 Static Resistance 174
9.4.2 Dynamic Resistance 174
9.4.3 Average AC Resistance 175
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CONTENTS xxiii
9.5 Diode Junction Capacitance 175

9.5.1 Transition Capacitance 175
9.5.2 Diffusion Capacitance 175
9.6 Diode Equivalent Circuits 176
9.7 Load Line Analysis of aDiode Circuit 177
9.7.1 DC Applied Voltage 177
9.7.2 AC Applied Voltage 177
9.8 Breakdown Diodes 178
9.8.1 Avalanche Diodes 179
9.8.2 Zener Diode 179
9.9 Varactor Diodes 180
9.10 Tunnel Diodes 181
9.11 Schottky Diodes 182
9.12 Point Contact Diodes and Power Diodes 182
9.12.1 Point Contact Diodes 182
9.12.2 Power Diodes 182
9.13 Light-Emitting Diodes 183
9.14 Photodiodes 183
9.14.1 Photodiode Application Circuits 184
Solved Examples 186
10 BJTs and FETs 201
10.1 Transistor Construction and Types 201

10.1.1 NPN Transistor 201
10.1.2 PNP Transistor 202
10.2 Transistor Operation 202
10.3 Transistor Configurations 204
10.3.1 Common Base Configuration 204
10.3.2 Common-Emitter Configuration 206
10.3.3 Common-Collector Configuration 208
10.4 EbersMoll Model of Transistors 210
10.5 Bipolar Junction Transistors Versus Field-Effect Transistors 211
10.6 Junction Field-Effect Transistors 211
10.6.1 Construction and Principle of Operation 211
10.6.2 Characteristic Curves 212
10.6.3 Effect of Temperature on JFET Parameters 214
10.7 Metal-Oxide Field-Effect Transistors 215
10.7.1 Depletion MOSFETs 215
10.7.2 Enhancement MOSFETs 217
10.8 FET Parameters and Specifications 219
10.8.1 Characteristic Parameters 219
10.8.2 Differences between JFETs and MOSFETs 220
10.8.3 Handling MOSFETs 220
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xxiv CONTENTS
10.9 Dual-Gate MOSFET 220

10.10 VMOS Devices 221
10.11 CMOS Devices 222
10.12 Insulated Gate Bipolar Transistors 223
Solved Examples 225
11 Laser Basics 241

11.1.1 Absorption and Emission Processes 241
11.2 Types of Laser System 242
11.2.1 Two-Level Laser System 242
11.2.2 Three-Level Laser System 242
11.2.3 Four-Level Laser System 243
11.3 Gain of Laser Medium 243
11.4 Laser Resonator 244
11.5 Longitudinal and Transverse Modes 244
11.6 Laser Characteristics 245
11.6.1 Monochromaticity 245
11.6.2 Coherence 246
11.6.3 Directionality 247
11.7 Types of Lasers 247
11.7.1 Solid-State Lasers 247
11.7.2 Gas Lasers 247
11.7.3 Semiconductor Lasers 248
Solved Examples 249
12 Device Technology 253
12.1 Integrated Circuits 253

12.2 Integrated Circuit Fabrication Process 254
12.2.1 Lithography 254
12.2.2 Etching 254
12.2.3 Deposition 254
12.2.4 Chemical Mechanical Planarization 255
12.2.5 Oxidation 255
12.2.6 Doping 255
12.2.7 Diffusion 256
12.3 CMOS Fabrication 256
12.3.1 N-Well CMOS Process 256
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CONTENTS xxv
12.3.2 P-Well CMOS Process 256

12.3.3 Twin-Tub Process 256
Solved Examples 257
PART III: ANALOG CIRCUITS 259
13 Small Signal Equivalent Circuits 261
13.1 Diodes 261

13.2 h-Parameter Model for BJTs 262
13.2.1 h-Parameter Model for the Common-Emitter BJT Configuration 262
13.2.2 h-Parameter Model for the Common-Collector BJT Configuration 263
13.2.3 h-Parameter Model for the Common-Base BJT Configuration 263
13.3 re Transistor Model 264
13.3.1 re Model for Common-Emitter BJT Configuration 264
13.3.2 re Model for Common-Base BJT Configuration 264
13.3.3 re Model for Common-Collector BJT Configuration 265
13.4 Equivalent Model of FETs 265
Solved Examples 266
14 Simple Diode Circuits 273
14.1 Connecting Diodes in Series 273

14.2 Connecting Diodes in Parallel 273
14.3 Clipping Circuits 274
14.4 Clamping Circuits 276
14.5 Rectifier Circuits 278
14.5.2 Types of Rectifiers 278
14.6 Voltage Multiplier Circuits 280
14.7 Voltage Regulator 280
Solved Examples 281
15 Biasing and Bias Stability 297
15.1 BJT Amplifiers 297

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xxvi CONTENTS
15.1.2 Common Base Configuration 300

15.1.3 Common Collector Configuration 300
15.2 Bias Stabilization in BJTs 301
15.2.1 Stability Factor 301
15.2.2 Stability Factor (SI ) 302
CO
15.2.3 Stability Factor (SVBE) 302
15.2.4 Stability Factor (Sb) 302
15.3 Bias Compensation 303
15.3.1 Diode Compensation for BaseEmitter Voltage (VBE) 303
15.3.2 Diode Compensation for Leakage Current (ICO) 303
15.3.3 Thermistor Compensation 303
15.3.4 Operating Point Considerations in Thermal Runaway 303
15.4 Transistor Switch 304
15.5 JFET Amplifiers 305
15.5.1 Common Source Configuration 305
15.5.2 Common Drain Configuration 306
15.5.3 Common Gate configuration 306
15.6 Depletion MOSFETS 307
15.7 Enhancement MOSFETS 308
15.7.1 Feedback Biasing Configuration 308
15.7.2 Voltage-Divider Biasing Configuration 308
Solved Examples 309
16 Amplifiers 327
16.1 Amplifiers An Introduction 327

16.2 Single-Stage Amplifiers 328
16.2.1 Analysis of a Transistor Amplifier Using Complete h-Parameter Model 328
16.3 Analysis of Transistor Configurations Using Simplified h-Parameter Model 329
16.3.2 Common-Collector or Emitter-Follower Configuration 330
16.3.3 Common-Base Configuration 331
16.4 Analysis of FET Amplifiers 331
16.4.1 Common-Source FET Amplifier 331
16.4.2 Common-Drain FET Amplifier 331
16.5 Multistage Amplifiers 332
16.5.1 BJT Cascade Amplifier 332
16.5.2 FET Cascade Amplifier 333
16.5.3 Darlington Amplifier 334
16.5.4 Cascode Amplifier 335
16.6 Differential Amplifiers 336
16.7 Operational Amplifiers 336
16.7.1 Ideal Opamp Versus Practical Opamp 337
16.7.2 Performance Parameters 337
16.7.3 Types of Opamps 340
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CONTENTS xxvii
16.8 Feedback in Amplifiers 341

16.8.1 Advantages of Negative Feedback 341
16.8.2 Feedback Topologies 342
16.9 Power Amplifiers 345
16.9.1 Classification 346
16.9.2 Power Amplifier Characteristics 351
16.9.3 Thermal Management of Power Transistors 351
Solved Examples 353
17 Frequency Response of Amplifiers 375
17.1 Low-Frequency Response of BJT Amplifiers 375

17.1.1 Effect of Input-Coupling Capacitor 376
17.1.2 Effect of the Output-Coupling Capacitor 376
17.1.3 Effect of Bypass Capacitor 376
17.2 Low-Frequency Response FET Amplifiers 377
17.2.1 Effect of Input-Coupling Capacitor 377
17.2.2 Effect of Output-Coupling Capacitor 377
17.2.3 Effect of Source Capacitor 377
17.3 High-Frequency Response of BJT Amplifiers 378
17.3.1 High-Frequency Model for the Common-Emitter Transistor Amplifier 378
17.3.2 High-Frequency Response of Common-Collector Transistor Amplifier 382
17.4 High-Frequency Response of a FET Amplifier 384
17.4.1 Common-Source Amplifier at High Frequencies 384
17.4.2 Common-Drain Amplifier at High Frequencies 385
17.5 Amplifier Rise Time and Sag 385
17.5.1 Rise Time 385
17.5.2 Tilt or Sag 386
17.6 Frequency Response of Cascaded Amplifier Stages 386
17.6.1 Low-Frequency Response of Cascaded Amplifier Stages 387
17.6.2 High-Frequency Response of Cascaded Amplifier Stages 387
Solved Examples 389
18 Simple Opamp Circuits 403
18.1 Inverting Amplifier 403

18.2 Non-Inverting Amplifier 404
18.3 Voltage Follower 405
18.4 Summing Amplifier 405
18.5 Difference Amplifier (Subtractor) 406
18.6 Averager 406
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xxviii CONTENTS
18.7 Integrator 406

18.8 Differentiator 407
18.9 Rectifier Circuits 408
18.10 Clipper Circuits 409
18.11 Clamper Circuits 409
18.12 Peak Detector Circuit 410
18.13 Absolute Value Circuit 411
18.14 Comparator 411
18.14.1 Opamp Comparator 412
18.14.2 Comparator with Hysteresis 413
18.14.3 Window Comparator 414
18.15 Phase Shifters 415
18.16 Instrumentation Amplifier 416
18.17 Non-Linear Amplifier 417
18.18 Relaxation Oscillator 417
18.19 Current-to-Voltage Converter 418
18.20 Voltage-to-Current Converter 418
18.21 Active Filters 419
18.21.1 First-Order Filters 419
18.21.2 Second-Order Filters 420
18.21.3 Sine Wave Oscillators 421
Solved Examples 422
19 Filters 447
19.1 Passive Low-Pass Filters 447

19.1.1 Basic RC Low-Pass Filter 447
19.1.2 RC Low-Pass filter Circuit as an Integrator 448
19.2 Passive High-Pass Filters 449
19.2.1 Basic RC High-Pass Filter 449
19.2.2 RC High-Pass Filter as Differentiator 449
Solved Examples 450
20 Sinusoidal Oscillators 453
20.1 Conditions for Oscillations Barkhausen Criterion 453

20.2 RC Oscillators 454
20.2.1 RC Phase-Shift Oscillator 454
20.2.2 Bubba Oscillator 456
20.2.3 Twin-T Oscillator 456
20.2.4 Wien bridge Oscillator 456
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CONTENTS xxix
20.3 LC Oscillators 457

20.3.1 Armstrong Oscillator 457
20.3.2 Hartley Oscillator 458
20.3.3 Colpitt Oscillator 458
20.3.4 Clapp Oscillator 459
20.4 Crystal Oscillator 459
Solved Examples 462
21 Function Generators and Wave-Shaping Circuits 469
21.1 Multivibrators 469

21.1.1 Bistable Multivibrator 469
21.1.2 Schmitt Trigger 470
21.1.3 Monostable Multivibrator 470
21.1.4 Astable Multivibrator 472
21.2 555 Timer 473
21.2.1 Astable Multivibrator Using Timer IC 555 473
21.2.2 Monostable Multivibrator Using Timer IC 555 474
Solved Examples 476
22 Power Supplies 485
22.1 Constituents of a Linear Power Supply 485

22.2 Filters 486
22.2.1 Inductor Filter 486
22.2.2 Capacitor Filter 487
22.2.3 LC Filter 487
22.2.4 CLC Filter (p-Filter) 488
22.3 Linear Regulators 488
22.3.1 Emitter-Follower Regulator 489
22.3.2 Series-Pass Regulator 489
22.3.3 Current Limiting in Series-Pass Linear Regulators 490
22.3.4 Shunt Regulator 490
22.4 Linear IC Voltage Regulators 491
22.4.1 General Purpose Precision Linear Voltage Regulator 491
22.4.2 Three-Terminal Regulators 491
22.4.3 Boosting Current Delivery Capability 492
22.5 Switched Mode Power Supplies 493
22.5.1 Different Types of Switched Mode Power Supplies 493
22.5.2 Flyback Converters 493
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xxx CONTENTS
22.5.3 Forward Converter 494

22.5.4 PushPull Converter 495
22.6 Switching Regulators 495
22.6.1 Buck Regulator 496
22.6.2 Boost Regulator 496
22.6.3 Inverting Regulator 497
22.7 Linear Versus Switched Mode Power Supplies 497
22.8 Regulated Power Supply Parameters 497
22.8.1 Load Regulation 497
22.8.2 Line Regulation 498
22.8.3 Output Impedance 498
22.8.4 Ripple Rejection Factor 498
Solved Examples 499
PART IV: DIGITAL ELECTRONICS 511
23 Boolean algebra 513
23.1 Number Systems 513

23.1.1 Decimal Number System 513
23.1.2 Binary Number System 513
23.1.3 Octal Number System 514
23.1.4 Hexadecimal Number System 514
23.2 Representation of Binary Numbers 514
23.2.1 Sign-Bit Magnitude 514
23.2.2 1s Complement 514
23.2.3 2s Complement 514
23.3 Number Conversions 515
23.3.1 Finding Decimal Equivalent 515
23.3.2 Decimal-to-Binary Conversion 515
23.3.3 Decimal-to-Octal Conversion 516
23.3.4 Decimal-to-Hexadecimal Conversion 516
23.3.5 Octal-to-Binary and Binary-to-Octal Conversion 516
23.3.6 Hexadecimal-to-Binary and Binary-to-Hexadecimal Conversion 516
23.3.7 Hexadecimal-to-Octal and Octal-to-Hexadecimal Conversion 517
23.4 Floating Point Numbers 517
23.5 BCD Numbers 517
23.6 Gray Code Numbers 518
23.7 Boolean Algebra An Introduction 519
23.7.1 Variables, Literals and Terms in Boolean Expressions 519
23.7.2 Equivalent and Complement of Boolean Expressions 519
23.7.3 Dual of a Boolean Expression 519
23.8 Postulates and Theorems of Boolean Algebra 520
23.8.1 Postulates 520
23.8.2 Theorems of Boolean Algebra 520
23.9 Simplification of Boolean Functions 524
23.9.1 Sum-of-Products and Product-of-Sums Boolean Expressions 525
23.9.2 Expanded Forms of Boolean Expressions 525
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CONTENTS xxxi
23.9.3 Canonical Form of Boolean Expressions 525

23.9.4 S and P Nomenclature 526
23.9.5 QuineMcCluskey Tabular Method 526
23.9.6 Karnaugh Map Method 529
Solved Examples 532
24 Logic Gates and Logic Families 541
24.1 Positive and Negative Logic 541

24.2 Truth Table 541
24.3 Logic Gates 541
24.3.1 OR Gate 542
24.3.2 AND Gate 542
24.3.3 NOT Gate 543
24.3.4 Exclusive-OR Gate 543
24.3.5 NAND Gate 543
24.3.6 NOR Gate 544
24.3.7 Exclusive-NOR Gate 544
24.3.8 INHIBIT Gate 544
24.3.9 Universal Gates 545
24.3.10 Gate with Open Collector/Drain Outputs 545
24.3.11 Tristate Logic Gate 545
24.3.12 AND-OR-INVERT Gates 546
24.3.13 Schmitt Gates 546
24.3.14 Fan-out of Logic Gates 547
24.4 Buffers and Transceivers 548
24.5 Logic Families 549
24.5.1 Types of Logic Families 549
24.6 TransistorTransistor logic 552
24.6.1 Standard TTL 552
24.6.2 Low-Power TTL 553
24.6.3 High-Power TTL 553
24.6.4 Schottky TTL (74S/54S) 553
24.6.5 Low-Power Schottky TTL 553
24.6.6 Advanced Low-Power Schottky and Advanced Schottky TTL 554
24.7 Emitter-Coupled Logic 554
24.7.1 Logic Gate Implementation in ECL 555
24.7.2 Salient Features of ECL 556
24.8 CMOS Logic Family 556
24.8.1 Circuit Implementation of Logic Functions 556
24.8.2 CMOS with Open Drain Outputs 558
24.8.3 CMOS with Tristate Outputs 559
24.8.4 Floating or Unused Inputs 559
24.8.5 CMOS Subfamilies 559
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xxxii CONTENTS
24.8.6 BiCMOS Logic 560

24.8.7 NMOS and PMOS Logic 560
24.9 Comparison of Different Logic Families 561
Solved Examples 562
25 Combinational Circuits 571
25.1 Arithmetic Circuits 571

25.1.1 Half-Adder 571
25.1.2 Full-Adder 572
25.1.3 Half-Subtractor 572
25.1.4 Full-Subtractor 573
25.1.5 Controlled Inverter 574
25.1.6 AdderSubtractor 574
25.1.7 BCD Adder 575
25.1.8 Magnitude Comparator 577
25.2 Multiplexers 578
25.2.1 Implementing Boolean Functions with Multiplexers 578
25.2.2 Multiplexers for Parallel-to-Serial Data Conversion 580
25.2.3 Cascading Multiplexer Circuits 580
25.2.4 Encoders 581
25.2.5 Priority Encoder 581
25.3 Demultiplexers and Decoders 582
25.3.1 Implementing Boolean Functions with Decoders 582
25.3.2 Cascading Decoder Circuits 583
25.4 Programmable Logic Devices 583
25.4.1 Fixed Logic Versus Programmable Logic 584
25.4.2 Programmable ROMs 585
25.4.3 Programmable Logic Array 586
25.4.4 Programmable Array Logic 588
Solved Examples 590
26 Sequential Circuits 601
26.1 Multivibrator 601

26.1.1 Bistable Multivibrator 601
26.1.2 Schmitt Trigger 602
26.1.3 Monostable Multivibrator 602
26.1.4 Astable Multivibrator 603
26.1.5 IC Timer Based Multivibrators 603
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CONTENTS xxxiii
26.2 R-S (Reset and Set) FlipFlop 606

26.2.1 R-S FlipFlops with Active LOW and Active HIGH Inputs 607
26.2.2 Clocked R-S FlipFlop 609
26.3 Level-Triggered and Edge-Triggered FlipFlops 609
26.4 J-K FlipFlop 610
26.4.1 J-K FlipFlop with Preset and Clear Inputs 611
26.4.2 MasterSlave FlipFlop 612
26.5 Toggle FlipFlop (T- FlipFlop) 612
26.5.1 J-K FlipFlop as Toggle FlipFlop 614
26.6 D-FlipFlop 615
26.6.1 J-K FlipFlop as D-FlipFlop 615
26.6.2 D-Type Latch 616
26.7 Synchronous and Asynchronous Inputs 616
26.8 Counters 617
26.8.1 Asynchronous (Ripple) Counter 617
26.8.2 Synchronous Counter 617
26.8.3 Modulus of a Counter 618
26.8.4 Binary Ripple Counter Operational Basics 618
26.8.5 Binary Ripple Counters with Modulus Less than 2N 619
26.8.6 Synchronous or Parallel Counters 620
26.8.7 UP/DOWN Counters 620
26.8.8 Decade and BCD Counters 621
26.8.9 Presettable Counters 621
26.8.10 Decoding a Counter 621
26.8.11 Cascading Counters 621
26.9 Shift Register 622
26.9.1 Serial-In Serial-Out (SISO) Shift Register 622
26.9.2 Serial-In Parallel-Out Shift (SIPO) Register 624
26.9.3 Parallel-In Serial-Out (PISO) Shift Register 624
26.9.4 Parallel-In Parallel-Out (PIPO) Shift Register 624
26.9.5 Bidirectional Shift Register 624
26.9.6 Universal Shift Register 625
26.10 Shift Register Counters 627
26.10.1 Ring Counter 627
26.10.2 Shift Counter 627
Solved Examples 629
27 D/A and A/D Converters 643
27.1 D/A Converters 643

27.1.1 Simple Resistive Divider Network for D/A Conversion 643
27.1.2 Binary Ladder Network for D/A Conversion 644
27.2 D/A Convertor Specifications 645
27.2.1 Resolution 645
FM.indd 33 6/30/2015 1:23:55 PM

xxxiv CONTENTS
27.2.2 Accuracy 645

27.2.3 Conversion Speed or Settling Time 645
27.2.4 Dynamic Range 645
27.2.5 Non-linearity and Differential Non-linearity 645
27.2.6 Monotonocity 646
27.3 Types of D/A Converters 646
27.3.1 Multiplying-type D/A Converters 646
27.3.2 Bipolar Output D/A Converters 647
27.3.3 Companding D/A Converters 647
27.4 Modes of Operation 647
27.4.1 Current Steering Mode of Operation 647
27.4.2 Voltage Switching Mode of Operation 648
27.5 BCD Input D/A Converter 648
27.6 A/D Converters 649
27.6.1 A/D Converter Specifications 649
27.8 Types of A/D Converters 651
27.8.1 Simultaneous or Flash A/D Converter 651
27.8.2 Half-Flash A/D Converter 652
27.8.3 Counter-Type A/D Converter 653
27.8.4 Tracking-Type A/D Converter 653
27.8.5 Successive Approximation Type A/D Converter 653
27.8.6 Single-Scope, Dual-Scope and Multi-Slope A/D Converters 654
27.8.7 SigmaDelta A/D Converter 656
Solved Examples 657
28 Microprocessors and Memory Devices 663
28.1 Introduction to Microprocessors 663

28.2 Microprocessor Architecture 665
28.2.1 Arithmetic Logic Unit (ALU) 665
28.2.2 Register File 665
28.2.3 Control Unit 666
28.3 Basic Microprocessor Instructions 667
28.3.1 Data Transfer Instructions 667
28.3.2 Arithmetic Instructions 667
28.3.3 Logic Instructions 667
28.3.4 Control Transfer Instructions 668
28.3.5 Machine Control Instructions 669
28.4 Addressing Modes 669
28.4.1 Absolute or Memory Direct Addressing Mode 669
28.4.2 Immediate Addressing Mode 669
28.4.3 Register Direct Addressing Mode 669
28.4.4 Register Indirect Addressing Mode 669
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CONTENTS xxxv
28.4.5 Indexed Addressing Mode 670

28.4.6 Implicit Addressing Mode and Relative Addressing Mode 670
28.5 Programming Microprocessors 670
28.6 Risc Versus Cisc Processors 670
28.7 8085 Microprocessor 671
28.7.1 8085 Registers 673
28.7.2 Addressing Modes 674
28.7.3 8085 Instructions 674
28.8 Memory Devices 674
28.9 Primary Memory 674
28.10 Random Access Memory (RAM) 675
28.10.1 Static RAM (SRAM) 675
28.10.2 Dynamic RAM (DRAM) 680
28.10.3 RAM Applications 682
28.11 Read Only Memory (ROM) 683
28.11.1 ROM Architecture 683
28.11.2 Types of ROM 685
28.11.3 Applications of ROMs 688
28.12 Expanding Memory Capacity 689
28.12.1 Word Size Expansion 689
28.12.2 Memory Locations Expansion 690
28.13 Peripheral Devices 691
28.13.1 Programmable Timer/Counter 691
28.13.2 Programmable Peripheral Interface (PPI) 691
28.13.3 Programmable Interrupt Controller (PIC) 691
28.13.4 DMA Controller 691
28.13.5 Programmable Communication Interface 691
28.13.6 Math Co-Processor 691
28.13.7 Programmable Keyboard/Display Interface 692
28.13.8 Programmable CRT Controller 692
28.13.9 Floppy Disk Controller 692
28.13.10 Clock Generator 692
28.13.11 Octal Bus Transceiver 692
Solved Examples 692
PART V: SIGNALS AND SYSTEMS 703
29 Laplace Transform 705

29.1.1 Properties for ROC of Laplace Transforms 706
29.2 Properties of Laplace Transform 706
29.3 Analysis and Characterization of LTI Systems Using Laplace Transform 708
29.3.1 Causality 708
29.3.2 Stability 709
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xxxvi CONTENTS
29.3.3 System Functions for Interconnections of LTI Systems 709

29.4 Inverse Laplace Transform 709
Solved Examples 710
30 Continuous-Time and Discrete-Time Fourier Series 719
30.1 Fourier Series Representation of Continuous-Time Periodic Signals 719

30.1.1 Convergence of Fourier Series 720
30.1.2 Properties of Continuous-Time Fourier Series 720
30.2 Fourier Series Representation of Discrete-Time Periodic Signals 721
30.2.1 Properties of Fourier Series of Discrete-Time Periodic Signals 722
Solved Examples 724
31 Continuous-Time and Discrete-Time Fourier Transform 729
31.1 Continuous-Time Fourier Transform 729

31.1.1 Convergence of Fourier Transform 730
31.2 Properties of Continuous-Time Fourier Transform 730
31.3 Frequency Response of Continuous-Time LTI Systems 731
31.3.1 LTI Systems Characterized in Differential Equations 733
31.4 Discrete-Time Fourier Transform 733
31.5 Properties of Discrete-Time Fourier Transform 734
31.6 Frequency Response of Discrete-Time LTI Systems 736
31.6.1 LTI Systems Characterized in Difference Equations 736
31.7 Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) 737
Solved Examples 739
32 z-Transform 753
32.1 z-Transform and Inverse z-Transform 753

32.1.1 Properties for ROC of z-Transforms 753
32.2 Properties of z-Transform 754
32.3 LTI Systems and z-Transform 755
32.3.1 LTI Systems Characterized by Difference Equations 755
32.3.2 Interconnections of LTI Systems 756
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CONTENTS xxxvii
32.4 Unilateral z-Transform 756

Solved Examples 756
33 Sampling Theorem 769
33.1 Sampling Theorem 769

33.2 Sampling with Zero-Order Hold 769
33.3 Aliasing Problem 770
Solved Examples 771
34 Linear Time-Invariant (LTI) Systems 777

34.1.1 Signals and Their Classification 777
34.1.2 Basic Continuous-Time and Discrete-Time Signals 778
34.1.3 Continuous and Discrete-Time Systems 781
34.1.4 Basic System Properties 781
34.2 LTI Systems 782
34.2.1 Discrete-Time LTI Systems 782
34.2.2 Continuous-Time LTI Systems 782
34.3 Properties of LTI Systems 783
34.4 Frequency Response of Continuous-Time LTI Systems 784
34.4.1 First-Order Continuous-Time LTI Systems 785
34.4.2 Second-Order Continuous-Time LTI Systems 785
34.4.3 Continuous-Time LTI Systems Characterized by Nth Order Differential Equations 786
34.5 Frequency Response of Discrete-Time LTI Systems 786
34.5.1 First-Order Discrete-Time LTI Systems 786
34.5.2 Second-Order Discrete Time LTI Systems 787
34.5.3 Discrete-Time LTI Systems Characterized by Nth Order Differential Equations 787
34.5.4 Group and Phase Delays 787
34.6 Filtering 787
34.6.1 Frequency-Shaping Filters 788
34.6.2 Frequency-Selective Filters 788
34.6.3 Continuous-Time Filters 789
34.6.4 Discrete-Time Filters 789
Solved Examples 792
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xxxviii CONTENTS
PART VI: CONTROL SYSTEMS 807
35 Control System Basics 809
35.1 Control System 809

35.1.1 Open Loop and Closed Loop Control Systems 809
35.1.2 Linear and Non-Linear Control Systems 810
35.1.3 Continuous Time and Discrete Time Control Systems 810
35.1.4 Time Varying and Time Invariant Control Systems 810
35.1.5 Causal Systems 811
35.1.6 Free and Forced Response 811
35.1.7 Steady-State, Transient and Total Response 811
35.1.8 Unit Step, Ramp and Impulse Response 811
35.2 Second-Order Control System 812
35.2.1 Unit Step Response 812
35.3 Transfer Function 813
35.4 Stability 813
35.4.1 Relative Stability 813
35.5 Routh Stability Criterion 814
35.6 Hurwitz Stability Criterion 814
35.7 Continued Fraction Stability Criterion 815
Solved Examples 816
36 Block Diagrams and Signal Flow Graphs 829
36.1 Feedback Control System 829

36.2 Block Diagram Reduction 830
36.2.1 Rules of Block Diagram Reduction 830
36.2.2 Canonical Form to Unity Feedback Form 833
36.3 Signal Flow Graphs 833
36.3.1 Signal Flow Graph Terminologies 834
36.3.2 Transfer Function from Signal Flow Graph 834
36.4 Mathematical Models of Physical Systems 835
Solved Examples 836
37 System Classification, Error Constants andSensitivity Parameters 847
37.1 Classification of Feedback Control Systems 847

37.2 Error Constants 848
37.3 Error Constants for General Systems 849
37.4 Sensitivity Parameters 849
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CONTENTS xxxix

Solved Examples 850
38 Control System Controllers and Compensators 859
38.1 Industrial Controllers 859

38.2 PID Controller 860
38.2.1 Proportional Element 860
38.2.2 Integral Element 861
38.2.3 Derivative Element 861
38.3 Control System Compensators 861
38.3.1 Lead Compensator 861
38.3.2 Lag Compensator 862
38.3.3 LagLead Compensator 862
Solved Examples 863
39 Root Locus Analysis 873
39.1 Root Locus 873

39.2 Angle and Magnitude Criteria 874
39.3 Construction of Root Locus 874
39.4 Gain Margin and Phase Margin 875
39.5 Determination of Damping Ratio 875
39.6 Closed-Loop Transfer Function 875
Solved Examples 876
40 Frequency Response Analysis: Nyquist Analysis andBode Plots 885
40.1 Polar Plots 885

40.2 Nyquist Analysis 886
40.3 Nyquist Stability Plot 886
40.4 Nyquist Stability Criterion 887
40.5 Gain Margin and Phase Margin 887
40.6 Gain Factor Compensation 888
40.7 Bode Analysis 888
40.7.1 Gain Margin and Phase Margin 890
Solved Examples 891
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xl CONTENTS

41 State Variable Analysis 905
41.1 State Variable Analysis 905

42.2 State Variables and State Vector 905
41.3 State Equation Representation of LTI Systems 906
41.4 State Transition Matrix 907
41.4.1 Properties of State Transition Matrix 907
41.5 Solution of Linear Time-Invariant State Equation 907
41.6 Controllability of Linear Systems 908
41.7 Observability of Linear Systems 908
41.8 Eigen Values 909
Solved Examples 910
Practice Examples 912
PART VII: COMMUNICATION SYSTEMS 921
42 Random Signals and Noise 923
42.1 Random Variables 923

42.1.1 Discrete Random Variable 923
42.1.2 Continuous Random Variable 924
42.1.3 Gaussian Random Variable 924
42.1.4 Joint Distribution 924
42.1.5 Conditional Densities 925
42.1.6 Independent Random Variables 925
42.1.7 Statistical Averages (Means) 925
42.1.8 Moments 926
42.2 Autocorrelation 926
42.3 Power Spectral Density 926
42.3.1 Power of a Random Process 927
42.4 Noise 927
42.4.1 White Noise 927
42.4.2 Gaussian Noise 928
42.4.3 Thermal Noise 928
42.4.4 Flicker Noise 928
42.4.5 Shot Noise 928
Solved Examples 931
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CONTENTS xli
43 Analog Communication Systems 953

43.2 Amplitude Modulation 953
43.2.1 Frequency Spectrum of AM Signal 954
43.2.2 Power in AM Signal 954
43.2.3 Noise in AM Signal 955
43.2.4 Different Forms of Amplitude Modulation 955
43.3 Superheterodyne Receiver 959
43.4 Frequency Modulation 960
43.4.1 Frequency Spectrum of FM Signal 961
43.4.2 Narrow-Band and Wide-Band FM 962
43.4.3 Noise in FM Signal 962
43.4.4 Generation of FM Signals 965
43.4.5 Detection of FM Signals 966
43.5 Phase Modulation 969
43.5.1 Relation between FM and PM 969
43.6 Analog Pulse Communication Systems 970
43.6.1 Pulse Amplitude Modulation (PAM) 970
43.6.2 Pulse Width Modulation (PWM) 970
43.6.3 Pulse Position Modulation (PPM) 970
Solved Examples 971
44 Fundamentals of Information Theory 993
44.1 Measure of Information 993

44.1.1 Entropy of a Source 993
44.2 Source Encoding 994
44.3 Error-Free Communication Over a Noisy Channel 994
44.4 Channel Capacity of a Discrete Memoryless Channel 994
44.5 Channel Capacity of a Continuous Memoryless Channel 995
44.5.1 Entropy of a Band-Limited White Gaussian Noise 995
44.5.2 Mutual Information I(x;y) 995
44.6 ShannonHartley Theorem 996
Solved Examples 997
45 Digital Communication Systems 1001
45.1 Sampling Theorem 1001

45.2 Digital Pulse Communication Systems Techniques 1001
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xlii CONTENTS
45.2.1 Pulse Code Modulation 1002

45.2.2 Differential PCM 1003
45.2.3 Delta Modulation 1004
45.2.4 Adaptive Delta Modulation 1004
45.3 Digital Modulation Techniques 1004
45.3.1 Amplitude Shift Keying 1004
45.3.2 Frequency Shift Keying 1005
45.3.3 Phase Shift Keying 1005
45.3.4 Differential Phase Shift Keying 1006
45.3.5 Quadrature Phase Shift Keying 1006
45.3.6 Offset QPSK 1007
Solved Examples 1008
46 Multiplexing and Multiple Access Techniques 1033
46.1 Multiplexing Techniques 1033

46.1.1 Frequency-Division Multiplexing 1033
46.1.2 Time-Division Multiplexing 1034
46.2 Multiple Access Techniques 1034
46.2.1 Frequency-Division Multiple Access 1034
46.2.2 Time-Division Multiple Access 1035
46.2.3 Code-Division Multiple Access 1036
46.2.4 Space Domain Multiple Access 1036
PART VIII: ELECTROMAGNETICS 1041
47 Elements of Vector Calculus 1043
47.1 Vector and Scalar 1043

47.1.1 Coordinate Systems 1044
47.2 Dot Product and Cross Product 1044
47.3 Vector Differentiation 1045
47.4 Del Operator - Gradient - Divergence - Curl 1046
47.5 Vector Integration 1047
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CONTENTS xliii
48 Maxwells Equations 1051
48.1 Faradays Law 1051

48.2 Biot-Savart Law 1052
48.3 Amperes Law 1052
48.4 Displacement Current 1052
48.5 Maxwells Equations 1053
48.5.1 Maxwells First Equation 1053
48.5.2 Maxwells Second Equation 1053
48.5.3 Maxwells Third Equation 1053
48.5.4 Maxwells Fourth Equation 1053

48.6 Boundary Conditions

1054
48.6.1 Boundary Conditions for E and D 1054

48.6.2 Boundary Conditions for H and B 1054
48.7 Poissons and Laplaces Equations 1055
49 Plane Waves 1067
49.1 Wave Equations 1067

49.2 Solutions to Wave Equations 1068
49.2.1 Plane Wave Propagation in Partially Conducting Media 1068
49.2.2 Plane Wave Propagation in Perfect Dielectrics 1068
49.2.3 Plane Wave Propagation in Good Conductors 1069
49.3 Propagation Through Interface Between Two Media 1069
49.3.1 Normal Incidence 1069
49.3.2 Oblique Incidence 1070
49.4 Polarization 1070
49.5 Formation of Standing Waves 1071
49.6 Poyntings Theorem 1071
50 Transmission Lines 1085
50.1 Transmission Line Equivalent Circuit 1085

50.2 Transmission Line Losses 1086
50.3 Transmission Line Propagation Modes 1086
50.4 Transmission Line Parameters 1087
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xliv CONTENTS
50.4.1 Characteristic Impedance 1087

50.4.2 Propagation Constant 1087
50.4.3 Reflection Coefficient 1087
50.4.4 Standing Wave Ratio 1088
50.4.5 Input Impedance 1088
50.4.6 Return Loss 1089
50.4.7 Mismatch Loss 1089
50.5 Types of Transmission Lines 1089
50.6 Impedance Matching Using Transmission Lines 1090
50.6.1 Single Stub Matching 1090
50.6.2 Double Stub Matching 1091
50.6.3 Quarter-Wave Transformer 1091
50.7 Smith Chart 1091
50.8 Scattering Parameters (S-Parameters) 1092
51 Waveguides 1107
51.1 Waveguide 1107

51.2 Waveguide Modes 1108
51.2.1 Dominant Modes 1108
51.2.2 TEM Mode 1109
51.3 Waveguide Parameters 1109
51.3.1 Cut-off Wavelength 1109
51.3.2 Guide Wavelength 1109
51.3.3 Group Velocity and Phase Velocity 1110
51.3.4 Characteristic Wave Impedance 1110
51.4 Rectangular Waveguides 1111
51.4.1 Transverse Electric Wave Propagation 1111
51.4.2 Transverse Magnetic Wave Propagation 1111
51.5 Power Loss in Rectangular Waveguides 1112
51.6 Circular Waveguides 1113
51.6.1 Transverse Electric Wave Propagation 1113
51.6.2 Transverse Magnetic Wave Propagation 1113
51.7 Power Loss in Circular Waveguides 1113
51.8 Propagation in Optical Fibres 1114
51.8.1 Numerical Aperture 1114
51.8.2 Dispersion 1114
51.8.3 Types of Fibres 1115
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CONTENTS xlv
52 Basics of Antennas 1125
52.1 Antenna Basics 1125

52.1.1 Antenna Reciprocity 1125
52.1.2 Radiation Mechanism 1126
52.2 Antenna Parameters andCharacteristics 1126
52.2.1 Directive Gain 1127
52.2.2 Power Gain 1127
52.2.3 Directional Pattern 1127
52.2.4 Beam Width 1129
52.2.5 Bandwidth 1129
52.2.6 Polarization 1129
52.2.7 Antenna Impedance 1131
52.2.8 Antenna Aperture 1131
52.3 Resonant and Non-Resonant Antennas 1131
52.4 Electrical and Physical Length 1132
52.5 Types of Antennas 1132
52.5.1 Hertz, Dipole and Marconi Antennas 1132
52.5.2 Yagi-Uda Antenna 1133
52.5.3 V-Antenna and Rhombic Antenna 1133
52.5.4 Reflector Antennas 1134
Solved GATE Papers 2014 1143

Solved GATE Papers 2015 1201
Index 1249
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FM.indd 46 6/30/2015 1:23:57 PM
PART I: NETWORKS
MARKS DISTRIBUTION FOR GATE QUESTIONS
6
Number of Questions
5
Marks 1
4
Marks 2
3 Total number of questions
0
2015 2014 2013 2012 2011 2010 2009
01-Chapter-01-Gate-ECE.indd 1 6/2/2015 10:55:52 AM

2 part i: NETWORKS
Topic Distribution for GATE Questions
Year Topic
2015 Lumped circuit model and loss tangent
Solution methods: Nodal and mesh analysis
Two-port network parameters
Norton's theorem
Electrostatic potential
Time domain analysis of simple RLC circuits
Steady state sinusoidal analysis using phasors
Frequency domain analysis of RLC circuits
Magnetic field
Thevenin's maximum power transfer
Equivalent resistance
Graphs
2014 Thevenin and Norton's maximum power transfer
Wye-Delta transformation
Solution methods: Nodal and mesh analysis
Frequency domain analysis of RLC circuits
Transfer functions of networks
Steady state sinusoidal analysis using phasors
Complex power
Two-port network parameters
RMS of a signal
Equivalent resistance
Magnetic coupling
2013 Solution methods: Nodal and mesh analysis
Maximum power transfer
Thevenin's theorem
Wye-Delta transformation
Two-port network parameters: Driving point and transfer functions
Nortons theorem

CHAPTER 1
NETWORK GRAPHS
This chapter discusses about the concept of network graphs, the matrices associated with the graphs, namely, the
incidence, fundamental cut-set and fundamental circuit matrices.
1.1 NETWORK GRAPHS - AN continuous path through all the branches (any of which
may be traversed more than once) which touches all the
INTRODUCTION nodes. If a graph has n number of nodes, then its rank
is (n - 1).
A linear graph of a network comprises of a collection A subgraph is a subset of the branches and nodes of
of nodes or vertices (points) and branches (line seg- a graph. A subgraph is said to be proper if it consists
ments), with the different nodes connected together by of strictly less than all the branches and nodes of the
branches. It is drawn by representing the voltage and graph. A path is a particular subgraph having the prop-
current sources by their internal impedances (note that erties that at its two terminal nodes, one branch of the
the internal impedance of an ideal voltage source is zero, subgraph is incident and at the other nodes referred to
hence it is denoted as a short circuit and that of an ideal as the internal nodes, two branches are incident. Also,
current source is infinite, hence it is denoted as an open there should be no other proper subgraph having the
circuit) and keeping all the nodes and branches of the same terminal nodes with above mentioned properties.
network. Figure 1.1(a) shows a network and Fig. 1.1(b) A tree is a set of branches with each node connected
shows its corresponding network graph. to every other node, directly or indirectly such that the
A graph whose branches carry an arrow to indicate removal of any single branch destroys this property.
their orientation are referred to as directed graphs or In other words, a tree of the graph is a subset of the
oriented graphs, else they are referred to as undirected branches such that all graph nodes are connected by
graphs. A connected graph is one in which there is a branches but without forming a closed path. A tree has

4 Chapter 1: Network Graphs
Tree Twigs of Links of

(3) Tree Cotree
2
1 3 (2) {2, 5, 6 {1, 3, 4
(2) (4) (6)
(1) (5) (5)
(6)
+
V
4 (2) (4) {2, 4, 5 {1, 3, 6

(a)
(3) (3) (5)
2 2
1 3 1 3
(2) (4) (2) (4) (4) {1, 4, 6 {2, 3, 5
(5) (6) (5) (6)
(1) (1) (6)
(1)
4 4 Figure 1.2| Trees, cotrees and twigs of network graph

(b) in Fig. 1.1.
Figure 1.1| (a) Network of a circuit. (b) Network

graph of the circuit in (a). complete incidence matrix corresponds to the node of
the graph and has non-zero entries in all those columns
(n - 1) branches, where n is the number of nodes of the of the braches which are associated with that node and
graph. The branches of the tree are referred to as twigs zero entries in all other columns. The sum of the entries
and those branches which are not the part of the tree in any column of the complete incidence matrix is zero
are referred to as links or chords. All the links combined and its determinant for a closed loop is zero. The entries
together form a cotree and it represents the complement highlighted in grey are the elements of the incidence
of the tree. Figure 1.2 shows the possible trees, its twigs matrix Aa, which is shown as follows:
and corresponding cotree for the graph shown in Fig. 1.1.
-1 1 1 0 0 0
If the graph is not-connected, then a set of trees, one 0 -1 0 -1 1 0
Aa=
-
for each separate part is referred to as a forest. The
0 0 1 1 0 1
0 -1 -1
complement of a forest is a coforest.
1 0 0
1.2 INCIDENCE MATRIX

Table 1.1| Complete incidence matrix.
For a graph with n nodes and b branches, the complete Branches

incidence matrix Aa is a rectangular matrix of the order Nodes 1 2 3 4 5 6
n b, with number of rows equal to the number of nodes
in the graph and number of columns equal to the number 1 -1 1 1 0 0 0
of branches of the graph and has a rank of (n - 1). The 2 0 -1 0 -1 1 0
element amk of the matrix is given as follows: 3 0 0 -1 1 0 1
amk = 0, if branch k is not associated with node m. 4 1 0 0 0 -1 -1
= 1 , if branch k is associated with node m and
oriented away from node m.
Two different graphs having the same number of nodes
= -
1, if branch k is associated with node m and and branches and one-to-one correspondence between
oriented towards node m. their nodes as well as their branches have the same com-
The complete incidence matrix for the network graph plete incidence matrix. Such graphs are referred to as
shown in Fig. 1.1 is listed in Table 1.1. Each row in the isomorphic graphs.

1.3 FUNDAMENTAL CUT-SET MATRIX 5
It may be noted here that all the rows are not indepen- (1)
dent and at least one row can be obtained by the alge-
braic manipulation of other rows. The matrix obtained
from the complete incidence matrix by eliminating one (5) (3) (2)
of the rows is referred to as the incidence matrix or the
reduced incidence matrix (denoted by A). For the inci- (4)
dence matrix given in Table 1.1, the reduced incidence
(a)
matrix formed by eliminating the last row is
-1 1 1 0 0 0
A = 0 -1 0 -1 1 0
(5) (3) (2)
0 0 1 1 0 1
The number of trees of a graph are given by
(b)
T = det{[A][A]T (1.1)
where [A] and [A]T are the reduced incidence matrix and
its transpose, respectively.
(5) (3)
1.3 FUNDAMENTAL CUT-SET

MATRIX (c)
Figure 1.3| Cut-sets of a network graph.
A cut-set is the minimum set of branches of a connected coincide with the cut-set orientation. Figure 1.4 shows a
graph, that the removal of these branches cuts the graphs network graph.
into two parts. In other words, cut-set is the minimum
set of branches such that the removal of these branches
reduces the rank of the graph by one. (2)
As an example, let us consider a network graph shown
in Fig. 1.3(a). As we can see from the figure, the rank of 2
the graph is 3. The removal of braches 1 and 4 breaks 1 3
(1) (6)
the graph into two connected subgraphs as shown in Fig.
1.3(b). Therefore, [1, 4] may be a cut-set. Also, remov-
ing the branches 1, 2 and 4 reduces the graph into two (4) 3
(3)
connected subgraphs as shown in Fig. 1.3(c). Therefore (5)
[1, 2, 4] may be a cut-set. Since, [1, 4] is a subset of [1, 2, (7)
4], therefore [1, 4] is a proper cut-set and not [1, 2, 4] as
it contains the minimum set of edges.
4
Each branch of a cut-set has one of its terminals
incident at a node in one group and its other end at a Figure 1.4| Network graph.
node in the other group. The cut-set matrix has its rows
corresponding to the cut-sets and the columns are the The cut-sets of the graph are [1, 2, 4], [1, 2, 3, 6, 7],
branches of the graph and is given by Qa = [qij], where [5, 6], [3, 4, 5, 7], [3, 4, 6, 7] and so on. The cut-set matrix
qij = 1 , if branch j is in the cut-set i and the orientations can be written as
1 -1
coincide. 0 1 0 0 0
=-
1, if branch j is in the cut-set i and the orienta- -1 1 -1 0 0 -1 -1

tions do not coincide. Qa = 0 0 0 0 -1 1 0
= 0, if the branch j is not in the cut-set i. 0 0 1 -1 1 0 1
0 0 1 -1 0 1 1
It may be mentioned here that a cut-set is oriented by
selecting an orientation from one of the two parts to the Those graphs whose complete incidence matrix are
other. The orientations of a branch in a cut-set as per contained within the cut-set matrix are referred to as
the orientation of the network graph may or may not non-separable.

1.3.1 Fundamental or f-Cut-Set Matrix The f-cut-set matrix Q is

1 -1 0 1 0 0 0
Q = 0 0 1 -1 0
For a network graph, select a tree and focus on the twig
0 0
bk of the tree that disconnects the tree into two pieces.
All the links which go from one part of this disconnected 0 0 1 -1 0 1 1
tree to the other along with the twig bk will constitute
The rows correspond to the f-cut-sets 1, 5 and 7 and the
a cut-set. This is referred to as fundamental cut-set or
columns correspond to the branches 1, 2, 3, 4, 5, 6 and
f-cut-set. Therefore, for each branch of the tree, there will
7. The branch voltage matrix [Vb] is expressed in terms
be an f-cut-set. The direction of an f-cut-set is chosen to
of node voltage matrix [Vn] as follows:
be that of the twig defining the cut-set. For a network
graph with n nodes, there are (n - 1) twigs in a tree and
[Vb] = [Q]T[Vn] (1.2)
therefore there are (n - 1) number of f-cut-sets. The fun-
damental or the f-cut-set matrix is defined as a matrix [Vb] = [A]T[Vn] (1.3)
whose each row represents a f-cut-set with respect to
a given tree of the graph. The rank of the matrix Q is where [Vb] is the branch voltage matrix which is a column
(n - 1). The f-cut-set Q = [qij] has one row for each f-cut- matrix of order (b 1), [Vn] is the node voltage matrix
set of the graph and one column for each edge, where which is a column matrix of order [(n - 1) 1], [Q] is
the f-cut-set matrix of the order [(n - 1) b] and [A] is
qij = 1 , if edge j is in f-cut-set i and the direction of edge the reduced incidence matrix of the order [(n - 1) b].
j coincides with that of the f-cut-set i.
= -
1, if edge j is in f-cut-set i and the direction of 1.3.2 Circuit Matrix
edge j does not coincide with that of the f-cut-set i.
The circuit matrix (represented by Ba) of a graph, with
= 0, if edge j is not in f-cut-set i. n nodes and b branches is a rectangular matrix with b
columns and as many rows as there are loops. The rank
For the network graph shown in Fig. 1.4, consider a of the circuit matrix is [b - (n - 1)]. The element of mth
tree shown in Fig. 1.5(a). The f-cut-sets are shown in row and kth column is given as follows:
Fig. 1.5(b).
bmk = 0, if branch k is not in loop m.
= +
1, if branch k is in loop m and their orienta-
tions coincide.
(1) = -
1, if branch k is in loop m and their orienta-
tions do not coincide.
(7)
(5) 1.4 f-CIRCUIT OR TIE-SET MATRIX
(a) Tie-set is a set of branches contained in a loop such that

each loop contains one link and the remainder are tree
branches. An f-tie-set is referred to as a group of branches
(2) contacting only one link and minimum number of twigs.
The number of fundamental tie-sets of a graph is equal to
2 the number of links or the number of Kirchhoffs voltage
1 3
(1) (6) law mesh equations. It may be mentioned here that the
Kirchhoffs voltage law equations can be obtained from
(4) (3) the rows of an f-tie-set matrix and the branch currents
(7) (5) can be obtained from the columns of the f-tie-set matrix.
The fundamental tie-set matrix is formed by using the
following procedure:
4 1. Draw the directed graph of a network and choose
a tree.
(b) 2. Each link forms an independent loop. The direction
Figure 1.5| (a) Tree of a graph in Fig. 1.4. (b) f-cut- of the loop is the same as that of the correspond-
sets of the graph in Fig. 1.5(a). ing link.
01-Chapter-01-Gate-ECE.indd 6 6/6/2015 5:26:27 PM

SOLVED EXAMPLES 7
3. Elements bij of the tie-set matrix are given by where At is a square matrix of twigs of order (n - 1)
bij = 1 , when the branch bj is in loop i and is directed (n - 1) and rank (n - 1). Here, Al is the matrix of links
in the same direction as the loop current. of the order of (n - 1) (b - n + 1).
= -
1, when the branch bj is in loop i and is
B = [Bt : Bl] = [Bt : U] (1.6)
directed in the opposite direction as the loop
current.
where Bt is a matrix of twigs of order (b - n + 1) (n -
= 0, when the branch bj is not in loop i. 1), Bl is the matrix of links of the order of (b - n + 1)
The tie-set matrix is an (b - n + 1) b matrix. (b - n + 1) and is an identity matrix
The relation between the branch current matrix [Ib]
Q = [Qt : Ql] = [U : Ql] (1.7)
and the loop current matrix [IL] is given by
where Qt is an identity matrix of twigs of order
[Ib] = [B]T[IL] (1.4)
(n - 1) (n - 1) and Ql is the matrix of links of order of
(n - 1) (b - n + 1).
1.5 INTER-RELATIONSHIPS The inter-relationships between different matrices are
BETWEEN DIFFERENT MATRICES as follows:
Bt = [At-1Al]T (1.8)
If A is the incidence matrix, B is the fundamental circuit
matrix and Q is the fundamental cut-set matrix, then Ql = At-1Al (1.9)
A = [At : Al] (1.5) BQT = QBT = 0 (1.10)
IMPORTANT FORMULAS
1. The number of trees of a graph are 4. Bt = [At-1Al]T

T = det{[A][A]T 5. Ql = At-1Al
2. [Vb] = [Q]T[Vn] and [Vb] = [A]T[Vn] 6. BQT = QBT = 0
3. [IL] is [Ib] = [B]T[IL]
SOLVED EXAMPLES
Multiple Choice Questions
1. Identify which of the following is NOT a tree of the Solution. The tree does not contain any loop. The
graph shown in the following figure. following figure shows that the connect adhg has a
loop. Therefore, it is not a tree.
a
a
2
1 3 1 3
b c
d e f g
h d g
4 5
4 5
(a) begh (b) defg h
(c) adhg (d) aegh Ans. (c)

2. For the network shown in the following figure, the 2

incidence matrix is given by
2 a b
g
+ f e

1 3
5
5 h
1 3 c
d
4
4
The incidence matrix Aa is comprised of elements
aij such that
+1 0 0 -1 0 -1 0 0
-1 +1 0 0 0 0 -1 0 aij = +1, when the current in branch j leaves node i.
(a) A = 0 -1 +1 0 -1 0 0 0
= -
1, when the current in branch j enters node i.
0 0 -1 +1 0 0 0 -1 = 0, when branch j is not connected to node i.
0 0 0 0 +1 +1 +1 +1
Therefore, the incidence matrix is given by
-1 0 0 +1 0 -1 0 0
+1 +1 0 0 0 0 +1 0 Branch Numbers

(b) A = 0 -1 +1 0 -1 0 0 0 Nodes a b c d e f g h
0 0 -1 -1 0 0 0 -1
0 0 0 0 +1 +1 -1 +1
1 +1 0 0 -1 0 -1 0 0
2 -1 +1 0 0 0 0 -1 0
+1 0 0 -1 0 -1 0 0 3 0 -1 +1 0 -1 0 0 0
-1 +1 0 -1 0
0 0 0 4 0 0 -1 +1 0 0 0 -1
(c) A = 0 -1 +1 0 -1 0 0 0
0 0 -1 + 1 0 0 0 +1 5 0 0 0 0 +1 +1 +1 +1
0 0 0 0 +1 +1 +1 -1
The incidence matrix can also be represented as
-1 0 0 +1 0 +1 0 0 follows:
+1 +1 0 0 0 0 +1 0

(d) A = 0 -1 +1 0 -1 0 0 0 +1 0 0 -1 0 -1 0 0
0 0 -1 -1 0 0 0 -1 -1 +1 0 0 0 0 -1 0
0 0 0 0 +1 -1 -1 +1
A = 0 -1 +1 0 -1 0 0 0

0 0 -1 +1 0 0 0 -1
Solution. The network shown in the given figure 0 0 0 0 +1 +1 +1 +1
has five nodes and eight branches. The graph for
the network is shown in the following figure. Ans. (a)
Numerical Answer Question
1. A network has seven nodes and five independent Solution. We know that
loops. What is the number of branches in the
network? e = b - (n - 1)

PRACTICE EXERCISE 9
where b is the number of branches, n is number of b = e + (n - 1) = 5 + (7 - 1) = 5 + 6 = 11

nodes and e is the number of independent loops.
Therefore, Ans. (11)
PRACTICE EXERCISE
1. Relative to a given fixed tree of a network, 3. Refer to the network shown in the following figure.
The tie-set matrix is
(a) link currents form an independent set.
(b) branch currents form an independent set.
(a) [1 1] (b) [4 4]
(c) link voltages form an independent set.
(d) branch voltages form an independent. (c) [10 2.5] (d) [10 4]
(1 Mark) (1 Mark)
2. For the incidence matrix given below, the corre-
sponding network graph is
4 4
1 0 0 0 1 0 0 1 +
0 1 0 0 -1 1 0 0 Vx I2
A=
0 -1 1 -1 4
+ Vx
0 0 1 0 10 V

0 0 0 1 0 0 -1 0 I1 4
9
b 9 4. Refer to the network shown in Question 3. The
b2 1 2 loop currents are
1
1 5 e6 2 1 2
5 5
a 6 c 10 5 6 7 (a) 5A and 6A (b) A and A
5 e 7 10 5 6 7 6 6
a c
8 7
4 8 3 8 (c) 5A and 5A (d) 6A and 6A
4 d 3 4 8 3
4 3 (2 Marks)
d
(a) (b)
(a) (b) 5. Which of the following statements is/are true?
8
3 8 S1: Branch voltage matrix [Vb] is related to
3 5 b 6 c 7 node voltage matrix [Vn] as [Vb] = [Q]T[Vn] and [Vb]
7 8 a d
7 8 a 5 b 6 c 7
d = [A]T [Vn]
2 6 4 12 3
2 1 12 3 4 S2: The relation between the branch current
6 54
4 matrix [Ib] and the loop current matrix [IL] is [Ib]
5 0
1 = [B]T[IL]
0
(c) (d) (a) S1 only (b) S2 only
(c) (d) (c) None (d) Both
(2 Marks) (1 Mark)

Numerical Answer Questions
1. For the network shown in the following figure, find 2. For the given reduced incidence matrix, how many
the maximum number of possible trees. (Assume branches are there for the corresponding network?
that all active sources to be ideal.) (1 Mark)
(2 Marks)
b -1 0 0 +1 0 +1 0 0
+1 +1 0 0 0 0 +1 0

2 A = 0 -1 + 1 0 -1 0 0 0
1
0 0 -1 -1 0 0 0 -1
e
5
i 0 0 0 0 +1 -1 -1 +1
+
a 0 c
7 8
3. For the reduced incidence matrix given in Question
6 2, how many nodes are there for the corresponding
4 3 network?
(1 Mark)
d
ANSWERS TO PRACTICE EXERCISE
1. (a) The link currents form an independent set. Therefore, the tie-set matrix B is given by
2. (d) The given matrix is a reduced incidence matrix. B = [1 1]
The matrix can be rewritten as
4. (b) Using the equation BZBBTIL = BEB -BZBIB.
1 2 3 4 5 6 7 8 Therefore,
a 1 0 0 0 1 0 0 1
b 0 1 0 0 -1 1 0 0 4 0 1
BZB B T = [1 1]
A=
1 -1
=8
c 0 0 1 0 0 -1 0 4 1
d 0 0 0 1 0 0 -1 0 and
10 4 0 0
The branches 1, 2, 3 and 4 are connected to the B(EB - ZB IB ) = [1 1] -
reference node. The branch 5 is connecting nodes a 0 0 4 V x /4
and b, the branch 6 is connecting nodes b and c, the = 10 - Vx
branch 7 is connecting nodes c and d and the branch
8 is connecting nodes a and c. So the graph shown Therefore,
in option (d) is the corresponding graph with +1 8I1 = 10 - Vx
for an arrow leaving the node and -1 for an arrow
entering a node. However, Vx = 4I1. Therefore,
3. (a) In the given circuit, the 4 resistor in series 5
with the current source is shorted. The network I1 = A
6
graph is shown in the following figure.
Since I2 = Vx/4, we get
5
1 2 I2 = A
6
5. (d)

SOLVED GATE PREVIOUS YEARS QUESTIONS 11
1. Considering the ideal current source as open-circuit 1 -1 0

and the ideal voltage source as short circuit, the 0 1 -1
oriented network graph can be drawn as shown in 0 1
AT =
0
-1
the following figure. Node d is taken as the refer-
1 0
ence node. 1 -1 0
-1 0
0
b
and
1 -1 0
1 2 0 - 1
1 0 0 -1 1 -1
1
1
det AAT = -1 0
5 0 0
1 -1
-1
1 0
0
a,0 c 1 0
6 0 -1 1 0 0
1 -1 0
-1 0
4 3 0
= 12
d Therefore, the possible number of trees is 12.
Ans. (12)
The incidence matrix is given by
2. For the reduced incidence matrix having c col-
umns, the network has c branches. Therefore, the
1 0 0 -1 1 -1 number of branches is 8.
A = -1 1 -1 0

1 0 Ans. (8)
0 -1 1 0 0 0
3. For a reduced incidence matrix with r rows, the
number of nodes are (r + 1). Therefore, the number
The transpose of the matrix A is given by of nodes for the given matrix is 6.
Ans. (6)
SOLVED GATE PREVIOUS YEARS QUESTIONS
1. Consider the network graph shown in the follow- Solution. It is forming a closed loop. So it cannot
ing figure. be a tree.
Ans. (b)
2. In the graph shown in the following figure, the

number of trees (P) and the number of cut-sets (Q)
are
1
Which one of the following is NOT a `tree of this
graph?
2 3
(a) (b)
4
(a) P = 2, Q = 2 (b) P = 2, Q = 6
(c) P = 4, Q = 6 (d) P = 4, Q = 10
(c) (d)
(GATE 2008: 1 Mark)
(GATE 2004: 1 Mark)

Solution. The different trees (P) are shown in the 1 5 2

following figure:
3 6 4
Therefore, the number of cut-sets is 6.

Ans. (c)
Therefore, the number of trees is 4. The different

cut-sets (Q) are shown in the following figure:

CHAPTER 2
NODAL AND MESH ANALYSIS
This chapter discusses the topics Kirchhoffs voltage law, Kirchhoffs current law, series networks, parallel networks and
series-parallel networks, source transformation, network transformations, and mesh and nodal analysis of networks.
2.1 KIRCHHOFFS CIRCUIT LAWS into that node is equal to the sum of currents flowing out
of that node or the algebraic sum of currents in a net-
work of conductors meeting at a point is zero. In other
Kirchhoffs circuit laws govern the conservation of words, the sum of currents entering the junction is thus
charge and energy in electrical circuits. There are two equal to the sum of currents leaving the junction. This
Kirchhoffs circuit laws, namely, the Kirchhoffs voltage implies that the current is conserved (no loss of current).
law and the Kirchhoffs current law.
2.2 SERIES, PARALLEL AND

2.1.1 Kirchhoffs Voltage Law
SERIES-PARALLEL NETWORKS
According to Kirchhoffs voltage law, the algebraic sum
of all branch voltages around any closed loop of a net-
work is zero at all instants of time. In other words, the
directed sum of electrical potential differences around 2.2.1 Resistors in Series
any closed circuit is zero.
Figure 2.1 shows n resistors R1, R2, ..., Rn in series.
2.1.2 Kirchhoffs Current Law

R1 R2 R3 R4 Rn Req

Kirchhoffs current law states that at any node (junc-
tion) in an electrical circuit, the sum of currents flowing Figure 2.1| Resistors in series.

14 Chapter 2: Nodal and Mesh Analysis
The equivalent resistance Req is given by 2.2.5 Inductors in Series

Req = R1 + R2 + + Rn (2.1)
Figure 2.5 shows n inductors L1, L2, ..., Ln in series.
2.2.2 Resistors in Parallel The equivalent inductance Leq is given by
Figure 2.2 shows n resistors R1, R2, ..., Rn Leq = L1 + L2 + + Ln (2.5)

in parallel.

L1 L2 L3 L4 Ln Leq
Figure 2.5| Inductors in series.
R1 R2 R3 R4 Rn Req
2.2.6 Inductors in Parallel
Figure 2.2| Resistors in parallel. Figure 2.6 shows n inductors L1, L2, ..., Ln in parallel.
The equivalent inductance Leq is given by
The equivalent resistance Req is given by
1 1 1 1
= + + + (2.6)
1 1 1 1 Leq L1 L2 Ln
= + + + (2.2)
Req R1 R2 Rn
2.2.3 Capacitors in Series

L1 L2 L3 L4 Ln Leq
Figure 2.3 shows n capacitors C1, C2, ..., Cn in series.
C1 C2 C3 C4 Cn Ceq

Figure 2.6| Inductors in parallel.
Figure 2.3| Capacitors in series.
The equivalent capacitance Ceq is given by 2.3 SOURCE AND NETWORK

1 1 1 1 TRANSFORMATIONS
= + + + (2.3)
Ceq C1 C2 Cn
2.3.1 Source Transformation
2.2.4 Capacitors in Parallel
A voltage source V in series with its internal resistance R
Figure 2.4 shows n capacitors C1, C2, ..., Cn in parallel. can be converted into an equivalent current source I placed
in parallel with resistance R, where the value of I is given
by I = (V/R) [Fig. 2.7(a)]. Also, a current source I in par-
allel with resistance R can be replaced by a voltage source
V in series with resistance R, where V = IR [Fig. 2.7(b)].
C1 C2 C3 C4 Cn Ceq
R R
I I
+ + V
Figure 2.4| Capacitors in parallel.
R R
V
The equivalent capacitance Ceq is given by

(a) (b)
Ceq = C1 + C2 + + Cn (2.4) Figure 2.7| Source transformation.

2.5 NODAL ANALYSIS 15
2.3.2 Network Transformations present. For a network comprising of m number of

meshes, the mesh equations using Kirchhoffs voltage
2.3.2.1T to o-Transformations law can be generalized as
Z11 Z12 Z13 Z1m I1 V1
Figure 2.8(a) shows a T-network and Fig. 2.8(b) shows a Z Z22 Z23 Z2m I2 V2
p-network. The impedances ZA, ZB and ZC of a p-network 21 = or [Z ][I ] = [V ]

are expressed in terms of the impedances of T-network
Zm1 Zm2 Zm3 Zmm I m Vm
Z1, Z2 and Z3 as given below.
where matrix Z is a square matrix called the impedance
Z Z + Z2Z3 + Z3Z1
ZA = 1 2 (2.7) matrix having Zij as elements where i = 1, 2, 3, ..., m and
Z2 j = 1, 2, 3, ..., m, V is a column matrix of input voltages
Z1Z2 + Z2Z3 + Z3Z1 Vi, where i = 1, 2, 3, ..., m and I is a column matrix of
ZB = (2.8) mesh currents Ii where i = 1, 2, 3, ..., m. In the imped-
Z3
ance matrix, Zii is the self-impedance of the ith mesh and
Z1Z2 + Z2Z3 + Z3Z1 Zij is the mutual impedance between the ith and the jth
ZC = (2.9)
Z1 meshes. The order of the impedance matrix is equal to
the number of meshes.
The procedure for writing the mesh equations for net-
1 2 works comprising of voltage sources in matrix form is as
Z1 Z2 follows. In the case when the current sources are present,
convert the current source to voltage source by source
Z3
transformation and then follow the following procedure:
1 2 1.All the impedances through which the loop current
Ij flows in the jth loop are summed up and denoted
(a) by Zjj. In other words, the coefficient of Ij is Zjj with
positive sign. Zjj is called self-impedance of the loop j.
1 2 2. All the impedances through which loop currents
ZB
Ij in the jth loop and Ik in the kth loop flow are
summed up. This is denoted by Zjk. Here, Zjk is
ZA ZC positive if the currents Ij and Ik through Zjk are in
1 2 the same direction and is negative if the currents Ij
and Ik through Zjk are in opposite directions.
(b) 3. Let Vj be the effective voltage in the jth loop
Figure 2.8| (a) T-network. (b) p network. through which the current Ij flows. The sign of Vj
is positive if the direction of Vj is the same as that
of Ij and is negative when the direction of Vj is
The impedances Z1, Z2 and Z3 of a T-network are opposite to that of Ij.
expressed in terms of the impedances of p-network ZA, Note that to avoid chances of error, the directions of
ZB and ZC as follows: loop currents should be taken in the same direction,
either clockwise or anticlockwise direction. For networks
ZA ZB
Z1 = (2.10) having only passive elements and only independent
ZA + ZB + ZC sources, the impedance matrix is symmetric Zij = Zji.
ZB ZC For a network comprising of b branches, n nodes and s
Z2 = (2.11) separate parts, the number of linearly independent mesh
equations are m = (b - n + s). The matrix equation can
ZA + ZB + ZC
ZA ZC be solved using various methods including the method
Z3 = (2.12) of determinants or the Cramers rule. The description of
ZA + ZB + ZC
these methods is beyond the scope of this chapter.
2.4 MESH ANALYSIS 2.5 NODAL ANALYSIS
Mesh analysis is applicable to networks comprising of For a network with (m + 1) nodes including the refer-
multiple meshes where only voltage input sources are ence node or the datum node, the node equations can

be written in matrix form of the order of (m m) using Here, Yjj is referred to as the self-admittance of
Kirchhoffs current law as follows: node j.
3. All admittances connected to node j and node k are
summed up and denoted as Yjk. Here, Yjk is referred
Y11 Y12 Y13 .... Y1m V1 I1
Y to as the mutual admittance of nodes j and k. Yjk is
Y22 Y23 .... Y2m V2 I2
21 = or written on the left side of the equation with nega-

tive sign. If no admittance is connected between
Y m1 Y m2 Y m3 .... Y mm Vm I m nodes j and k, then Yjk is zero. If the network con-
sists of only passive elements, then the admittance
[Y ][V ] = [I ]
matrix is symmetric, that is, Yjk = Ykj.
The procedure for writing the node equations in matrix 4.Ij is the current source connected to node j and is
form is as follows. positive if it is flowing towards node j and is nega-
tive if it is flowing away from the node j. If there is
1. The network should have only current sources.
no current source connected to node j, then Ij is zero.
In case voltage sources are present, convert all
voltage sources into current sources using source The matrix equation can be solved using various methods
transformation. including the method of determinants or the Cramers
2. For node j, the admittances of all branches con- rule. The description of these methods is beyond the
nected to node j are summed up and denoted by Yjj. scope of this chapter.
IMPORTANT FORMULAS
1. The equivalent resistance Req of n resistors in series Z1Z2 + Z2Z3 + Z3Z1

is ZB =
Z3
Req = R1 + R2 + + Rn Z1Z2 + Z2Z3 + Z3Z1
ZC =
2. The equivalent resistance Req of n resistors in par- Z1
allel is
1 1 1 1 8. p to T-Transformations:
= + + + ZA ZB
Req R1 R2 Rn Z1 =
ZA + ZB + ZC
3. The equivalent capacitance Ceq of n capacitors in
ZB ZC
series is Z2 =
ZA + ZB + ZC
1 1 1 1
= + + + ZA ZC
Ceq C1 C2 Cn Z3 =
ZA + ZB + ZC
4. The equivalent capacitance Ceq of n capacitors in
parallel is 9. Mesh analysis:
Ceq = C1 + C2 + + Cn
Z11 Z12 Z13 .... Z1m I1 V1
Z Z22 Z23 .... Z2m I2 V2
5. The equivalent inductance Leq of n inductors in 21 = or
series is
Zm1 Zm2 Zm3 .... Zmm I m Vm
Leq = L1 + L2 + + Ln
[Z ][I ] = [V ]
6. The equivalent inductance Leq of n inductors in
parallel is 10. Nodal analysis
1 1 1 1
= + + + Y11 Y12 Y13 .... Y1m V1 I1
Leq L1 L2 Ln Y Y22 Y23 .... Y2m V2 I2
21 = or
7. T to p-Transformations:
Y m1 Y m2 Y m3 .... Y mm Vm I m
Z1Z2 + Z2Z3 + Z3Z1
ZA =
Z2 [Y ][V ] = [I ]

SOLVED EXAMPLES 17
SOLVED EXAMPLES
1. For the circuit shown in the following figure, the 2. For the circuit shown in Question 1, the current
current through resistor R1 is through resistor R2 is
(a) -143 mA (b) -429 mA
I1 R1, 10 A R2, 20 I (c) 143 mA (d) 429 mA
2
10V 20 V Solution. Refer to the Solution of Question 1.

1 R3, 2 Substituting the value of I3 = (2/7) A in Eq. (3),
40
V1 V2 we get
I3 80
20 - 20I2 - =0
7
B
Therefore,
(a) -143 mA (b) -429 mA
(c) 143 mA (d) 429 mA 3
I2 = A = 429 mA
7
Solution. Applying Kirchhoffs current law at Ans. (d)
nodeA, we get
3. The voltage V in the circuit shown in the following
I3 = I1 + I2 (1) figure is
Applying Kirchhoffs voltage law in left loop, we get 3
+
10 - 10I1 - 40I3 = 0 (2)
+ +
Applying Kirchhoffs voltage law in right loop, we get V 10 V 5V
20 - 20I2 - 40I3 = 0 (3)

Multiplying Eq. (2) by 2 and adding it with Eq.
(3), we get (a) 10 V (b) 15 V
(c) 5 V (d) None of the these
40 - 20(I1 + I2) - 120I3 = 0 (4)
Solution. The voltage, V, in the given circuit is
Substituting the value of I1 + I2 = I3 in Eq. (4), equal to the voltage across the terminals marked as
we get `+ and `- which is equal to 10 V.
40 - 140I3 = 0 Ans. (a)
4. The current i4 in the circuit shown in the following
Therefore, figure equals to
40 2 i1=5 A i2=3 A
I3 = = A
140 7
Substituting the value of I3 in Eq. (2), we get i0=7 A
80
10 - 10I1 - =0
7
Therefore,
-1 i4=? i3=4 A
I1 = A = -143 mA
7
(a) 12 A (b) -12 A
Ans. (a) (c) 4 A (d) None of these

Solution. Refer to the following figure. Solution. Applying Kirchhoffs current law to the
node containing elements C, E and F, we get
i1=5 A i2=3 A
-6 + i = 1
A
i0=7 A Therefore,
i6 i=7A
i5
Therefore, power received by element F is
PF = (-6) 7 = -42 W
i4=? i3=4 A
In other words, the element supplies power of 42 W.
Applying Kirchhoffs current law at node A, we get Ans. (d)
i0 + i1 + i4 = 0 7. Refer to the network in the following figure. What
voltage would be needed to replace the 5 V source
Therefore, to obtain vy = -6 V for iz = 0.5 A?
7 + 5 + i4 = 0 or i4 = -12 A (a) 2.167 V (b) -2.167 V
(c) 4.325 V (d) -4.325 V
Ans. (b)
5. For the circuit shown in the following figure, the 2 iz
power delivered by element D is
+ +
(a) 36 W (b) -36 W 5V + 2 vx 1 vy

3vx
(c) 42 W (d) -42 W
+ 3v
C Solution. Applying Kirchhoff's current law (KCL)
at the 2-1-iz junction, we get
6 A +
3 v A 2 A 3 v B 4A 6v E 1 A 6 v F i vy = 1(3vx + iz ) = -6
+ + 6A +
Substituting the value of iz = 0.5 A and vy = -6 V
D in the above equation, we get
v +
-6 - 0.5
vx = = -2.167 V
Solution. Applying Kirchhoffs voltage law to 3
loop having elements C, E, D and B, we get
Ans. (b)
3 + 6 + v + (-3) = 0 8. Among the four networks, N1, N2, N3 and N4,
given in the following figure, the networks having
Therefore,
identical driving point function are
v = -6 V
2H 1 2H 1
2
Therefore, the power supplied by element D is
1F
PD = (-6) (6) = -36 W 1F N1 2 1F N2
In other words, the element receives a power of
36 W or in theoretical terms, the element delivers 1
a power of -36 W. 1 1 2H
Ans. (b)
6. For the circuit shown in Question 5, the power 1H
received by element F is 1F N3 1F N4
(a) 36 W (b) -36 W (a) N1 and N2 (b) N2 and N4

(c) 42 W (d) -42 W (c) N1 and N3 (d) N1 and N4

SOLVED EXAMPLES 19
Solution. For the network N1, the driving point Solution. The given network comprises of series-
function is parallel combination of resistors. The equivalent
1 1 2s2 + 2s + 1 resistance of the combination of resistors R1, R2
Y1(s) = s + + = and R3 is
2s + 1 (1/s) + 2 2s + 1
For the network N2, the driving point function is R1,2,3 = (100 + 50) 100 = 60
1 1 1+s The equivalent resistance of the combination of
Y2 (s) = + =
2s + 1 2 + (1/s) 2s + 1 resistors R4 and R5 is
For the network N3, the driving point function is R4,5 = 56 56 = 28
1
Y3 (s) = s + The total equivalent resistance of the circuit is
1 + [1/{1 + (1/s)}]
1+s Req = 60 + 28 + 150 = 238
= s+
s+1+ s The following figure shows the equivalent circuit.
2
2s + 2s + 1
= Req
2s + 1
For network N4, the driving point function is 238
Battery
1 2s2 + s + 1
Y 4 (s) = s + =
2s + 1 2s + 1 100 V
From the above, we can see that N1 and N3 net-
works have identical driving point function.
Ans. (c)
The current through R6 is the same as the current
9. For the network shown in the following figure, the
through Req. Therefore,
current through resistor R6 is
R1 100
IR = A = 420 mA
6
238
100 Ans. (a)
R2 R3 10. For the network shown in Question 9, the current
100 50
Battery R6 through resistor R2 is
100 V R4 150 (a) 175 mA (b) 165 mA
(c) 168 mA (d) 178 mA
56
R5 Solution. The current through resistor R2 is
56 420 10-3
100
A = 168 mA
250
(a) 420 mA (b) 310 mA
(c) 750 mA (d) 350 mA Ans. (c)
1. The two electrical sub-networks N1 and N2 are con- +10 V

nected through three resistors as shown in the fol- 5
lowing figure. The voltages across 5 resistor and
1 resistor are given to be 10 V and 5 V, respec- 15
tively. What is the voltage across 15 resistor (in
N1 N2
volts)? 1
+5 V

Solution. The current through 5 resistor is 10 + 2Vo = I

10 Using Ohms law,
i5 = = 2A
5
Vo = -4I = -4(10 + 2Vo)
The current through 1 resistor is
Solving the above equation, we get
5
i1 =
= 5A
1 Vo = -4.44 V = -4440 mV
Hence, the current through 15 resistor is Ans. (-4440)
i15 = -(i1 + i5) = -(5 + 2) = -7 A 4. For the circuit shown in Question 3, find the value
of power dissipated (in watts) by the dependent
The voltage across 15 resistor is source.
V15 = 15(i15) = 15(-7) = -105 V
Ans. (105) Solution. Applying Kirchhoffs voltage law in loop 1,
we get
2. A DC circuit shown in the following figure has a
voltage source V, a current source I and several -Vo + 6I - Vx = 0
resistors. A particular resistor R dissipates a power Therefore,
of 4W when V alone is active. The same resistor -Vo + 6(10 + 2Vo) - Vx = 0
R dissipates a power of 9W when I alone is active.
What is the power dissipated by R (in watts) when Substituting the value of Vo = -4.44 V in the
both sources are active? above equation, we get
Vx = 11.16 V
+ Resistive The power dissipated in the dependent source is
V network R
-(2Vo)(Vx) = -(2 -4.44) 11.16 = 99.1 W
Ans. (99.1)
5. For the circuit shown in the following figure, find

I
the power supplied by the 2 A current source (in
Solution. The power dissipated when V alone is watts).
acting is
P1 = 4W 2A 100 i100
B A
The power dissipated when I alone is acting is i2
i1 i60
P2 = 9W i3
60 4 50 200 V
The total power dissipated when both the sources 30 25 +
are active is 1
3 2
P = ( P1 + P2 )2 = ( 4 + 9 )2

= (2 + 3)2 = 25 W
Ans. (25) Solution. Applying Kirchhoffs current law at
3. For the circuit shown in the following figure, find node B, we get
the value of Vo (in milli-volts). i1 + i60 = 2

Therefore,
4 i60 = 2 - i1
I A
1 + Vo
Applying Kirchhoffs current law at node A, we get
+
6 10 A Vx 2Vo 2 = i2 + i3 + i100

Therefore,
i100 = 2 - i2 - i3
Solution. Applying Kirchhoffs current law at Applying Kirchhoffs voltage law around loop 1,
node A, we get we get

PRACTICE EXERCISE 21
100(2 - i2 - i3) + 200 - 25i3 = 0 Therefore,

4
i1 = A
Therefore, 3
100i2 + 125i3 = 400 Applying Kirchhoffs voltage law around loop 4,
we get
Applying Kirchhoffs voltage law around loop 2, V2A + 50i2 + 60i60 = 0
we get
Therefore,
-50i2 + 25i3 = 0 -680
V2A = V
Solving the above two equations, we get 7
The power dissipated in the 2 A current source is
8 16
i2 = A and i3 = A -680
7 7 V2A 2 = 2 = -194.29 W
7
Applying Kirchhoffs voltage law around loop 3,
Therefore, the power supplied by the 2 A current
we get
source = 194.29 W
-60(2 - i1) + 30i1 = 0 Ans. (194.29)
PRACTICE EXERCISE
1. The internal resistance of a battery which has an (a) 605 mV (b) 705 mV
open circuit voltage of 12 V and delivers a current (c) 805 mV (d) 905 mV
of 100 A to a load resistance of 0.1 is (2 Marks)
(a) 2 (b) 200 m (c) 20 m (d) 2 m 4. Refer to the network shown in the following figure.
(2 Marks) The reading of the voltmeter connected between
terminals a-b is (Given that the average power dis-
2. A square waveform, as shown in the following
sipated in the 5 resistor is 20 W and assume the
figure, is applied across 1 mH ideal inductor.
voltmeter to be ideal)
The current through the inductor is a wave
g f e c 8 a
of peak amplitude. +
vL(t) 6 90 V 17

+
1V + 5
R VM VM

20W
13
0.5 1 t(ms) h d 7 b
1 (a) 10 V (b) 5 V (c) -5 V (d) -10 V
(2 Marks)
(a) Triangular, 0.5 A (b) Square, 1 A
(c) Spikes, (d) None of these 5. In the network shown in Question 4, the reading
(2 Marks) of the voltmeter connected between terminals c-g
is (Given that the average power dissipated in the
3. For the network shown in the following figure, the 5 resistor is 20 W and assume the voltmeter to
value of source voltage Vs that gives 7.5 mA cur- be ideal.)
rent in the 3 resistor is
(a) 15 V (b) 24 V (c) 44 V (d) 45 V
a 8 b 4 c 1 d (1 Mark)
6. Two 2H inductance coils are connected in series
and are also magnetically coupled to each other
VS + 7 6 3 7.5 mA with coefficient of coupling being 0.1. The total

inductance of the combination can be
(a) 0.4H (b) 3.2H (c) 4.0H (d) 4.4H
h g e
12 2
f (2 Marks)

7. Refer to the circuit in the following figure, the value 13. For the circuit given in Question 12, the power
of vx is absorbed by the 5 resistor is
4 (a) 395 W (b) 355 W (c) 435 W (d) 405 W
iin
+ vx (1 Mark)
14. Refer to the transistor circuit in the following
+ + figure. If the value of ID is 1.5 mA, the value of
2 2V 6 A Is 2 8V 4vx VDS is

(a) 2.5 V (b) 1.5 V (c) 0.5 V (d) 3 V
(1 Mark)
(a) -6 V (b) 5 V (c) -8 V (d) 3 V
(1 Mark) ID
8. In the circuit shown in Question 7, the value of iin is 5 k
(a) -29 A (b) 28 A (c) -29.5 A (d) 23 A IG=0 +
(2 Marks) +
VDS 12 V
+
9. In the circuit shown in Question 7, the value of the VGS
power provided by the dependent source is +
VG ID
2 k
(a) 192 W (b) 175 W (c) -175 W (d) -192 W
(1 Mark)
10. The voltage V in the following figure is equal to 15. In the transistor circuit in Question 14, if ID = 2
4V mA and VG = 3 V, then the value of VGS is
+ (a) 1 V (b) 2 V (c) -1 V (d) -2 V
(1 Mark)
5V + 2 + 4V

16. For the circuit shown in the following figure, gm =
25 10-3 S (in siemens) and vs = 10 cos 5t mV,
the voltage vo is
+V
300
(a) 3 V (b) -3 V
(c) 5 V (d) None of these
(1 Mark) + +
11. The nodal method of circuit analysis is based on vs 50 k v gmv 1 k vo
(a) Kirchhoffs voltage law and Ohms law
(b) Kirchhoffs current law and Ohms law
(c) K
irchhoffs current law and Kirchhoffs voltage law
(d) Kirchhoffs current law, Kirchhoffs voltage law (a) -248.5 cos 5t mV (b) 248.5 cos 5t mV
and Ohms law (c) -178.5 cos 5t mV (d) +178.5 cos 5t mV
(1 Mark) (2 Marks)
12. For the circuit given in the following figure, the 17. For the network shown in the following figure, find
current through the 60 V source is R if Req = 80 .
10 R 40
+ v3
i3
+
i1 i2 i4 i5
+ +
5i2
+ + Req 100 30 20
60V + v1 20 v1 v5

v2 v4 5
4
(a) 213.3 (b) 116.6

(a) 27 A (b) 18 A (c) 36 A (d) 45 A (c) 894.4 (d) 523.6
(2 Marks) (1 Mark)

18. For the network shown in Question 17, find R if V2 0V

R = Req.
+ +
(a) -51.79 (b) 51.79
(c) -61.79 (d) 61.79 2V 1V
(1 Mark)
+
19. For the circuit in the following figure, the value of E=?
ix is
15 k 10 k + +

4V 5V
5V V1 10V
+ 10 k ix 4 k 47 k (a) -16 V

(b) 4 V
(c) -6 V (d) 16 V
(1 Mark)
(a) 0.144 mA (b) 0.512 mA value of Vs which makes Io = 7.5 mA is
(c) 0.234 mA (d) 0.381 mA 8 1 4 2
(2 Marks)
20. For the circuit shown in Question 19, the power

Vs + 6 6
dissipated by the 15 k resistor is 7
Io
(a) 0.541 mW (b) 0.712 mW 12
(c) 0.845 mW (d) 0.123 mW
(1 Mark) (a) 705 mV (b) 695 mV
21. In the circuit of the following figure, the value of (c) 725 mV (d) 680 mV
the voltage source E is (2 Marks)

1. Find the voltage eo (in volts) of the circuit shown 3. For the circuit shown in Question 2, what is the
in the following figure. voltage drop (in volts) across the 6 resistor?
(1 Mark) (1 Mark)
4. The voltage eo (in volts) in the following figure is
4 2
+
4 2
12 V eo 2 16 V +
8A 10 12 eo
6
2. For the circuit shown in the following figure, what

is the value of current supplied (in amperes) by the 5. For the network shown in the following figure, find
60 V source? the transfer resistance, Vin/I4, (in ohms). (RL = 10 )
(2 Marks)
(2 Marks)
10 10 10
7 a
Vin I1 I2 I3
5 5 5
I1 +
12 I2 6 I3 12
RL
+
60 V I4
I4

6. How much power is delivered (in watt) by the 5 2

dependent current source shown in the following
figure?
(2 Marks) I1 I2
4
5 20 V 10 V
+ +
3
+ V1
5 A

V1=20 V
5 I3 I4
I
5 4
7. For the network shown in the following figure, find 8. For the network shown in Question 7, find the
the value of I1 (in milli-ampere). value of I4 (in ampere).
(2 Marks) (1 Mark)
1. (c) The following figure shows the equivalent cir-

L L
1
cuit of the problem iL (t) = v (t) dt
0.510
-3
Equivalent 110-3
1 dt + ( -1) dt +
1
=
1 10-3 0
circuit of
battery 0.510-3
100 A
R 1 t 0.510-3 - t 110-3 -3 +
0.10 -3
=
1 10 0
0.510
+
12 V
The following figure shows the waveform of current
iL(t). Slope of the waveform is +2 for the rising tri-
angular wave and 2 for the falling triangular wave.
The internal resistance of the battery (R) can iL(t)
be calculated using the expression that current
through the load resistor given as
0.5
12
I= = 100
R + 0.1 t(ms)
0.5 1.5 2.0
Therefore,
0.5
R = 0.02 = 20 m
2. (a) The current through the inductor is The peak value of current is
0.5 10-3
iL (t) = vL (t) dt
1 = 0. 5 A
L 1 10-3
3. (b) The resistive network is a series parallel combi-
So, the current through inductor is the integration nation of resistors. The equivalent resistance seen
of the applied voltage across the inductor. On inte- at terminals c-f is
grating a square wave, we get a triangular wave.
So, the current through the inductor is a triangular 6 (1 + 3 + 2) = 3
wave. The equivalent resistance seen at terminals b-g is

ANSWERS TO PRACTICE EXERCISE 25
7 (4 + 3) = 3.5 Therefore,
The resistance seen by the voltage source is VM = 44 V
8 + 12 + 3.5 = 23.5 6. (d) The total inductance of the combination of the

two inductance coils is given by
The current out of the voltage source is Vs/23.5.
The current flowing through the 4 resistor in L = L1 + L2 2M
= L1 + L2 2k L1L2
branch b-c is
Vs 7 Vs
= Therefore,
23.5 7 + 7 47
The current flowing through the 3 resistor in the L = 2 + 2 2(0.1) 2 2 = 4 0.4
branch d-e is
Hence, the value of L can be 3.6 H or 4.4 H. Therefore,
Vs 6 Vs option (d) is the correct answer.
=
47 6 + 6 94
7. (a) Applying Kirchhoffs voltage law to the 2 -
It is given that the current through the 3 resistor 4 -2 loop, we get
is 7.5 mA. Therefore,
-2 + vx + 8 = 0
= 7.5 10-3
Vs
94 Therefore,
Therefore, vx = -6 V
Vs = 705 mV 8. (d) Applying Kirchhoffs current law to the top
right node, we get
4. (d) The current through the 5 resistor is
vx
Is + + 4vx - 4 = 0
20 4
=2 A
5 Therefore,
From the given polarity of the voltage source, the Is = 29.5 A
direction of the current is such that it passes from
d to c. Therefore, d is positive with respect to c. Applying Kirchhoffs current law to the top left
The voltage is node, we get
Vdc = 2 5 = 10 V -2 v
iin + - Is - x + 6 = 0
2 4
Applying Kirchhoffs voltage law to the loop abdca
containing the voltmeter, we get Solving the above equation, we get
Vac + Vcd + Vdb + Vba = 0 iin = 23 A
Since the current flowing through the ideal voltme- 9. (d) The power provided by the dependent source is
ter is zero, we have
8 (4vx) = 8 4 -6 = -192 W
Vac = 0, Vdb = 0 and VM = -Vba
10.(a) Applying Kirchhoffs voltage law to the outer
Therefore, loop, we get
VM = -10 V V+5-4-4=0
5. (c) Applying Kirchhoffs voltage law to loop cefgc, Therefore,
we get
V=3V
Vce + Vef + Vfg + Vgc = 0
11. (b)
Therefore,
12. (a) Given that v1 = 60 V. Therefore, v2 = 60 V.
2 17 - 90 + 2 6 + VM = 0 The current i2 is obtained as

v2 60 Applying Kirchhoffs voltage law to the input loop,

i2 = = = 3A we get
20 20
The current i4 is obtained as vs - (300 + 50 103)i = 0
v1 60 Substituting the value of vs and solving for i, we

i4 = = = 15 A get
4 4
The voltage v3 is obtained as 10 cos 5t
i= mA
300 + 50 103
v3 = 5i2 = 5 3 = 15 V
Therefore,
By applying Kirchhoffs voltage law to the outer
50 103 10 cos 5t
loop, we get vp = mV= 9.940 cos 5t mV
300 + 50 103
-60 + v3 + v5 = 0 Therefore,
Therefore, vo = -1 103 gm vp
v5 = 60 - 15 = 45 V = -1 103 25 10-3 9.940 cos 5t mV
The current i5 is obtained as = -248.5 cos 5t mV
v5 45 17. (a) The equivalent resistance is given by
i5 = = =9A
5 5
Req = {( 20 + 40 ) 30 + R} 100 + 10 = 80
Applying Kirchhoffs current law at the top right
node, we get Solving the above equation, we get
i3 = i4 + i5 R = 213.3
Therefore, 18. (b) When R = Req,
i3 = 15 + 9 = 24 A
R = {( 20 + 40 ) 30 + R} 100 + 10
Applying Kirchhoffs current law at the top left
node, we get Solving the above equation, we get
i1 = i2 + i3 R = -61.79 or 51.79
Therefore,
Since R cannot have negative values, therefore R
i1 = 3 + 24 = 27 A = 51.79 .
13. (d) The power absorbed by the 5 resistor is 19. (a) The equivalent resistance seen by the 5V
source is
v5i5 = 45 9 = 405 W
14. (b) By applying Kirchhoffs voltage law, to the [{(4 103 47 103 ) + 10 103 } 10 103 ] + (15 103 )
12 V-5 k-VDS-2 k loop we get = 20.09 k
-12 + 5000ID +VDS + 2000ID = 0 Therefore, the current delivered by the 5 V source is
Therefore,
5
VDS = 12 - 7000 1.5 10-3 = 1.5 V = 0.249 mA
20.09 103
15. (c) By applying Kirchhoffs voltage law to the Therefore, the current ix is obtained as
VG -VGS-2 k loop, we get
13.69 103
-VG + VGS + 2000ID = 0 ix = 0.249 10-3
10 103 + 13.69 103

Therefore,
VGS = VG - 2000ID = 3 - 2000 2 10-3 = -1 V
= 0.144 mA
20. (c) The voltage across the 15 k resistor is

16. (a) The output voltage vo is given by
vo = -1 103 gm vp 5 - 10 103 0.144 10-3 = 3.56 V

1 1 1 1
20 + 7 + 4 - V1 V/20
4
1 1 1 1 V = 0
- + + 2 27

4 4 6 6
The power dissipated across the 15 k resistor is 0.443 -0.250 V1 V /20
-0.250 0.583 V = 0
(3.56)2 2
W = 0.845 mW
15 103 Solving for V2, we get
21. (a) Applying Kirchhoffs voltage law to the right 0.443 Vs /20
loop, we get N2 -0.250 0
V2 = = = 0.0638Vs
0 - 1 - E - 5 - 10 = 0 R 0.443 -0.250
Therefore, -0.250 0.583
E = -16 V Now,
22. (a) Using node voltage method, the matrix form of V2 = 6 Io = 6 7.5 10-3
equations is given by
Therefore,
0.0638Vs = 6 7.5 10-3
1 1 1 1
20 + 7 + 4 - V1 V/20
4 =
1 1 1 1 V2 0 Hence,
- + +
4 4 6 6 Vs = 705 mV
0.443 -0.250 V1 V /20
=
Numerical-Answer .583 V2 0
0.250 0Questions
1. Applying Kirchhoffs current law at the 4-4-2 3. The voltage drop across 6 resistor is
node, we get 1
eo - 12 eo eo 6I3 = 6 I1 = 18 V
2
+ + =0
4 4 4 Ans. (18)
Solving the above equation, we get 4. Applying source conversion, the equivalent circuit
eo = 4 V is shown in the following figure.
10 2
Ans. (4)
2. Applying Kirchhoffs voltage law to different loops,
16 V +
we get
80 V 12 eo
12I2 = 6I3 and 12I2 = 12I4
6
Therefore,
I3 = 2I2 and I4 = I2
Applying Kirchhoffs voltage law to the outer loop, Applying Kirchhoffs current law at the 2 -16 -12
we get node, we get
60 = 7I1 + 12I4 eo - 80 eo eo - 16
+ + =0
12 12 6
Applying Kirchhoffs current law at the 7-12-
6-12 node, we get Solving the above equation, we get
I1 = I2 + I3 + I4 eo = 28 V
Ans. (28)
Substituting the value of I3 and I4, in the equation
5. The network equation matrix is given by
above, we get
I1 = 4I2 15 -5 0 0 I1 Vin
-5 20 -5 0 I2 0
0 -5 20 =
-5 I3 0
Therefore,
1
60 = 7 I1 + 12 I1 0 0 -5 5 + RL I 0
4 4
Thus,
R = 5125R + 18750
I1 = 6 A
Ans. (6) N4 = 125Vin

N4 V in 9 -4 0 0
Now, I 4 = =
-4 9 -4 8 -3
R
R 41RL + 150 6 0 0
= = = 1786
0 0 8 -3 -4 6 -3 7
Therefore, the transfer resistance is
0 0 -3 7
Vin
= 41RL + 150 = 560
I4 20 -4 0 0
Ans. (560) -10 6 0 0 20 -4
N1 = = 47 = 3760 and
6. Applying Kirchhoffs voltage law to the left loop, we get -20 0 8 -3 -10 6
V 10 0 -3 7
20 - 5I - 5 I - 1 = 0
5
Therefore, 9 -4 0 20
-4 6 0 -10
- 10I + 20 - 20 = 0 or I = 0 N4 =
0 0 8 -20
= 760
Therefore, only the dependent source acts. The 0 0 -3 10
current of dependent source is
V1 The current I1 is given by
= 4A
5 N1 3760
The power delivered is I1 = = = 2.11 A = 2110 mA
R 1786
(4)2R = 16 5 = 80 W
Ans. (2110)
Ans. (80)
8. The current I4 is obtained as follows:
7. The matrix form of network equations is given by
9 -4 0 0 I1 20 N4 760
I4 = = = 0.426 A
-4 6 0 0 I2 -10 R 1786
=
0 0 8 -3 I3 -20 Ans. (0.426)
0 0 -3 7 I 4 10
1. The minimum number of equations required to 5

analyze the circuit shown in the following figure is (a) (b) 1
6
C C 6 3
(c) (d)
5 2
(GATE 2003: 2 Marks)
R R Solution. Figure given below shows the circuit
arrangement
V R C R i
i 3 1
1
a
1
i
3 1

i
1
1
(a) 3 (b) 4 3
i
(c) 6 (d) 7 1 6
1
(GATE 2003: 1 Mark)
1 1
Solution. Since the voltage at one node is known, 1 1 i
using nodal analysis, we conclude that only three b
i
equations required. Ans. (a) 3
2. Twelve 1 resistances are used as edges to form a Therefore,
cube. The resistance between two diagonally oppo- i i i
site corners of the cube is Vab = 1 + 1 + 1
3 6 3

The resistance between the two diagonally opposite If current enters the dotted terminals of coil 1,
corners of the cube is then a voltage is developed across coil 2 whose
Vab higher potential is at dotted terminals. Applying
5
Req = = Kirchhoffs voltage law, we get
i 6
-Mdi L1di Mdi di
Ans. (a) V = + - + L2
dt dt dt dt
3. The current flowing through the resistance R in the di
circuit shown in the following figure has the form = (L1 + L2 - 2M )
dt
P cos 4t where P is
The above equation can be written as
M = 0.75 H di
1/10.24 F V = Leq
dt
where Leq is the equivalent inductance measured
between the terminals 1 and 2 and is given by
3 R = 3.92
Leq = L1 + L2 - 2M
Ans. (d)
V = 2 cos 4t +
20 V
5. The transfer function H(s) =
Vo (s)
of an RLC cir-
V i (s)
(a) (0.18 + j 0.72) (b) (0.46 + j 1.90) 106
(c) -(0.18 + j 1.90) (d) -(0.192 + j 0.144) cuit is given by H(s) = . The qual-
s2 + 20s + 106
(GATE 2003: 2 Marks) ity factor (Q-factor) of this circuit is
(a) 25 (b) 50 (c) 100 (d) 5000
Solution. Question is incomplete since L1 and L2
are not given.
Solution. The characteristic equation of the given
4. The equivalent inductance measured between the
transfer function is
terminals 1 and 2 for the circuit shown in the fol-
lowing figure is s2 + 20s + 106
Comparing the given characteristic equation with
M
the standard characteristic equation
1 s2 + BWs + w o2 = 0
L1 L2
We have the quality factor
w
Q= o
2 BW
(a) L1 + L2 + M (b) L1 + L2 - M where w o = 106 and BW = 20. Therefore,
(c) L1 + L2 + 2M (d) L1 + L2 - 2M
103 1000
Q= = = 50
(GATE 2004: 1 Mark) 20 20
Ans. (b)
Solution. The following figure shows the equiva-
lent circuit, with voltage source V connected across 6. For the circuit shown in the following figure, the
terminals 1 and 2 initial conditions are zero. Its transfer function
V (s)
H(s) = o is
Mdi/dt L1 Mdi/dt L2 V i (s)
-+ -+
1 2 + 10 k 10 mH +
vi(t) 100 F vo(t)

1 106
(a) (b)
s2 + 106 s + 106 s2 + 103 s + 106 R1 R4
3 6
10 10
(c) (d) 10 V + a + b
2
s + 10 s + 103 6
s + 106 s + 106
2

R2 R3
Solution. The transfer function is
1 / sC
H(s) =
R + sL + (1 / sC )
1 (a) 0.238 V (b) 0.138 V
= 2
s LC + sCR + 1 (c) -0.238 V (d) 1 V
1 (GATE 2005: 2 Marks)
= -3 -6
s (10 10
2
100 10 ) + s(10 103 100 10-6 ) + 1
Solution.
Therefore,
Va = 5 (R1 = R2)
1
H(s) =
10-6 s2 + s + 1 R3 1.1
6 Vb = 10 = 10
10 R3 + R4 2.1
=
s2 + 106 s + 106
The voltage reading of the ideal voltmeter con-
Ans. (d) nected between a and b is
7. Impedance Z as shown in the following figure is V = Va - Vb
j5 j2 That is,
V = -0.238 V
j10
j2 Ans. (c)
9. In the interconnection of ideal sources shown in the
j10 following figure, it is known that the 60 V source is
absorbing power.
+
Z 20 V
(a) j29 (b) j9
(c) j19 (d) j39
+

(GATE 2005: 2 Marks) I 60 V
12 A
Solution. The total impedance is
5j + 2j + 2j + 20j - 20j = 9j
It may be mentioned here that one of the imped- Which of the following can be the value of the
ances due to mutual inductance is additive and the current source I?
other is subtractive. (a) 10 A (b) 13 A
Ans. (b) (c) 15 A (d) 18 A
8. If R1 = R2 = R4 = R and R3 = 1.1R in the bridge (GATE 2009: 1 Mark)
circuit shown in the following figure, then the read-
ing in the ideal voltmeter connected between a and Solution. Since the power is absorbed by 60 V
b is source, I> 0.

20 V Therefore,
+ E = (6600) 2 J = 13200 J = 13.2 kJ
Ans. (c)
+ I 11. In the circuit shown, the power supplied by the

I 60 V
voltage source is
12 A
1 1
Now,
I = 12 - 1 + 10 V

Therefore, 1A
2A
12 - 1 > 0 or I < 12 A. 1
1
Ans. (a)
10. A fully charged mobile phone with a 12 V battery
(a) 0 W (b) 5 W
is good for a 10 minute talk-time. Assume that,
(c) 10 W (d) 100 W
during the talk-time the battery delivers a constant
current of 2 A and its voltage drops linearly from
12 V to 10 V as shown in the following figure. How
Solution. The given network can be redrawn as
much energy does the battery deliver during this
shown in the following figure.
talk-time?
(a) 220 J (b) 12 kJ 1 3+i i
(c) 13.2 kJ (d) 14.4 J
v(t)
1 1
12 V
3A + 10 V
10 V
2+i
1A
1 2A
t
0 10 min
(GATE 2009: 1 Mark) 1
Solution. We know that Applying Kirchhoffs voltage law in the outer loop,
we get
P = v(t)i(t)
(3 + i)2 + (2 + i)2 = 10
The energy is given by
P t = v(t)i(t) t
i=0
Now, i(t) = I = 2 A (given) and v(t) t = Area
under v(t)-t curve. Therefore,
The power supplied by the voltage source is
1
v(t) t = 2 600 + (10 600)
2 P = Vi = 10 0 = 0 W
= 600 + 6000 = 6600 Ans. (a)

12. In the circuit shown below, the current I is equal to 2 -1

(a) A (b) A
1+ j 1+ j
1
I j4 j4 (c) A (d) 0 A
1+ j (GATE 2012: 1 Mark)
6
140 V Solution. The given network can be redrawn as
6 6
A
i (i+1)
(a) 1.4 0 A (b) 2.0 0 A
(c) 2.8 0 A (d) 3.2 0 A 1 j1
1A
10 V 10 V
Solution. Converting delta into star, the circuit
can be redrawn as shown below. B + D + C
1A
I j4 j1 1
j4
140 2 2
i (i+1)
E
2 According to Kirchhoffs current law at node
D, there will be no current in voltage sources.
According to Kirchhoffs current law at node A,
The equivalent impedance of the circuit is current through inductor will be
Z = (2 + j4) (2 - j4) + 2 i1 = i + 1 (1)
Solving the above equation, we get Applying Kirchhoffs voltage law in loop ABDC,
we have
Z =7
1 i + (i + 1)j1 - 1 0 + 1 0 = 0
Therefore, the current I is obtained as
Therefore,
140
I= = 20A -j
7 i= (2)
Ans. (b) 1+ j
13. In the circuit shown below, the current through the Therefore from Eqs. (1) and (2), we have
inductor is -j 1
i1 = i + 1 = +1 = A
j +1 j +1
Ans. (c)
1 j1 14. The average power delivered to an impedance
(4 - j3) by a current 5 cos (100pt + 100)A is
10 A
10 V 10 V (a) 44.2 W (b) 50 W
(c) 62.5 W (d) 125 W
+ +
(GATE 2012: 1 Mark)
10 A
Solution. The average power is the same as RMS
j1 1 power.
2
5 25
4 = 2 4 = 50 W
2
P = I rms R=
2

Note: Power is consumed only by resistance, that 16. The following arrangement consists of an ideal
is, by the real part of impedance. transformer and an attenuator which attenuates
Ans. (b) by a factor of 0.8. An AC voltage VWX1 = 100 V
15. If VA - VB = 6 V, then VC - VD is is applied across WX to get an open circuit voltage
VYZl across YZ. Next, an AC voltage VYZ2 = 100 V
R VA 2 VB R is applied across YZ to get an open circuit voltage
VWX2 across WX. Then, VYZ1/VWX1, VWX2/VYZ2
are, respectively,
R R
1
R R R 10 V
+ W
1 : 1.25
R
+ VC VD
Y
5V 2A
(a) -5 V (b) 2 V (c) 3 V (d) 6 V Z
X
Solution. The network can be redrawn as shown 125 80 100 80

in the following figure. (a) and (b) and
100 100 100 100
i
R VA VB i1 100 100 80 80
E (c) and (d) and
100 100 100 100
2
A B
i2 i4
R R R R
i3
i6 1 F +
10 V
Solution.
C D V YZ1 = 100 1.25 0.8 = 100 V
+ VC i5 V
D In the second case when 100 V is applied at YZ
5V 2A terminals, this whole 100 V will appear across the
V A - VB 6 secondary winding. Hence,
i= = = 3A
2 2 100
V WX2 = = 80 V
Applying Kirchhoffs current law at node B, we have 1.25
i = i2 + i1 Therefore,
Therefore, V YZ1 100 V WX2 80
i2 + i1 = 3 A = , =
V WX1 100 V YZ2 100
Applying Kirchhoffs current law at node E, we
have Ans. (b)
i1 = i3 + i4 17. Three capacitors C1, C2 and C3 whose values are
10 F, 5 F, and 2 F, respectively, have break-
Applying Kirchhoffs current law at node D, we down voltages of 10 V, 5 V and 2 V, respectively.
have For the interconnection shown in the following
i5 = i2 + i3 + i4 = i2 + i1 figure, the maximum safe voltage in volts that can
Therefore, be applied across the combination, and the corre-
i5 = 3 A sponding total charge (in C) stored in the effective
capacitance across the terminals are, respectively
Applying Kirchhoffs current law at node F, we have
i6 + 2 + i5 = 0 C2 C3
Therefore,
i6 = -2 - i5 = -5 A
Hence,
VC - VD = 1 i6 = -5 V
Ans. (a) C1

(a) 2.8 and 36 (b) 7 and 119 (a) 13, -20 (b) 8, -10
(c) 2.8 and 32 (d) 7 and 80 (c) -8, 20 (d) -13, 20
(GATE 2013: 2 Marks) (GATE 2013: 2 Marks)
Solution. The charge across a capacitor is Solution. The network given in the problem can
Q = CV be redrawn as shown in the following figure.
The breakdown charge of capacitor C1 is A
-6
Q1 = C1V1 = 10 10 10 = 100 C I1
I2
The breakdown charge of capacitor C2 is 5
+
Q2 = C2V2 = 5 10-6 5 = 25 C
Is +
+ 10 V 2 V2 1 V1
The breakdown charge of capacitor C3 is
Vs 2A
Q3 = C3V3 = 2 10-6 2 = 4 C

When the capacitors are in series, the charge is
the same. So, the maximum charge on C2 and C3 The voltage across 1 resistance is
will be minimum of (Q2, Q3) = min(25 C, 4 C)
= 4 C = Q23. V1 = 10 V
In series, the equivalent capacitance of C2 and C3 is The current through 1 resistance is
-6 -6
C2C3 5 10 2 10 10 10
C23 = = - -
= F I1 = = 10 A
C2 + C3 5 10 + 2 10
6 6 7 1
So, the equivalent voltage is The voltage across 2 resistance
4 10-6
V2 = 10 V
Q23 28
V23 = = -
= = 2.8 V The current through 2 resistance is
C23 (10/7) 10 6 10
10
In parallel, the voltage is same: I2 = = 5A
2
V1 = V23 = 2.8 V
Therefore, the maximum safe voltage that can be -2 + Is + I2 + I1 = 0
Is = 2 - I1 - I2 = 2 - 10 - 5
applied across the combination is 2.8 V. The charge
on capacitor C1 is
Therefore,
Q1 = C1V1 = 10 10-6 2.8 = 28 C
Is = -13 A
In parallel, the total charge Q is obtained as The voltage at node A is
-6 -6
Q = Q1 + Q23 = 4 10 + 28 10 = 32 C VA = 10 V
Applying Kirchhoffs voltage law on the left loop,
Therefore, the effective capacitance across the ter-
we get
minals is 32 C.
Ans. (c) Vs - 10 - 10 = 0
Common Data for Questions 18 and 19: Consider Hence,
the following figure: Vs = 20 V
Ans. (d)
I1 19. The current in the 1 resistor (in amperes) is
5
Is (a) 2 (b) 3.33
+ 10 V 2 1 (c) 10 (d) 12
Vs 2A
Solution. The current in the 1 resistor is
10
18. The current Is in amperes in the voltage source, I1 = = 10 A
1
and voltage Vs in volts across the current source
respectively, are Ans. (c)

CHAPTER 3
NETWORK THEOREMS
This chapter discusses the different network theorems including the superposition theorem, Thevenins and Nortons
theorems, maximum power transfer theorem and the Wye-delta transformations.
3.1 SUPERPOSITION THEOREM the current or voltage at any point in the network may
be calculated as algebraic sum of the individual contri-
butions of each source acting alone.
For a linear network, the overall effect produced in the
system due to a number of sources acting jointly can 3.2 THEVENINS THEOREM
be determined by superposing the effects of each of the
source acting separately. In other others, in a linear
network with several sources (including the equivalent A linear two-terminal circuit containing energy sources
sources due to initial conditions), the overall response at and impedances can be replaced by an equivalent cir-
any point in the network is equal to the sum of individ- cuit consisting of a voltage source VTH in series with
ual response of each source, considered separately, the an impedance ZTH, where VTH is referred to as the
other sources being made inoperative. A voltage source Thevenins equivalent voltage and is the opencircuit
can be made inoperative by making it as a short circuit voltage at the terminals and ZTH is referred to as the
and replacing it by its internal impedance. A current Thevenins equivalent impedance and is the input or
source can be made inoperative by making it as an open equivalent impedance at the terminals when the inde-
circuit and replacing it by its shunt impedance. pendent sources are made inactive. Figure 3.1(a) shows a
In nutshell, according to superposition theorem, in any generalized linear two-terminal network and Fig. 3.1(b)
linear circuit containing multiple independent sources, shows its Thevenins equivalent circuit.

36 Chapter 3: Network Theorems
i x shows a generalized two-terminal linear network and

Fig. 3.2(b) shows it Nortons equivalent circuit.
Linear +
circuit V Load
a
A a
Linear
y two-terminal iN ZN
(a) network
b
b
ZTH x (a) (b)
+ Figure 3.2| (a) Generalized two-terminal linear network.
l (b) Nortons equivalent circuit of (a).
VTH + Load
V
It may be mentioned here that Nortons equivalent
circuit is a dual of the Thevenins equivalent circuit.
y Therefore, ZTH = ZN and iN = VTH/ZTH. In fact, source
transformation of Thevenins equivalent circuit leads to
(b)
Nortons equivalent circuit.
Figure 3.1|(a) Generalized linear two-terminal network. If the network contains impedances and independent
(b) Thevenins equivalent circuit of (a).
sources, then deactivate the sources and find ZN by cir-
cuit reduction techniques and find iN with sources acti-
vated. If the network contains impedances, independent
The impedance ZTH can be calculated as follows. and dependent sources, then determine the short-circuit
current iN with all sources activated and find the open-
1. If the circuit contains only independent sources circuit voltage voc. ZN is the ratio of the open circuit
and resistors, deactivate the sources and find ZTH voltage voc to the short-circuit current iN. If the network
by circuit reduction techniques. Independent cur- contains only impedances and dependent sources, then
rent sources are deactivated by opening them while connect 1 A current source to the terminals and find
independent voltage sources are deactivated by the terminal voltage. ZN is the ratio of the open circuit
shorting them. terminal voltage to the 1 A current.
2. If the circuit contains resistors, dependent and
independent sources, determine the open circuit
voltage with the sources activated and the short 3.4 MAXIMUM POWER TRANSFER
circuit current when a short circuit is applied to THEOREM
the terminals. ZTH is the ratio of the open circuit
voltage to the short circuit current.
3.If the circuit contains impedances and only depen- The maximum power transfer theorem states that the
dent sources, then connect 1 A current source to the maximum power will be delivered by a network to a load
desired terminals, where ZTH has to be found and impedance ZL, if the load impedance ZL is a complex conju-
determine the terminal voltage. ZTH in this case is gate of the impedance Z of the network. Also, if a network
the ratio of the terminal voltage to 1 A current. is represented by its Thevenins equivalent circuit, maxi-
mum power transfer is attained when the load impedance
ZL is equal to the complex conjugate of the Thevenins
impedance ZTH. Maximum power transferred is given by
3.3 NORTONS THEOREM 2
VTH V2
Pmax = = TH
4RL 4RTH
Nortons theorem states that a linear two-terminal net-
work can be replaced by an equivalent circuit consisting 3.5 RECIPROCITY THEOREM
of a current source iN in parallel with impedance ZN,
where iN is the short-circuit current through the termi-
nals and ZN is the input or equivalent impedance at the The reciprocity theorem states that in a linear bilateral
terminals when the independent sources are turned off. single source circuit, the ratio of excitation to response
ZN is also given by the ratio of open circuit voltage to is constant when the positions of excitation and response
shortcircuit current at the terminal pair. Figure 3.2(a) are interchanged. Reciprocity theorem is applicable to

3.7 SUBSTITUTION, COMPENSATION AND TELLEGENS THEOREMS 37
circuits comprising of linear, time-invairant, bilateral, (I1/Y1 ) + (I2/Y2 ) + + (I n /Y n )

passive elements and a single source with zero initial I=
(1/Y1 ) + (1/Y2 ) + + (1/Y n )
conditions. Furthermore, the dependent sources are
excluded even if they are linear. Also, when the positions n
of source and response are interchanged, their directions (Ii/Yi ) (3.3)

i =1
should be marked same as in the original circuit. = n
If we consider two loops X and Y in a network and if an (1/Yi )
ideal voltage source V in loop X produces current I in loop i =1
Y, then by interchanging positions, if an identical source V 1 1
Y = = (3.4)
in loop Y produces the same current I in loop X, then the 1/Y1 + 1/Y2 + ...1/Y n n
network is said to be reciprocal. In other words, a linear 1/Yi
network is reciprocal if it remains invariant due to the i =1
interchange of positions of cause and effect in the network.
3.6 MILLMANS THEOREM 3.7 SUBSTITUTION, COMPENSATION

AND TELLEGENS THEOREMS
Millmans theorem states that if n number of generators
having generated emfs E1, E2, ..., En and internal imped- 3.7.1 Substitution Theorem
ances Z1, Z2 ... Zn are connected in parallel, then the emfs
and impedances can be combined to give a single equiva- According to substitution theorem, any branch in a net-
lent emf of E with an internal impedance of equivalent work may be substituted by a different branch without
value Z given by disturbing the voltages and currents in the entire net-
work, provided that the new branch has the same set
E1Y1 + E2 Y2 + En Y n n n
E= = Ei Y i Yi (3.1) of terminal voltages and current as the original branch.
Y1 + Y2 + Y n i =1 i =1
n 3.7.2 Compensation Theorem
Yi
1
Z= =1 (3.2)
Y1 + Y2 + ... Y n i =1 According to compensation theorem, if in a linear net-
1 1 1 work, the current in a branch is I and its impedance Z
where, Y1 = , Y2 = Yn =
Z1 Z2 Zn is increased by Z, then the increment in voltage and
current in each branch of the network is that voltage or
Figure 3.3(a) shows n number of generators having gen- current that would be produced by an opposing voltage
erated emfs E1, E2, ..., En and internal impedances Z1, source of value IZ introduced into the altered branch
Z2, ..., Zn connected in parallel and Fig. 3.3(b) shows after modification.
Millmans equivalent circuit.
x Z 3.7.3 Tellegens Theorem

+ x
Z1 Z2 Zn Tellegens theorem states that for any lumped network
E + whose network graph has b branches and n nodes, with
E1 + E2 + En + E

branch voltages and currents represented by vk and ik,
y y respectively (k = 1, 2, ..., b), measured with respect to
arbitrarily chosen associated reference directions and
(a) (b) satisfying all constraints of Kirchhoffs voltage law and
Figure 3.3| (a) n number of generators having Kirchhoffs current law, respectively, then
generated emfs E1, E2, ..., En and internal
b
impedances Z1, Z2, ..., Zn connected in par-
allel. (b) Millmans equivalent circuit of (a). vk ik = 0 (3.5)
k =1
A similar theorem can be stated for n current sources
in series. If n current sources I1, I2, ..., In with internal It may be mentioned here that the Tellegens theorem
admittances Y1, Y2, ..., Yn are connected in series then is applicable for any lumped network having linear or
they can be replaced by a single ideal current source with non-linear, active or passive and time-varying or time-
internal admittance Y given by invariant elements.

3.8 WYE-DELTA TRANSFORMATIONS Rb Rc

R1 = (3.6)
Ra + Rb + Rc
3.8.1 Delta-to-Wye Transformation Rc Ra
R2 = (3.7)
Ra + Rb + Rc
Figure 3.4 shows a delta network with resistances Ra,
Rb and Rc. Ra Rb
R3 = (3.8)
Ra + Rb + Rc
Rc
a b 3.8.2 Wye-to-Delta Transformation
R1 R2
n For the Delta-Wye transfomations shown in Fig. 3.4, if
the resistances of the Wye network R1, R2 and R3 are
given then the resistances of the Delta network Ra, Rb
Rb Ra
and Rc are given by
R3
R2R3
Ra = R2 + R3 + (3.9)
R1
c
Figure 3.4| Delta-Wye Transformations.
R1R3
Rb = R1 + R3 + (3.10)
R2
The corresponding resistances of the Wye network R1, R1R2

Rc = R1 + R2 + (3.11)
R2 and R3 are given by R3
IMPORTANT FORMULAS
1. Superposition theorem: In any linear circuit con- with impedance ZN, where iN is the short-circuit
taining multiple independent sources, the current current through the terminals and ZN is the input
or voltage at any point in the network may be cal- or equivalent impedance at the terminals when the
culated as algebraic sum of the individual contribu- independent sources are turned off.
tions of each source acting alone.
5. Reciprocity theorem: It states that in a linear bilat-
2. Maximum power transfer theorem: The maximum eral single source circuit, the ratio of excitation to
power will be delivered by a network to a load response is constant when the positions of excita-
impedance ZL, if the load impedance ZL is a com- tion and response are interchanged.
plex conjugate of the impedance Z of the network.
6. According to Millmans theorem
3. Thevenins theorem: A linear twoterminal circuit
containing energy sources and impedances can be n
replaced by an equivalent circuit consisting of a E Y + E2 Y2 + + En Y n

Ei Y i
voltage source VTH in series with an impedance E= 1 1 = i =1
Y1 + Y2 + + Y n n
ZTH, where VTH is referred to as the Thevenins Yi
equivalent voltage and is the open-circuit volt- i =1
age at the terminals and ZTH is referred to as the
Thevenins equivalent impedance and is the input 1 1
and Z= =
or equivalent impedance at the terminals when the Y1 + Y2 + + Y n n
independent sources are made inactive. Yi
i =1
4. Nortons theorem: It states that a linear two-ter-
minal network can be replaced by an equivalent 7. Delta-to-Wye transformation and Wye-to-delta
circuit consisting of a current source iN in parallel transformations:

SOLVED EXAMPLES 39
i. Delta-to-Wye transformation ii. Wye-to-delta transformation

Rb Rc R2R3
R1 = Ra = R2 + R3 +
Ra + Rb + Rc R1
Rc Ra R1R3
R2 = Rb = R1 + R3 +
Ra + Rb + Rc R2
Ra Rb R1R2
R3 = Rc = R1 + R2 +
Ra + Rb + Rc R3
SOLVED EXAMPLES

1. For the circuit shown in the following figure (R1 = Therefore,
1 , R2 = 1 , C1 = 1 F, L1 = 1 H, v(t) = 2t, i(t) =
e-t. Then, the value of voltage vo(t) is given by
1

1/R2 + sC1
(The initial conditions may be assumed to be zero.) V o(s) = V (s)
1
R1 L1 + R1
1/R2 + sC1
V (s) 2
= = 2
+ + s + 2 s (s + 2)
C1 R2

v(t) v (t) i(t)
o
Taking inverse Laplace transform, we get
vo (t) = t + e-2t - u(t)

1 1
2 2
(a) vo (t) = e-t - e-2t + t - u(t)
1 1
Considering the effect of current source i(t) and
2 2
making the voltage source v(t) inoperative, the
(b) vo (t) = e-t - e-2t + t - u(t)
1 equivalent circuit is shown in the following figure.
2 L1
(c) vo (t) = e-t - e-2t + t + u(t)
1 1
2 2
+
R1 C1 v (t) R2 i(t)
(d) vo (t) = e-t + e-2t + t + u(t) o
1 1
2 2
Solution. The output voltage can be found using

Therefore,
the superposition theorem. It is given that the ini-
tial conditions are zero, therefore, the initial voltage 1
across the capacitor is zero and the initial current Vo(s) = I (s)
across the inductor is zero. Considering the effect of 1/R1 + 1/R2 + C1s
voltage source v(t) and making the current source I (s)
=
i(t) inoperative, the equivalent circuit is shown in (s + 2)
the following figure. 1
=
R1 (s + 1)(s + 2)
1 1
= -
(s + 1) (s + 2)
+ +
C1 R2

v(t) v(t)
o
vo (t) = (e-t - e-2t )u(t)

The total output vo(t) is the sum of v

o (t) and Applying Kirchhoffs voltage law to the upper loop,
v(t).
o Therefore, we get
2 103 io + 2 103io + 6 = 0
vo (t) = t + e-2t - u(t) + (e-t - e-2t )u(t)
1 1
2 2
Therefore, io = -1.5 mA. Keeping the 2 mA cur-
= e-t - e-2t + t - u(t)
1 1 rent source active and replacing the voltage sources
2 2 of 6 V and 12 V as short circuits, the resultant
Ans. (a) circuit is shown in the following figure.
2 k
current io is
2 k
2 k 12 V io
+ 2 k
2 k
2 k 6V
io 2 mA
+ 2 k 2 k
2 mA 2 k 2 k
i
2 mA 2 k 2 k
The current of 2 mA gets divided equally. Therefore,
(a) 1 mA (b) 2 mA io = 1mA
(c) 2.5 mA (d) 1.5 mA
Applying superposition theorem, we get
io = io + io + io
Solution. We will apply the superposition theo-
rem to find out the current io. Keeping the 12 V
source active, and making the 2 mA current source = 3 mA - 1.5 mA + 1 mA = 2.5 mA
as an open circuit and the 6 V voltage source as a Ans. (c)
short circuit, the resultant circuit is shown in the
following figure. 3. The Thevenins equivalent voltage VTH appear-
ing between the terminals A and B of the network
12 V shown in the following figure is given by
2 k 12 V
+ 2 k
+
2 k 3 A

io io 2 k
1000V
2 k 2 k
j2 j6 j4 VTH
The current io is given by B
io =
12
= 3 mA
(2 + 2) 103 (a) j16(3 - j4) (b) j16(3 + j4)
Keeping the 6 V source active, and making the 2 mA (c) 16(3 + j4) (d) 16(3 - j4)
current source as an open circuit and the 12 V volt-
age source as a short circuit, the resultant circuit is Solution. Thevenins equivalent voltage is
VTH = 1000
4j
2 k 2 k 2 k 3 + 4j
100 4 j(3 - 4 j)
2 k io 6 V =
25

+ +
= 16 j(3 - 4 j) Ans. (a)
io 6V
2 k 2 k 2 k 2 k
current io is

SOLVED EXAMPLES 41
12 k The circuit shown in the previous figure can be

further simplified to the one shown in the following
4 mA
12 k figure.
iA
io
+

12 k 6V 12 k 12 k
12 k io 12 k 4 mA 12 k
(a) 1 mA (b) 0.8 mA

(c) -1 mA (d) 0.5 mA
Solution. The network shown in the given figure Applying the current division principle, current iA
has two sources, one voltage source of 6V and is given by
one current source of 4 mA. Considering only the
voltage source and replacing the current source by
12 103
iA = 3
(12 10 || 12 10 ) + 12 10 + 12 10
3 3 3
open circuit, the equivalent circuit is shown in the
4 10-3 = 1.6 mA
following figure.
12 k
Applying the current division principle again, we get
12 k
12 103
io = 3
1.6 10-3 = 0.8 mA
io 12 10 + 12 10
3
+ 6V
12 k 12 k
Therefore,
io = io + io = -0.3 10-3 + 0.8 10-3 = 0.5 mA
The circuit shown in the above figure can be further Ans. (d)
simplified to the one shown in the following figure. 5. In the following figure, what is the power dissi-
pated in the 2 resistor?
12 k
(a) 67.2 mW (b) 52.5 mW
i (c) 76.8 mW (d) 34.2 mW
2
24 k12 k + 6V
= 8 k
7 3
+

5V 1A 3A
-6
io = = - 0.3 mA
(8 + 12) 103
Solution. The given circuit can be further simplified
Considering only the current source and replacing by considering the current sources of 3 A and 1 A
the voltage source by short circuit, the equivalent as one current source of 2 A.
circuit is shown in the following figure. Considering the effect of voltage source and open
circuiting the current source, the resultant circuit
12 k is shown in the following figure.
12 k
4 mA 2
io i1
12 k 12 k 5V + 2.1


Now, Therefore,
2
n2 2 1 n 1
i1 =
5
= 1.22 A = = or 2 =
2 + 2.1 n1 8 4 n1 2
Considering the effect of only the current source Hence,
and short circuiting the voltage source, the resul- n1 = 2n2 = 2 40 = 80
tant circuit is shown in the following figure.
Ans. (c)
2 7. In the circuit shown in the following figure; the
value of load RL for maximum power transfer to
i2 it is
2.1 2A (a) 11 (b) 13
(c) 20 (d) 27
Ix
3 12
2 2.1
i2 = - = -1.024 A
+
2 + 2.1 12 V 12 2Ix RL
The total current is
i = i1 + i2 = 1.22 - 1.024 = 0.196 A
the power dissipated in the 2 resistor is Solution. Open circuiting the load resistor RL, the
equivalent circuit is shown in the following figure.
i2R = (0.196)2 2 = 76.8 mW
Ix
Ans. (c)
3 12 +
6. If the secondary winding of the ideal transformer
depicted in the circuit in the following figure has 40 +
12 V 12 Voc
turns, the number of turns in the primary winding for
maximum power transfer to the 2 resistor will be 2Ix

Ideal
8 transformer For the circuit shown above, we have
(V oc - 12) Voc (12 - Voc )
+ - 2I x = 0 and I x =
3 12 3
2
Vg 40
turns Solving both these two equations, we get
144
Voc = V
13
(a) 20 (b) 40 Short circuiting the load resistor RL, the equivalent
(c) 80 (d) 160 circuit is shown in the following figure.
Solution. Let n1 be the number of turns for the Ix

primary winding, n2 be the number of turns for
the secondary winding, ZL be the load resistance 3
and Zs be the source resistance. For the maximum
power transfer to the 2 resistor,
+ 12 2Ix
12 V Isc
ZL = 2
For a transformer,
Now,
2
n2 ZL
I x =
12
= =4A
n1 Zs 3

SOLVED EXAMPLES 43
I sc = I x + 2I x = 12 A Voc = 12 - Vx = 12 - 1 103I = 9 V
Thevenins equivalent resistance is Considering the load resistance RL as short circuit,

the equivalent circuit is shown in the following
Voc 12 figure.
RTH = =
I sc 13
1 k 1 k
The value of load resistor RL for maximum power
+
transfer is Vx
12
RL = 12 + = 12.92 13 + +
2Vx
13
12 V
Isc
Ans. (b)
8. For the network shown in the following figure,
the value of RL that will achieve maximum power
transfer is Vx = 12 V
(a) 1 k (b) 2 k
12 24
1 1 Isc = + = 36 mA
(c)
3
k (d)
4
k 1 10 3
1 103
Thevenins equivalent resistance is
1 k 1 k
Voc 9 1
+ RTH = = -
= k
Vx I sc 36 10 3 4
+ + Therefore, the load resistance value that lets maxi-

12 V RL 2Vx
mum power transfer is
1
k
4
Solution. Considering the load resistance RL as Ans. (d)
an open circuit, the equivalent circuit is shown in
the following figure. 9. For the network shown in Question 8, the maxi-
mum power that can be transferred to load resis-
1 k 1 k tance RL is
I
+ (a) 81 mW (b) 162 mW
Vx +
(c) 172 mW (d) 187 mW
2Vx
+ +
12 V
Voc Solution. The maximum transferred power is

1 92
mW = 81 mW
4 1/4
Applying Kirchhoffs voltage law to the outer loop,
we have Ans. (a)
10. In the following figure, the value of the resistance,
12 - 1 103I - 1 103I - 2Vx = 0
R, connected across the terminals, A and B, which
Also, will absorb the maximum power, is
Vx = 1 103I
3 k 4 k
Therefore,
I = 3 mA A B
V
Applying Kirchhoffs voltage law to the left loop, R
we get 6 k 4 k
12 - Vx - Voc = 0
(a) 4.00 k (b) 4.11 k
Solving the above equations, we get (c) 8.00 k (d) 9.00 k

Solution. Therefore,
RAB = RTH = R = (3 10 6 10 )3 3
R = 4 k
+ (4 10 4 10 )
3 3
Ans. (a)
1. The following figure shows a network. Find the

current flowing through resistor R (in Ampere). RTH = 8
a
5 4 a
i +
VTH = 40 V
+
50 V
20 R=2
b
The circuit given in the problem can be therefore

b redrawn as that given in the following figure.
Solution. The current can be found out using the

8 a
Thevenins theorem. The resistor R sees the circuit
shown in the following figure. i
5 4
a 40 V + 2

+
50 V

I 20 b
The current i through resistor R is given by

b
40
The Thevenins equivalent resistance is obtained i = =4 A
by replacing the voltage source by short-circuit. 8+2
Therefore, Ans. (4)
R TH = (5 20) + 4 = 8 2. For the circuit shown in the following figure, find

the voltage Vo (in volts).
The Thevenins equivalent voltage is given by
4 mA
VTH = 20I
Applying Kirchhoffs voltage law to the loop,
we get 6 k 4 k
50 - 5I - 20I = 0 +
+
12 V 3 k 2 k Vo
Therefore,
I=2A
and hence
Solution. The voltage Vo is the voltage across
VTH = 40 V the 2 k resistor. The voltage can be found using
Thevenins theorem. Removing the 2 k resistor,
The Thevenins equivalent circuit as seen by resis- the circuit looks like as shown in the following
tor R is shown in the following figure. figure.

SOLVED EXAMPLES 45
4 mA 6 k a
+
+
28 V

i1 i 2 k Vo
6 k 4 k
a
+ b
+
12 V i2 3 k
Voc
Therefore,
b
Vo = i 2 103
From the figure, 28
= 3
2 103 = 7 V
6 10 + 2 10
3
i1 = 4 mA.
Applying Kirchhoffs voltage law in the bottom Ans. (7)

loop, we get
12 - 6 103 (i2 - i1) - 3 103(i2) = 0
3. For the circuit shown in the following figure, in
the absence of the current source of 10 mA,
Substituting the value of i1 in the above equation the current ia is equal to 2 mA. The value of ia
and solving it, we get (in mA), when the current source of 10 mA is
attached, is
i2 = 4 mA
The voltage Voc can be found by using Kirchhoffs 10 mA

voltage law,
3 103i2 + 4 103i1 - Voc = 0

x 2 k y
Voc = 28 V +
10 k 18 k 5 mA

20 V
The Thevenins equivalent resistance can be found ia
by replacing the voltage source by short circuit and
the current source by open circuit as shown in the
following figure.
Solution. The total current ia can be found using
superposition theorem. The given current ia of
2 mA is that considering the effect of 20 V volt-
age source and 5 mA current source. Considering
6 k 4 k the effect of new current source of 10 mA and
a deactivating the other two sources, we get
the resultant circuit as shown in the following
figure.
3 k RTH
10 mA
b
2 k y y
Now, x
ia3
RTH = (6 103 3 103 ) + 4 103 = 6 k ia3
10 k 18 k 2 k 18 k
The Thevenins equivalent of the given circuit is 10 mA
shown in the following figure. x

The current ia3 is given by Applying Kirchhoffs voltage law, we get

2 103 10 2 - 3Vab2 - Vab2 = 0
ia3 = 10 10-3 = 1 mA
18 103 + 2 103

Therefore,
Therefore the total current is
ia = 2 mA + 1 mA = 3 mA Vab2 = 5 V
Ans. (3)
By applying superposition theorem, we get
4. What is the voltage Vab in volts for the circuit
shown in the following figure. Vab = Vab1 + Vab2 = 1 + 5 = 6 V
10 Ans. (6)
+ a 5. In the circuit shown the following figure, the power
+
3Vab dissipated in the resistor R is 1 W when only source
+ `1 is present and `2 is replaced by a short . The
4V 2A
Vab power dissipated in the same resistor R is 4 W
when only source `2 is present and source `1 is
replaced by a short. When both the sources `1 and
b
`2 are present, the power dissipated in R in watts,
Solution. The voltage Vab can be calculated using will be
the superposition theorem. Considering the effect
of only the voltage source of 4 V and open circuit- 1 2
ing the current source of 2 A, the resultant circuit
is shown in the following figure.
3Vab1
10 |V1|ejt V Source +
|V2|ejt V
R = 1
+ + `1
+ Source
`2
+ i=0
4V
Vab1
Solution. It is given that the power dissipated in
resistor R due to source 1 is
Applying Kirchhoffs voltage law, we get P1 = 1 W
4 - 10 0 - 3Vab1 - Vab1 = 0 and the power dissipated in resistor R due to source

Therefore, 2 is
Vab1 = 1 V
P2 = 4 W
Considering the effect of only the current source
of 2 A and short circuiting the voltage source of Since the polarity of both sources is different, the
4 V, the resultant circuit is shown in the following total power dissipated when both the sources are
figure. present is
3Vab2
10
+ P = ( P1 - P2 )2
+
2A = ( 1 - 4 )2
= (1 - 2)2
2A Vab2
=1 W

Ans. (1)

PRACTICE EXERCISE
1. Refer to circuit shown in the following figure. What i

a
value of voltage Vs delivers current I of 2 A?
(a) 2.1 V (b) 3.5 V
(c) 5.7 V (d) 6.2 V 12.5 10
(2 Marks)
Vs 5
1 2 + 30
120 V
c n
I =2A
1 1
1 15 20
+
Vs 1 1
1 b
(a) 7.5 (b) 12.5
(c) 9.6 (d) 13.5
3 0.5
(1 Mark)
5. Refer to the circuit shown in Question 4. The value
0.5 of current i is
2. If an impedance ZL is connected across a voltage (a) 12.46 A (b) 5.42 A

source V with source impedance Zs, then for maxi- (c) 11.53 A (d) 14.26 A
mum power transfer the load impedance must be (1 Mark)
equal to 6. For the network shown in the following figure, the
(a) source impedance Zs current supplied by the 40 V voltage source is
(b) complex conjugate of Zs (a) 1 A (b) 1.5 A (c) 0.5 A (d) 2.5 A
(c) real part of Zs (1 Mark)
(d) imaginary part of Zs
(1 Mark)
5
3. The value of the equivalent resistance between ter- 100 125
minals A-B of the circuit in the following figure is
Vs + 25
A
4 2
40 V
c e 40 37.5
d
2 3 1
7. For the network shown in Question 6, the power
3 delivered by the 40 V voltage source is
4
(a) 40 W (b) 60 W (c) 100 W (d) 20 W
(1 Mark)
8. Superposition theorem is NOT applicable to net-
B
works containing
(a) 1.51 (b) 2.21
(c) 4.61 (d) 6.74
(a) non-linear elements

(b) dependent voltage sources
(2 Marks)
(c) dependent current sources
4. Refer to the circuit shown in the following figure. (d) transformers
The value of resistance between the terminals a-b is (1 Mark)

9. For the circuit shown in the following figure, the What is the value of ZL in rectangular form that
value of current Io is will give the maximum value of average power
7 9 delivered to it
(a) mA (c) mA
5 5 3000 j4000 a
12 16
(c) mA (d) - mA
5 5
(2 Marks)
6 k + ZL
100 V RMS

6 k
b
12 V + 6 k 6 mA k

Io (a) 3535.5 - j3535.5 (b) 3535.5 + j3535.5
(c) 5000 - j5000 (d) 5000 + j5000
10. The superposition theorem is essentially based on (1 Mark)
the concept of 15. For the data given in Question 14, the maximum
(a) duality (b) linearity average power delivered to ZL is
(c) reciprocity (d) non-linearity (a) 5.1 mW (b) 8.2 mW
(1 Mark) (c) 3.4 mW (d) 9.1 mW
11. A load, ZL = RL + jXL is to be matched, using an (1 Mark)
ideal transformer, to a generator of internal imped- 16. For the circuit shown in the following figure, it is
ance, Zs = Rs + jXs . The turns ratio of the trans- given that the maximum power delivered to the
former required is load (RL) is 3 mW. The value of R is
(a) ZL /Zs (b) RL /Rs R
(c) RL /Zs (d) ZL /Rs R a

(1 Mark) R
12. For the circuit shown in the following figure, the RL
1V + 2V + 3V +
value of load impedance ZL that leads to maximum
average power being transferred to it is
1
(a) 3 + 4j (b) b
3 + 4j
1 (a) 0.3 k (b) 2 k (c) 1 k (d) 2.5 k
(c) (d) 3 - 4j (2 Marks)
3 - 4j
(1 Mark) 17. For the circuit shown in Question 16, the value of
RL is
j4 a
(a) 0.3 k (b) 2 k (c) 1 k (d) 2.5 k
(1 Mark)
18. The following figures (a) and (b) show two circuits.
40A RMS 3 ZL For the circuits to be equivalent the value of Is is
+
b + +
Ia
Is 3V
13. For the circuit shown in Question 12, the maxi- R V 2 9Ia V
mum average power being transferred to the load is
(a) 10 W (b) 15 W (c) 12 W (d) 18 W
(1 Mark) N1 N2
14. The following figure shows a circuit. A load imped- (a) (b)
ance ZL having a constant phase angle of -45 is (a) 5 A (b) 10 A (c) 15 A (d) 20 A
connected across the load terminals in the circuit. (2 Marks)

19. For the two circuits shown in Question 18 to be 22. For the circuit shown in Question 21, the Nortons
equivalent, the value of R is equivalent current and the Nortons equivalent
(a) 1 (b) 0.5 (c) 0.7 (d) 0.2
resistance, respectively, are
(1 Mark) (a) 1.05418.43, j150
(b) 1.054108.43, 150
20. For the circuit shown in the following figure, the
(c) 0.85418.43, j150
current through the 10 resistor is
(d) 0.854108.43, 150
P (1 Mark)
23. In the circuit shown in the following figure, the
5 12 4 value of the load resistor RL which maximizes the
10
power delivered to it is
10 1H
+ 22 V + 48 V 12 V
+
Em cos 10t
Q RL
(a) 853 mA (b) 764 mA
(c) 267 mA (d) 912 mA
(2 Marks)
(a) 14.14 (b) 10
21. For the circuit shown in the following figure, the (c) 200 (d) 28.28
Thevenins equivalent voltage and the Thevenins (1 Mark)
equivalent impedance, respectively, are
(a) 158.11108.43, j150 value of current through the load resistance of 2
(b) 158.11108.43, 150 across terminals A-B is
(c) 128.11108.43, j150
(d) 128.11108.43, 150 (a) 1.23 A (b) 1.38 A
(2 Marks) (c) 0.45 A (d) 0.93 A
j300 (2 Marks)
E 2 C A
200 j100
2 2
a I1 4 I2
1000 10090
+ +
8V 4V
b
F D B
1. What is the value of R (in ohms) required for maxi- 5 4

mum power transfer for the network shown in the
following figure?
(1 Mark)
+
20 3A R
25 V

2. In the circuit shown in the following figure, when 5. Use the data of the linear and reciprocal networks
switch S1 is closed, the ideal ammeter M1 reads 5 in following figures. Find the current i (in amperes)
A. What will the ideal voltmeter M2 read (in volts) in the circuit shown in figure (b).
when S1 is kept open? (1 Mark)
(2 Marks)
R2 R2
M2
V R1 R3 R1 R3
4 3 +
R4 i=? R4
10 V 2A 20 V

S1
6 A M1
(a) (b)
10
8 5 6. For the circuit shown in the following figure, what
is the Thevenins equivalent voltage (in volts)
across the terminals a-b?
2 3 (1 Mark)
3. For the circuit shown in the following figure, find 4 2

the value of voltage v2 (in volts). + a
(2 Marks) +
2i i
v1 15 v2
+
12 V 4 Voc
i
7
2A 5 4i

+ b
3V

7. For the circuit shown in Question 6, what is the
Thevenins equivalent resistance (in ohms) across
4. For the circuit shown in Question 3, find the value terminals a-b?
of voltage v1 (in volts). (1 Mark)
1. (d) The problem can be solved using delta-Wye The values of different resistors are
transformation. Converting the two delta networks 3 1
a-c-d and e-f-g into equivalent Wye-networks as R ao = = 0. 6
5
shown in the following figure:
11
= 0. 2
1 2
I=2A R co =
a b 5
3 1
R do = = 0. 6
1 1
o
5
3 1
c d R eo = = 0. 6
1
+ 5

Vs
1 1 3 1
1 R go =
5
= 0. 6
e f
11
o = 0.2
3 0.5
R fo =
5
Therefore, the given circuit can be redrawn as
g 0.5 h shown in the following figure.

Now,
1
I=2
a
24
RcB = 2 + 4 + = 8.66
0.6
3
34
ReB = 3 + 4 + = 13
0.2 0.6 2
o 23
c d Rce = 2 + 3 + + = 6.5
+ 4
Vs 1 1
Converting the delta network connected between
A-c-e into Wye-network, we get
e f
o 42
0.6 0.2 RAo = = 0.64
4 + 2 + 6.5
0.6 4 6.5
Rco = = 2.08
4 + 2 + 6.5
g 6. 5 2
Reo = = 1.04
4 + 2 + 6.5
Using the serialparallel combination formula, cir-
cuit shown in the above figure can be further sim- and the equivalent circuit is shown in the following
plified to that shown in the following figure. figure.
I=2 A
2.08
c 0.64 e
1.04
3.1
+
Vs
8.66
0
3 13 1
Therefore,
B
Vs = I 3.1 = 2 3.1 = 6.2 V
2. (b) According to maximum power transfer theo- The circuit shown in the above figure can be fur-
rem, for the maximum power transfer to the load ther simplified to that shown in the following figure
impedance, the load impedance should be complex using seriesparallel connection of resistors.
conjugate of the source impedance.
A
3. (b) Convert the Wye-network between terminals
c-e-B with common node d into delta network as
2.08
shown in the following figure. c 0.64 e
1.04
A
4 2
0
2.23 0.93
c e
6.5
8.66
3 13 1 B
Therefore, the equivalent resistance between ter-
minals A-B is
B (2.23 + 2.08) (1.04 + 0.93) + 0.64 = 2.21

4. (c) Converting the Wye-network comprising 5 , 5

10 and 20 resistors into delta-network, we get
R1
the equivalent circuit as shown in the following
figure, where 50
Vs +
10 12.5
10 20 + 20 5 + 5 10 40 V
Ra = = 35 R3 R2
10
10 20 + 20 5 + 5 10
Rb = = 17.5
20 40 37.5
10 20 + 20 5 + 5 10
Rc = = 70
5
where
a 100 125
R1 = = 50
Rb 250
125 25
12.5 R2 = = 12.5
17.5 250
100 25
Rc = 10
30
R3 =
70 250
35
15
The resistance across the 40 V supply is
Ra 50 50
R = 55 + = 80
b 100
Therefore, the given circuit finally simplifies to
On further simplifying, we get the equivalent cir- that shown in the following figure.
cuit as shown in the following figure.
i
a
Vs +
40 V 80
7.292
21
10.5 Therefore, the current delivered to the load is

b 40
= 0. 5 A
80
Therefore,
7. (d) The power delivered is
Rab = (7.292 + 10.5) 21 = 9.6
(Vs )2 =
(40) 2
= 20 W
5. (a) The value of current i is obtained as follows: R 80
8. (a) The superposition theorem is applicable for

V 120
i= s = = 12.46 A linear networks only.
Rab 9.63
9. (d) The current Io can be found using superpo-
6. (c) Replacing the upper delta network (100 , 125 sition theorem. Considering only the current
and 25 ) with its equivalent Wye network, we source of 6 mA and replacing voltage source of
get the equivalent circuit as shown in the following 12 V by short circuit, the equivalent circuit is
figure. shown in the following figure.

Therefore,
6 k n2 ZL
=
n1 ZS
6 k 6 k 6 mA k
I 12. (d) The problem can be solved using Thevenins
theorem. To find the Thevenins equivalent volt-
age (VTH), disconnect the load impedance ZL.
The current io is given as Therefore,
VTH = 40 3 = 120 (RMS)

(6 103 || 6 103 ) + 6 103
I o = -6 10-3 3
{(6 10 || 6 10 ) + 6 10 } + 6 10
3 3 3 The Thevenins equivalent impedance (ZTH) is
found by deactivating all the independent sources
18
=- mA as shown in the following figure.
5
j4
Considering only the voltage source of 12 V and
a
open-circuiting the current source of 6 mA, the
3
I 6 k 6 k
+ 12 V 6 k k
b
Io
The Thevenins equivalent impedance
The current I is given by ZTH = 3 + j4

12 From maximum power transfer theorem, the
I=
{(6 10 + 6 10 ) || (6 103 )} + 6 103
3 3
load impedance ZL is complex conjugate of ZTH.

Therefore,
ZL = 3 - j4
6
= mA
5
Now, 13.(c) The Thenvenins equivalent circuit for maxi-
mum power transfer is shown in the following
I (6 103 ) figure.
I o =
2
= mA
12 10 + 6 10
3 3 5
ZTH = 3 + j4
The current Io is obtained as follows:
-18 2 -16
I o + I o = + mA = mA
5 5 5 120 V RMS + ZL = 3 j4

10. (b) The concept of linearity is the base of the ITH
superposition theorem.
11. (a) The turns ratio is n2/n1, where n2 is the number
of turns in the secondary winding and n1 is the Now,
number of turns in the primary winding. For the 120
I TH(RMS) = = 20
transformer, 3 + j4 + 3 - j4
2 The maximum average power delivered to load
ZL n
= 2
Zs n1
2
P = I TH Real {ZL } = 4 3 = 12 W

14. (a) Given that the phase angle of ZL is -45. We a

know that for maximum power transfer, the mag-
nitude of the load impedance is equal to that of the R R R
impedance looking at the load impedance termi-
nals. Therefore, for the given circuit, + + +
1V 2V 3V

2 2
ZL = (3000) + (4000) = 5000
b
Therefore,
Applying Kirchhoffs voltage law to this circuit, we get
ZL = ZL - 45
VTH - 1 VTH - 2 VTH - 3
5000 5000
= -j R
+
R
+
R
=0
2 2
= 3535.5 - j3535.5 Solving the above equation, we get
VTH = 2 V
15. (b) The equivalent circuit with ZL = 3535.5
-j3535.5 is shown in the following figure. RTH is obtained by shorting all the voltage sources:
R
3000 j4000
RTH = (R R R) =
3
a Therefore, the maximum power transferred is
R jXL
22
100 V RMS 3535.53 = 3 10-3
4 (R / 3)
+ R

It ZL Therefore,
jX j3535.53 R = 1 k
b
17. (a) The resistance seen across the load resistance
terminals is
The RMS value of current It is given by
R
= 333
10 0 3
It =
(3000 + j4000) + (3535.5 - j3535.5) Therefore, RL = 333 . The nearest value in the
= 1.526 - 4.07 mA answers is 0.3 k.
The maximum power transferred is 18. (c) The current source in network N1 in figure (a)
is transformed into a voltage source as shown in
Pmax = I t2 RL the following figure:
= (1.526 10-3 )2 3535.5 I
= 8.2 mW +
R
+
16. (c) The maximum power delivered to the load in a IsR V
resistive network is
2
VTH
4RTH For the circuit shown in this figure, applying
where, VTH is the Thevenins equivalent voltage Kirchhoffs voltage law, we get
and RTH is the Thevenins equivalent resistance. V - IR - IsR = 0
VTH is calculated by open circuiting the load resis-
tance terminals. The following figure shows the cir- The networks shown in the given figure (b) and
cuit with load resistance terminals open circuited. this figure are identical. Therefore,

I = -10Ia j300
For the network shown in figure (b), applying x
Kirchhoffs voltage law, we get
V - 3 + 2Ia = 0 I1
a
Solving the above three equations, for network N2,
200 j100
1000
+
we get
I b
V - =3
5
For the networks shown in figure (a) and (b) to be
identical, the equations The current I1 is given by
I
V - IR - ISR = 0 and V - =3 1000 100
5 I1 = = A
-j300 + j100 -j200
should be the same. Therefore,
Now,
I
IR = and ISR = 3 Vab1 = I1( j100) = -500
5
Therefore, Considering the 10090 source and short circu-
iting the 1000 source, the equivalent circuit is
IS = 15 A
19. (d) Refer to the Solution of Question 18. Therefore,
j100
R = 0.2 y
20. (a) The problem can be solved using Millmans
theorem. The equivalent circuit is shown in the fol-
I2 a
lowing figure.
10090
+ j300
P 200 b
IL
R 10
The current I2 is given by
+
E 10090
I2 =
-j300 + j100
Q Now,
Here,
Vab2 = I2 (-j300) = j150 V
22(1/5) + 48(1/12) - 12(1/4)
E= = 10.13 V
(1/5) + (1/12) + (1/4) Also,
1 VTH = Vab1 + Vab2 = -50 + j150 = 158.11108.43

and R= = 1.88
(1/5) + (1/12) + (1/4) To find Thevenins equivalent impedance all the
Hence, active sources are deactivated. The equivalent cir-
cuit is shown in the following figure.
E 10.13
j300
IL = = = 853 mA
R + 10 1.88 + 10
21. (a) The Thevenins equivalent voltage can be found 200 j100 a
using the superposition theorem. It is the voltage
a
j100
Vab at the terminal a-b. Considering the 1000
j300
source and short circuiting the 10090 source, the b
b

Therefore, 24. (b) Applying Kirchhoffs voltage law to the left

loop, we get
ZTH = j100 -j300 = j150
-2I1 - 4(I1 - I2) + 8 = 0 or 3I1 - 2I2 = 4
22. (a) The Nortons equivalent current is
Applying Kirchhoffs voltage law to the right loop,
V TH 158.11108.43
IN = = = 1.05418.43 we get
ZTH 15090
-2I2 - 2I2 - 4 - 4(I2 - I1) = 0 or I1 - 2I2 = 1
The Nortons equivalent impedance is equal to the
Thevenins equivalent impedance. Therefore, Solving the above two equations, we get
ZN = ZTH = j150 I2 = 0.25 A
Therefore,
23. (a) The impedance of the inductor is
VAB = 4 + 2 0.25 = 4.5 V
wL = 10 1 = 10 The Thevenins equivalent resistance between ter-
Therefore, impedance looking into the load resis- minals A and B is obtained by shorting the voltage
tance is sources. Therefore,
Zs = 10 + j10
RTH = {( 2 4 + 2 ) 2} = 1.25
Then, RL for maximum power transfer is the com-
For the load resistance of 2 between terminals
plex conjugate of Zs. Therefore,
RL = 10 - j10 = 10 245 A and B, the current I through the load resistor is
Hence, 4.5
R L = 14.14 I = = 1.38 A
2 + 1.25

The voltage across the voltmeter is
1. For maximum power transfer, R should be equal
to Req of the circuit seen from the terminals after Voc = I sc RTH = 5 10 = 50 V
removing R. Deactivating the voltage and the cur- Ans. (50)
rent sources, the equivalent circuit is shown in the
3. By superposition theorem, the current i is given by
following figure.
5 4 7 3 7 + 15
i=2 + + 4i
7 + 15 + 5 7 + 15 + 5 7 + 15 + 5
17 88
20
= + i
27 27

17
Now, i=- A
Req = (5 20) + 4 = 4 + 4 = 8 61
Therefore, the value of load resistor R is 8 . The voltage v2 is given by
Ans. (8)
v2 = 5i = -1.4 V
2. When switch S1 is closed, the short circuit current is Ans. (-1.4)
Isc = 5 A 4. Refer to the Solution of Question 3 and the voltage
Thevenins equivalent resistance seen across the v1 is given by
v1 = v2 - (4i - i)15 = 11.15 V
terminals where switch S1 is connected is
RTH = [(4 6 + 2 8) + 3 + 3] 10 + 5 = 10 Ans. (11.15)

4 2
5. This is a reciprocal and linear network according 2i
a
to reciprocity theorem which states: Two loops +
A and B of a network N are reciprocal if an ideal
voltage source E in loop A produces a current I in i
loop B, then interchanging positions an identical
voltage source in loop B produces the same current
+
12 V i1 4 i2 Voc

I in loop A.
Since the network is linear, the principle of homo-
geneity holds and so when volt source is doubled,
b
current also doubles with opposite direction.
Therefore, Applying Kirchhoffs voltage law to the two loops,
we get
i = -4 A
Ans. (-4) 12 - 4i1 + 2i - 4(i1 - i2) = 0
6. Applying Kirchhoffs voltage law to the loop, we and 2i2 - 4(i2 - i1) = 0
get Also,
12 - 4i + 2i - 4i = 0 i = i1 - i2
Therefore, Solving the above equations, we get
i=2A 12
i2 = I sc = A
Now, 7
VTH = Voc = 2 4 = 8 V Therefore,
Ans. (8) V 87
RTH = TH = = 4.67
7. We short-circuit the terminals a-b, to find short- I sc 12
circuit current Isc as shown in the following figure. Ans. (4.67)
1. A source of angular frequency 1 rad/s has a source 100

impedance consisting of 1 resistance in series
with 1 H inductance. The load that will obtain the
maximum power transfer is
(a) 1 resistance. +
(b) 1 resistance in parallel with 1 H inductance.
10 V RL
(c) 1 resistance in series with 1 F capacitor.
(d) 1 resistance in parallel with 1 F capacitor.
(GATE 2003: 1 Mark)
(a) 1 W (b) 10 W
Solution. For the maximum power, the load resis- (c) 0.25 W (d) 0.5 W
tance is a complex conjugate of the source resis-
tance. Here, the source resistance Solution. For maximum power transfer,
Z s = 1 + 1j RL = RS = 100
Therefore, the load resistance ZL = 1 - 1j , which

The voltage V across RL is
is also the resistance of 1 resistance in series with 10 100
1 F capacitor. V = =5 V
100 + 100
Ans. (c)
The maximum power transferred to RL is
2. The maximum power that can be transferred to
the load resistor RL from the voltage source in the V2 55
Pmax = = = 0.25 W
circuit shown in the following figure is RL 100
(GATE 2003: 1 Mark) Ans. (c)

3. For the circuit shown in the following figure Solution. It is given that the source impedance is
Thevenins equivalent voltage and Thevenins
Zs = Rs + jXs
equivalent resistance at terminals a-b is
From maximum power transfer theorem, the maxi-
5
1A
mum power is transferred to the load impedance
when it is a complex conjugate of the source imped-
ance, that is,
a I1
+
5
+ ZL = Zs* = Rs - jXs
0.5I1
10 V
b Ans. (d)
Thevenin voltage and resistance looking into X-Y
(a) 5 V and 2 (b) 7.5 V and 2.5 are
(c) 4 V and 2 (d) 3 V and 2.5
1
(GATE 2005: 2 Marks) X
i
Solution. To calculate Thevenins equivalent
1 2
2i +
voltage VTH, applying Kirchhoffs current law at 2A
terminal a, we get
Vab Vab - 10 Y
+ =1
5 5
4 2
(When current source is in series with voltage (a) V, 2 (b) 4 V,
3 3
source effect of current source is taken.). Solving
4 2
the above equation, we get (c) V, (d) 4 V, 2
3 3
Vab = 7.5 V (GATE 2007: 2 Marks)
To calculate the Thevenins equivalent resistance,
Solution. Let VTH be the Thevenins equivalent
RTH, short circuit the independent voltage source
voltage across X-Y. Applying Kirchhoffs current
and open circuit the independent current source as
law at node X, we get
VTH VTH V TH - 2i
2= + +
a 5 2 1 1
where
VTH
i=
10 5 1
Therefore,
1 1 1 2
b 2 = VTH + + -
2 1 1 1
Therefore, Hence,
RTH = 5 5 = 2.5 VTH = 4 V
Ans. (b) From the figure, the short-circuit current is
4. An independent voltage source in series with an
I sc = 2 A
impedance Zs = Rs + jXs delivers a maximum
average power to a load impedance ZL when Therefore,
(a) ZL = Rs + jXs (b) ZL = Rs VTH 4
RTH = = =2
(c) ZL = jXs (d) ZL = Rs - jXs I sc 2
(GATE 2007: 1 Mark) Ans. (d)

6. The Thevenin equivalent impedance ZTH between Solution. The circuit given in the problem can be
the nodes P and Q in the circuit shown in the fol- replaced by the figure shown below after applying
lowing figure is 1 V source to the load terminals and short circuit-
1H 1F ing the voltage source of 100 V.
Vx 4 I1
+
P
1
1A 1
4 4 I
+
10 V Q
+ (I I1)
Vx + 1V
1
(a) 1 (b) 1 + s +
s
2
(c) 2 + s +
1
(d) 2
s + s+1 Req = 1
I
s s + 2s + 1
For the maximum power transfer,
Solution. The figure given below shows the equiva- RL = Req
lent circuit of the network given in the problem, with Applying Kirchhoffs voltage law to the outer loop,
the circuit elements being replaced by their imped- we get
ances and the independent sources being deactivated.
1 = 4I1 + Vx
P
1/s Also,
s Vx = 4(I - I1)
1 1 From the above two equations, we get
1
I= A
4
Q Therefore,
Therefore, the Thevenins equivalent resistance 1
Req = =4
between P and Q is given by I
1 (s + 1)[1 + (1/s)] Ans. (c)
ZTH = (s + 1) 1 + =
s (s + 1) + 1 + (1/s) 8. In the circuit shown in the following figure, the
2 Norton equivalent current in amperes with respect
(s + 1) /s
= =1 to the terminals P and Q is
(s + 1)(s + 1)/s
Ans. (a) j30
7. In the circuit shown in the following figure, what P
value of RL maximizes the power delivered to RL?
Vx 4 160A 25 j50
+
4 4 Q
+ 15
+ Vx
Vt 100 V RL (a) 6.4 - j4.8 (b) 6.56 - j7.87
(c) 10 + j0 (d) 16 + j0
8 (GATE 2011: 1 Mark)

(a) 2.4 (b)
3
Solution. The Norton equivalent current is
(c) 4 (d) 6
obtained by short circuiting the terminals PQ as
(GATE 2009: 2 Marks) shown in the circuit depicted in the following figure.

Isc Isc P 10. The impedance looking into nodes 1 and 2 in the
circuit shown in the following figure is
j30 ib
160A 25 j50 1 k 99 ib
15 9
Q 1
100
The short circuit current is 2
I sc =
25
16 0 =
25
16 0 (a) 50 (b) 100
15 + j30 + 25 40 + j30 (c) 5 k (d) 10.1 k
(25 16)0
= 8 - 36.86
(GATE 2012: 1 Mark)
=
50 36.86
Solution. To find the Thevenins equivalent
Hence, the Norton current is impedance across nodes 1 and 2, connect a 1V
I N = I sc = 8 - 36.86 source and find the current through the voltage
= (6.4 - j4.8) A source as shown in the following figure.
Ans. (a) ib
9. In the circuit shown below, the value of RL such
that the power transferred to RL is maximum is 1 k 99 ib
10 10
9 k
1
10 100 k
+ 2
5V 1A RL
+
2V
+
(a) 5 (b) 10 1
(c) 15 (d) 20
ib ia iTH
(GATE 2011: 1 Mark)
(9+ 1) k 100 99ib V =1 V
Solution. For maximum power transfer,
RL = RTH
To calculate RTH, short circuit the voltage sources 2
and open circuit the current sources as depicted in Thevenins impedance is
the following figure.
1
ZTH =
I
10 10
10 By applying Kirchhoffs current law at node 1, we
oc get
sc sc ib - ia + 99ib = iTH
RTH
Therefore,
Therefore,
100ib - ia = iTH
RTH = 10 + 10 10 = 15
By applying Kirchhoffs voltage law to the outer
Ans. (c) loop, we get

10 103 ib = 1 So, the power delivered to circuit B by circuit A is
7 7
2
P = i2R + i1 3 = R + - 3 j 3
Therefore,
2 + R 2+R
ib = 10-4 A
Applying Kirchhoffs voltage law in the first loop, P

For P to be maximum will be zero. Therefore,
we get R
10 103ib = -100 ia P 7
2
98R 21
=
- - =0
R 2+R (2 + R)3
(2 + R)2
Therefore,
ia = -100 ib
49(2 + R) - 98R - 21(2 + R) = 0
Substituting the value of ia in the expression,
Therefore,
100ib - ia = iTH
56
R= = 0.8
we get 70
Ans. (a)
100ib + 100ia = iTH
12. A source vs (t) = V cos 100t has an internal
Therefore, impedance of (4 + j3) . If a purely resistive load
iTH = 200ib = 200 10-4 = 0.02 A
connected to this source has to extract the max-
imum power out of the source, its value (in )
Hence, should be
1 1 (a) 3 (b) 4
ZTH = = = 50
iTH 0.02 (c) 5 (d) 7
(GATE 2013: 1 Mark)
Ans. (c)
11. Assuming that both voltage sources are in phase, Solution. For the pure resistive load (RL) to
the value of R for which maximum power is trans- extract the maximum power,
ferred from circuit A to circuit B (see the following
figure) is RL = Rs2 + Xs2 = 42 + 32 = 5
2 R Ans. (c)
13. In the circuit shown in the following figure, if
+ + the source voltage Vs = 10053.13V , then the
10 V j1 3V Thevenins equivalent voltage (in volts) as seen by
the load resistance RL is
Circuit A Circuit B (a) 10090 (b) 8000

(c) 80090 (d) 10060
(a) 0.8 (b) 1.4 (GATE 2013: 2 Marks)
(c) 2 (d) 2.8
3 j4 j6 3
Solution. The current through R is +

VL1 RL =10
10 - 3 7 i1 +
j40i2
+
10VL1 i2
i= = A Vs
2+R 2+R
The current through 3 V source is
3
i1 = i - = i - 3j Solution. To find VTH, open circuit the load resis-
-j1 tance RL. Then, i2 = 0.

V ( j4) 100 53.13 (a) k2 (b) k

VL1 = s = 490 = 80 90
3 + j4 553.13 1
(c) (d) k
k
VTH = 10 VL1 + i2 j6 + i2 3 (GATE 2013: 1 Mark)
= 10 80 90 + 0 j6 + 0 3
Solution.
= 800 90
Rb Rc
Ans. (c) RA =
Ra + Rb + Rc
14. Consider a delta connection of resistors and its After scaling,
equivalent star connection as shown below. If all
elements of the delta connection are scaled by a Ra = kRa , Rb = kRb and Rc = kRc
factor k, k > 0, the elements of the corresponding
After scaling, the new value of RA is
star equivalent will be scaled by a factor of
kRb kRc kRb Rc
RA = =
kRa + kRb + kRc (Ra + Rb + Rc )
Ra RC RB Therefore,
RA = kRA
Rb Rc RA
Similarly, RB = kRB and RC = kRC
Ans. (b)

CHAPTER 4
STEADY-STATE SINUSOIDAL ANALYSIS
This chapter discusses the steady-state response of circuits driven by sinusoidal sources both in time domain as well as
frequency domain. The response in frequency domain is described in terms of phasors.
4.1 INTRODUCTION where V is the amplitude of the waveform, is the

phase angle of the waveform at t = 0 and w is the
angular frequency of the waveform. The frequency
The waveform shown in Fig. 4.1 is a sinusoidal wave- f and the time-period T of the waveform can be
form represented by the equation expressed as
v(t) = V sin(wt + f ) (4.1)
1 w
f= = (4.2)
v(t) T 2p
V
When these sinusoidal waveforms are applied to network
w t (rad) elements including resistors, capacitors and inductors
f 0 p 2p or their combination they respond depending upon the
V parameters of the waveform and their characteristics.
Figure 4.1| Sinusoidal waveform.

This chapter discusses the response of circuits to these
sinusoidal sources.

64 Chapter 4: Steady-State Sinusoidal Analysis
4.2 SINOSOIDAL STEADY-STATE 4.2.2 Series RC Steady-State Sinusoidal

RESPONSE IN TIME DOMAIN Response
For a series RC circuit shown in Fig. 4.2(a), the current

4.2.1 Element Steady-State Sinusoidal Response and voltage relationship for a sinusoidal current input
i(t) is shown in Fig. 4.2(b).
Table 4.1 lists the response of a resistor, an inductor
and a capacitor when sinusoidal input voltages v(t) = + +
Vsinwt and v(t) = Vcoswt are applied to them. R vR(t)

Table 4.1|Element response to sinusoidal input voltage.
i(t) + v(t)
C vC(t)
v(t) = Vsinwt v(t) = Vcoswt
iR(t) (a)
+
sin w t cos w t
v(t) R V V

iR (t) = iR (t) = v(t)
R R V
I
+ iL(t) V V t
iL (t) =
wL
sin iL (t) =
wL
cos q
v(t) L
(w t 90) (w t 90) i(t)
(b)
iC(t) iC (t) = w CV sin iC (t) = w CV cos
v(t)
+
C (w + 90) (w + 90) Figure 4.2| (a) Series RC circuit. (b) Series RC circuit
sinusoidal response.
If a current i(t) = Isinwt is applied at the input, the

voltage response is
Table 4.2 shows the response of the elements when sinu-
soidal input current i(t) = Isinwt and i(t) = Icoswt is 1
2
v(t) = I R 2 + sin(w t q ) (4.3)
wC
applied to them.
Table 4.2|Element response to sinusoidal input current.

where
1
i(t) = Isinwt i(t) = Icoswt q = tan1
w CR
i(t)
Therefore, the voltage lags the current by an angle q. It
+ vR (t) = RI sin w t vR (t) = RI cos w t may be mentioned here that q 0 for (1/wC) << R
vR(t) R
and q 90 for (1/wC) >> R.
If a voltage v(t) = Vsinwt is applied at the input, the
i(t) vL(t) = w LI sin vL(t) = w LI cos current response is
+
vL(t) L (w t + 90) (w t + 90)
i(t) =
V
sin(w t + q ) (4.4)
R + (1 / w C )2
2
i(t) I I
+ vC(t) = sin vC(t) = cos
wC wC
vC(t) C where

(w 90) (w t - 90) 1
q = tan1
w CR
From Tables 4.1 and 4.2, we can see that in a resistor,
the current and voltage are in phase, in a capacitor, the Therefore, the current leads the voltage by an angle q.
current leads the voltage by 90 and in an inductor, the It may be mentioned here that q 0 for (1/wC) << R
voltage leads the current by 90. and q 90 for (1/wC) >> R.

4.4IMPEDANCE AND ADMITTANCE PARAMETERS IN FREQUENCY DOMAIN 65
4.2.3 Series RL Steady-State Sinusoidal 4.3 PHASORS

Response
For a series RL circuit shown in Fig. 4.3(a), the current A sinusoidal signal f = Asin(wt + q ) can also be written as
and voltage relationship for a sinusoidal current input f = Aq . When written in this form, the function is called
i(t) is shown in Fig. 4.3(b). a phasor with magnitude A and phase q. A phasor rotating
in counterclockwise direction at a constant angular velocity
w is shown in Fig. 4.4. It produces a projection on the hori-
+ + zontal axis which is a cosine function. In nutshell, phasor is
R a vector, whose length is the amplitude of the cosine func-
vR(t)
i(t) v(t) tion and angle is the angle of the cosine function.
+
vL(t) 3 2

(a)

V
1
I v(t)
t
q i(t)
0
(b) 1
Figure 4.3| (a) Series RL circuit. (b) Series RL circuit
sinusoidal response. 2
/2
3
If a current i(t) = Isinwt is applied at the input, the
4
voltage response is
3/2
u(t) = I R 2 + (wL)2 sin(w t + q ) (4.5)
where
2
1 wL
q = tan t
R
Figure 4.4| Rotating phasor.
Therefore, the voltage leads the current by an angle q.
It may be mentioned here that q 0 for wL << R and
4.4 IMPEDANCE AND ADMITTANCE
q 90 for wL >> R.
PARAMETERS IN FREQUENCY
If a voltage v(t) = Vsinwt is applied at the input, the
DOMAIN
current response is

sin(w t q )
V
i(t) = (4.6) V to phasor current I is
The ratio of phasor voltage
R 2 + (wL)2 referred to as impedance Z . Therefore,

V
Z=
where
(4.7)
wL I
q = tan1
R The impedance angle q is the angle by which the voltage
leads the current and is given by
Therefore, the current lags the voltage by an angle q. It

V f
may be mentioned here that q 0 for wL << R and Zq = = (f y )
V
(4.8)
q 90 for wL >> R. Iy I

Table 4.3| Phasor relations for different circuits.
Frequency Domain Circuit

Phasor Diagram
Impedance Form Admittance Form
I Z R() Y G(s)
w f =y

Current and voltage in phase; q = 0 Z = R0 Y = G0
V
R
Z Y G jBL
q
w f y jXL
I

Z = R 2 + XL2 q Y = G2 + BL2 -q
Current lags voltage; 0 < q < 90
I V
q
R
Z Y G
y jXC
jBC
f
w

Current leads voltage; -90 < q < 0 Z = R 2 + XC2 -q Y = G2 + BC2 + q

The angle q is positive for series RL circuit and negative If n impedances Z 1, Z 2, ..., Z nare connected in series,
for series RC circuit. then the equivalent impedance Z eq is obtained by phasor
Table 4.3 shows the phasor relationships between cur- addition as given in Eq. (4.9):
rents and voltages for different circuits.
Z eq = Z 1 + Z 2 + + Z n (4.9)
Figure 4.5 shows the impedance diagram. Impedance Z 1

is in the first quadrant; therefore, it exhibits inductive If n impedances Z 1 , Z 2 , , Z n are connected in parallel,
reactance and Z 2 is in the fourth quadrant and therefore then the equivalent impedance Z eq is obtained by phasor
series
it exhibits capacitive reactance. The equivalent Z mathematics as given in Eq. (4.10):
is obtained by vector addition of Z 1 and Z 2 as shown in
1 1 1 1
Fig. (4.5). = + + + (4.10)
Z eq Z1 Z 2 Zn
jX() Z1

Admittance ( Y ) is the reciprocal of the impedance (Z ).

1
Y = =
1
Z= Z1+Z2 -q (4.11)
q1
Z Z

Figure 4.6 shows the admittance diagram. Admittance
q2 R ()

Y 1 is in the first quadrant; therefore, it exhibits capaci-
tive susceptance and Y 2 is in the fourth quadrant and
Z2 therefore it
exhibits inductive suspectance. The
parallel

equivalent Y is obtained by vector addition of Y 1 and Y 2
Figure 4.5| Impedance diagram. as shown in Fig. (4.6).

SOLVED EXAMPLES 67
1 1 1 1
= + + +
jB(s) (4.12)
Y1
Y eq Y 1 Y2 Yn

Y = Y1+ Y2

If n admittances Y 1, Y 2, ..., Y n are connected in paral-
lel, then the equivalent admittance Y eq is obtained by
q1
phasor addition as given in Eq. (4.13).

q2 G(s) Y eq = Y 1 + Y 2 + + Y n (4.13)
Y2 It may be mentioned here that the impedances in series

divide the total voltage in the ratio of the impedances
Figure 4.6| Admittance diagram. and impedances in parallel divide the total current in

the inverse ratio of impedances or in direct ratio of
If n admittances Y1, Y2, ..., Yn are
connected in series, admittances.
then the equivalent admittance Yeq is obtained by
phasor mathematics as given in Eq. (4.12).
IMPORTANT FORMULAS

Zeq = Z1 + Z2 + + Zn
1. Series RC steady-state sinusoidal response:
2
1
u(t) = I R 2 + sin (w t - q ) or
5. If n impedances Z 1 , Z 2, ..., Z n are connected in
wC parallel, then
1 1 1 1
= + + +
sin(w t + q )
V
i(t) = Z eq Z1 Z2 Zn
R 2 + (1 / w C )2

2. Series RL steady-state sinusoidal response: 6. Admittance ( Y ) is the reciprocal of the impedance (Z):

1 1
u(t) = I R 2 + (wL)2 sin(w t + q ) or Y = = q
Z Z

sin(w t - q )
V 7. If n admittances Y 1, Y 2, ..., Y n are connected in
i(t) =
R 2 + (wL)2 series, then
1 1 1 1
3. Impedance: = + + +

V V f
Yeq Y1 Y2

Yn
Z = and Zq = = (f - y )
V
Iy
8. If n admittances Y 1, Y 2, ..., Y n are connected in
I I
parallel, then
4. If n impedances Z1 , Z 2 , , Z n are connected in
series, then Y eq = Y1 + Y1 + + Yn
SOLVED EXAMPLES

1. For the circuit shown in the following figure, if w = (a) 35.44 cos(500t + 58.93) V
500 rad/s and iL(t) = 2.540, the value of vs(t) is (b) 35.44 cos(500t + 28.93) V
(c) 12.24 cos(500t + 58.93) V
+2530 (d) 12.24 (500t + 28.93) V
+ iL(t)
+ 10 V Solution. The impedance of the inductor is
vs(t) 25
ZL = jwL = j 500 0.02 = j10
20 mH


It is given that the current flowing through the Therefore, the current through the diagonal element
inductor is (1F capacitor) is zero.
Ans. (a)
iL(t) = 2.540
3. The following figure shows a network. The value of
Therefore, the voltage across the inductor is impedance Zin for w = 800 rad/s is
vL(t) = (2.540) (j10) = 25130 2mF

As the 25 resistor is in parallel with the induc-
tor, same voltage appears across its terminals. The a
current through the 25 resistor is therefore equal to
25130 300 600 0.6 H
iR(t) = = 1130
25
Therefore, the current flowing through the voltage b
source vs(t) and the 10 resistor is
(a) (587.6 - j119.79) (b) (587.6 + j119.79)
i = 2.540 + 1130 = 2.6961.80
(c) (478 + j175.55) (d) (478 - j175.55)
Applying Kirchhoffs voltage law to the left loop,
we get
Solution. For w = 800 rad/s, the impedance of 2F
vs(t) = 10 2.6961.80 + 25-30 +
capacitor = -j625 and that of 0.6H inductor = j480.
25130
Therefore,
= 35.4458.93
300(-j625) 600( j480)
Zin = +
orvs(t) = 35.44 cos(500t + 58.93) V 300 - j625 600 + j480
= (478 + j175.55)
Ans. (a)
2. The value of current through the 1 Farad capaci-
Ans. (c)
tor in the circuit shown in the following figure (in
Amperes) is 4. For the network in Question 3, the value of imped-
ance Zin for w = 1600 rad/s is
0.5 F
1 1 2 (a) (587.6 - j119.79) (b) ( 587.6 + j119.79 )
1F
(c) (478 + j175.55) (d) (478 - j175.55)
1
2sin100 t
1 1H
Solution. For w = 1600 rad/s, the impedance of
0.5 F
2 mF capacitor = -j312.5 and that of 0.6 H induc-
(a) zero (b) one tor = j960. Therefore,
(c) two (d) three
300(-j312.5) 600( j960)
Zin = +
Solution. The given circuit is a bridge circuit and 300 - j312.5 600 + j960
can be redrawn as shown in the following figure.
= (587.6 + j119.79)
Ans. (b)
1 (1+ 2s )
if a voltage source vs(t) = 120 cos 800t V is con-
2sin 100 t
(2+s) nected to terminals a-b, then the current flow-
1F ing through the 300 resistance in the left-right
direction is
1 (1+ 2s )
(a) 564 cos (800t) mA
The product of impedances of opposite arms are equal: (b) 45.7 cos (800t - 2.78) mA
2 2 (c) 212.4 cos (800t - 45.82) mA

1 1 + = 1 1 +
s s (d) 312.5 cos (800t - 29.43) mA

SOLVED EXAMPLES 69
2mF i(t) i1(t) i2(t)
cos t
R2
Em
a R1
C
300 600 0.6H
b =0
I2
(a) =
Solution. It is given that w = 800 rad/s. Therefore,
E =Em0
the impedance of 2 F capacitor is equal to -j625
Em Em
and that of 0.6 H inductor is equal to j480. Therefore, 2R2 2R2
300(-j625) 600( j480)

Zin = + Em =0 E =Em0
300 - j625 600 + j480
(b) 2R2
= (478 + j175.55)
Em
Therefore, the current supplied by the voltage 2R2 I2
source vs(t) is
=
120
is (t) = A
478 + j175.55 I2
=0 =
Therefore, the current through the 300 resistor is
(c)
-j625
E =Em0
120
i300 (t) = A Em Em Em
478 + j175.55 300 - j625 2R2 2R2 2R2
= 0.2124 - 45.82
= 212.4 cos(800t - 45.82) mA
Em =0 E =Em0
Ans. (c) (d) 2R2
6. The current, i(t), through a 20 resistor in Em
series with an inductance, is given by i(t) = 3 + 4 2R2
sin(100t+45) + 4sin(300t+60) A. The rms Em I2
value of the current and the power dissipated in 2R2
the circuit are:
=
(a) 41 A, 410 W, respectively

(b) 35 A, 350 W, respectively Solution. We know that
(c) 5 A, 250 W, respectively jw C
i2 (t) = Em 0
1 + jw CR2
(d) 11 A, 1210 W, respectively
Solution. The rms value of the current is That is,

Em 0 w C90
2 2 i2 (t) =
I rms
4
= 32 +
4
+ = 5A 1 + w 2C 2R22 tan-1 w CR2
2 2
Em w C
The power is dissipated only in the 20 resistor. = 90 - tan-1 w CR2
The rms value of the power dissipated is 1 + w C R2
2 2 2
2
Prms = I rms R = (5)2 20 = 250 W At w = 0, i2 (t) = 0 and at w = ,
Ans. (c) Em
i2 (t) =
7. When the angular frequency w of the circuit shown R2
in the following figure is varied from 0 to , the Hence, the figure shown in option (a) satisfies both
locus of the current phasor i2(t) is given by conditions. Ans. (a)

1. A network comprises of two admittances Y1 = 3 Solution. We will determine the Thevenins equiv-
+ j4 mS and Y2 = 5 + j3 mS in parallel and an alent circuit without the load ZL. The open circuit
admittance Y3 = 2 - j4 mS in series with the voltage Voc can be determined from the equivalent
parallel combination. It is given that a current of circuit shown in the following figure.
0.130A flows through Y1, then what is the mag-
nitude of voltage (in volts) across Y1? j1
Solution. The voltage across the admittance Y1 1 1 I

is equal to the current across Y1/Y1, which is
R+
expressed as V +
+
120 V + V oc
0.130
= 20 - 23.13 V 60 V
(3 + j4) 10-3
The current I is given by
Therefore, the magnitude of voltage is 20V.
Ans. (20) (120 - (-60)) 18
I= = A
2. For the data given in Question 1, what is the magni- 1- j 1- j
tude of voltage (in volts) across the entire network?
Using Kirchhoffs voltage law, we get
Solution. The voltage across admittance Y2 is equal Voc = 1I - 60
to the voltage across admittance Y1. Therefore, the
current through admittance Y2 is expressed as 12 + 6 j
= V
1- j
Y2V2 = (5 + j3) 10-3 20-23.13 = 9.4971.56
= 0.108-1.3286A The Thevenins equivalent resistance can be calcu-
Therefore, the current through admittance Y3 is lated by looking into the open-circuit terminals with
all the sources made inactive, that is, replacing the
0.130 + 0.108-1.3286 = 0.213.74A voltage sources by short circuit and current sources
Therefore, the voltage across admittance Y3 is by open circuit as shown in the following figure.
I3
=
0.213.74
= 44.7277.18 j1
Y3 (2 - j4) 10 3
1 1
The voltage across the entire network is equal to
the following:
ZTH
Voltage across admittance Y2
+ Voltage across admittance Y3
That is, (1)(-j) -j 1 1
ZTH = = = -j
20-23.13 + 44.7277.18 = 45.6051.62 1- j 1- j 2 2
Therefore, the magnitude of the voltage across the For the maximum power transfer,
entire network 45.60V.
Ans. (45.6) 1 1
ZL = ZTH * = +j
2 2
what is the value of maximum power transferred Therefore, the given network is reduced to one
to load (in W)? shown in the following figure.
j1
I
1 j 1
1 1 2 2 1
9.49 71.56 V
+ 2

120 V
+ + ZL +j 1
2
60 V

The current I is given by The maximum power transferred to the load is
9.4971.56 PL = 1/2(9.49)2(1/2) = 90W

I= = 9.4971.56A
(1/2) - j(1/2) + (1/2) + j(1/2) Ans. (90)
PRACTICE EXERCISE

1. What is the value of Z1 in the network shown in VR
the following figure? (Given that I = 31.524.0A
V
and V = 50.060.0).
+
I 4.0
V Z1 10 VC
j3.0 (b)

(a) 2.0 - j2.0 (b) 5.0 + j5.0
(a) equal to the resonance frequency
(c) 5.0 - j5.0 (d) 2.0 + j2.0
(b) less than the resonance frequency
(c) greater than the resonance frequency
(2 Marks)
(d) not zero
2. For the circuit shown in the following figure, the (2 Marks)
value of voltage V1 is
(a) 25.78-70.48 V (b) 31.41-87.18 V current ic is [Given that ir = 15cos(5000t-30)]
(c) 25.7870.48 V (d) 31.4187.18 V
+ + ir ic
+
10
1045 V vr vc
V1 1 2 V2 100 F
4
30 A j3 j6 12
(a) 15cos(5000t) A
(b) 35cos(5000t) A
(c) 75cos(5000t+60) A
(2 Marks)
(d) 25cos(5000t-30) A
3. For the circuit shown in Question 2, the value of (2 Marks)
voltage V2 is
6. In the circuit shown in the following figure, A1,
(a) 25.78-70.48 V (b) 31.41-87.18 V A2 and A3 are ideal ammeters. If A1 reads 5 A, A2
(c) 25.7870.48 V (d) 31.4187.18 V reads 12 A, then A3 should read
(1 Mark)
R
4. For the series RLC circuit shown in the following A1
figure (a), the partial phasor diagram at a certain
frequency is a shown in the following figure (b). A3
The operating frequency of the circuit is C
A2
+ +
+
VR VL +
V
VC 100 sin t
(a) 7 A (b) 12 A
(c) 13 A (d) 17 A
(a) (1 Mark)

7. A series LCR circuit consisting of R = 10, XL = 20 (a) is greater than Vin

and XC = 20 is connected across an AC supply of (b) is equal to Vin
200 V rms. The rms voltage across the capacitor is (c) is less than Vin
(d) depends upon the value of Vin
(a) 200-90 V (b) 200+90 V (2 Marks)
(c) 400+90 V (d) 400-90 V

(1 Mark) 12. For the circuit shown in the figure of Question 11,
the phase of Vout is
phasor voltage VAB is (a) same as Vin
(b) leading that of Vin
(c) lagging behind Vin
Y (d) depends upon the value of Vin
10 I2 j2
(1 Mark)
1845 I1 A B 13. For the circuit shown in the following figure, the
value of vout(t) for vin(t) = 10sin10t is
20 j6
X
10 F
(a) 11.659.9 (b) 16.812.1
(c) 16.812.1 (d) 11.6-59.9
(2 Mark) 10 H
10 k Va
9. A DC voltage source is connected across a series
RLC circuit. Under steady-state conditions, the +
applied DC voltage drops entirely across the Vb +
+ vout(t) 10
(a) R only (b) L only vin(t)
(c) C only (d) R and L combination
(1 Mark)
(a) 101.01 sin(10t - 90) V
voltage across resistor R is
(Given that R = 1 ) (b) 101.01sin(10t) mV
(c) 101.01 sin(10t - 90) mV
10 10 mH 5 (d) 101.01sin(10t) V
(2 .Marks)
+
v(t) 50 F R
14. For the circuit shown in Question 13, the value of
8745 vout(t) for vin(t) = 10sin100t is
(a) 10 sin (100t - 90) V (b) 10 sin (100t) mV
(a) 5.439-45 (b) 4.367-5 (c) zero (d) Infinity
(c) 1.67423 (d) 7.65987 (1 Mark)
(1 Mark) 15. In the circuit shown in the following figure, assume
that the diodes are ideal and the meter is an aver-
age indicating ammeter. The ammeter will read
magnitude of Vout is
+ A
j1000 D1
D2
1 k Va 4sin(t)V 10 k
+ 10 k
Vb +
V in + V out 10

(a) 0.4 2 mA (b) 0.4 mA
0.8 0.4
(c) mA (d) mA
p p
(1 Mark)

16. The parallel RLC circuit shown in the following 20. For the network in Question 18, the voltage phasor
figure is in resonance. In this circuit, diagram is
IC 2.03 V VR
IR IL
VL 115 9.08 V
1mA rms R L 90
C 25
(a) 10 V
VS
(a) IR < 1 mA (b) IR + I L > 1 mA 65
(c) IR + IC < 1 mA (d) I L + IC > 1 mA

(1 Mark)
VC
17. Consider a DC voltage source connected to a series 6.26 V
RC circuit. When the steady-state reaches, the ratio
of the energy stored in the capacitor to the total 3.03 V VR
energy supplied by the voltage source, is equal to VL 125 9.08 V
90
(a) 0.362 (b) 0.500
35
(c) 0.632 (d) 1.000 (b) 10 V
(1 Mark) VS
18. For the network shown in the following figure, the 55
voltage across the capacitor is
R
VC
Vs 75 7.26 V
XL
100 V XC 25 3.03 V VR
VL 115 9.08 V
90
60 25
10 V
(a) 7.26-65 V (b) 7.26-55 V VS
(c)
(c) 6.26-65 V (d) 6.26-55 V 65
(2 Marks)
19. For the network in Question 18, the voltage across
the inductor is VC
(a) 3.03125 V (b) 3.03115 V 7.26 V
(c) 2.03115 V (d) 2.03125 V (d) None of these
(1 Mark) (2 Marks)
1. For the network shown in the following figure, find the 3. For the circuit shown in the following figure, find the
magnitude (in ohms) of impedance of the network. magnitude (in volts) of the voltage across the capacitor.
Z1
R XL XC R1 XL Z2
VS 100 100 50
1.0 k 500
VS R2 XC
(2 Marks) 1.0 k 500
500 V
2. For the network in Question 1, find the phase angle
(in degrees) of impedance.
(1 Mark) (2 Marks)

4. For the circuit in Question 3, the phase (in degrees) 7. Find the magnitude (rms value in volts) of the
of the voltage across the capacitor is voltage source for the network shown in the fol-
(1 Mark) lowing figure.
average power supplied by the current source (in 0.1 j0.5
watts) is
I1 + I2
Is 60 kW 40 kW
j1 j1
+
Vs 0.85 PF 2400 V rms 0.78 PF
+ 1 lagging lagging
100 V

230 A
(2 Marks)
(2 Marks) 8. What is the phase (in degree) of the voltage
6. For the network in Question 5, the average power source for the network shown in the figure of
supplied by the voltage source in watts is Question 7.
(1 Mark) (1 Mark)
1. (d) The admittance is Applying Kirchhoffs current law at the supernode,

we get
I 31.524.0 V V V
Y= = 3= 1 + 2 + 2
50.060.0 -j3 j6 12
V
= 0.630-36.0 or 36 = j4V1 + (1 - j2)V2
= 0.510 - j0.370S Solving the above two equations, we get
That is,
V1 = 25.78-70.48V
1 1
Y = 0.510 - j0.370 = Y1 + +
10 4. 0 + j 3 . 0 3. (b) Refer to the Solution of Question 2. Therefore,
Therefore,
V2 = 31.41-87.18V
Y1 = 0.354-45
4. (b) The given network is the series RLC circuit,
R is in phase
1 1
= 2.0 + j2.0 where the voltage across the resistor V
and Z1 = =
Y1 0.354 -45 with the series circuit current I R and I R is same in all
the elements. From the phasor diagram, we see
2. (a) Applying Kirchhoffs voltage law to the top
that the voltage across the resistor is leading the
loop, we get
voltage across the capacitor. Therefore, the current
V1 = V2 + 1045 is leading the voltage in the circuit. So, the given
circuit will behave as a capacitive circuit. Hence
The equivalent circuit of the given circuit is shown VC > VL. Therefore, XC > XL. Hence,
in the following figure.
> wL w2 <
1 1
or or w < wr
Supernode wC LC
V1 V2 where wr is the resonance frequency.
5. (c) For the parallel circuit shown in the given
figure, voltage across capacitor vc is equal to the
j3 j6 12
voltage across resistor vr. Therefore,
3A
vc = vr = Rir = 10(15.0 cos (5000t - 30)
= 150.0 cos (5000t - 30)

The current through the capacitor ic is Va - Vin Va - Vout

+ =0
dvc -j1000
= wCVcos(5000t - 30 + 90)
1000
C
dt Due to virtual earth,
= 75cos(5000t + 60) A
Va = Vb = 0
6. (c) The reading of the ammeter A3 is given by 12. (b) Refer to the Solution of Question 11. Therefore,
A32 = A12 + A22 Vout = jVin = Vin90
Therefore, 13. (c) Given that the input voltage
A32 = (5)2 + (12)2 vin(t) = 10 sin10t
Solving the above equation, we get Therefore,
A3 =13 A w = 10
Applying Kirchhoffs current law at inverting node
7. (d) Since XL = XC, the circuit is at resonance. The
of the opamp, we get
current across resistor R is given by
Va - vin (t) Va - vout (t) Va - vout (t)
+ + =0
- j10000
V 200
I= = = 20 A 10000 j100
R 10
Using the concept of virtual ground, we get
The voltage across the capacitor is given by Va = Vb = 0
VC = I(-jXC) = 20(-j20) = -j400 Solving the above equation, we get
Therefore, vout(t) = 101.01 sin(10t - 90) mV
VC = 400 -90 V 14. (d) Given that the input voltage
8. (d) By current division method, vin(t) = 10 sin 100t
Therefore,
I1 = 4.64120.1 A
w = 100
and I2 = 17.430.1 A
Applying Kirchhoffs current law at inverting node
Considering the path AXB, we get of the opamp, we get
VAB = VAX + VXB Va - vin (t ) Va - vout (t ) Va - vout (t )
+ + =0
10000 - j1000 j1000
= 20(I1) - (j6)I2
Using the concept of virtual ground, we get
= 92.8120.1 + 104.4-59.9
Va = Vb = 0
= 11.6-59.9
9. (c) For the DC voltage source, the inductor behaves 104
vout(t) = 90 =
0
as a short circuit and the capacitor behaves as
an open circuit. Therefore, under steady-state
conditions, the applied DC voltage drops entirely Please note that the LC combination forms a paral-
across the capacitor C only. lel resonant circuit and therefore the output goes
10. (a) Using current division method, the current to infinity.
across resistor R is given by 5.439-45. The volt- 15. (d) Diode D1 will conduct for the positive half cycle
age across the resistor R is of the input. The ammeter will read the following
average value:
1(5.439-45) = 5.439-45
Vm 1 4 1 0. 4
11. (b) Using nodal analysis at inverting terminal of = = mA
the opamp, we get p R p 10 10 3
p

16. (b) At resonance,

Z = (75)2 + (35)2 - tan-1 - = 82.8 -25
35
I = IR = 1 mA 75
Therefore, Therefore, the current I through the circuit is
IR + I L = IR2 + I L2
Vs 100
I= = = 12125 mA
Z 82.8 - 25
= 12 + I L2 > 1 mA
The voltage across the capacitor is
VC = IXC = (121 10-325)(60-90)

17. (b) The energy supplied by the voltage source is
Ws = CVs2 = 7.26-65 V
The energy stored in the capacitor is 19. (b) The voltage across the inductor is
1
WC = CVs2 VL = IXL = (121 10-325)(2590)
2
Therefore, = 3.03115 V
WC 20. (c) The voltages across the inductor and the capac-
= 0.5
Ws itor have been calculated in the earlier problems.
The voltage across the resistor is
18. (a) The total impedance of the circuit is
Z = R + jXL - jXC VR = IR = (121 10-325)(750)
= 75 + j25 - j60 = 9.0825 V
= (75 - j35)
Therefore, the phasor diagram shown in option (c)
The impedance Z in polar form is represents the correct diagram.
1. The admittance of the circuit is given by Z1 = 1000 + j500 = 111826.6

1 1 1 1
Y = = + + Let, Z2 be the impedance of parallel combination of
Z R 0 XL 90 XC - 90 R2 and XC. Therefore,
Z2= 447-63.4 = 200 - j400
1 1 1
= + +
100 0 100 90 50 - 90
Therefore, Therefore, the total impedance is
1 Ztot = Z1 + Z2 = 1200 + j100 = 12044.76

= 100 mS + 10 - 90 mS + 2090 mS
Z Now,
= (10 + j10) mS
Z 447-63.4
Therefore, VC = 2 Vs = 500
Ztot 12044.76
1 1
Z= = = 18.6-68.2 V
(10 + j10) mS (10 10 ) + (10 10-3 )2
- 3 2
Therefore, the magnitude is 18.6 V.
10 10-3
-tan-1
Ans. (18.6)
10 10-3 = 70.7 -45
4. Refer to the solution of Question 3. Therefore, the
Therefore, the magnitude is 70.7 . phase angle is -68.2.
Ans. (70.7) Ans. (68.2)
2. Refer to the solution of Question 1. Therefore, the 5. Since the series impedance of the inductor and the
phase angle is -45. capacitor are equal in magnitude and opposite in
Ans. (-45) sign, from the viewpoint of calculating the average
3. Let Z1 be the impedance of series combination of power, the network can be simplified to the one
R1 and XL shown in the following figure.

7. The magnitude of current I1 is

IVS
+ ICS P1 60000
I1 = = = 294.12 A rms
+ V1 1 VL (PF1 ) 240 0.85
100 V 230 A

The phase of the current I1 is
q I = -cos-1(0.85) = -31.79
1
The average power is given by
Therefore,
VI cos(q v - q i )
1
P = I1 = 294.12-31.79 A rms
2
The magnitude of current I2 is
For the current source,
P2 40000
I2 = = = 213.68 A rms
V = V1 = 10 V VL (PF2 ) 240 0.78
I = ICS = 2 A
The phase of the current I2 is
qv = 0
q I = - cos-1(0.78) = -38.74
qi = 30 2
Therefore, the average power delivered by the current Therefore, I2 = 213.68-38.74 A rms
source is Using Kirchhoffs current law, we get
(1/2)(10)(2)cos(-30) = 8.66 W
Is = I1 + I2 = 294.12-31.79 + 213.68-38.74
Ans. (8.66)
= 504.1-34.25 A rms
6. To calculate the average power delivered by the
voltage source, we need to calculate the current Therefore,
IVS. Using Kirchhoffs current law, we get
Vs = IS (0.1 + j0.5) + 2400
V
I VS + 230 = 1 = 100 = 460.1723.02 V rms
1
Therefore, the rms value of the voltage source is
Therefore, 460.17 V.
IVS = 8.33-6.9A Ans. (460.17)
The power delivered by the voltage source is
8. Refer to the Solution of Question 7. Therefore, the
PVS = 1/2(10)(8.33)cos[0 - (-6.9)] = 41.34 W phase angle is 23.02.
Ans. (41.34) Ans. (23.02)
1. A series RLC circuit has a resonance frequency of R

1 kHz and a quality factor Q = 100. If each of R, and BW =
L
L and C is doubled from its original value, the new
Q of the circuit is Therefore,
(a) 25 (b) 50
(c) 100 (d) 200 1 L
Q=
(GATE 2003: 1 Mark) R C
Solution. The quality factor is
When R, L and C are doubled,
f
Q= o
Q =
BW 1
Q = 50
1 2
where fo =
2p LC Ans. (b)

2. An input voltage u(t) = 10 2 cos(t + 10 ) + 10 5

Therefore,
cos(2t + 10 )V is applied to a series combination i(t) = sin 2t[3 + 4 j ] = 5 sin 2t tan-1
4
of resistance R = 1 and an inductance L = 1 H. 3
The resulting steady-state current i(t) in ampere is = 5 sin(2t + 53.1)
Ans. (a)
(a) 10cos(t + 55) + 10cos(2t + 10+ tan-1 2) 4. For the circuit shown in the following figure, the
3 time constant RC = 1 ms. The input voltage is
(b) 10 cos ( t + 55 ) + 10 cos(2t + 55) vi (t) = 2 sin 103 t . The output voltage vo(t) is
2
(c) 10cos(t - 35) + 10cos(2t + 10 - tan-1 2)
equal to
R
cos(2t - 35 )
3
(d) 10 cos ( t - 35 ) + 10
2 + +
vi(t) C vo(t)
Solution. For a series RL circuit,
u(t)
i(t) =
R + jwL
(a) sin(103t - 45) (b) sin(103t + 45)
For the given circuit, (c) sin(103t - 53) (d) sin(103t + 53)
10 2 cos(t + 10) 10 5 cos(2t + 10) (GATE 2004: 1 Mark)
i(t) = +
1 + 1j 1 + 2j
10 2 cos(t + 10) 10 5 cos(2t + 10) Solution.
=
245
+
5 tan-1 2 1/ jw C
vo (t) = v (t)
R + (1/ jw C ) i
Therefore,
1
2 sin 103 t
i(t) = 10 cos(t - 35) + 10 cos(2t + 10 - tan-1 2)
=
1 + jw CR
1
Ans. (c) = 2 sin 103 t
3. The circuit shown in the following figure, with 1 + j 103 10 -3
R = 1/3 , L = 1/4 H, C = 3 F, has the input volt- Therefore,
age v(t) = sin2t. The resulting current i(t) is
vo (t) = sin(103 t - 45)
i(t)
Ans. (a)
5. Consider the following statements S1 and S2:

v(t) R L C S1: At the resonant frequency, the impedance of a
series RLC circuit is zero.
S2: In a parallel GLC circuit, increasing the con-
ductance G results in increase in Q factor.
(a) 5sin(2t + 53.1) (b) 5sin(2t - 53.1)
(d) 25sin(2t - 53.1)
Which one of the following is correct?
(c) 25sin(2t + 53.1)
(a) S1 is False and S2 is True
(GATE 2004: 1 Mark)
(b) Both S1 and S2 are True
(c) S1 is True and S2 is False
Solution. For the circuit shown in the given figure,
(d) Both S1 and S2 are False
i(t) = v(t) Y (GATE 2004: 2 Marks)
Therefore,
Solution. For a series RLC circuit
1 1
i(t) = v(t) + + jw C
R jwL
1
Z = R + j wL -
wC
4
= sin 2t 3 + + j 2 3
2j At resonant frequency,

1
wL - wn =
1
=0 and
wC LC
Therefore Therefore,
Z = R (purely resistive)
x= or x =
R R C
Hence, at resonant frequency the impedance of a LC
2L 2 L
series RLC circuit is not zero. Therefore, the state-
ment S1 is not True. For a parallel GLC circuit, For no oscillations,
C x 1
Q=R Therefore,
L
Since R C L
1 or R 2
2 L C Ans. (c)
1
G=
R 7. In a series RLC circuit, R = 2 k, L = 1 H, and
we get C = 1/400 mF . The resonant frequency is
1
1 C (a) 2 104 Hz (b) 104 Hz
Q=
G L p
(c) 104 Hz (d) 2 104 Hz
Hence, as G increases, Q decreases if C and L are
same. Therefore, the statement S2 is also not True. (GATE 2005: 1 Mark)
Ans. (d)
Solution. The resonant frequency is
6. The condition on R, L and C such that the
step response y(t) in the following figure has no 1 1
fo = =
2p LC
oscillations, is
2p 1 (1/400) 10-6
L R
103 20 104
= = Hz
+ 2p p
+
Ans. (b)
u(t) C y(t)
instantaneous current i1(t) is
j2 j2
(a) R
1 L L +
(b) R
2 C C 50 A i1(t) 3 1060 A

(c) R 2
L L
(d) R =
C C
(GATE 2005: 1 Mark)
90 A - 90 A
10 3 10 3
(a) (b)
Solution. The transfer function of the circuit 2 2
(c) 560 A (d) 5 - 60 A
shown in the given figure is
Y (s) 1/sC (GATE 2005: 2 Mark)

=
U (s) R + sL + (1/sC )
1 Solution. When current source 5 0 A is acting
= 2 alone, and current source 1060 is open circuited
s LC + sCR + 1
1/LC i1 (t) = -50
= 2
s + (R/L)s + (1/LC ) When current source 10 60 A is acting alone, and
current source 5 0 A is open circuited
Now,
R i1(t) = 1060
2xw n =
L

Therefore, when both the current sources are (a) 8 VAR (b) 16 VAR
present, (c) 28 VAR (d) 32 VAR
i1(t) = 1060 - 50
= 5 + 8.66 j - 5 Solution. Let I be the current through the circuit.
= 8.66 j A Therefore,
Hence, 20 10
I= = = 2 - 36.87
8 + 6j 4 + 3j
10
i1(t) = 5 390 = 390 A
2 The reactive power is
Q = | I 2 | Real part of XL = 4 4 = 16 VAR

Ans. (a)
9. In the AC network shown in the following figure, Ans. (b)
the phasor voltage VAB (in volts) is
11. For a parallel RLC circuit, which one of the follow-
A ing statements is NOT correct?
(a) T he bandwidth of the circuit decreases if R is
5 5 increased
(b) The bandwidth of the circuit remains same if
530 A L is increased
j3 j3 (c) At resonance, input impedance is a real quantity
(d) At resonance, the magnitude of input impedance
attains its minimum value
B (GATE 2010: 1 Mark)
(a) 0 (b) 530 Solution. The characteristic equation for a parallel

(c) 12.530 (d) 1730
RLC circuit is
1 1
(GATE 2007: 2 Marks) s2 + s+ =0
RC LC
Solution. We know that where bandwidth is
VAB = Current Impedance 1

RC
That is,
It is clear that the bandwidth of a parallel RLC circuit
VAB = 530 (5 - 3 j) (5 + 3 j) is independent of L and decreases if R is increased. At
resonant frequency, imaginary part of input imped-
(5 - 3 j) (5 + 3 j)
= 530 ance is zero. Hence, at resonance input impedance is a
5 - 3j + 5 + 3j real quantity. In parallel RLC circuit, the admittance
25 + 9 is minimum at resonance. Hence magnitude of input
= 530 = 1730 V impedance attains its maximum value at resonance.
10
Ans. (d)
Ans. (d)
12. The current I in the circuit shown in the following
10. An AC source of rms voltage 20 V with internal figure is
impedance Zs = (1 + 2j) feeds a load of imped-
ance ZL = (7 + 4j) in the following figure. The
reactive power consumed by the load is 20 mH
50 F
200 V
=103 rad/s
I 1
Zs = (1+2j)
200 V + ZL = (7+ 4j) (a) -j1 A

(b) j1 A
(c) 0 A (d) 20 A

Solution. The circuit shown in the given figure is 1

redrawn as shown in the following figure (L = 20 R+
sC
mH, C = 50 H):
+
VA +
Vi(s) (R1/sC) Vo(s)

j L I(s)
Vin
1
200 V I 1
=103 rad/s j C From this figure, we have
1 R (1/sC )
Vi (s) = R + I (s) + I (s)
sC R + (1/sC )
1 + sCR R
VA - V in VA VA =
sC
I (s) +
1 + sCR
I (s)
+ + =0
jwL 1 1 / jwC Given that
Therefore, t
vi (t) = Vp cos
RC
+ 1 + j103 50 10-6
1
VA -3
j10 20 10
3
Therefore,
w=
1
20
=
j10 20 10-3
3 RC
Substituting w =
1
Solving the above equation, we get and s = jw in the expression
RC
for Vi(s), we get
VA = -j1 V
(1 + j)R R
Vi (s) = + I (s)
Also, j 1 + j
VA Therefore,
I=
1 Vi (s) 3R
=
Therefore, I (s) (1 + j)
I = -j1 A or I (s) =
Vi (s)
(1 + j)
3R
Ans. (a)
Now,
13. The circuit shown in the following figure is driven
by a sinusoidal input Vi = Vpcos(t/RC). The 1 R (1/sC )
Vo (s) = R I (s) = I (s)
steady output Vo is sC R + (1/sC )
R C Therefore,
+ R V (s)
+ Vo (s) = i (1 + j)
1 + sCR 3R
Vi R C Vo
=
R V i (s)
(1 + j)
1 + j 3R
V (s)
Vp Vp = i
t t 3
(a) cos (b) sin
3 RC 3 RC In time domain,
t
Vp t Vp t 1 Vp
(c) cos (d) sin vo (t) = vi (t) = cos
2 RC 2 RC 3 3 RC
(GATE 2011: 1 Mark) Ans. (a)
Solution. The following figure shows the circuit in 14. Two magnetically uncoupled inductive coils have Q
the given figure which is drawn in s-domain. factors q1 and q2 at the chosen operating frequency.

Their respective resistances are R1 and R2. When Therefore,

connected in series, their effective Q factor q at the
wL1 = q1R1 and wL2 = q2R2
same operating frequency is
1 1 The coils are connected in series; therefore,
(a) q1 + q2 (b) +
q1 q2 q R = wL1 + wL2 = q1R1 + q2R2
q1R1 + q2R2 q R + q2R1
(c) (d) 1 2 Therefore,
R1 + R2 R1 + R2
q1R1 + q2R2
(GATE 2013: 2 Marks) q=
R
Solution.
Since R = R1 + R2 , we get
wL1
q1 =
R1 q1R1 + q2R2
q=
wL2 R1 + R2
and q2 =
R2 Ans. (c)

CHAPTER 5
RLC CIRCUITS
This chapter discusses the time domain and frequency domain analysis of RLC circuits using linear constant coefficient
differential equations and Laplace transform, respectively.
5.1 TIME DOMAIN ANALYSIS OF RLC 5.1.2 Initially Charged Source-Free RC Circuit
CIRCUITS
Figure 5.1 shows an RC circuit. The capacitor has an
initial charge of Qo and the switch is closed at t = 0.
5.1.1 First-Order RC and RL Circuits
The first-order RC and RL circuits contain one capaci-

tor and one inductor, respectively. The response of such i
a circuit can be decomposed into natural response or the
+
forced response. The natural response is due to the initial C vC R vR
condition of the storage element. The forced response is +
the result of an externally applied input, Another way to
express the response is in terms of transient response and
Figure 5.1| Initially charged source-free RC circuit.

steady state response. The transient response of a circuit
is its temporary response that dies out with time. The
steady-state response is the behavior of a circuit a long
time after the external excitation or source is applied. Applying Kirchhoffs voltage law (KVL) to the loop,
The response of source-free RC and RL circuits and RL we get
and RC circuits with external source is discussed in the
following sections. vR + vC = 0

84 Chapter 5: RLC Circuits
Now, The initial energy stored in the capacitor is

dq Q2
vR = R Wo =
1
CVo2 = o (5.6)
dt 2 2C
q The transient energy stored in the capacitor is given by
and vC =
C
Cv = Wo e2t/RC
1 2
Substituting the values of vR and vC in the above equa- wC = (5.7)
2 C
tion and solving, we get
The energy dissipated in the resistor is
dq q
+
dt RC
=0 (5.1) wR = Wo WC = Wo (1 e2t /RC ) (5.8)
Equation (5.1) is a first-order homogeneous linear dif- The time constant of an RC circuit is given by
ferential equation. Solving the above equation, we get
= RC (5.9)
q = Qo et /RC (5.2)
is the time at which the function f given by f = Aet/
where q is the charge across the capacitor at any time t. is 36.8% of its initial value.
The voltage across the capacitor at any time t is
Q et /RC 5.1.3 Source-Free RL Circuit with Initial
= Vo et /RC
q
vC = = o (5.3) Current
C C
where, Vo is the initial voltage across the capacitor. Figure 5.3 shows an RL circuit with initial current Io. The
The voltage across the resistor at any time t is switch is at position 1 at t < 0 and is moved to position 2
vR = vC = Vo et /RC
at t = 0 and remains in that position thereafter.
(5.4)
The current through the circuit at any time t is 1
= o et/RC
vR V
i= (5.5)
R R 2
+
Figure 5.2(a), (b) and (c) show the curves for the charge
Io L vL
q versus time t, the capacitor voltage vC and resistor vR R
voltage vR versus time t and the current i versus time t,
i
+
respectively.
Figure 5.3| Source-free RL circuit with initial current.

q Vo
vC Applying KVL to the loop, we get
Qo
t vR + vL = 0
vR
Vo
Now,
t
vR = Ri
(a) (b) di
and vL = L
dt
i
Substituting the values of vR and vL in the above equa-
tion and solving, we get
0 t di R
+ i=0 (5.10)
dt L
Vo Equation (5.10) is a first-order homogeneous linear dif-
R ferential equation. Solving the above equation, we get
the current i in the circuit as given below
(c)
i = I o etR /L
Figure 5.2| Charge, voltage and current curves for
(5.11)
initially charged source-free RC circuit. The voltage across the inductor is

5.1 TIME DOMAIN ANALYSIS OF RLC CIRCUITS 85
vL = I o RetR/L (5.12) u(t to)

1
The voltage across the resistor is
vR = I o RetR /L (5.13)
The initial energy stored in the inductor is t

0 to
1
Wo = LI 2
2 o Figure 5.5| Delayed unit step function.
The transient energy stored in the inductor is given by It may be mentioned here that the unit step function and
2tR/L its delayed version can be used to represent an abrupt
wL = Wo e (5.14)
change in voltage or current.
The energy dissipated in the resistor is
5.1.4.3Unit Impulse Function
wR = Wo WL = Wo (1 e2tR/L ) (5.15)
The unit impulse function, which is also known as the
The time constant of an RL circuit is given by
delta function, is the differentiated output of the unit
t =
L step function and is defined as
(5.16)
+
0 t 0
R
As mentioned earlier, is the time at which the function
d (t) =
t = 0
and d (t)dt = 1 (5.19)

f given by f = Aet /t is 36.8% of its initial value.
Figure 5.6 shows the unit impulse function

5.1.4 Singularity Functions
(t)
The singularity functions are functions that are either
discontinuous or have discontinuous derivatives. In this
section, some of the singularity functions are discussed
for basic understanding of fundamental input waveforms.
0 t
5.1.4.1Unit Step Function
Figure 5.6| Unit impulse function.
The unit step function is given by Eq. (5.17) and is
shown in Fig. 5.4:
5.1.4.4Unit Ramp Function
0 t < 0
u(t) =
1 t 0
(5.17)
The unit ramp function is the integral of the unit step
u(t) function and is given by
0 t < to
1 r(t) =
t t to
(5.20)
Figure 5.7 shows the unit ramp function.
0 t
r(t)
Figure 5.4| Unit step function.
1
5.1.4.2Delayed Unit Step Function
The delayed unit step function is given by Eq. (5.18) and

is shown in Fig. 5.5:
0 t < to
0 1 t
u(t to ) =
1 t to
(5.18)
Figure 5.7| Unit ramp function.

5.1.5 Step Response of an RC Circuit v(t)

Consider the circuit shown in Fig. 5.8(a).The switch is Vs
initially open and is closed at time t = 0. In such a
case, the input is modeled as a step function. The step
response of a circuit is its behavior when the input cur-
rent or voltage excitation is a step function. The circuit
Vo
shown in Fig. 5.8(b) is an equivalent of the circuit shown
in Fig. 5.8(a).
0 t
Figure 5.9| RC circuit voltage waveform.

t=0
R R
The transient response is

+ +
Vs +
C v(t) Vsu(t) +
C v(t) vt (t) = (Vo Vs )et/RC = (Vo Vs )et/t (5.24)

The steady-state response is
vss = Vs (5.25)
(a) (b)
The complete response can also be expressed as
Figure 5.8| RC Circuit with source.
v(t) = v() + [v(0) v()]et /RC (5.26)
Let the initial voltage on the capacitor be Vo. As we +
where v(0) is the initial voltage at t = 0 and v() is the
know that the voltage across the capacitor cannot change final or the steady-state voltage.
instantaneously, Therefore,
v(0-) = v(0+) = Vo. 5.1.6 Step Response of an RL Circuit

Applying KVL, we get Consider the circuit shown in Fig. 5.10 (a).The switch is
dv(t) v(t) Vs u(t) initially open and is closed at time t = 0. In such a case, the
C + =0 input is modeled as a step function. The step response of
dt R
a circuit is its behavior when the input current or voltage
For t > 0, u(t) = 1. Therefore, the above equation can excitation is a step function. The circuit shown in Fig. 5.10
be simplified as (b) is an equivalent of the circuit shown in Fig. 5.10 (a).
dv(t) v(t) Vs dv(t) dt
= or =
dt RC v Vs RC R
i(t)
Integrating on both sides and introducing initial condi- t=0
tions, we get +
Vs + v(t)

L
for t < 0
Vo
v(t) = t / RC (5.21)
Vs + (Vo Vs )e for t 0
Figure 5.9 shows the waveform for voltage v(t). Equation (a)
(5.21) shows the total response of the RC circuit to a
sudden application of DC voltage, assuming that the R
capacitor is initially charged. The natural response com- i(t)
ponent of the response given in Eq. (5.21) is +
Vsu(t) +

L v(t)
vn (t) = Vo et/RC = Vo et/t (5.22)
where = RC is the time constant of the RC circuit. The

forced response is (b)
vf (t) = Vs (1 et/RC ) = Vs (1 et/t ) (5.23) Figure 5.10| RL circuit with source.

5.2 RESONANCE IN RLC CIRCUITS 87
The current through the circuit is where s1 and s2 are the roots of the equation
Io for t < 0 R 1
s2 + s +
L
=0
i(t) = Vs Vs tR /L LC
for t 0
(5.27)
R + I o R e
That is,
The current i(t) is shown in Fig. 5.11.
R
2
R 1
s1 = + = a + b
2L 2L LC
i(t)
R
2
Io R 1
and s2 = = a b (5.34)
2L 2L LC
where
Vs
R
a =
R
2L
1
wo =
0 t LC
b = a 2 w 02
Figure 5.11| Current through an RL circuit.
The circuit is overdamped when > wo and the current
The forced response is i(t) is given by
i(t) = eat (Ae bt + Bebt )
Vs
if (t) = (5.28)
R
The circuit is critically damped when = wo and the
The natural response is
current i(t) is given by
V
in (t) = I o s etR/L i(t) = eat (A + Bt)
R
(5.29)
The time constant of the circuit is The circuit is underdamped when < wo and current
i(t) is given by
t =
L
i(t) = eat (A cos b t + B sin b t)
(5.30)
R
The complete response can also be expressed as
i(t) = i() + [i(0) i()]et /t (5.31)
t=0 +
R vR
5.1.7 Series RLC Circuit
+
i(t) vL
Figure 5.12 shows a series RLC circuit. The differential L

equation of the circuit is of second order; therefore, its
solution contains two constants, which are determined +
C vC
by the initial conditions. Depending upon the relative
Figure 5.12| Series RLC circuit.
values of circuit parameters, the solution will be over-
damped, critically damped or underdamped. The equa-
tion of the circuit shown in Fig. 5.12 is given by
d 2 i(t) R di(t) 1 5.2 RESONANCE IN RLC CIRCUITS

2
+ + i(t) = 0 (5.32)
dt L dt LC
The above equation is a homogeneous differential equa- 5.2.1 RLC Series Circuit: Series Resonance
tion of the second order. The solution of this equation is
of the form Figure 5.13(a) shows a series RLC circuit. The circuit
i(t) = Ae s1t
+ Be s2 t under open-circuit condition has driving-point or input
(5.33)
impedance given by

1 5.2.2 RLC Parallel Circuit: Parallel Resonance

Zin (w ) = R + j wL (5.35)
wC
Figure 5.14 shows a parallel RLC circuit. The circuit
The circuit is said to be in series resonance when Zin(w) is under open-circuit condition has driving-point or input
real and the imaginary part of Zin(w) is zero. Therefore, admittance given by
at the resonant frequency wo,
Y in (w ) = + jw C
1 1 1
= + (5.39)
1 1 Zin (w ) R jwL
w o L w C = 0 or w o = (5.36)
o LC The circuit is said to be in parallel resonance when Zin(w)
or Yin(w) is real and the imaginary part of Zin(w) or
The net reactance at frequencies below the resonant fre- Yin(w) is zero. The impedance is maximum and admit-
quency is capacitive and the reactance above the reso- tance is minimum at the resonant frequency. Therefore,
nant frequency is inductive. Figure 5.13(b) shows the at the resonant frequency wo,
frequency response of the series RLC circuit shown in
1 1
Fig. 5.13(a). w o L + w C = 0 or w o = (5.40)
o LC
L C
I2=0
I1 I2
+ + +
I1 + +
v1 R v2
R L
+
v1 C v2

(a)
Zin(w)
Zin(w)
R Figure 5.14| Parallel RLC circuit.
+90
The quality factor or the figure-of-merit is defined as
w R C
wo Qo = = w o CR = R (5.41)
1 w oL L
90
wo w The bandwidth of the circuit is given by
wo
b = (5.42)
(b) Qo
Figure 5.13| (a) Series RLC circuit. (b) Frequency Therefore, higher the quality, narrower will be the
response of series RLC circuit.
bandwidth.
The quality factor or the figure-of-merit is defined as 5.3 LAPLACE TRANSFORM METHOD
Maximum energy stored FOR RLC CIRCUITS
Qo = 2p
Energy dissipted per cycle
w oL 1 1 L The solutions of RLC circuits can also be obtained using
= = = (5.37)
R w o CR R C Laplace transforms (s-domain solution). The basics of
Laplace transform are covered in the unit of signals and
systems. Here, we present the details relevant from the
The bandwidth of the circuit is given by
viewpoint of RLC circuits. Table 5.1 shows the time-
R wo domain and s-domain representation of the three basic
B= = (5.38) network elements namely R, L and C. Table 5.2 shows
L Qo
the Laplace transform pairs for some of the common
Therefore, higher the quality, narrower will be the waveforms and Table 5.3 shows the Laplace transforma-
bandwidth. tion table for various operations.

5.3 LAPLACE TRANSFORM METHOD FOR RLC CIRCUITS 89
Table 5.1| Time domain and s-domain representation of basic network elements.
Time Domain s-Domain s-Domain Voltage

Expression
i I(s)
RI (s)
R R
i i(0+) I(s)
L
+
sL I (s) Li(0+ )
sL
Li(0+)
i I(s)
L i(0+)
+
sL I (s) + Li(0+ )
sL
Li(0+)
i C I(s) 1/sC
+ + + I (s) Vo
+
+ Vo
sC s
Vo/s
i C I(s) 1/sC
+ + + I (s) Vo

Vo + Vo/s sC s
Table 5.2| Laplace transform of common waveforms Table 5.3| Laplace transform of different operations
f(t) F (s) = L f (t)

f(t) F (s) = Lf (t) = f (t)est dt
et0 s F (s)

f(t - t0)u(t - t0)
1
u(t)
d
s f (t) sF(s) - f(0+)
dt
eat 1
sa
t
f(t) dt
F (s)
w s 0 s
sinwt, coswt ,
s +w
2 2
s +w
2 2
F (s) f (1)(0+ )
sinhat, coshat +
a s s s
sinhat, coshat ,
s a
2 2
s a2
2
d
tf(t) F (s)
eatf(t) F(s + a) ds
F (s) ds
n! 1
tn f (t)
sn + 1 t s

Using the formulas given in Tables 5.1, 5.2 and 5.3, the the parameters determined can then be converted into
time-domain KVL, KCL and mesh equations can be con- time-domain.
verted into s-domain and can be solved. The values of
IMPORTANT FORMULAS
1. The voltage across a capacitor in an RC circuit is 5. The resonant frequency for a series and parallel
Vo for t < 0 RLC circuits is
v(t) = t / RC
Vs + (Vo Vs )e for t 0
wo =
1
2. The current through an inductor in an RL circuit is LC
Io for t < 0
6. For a series RLC circuit, the quality factor is
i(t) = Vs Vs tR /L
R + I o R e for t 0
w oL 1 1 L
Qo = = =
3. The time constant of an RC circuit is R w o CR R C
= RC
7. For a parallel RLC circuit, the quality factor is
4. The time constant of an RL is
t =
L R C
Qo = = w o CR = R
R w oL L
SOLVED EXAMPLES

1. A 10 resistor, a 1 H inductor and 1 F capaci- Solution. The impedance seen by the volt-
tor are connected in parallel. The combination is age source is the parallel impedance of the two
driven by a unit step current. Under the steady branches. Therefore,
state condition, the source current flows through: Z = (20 + 37.7 j) (10 53.1j) = 67.4 + 11.8 j
(a) the resistor (b) the inductor
The rms value of the current or the magnitude of
(c) the capacitor only (d) all the three elements
current I is
Solution. At steady state, the inductor behaves V 230 230
as a short circuit and the capacitor acts as an open I = = = = 3.36 A
Z 2 2 68.4
circuit. So, under steady-state condition for a par- (67.4) + (11.8)
allel combination of R, L and C, the source current Ans. (a)
flows through the inductor.
Ans. (b) 3. For the circuit in Question 2, the phase angle
between V and I is
magnitude of the current I is (a) 0 (b) 4.3
(c) 9.9 (d) 2.3
I
R1 20 W R2 10 W Solution. The voltage source V and the current I
can be written in polar form as follows:
V = 230 V
rms Vin = (230)e jwt and ZT = (68.4)e jf
X1 37.7j X2 53.1j
Therefore,
Im ZT 11.8
(a) 3.36 A (b) 2.14 A tan f = = = 0.175
(c) 6.73 A (d) 4.51 A Re ZT 67.4

SOLVED EXAMPLES 91
Therefore, R2
or V2 (s) = V (s)
= 9.9 R1 + R2 1
The current I can be written as For the impulse response,
230 j(wtf )
= 3.36e j(wt9.9)
v1(t) = (t)
I =
68.4
e
Therefore,
The real part of I is
V1(s) = 1
3.36cos(wt - 9.9)
Therefore,
Therefore, the current lags the voltage by 9.9. R2
Ans. (c) v2 (t) = d (t)
R1 + R2
4. For the compensated attenuator shown in the fol- Ans. (b)
lowing figure, the impulse response under the con- 5. A 2 nF capacitor having an initial charge of 5.1 C
dition R1C1 = R2C2 is is discharged through a 1.3 k resistor. The maxi-
mum current through the resistor is
R1 (a) 1.78 A (b) -1.78 A
+ + (c) 1.96 A (d) -1.96 A
C1 C R2
v1(t) 2 v2(t) Solution. The charge on the capacitor at time t
in an RC circuit with initial charge qo is given by

q = qo et /t
(a)
R2
[1 e1/R1C1 ]u(t) (b)
R2
d (t) where t = RC is the time constant and qo is the
R1 + R2 R1 + R2 initial charge. The current I at time t is given by
= [qo et/t ] = o et/t = o et/t

R2 R2 dq d q q
et /R1C1 u(t) I=
(c)
R1 + R2
u(t) (d)
R1 + R2 dt dt t RC
The maximum current occurs at t = 0. Therefore,
Solution. The impedance of parallel combination qo 5.1 106
I max = = = 1.96 A
1300 2 109
of R2 and C2 is RC
R2 (1/C2s) R2 Ans. (d)
Z2 (s) = =
R2 + (1/C2s) R2C2s + 1
6. For the data given in Question 5, the current
The impedance of parallel combination of R1 and through the resistor after 9000 ns is
C1 is
(a) -66.1 mA (b) -45.6 mA
R (1/C1s) R1 (c) 23.9 mA (d) None of these
Z1(s) = 1 =
R1 + (1/C1s) R1C1s + 1
Now, Solution. Referring to the Solution of Question 5,
it is clear that the current I at time t is given by
V2 (s) Z2 (s)
= qo t /t
V1(s) Z1(s) + Z2 (s) I = e
RC
Also, it is given that
Therefore, at t = 9000 ns, the current is
5.1 106
R1C1 = R2C2 9
/13002109 )
I = 9
e(900010
Therefore, 1300 2 10
V2 (s) R2/(R2C2s + 1) = 66.1 mA
=
V1(s) [R1/(R2C2 s + 1)] + [R2 /(R2C2 s + 1)] Ans. (a)
R2
= 7. For the data given in Question 5, the charge
R1 + R2 remaining on the capacitor after 8000 ns is

(a) 200 nC (b) 235 nC where = RC is the time constant and qo is the ini-
(c) 139 nC (d) None of these tial charge. Therefore, after 8000 ns, the charge is
Solution. The charge on the capacitor at time t in 9
/(13002109 )
an RC circuit with initial charge qo is given by q = (5.1 106 )e800010 = 235 nC
t /t
q = qo e Ans. (b)
4
1. If the Laplace transform of the voltage across a cap- vC(0) = 6 V
s+1
acitor of value of (1/2) F is Vc (s) = 3 .
s + s2 + s + 1
Find the value of the current (in ampere) through
+
the capacitor at t = 0+. + 2F vC

10 V
Solution. The impedance offered by a capacitor
of value C in s-domain is
1 2
Zc (s) = =
Cs s
Solution. The voltage across the capacitor does
The current through the capacitor C is not change instantaneously, Therefore,
I c (s) =
Vc (s)
=
s(s + 1)
=
s vC (0 ) = vC (0+ ) = 6 V
Zc (s) 2(s3 + s2 + s + 1) 2(s2 + 1)
So, at t = 0+, we have
+ 4
Therefore, value of i(0 ) is obtained as follows: vR = 10 - 6 = 4 V and iR (0+ ) = =1 A
4
i(0+ ) = lim sIC (s) = lim
s2
=
1
= 0. 5 A At t =, the capacitor acts as an open circuit.
s s 2
2(s + 1) 2+0 Therefore,
Ans. (0.5) iR() = 0 A
Also,
2. The flash unit of a camera produces flash by using the
energy stored in a capacitor C. Given that the value = RC = 4 2 = 8 s
of the capacitor is 750 F and the capacitor recharges The current through the circuit at any time t is
through a resistor R such that the RC time constant
is 3 s. Find the value of the resistor R (in k). i(t) = i() + [i(0+ ) i()]et /t
= 0 + (1 - 0)e-t/8 = e-t/8
Solution. The time constant of an RC circuit is
= RC The energy absorbed by 4 resistor in time 0 to
Therefore, is given by
t 3
R = = = 4 kW et / 4
C 750 106 E = [i(t)]2 Rdt = 4e dt = 4 e dt = 4
t / 4 t / 4
0 0 0
1 / 4
Ans. (4) 0

3. In the circuit shown in the following figure, what is = 16 et /4 = 16 J
the energy absorbed by the 4 resistor (in Joules)
0
in the time interval (0, )? Ans. (16)
PRACTICE EXERCISE

1. In an RLC circuit having R and L in series and C (a) t he impedance and current are maximum at the
in parallel to the series combination, resonant frequency

(b) the value of maximum impedance = L/RC (a) 1 W (b) 50 mW

(c) t he currents in the RL and C branches are 180 (c) 200 mW (d) None of these
phase-shifted with respect to each other (1 Mark)
(d) the resonant frequency fr is given by 8. For the circuit in Question 6, the initial energy
1 1 R2 stored in the capacitor is
fr = 2
2p LC L (a) 1 W (b) 5 mW
(1 Mark) (c) 200 mW (d) None of these
2. The voltages VC1, VC2 and VC3 across the capacitors (1 Mark)
in the circuit shown in the following figure, under 9. A series RC circuit (R = 1 k and C = 1 F)
steady state, are respectively, has zero initial charge on the capacitor. A constant
10 k 1H 2 F 2 H 25 k voltage source of 50 V is applied to the circuit at
+ t = 0. The voltage across the capacitor is expressed as
(a) 50 + 50e-1000t (b) 50 - 50-1000t
VC2
+ +
+ VC1 1 F VC3 3 F (c) 50 + 50e-t (d) 50
100 V 40 k
(2 Marks)
10. For the data discussed in Question 9, the voltage
across the resistor is
(a) 80 V, 32 V, 48 V (b) 80 V, 48 V, 32 V
(c) 20 V, 8 V, 12 V (d) 20 V, 12 V, 8V (a) 50e-1000t (b) 501000t (c) 50e-t (d) 50
(2 Marks) (1 Mark)
3. For a coil with inductance L having resistance R 11. The following figure shows a circuit. The switch
in series with capacitor C has the following imped- is initially open and then moved to position 1 at
ance at resonance frequency t = 0 and then moved to position 2 at t = 250 s.
(a) zero (b) R (c) L/RC (d) The current at t = 100 s is
(1 Mark)
(a) 15.7 mA (b) 40.2 mA
4. An inductor L having a reactance of 25 and a (c) 26.8 mA (d) None of these
resistance R gives off heat at 10 W when a current (2 Marks)
of 500 mA (rms) passes through it. The impedance
of the inductor is 2
1
(a) 41.5 (b) 42.7 (c) 45.7 (d) 40
(2 Marks) i 500
5. A ramp voltage, vi(t) = 100t V, is applied to +
20 V
an RC differentiating circuit with R = 5 k and C = +
4 F. The maximum output voltage is Qo 0.5 F

(a) 0.2 V (b) 2.0 V (c) 10.0 V (d) 50.0 V
(1 Mark)
6. For the circuit shown in the following figure, the 12. For the circuit in Question 11, the current at t =
switch is closed at t = 0. At t = 0-, the voltage 500 ms is
across the capacitor is 50 V. The current across the
resistor is given by (a) -38.7 mA (b) -15.6 mA
(c) 0 mA (d) None of these
(a) 0.125 A (b) 0.125e-2.5t (2 Marks)
(c) 0.125e-0.0016t (d) 0.125e-62.5t
(2 Marks) 13. In the circuit shown in the following figure, the
voltage v(t) is
1 1 1
i
+
vr(t) 400
+
vc(t) 4 F

+

eat v(t) 1H ebt

7. For the circuit in Question 6, the total energy dis-
sipated in the resistor is

(a) eat-ebt (b) eat+ebt (a) increasing Rl and decreasing R2

(c) aeat-bebt (d) aeat+bebt (b) decreasing Rl
(1 Mark) (c) increasing R2
(d) None of the above
14. For the circuit shown in the following figure, what (2 Marks)
value of is will lead to different values of voltages
v1 and v2? 17. The resonant frequency of the series circuit shown
in the following figure is
10 ix
M =1 H
+ v1
10 iy
+
10
is 10 v2 10
2H 2H 2F
(a) 1 A 1 1
(a) Hz (b) Hz
(b) 0.1 A 4p 3 4p
(c) Many values of is are possible
(d) Condition is impossible to achieve 1 1
(c) Hz (d) Hz
(1 Mark) 2p 10 4p 2
15. For the circuit in Question 14, if ix = 5 A, then the (2 Marks)
value of v1 is
18. In the series circuit shown in the following figure,
(a) 5 V (b) 25 V (c) 75 V (d) 50 V for series resonance, the value of the coupling coef-

(1 Mark) ficient k will be
16. The half-power bandwidth of the resonant circuit
k
shown in the following figure can be increased by
R1 18 j12 j2 j8
C R2
(a) 0.25 (b) 0.5
L
(c) 0.999 (d) 1.0
(2 Marks)

1. If the three-phase balanced source shown in the 3. For the circuit in the following figure, the voltage
following figure delivers 1500 W at a leading power Vo (in volts) is
factor 0.844, then find the magnitude of value of ZL (1 Mark)
(in ohms) approximately.
(2 Marks)
2 2
ZL ZL +

4V 2V
+
Three phase 400 V
balanced ZL 2 Vo
source +

switch was closed for a long time before opening at
2. For the three-phase balanced source of Question 1, t = 0. The voltage Vx (in volts) at t = 0+ is
the phase angle of value of ZL (in degrees) is
(1 Mark) (2 Marks)

t=0 6. For the circuit shown in the following figure, find

the value of current through the 8.4Hinductor
(in Amperes) at t = .
2.5 A (2 Marks)
20 8.4 H 10 H
5H i1 i2
t=0

+ 336 V i1(0 )=0 42
i2 (0 )=0 48

20 +
Vx
5. A series RLC circuit has a Q of 100 and an imped-
7. For the circuit in Question 6, find the value of
current through the 48 resistor (in amperes) at
ance of (100 + j0) at its resonant angular frequency
of 107 rad/s. Determine the value resistance R (in
t = .
kilo-ohm).
(1 Mark) (1 Mark)
1. (d) The resonant frequency fr of a RLC circuit 2

Pavg = I rms R
having R and L in series and C in parallel to the
series combination is given by Therefore,
1 1 R2
Pavg 10
= 40
fr = 2 R= =
2p
2
LC L I rms (0.5)2
The impedance is given by
2. (b) Under steady-state conditions, the inductor
behaves as a short circuit and capacitor behaves as Z = R 2 + XL2 = 402 + 252 = 42.7
an open circuit. The given circuit can be redrawn
as shown in the following figure.
5. (b) The output voltage is given by
10 k 2F 25 k
dvi (t)
+V vo (t) = RC
dt
C2
+ + + Therefore,
100 V VC1 40 k VC3 3F
vo (t) = (5 103 )(4 106 )
d
(100t) = 2 V
dt
6. (d) For t > 0, vr(t) = vc(t). Also,
40 10 3
vc(0+) = vc(0-) = 50 V
VC 1 = 100 = 80 V
10 10 + 40 10
3 3
3 and RC = 400 4 10-6 = 16 10-3.

VC 2 = 80 = 48 V
2+3 Therefore,
2
VC 3 = 80 = 32 V 1
=
1
= 62.5
2+3 RC 16 103
3. (b) The impedance of a coil with inductance L Now,
vc(t) = vc(0-)e-t/RC = 50e-62.5t
having resistance R in series with capacitor C has
impedance R at the resonant frequency.
4. (b) The average power dissipated through the Therefore,
resistance R is given by vr(t) = 50e-62.5t

Therefore, the current through the resistor is for 0 t 250 s

62.5t
= 0.125e62.5t
vr (t) 50e Since the switch is initially open, q(0) = 0 and the
i(t) = =
R 400 current at time t = 0+ is given by
7. (b) The power in the resistor is dq 20 V
i(0+ ) = = = 0.04 A
Pr (t) = vr (t)i(t) = 6.25e -125t dt t=0 + 500
The energy dissipated in the resistor is t = 500 0.5 10-6 = 250 10-6 s
t t i(0+ ) = a/t. Therefore,
125t 125t
wr (t) = Pr (t)dt = 6.25e dt = 0.05(1 e ) a = 0.04 250 106
0 0
= 10 106 C
The total energy dissipated in the resistor is for
t . Therefore, the total energy dissipated in the Also, b = -a. Therefore,
-6)
q = -10 10-6e-t/(250 10 + 10 10-6 C
resistor is
0.05 W = 50 mW = 10(1 - e-4000t) mC
8. (b) The initial energy stored in the capacitor is Therefore, the current for 0 t 250 s is given by
= 10 106 4000 e4000 t A

dq
C[vc (0 )]2
1 i=
wC (0) = dt
2
= 40e4000 t mA
= (4 106 )(50)2 = 5 mW
1
2 Therefore, for current at t = 100 s is 26.8 mA.
Therefore, all the stored energy in the capacitor is 12. (a) The charge across the capacitor as t is
q() = CV = (0.5 10-6) (-20) = -10 mC

dissipated by the resistor in the form of heat.
9. (b) The voltage across the capacitor does not
change instantaneously. Therefore, For t , the charge on the capacitor is given by
vc(0+) = vc(0-) = 0 q(t) = [q(t ) q()]e(tt )/t + q()

= (71.55e4000 t 10) mC
As t , the voltage across the capacitor is
The current i for t > is given by
vc() = 50 V
= 286.2e4000 t mA
dq
The time constant is i=
dt
RC = 1 103 1 10-6 = 10-3 s Therefore, the current i at t = 500 s is -38.7 mA.
The expression for the voltage across the capaci- 13. (d) Applying KCL at node (1), we get
tor is
L
1
eat + ebt = v(t)dt
vc(t) = [vc(0+) - vc()]e-t/RC + vc()
Taking the differential and solving for v(t), we get
Substituting the different values, we get
d at
-t/10-3 -1000t v(t) = L [e + ebt ] = aeat + bebt
vc(t) = [0 - 50)]e + 50 = 50 - 50e dt
10. (a) Refer to the Solution of Question 9 and apply- 14. (d) From the given circuit, we can see that volt-
ing KVL to the circuit, we get age v1 is always equal to voltage v2. Therefore,
the condition given in the problem is impossible
vc(t) + vr(t) = 50 to achieve.
Therefore, 15. (b)

v1 v
+ 1
vr(t) = 50e-1000t
ix =
10 10
11. (c) The charge across the capacitor is given by Solving the above equation, we get
q = ae-t/ + b v1 = 25 V

16. (a) For a resonant circuit, 1 1

w = = rad/s
Selectivity Q 22 2
1 Therefore,
and Bandwidth
1
Q 2pf =
2
where, Q is the quality factor.
1
Therefore, f = Hz
4p
1
Bandwidth 18. (a) At resonance,
Selectivity
If R1 0 and R2 , then the circuit will have XL- XC = 0
only L and C elements and it will have high selec- Therefore,
tivity. The half power bandwidth can be increased
by reducing the selectivity or in other words, the XL = XC
half power bandwidth can be increased by increas-
ing the series resistance R1 and decreasing the par- Hence,
allel resistance R2. XL = j12 or XL = j12
17. (b) The equivalent inductance is
The magnitude of inductive reactance is
Leq = L1 + L2 - 2M = 2 + 2 - 2(1) = 2 H XL = XL1 + XL2 + 2k XL1 XL2

At resonance,
Substituting the different values in the above
XL = XC
equation, we get
Therefore,
XL = j2 + j8 + 2k j2 j8 = j12
1
w =
Leq C Therefore,
Substituting the value of Leq and C in the expression, 2kj4 = j2 or k = 0.25

1. The power delivered by a three-phase balanced As the power factor is leading, load is capacitive so
source is angle will be negative. Therefore,
3VpIpcosq q = -32.44
Ans. (-32.44)
Therefore, 3. Since the diode is forward biased, it is taken as
3VpIpcosq = 1500 short circuit. Let the voltage at the 2 -2 -diode
junction be V. Applying KCL at the 2 -2 -diode
V V node, we get
or 3 L L cosq = 1500
3 3ZL V 4 V V +2
+ + =0
2 2 2
Hence, Therefore,
VL2 cos q 2
ZL = V = V
1500 3
4002 0.844 Now,
= = 90 2
1500 Vo = V = V = 0.66 V
Ans. (90) 3
Ans. (-0.66)
2. Refer to the Solution of Question 1. Also,
4. When switch was closed, circuit was in steady
q = cos-1(0.844) = 32.44 state, as shown in the following figure.

6. The equivalent circuit in s-domain is shown in the

following figure.
20 2.5 A
8.4s 10 s
+
336/s 42 48
I1 I2
20
Vx +
The KVL equations in s-domain for the two meshes
Therefore, are given by
iL(0-) = 2.5 A
336
8.4sI1 + 42(I1 I2 ) =
s
At t = 0+, the circuit is as shown in the following
and 42(I2 I1 ) + (10 s + 48)I2 = 0
figure.
The above equations can be written in matrix form
as
42 + 8.4s 42 I1 336/s
42 90 + 10s I2 0
=
20 2.5 A
Therefore,
2.5 A
1
I1 42 + 8.4s 42 336/s
I = 42 + 10s 0
2 90
20 15 14 1
s s + 2 s + 12
+ V =
7 8. 4 + 1. 4
+
At t = 0 , the voltage V is s s + 2 s + 12
V = IR= 2.5 20 = 50 V Converting the currents in time-domain, we get
i1(t) = (15 - 14e-2t - e-12t)u(t) and i2(t)

+
Therefore, the voltage Vx at t = 0 is
Vx = -V = -50 V = (7 - 8.4e-2t + 1.4e-12t)u(t)
Ans. (-50)
Therefore, as t ,
5. We know that for a series RLC circuit,
Z = R + j (XL - XC)
i1(t) = 15 A
Ans. (15)
Given that Z at resonant frequency = 100 + j0
7. Refer to Solution of Question 6. Therefore, as t ,
Therefore,
R = 100 = 0.1 k i2(t) = 7 A
Ans. (0.4) Ans. (7)
1. The differential equation for the current i(t) in the

d 2 i(t) di(t)
circuit of the figure is (a) 2 2
+2 + i(t) = sin t
2W
dt dt
i(t) 2H
2
(b) d i(t) + 2 di(t) + 2i(t) = cos t
+ dt2 dt
sin t 1F

2 V
(c) 2 d i(t) + 2 di(t) + i(t) = cos t
2 dt
dt
2
(d) d i(t) + 2 di(t) + 2i(t) = sin t
dt2 dt R R
(GATE 2003: 1 Mark) i1(0+)
Solution. Using KVL around the loop, we have
+ i(t)dt
di(t) 1
sint = 2i(t) + 2
dt 1 Applying KVL to the outer loop, we get
-i1(0+)R - V - i1(0+)R = 0
Differentiating the above equation, we get
Therefore,
2di(t) d 2 i(t)
V
i1(0+ ) =
cos t = +2 + i(t)
dt dt2 2R
d2i di Ans. (a)
2 +2 + i(t) = cos t
dt2 dt 3. I1(s) and I2(s) are the Laplace transforms of i1(t)
Ans. (c) and i2(t), respectively. The equations for the loop
currents I1(s) and I2(s) for the circuit shown in the
Common Data for Questions 2 and 3: The circuit given figure, after the switch is brought from posi-
for questions 2 and 3 is shown in the following figure. tion 1 to position 2 at t = 0, are
Assume that the switch S is in position 1 for a long time

Ls I (s) V
and thrown to position 2 at t = 0. 1
R + Ls + Cs
(a) = s
1 I2 (s)
1
1
S C Ls R+ 0
Cs

Ls I (s) V
1
i1(t) i2(t) R + Ls + Cs
=s
2
(b)
1 I2 (s)
R 1
V L
R Ls R+ 0
C Cs

I1(s)
1
R + Ls + Cs Ls V
(c)
1 I2 (s)
+
2. At t = 0 , the current i1(t) is = s

V V Ls R + Ls + 0
(a) (b) Cs
2R R

I1(s)
1
V R + Ls + Cs Ls V
(c) (d) zero
(d)
1 I2 (s)
4R = s

Ls R + Ls + 0
Solution. At t = 0-, in steady state, the circuit Cs
representation is shown below. (GATE 2003: 2 Marks)
vc(0) Solution. When the switch is in position 2, the
circuit is as shown in the following figure.
R V/s
1/sC
V +
i1(0)
i2(0) I2(s) R
I1(s) sL
From the figure, we can see that at t = 0- R
i1(0-) = i2(0-) = 0 and vc(0-) = V
1 2 1/sC
At t = 0+, the circuit is as shown in the following

figure. Applying KVL in left loop, we get

(c)
0.5
0.31
100 Chapter 5: RLC Circuits 1 t(s)

2
V 1
I1(s) R + + I1(s)
i(t)
+ [I1(s) I2 (s)]sL = 0
s sC
Therefore, 1
1 V
I1(s) R + + sL I2 (s) sL = (d) 0.63
sC s
Applying KVL in right loop, we get
1
[I2 (s) I1(s)]sL + I2 (s)R + I2 (s) =0 2 t(s)
sC
Therefore, (GATE 2004: 1 Mark)
1 Solution. For the given figure, the Laplace trans-

I1(s) sL + I2 (s) R + sL +
sC
=0

form of the current i(t) is
V (s) 1 1 1 1
The equations can be written in matrix formation
s + 2 s(s + 2) 2 s s + 2
I (s) = = =
as given below

I1(s)
1
sL
Taking the inverse Laplace transform, we get
R + sL + sC
V
1 I2 (s)
= s

1
(1 e2t )
i(t) =
sL R + sL + 0 2
sC
Therefore, at t = 0, i(t) = 0, at t = , i(t) =
Ans. (c) 1
0.5 and at t = , i(t) = 0.31. The following figure
4. For the RL circuit shown in the following figure, 2
the input voltage v1(t) = u(t). The current i(t) is shows the curve for i(t) meeting the above men-
1H tioned values.
i(t)
v1(t) i(t) 2
0.5
i(t) 0.31
0.5 0 1 t(s)
(a) 2
0.31
Graph depicted in option (c) matches the conditions.
Ans. (c)
2 t(s) 5. The circuit shown in the following figure has initial

current iL(0-) = 1A through the inductor and an
i(t) initial voltage vC(0-) = -1V across the capacitor.
For input v(t)= u(t), the Laplace transform of the
current i(t) for t 0 is
1
(b)
0.63 1 1H
+
i(t) +
1 t(s) 1F
2 v(t)
i(t)

(c)
0.5 s s+2
(a) (b)
0.31 s2 + s + 1 s2 + s + 1
s2 s2
(c) (d)
s2 + s + 1 s2 + s + 1
1 t(s)
i(t)
1
05-Chapter-05-Gate-ECE.indd 100
(d) 0.63 6/30/2015 12:21:02 PM
Solution. For a series RLC circuit with input

voltage source v(t), applying KVL, we get I(s)
0.002 s
i(t)dt
Ldi(t) 1
v(t) = Ri(t) + +
dt C 0
Taking Laplace transform on both sides, we get

+ 1 mV
+
I (s) vC (0 )
V (s) = RI (s) + LsI (s) LiL (0+ ) + +
sC s
(a) 0.5 A (b) 2.0 A (c) 1.0 A (d) 0.0 A
We know that (GATE 2006: 2 Marks)
iL (0 ) = iL (0+ ) vC (0 )s = vC (0+ )
Solution. The voltage across the inductor is given
and
by
Substituting the values of R, L, C, iL(0+) and LdI
V =
vC(0+) in the above equation, we get dt
Taking Laplace Transform on both sides, we get
1 I (s) 1
= I (s) + sI (s) 1 + V(s) = sLI(s) - LI(0+)
s s s
It is given that LI(0+) = 1 mV. Therefore,
1 103
s+2 I(0+ ) = = 0.5 A
I (s) = 2
2 103
s + s+1 Ans. (a)
Ans. (b)
8. In the circuit shown in the following figure, assume
6. A square pulse of 3V amplitude is applied to CR that all the capacitors are initially uncharged. If
circuit shown in the following figure. The capaci- vi(t) = 10u(t) V, vo(t) is given by
tor is initially uncharged. The output voltage V2 at
1 k
time t = 2 s is
V1
0.1 F + +
3V + +
4 F
V1 1 k V2 vi(t) 4 k 1 F vo(t)

2s t
(a) 3 V (b) -3 V (a) 8e-t/0.004 V (b) 8(1 - e-t/0.004) V

(c) 4 V (d) -4 V (c) 8u(t) V (d) 8 V
Solution. The time constant is Solution. The impedance of a parallel combina-
-6 -4
RC = 0.1 10 10 = 10 s = 100 s
3 tion of R and C is given by
R (1/Cs) R
Since RC is very small, steady state will be reached Z= =
R + (1/Cs) RCs + 1
in 2s. Therefore, the voltage across the capacitor VC
after 2 seconds is 3 V. The output voltage vo(t) is given by
Since the voltage across the capacitor cannot vo (t)

change instantaneously, therefore
4 103

V2 = -VC = -3 V
6
4 10 10 s + 1

3
Ans. (b) = vi (t)
4 10 1 10
3 3
4 103 106 s + 1 1 103 4 106 s + 1

7. A 2 mH inductor with some initial current can be +
represented as shown below, where s is the Laplace
Transform variable. The value of initial current is = 0.8vi (t)

Therefore, Rs I s
vo(t) =0.8 10u(t) = 8u(t) V (a) 0 (b)
L
Ans. (c)
(R + Rs )I s
9. In the circuit shown, VC is 0 V at t = 0 s. For t 0, (c) (d)
L
the capacitor current iC(t) , where t is in seconds, (GATE 2008: 1 Mark)
is given by
Solution. At t = 0+, the inductor behaves as an
open circuit. Therefore,
20 k iC(t) VL = IsRs
+ Also,
di
4 F VL = L (0+ )
+
10 V 20 k VC

dt
Therefore,
di + V IR
(0 ) = L = s s
dt L L
Ans. (b)
(a) 0.50 exp(-25t) mA (b) 0.25 exp(-25 t) mA
11. The circuit shown in the following figure is used to
(c) 0.50 exp(-12.5t) mA(d) 0.25 exp(-6.25 t) mA
charge the capacitor C alternately from two cur-
(GATE 2007: 2 Marks) rent sources as indicated. The switches S1 and S2
are mechanically coupled and connected as follows:
Solution. At t = 0+, capacitor is short circuit and
For 2nT t < (2n + 1) T, (n = 0,1,2...) S1 to P1
at t = , capacitor is open circuit. Therefore,
and S2 to P2.
IC (0+ ) =
10 V
= 0.5 mA For (2n + 1)T t < (2n+ 2)T, (n = 0,1,2...) S1 to
20 103 Q1 and S2 to Q2
The current through the capacitor at t = is Q1 P1 Q2 P2
+
IC() = 0 S1
S2
The time constant of the circuit is
= ReqC = (20 103 || 20 103 ) 4 106 = 40 ms 1 0.5 1F VC(t) 1 1

C
Using the formula
iC(t) = iC() - [iC () - iC(0)]e-t/ 1A 1A

we get
iC(t) = 0 - (0 - 0.5)]e-t/40 10 = 0.5e-25t mA
-3 Assume that the capacitor has zero initial charge.
Given that u(t) is a unit step function, the voltage
Ans. (a) VC(t) across the capacitor is given by

(1)n tu(t nT )
10. In the following circuit, the switch S is closed at
di + (a)
t = 0. The rate of change of current (0 ) is n =0
dt
(b) u(t) + 2 (1)n u(t nT )
given by
n =1
S
(c) tu(t) + 2 (1)n (t nT )u(t nT )
R
n =1

Is Rs i(t)
L (d) [0.5 e(12nT ) + 0.5e(t2nT T ) ]
n =0

Solution. The waveform of voltage VC(t) is shown 13. For t > 0, the voltage across the resistor is
below.
[e( e(1/2)t ]
1 3 / 2)t
(a)
VC(t) 3
1 3t 3t
(b) e(1/2)t cos
1
2T sin
t 2 3 2
T
1 3t
e(1/2)t sin
2
(c)
3 2
In mathematical form, we have 3t
e(1/2)t cos
2
(d)
VC(t) = tu(t) - 2(t - T)u(t - T) + 2(t - 2T)u(t - 2T)... 3 2
= tu(t) + 2 (1)n (t nT )u(t nT )
n =1 Solution. The Laplace transform of the voltage
Ans. (c) across the resistor is
Common Data for Questions 12 and 13: The fol- 1 s
lowing series RLC circuit with zero initial conditions is VR (s) = 1 = 2
s + 1 + (1/s) s + s+1
excited by a unit impulse function (t).
s + (1/2) (1/2) ( 3 /2) (2/ 3 )
1H 1 = 2 2

[s + (1/2)] + ( 3 /2) [s + (1/2)]2 + ( 3 /2)2
+
(t) + 1F VC(t)
3 3
VR (t) = et /2 cos
1 t /2
t e sin t
2 3 2
12. For t > 0, the output voltage VC(t) is Therefore,
1 t 3 3 3
VR (t) = et /2 cos
1
t t
1
t t sin
e 2 e 2
2 2
(a) (b) te 2 2 3 2
3 3
Ans. (b)
3 3
1 1
2 t 2 t 14. The switch in the circuit shown was on position a
(c) e 2 cos t (d) e 2 sin t
3 2 3 2 for a long time, and is moved to position b at time
t = 0. The current i(t) for t > 0 is given by
Solution. The Laplace transform of the voltage 10 k a b

across the capacitor is i(t)
1 1

0.2 F
VC (s) =
s + 1 + (1/s) s 100 V
+
5 k
1 1
= 2 =
s + s + 1 [s + (1/2)]2 + ( 3/2)2 0.5 F 0.3 F
3 (a) 0.2e-125tu(t) mA (b) 20e-1250tu(t) mA
e(t /2) sin
2
VC (t) = t
3 2 (c) 0.2e-1250tu(t) mA (d) 20e-1000tu(t) mA
Ans. (d) (GATE 2009: 2 Marks)

Solution. At t = 0-, the switch is in position à' Solution. It is given that

as shown in the following figure.
+ Ri = V0 (1 + BeRt / L sin t)u(t)
di
L
10 k dt
+ Taking Laplace transform on both sides, we
get
0.2 F
= 0.16 F
LsI (s) Li(0 ) + RI (s) =
+ V0 V0 B
100 V 100 V = v(0) +
s [s + (R/L)]2 + 1
= v(0+)
0.5 F 0.3 F Substituting the value of i(0) and solving for I(s),
we get
0.8 F
1 LV0 V0 V0 B
I (s) = + +
At t > 0, the switch is in position `b', as shown in Ls + R R [s + (R/L)] + 1
s 2
the following figure.
By the final value theorem,
I(s) V0
lim i(t) = lim sI (s) =
t s 0 R
1/sC R = 5 k Ans. (a)
16. In the circuit shown, the switch S is open for a long
v(0+) 100 +

= s time and is closed at t = 0. The current i(t) for
s t 0+ is
C = (0.5 + 0.3) 0.2 F = 0.16 F t=0 10

S
The current through the capacitor is
1.5 A 10 15 mH
+
v(0 ) t /RC 10
u(t)
i(t)
i(t) = e
R
Now,
(a) i(t) = 0.5 - 0.125 e-1000t A
v(0+) = 100 V,
1
=
1 (b) i(t) = 1.5 - 0.125 e-1000tA
RC 5 10 0.16 106
3 (c) i(t) = 0.5 - 0.5 e-1000tA
(d) i(t) = 0.5 - 0.375 e-1000t A
and R = 5 k
Solution. At t = 0-, the circuit is shown below.

Therefore,
-1250t
i(t) = 20e u(t) mA
10
Ans. (b)
0.75 A
15. The time-domain behavior of an RL circuit is rep-
0.75 A
resented by L + Ri = V0 (1 + BeRt / L sin t)u(t) .
di
dt
V 1.5 A
For an initial current of i(0) = 0 , the steady-
R 10
state value of the current is given by
V0 2V0
(a) i(t) (b) i(t)
R R
V0 2V0 The current will divide equally in both 10 resis-
(c) i(t) (1 + B) (d) i(t) (1 + B)
R R tors as shown in the circuit. Therefore,
(GATE 2009: 2 Marks) i(0-) = i(0+) = 0.75 A

At t 0+, the circuit in s-domain is as shown below. i(t)
10
i(s) 10
Ls +

100 V
10 10
15

s 50 F
+
Li(0+)
+
(a) i(t) = 15 exp(-2 103t) A

The above circuit can be rearranged as shown (b) i(t) = 5 exp(-2 103t) A
below. (c) i(t) = 10 exp(-2 103t) A
(d) i(t) = -5 exp(-2 103t) A
10 V(s) 10 (GATE 2011: 2 Marks)

Solution. At t = 0 , voltage across the capacitor is
i(s)
2.5 103
Vc (0 ) =
Q
Ls = = 50 V
+ 15 C 50 106
s

Therefore,
10 +
Li(0 ) + Vc(0+) = -50 V
In steady-state, the capacitor behaves as an open
circuit; therefore,
Applying KCL, we get Vc() = 100 V
V (s) (15/s) V (s) V (s) + 15 103 0.75

Now,
+ + =0 V c (t) = V c () + V c (0+ ) V c () et /RC
10 10 10 + 15 103 s
= 100 150e210
3
t
The current through the capacitor is
10000 + 7.5s
V (s) = dVc (t)
2s(s + 1000) ic (t) = C
dt
10000 {10000 + 7.5(1000)}
= 50 106 150 2 103 e210
3
= + t
2 1000s 2(1000)(s + 1000)
= 15e210 t A
3
5 1.25
=
s s + 1000 Ans. (a)
Taking inverse Laplace transform, we get 18. In the circuit shown in the following figure, C1 and
-1000t C2 are ideal capacitors, C1 had been charged to 12 V
v(t) = 5 - 1.25 e V
before the ideal switch S is closed at t = 0, The
Now, current i(t) for all t is
u (t)
i(t) = = 0.5 0.125e1000 t A S t=0
10
Ans. (a)
17. In the following circuit shown, the initial charge
on the capacitor is 2.5 mC, with the voltage C1 C2
polarity as indicated. The switch is closed at time i(t)
t = 0. The current i(t) at a time t after the
switch is closed is

(a) zero Solution. From the given figure, we have

(b) a step function
A
(c) an exponentially decaying function
(d) an impulse function I+1
(GATE 2012: 1 Mark) I j1 W
1W
Solution. Since there is no resistance, hence the 10 A
time constant will be zero. This means as soon as
10 10 V
the switch will be closed, voltages across C1 and C2
will become equal. We know that capacitor allows D + +
B
sudden change of voltage only if impulse of current
passes through it. Therefore, the current i(t) is an 10A I +1
impulse current. j1 W
Ans. (d) 1W
19. In the circuit shown below, the current through I
the inductor is
C
A
VB + 10 10 = VD
j1 W
1W
Therefore, VB = VD
10A Hence, the voltage drop across BD, VBD = 0
Therefore no current flows through it.
10V 10V Using KVL along the loop ABCD, we get
D + +
B
I 1 j(I + 1) (I + 1) + Ij = 0
10A Solving the above equation, we get
j1 W 1W I=-
j +1
2
Current through inductor is
C
j + 1
1 I + 1 =
2
2 +1
(a) A (b) A
1+ j 1+ j
1 j 1 j 1
1 = = =
(c) A (d) 0 A 2 (1 j)(1 + j) 1 + j
1+ j

CHAPTER 6
TWO-PORT NETWORKS
This chapter discusses the different parameters used to describe the two-port networks including the impedance, admit-
tance, transmission, inverse transmission, hybrid and inverse hybrid parameters.
6.1 INTRODUCTION 1 2
+ I +
1 I2
Two-port
A two-port network is an electrical network with two V1 V2
network
separate ports for input and output. Figure 6.1 shows a
two-port network. The port labeled 1-1 is the input port 1 2
Figure 6.1| Two-port network.
while the port labeled 2-2 is the output port. The port
variables are port currents and port voltages as shown in
the figure. Here, I1 is the input current, I2 the output cur-
rent, V1 is the input voltage and V2 is the output voltage.
Two sets of linear equations are required for describing 6.2 OPEN-CIRCUIT IMPEDANCE
the relationships between the port voltages and currents PARAMETERS
of a two-port network. The various terms that relate these
voltages and currents are referred to as parameters. The
choice of two independent and two dependent parameters The impedance parameters are used in the synthesis
results in different parameters, namely, the impedance, of filters. The input and output voltages (V1 and V2,
admittance, transmission, inverse transmission, hybrid respectively) can be expressed in terms of input and
and inverse hybrid parameters. These parameters are dis- output currents (I1 and I2, respectively) as given in
cussed in the chapter. Eqs (6.1) and (6.2).

108 Chapter 6: Two-Port Networks
V1 = z11I1 + z12 I2 (6.1) 6.2.1 Condition for Reciprocity and Symmetry
A network is said to be reciprocal if the ratio of the

V2 = z21I1 + z22 I2 (6.2) response transform to the excitation transform is inva-
z11 is the open circuit input impedance or the input driv- riant to an interchange of the positions of excitation
ing-point impedance with output port open-circuited: and response in the network. If the transfer impe-dances
z12 and z21 are equal, then the network is reciprocal.
V1 Therefore, for a two-port network to be reciprocal,
z11 = (6.3)
I1 I2 = 0 z12 = z21.
z12 is the open circuit transfer impedance from port 1 to A two-port network is said to be symmetric, if the
port 2 or the reverse transfer impedance with input port ports can be interchanged without changing the port
open-circuited: voltages and currents. For a two-port network to be
V symmetric, z11 = z22.
z12 = 1 (6.4)
I 2 I1 = 0
z21 is the open circuit transfer impedance from port 2 to 6.3 SHORT-CIRCUIT ADMITTANCE
port 1 or the forward transfer impedance with output PARAMETERS
port open-circuited:
V
z21 = 2 (6.5) The admittance parameters are also used in the syn-
I1 I2 = 0 thesis of filters. The input and output currents (I1 and
z22 is the open circuit output impedance or the output I2, respectively) can be expressed in terms of input and
driving point impedance with input port open-circuited: output voltages (V1 and V2, respectively) as given in
Eqs. (6.7) and (6.8):
V2
z22 = (6.6) I1 = y11V1 + y12V2 (6.7)
I2 I1 = 0
z11 and z21 are obtained by open-circuiting the output port I2 = y21V1 + y22V2 (6.8)
and input port is excited by a known voltage source V1 y11 is the short circuit input admittance or the input driving-
as shown in Fig. 6.2(a). Here, z12 and z22 are obtained by point admittance with output port short-circuited:
open-circuiting the input port and the output port is excited
by a known voltage source V2 as shown in Fig. 6.2(b). I1
y11 = (6.9)
V1 V2 = 0
I1 I2 = 0
y12 is the short circuit transfer admittance from port 1
to port 2 or the reverse transfer admittance with input
V1 +
z11 = port short-circuited:
I1 I
V1
+
V2 y12 = 1 (6.10)
V2
V 2 V1 = 0

z21 =
I1 y21 is the short circuit transfer admittance from port 2
to port 1 or the forward transfer admittance with output
port short-circuited:
(a) I
y21 = 2 (6.11)
V1 V2 = 0
I1 = 0 I2
y22 is the short circuit output admittance or the output
V1 driving point admittance with input port short-circuited
+
z12 = I2
I2 y22 = (6.12)
+
V V2
2
V1 V1 = 0
V2
Here, y11 and y21 are obtained by short-circuiting the

z22 =
I2 output port and input port is excited by a known cur-
rent source I1 as shown in Fig. 6.3(a) and y12 and y22
are obtained by short-circuiting the input port and the
(b)
output port is excited by a known current source I2 as
Figure 6.2| Calculation of impedance parameters. shown in Fig. 6.3(b).

6.5 INVERSE TRANSMISSION PARAMETERS 109
I1 A is the reverse voltage ratio with the output port open-

I2
circuited or the open-circuit voltage ratio:
+ I1 + V1
y11 = A= (6.15)
V1 V2 I2 = 0
I1 V1 V2 = 0
I2 and B is the transfer impedance with the output port

y21 = short-circuited or the negative short-circuit transfer
V1
impedance:
V
B = 1 (6.16)
(a) I2 V2 = 0
I1 I2 C is the transfer admittance with the output port open-

circuited or open circuit transfer admittance:
+ I1 + I1
y12 = C= (6.17)
V2 V2 I2 = 0
V1 = 0 V2 I2
I2 D is the reverse current ratio with the output port short-

y22 =
V2 circuited or the negative short-circuit current ratio:
I1
D = (6.18)
(b) I2 V2 = 0
Figure 6.3| Calculation of admittance parameters.

6.4.1 Condition for Reciprocity and Symmetry
6.3.1 Condition for Reciprocity and Symmetry For a two-port network to be reciprocal,
AD BC = 1
For a two-port network to be reciprocal, For a two-port network to be symmetric,
y12 = y21 A=D
For a two-port network to be symmetric,
6.5 INVERSE TRANSMISSION
y11 = y22 PARAMETERS
It may be mentioned here that the impedance and the
admittance parameters are grouped together into the
The output voltage and current (V2 and I2, respectively)
category of immittance parameters.
can be expressed in terms of input voltage and cur-
rent (V1 and I1, respectively) as given in Eqs. (6.19)
and(6.20):
6.4 TRANSMISSION PARAMETERS V2 = AV1 + B(I1 ) (6.19)
I2 = CV1 + D(I1 ) (6.20)

The transmission and inverse transmission parameters
describe the voltage and the current at one end of the where A is the forward voltage ratio with the input port
two-port network in terms of the current and voltage at open-circuited or the open-circuit voltage gain:
the other end.
V2
The input voltage and current (V1 and I1, respec- A= (6.21)
V1 I1 = 0
tively) can be expressed in terms of output voltage and
current (V2 and I2, respectively) as given in Eqs. (6.13) and B is the transfer impedance with the input port
and (6.14): short-circuited or the negative short-circuit transfer
impedance:
V1 = AV2 + B(I2 ) (6.13)
V2
B = (6.22)
I1 = CV2 + D(I2 ) (6.14) I1 V1 = 0

C is the transfer admittance with the input port open- Here the parameters are dimensionally mixed, hence they
circuited or open circuit transfer admittance: are referred to as hybrid parameters. Figure 6.4 shows
the h-parameter equivalent model of a two-port network.
I2
C = (6.23) I1 I2
V1 I1 = 0 h11
D is the forward current ratio with the input port short- + +

circuited or the negative short-circuit current gain:
+
V1 h12V2 h21I1 1/h22 V2
I
D = 2 (6.24)
I1 V1 = 0
Figure 6.4| h-parameter equivalent model.

6.5.1 Condition for Reciprocity and Symmetry
For a two-port network to be reciprocal, 6.6.1 Condition for Reciprocity and Symmetry
AD B C = 1
For a two-port network to be reciprocal,
A = D h12 = h21

6.6 HYBRID PARAMETERS h11 h12
=1
h21 h22
h11h22 h12h21 = 1
The input voltage and output current (V1 and I2, respec-
or
tively) can be expressed in terms of output voltage and
input current (V2 and I1, respectively) as given in Eqs.
(6.25) and (6.26): 6.7 INVERSE HYBRID PARAMETERS
V1 = h11I1 + h12V2 (6.25)
The output voltage and input current (V2 and I1,
I2 = h21I1 + h22V2 (6.26) respectively) can be expressed in terms of input voltage
h11 is the input impedance with the output port and output current (V1 and I2, respectively) as given in
short-circuited or the short-circuit input impedance: Eqs. (6.31) and (6.32):
V1 I1 = g11V1 + g12 I2 (6.31)

h11 = (6.27)
I1 V2 = 0
V2 = g21V1 + g22 I2 (6.32)
h21 is the forward current gain with the output port short- g11 is the input admittance with the output port open-
circuited or the short-circuit forward current gain:
circuited or the open-circuit input admittance:
I2 I1
h21 = (6.28) g11 = (6.33)
I1 V2 = 0 V1 I2 = 0
h12 is the reverse voltage gain with the input port open- g21 is the forward voltage gain with the output port
circuited or the open-circuit reverse voltage gain: open-circuited or the open-circuit forward voltage gain:
V1 V2
h12 = (6.29) g21 = (6.34)
V2 I1 = 0 V1 I2 = 0
h22 is the output admittance with the input port open- g12 is the reverse current gain with the input port short-
circuited or the open-circuit output admittance:
circuited or the short-circuit reverse current gain:
I2 I1
h22 = (6.30) g12 = (6.35)
V2 I1 = 0 I2 V1 = 0

6.8 INTERRELATION BETWEEN DIFFERENT PARAMETERS 111
g22 is the output impedance with the input port 6.7.1 Condition for Reciprocity and Symmetry
short-circuited or the short-circuit output impedance:
For a two-port network to be reciprocal,
V
g22 = 2 (6.36) g12 = g21
I2 V1 = 0
The parameters are dimensionally mixed; hence, they
are referred to as hybrid parameters. Figure 6.5 shows g11 g12
=1
the g-parameter equivalent model of a two-port network. g21 g22
I1 I2
g22 or g11g22 g12g21 = 1
+ +
1
6.8 INTERRELATION BETWEEN
g11 g21I2 + g21V1 DIFFERENT PARAMETERS
V1 V2

Table 6.1 gives the conversion formulas between differ-
Figure 6.5| g-parameter equivalent model. ent parameters.
Table 6.1| Conversion formulas between different parameters.
z y h g T t
y22 y12 Dh h12 1 g12 DT
z11 z12
A d 1
Dy Dy h22 h22 g11 g11 C C c c
z
y21 y11 h21 1 g21 Dg Dt
z21 z22
1 D a
Dy Dy h22 h22 g11 g11 C C c c
z22 z12 1 h12 Dg g12 DT a

D 1
y11 y12
Dz Dz h11 h11 g22 g22 B B b b
y
z21 z11 h21 Dh g21 1 1 Dt d

A
y21 y22
Dz Dz h11 h11 g22 g22 B B b b
Dz z12 y12 g22 g12 DT

1 b 1

B
h11 h12
z22 z22 y11 y11 Dg g D D a a
h
z21 1 y21 Dy g21 g11 1 Dt

c

C
h21 h22
z22 z22 y11 y11 g Dg D D a a
1 z12 Dy y12 h22 h12 DT c 1

C
g11 g12
z11 z11 y22 y22 Dh Dh A A d d
g
z21 Dz y21 1 h21 h11 Dt b

1 B
g21 g22
z11 z11 y22 y22 Dh Dh A A d d
z11 Dz y22 1 Dh h11 1 g22 d b
A B
z21 z21 y21 y21 h21 h21 g21 g21 Dt Dt
T
1 z22 Dy y11 h22 1 g11 Dg c a
C D
z21 z21 y21 y21 h21 h21 g21 g21 Dt Dt
z22 Dz y11 1 1 h11 Dg g22 D B
a b
z12 z12 y12 y12 h12 h12 g12 g12 DT DT
t
1 z11 Dy y22 h22 Dh g11 1 C A
c d
z12 z12 y12 y12 h12 h12 g12 g12 DT DT

6.9 INTERCONNECTION OF and Z22a and Z11b, Z12b, Z21b and Z22b, respectively.
TWO-PORT NETWORKS The z-parameters Z11, Z12, Z21 and Z22 of the series
networkis
6.9.1 Cascade Connection Z11 Z12 Z11a + Z11b Z12a + Z12b

Z = Z22a + Z22b
(6.38)
21 Z22 Z21a + Z21b
Figure 6.6(a) shows the cascade connection of two net-
works Na and Nb with transmission parameters Aa, Ba,
Ca and Da and Ab, Bb, Cb and Db, respectively. The
6.9.3 Parallel Connection
transmission parameters A, B, C and D of the cascaded
network is
Figure 6.6(c) shows the parallel connection of two net-
A B Aa Ba Ab Bb works Na and Nb with y-parameters Y11a, Y12a, Y21a and
C D = C Da Cb Db
(6.37)
a Y22a and Y11b, Y12b, Y21b and Y22b, respectively. The
y-parameters Y11, Y12, Y21 and Y22 of the parallel net-
6.9.2 Series Connection work is
Figure 6.6(b) shows the series connection of two net- Y11 Y12 Y11a + Y11b Y12a + Y12b
Y Y22 Y21a + Y21b Y22a + Y22b
= (6.39)
works Na and Nb with z-parameters Z11a, Z12a, Z21a 21
1 I1 I1a I2a I1b I2b 2

+ + + + + I2
V1 V1a Na V2a V1b Nb V2b

1 2
(a)
I1 I1a I2a I2
+ +
+ V1a Na + I1 I1a I2a I2

V
2a
+ + + +
V V1a Na V2
1
V
2a
V1 V2
I1b I2b
+ +
I1b I2b

V1b Nb V2b
+ +
V1b Nb V2b

(b) (c)
Figure 6.6| (a) Cascade connection of two two-port networks. (b) Series connection of two two-port networks.
(c) Parallel connection of two two-port networks.
IMPORTANT FORMULAS
V1 V1 I1 I1
1. z11 = , z12 = 2. y11 = , y12 =
I1 I2 = 0 I2 I1 = 0 V1 V2 = 0 V2 V1 = 0
V2 V2 I2 I2
z21 = , z22 = y21 = , y22 =
I1 I2 = 0 I2 I1 = 0 V1 V2 = 0 V2 V1 = 0

SOLVED EXAMPLES 113
V1 V1 V1 V1
3. h11 = , h12 = 5. A = , B =
I1 V2 = 0 V2 I1 = 0 V2 I2 = 0 I2 V2 = 0
I2 I2 I1 I1
h21 = , h22 = C= , D =
I1 V2 = 0 V2 I1 = 0 V2 I2 = 0 I2 V2 = 0
I1 I1 V2 V2
4. g11 = , g12 = 6. A = , B =
V1 I2 = 0 I2 V1 = 0 V1 I1 = 0 I1 V1 = 0
V2 V2 I2 I2
g21 = , g22 = C = , D =
V1 I2 = 0 I2 V1 = 0 V1 I1 = 0 I1 V1 = 0
SOLVED EXAMPLES

I o =
1
parameters z11 and z21 are I1
1 + 11 4
1 1 1 1 4
= I
15 1
Therefore,
1 1 1 Io =
1
I
15 1
Now,
2
1 1 1 1
V2 = 2I o = I
15 1
Therefore,
(a) 2.733 , 0.133 (b) 1.467 , 0.231
(c) 4.612 , 0.452 (d) 7.212 , 0.521 z21 =
V2
=
2
= 0.133
I1 I2 = 0 15
Solution. To calculate z11 and z21 let us connect a Ans. (a)
current source I1 at the left side terminals as shown
in the following figure: 2. For the network of Question 1, the parameters z12
and z22 are
1 I o 1 1 1 I2 = 0 (a) 0.133 , 2.428 (b) 0.133 , 2.733
+ Io + (c) 0.452 , 2.764 (d) 0.452 , 5.631
I1 V1 1 1 1 V2 Solution. For the given network,

z12 = z21 = 0.133
1 1 1 1
To calculate z22, let us connect a voltage source
V2 across the right most terminals as shown in the
V1 following figure:
z11 =
I1 I2 = 0
= 2 + 1 || (1 + 1) + 1 || (1 + 1 + 1) I1=0 1 1 1 1
= 2.733 + +
From this figure, we can see that V1 1 1 1 V2
1
Io =
4I o 1 1 1 1

V2 We know that
z22 = = 2 + 1 || (1 + 1) + 1 || (1 + 1 + 1) V2
I2 I1 = 0 z22 =
I2
= 2.733
I1 = 0
Ans. (b) Therefore,
2I2 + 1I2
3. The open circuit impedance matrix of the two-port z22 = =3 W
network shown in the following figure is I2
Hence, the impedance matrix is

I1 2 I2
+ + 2 1
8 3
V1 1 3I1 V2
Ans. (a)
z-parameters are z11 = 10, z12 = 6, z21 = 4 and
z22 = 12. The values of current I1 and I2, respec-
tively, are
2 1 2 8 (a) 0.34 A, 0.25 A (b) 0.81 A, 0.15 A
(b)
3
(a)
8 3

8 (c) 0.93 A, 0.27 A (d) 0.71 A, 0.19 A
0 1 2 1
(d)
3
(c)
1 0

1 2 I1 I2
+ +
Solution. We know that
3A 4 V1 [z] V2 10
V
z11 = 1
I1 I2 = 0
Therefore,
Solution. The current source of 3 A with 4
2I1 1 impedance can be converted into an equivalent
z11 = = 2
I1 voltage source as shown in the following figure.
We know that
V2 4 2 I1
z21 =
I1 I2 = 0 +
+
12 V V1
Therefore,
6I1 + V1 6I1 2I1
z21 = = = 8
I1 I1
We know that Applying Kirchhoffs voltage law, we get

V1 12 + 6I1 + V1 = 0
z12 =
I2 I1 = 0 Therefore,
Therefore, V1 = 12 6I1
1 I2 From the given values of z-parameters, we get
z12 = = 1W
I2 V1 = 10I1 6I2 and V2 = 4I1 + 12I2

SOLVED EXAMPLES 115
From the given figure, I1 j2 I2 = 0

V2 = 10I2
+
Solving the above four equations, we get
I2 = 0.15 A and I1 = 0.81 A
4
+
V1 V2
Ans. (b)

5. For the circuit shown in Question 4, the values of
V1 and V2, respectively, are
(a) 5.8 V, 1.2 V (b) 8.2 V, 1.5 V Applying Kirchhoffs voltage law, we get
(c) 7.1 V, 1.5 V (d) 4.5 V, 9.1 V
V1 = (4 2j)I1 and V2 = 4I1
Solution. From the equations given in solution of The parameter A is
Question 4, we get
V1 4 2j
= 1 0. 5 j
V1 = 7.1 V and V2 = 1.5 V
=
V2 4
Ans. (c) The parameter C is
6. The short-circuit admittance matrix of a two-port I1 I
= 1 = 0.25
0 1/2 V2 4I1
network is
0
. The given two-port net-
1/2 To find the parameters B and D, consider the fol-
work is lowing figure:
(a) non-reciprocal and passive
I1 j2 I2
(b) non-reciprocal and active
(c) reciprocal and passive
(d) reciprocal and active +
Solution. Since y12 y21 , the given two-port net- V1

+ 4 V2 = 0
work is non-reciprocal and active.
Ans. (b)
7. For the two-port network shown in the following
figure, the ABCD parameters are
From this figure, we see that
j2 I1 = I2
Therefore, the parameter D is
4
I1
=1
I2
Now,
V1 = j2I1 = j2I2
1 + j0.5 j2 1 j0.5 j2
(a)
1
(b)
1

0.25 S 0.25 S
Therefore, parameter B is
V1
1 j0.5 j2 1 j0.5 j2 = 2 j W
(c)
1
(d)
1

0.25 S
I2
0.25 S
The ABCD parameter matrix is
Solution. To determine A and C parameters, let A B 1 j0.5 j2
us connect source V1 to the left terminals as shown C D = 0.25 S 1
in the following figure: Ans. (d)

1. Find the admittance parameter y12 (in milli-mhos) 2. For the two-port network shown in the following
in the two-port network shown in the following figure, what is the value of load impedance ZL (in
figure. ohms) for maximum power transfer. Given that the
10 40
20 z-parameter matrix is z =
30 60
I1 I2 .
20
E1 5 10 E2 +
120 Vrms [z] ZL

Solution. The given figure is redrawn as shown in Solution. The Thevenins equivalent impedance
the following figure. of a network is given by
(y3) z12z21 40 30
ZTH = z22 = 60 = 20 W
I1 20 I2 z11 + zs 20 + 10
For maximum power transfer,
E1 5 10 E2 ZL = ZTH
(y1) (y2)
Therefore,
ZL = 20 Ans. (20)
The admittance matrix is given for the network 3. In Question 2, the maximum power delivered to
shown in the above figure as follows: the load (in watts) is
y11 y12 y1 + y3 y
y = y + y
3
Solution.
y
21 22
y
3 2 3
Therefore, z21 30
VTH = Vs = 120 = 120
y = y z11 + zs 10 + 20
12 3
Hence, The maximum power delivered is

1 2
y12 = = 0.05 mho = 50 milli-mhos VTH
= 180 W
20 4ZTH
Ans. (-50) Ans. (180)
PRACTICE EXERCISE
1. Two two-port networks are connected in parallel. The 2. The condition AD BC = 1 for a two-port net-
combination is to be represented as a single two-port work implies that the network is a
network. The parameters of this network that are
(a) reciprocal network
obtained by addition of the individual parameters are
(b) lumped element network
(a) z-parameters (b) h-parameters (c) lossless network
(c) y-parameters (d) ABCD-parameters (d) unilateral element network
(1 Mark) (1 Mark)

3. Two two-port networks are connected in cascade. 7. For the two-port network of Question 6, the
The combination is to be represented as a single y-parameter matrix is
0.21 S 0.02 S
two-port network. The parameters of the network
0.21 S 0.02 S
(a)
0.02 S 0.24 S 0.02 S 0.24 S
that are obtained by multiplying the individual (b)
parameter matrices are
0.21 S 0.02 S 0.21 S 0.02 S
(c)
0.02 S 0.24 S 0.02 S 0.24 S
(a) z-parameter (b) h-parameter (d)
(c) y-parameter (d) ABCD-parameter
(1 Mark) (2 Marks)
4. Which of the following statements are true? 8. In the circuit shown in the following figure, the equiv-
S1: If n number of two-port networks with z-param- alent impedance seen across terminals A and B is
eters [Z]1, [Z]2, [Z]3, ..., [Z]n are connected in series,
2 4
then the z-parameters of the equivalent two-port A
network [Z]eq is given by j3
[Z]eq = [Z]1 + [Z]2 + [Z]3 + + [Z]n Zeq
S2: If n two-port networks with y-parameters [Y ]1,
[Y ]2, [Y ]3, ..., [Y ]n are connected in parallel, then j4
the y-parameters of the equivalent two-port net- 2 4
B
work [Y ]eq is given by
W (b)
16
W
[Y ]eq = [Y ]1 + [Y ]2 + [Y ]3 + + [Y ]n 8
(a)
S3: If n two-port networks with transmission 3 3
W (d) None of these
parameters [A]1, [A]2, [A]3, ..., [A]n are connected 8
(c)
in cascade, then the transmission parameters of the 3 + 12 j (1 Mark)
equivalent two-port network [A]eq is given by
[A]eq = [A]1 * [A]2 * [A]3*...*[A]n 9. For the two-port network shown in the following
figure, the h11 and h21 parameters, respectively, are
(a) S1 and S2 (b) S2 and S3
(c) S3 and S1 (d) S1, S2 and S3 1 4
(1 Mark) 1:2
5. For a two-port network to be reciprocal,
(a) z11= z22 and y11 = y22
(b) y21 = y12 and h21 = h12
(c) AD BC = 0
(d) None of these
(a) 2, 0.5 (b) 2, 0.5 (c) 0.5, 2 (d) 0.5, 2
(1 Mark)
6. For the two-port network shown in the following (2 Marks)
figure, the z-parameter matrix is
10. For the two-port network in Question 9, the h12
4 and h22 parameters, respectively, are
(a) 0.5, 0 (b) 0.5, 0 (c) 0, 0.5 (d) 0, 0.5
(2 Marks)
2
8 z-parameters (in ohms) are
1
6
4.8 W 0.4 W 4.8 W 0.4 W 1 1

(a)
4.2 W
(b)
0.4 W 0.4 W 4.2 W

4.8 W 0.4 W 4.8 W 0.4 W

(c) 1
0.4 W 4.2 W
(d)
0.4 W 4.2 W

(2 Marks)

(a) z11 = 5/3, z12 = 4/3, z21 = 4/3 and z22 = 5/3 1 Z1 1 0
(a) (b)
(b) z11 = 4/3, z12 = 5/3, z21 = 5/3 and z22 = 4/3
0 1 Y2 1
(c) z11 = 5/3, z12 = 4/3, z21 = 4/3 and z22 = 5/3
(d) z11 = 5/3, z12 = 4/3, z21 = 4/3 and z22 = 5/3
(c)
Z1
(d)
1 + Z1Y2 2 Z1
1 2
(2 Marks)
12. For the circuit in Question 11, the h-parameters are Y2 2
Y
3 4 3 4 (2 Marks)
5 W 5 5 W 5
(a)
3
(b)
4 3
16. For the opamp circuit shown in the following figure,
S S
4 the z-parameters are (Assume that the opamp to
5 5 5 5 be ideal.)
3 4 3 4
5 W 5 5 W 5 10 k
(c)
4 3
(d)
3

4
S S I3 R3
5 5 5 5 I1
R2
2 k
(1 Mark) 2 k I2
13. The Z -parameters Z11 and Z21 for the two-port 1 k V2
V1 + R4
network shown in the following figure are R1
I1 2 I2 C = 0.1 F 1
sC
4
E1 E2
10E1 1
z11 = R1 + , z12 = 0,
sC
(a)
6 R3 1
W; Z21 =
16
W z21 = 1 + , z = R4
(a) Z11 =
11 11 R2 sC 22
(b) Z11 = W; Z21 = W

6 4
1
11 11 z11 = 0, z12 = R1 + ,
16 sC
(c) Z11 = W; Z21 = W
6
R 1
(b)
11 11
z21 = 1 + 3 , z = R4
R2 sC 22
(d) Z11 = W; Z21 = W
6 4
11 11
(2 Marks) 1
z11 = R1 + , z = 0,
14. Given a two-port network, described by equations sC 12
R 1
V1 = I1 + 2V2 and I2 = 2I1 + 0.4V2. The y-param- (c)
eter matrix of the network is z21 = R4 , z22 = 1 + 3
R2 sC
1S 2S 1 S 2 S
(a) (b)
2 S 0 . 4 S 2 S 4.4 S (d) None of these
1 S 2 S 1 S 2 S (2 Marks)
(c)
2 S 4.4 S
(d)
2 S 0.4 S

17. If the network in Question 16 is fed with a voltage
(2 Marks) source with source resistance of 50 and a load
resistance of 1 k, the voltage gain is
transmission parameters are 2
(a) 2 (b)
Z1 [1 + 1.05 104 s]
2
(c) 4 (d)
Y2 [1 + 1.05 104 s]
(2 Marks)

18. The following figure shows the simplified equiva- I1 I2

lent circuit of the BJT. The h-parameters are + +
C3
Z1
I1 I2 V1 C1 gmV1 Y2 V2
+ +

V1 I1 Y2 V2 sC + sC3 sC3
(a) 1
gm sC3 Y2 + sC3
sC1 sC3
(b)
sC3 Y 2 + sC3
sC + sC3 sC3
(a) 2
Z 0 (c) 1
Y1 Y2
b gm
sC + sC3 sC3
b
(b) 1
Z (d) 1
Y2 m
g + sC Y 2 + sC3
a
3
(2 Marks)
(c) 1
Z 0 20. Which of the following statements are true?
b
Y 2 S1: When z11 = z22, the two-port network is said
(d) Cannot be determined from the given data to be symmetrical.
S2: When z12 = z21 the network is said to be
(1 Mark) reciprocal.
19. The following figure shows the simplified equiva- (a) S1 (b) S2
lent model of a field effect transistor. The y-param- (c) Both S1 and S2 (d) Neither S1 nor S2
eters are (1 Mark)
1. For the two-port network shown in the following 5. For the circuit shown in the following figure, find
figure, find the magnitude of current I1 (in Amperes). the value of h11 (in ).
(2 Marks)
300
I1 I2
40
+ +
100 0 V
Z11 =
Z12 = j20
V2 10 10 50
+ V1
Z21 = j30
Z22 = 50
+

Vx 100 10Vx
(2 Marks) +

2. For the two-port network of Question 1, find the
phase of current I1 (in degrees).
(1 Mark) 6. Find the value of h21 (in S) for the circuit in Question 5.
(1 Mark)
3. For the two-port network in Question 1, find the
magnitude of current I2 (in Amperes). 7. For the circuit in Question 5, find the value of h22
(in S).
(1 Mark) (1 Mark)
4. For the two-port network in Question 1, find the 8. Determine the value of h12 (in S) for the circuit in
phase of current I2 (in degrees). Question 5.
(1 Mark) (1 Mark)

9. Find the value of g11 (in S) for the circuit in 13. A two-port network is shown in the following
Question 5. figure. What is the parameter h21 for this network?
(1 Mark) (2 Marks)
10. For the circuit in Question 5, find the value of g21
(in ). I1 I2
(1 Mark) + +
11. What is the value of g12 (in ) for the circuit in
R R
Question 5. V1 V2
R
(1 Mark)
12. For the circuit in Question 5, determine the value
of g22 (in ).
(1 Mark)
1. (c) For the two-port networks connected in parallel, Applying Kirchhoffs voltage law to the 2 -4 -V2
the admittance parameter (y-parameters) are obtained loop, we get
by addition of the individual parameters. V2 4Io + 2Io = 0
2. (a) For a reciprocal network, AD BC = 1. Therefore,
2
V2 = I1
3. (d) For two two-port networks connected in cas- 5
cade, the ABCD parameter matrix is obtained by Now,
the multiplication of the individual ABCD param- V
z21 = 2 = = 0.4 W
2
eter matrices. I1 5
4. (d) To calculate z22 and z12, let us connect a source to
5. (b) For a two-port network to be reciprocal, the right terminals, as shown in the following figure:
y21 = y12 and h21 = h12 I1=0 1 4 2
2
6. (d) To find the parameters z11 and z21, let us con- + +
nect a current source I1 to the left terminals as
8
shown in the following figure: V1 V2 I2
4 Io 2 I2 =0
1
+ Io +
2 4 6 3
I1 V1 8 V2 V2
z22 = = (4 + 2) (8 + 6) = 4.2 W
I2
z12 = z21 = 0.4 W
4 6 3 Therefore, the z-parameter impedance matrix is
The same current Io passes through 4 and 8 4.8 W 0.4 W
z=
resistors and same current Io passes through the 0.4 W 4.2 W
2 and 6 resistors. Therefore, 7. (c) The y-parameter matrix can be found from the
V1 z-parameter matrix obtained in Question 6.
z11 = = (4 + 8) (2 + 6) = 4.8 W
I1 Dz = (4.8)(4.2) (0.4)2 = 20
Now, Therefore,
I1 = I1 and I o = I1
8 2 3 z22 4.2
Io = y = = = 0.21 S
8 + 12 5 5 11 Dz 20

z12 0.4 10. (b) Refer to the circuit shown in the following figure:
y12 = = = 0.02 S
Dz 20 I1 = 0 1 1:2 4 I2
z21 0.4
y21 = = = 0.02 S +
Dz 20

z 4.8 V1 V2
y22 = 11 = = 0.24 S +
Dz 20

Therefore, the y-parameter matrix is therefore
given by Since I1 = 0, we get I2 = 0. Therefore,
0.21 S 0.02 S
y=
0.02 S 0.24 S
h22 = 0
The relation between V1 and V2 is given by

8. (b) The bridge is balanced. Therefore,
V2 N
= 2 =2
= (2 4) + (2 4) = W
8
Zeq V1 N1
3 Now,
9. (a) To get the h11 and h21 parameters, let us con- V1 1
h12 = = = 0. 5
nect a current source at the left terminals as shown V2 2
in the following figure:
11. (a) To calculate z11 and z21, consider the circuit
shown in the following figure:
1 1:2 4 I2
+ + Io 1
I1 V1 V2 = 0
1 1 I2 =0
+ +
The impedance seen by the primary of the trans- I1 V1 1 V2

former is
4 4
ZP = = =1
n2 4
5
Applying Kirchhoffs voltage law to the left loop, V1 = I1 1 + 1 (1 + 1) = I
3 1
we get
Now,
V1 (1 + 1)I1 = 0 V1
= W
5
z11 =
Therefore, I1 3
V1 = 2I1 The current Io is given by
Now, 1 1
Io = I = I
V1 1+2 1 3 1
h11 = =2
I1 Also,
The current ratio is V2 + Io + I1 = 0
Therefore,
I1 N
= 2 = 2
4
V2 = I
I2 N1 3 1
Now, Now,
I 1
h21 = 2 = = 0.5 z21 =
V2
= W
4
I1 2 I1 3

Now, z12 and z22 can be calculated from the follow- Substituting, the value of E1 in the above equation
ing figure: (i.e., E1 = 6/11 I1 ), we get
1 11E2 44I1 + 60I1 = 0

Therefore,
E2
= W
16
I1 1 1 Z21 =
I1 11
+ + 14. (b) The h-parameter matrix is given by
1 W 2
h=
2 0.4 S
V1 V2 I2
Now,
h = 1(0.4) 2(2) = 4.4
The y-parameter matrix is given by
We can see that the circuits in the two figures are
similar. Therefore, 1 h12
h h11 1 S 2 S
= W y = 11 =
5
Dh 2 S 4.4 S
z22 = z11
3 h21
h h11
11
z21 = z12 = W
4
and
3 15. (c) The given network is a cascaded arrangement
12. (b) The h-parameters are expressed in terms of of two networks as shown in the following figure:
z-parameters as follows:
Z1
Dz z12 3 4
z W
z22 5 5
h = 22 =
z21 1 4 3

z22 5
S
5
z22
Y2
13. (c) In the two-port network given, we have
E1 = Z11I1 + Z12 I2 and E2 = Z21I1 + Z22 I2

Now,
E1
Z11 = N1 N2
I1 I2 = 0
The transmission parameters of the network N1 are
Applying Kirchhoffs voltage law in left side loop
[A]1 = 0
1 Z1
1
with I2 = 0, we get

E1 2I1 4I1 + 10E1 = 0 The transmission parameters for the network N2 are
1 0
[A]2
Therefore,
=
11E1 = 6I1 Y2 1
The transmission parameters of the cascaded net-
E1
= W
6 work are
or Z11 =
I1 11
1 Z1 1 0 1 + Z1Y2 Z1
[A]eq = 1 Y2
=
1
Now, 0 1 Y2
V2
Z21 = 16. (a) Applying Kirchhoffs voltage law, we get
I1 I2 = 0
Applying Kirchhoffs voltage law in right side loop I1

V1 = R1I1 +
with I2 = 0, sC
E2 4I1 + 10E1 = 0 and V2 = R4 I2 + R3 I3 + R2 I3

From the concept of virtual earth for opamps, we get V2 2

=
R2 I3 =
I1 Vg [1 + 1.05 104 s]
sC
Therefore, 18. (c) Applying Kirchhoffs voltage law at the input
(R2 + R3 ) I1 + R I
port, we get
V2 = 4 2
sCR2 V1 = I1Z1
Comparing with the equations for z-parameters, we Applying Kirchhoffs current law at output port,
get we get
1
z11 = R1 + I2 = I1 + Y2V2
sC
z12 = 0 Therefore, the h-parameters are
R 1
[h] = b1
Z 0
z21 = 1 + 3
R2 sC Y2
z22 = R4
19. (a) Using Kirchhoffs current law, we get
17. (d) The voltage gain of a terminated two-port net-
work in terms of its z-parameters is given by I1 = V1sC1 + (V1 V2 )sC3
= V1(sC1 + sC3 ) + V2 (sC3 )
V2 z21ZL
=
Vg (z11 + Zg )(z22 + ZL ) z12z21 I2 = V2 Y2 + gm V1 + (V2 V1 )sC3
Therefore, and = V1(gm sC3 ) + V2 (Y2 + sC3 )
V2 [1 + (R3/R2 )]ZL Therefore,

=
sC3
[Y ] = g
Vg (R 4 + ZL )[1 + sC(R1 + Zg )] sC1 + sC3
m sC3 Y2 + sC3
It is given that Zg = 50 ; ZL = 1 k; R3 = 10 k;
R2 = 1 k; R4 = 2 k and C = 0.1 F. Therefore, 20. (c)
1. From the given z parameters, the network equa- Substituting the value of I1 in the equation
tions are 100 = 40I1 + j20I2, we get
100 = j80I2 + j20I2
V1 = 40I1 + j20I2
Therefore,
and V2 = j30I1 + 50I2 I2 = j = 190
Now, Thus,
I1 = j2(j) = 2 = 20
V1 = 1000
Hence, the magnitude of current I1 in Amperes is 1.
and V2 = 10I2 Ans. (1)
2. Refer to the Solution of Question 1 and therefore
Substituting the values of V1 and V2 in the above
the phase of current I1 is 0.
equations, we get
Ans. (0)
100 = 40I1 + j20I2 3. Refer to the Solution of Question 1 and therefore
magnitude of current I2 is 1.
and 10I2 = j30I1 + 50I2 Ans. (1)
Therefore, 4. Refer to the Solution of Question 1 and therefore

the phase of current I2 is 90.
I1 = j2I2 Ans. (-90)

5. To calculate h11 and h21, let us connect a current Applying Kirchhoffs current law at node 2, we get
source to the left terminals as shown in the follow- V V + 10Vx
ing figure: I2 = 2 + 2
400 50
300 Therefore,
400I2 = 9V2 + 80Vx
10 50 2
From the circuit, we know that
1 100 1
+ Vx = V = V2

+ +
I2 400 2 4
I1 V1 Vx 100 +
10 Vx V2 = 0
Therefore,
400I2 = 9V2 + 20V2
Hence,
At node 1, applying Kirchhoffs current law, we get
I2 29
V V 0 h22 = = = 0.0725 S
I1 = x + x V2 400
100 300 Ans. (0.0725)
Therefore, 8. Refer to the Solution of Question 7 and
Vx = 75I1 V1 = Vx
Applying Kirchhoffs voltage law to the left loop, Therefore,
we get V2
V1 =
V1 10I1 Vx = 0 4
Hence,
Therefore,
V1 1
V1 10I1 75I1 = 0 h12 = = = 0.25 S
V2 4
Hence, Ans. (0.25)
V
h11 = 1 = 85 W 9. The g-parameter g11 can be calculated using the
I1 conversion formula:
Ans. (85)
h22
g11 = = 0.02929 S
6. Refer to the Solution of Question 5 and then apply- Dh
ing Kirchhoffs current law to node 2, we get Ans. (0.02929)
10Vx V 750 75 10. The g-parameter g21 can be calculated using the
I2 = x = I I = 14.75I1 conversion formula:
50 300 50 1 300 1
h21
Therefore, g21 = = 5.96 W
Dh
I2 Ans. (5.96)
h21 = = 14.75 S
I1
Ans. (14.75) 11. The g-parameter g12 can be calculated using the
conversion formula:
7. To find h22, let us connect a voltage source to the h12
g12 = = 0.101 W
right terminals as shown in the following figure: Dh
Ans. (0.101)
300 12. The g-parameter g22 can be calculated using the
conversion formula:
I1= 0 10 50 2 I2 g22 =
h11
= 34.34 W
1 Dh
+ + Ans. (34.34)

100
+
V2
V1 Vx 10Vx 13. Using h-parameters, current
+

I2 = h21I1 + h22V2

Therefore, Therefore,
I I1
h21 = 2 I2 =
I1 V2 = 0 2
Hence,
In the given circuit, when V2 = 0, we get
1
h21 =
2
I2R = (I1 + I2 )R Ans. (-0.5)
1. The impedance parameters Z11 and Z12 of the The equivalent circuit is shown in the following figure:
two-port network shown in the following figure are
2 0.5 0.5 2
1 2
1 2
2 2 2 R1 R3
R2 0.25
1 1
1 2
1 2
The impedance matrix is given by
(a) Z11 = 2.75 and Z12 = 0.25
R1 + R + 2 R3
(b) Z11 = 3 and Z12 = 0.5
(c) Z11 = 3 and Z12 = 0.25 R3 R 2 + R3
(d) Z11 = 2.25 and Z12 = 0.5 Therefore,
(GATE 2003: 2 Marks) Z11 = R1 + R3 + 2 = 0.5 + 0.25 + 2 = 2.75 W
Solution. Using Delta-Wye transformation, the and Z12 = R3 = 0.25 W

conversion circuit is as shown in the following
Ans. (a)
figure:
2. For the lattice circuit shown in the following figure,
2 2 2 Za = j2 and Zb = 2 . The values of the open
Z Z12
1 2
circuit impedance parameters Z = 11 are
1 R3 21
Z Z 22
R1 3 1 3
2 R2
1 1 Zb
Za
Za
1 2 Zb
Therefore, 2 4
2 1 2
R1 = = = 0. 5 1 j 1 + j 1 j 1 + j
(a)
1 + j 1 + j
(b)
1 + j 1 j
4 4
11 1
R2 = = = 0.25 1 + j 1 + j 1 + j 1 + j
(d)
1 + j 1 + j
(c)
1 j 1 j
4 4
2 1
R3 = = 0. 5

Solution. For the lattice network, Z-parameter Therefore,

matrix is given as 1
X=
n
Za + Zb Za Zb
Ans. (b)
Z= 2 2
Za Zb Za + Zb 4. The h-parameters of the circuit shown in the
2 2 following figure are
where I1 I2
Za = 2 j 10
Zb = 2 W + +
Therefore, V1 20 V2
1 + j j 1
Z=
j 1 1 + j
Ans. (d) 0.1 0.1 10 1
(a)
0.1 0.3
(b)
1 0.05

3. The ABCD parameters of an ideal n : 1 transformer
n 0 30 20 10 1
shown in the following figure are
0 X
(c)
20 20
(d)
05
. The
1 0.
value of X will be
I1 I2
Solution. The h-parameters can be calculated
using the formula
V1 V2 V1
h11 =
I1 V2 = 0
V1
h12 =
1 V2 I1 = 0
(a) n (b)
n
I2
1 h21 =
(c) n2 (d) I1
n2 V2 = 0
(GATE 2005: 1 Mark) I2

h22 =
V2 I1 = 0
Solution. The ABCD parameter matrix is given
by When V2 = 0, the circuit can be redrawn as shown
V1 A B V2 in the following figure:
I = C D I
1 2
+
For the given transformer, I1 10 I2
I2 V n V1
= 1 =
I1 V2 1
Therefore,
V1 = AV2 BI2 and I1 = CV2 DI2 From this figure, we can see that I1 = I2 and
V1 = 10I1 . Therefore,
The value of A and D parameters can be calculated I2
as follows: h21 = = 1
I1
V1 I1 V2 1
A= = n and D = = = V1
V2 I2 = 0
I2 V2 = 0
V1 n and h11 = = 10
I1

When I1 = 0, then V1 = V2 since there is no drop 6. In the two port network shown in the following
in 10 resistance. Therefore, figure, Z12 and Z21 are, respectively,
V1 I1 I2
h12 = =1
V2
Also,
re I1 r0
V2 = 20I2
Therefore,
I2 1 (a) re and r0 (b) 0 and r0
h22 = = = 0.05
V2 20 (c) 0 and r0 (d) re and r0
The h-parameter matrix is given by (GATE 2006: 2 Marks)
10 1 Solution. The Z12 and Z21 parameters can be cal-

1 0.05 culated using the following formulas:
Ans. (d) V1 V2
Z12 = and Z21 =
5. A two-port network is represented by ABCD I2 I1 = 0 I1 I2 = 0
V A B V 2 When I1 = 0, then V1 = 0. Therefore,
parameters given by 1 = . If port
I1 C D I2 V1
2 is terminated by RL, the input impedance seen at Z12 = =0
I2
port 1 is given by
When I2 = 0, then V2 = bI1r0 . Therefore,
A + BRL ARL + C
(a) (b) V2
C + DRL BRL + D Z21 = = br0
I1
DRL + A B + ARL Ans. (b)
(c) (d)
BRL + C D + CRL Linked Answer Questions 7 and 8: A two-port
network shown below is excited by external DC
sources. The voltages and currents are measured
Solution. The following figure shows the two- with voltmeters V1 and V2 and ammeters A1 and
port network terminated by resistance RL: A2 (all assumed to be ideal) as indicated. Under
following switch conditions, the readings obtained
I1 I2 are listed as follows:
+ + (i) S1 open and S2 closed: A1 = 0 A, V1 = 4.5 V,
V1 Two-port RL V2 V2 = 1.5 V, A2 = 1 A
network
(ii) S1 closed and S2 open: A1 = 4 A, V1 = 6 V, V2 = 6
V, A2 = 0 A
S1 S2
+ A A +
The voltages and currents of the network can be
expressed in terms of A, B, C and D parameters as 1 1 2 2
V1 = AV2 BI2 and I1 = CV2 DI2 + + + +

Two
6V V1 V2 1.5 V
Now,
port

V2 = I2RL network
Therefore, 1 2
V1 AV2 BI2 AI2RL BI2 7. The z-parameter matrix for this network is
= =
I1 CV2 DI2 CI2RL DI2
1.5 1.5 1.5 4.5
(a)
4.5 1.5
(b)
1.5 4.5
The input impedance is
V1 ARL + B
4.5 1.5
(c)
= 1.5 4.5
(d)
1.5 1.5 1.5 4.5
I1 CRL + D
Ans. (d)

Solution. It is given that when switch S1 is open So, the h-parameter matrix is
and S2 is closed, then 3 3
1 0.67
V1 = 4.5 V; V2 = 1.5 V; I2 = 1 A; I1 = 0
Ans. (a)
Therefore, 9. For the two-port network shown in the follow-
V 4.5
= 4.5
ing figure, the short-circuit admittance parameter
Z12 = 1 =
I2 I1 = 0 1 matrix is
0.5
V2 1.5
= 1. 5
1 2
Z22 = =
I2 I1 = 0 1
0.5 0.5
It is given that when switch S1 is closed and S2 is
open, then
1 2
I1 = 4 A; V1 = 6V ; V2 = 6 V; I2 = 0
4 2 1 0.5
(a)
2 4
(b)
1
S S

Therefore,
V1 0. 5
= 1.5 W
6
Z11 = =
I1 4 1 0.5 4 2
(c)
0.5 1
(d)
2 4
I2 = 0 S S
V2
= 1.5 W
6
Z21 = =
I1 I2 = 0 4 (GATE 2010: 1 Mark)
So, the z-parameter matrix is Solution. Short-circuit admittance parameters
1.5 4.5 for a two port -network shown in the following
1.5 1.5 figure are
Ans. (c) Y11 = Ya + Y b
Y12 = Y21 = Y b
8. The h-parameter matrix for this network is
Y22 = Y b + Y c
3 3 3 1
(a)
1 0.67
(b)
3 0.67

Yb
1 2
3 3 3 1
(c)
67
(d)
.67

1 0 . 3 0
Ya Yc
1 2
Solution. The network equations for h-parame-
ters are given by For the given network,
1
V1 = h11I1 + h12V2 and I2 = h21I1 + h22V2 Ya = Y b = Y c = = 2S
0.5
V1 4.5 Y11 = 2 + 2 = 4 S
Y12 = Y21 = 2 S
h12 = = =3
V2 I1 = 0 1.5
Y22 = 2 + 2 = 4 S
I 1
h22 = 2 = = 0.67 Therefore, the short-circuit admittance matrix is
V2 I1 = 0 1.5
4 2
V Z Z 2 4 S
h11 = 1 = Z11 12 21
I1 V2 = 0 Z 22 Ans. (a)
4.5 1.5 10. If the scattering matrix [S ] of a two port network is
= 1.5 3
1.5 0.20 0.990
[S ] =
I Z21 1.5 0.990 0.190
h21 = 2 = = = 1
I1 V2 = 0 Z22 1.5 then the network is

(a) loss less and reciprocal From given figure,

(b) loss less but not reciprocal
V2 = I2RL = 100I2
(c) not loss less but reciprocal
(d) neither loss less nor reciprocal Therefore,
(GATE 2010: 1 Mark) V2
I2 =
100
Solution. For the reciprocal networks
Substituting the value of I2 in Eq. (1), we get
S12 = S21
V2
For the symmetrical networks, = 0.01 V1 + 0.1 V2
100
S11 = S22
Therefore,
For anti-symmetrical networks,
V2
S11 = S22
1
=
V1 11
For lossless reciprocal networks,
Ans. (d)
S11 = S22 Common Data for Questions 12 and 13: With
2 2 10 V DC connected at port A in the linear non-
and S11 + S12 =1 reciprocal two-port network shown in the following
figure, the following were observed:
Therefore, the network is not lossless but reciprocal.
(i) 1 connected at port B draws a current of 3 A.
Ans. (c)
(ii) 2.5 connected at port B draws a current of 2 A.
network N is described by the following Y matrix: +
0.1 S 0.01 S
Y =
0.1 S
A B
0.01 S

25 W I1 I2
12. For the same network, with 6 V DC connected at
+ + port A, 1 connected at port B draws (7/3) A. If
+ 8 V DC is connected to port A, the open circuit
100 V V1 N V2 100 W
voltage at port B is
(a) 6 V (b) 7 V
(c) 8 V (d) 9 V
V2 Solution. It is given that V1 = 10 V, V2 = 3 V

The voltage gain is
V1 and I2 = 3 A. We know that
1 V1 = AV2 BI2
(b)
1
(a)
90 90
Therefore,
1
(c)
1
(d) 10 = 3A + 3B
99 11
(GATE 2011: 2 Marks) It is given that V1 = 10 V, V2 = 5 V and I2 = 2 A.
Therefore,
Solution. From the circuit, we have
10 = 5 A + 2 B
I2 = Y21V1 + Y22V2
Solving the two equations, we get
Therefore,
I2 = 0.01 V1 + 0.1 V2 (1) 10 20
A= and B =
9 9

Given V1 = 8 V. We need to find open circuit volt- Solution. It is given that

age at port B.
V1 = 10 V and V2 = (7 I2 )
8 = A (V2 )oc 0
Now,
Therefore, V1 = AV2 BI2
8 8 Therefore,
(V2 )oc = = = 7.2 V
A 10/9
10 = 7 I2 A BI2
The nearest answer in the given options is 7.
Ans. (b) Substituting the value of A and B in the above
13. With 10 V DC connected at port A of the network equation, we get
shown, the current drawn by 7 connected at port 70 20
10 = I2 I2
B is 9 9
3 5 Therefore,
(a) A (b) A
7 7
I 2 = 1 A
9
(c) 1 A (d) A The negative sign signifies that current is drawn
7
from the input V1.
(GATE 2012: 2 Marks) Ans. (c)

CHAPTER 7
STATE EQUATIONS FOR NETWORKS
This chapter discusses the network functions, poles and zeros of a network and analysis of a network using state
equations.
7.1 NETWORK FUNCTIONS The voltage transfer function is

V2 (s)
G21(s) = (7.1)
For a two-port network, the ratio of one voltage to V1(s)
another voltage is referred to as the voltage transfer The current transfer function is
function, the ratio of one current to another current
I2 (s)
is referred to as the current transfer function and the a 21(s) = (7.2)
ratio of one current to another voltage or one voltage to I1(s)
another current is referred to as the transfer admittance
The admittance transfer function is
or the transfer impedance functions, respectively. For a
two-port network shown in Fig. 7.1, there are four trans- I2 (s)
Y21(s) = (7.3)
fer functions, mentioned as follows. V1(s)
The impedance transfer function is
1 2
+ +
I1 I2 V2 (s)
Two-part Z21(s) = (7.4)
V1 V2 I1(s)
network

1 2 It may be mentioned here that all network functions,
mentioned in Eqs. (7.1) to (7.4) can be expressed in the
Figure 7.1| Two-port network. generalized form as

132 Chapter 7: State Equations for Networks
a sn + a1sn 1 + + an 1s + an
7.1.2 Necessary Conditions for Transfer
p(s)
N (s) = = 0m Functions
q(s) b0 s + b1sm1 + + bm1s + bm
(7.5)
The necessary conditions for a network function to be a

where, as and bs are the coefficients of real positive
transfer function with common factors in the numerator
value. The degree of the numerator polynomial is n and
polynomial p(s) and denominator polynomial q(s) can-
that of the denominator polynomial is m.
celled are listed as follows:
Let the numerator polynomial p(s) polynomial has n
roots z1, z2, z3, ..., zn and the denominator polynomial 1. The coefficients in the polynomials p(s) and q(s)
q(s) has m roots p1, p2, ..., pm. Then the network function should be real and positive.
N(s) can be written as 2. Complex and imaginary poles and zeros must be
conjugate.
(s z1 )(s z2 ) (s zn ) 3. The real part of all the poles and zeros must not
N (s) = C (7.6)
(s p1 )(s p2 ) (s pm ) be positive. If the real part is zero, then the pole
and zero must be simple.
where C is the scale factor and is given by 4. The polynomial q(s) must not have missing terms
a0 between the highest and lowest degree, unless all
C= the even or odd terms are missing.
b0
5. The polynomial p(s) may have terms missing
For s = z1 and z2, ..., zn, the network function becomes between the terms of lowest and highest degree and
zero and these values of s are referred to as the zeros some of the coefficients may be negative.
of the network function. For s = p1, p2, ..., pn, the net- 6. The degree of p(s) may be as small as zero, inde-
work function becomes infinite and these values of s pendent of the degree of q(s).
are referred to as the poles of the network function. A 7. For G12 and a12, the maximum degree of p(s) is
network function is completely specified in terms of its the degree of q(s). For Z12 and Y12, the maximum
zeros, poles and the scale factor. degree of p(s) is the degree of q(s) plus one.
The stable network functions with all left-hand
plane zeros are classified as minimum-phase functions
and those with any zero on the right-half plane are non- 7.2 ANALYSIS OF A NETWORK
minimum phase functions. USING STATE EQUATIONS
7.1.1 Necessary Conditions for Driving-Point The state variable analysis is used for solution of first-
Functions order, second-order and higher order systems. The
nth-order system is described in terms of set of n simul-
The necessary conditions for a network function to be taneous first-order equations obtained either directly or
a driving-point function with common factors in the from the nth-order equation of the system. Then the set
numerator polynomial p(s) and denominator polynomial is replaced by a single first-order matrix equation. The
q(s) cancelled are listed as follows: solution of the matrix equation is obtained using stan-
dard numerical and computer techniques.
1. The coefficients in the polynomials p(s) and q(s)
should be real and positive.
2. The complex and imaginary poles and zeros must 7.2.1 State Equations in Normal Form
be conjugate.
3. The real part of all the poles and zeros must not be The state equations are written making use of the con-
positive. If the real part is zero, then the pole and cept of graph theory. Graph theory was discussed in
zero must be simple. detail in Chapter 1. The steps to be followed to formu-
4. The polynomials p(s) and q(s) must not have late the first-order state equations for a given network
missing terms between the highest and lowest are as follows:
degree, unless all the even or odd terms are 1. Draw the network graph for the given circuit.
missing. 2. In the graph, choose a tree that contains all voltage
5. The degree of p(s) and q(s) may differ by zero or sources and maximum possible number of capaci-
one only. tors. All the current sources and the inductors are
6. The terms of lowest degree in p(s) and q(s) should left for the co-tree. The maximum number of con-
differ in degree by one at the most. trol voltages should be in the tree and the control

SOLVED EXAMPLES 133
currents in the co-tree. The resistors can be either y x1

in the tree or in the co-tree.
dy
3. Assign a voltage to each capacitor and mark its x2
polarity. Similarly for an inductor, assign a current dt
and specify its direction. These capacitor voltages d2y
and the inductor currents are the state variables. x3
dt2

4. Using Kirchhoffs voltage law (KVL), write the
loop equation for each loop comprising of an induc-
d n 1y
xn
tor link and a path in the tree.
5. Using Kirchhoffs current law (KCL), write a node dtn 1
equation at each capacitor.
6.If the resistor voltages occur in the KVL equations, Equation (7.7) can be replaced by first-order system
use KCL to formulate vR/R to a sum of link currents. x1 = 0x1 + 1x2 + 0x3 + 0x4 + + 0xn
If resistor currents occur in the KCL equations, use
KVL to set iRR equal to a sum of loop voltages. x2 = 0x1 + 0x2 + 1x3 + 0x4 + + 0xn
Substitute these values in the equations obtained in x3 = 0x1 + 0x2 + 0x3 + 1x4 + + 0xn
(7.8)
steps 4 and 5. The set of equations obtained are the
normal state equations in formal form.
xn 1 = 0x1 + 0x2 + 0x3 + 0x4 + + 1xn
7.2.2 State Matrix Differential Equation xn = b0 x1 b1x2 b2 x3 b3 x4 + bn 1xn + f (t)
The coefficients of xs can be denoted by a n n matrix

The response of passive electrical networks can be
A. Here, f(t) is an n 1 column matrix having func-
described in the form of a differential equation in the
tion f(t) in the last row and zero otherwise. Therefore,
time-domain as given below.
Eq. (7.8) can be rewritten as a single first-order matrix
dny d n 1y dy d2y
+ + b2
differential equation for the state vector x(t) as
n
+ bn 1 n 1 2
+ b1
+ b0 y = f (t)
dt
x = Ax(t ) + f (t)
dt dt dt
(7.9)
(7.7)
where f(t) is the forcing function. Let us consider the The matrix A is the characteristic or the system matrix
following: and f(t) is the forcing vector.
IMPORTANT FORMULAS
1. The voltage transfer function is 3. The admittance transfer function is

V2 (s) I2 (s)
G21(s) = Y21(s) =
V1(s) V1(s)
2. The current transfer function is 4. The impedance transfer function is
I2 (s) V2 (s)
a 21(s) = Z21(s) =
I1(s) I1(s)
SOLVED EXAMPLES
1. The necessary and sufficient condition for a rational (b) complex and lie in the left half of the s-plane
function of s, T(s) to be a driving point impedance of (c) c omplex and lie in the right half of the
an RC network is that all poles and zeros should be s-plane
(a) s imple and lie on the negative real axis of the (d) simple and lie on the positive real axis of the
s-plane s-plane

Solution. The poles and zeros should be simple 1 R

(c) s2 + s+ = 0
and lie on the negative real axis of the s-plane. LC L
Ans. (a)
(d) None of these
2. For the RLC circuit shown in the following figure,
the normal equations are Solution. As found in Question 2, the characteris-
tic matrix of the system is
R
R 1
L L
A=
0
1
+ vs= 0 iL C

The eigen values are the roots of the characteristic

C equation
+
det(sI A) = 0
vC
Therefore,
diL R v dv 1 R 1
(a) = iL C and C = iL + 0vC s+
R 1
dt L L dt C L L =0 or s2 + s+ =0
1
diL 1 R dv 1 s L LC
(b) = iL vC and C = iL + 0vC C
dt L L dt C
Ans. (b)
di R v dv R
(c) L = iL C and C = iL + 0vC 4. The circuit of the following figure represents a
dt L L dt C
(d) None of these
L1
Rs
Solution. The network comprises of a single mesh.
Applying KVL, we get Vo
diL C1
L + vC + 0 + RiL = 0
dt L2
Vs RL
The above equation can be rewritten as
C2
diL R v
= iL C
dt L L
Applying KCL at the positive end of the capacitor, (a) low-pass filter (b) high-pass filter
we get (c) band-pass filter (d) band-reject filter
Solution. At w = 0, the given circuit can be rep-

dvC
C = iL + 0vC
dt resented as shown in the following figure:
Therefore, the normal equations of the given net-
Rs
work are
+ +
diL R v dvC 1
= iL C and = iL + 0vC
dt L L dt C
Vs RL Vo
Ans. (a)
3. For the RLC circuit depicted in the figure of
Question 2, the eigen values of the system are the
roots of the characteristic equation given by
(a) s2 + Rs + LC = 0 Therefore,
R 1 Vo RL
(b) s2 + s +
LC
=0 = (finite value)
L Vs RL + Rs

SOLVED EXAMPLES 135
At w = , the given circuit can be represented as

+
shown in the following figure. Rs
Vs RL Vo
Rs
+ +
From this figure, we can see that Vo=0. The

Vs output versus frequency curve of the circuit given
RL Vo in the problem is shown in the following figure.
Therefore,
Vo RL
= (finite value) 0 1
Vs RL + Rs LC
1
At w =
Therefore, the given circuit represents a band-
, the circuit can be represented as
LC reject filter.
shown in the following figure. Ans. (d)
1. A driving point admittance function has pole and The state equation matrix is
zero locations as shown in the following figure. The
function can be realized using passive elements for x1 0 1 x1 0
s greater than . x = 2 3 x + u(t)
2 2
with initial condition x(0+) = [0, 1]T. The above

j equation is of the form
Pole
j1
x = Ax(t) + f (t)
s-plane
Zero Therefore,
2 1 1
s 1
(sI A)1 =
2 s + 3
j1 s+3 1
Pole (s + 2)(s + 1) (s + 2)(s + 1)
=
2 s
(s + 2)(s + 1) (s + 2)(s + 1)
Solution. For the function to be realized using
passive elements, s 1 > 0. Therefore, s > 1.
Ans. (1) Now,
2. The differential equation for a system is f(t) = L1[(sI A)1 ]

d2y 2et e2t et e2t
dy
+3 + 2y = f (t) . The response of the system
2 = 2 t
2et 2e2t et
dt dt
at t for f(t) = u(t) is . [Given that 2e
the initial conditions y(0+) = 0 and dy/dt(0+) = 1.]
The solution to the matrix state equation is
Solution. Let the state variables be
t
dy x(t) = f (t)x(0+ ) + f (t t )f (t )dt
x1 = y and x2 =
dt 0

Only the first component of x(t) is of interest. t

Therefore, = et e2t + [e(tt ) e2(tt ) ](1)dt
x1(t) = y(t) 0
2 t
= 0.5 0.5e
0
= [2et e2t et e2t ]
1
Therefore, for t , we have x1(t) 0.5.
0
t
(t t ) 2(t t ) (t t ) 2(t t )
+ [2e e e ] dt
u(t )
e Ans. (0.5)
0
PRACTICE EXERCISE
x 0 x1 1
(c) 1 = 1
normal-form equations are (Given that the current x 0 2 x + 1 u and
through the 0.1H inductor is i1.) 2 2
x
y = [ 4 4 ] 1
0.1 H 0.3 H x2
x 0 x1 1
(d) 1 =
2
+
x2 0 2 x2 1
u and
4
+
2t2u(t)V 3et2 A x
y = [4 4] 1
x2
(2 Marks)
3. A system has the transfer function given by
s2 + 3s + 9
= 10i1 + et (4.5t 30) + 5t2 u(t)
di1 2 Y (s)
(a) = 5 .
dt U (s) 5s + 8s4 + 24s3 + 34s2 + 23s + 6
= 10i1 + et (4.5t 30) + 5t2 u(t)

di1 2
(b) The state equation matrix is
dt
x1 1 1 0 0 0 x1 0
= 10i1 et (4.5t 30) + 5t2 u(t) x 0 1 0 x2 1
di1 2
2
(c) 1 0
dt (a) x3 = 0 0 1 0 0 x3 + 1 u(t) and
x4 0 0 0 2 0 x4 1
(d) 1 = 10i1 + et (4.5t 30) 5t2 u(t)
di 2
dt x 0 0
5 0 0 3 x5 1
x1
(2 Marks)
x
2
y(t) = [3.5 4.75 5.875 7 1.125] x3
2. A system has the transfer function given by
x4
Y (s) 4
= . The state equation matrix is
U (s) (s + 1)(s + 2) x
5
x 2 0 x1 1 x1 1 1 0 0 0 x1 0
x 0 1 0 x2 0
(a) 1 =
2 x2 1
+ u and

2 2
x 0 1 0
(b) x3 = 0 0 1 0 0 x3 + 1 u(t) and
x
y = [ 4 4 ] 1 x4 0 0 0 2 0 x4 1
x2 x 0
5 0 0 0 3 x5 1
x 1 0 x1 1 x1
(b) 1 = + x
x2 0 2 x2 0
u and
2
y(t) = [3.5 4.75 5.875 7 1.125] x3
x
y = [4 4] 1 x4
x2 x
5

x1 1 1 0 0 0 x1 0 1
x 0 1 0 x2 0
s+

1 0 Vo (s) CR1
(c) x3 = 0 0 x3 + 0 u(t) and
2
0 1 0 (a) V (s) =
1 R R + R2
x4 0 0 x4 1
i
0 0 2 s2 + + 2 s+ 1
x 0 0 33 x5 1 1
R C L LCR1
5 0 0
x1 R2 1
x s + L s + CR
Vo (s) 1
2
y(t) = [3.5 4.75 5.875 7 1.125] x3 (b) V (s) =
i 1 R R + R2
x4 s2 + + 2 s+ 1
x R1C L LCR1
5
R2
s+
x1 1 1 0 0 0 x1 0 Vo (s) L
x 0 1 0 x2 0 (c) V (s) = 1 R2
2
1 0 R + R2
0 x3 + 1 u(t) and
i 2

(d) 3 = s + + s+ 1
1
x 0 0 1 0 R C L LCR1
x4 0 0 0 2 0 x4 1
x 0
5 0 0 0 3 x5 1 (d) None of these
(2 Marks)
x1
x 6. For the network shown in the following figure, the
2 transfer function is (Given that R = 100 , L = 10 H
y(t) = [3.5 4.75 5.875 7 1.125] x3
x4 and C = 1 mF.)
x
5 C
(2 Marks) + +
4. For the network shown in the following figure, the Vi(t) L R Vo(t)
driving point impedance as a function of s is

+ R +
Vo ( jw ) ( jw )2
(a) =
Vi(t) C L Vo(t) Vi ( jw ) ( jw )2 + (10 jw ) + 100
Vo ( jw ) (100 jw )2

(b) =
Vi ( jw ) (100 jw )2 + (10 jw ) + 1
Vo ( jw ) ( jw )2
2 (c) =
(a) Z(s) =
s LCR + sL + R Vi ( jw ) ( jw )2 + ( jw ) + 1
s2 LC + 1 V ( jw ) 1
s2 LCR + sL + R (d) o =
(b) Z(s) = Vi ( jw ) ( jw ) + (10 jw ) + 100
2
s2 LC (2 Marks)
s2 LCR + sC + R 7. The network in Question 6 is a
(c) Z(s) =
s2 LC + 1 (a) high-pass filter (b) low-pass filter
s2R + sL + LC (c) band-pass filter (d) band-reject filter
(d) Z(s) = (1 Mark)
s2R + 1
(1 Mark) 8. The state equation in phase variable form of the
d3y d2y dy
5. For the network shown in the following figure, the differential equation 2 3 + 4 2 + 6 + 8y =
dt dt dt
transfer function as a function of s is
10u(t) is (Denote the state variables as x1, x2, ..., xn.)
+ + x1 1 0 0 x1 0
R1
(a) x2 = 0 0 x2 + 0 u(t) and

R2 1
Vi(t)
C x3 4 3 2 x3 5
Vo(t)
x1
y = [1 0 0 ] x2
L

x3

x1 0 1 0 x1 0 vc1 1 0 4 vc1 1 0

v
(b) x2 = 0

1 x2 + 0 u(t) and (a) vc 2 = 0 2 2 vc 2 + 0 2 i

0

x3 4 3 2 x3 5 0 iL 0 0 s
i
iL 0.5 0.5
x1 vc1 1 1 4 vc1 1 0
y = [1 1 1] x2 (b) vc 2 = 0 2
v
2 vc 2 + 0 2 i

i
x3 iL 0.5 0.5 0 iL 1 0 s
x1 0 1 0 x1 0
vc1 1 0 4 vc1 1 0
(c) x2 = 0 1 x2 + 0 u(t) and v
(c) vc 2 = 1 2 vc 2 + 0 2 i
0
2
x3 4 3 2 x3 5 i
0 iL 1 0 s
iL 0.5 0.5
x1
y = [1 0 0 ] x2 vc1 1 0 4 vc1 1 0
v
x3 (d) vc 2 = 0 2 2 vc 2 + 1 2 i

1 iL 0 0 s
i
x1 0 1 0 x1 1 iL 0.5 0.5
(d) x2 = 0 1 x2 + 1 u(t) and

0 (2 Marks)
x3 4 3 2 x3 5 10. For the circuit shown in the following figure, the
x1 current transfer function is
y = [1 0 0 ] x2
1H
x3
(2 Marks) Io
9. For the network shown in the following figure, the +
state equation in matrix form is Is 1 Vo 1H 1

4 vc1 2H vc2
iL
s s+1
0.25 F (a) 2
(b) 2
1
+ s + 3s + 1 s + 3s + 1
vi 0.5 F is
s+2
(c) 2
(d) None of these
s + 3s + 1
(2 Marks)
0
Numerical Answer Questions 4. For the network in Question 1, find the value of R
(in ohms).
1. The circuit shown in the following figure has imp- (1 Mark)
1000(s + 1) 5. For the network in Question 1, find the new value
edance given by Z(s) = .
(s + 1 + j50)(s + 1 j50) of R (in ohm) that will raise the resonant frequency
Find the value of C (in Farads). by a factor of 1000.
(2 Marks)
R
6. For the network in Question 1, find the new value
of G (in Seimens) that will raise the resonant fre-
C G quency by a factor of 1000.
L (2 Marks)
Z(s) 7. For the network in Question 1, find the new value
of L (in Henry) that will raise the resonant fre-
(2 Marks)
quency by a factor of 1000.
2. For the circuit in Question 1, find the value of G (2 Marks)
(in Siemens).
(1 Mark) 8. For the network in Question 1, find new value of C
(in Farads) that will raise the resonant frequency
3. For the network in Question 1, find the value of L
by a factor of 1000.
(in Henry).
(1 Mark) (1 Mark)

1. (a) The elements connected to the upper central Hence,

node are the two inductors and the current source.
x2 = 2x2 + u
Therefore, we need to place one inductor in the tree
as shown in the following figure. Writing in matrix form, we get
x1 1 0 x1 1 x1
x = 0 2 x + 1 u and y = [ 4 4] x
i1
2 2 2
3. (d) It is given that

+
3et2 Y (s) s2 + 3s + 9
= 5
2t2 u(t) U (s) 5s + 8s4 + 24s3 + 34s2 + 23s + 6

Therefore,
3. 5 4.75 5.875 7 1.125
The two forcing functions and the single state Y (s) = 3
+ 2
+ +
variable, current i1 are shown in the graph. The (s + 1) (s + 1) s +1 s+ 2 s+ 3
current directed to the right in the 0.3 H inductor Converting into matrix form, we get
2
is i1 + 3et , the voltage across the inductor is
x1 1 1 0 0 0 x1 0
d(i + 3et )
2
0.3 1 = 0.3 i1 1.8 tet

2 x 0 1 0 x2 0
2
1 0
dt x
3 = 0 0 1 0 0 x3 + 1 u(t)
The voltage across the 4 resistor is x4 0 0 0 2 0 x4 1
x 0
5 3 x5 1
4i1 + 12et
2 0 0 0
The normal-form equation is x1

x
2
di
0.1 1 + 0.3 1 1.8tet + 4i1 + 12et 2t2 u(t) = 0 and y(t) = [3.5 4.75 5.875 7 1.125] x3
di 2 2
x4
dt dt
x
That is, 5
= 10i1 + et (4.5t 30) + 5t2 u(t)

di1 2
4. (a) Driving the point impedance,
dt
1 (1/sC )(sL)
Z(s) = R + sL = R +
2. (c) It is given that the transfer function is sC (1/sC ) + sL
Y (s) 4 4 4 Solving the above equation, we get

= =
U (s) (s + 1)(s + 2) s + 1 s + 2 s2 LCR + sL + R
Z(s) =
Therefore, s2 LC + 1
4U (s) 4U (s)
Y (s) = = 4X1(s) 4X2 (s) 5. (b) The transfer function is given by
s+1 s+ 2
Vo (s) R2 + sL
=
Where V i (s) R2 + sL + {(R1/sC )/[R1 + (1/sC )]}
U (s)
X1(s) = Solving the above equation, we get
s+1
Vo (s) [s + (R2/L)] [s + (1/CR1 )]
Therefore, = 2
x1 = x1 + u
V i (s) s + [(1/R1C ) + (R2/L)]s + [R1 + (R2/LCR1 )]
U (s) 6. (a) Let the equivalent impedance of the parallel
X2 (s) =
s+2 impedance of L and R be Z. Therefore, Z is given by

jwLR and
Z = ( jwL) R =
R + jwL 0.5
dvc 2
iL + vc 2 is = 0 or vc 2
dt
The transfer function is given by = +2iL 2vc 2 + 2is
Vo ( jw ) Z The loop equation is
=
Vi ( jw ) Z + (1/jwC )
+ vc 2 vc1 = 0 or iL = 0.5vc1 0.5vc 2
diL
jwLR/(R + jwL) 2
= dt
[ jwLR/(R + jwL)] + (1/jwC )
The node and loop equations can be expressed in
Solving the above equation, we get matrix form as
vc1 1 0 4 vc1 1 0
Vo ( jw ) ( jw )2 LRC v = 0 v
c2 2 vc 2 + 0 2 i

2
is
=
Vi ( jw ) ( jw )2 LRC + (R + jwL)
iL 0.5 0.5 0 iL 0 0
( j)2 LRC 10. (a) The current transfer function is
=
( jw )2 LRC + ( jw )L + R
I o (s)
Substituting the values of R, L and C in the above I s (s)
equation, we get The current source Is can be converted into volt-
age source as shown in the following figure. In the
Vo ( jw ) ( jw )2 given figure, the parallel combination of 1 H induc-
tor and 1 resistor are replaced by their imped-
=
Vi ( jw ) ( jw )2 + (10 jw ) + 100
ances in s-domain. Therefore, impedance is
7. (a) From the transfer function, we can see that the s
given network behaves as a high-pass filter. Z = s1 =
s+1
8. (c) The differential equation is of third order;
hence, there are three state variables, namely, 1 s
x1 = y, x2 = y and x3 = y
+
The first derivatives are + Vo
Is = 1 Z

x1 = x2 , x2 = x3 and x3 = 4x1 3x2 2x3 + 5u(t)
In matrix form, the above equations can be writ-

ten as The voltage Vo(s) is given by
x1 0 1 0 x1 0 Z
x = 0 [I (s) 1]
1 x2 + 0 u(t)
Vo (s) =
2 Z + s+1 s

0
x3 4 3 2 x3 5 s/(s + 1)
= [I (s)]
x1 [s/(s + 1)] + (s + 1) s
and y = [1 0 0] x2

sI s (s)
=
x3 2
s + 3s + 1
9. (a) The state variables are the current through the The current Io(s) is
2 H inductor (iL), voltages across the 0.25 F capaci- Vo (s)
tor (vc1) and 0.5 F capacitor (vc2). The node equa- 1
tions are
Therefore,
dv v vi
0.25 c1 + iL + c1 = 0 or vc1
dt 4 sI s (s) I o (s) s
I o (s) = or = 2
= vc1 4iL + vi 2
s + 3s + 1 I s (s) s + 3s + 1

1. For the given network, 3. Refer to the Solution of Question 1 and
1 1 GR + 1
= G + jw C + = 2501
Z R + jwL LC
Therefore,
Solving the above equation for Z, we get
R + 1000
= 2501
j(w /C ) + (R/LC ) R
Z=
w + jw [(R/L) + (G/C )] + [(GR + 1)/LC ]
2 Therefore,
1000
It is given that impedance Z is R= = 0.4
2500
1000(s + 1) Hence,
Z(s) =
(s + 1 + j50)(s + 1 j50) L = 0.4 H
1000( jw + 1) Ans. (0.4)
=
( jw + 1 + j50)( jw + 1 j50) 4. From the Solution of Question 2, we have
1000( jw + 1)
=
(w 2 + 2 jw + 2501)
R = L (1)
From the Solution of Question 3, we have
Comparing the two impedances, we get
L = 0.4 H (2)
1
= 1000 Using Eqs. (1) and (2), we get
C
Therefore, R = 0.4
Ans. (0.4)
C = 1 mF = 0.001 F 5. The frequency scaling factor is
Ans. (0.001) Kf = 1000
2. Refer to the Solution of Question 1 The values of R and G are unaffected by frequency
scaling. Therefore,
R
= 1000
LC R = 0.4 and G = 1 mS
Ans. (0.4)
Therefore,
6. Refer to the solution of Question 5.
R=L G = 1 mS
Now, = 0.001 S
Ans. (0.001)
R G 7. The new value of the inductance is
+ =2
L C L 0.4
L = = = 0.0004
Therefore, Kf 1000
Ans. (0.0004)
G=C
8. The new value of the capacitance is
Thus,
C 103
G = 1 mS = 0.001 S C = = = 1 F
Kf 1000
Ans. (0.001) Ans. (1)

1. The driving-point impedance Z(s) of a network has Solution. For stability, poles and zeros interlace
the pole-zero locations as shown in the following on real axis. Since it is RC network, pole should
figure. If Z(0) = 3, then Z(s) is come first and zero should come at last.
Ans. (d)
Im
3. The first and the last critical frequencies (singu-
s-plane larities) of a driving point impedance function of a
1 passive network having two kinds of elements, are
a pole and a zero respectively. The above property
will be satisfied by
Re (a) RL network only
3 1 (b) RC network only
(c) LC network only
1 (d) RC as well as RL networks
denotes zero (GATE 2006: 2 Marks)
denotes pole
Solution. RC impedance function has the first
critical frequency due to pole and last critical fre-
3(s + 3) 2(s + 3) quency due to zero.
(a) 2
(b) 2
s + 2s + 3 s + 2s + 2 Ans. (b)
3(s 3) 2(s 3) 4. A negative resistance Rneg is connected to a pas-
(c) (d) sive network N having driving point impedance as
s 2s 2
2
s 2s 3
2
shown below. For Z2(s) to be positive real,
Solution. The impedance Z(s) is given by Rneg
K(s z) N
Z(s) =
(s p1 )(s p2 )
K(s + 3)
=
(s + 1 + j)(s + 1 j)
K(s + 3)
=
(s + 1)2 + 1 Z2(s) Z1(s)
It is given that (a) Rneg Re Z1( jw ), w
Z(0) = 3 (b) Rneg Re Z1( jw ) , w

Therefore, (c) Rneg Im Z1( jw ) , w
3K
= 3 or K = 2 (d) Rneg Z1( jw ) , w
2
Hence, Ans. (a)
2(s + 3) 5. The RC circuit shown in the following figure is
Z(s) = 2
s + 2s + 2
R C
Ans. (b)
+ +
2. The first and the last critical frequency of an
RC-driving point impedance function must, respec-
tively, be
Vi R C Vo
(a) a zero and a pole (b) a zero and a zero
(c) a pole and a pole (d) a pole and a zero

(GATE 2005: 1 Mark)

(a) a low-pass filter (b) a high-pass filter C1 L1

(c) a band-pass filter (d) a band-reject filter
+ +
(GATE 2007: 1 Mark)
Solution. At w , the capacitor acts as a short
circuit element and the circuit looks like as shown Vi R Vo

R
Filter 1
+ +
C2 = 4C1 L2 = L1/4
Vi R Vo
+ +
Vi R Vo
Therefore,

Vo
=0 Filter 2
Vi
(a) 4 (b) 1
At w 0, the capacitor acts as an open circuit 1 1
and the circuit looks like as shown in the following (c) (d)
2 4
figure.
R Solution. The bandwidth of series RLC circuit is
+ + R
L
The bandwidth of filter 1 is
Vi R Vo R
B1 =
L1
The bandwidth of filter 2,

R
B2 =
Therefore, L2
Vo It is given that
=0
Vi L1
L2 =
The frequency response of the circuit is shown in 4
the following figure: Therefore,
B1 1
Vo/Vi =
B2 4
Ans. (d)
7. The driving point impedance of the following net-
0.2s

work is given by Z(s) = 2 . The compo-
s + 0.1s + 2
nent values are
From this graph, we can see that the circuit is a
band-pass filter.
Ans. (c)
Z(s)
6. Two series resonant filters are as shown in the fol- L C R
lowing figure. Let the 3 dB bandwidth of filter 1 be
B1 and that of filter 2 be B2. The value of B1/B2 is

(a) L = 5 H, R = 0.5 , C = 0.1 F R

(b) L= 0.1 H, R = 0.5 , C = 5 F + +

(c) L = 5 H, R = 2 , C = 0.1 F
(d) L=0.1 H, R = 2 , C = 5F
Vi Z Vo
Solution. It is given that the impedance is

0.2s Therefore, the transfer function is
Z(s) = 2
s + 0.1s + 2 Z RL
Therefore the admittance is H(s) = =
Z + R (RL + R) + sRRL C
s2 + 0.1s + 2 s 1 2
Y (s) = = + + If R = RL , then
0.2s 0.2 2 0.2s
10 1
= 5s + 0.5 + H(s) =
s 2 + sRC
The admittance Y(s) of a parallel RLC circuit is Therefore,
given by RL = R
1 1 Ans. (c)
Y (s) = Cs + + V2 (s)
R Ls 9. The transfer function of the circuit shown
as follows is V1(s)
Therefore,
C = 5F 100 F
+ +
1
R= = 2
0.5
10 k
1
L= = 0.1 H V1(s) V2(s)
10
Ans. (d) 100 F

8. If the transfer function of the following network is
Vo (s) 1 0.5s + 1 3s + 6
= . (a) (b)
V i (s) 2 + sCR s+1 s+2
R s+2 s+1
+ + (c) (d)
s+1 s+2
(GATE 2013: 1 Mark)
Vi C RL Vo
Solution.
V2 (s) 10 103 + (1/100 106 s)

=
The value of the load resistance RL is V1(s) 10 103 + (1/100 106 s) + (1/100 106 s)
R R s 104 + 104
(a) (b) =
4 2 s 104 + 104 + 104
(c) R (d) 2R 104 (1 + s)
(GATE 2009: 1 Mark) =
104 (s + 2)
Solution. The parallel combination of RL and C is
replaced by impedance Z as shown in the following Therefore,
figure. The impedance is V2 (s) s + 1
RL =
Z= V1(s) s + 2
1 + sRL C Ans. (d)

PART II: ELECTRONIC DEVICES
9
8
7
Number of Questions
6
5 Marks 1
4 Marks 2
Total number of questions
3
2
1
0
2015 2014 2013 2012 2011 2010 2009

146 Part II: ELECTRONIC DEVICES
Year Topic
2015 Silicon resistivity
Carrier transport in silicon: Diffusion current, Drift current, Mobility and Resistivity
MOSFET
Basics of LASERs
Zener diode
BJT
MOS capacitor
P-N junction diode
Energy band diagram
2014 Carrier transport in silicon: Diffusion current, Drift current, Mobility and Resistivity
MOSFET
Basics of LASERs
BJT
Generation and recombination of carriers
Silicon resistivity
N-tub, P-tub
Device technology: Integrated circuits
P-N junction diode
Extrinsic silicon
MOS capacitor
Band diagram
2013 P-N junction diode
Fabrication process of CMOS
Zener diode
P-N junction diode
BJT
MOS capacitor
P-N junction diode
Zener diode
BJT
MOSFET
P-N junction diode
BJT
MOSFET
P-N junction diode
MOSFET

CHAPTER 8
SEMICONDUCTOR PHYSICS
In this chapter, energy bands in silicon, intrinsic and extrinsic silicon; carrier transport in silicon: diffusion current, drift
current, mobility and resistivity; and generation and recombination of carriers are covered.
8.1 SEMICONDUCTOR MATERIALS valence shell, that is, the outer most shell, are referred
to as the valence electrons.) Valence electrons are tightly
bound to the atom, so there are no free electrons that
Materials, in general, can be classified as insulators, can move through the material. Some of the popular
conductors and semiconductors depending upon their insulator materials are mica, glass, quartz, etc.
conductivity levels. The energy band structure of an insulator is shown
inFig. 8.1. It shows that here is a large forbidden band
8.1.1 Insulators gap of greater than 5eV between the valence and the
conduction energy bands of an insulator. For example, the
Insulators are materials that offer a large resistance to band gap of diamond is approximately equal to 5.5eV.
the flow of current through them. The typical resistivity Because of this large forbidden band-gap, there are very
level of an insulator is of the order of 1010 to 1012cm. few electrons in the conduction band and hence the con-
Therefore, the application of voltage across the insulator ductivity of an insulator is poor. Even an increase in the
results in negligible flow of current. If one looks at the temperature or the energy of the applied electric field
atomic structure of insulators, one finds that they have is insufficient to transfer the electrons from the valence
seven to eight valence electrons. (The electrons in the band to the conduction band.

148 Chapter 8: Semiconductor Physics
Conduction band
1 Valence
electron
Forbidden
band gap
(>5 eV)
Valence
Valence band electrons
Nucleus
Figure 8.1| Energy band diagram of an insulator.
(a)
8.1.2 Conductors
Conductors are materials that offer very little resistance to

the flow of current through them, that is, they support a Free
generous flow of current when an external electric field electrons Conduction
band
is applied across their terminals. Resistivity level of con
ductors is of the order of 104 to 106 cm. Generally,
conductors have three or less than three valence electrons.
These electrons are loosely bound and are free to move Valence Valence and
band conduction
through the material. Metals such as copper, aluminium,
bands overlap
gold, and silver are good conductors. Figure8.2(a) shows
the atomic structure of copper. Copper has one valance
electron and hence is a good conductor. Figure 8.2(b) (b)
Figure 8.2|(a) Atomic structure of a conductor (copper).

shows the energy band diagram of a conductor. The
valence and the conduction bands overlap and there is
no energy gap to overcome for the electrons in order (b) Energy band diagram of a conductor.
to move from the valence band to the conduction
band. This implies that there are free electrons in the
A look at the band structure of semiconductors (Fig. 8.4)
conduction band even at absolute zero temperature
suggests that the forbidden energy gap is of the order of
(0K). Therefore, when an external electric field is applied,
1eV. For example, the band gap energy for silicon, ger-
there is a large flow of current through the conductor.
manium and gallium arsenide is 1.21eV, 0.785eV and
1.42eV, respectively, at absolute zero temperature (0K).
8.1.3 Semiconductors At 0K and at low temperatures, valence band electrons
do not have sufficient energy to cross the energy band gap
Semiconductors are materials that have conductivity and reach the conduction band. Thus, semiconductors act
levels somewhere between the extremes of a conductor as insulators at 0K and at low temperatures. As the tem-
and an insulator. The resistivity level of semiconductors perature is increased, a large number of valence electrons
is in the range of 10104 cm. Two of the most com- acquire sufficient energy to leave the valence band, cross
monly used semiconductor materials are silicon (Si) and the energy band gap and reach the conduction band.
germanium (Ge). Silicon has 14 orbiting electrons and These are now the free electrons as they can move freely
germanium has 32 orbiting electrons as shown in Figs. under the influence of an external applied electric field. At
8.3(a) and (b), respectively. As is evident from the figure, room temperature (300K), there are sufficient electrons
both silicon and germanium have four valence electrons. in the conduction band and hence the semiconductor is
Materials having three and five valence electrons combine capable of conducting some current at room temperature.
with each other to form semiconductors. Examples of The absence of an electron in the valence band is referred
such semiconductors are gallium arsenide (GaAs) and to as a hole and is represented by a small circle as shown
indium phosphide (InP). The valence electrons in a semi- in Fig. 8.4. Both electrons and holes constitute the flow
conductor are not free to move as they are in a metal, of current in a semiconductor, whereas in the case of con-
but are trapped in bonds between adjacent atoms. ductors, the current is due to the flow of electrons only.

8.2 SEMICONDUCTOR TYPES 149
Valence
electrons
Valence
electrons
Nucleus Nucleus
(a) (b)
Figure 8.3| (a) Atomic structure of silicon. (b) Atomic structure of germanium.
germanium are the two most important semiconductors

Conduction band used. Other examples include gallium arsenide (GaAs)
and indium antimonide (InSb) and so on.
Free electrons
Forbidden (at room
band gap temperature) 8.2.1.1Structure
(1 eV)
Figure 8.5(a) shows the crystal structure of silicon at
Valence band Valence absolute zero temperature (0K). Because of the covalent
Holes electrons bonding, the valence electrons are tightly bound to the
Figure 8.4| Energy band diagram of a semiconductor.

nucleus and hence the crystal has poor conductivity at
low temperature. At room temperature, the thermal
energy is sufficient enough to break some of the covalent
bonds as shown in Fig. 8.5(b). The electrons are raised to
the conduction band and are referred to as free electrons
8.2 SEMICONDUCTOR TYPES
that are available for conduction. The absence of elec-
tron in the covalent bond means that the atom now has
In the discussion above, it is assumed that there are a positive charge referred to as a hole and is represented
no external atoms added to the parent semiconductor by a small circle in Fig. 8.5(b). Holes serve as a carrier of
material. Such semiconductors are referred to as intrin- electricity like free electrons. In fact, the motion of hole
sic semiconductors. Certain impurity atoms when added in one direction is equivalent to the motion of negative
to the intrinsic semiconductor materials increase their charge in the opposite direction.
conductivity. Such semiconductors, with added impurity Germanium also has four electrons in the valence
atoms, are called extrinsic semiconductors. Intrinsic and shell. Intrinsic semiconductors are also formed by
extrinsic semiconductors are discussed as follows. combination of atoms having three valence electrons with
atoms having five valence electrons. Examples include
gallium arsenide (GaAs) and indium antimonide (InSb).
8.2.1 Intrinsic Semiconductors In gallium arsenide, gallium atom has three valence elec-
trons and arsenic atom has five valence electrons. Other
Intrinsic semiconductors are semiconductors with very combinations are also possible, such as mercury, cadmium
low level of impurity concentration. They are essentially and tellurium bond to form mercury cadmium telluride
as pure as can be available through modern technology. (HgCdTe). Detailed description of these semiconductors
The purity levels are of the order of 1 part in 10 billion. is outside the scope of this book. However, the discussion
Conduction in intrinsic semiconductors is either due to for silicon semiconductors holds good for these intrinsic
thermal excitation or due to crystal defects. Silicon and semiconductors also.

Si crystal Si crystal
Si Si Si Si Si Si Si Si
+4 +4 +4 +4 +4 +4 +4 +4
Valence Free Valence

electrons electron Si Si Si Si electrons
Si Si Si Si
+4 +4 +4 +4 +4 +4 +4 +4
Nucleus and Hole Nucleus and
inner shells inner shells
Si Si Si Si Si Si Si Si
+4 +4 +4 +4 +4 +4 +4 +4
Covalent Covalent
Si Si Si Si bonds Si Si Si Si bonds
+4 +4 +4 +4 +4 +4 +4 +4
(a) (b)
Figure 8.5|(a) Crystal structure of silicon at absolute zero temperature. (b) Crystal structure of silicon at room temperature.
In a nutshell, it can be said that at low tempera- combine with holes present at the maximum of valence
tures of the order of 0K, the intrinsic semiconductor band while conserving momentum. The energy released
behaves as an insulator as no free carriers of electricity due to recombination is emitted in the form of photon
are available. of light. Hence, they are used in making light-emitting
diodes (LEDs) and laser diodes. Examples of direct band
8.2.1.2Types gap semiconductors include gallium arsenide and mercury
cadmium telluride. In an indirect band gap semiconduc-
Intrinsic semiconductors can be further classified as tor, the maximum energy of the valence band occurs at a
direct band gap semiconductors and indirect band gap different momentum value than the minimum energy of
semiconductors. In a direct band gap semiconductor, the the conduction band [Fig. 8.6(b)]. Hence, a direct transi-
maximum energy of the valence band occurs at the same tion across the band gap does not conserve momentum
momentum value as the minimum energy of the conduction and does not emit photons of light. Instead, the energy
band [Fig. 8.6(a)]. Thus, in a direct band gap semiconduc- in this case is released in the form of heat. Silicon and
tor, electrons present at the minimum of conduction band germanium are indirect band gap semiconductors.
Energy Energy
Conduction band Conduction band
Band gap Band gap
Valence band Valence band

Momentum Momentum
(a) (b)
Figure 8.6| (a) Direct band gap intrinsic semiconductor. (b) Indirect band gap intrinsic semiconductor.

8.2.1.3Charge Concentration current density. The expression for conductivity (s) is

as follows:
In an intrinsic semiconductor, the number of holes is
s = (nmn + pmp )q (8.4)
equal to the number of electrons. Hole and electron pairs
are generated by thermal agitation and disappear due to As in an intrinsic semiconductor, n = p = ni, therefore,
recombination. Therefore, in an intrinsic semiconductor,
J = (mn + mp )ni qe (8.5)
n = p = ni (8.1)

where n is the electron concentration (number of electrons/ and s = (mn + mp )ni q (8.6)
cm3), p is the hole concentration (number of holes/cm3)
and ni is the intrinsic concentration. 8.2.1.5Energy Band Gap
The value of ni is given by the following expression:
The forbidden energy band gap (also called energy band
-EG0 gap) of a semiconductor depends on its temperature and
ni2 3
= AT exp
kT
(8.2)
decreases with increase in temperature.

where T is the temperature in kelvin, EG0 is the energy For silicon, the energy band gap [Eg(T)] in eV at tempera
gap at 0K, k is the Boltzmann constant in eV/K and A ture T (K) is given by the following expression:
is the constant.
Eg (T ) = 1.21 - 3.60 10-4 T (8.7)
It is clear from Eq. (8.2) that the intrinsic concentration
ni increases with increase in temperature. and for germanium, it is given by
8.2.1.4Electrical Properties Eg (T ) = 0.785 - 2.23 10-4 T (8.8)

A semiconductor is a bipolar device, that is, both elec- where T is the temperature in kelvin.
trons and holes contribute to the flow of current. It may At room temperature (taken as 300K), the band
be mentioned here that metals are unipolar devices, that gap for silicon and germanium are 1.1eV and 0.72eV,
is, only electrons act as current carriers. In a semicon- respectively.
ductor, there are two different mechanisms of current
flow, namely, the electron flow in the conduction band 8.2.1.6Fermi Level
and the hole flow in the valence band. When an external
potential is applied, the free electron may either con- The probability that an energy level in a semiconduc-
tribute to the current by drifting through the crystal or tor is occupied by an electron is given by the following
combine with a hole in the valence band. The first com- expression:
ponent constitutes the electron flow in the conduction
band. When an electron combines with a hole, it leaves a 1
f (E ) = (8.9)
hole in its initial position. This hole may now be filled by 1 + exp[(E - EF ) kT ]
an electron from another covalent bond creating a hole
in its position and the process continues. This results in where f(E) is the FermiDirac probability function =
the motion of holes in a direction opposite to the direc- Probability of finding an electron in the energy state E, k
tion of motion of electrons. is the Boltzmann constant = 8.642 105eV/K, T is the
The mathematical expression for the current density in temperature in kelvin and EF is the Fermi level in eV.
any material is as follows: Fermi level represents the energy state with 50%
J = (nmn + pmp )qe (8.3) probability of being filled by an electron if no forbidden
energy band gap exists. In an intrinsic semiconductor at
where J is the current density in A/cm2 , n is the electron absolute zero temperature, the probability of finding an
concentration (number of electrons/cm3), p is the hole electron in the valence band is 100% and the probability
concentration (number of holes/cm3), mn is the mobility of of finding the electron in the conduction band is 0%.
an electron in the material in cm2/Vs, mp is the mobility The Fermi level in an intrinsic semiconductor at abso-
of a hole in the material in cm2/Vs, q is the charge of lute zero temperature lies at the centre of the forbidden
an electron = 1.6 1019 C and e is the applied electric band gap [Fig. 8.7(a)].
field in V/cm. As the temperature increases, some of the electrons
This current is due to the potential gradient created are excited to higher energy levels. They leave the
by the applied electric field and is referred to as drift valence band and jump to the conduction band. Thus,

Conduction band Conduction band

EC EC
(E + EV) (E + EV)
EF = C Band gap Band gap EF = C
2 2
FermiDirac EV EV FermiDirac
probability Valence band Valence band probability
curve at T = 0 K curve at T = 300 K
(a) (b)
Figure 8.7| (a) FermiDirac probability function of an intrinsic semiconductor at Absolute zero temperature.
(b) FermiDirac probability function of an intrinsic semiconductor at 300K.
the probability of finding an electron in the valence band are called donor atoms. Figure 8.8 shows the crystal
decreases and the probability of finding an electron in the structure of an N-type semiconductor material (Si). As is
conduction band increases [Fig. 8.7(b)]. The Fermi level evident from the figure, four of the five electrons of the
remains at the centre of the forbidden band gap and is pentavalent impurity atom (antimony) form covalent
given by bonds with four intrinsic semiconductor atoms and the
EC + EV fifth electron is loosely bound to the pentavalent atom
EF = and is relatively free to move within the crystal and is
2 referred to as the free electron. The energy required to
where EC is the energy of the conduction band and EV is detach this fifth electron from the atom is very small, of
the energy of the valence band. the order of 0.01eV for germanium and 0.05eV for silicon.
The effect of doping creates a discrete energy level
8.2.2 Extrinsic Semiconductors called donor energy level in the forbidden band gap
with energy level (ED) slightly less than the conduc-
Intrinsic semiconductors have very limited applications tion band (Fig. 8.9). The difference between the energy
as they conduct a very small amount of current. However, levels of the conduction band and this donor energy
the electrical characteristics of an intrinsic semiconduc- level is the energy required to free the electron (0.01eV
tor are significantly changed by adding impurity atoms for germanium and 0.05eV for silicon). At room tem-
to the pure semiconductor material. The impurities perature, almost all the fifth electrons from the donor
added are of the order of 1 part in 105 to 1 part in 108. materials are raised to the conduction band and hence
However, this small alteration results in large change in the number of electrons in the conduction band increases
the semiconductor material properties. As an example, significantly.
the conductivity is increased about 1000 times. This pro-
cess of addition of impurities is called doping and the
resultant semiconductor is called an extrinsic semicon-
ductor. If the added impurity is a pentavalent atom,
then the resultant semiconductor is called an N-type Free electron
+4 +4 +4 (Fifth valence
semiconductor and if the impurity added is trivalent in Si Si Si electron of Sb)
nature, then the semiconductor is referred to as P-type
semiconductor. Pentavalent
+4 +5 +4 impurity atom (Sb)
Si Sb Si
8.2.2.1N-Type Extrinsic Semiconductors
Intrinsic
An N-type semiconductor material is created by adding +4 +4 +4 semiconductor atom
approximately 1 part in 108 parts of pentavalent Si Si Si
impurities to the semiconductor material. Pentavalent
atoms are those atoms that have five valence electrons.
Some examples of pentavalent atoms are phosphorus,
antimony, arsenic, etc. Pentavalent impurity atoms Figure 8.8|Crystal structure of an N-type semiconductor (Si).

and NA negatively charged ions per cubic centimetre are

contributed by the acceptor atoms. Let us assume that
Conduction band
the concentration of free electrons and holes in the semi-
EC 0.05 eV(Si), conductor are n and p, respectively.
ED 0.01 eV(Ge)
Therefore, according to the law of electrical neutrality,
Donor
energy level ND + p = N A + n (8.10)
For an N-type semiconductor, NA = 0. Also, the con-

EV
centration of free electrons (n) is much greater than
Valence band the concentration of holes (p). Therefore, for an N-type
semiconductor, Eq. (8.10) reduces to the following form:
Figure 8.9| Energy band diagram of an N-type n ND (8.11)

semiconductor.
Hence, for an N-type semiconductor, the free-electron
In an N-type semiconductor, the number of electrons concentration is approximately equal to the concentra-
increase and the number of holes decrease as compared tion of donor atoms. Alternatively, the number of free
to what are available in an intrinsic semiconductor. The electrons is approximately equal to the number of donor
decrease in the number of holes is attributed to the atoms. Therefore, the current density in an N-type
increase in the rate of recombination of electrons with semiconductor is given by the following expression:
holes. Current in the N-type semiconductor is dominated
by electrons which are referred to as majority carriers. J N D m n qe (8.12)
Holes are the minority carriers in the N-type semicon-
ductor (Fig. 8.10). where mn is the mobility of free electrons in the semicon-
ductor (cm2/Vs) and e is the applied electric field (V/cm).
Conduction Ie Electron flow The expression for conductivity in an N-type semi-
band (Majority carriers) conductor is
Donor s ND mn q (8.13)

energy level
Fermi Level
The expression for FermiDirac probability function for
an extrinsic semiconductor is the same as that for the
Hole flow intrinsic semiconductor. The only change that occurs is in
Valence band Ih (Minority carriers)
the Fermi level. The Fermi level (Fig. 8.11) in an N-type
I= Ie + Ih semiconductor is raised and is closer to theconduction
+ band as there is a significant increase in the number of
V
Figure 8.10| Current flow in an N-type semiconductor.

Here I is the total conventional current
flow, Ie is the c urrent flow due to electrons Conduction band
Donor
and Ih is the current flow due to holes.
EC energy
ED level
Electrical Properties EF
Semiconductor materials are electrically neutral. According Fermi
to the law of electrical neutrality, in an electrically neutral level
material, the magnitude of positive charge concentration
EV
is equal to the magnitude of negative charge concentration.
Let us consider a semiconductor that has ND donor
atoms/cm3 and NA acceptor atoms/cm3, that is, the Valence band
concentrations of donor and acceptor atoms are ND and
NA, respectively. Therefore, ND positively charged ions
per cubic centimetre are contributed by the donor atoms Figure 8.11| Fermi level in an N-type semiconductor.

electrons in the conduction band and there are fewer

holes in the valence band. As the temperature increases,
more electronhole pairs are generated and the Fermi
level shifts towards the centre of the forbidden energy
band gap. +4 +4 +4
Si Si Si Trivalent
The Fermi level is given by the following expression:
impurity
N atom (B)
EF = EC - kT ln C (8.14) +4 +3 +4
ND
Si B Si
where EC is the bottom of the conduction band, k is the
Boltzmann constant in eV/K (8.642 105 eV/K), T is
Hole
the Temperature in kelvin, NC is the density of states in +4 +4 +4
the conduction band and is constant for a material at a Intrinsic
Si Si Si
given temperature and ND is the donor atom concentra- semiconductor
tion (number of atoms/cm3). atom
The value of NC is
Figure 8.12|Crystal structure of a P-type semiconductor (Si).
2pmnkTq
3/2
2
h2
where mn is the effective mass of an electron, T is the
temperature in kelvin, h is the Plancks constant and q is Conduction band
the electronic charge = 1.6 1019 C.
EC
Acceptor
8.2.2.2P-Type Extrinsic Semiconductors energy level
A P-type semiconductor is created by adding approxi- EA 0.08 eV(Si)
mately 1 part in 105 parts of trivalent impurity to the EV 0.01 eV(Ge)
intrinsic semiconductor. Trivalent atoms have three elec-
Valence band
trons in their valence shell and are called acceptor atoms
in the context of semiconductor devices. Examples of
Figure 8.13| Energy band diagram of a P-type
trivalent impurities include boron (B), indium (In) and
gallium (Ga). As there are three electrons in the valence
semiconductor.
shell of these trivalent impurity atoms, only three cova-
lent bonds can be formed with the neighbouring intrinsic
semiconductor atoms and a vacancy exists in the fourth number of electrons jump to the acceptor energy level
bond as shown in Fig. 8.12. This vacancy is referred to resulting in a large number of holes in the valence band.
as the hole and is represented by a small circle. The hole In a P-type semiconductor, the number of electrons
is ready to accept an electron from a neighbouring atom, decreases and the number of holes increases as compared
thereby creating a hole in the neighbouring atom. This to what are available in an intrinsic semiconductor. The
hole in turn is ready to accept an electron thereby creat- decrease in the number of electrons is attributed to the
ing another hole. In this way, the hole moves through increase in the rate of recombination of electrons with
the crystal. holes. Current in the P-type semiconductor is domi-
The effect of doping creates a discrete energy level called nated by holes, which are referred to as majority car-
acceptor level in the forbidden energy band gap with riers. Electrons are the minority carriers in a P-type
energy level (EA) just above the valence band (Fig. semiconductor material (Fig. 8.14). It may be mentioned
8.13). The difference between the energy levels of the here that the conductivity of an N-type semiconductor
acceptor band (EA) and the valence band (EV) is the is higher as compared to that of a P-type semiconduc-
energy required by an electron to leave the valence band tor as the mobility of electrons is greater than that of
and occupy the acceptor band and thereby leaving a hole holes. For the same level of doping in the N-type and the
in the valence band. The difference (EAEV) is of the P-type semiconductors, the conductivity of an N-type
order of 0.08eV for silicon and 0.01eV for germanium. As semiconductor is around twice compared to that of a
very small energy is required for the electron to leave the P-type semiconductor. Also, it may be noted in practi-
valence band and occupy the acceptor energy level, large cal semiconductors that the concentration of dopants is

8.3 LAW OF MASS ACTION 155
in an intrinsic semiconductor and is closer to the valence

Conduction band band as there is a significant increase in the number of
Ie Electron flow holes in the valence band and decrease in the number
(Minority carriers) of electrons in the conduction band. As the temperature
increases, more electronhole pairs are generated and the
Fermi level shifts towards the centre of the energy gap.
Acceptor
energy level
Conduction band
Ih Hole flow I
EC
Valence band (Majority carriers)
I = I h + Ie Fermi level
V
+ EF Acceptor
EA energy level
Figure 8.14| Current flow in a P-type semiconductor. EV
Here I is the total conventional current
flow, Ie is the current flow due to electrons Valence band
and Ih is the current flow due to holes.
Figure 8.15| Fermi level in a P-type semiconductor.

greater in P-type semiconductors (approximately 1 part
in 105 parts) as compared to that in N-type semiconduc- The Fermi level is given by the following expression:
tors (approximately 1 part in 108 parts).
N
EF = EV + kT ln V (8.18)
Electrical Properties NA
For a P-type semiconductor ND = 0. Also the con- where EV is the valence band energy level, NV is the
centration of free electrons (n) is much less than the density of states in the valence band and is constant for
concentration of holes (p). Therefore, for a P-type semi- a material at a given temperature and T is the tempera-
conductor, hole concentration is approximately equal to ture in kelvin.
the acceptor atom concentration. Therefore, NV is equal to
2pmpkTq
3/2
p NA (8.15) 2
h2
Alternatively, the number of holes in a P-type semicon-
ductor is approximately equal to the number of acceptor where mp is the effective mass of a hole, h is the Plancks
atoms. constant, T is the temperature in kelvin, q is the electronic
charge = 1.6 1019 C, k is the Boltzmann constant in
Therefore, the current density in a P-type semicon- eV/K = 8.642 10-5 eV/K and NA is the donor atom
ductor is given by the following expression:
concentration (number of atoms/cm3).
J NA mp qe (8.16)

where mp is the mobility of holes in the semiconductor 8.3 LAW OF MASS ACTION
(cm2/Vs) and e is the applied electric field (V/cm).
The expression for conductivity is The concentration of holes and electrons in a semiconduc-
tor are governed by the law of mass action. According
s NA mp q (8.17) to the law of mass action, the product of free-electron

concentration and hole concentration in any semiconductor
Fermi Level is constant and is given by the following expression:
As mentioned before, the FermiDirac probability func- np = ni2 (8.19)
tion for an extrinsic semiconductor is same as that for the
intrinsic semiconductor. The only change that occurs is where n is the free electron concentration (negatively
the change in the Fermi level. The Fermi level in a P-type charged carriers), p is the hole concentration (positively
semiconductor (Fig. 8.15) is lowered as compared to that charged carriers) and ni is the intrinsic concentration.

Therefore, the product of concentration of negative If the current is in the positive x- direction and B in the
and positive charge carriers in a semiconductor is inde- positive z- direction, a force will be exerted on the current
pendent of the type and amount of doping and is equal carriers in the negative Y direction. Thus, the carriers
to the square of the intrinsic concentration. Hence, in will accumulate on the side B as shown in Fig.8.16. For
an N-type semiconductor, as the number of electrons a P-type semiconductor, the holes will accumulate on
increases the number of holes decreases, and in a P-type side B and thus side B will be more positive than side
semiconductor, as the number of holes increases the A. Similarly, for N-type semiconductors and conductors,
number of electrons decrease. electrons will accumulate on side B and thus side A will
For an N-type semiconductor, be more positive than side B. The magnitude of the volt-
age will depend on the carrier concentration. Thus, the
n ND Hall effect can be used to determine the carrier concen-
tration and also whether the semiconductor is P type or
Therefore, N type.
ni2
p (8.20) The Hall voltage VH is given by the following
ND expression:
BIRH
For a P-type semiconductor, VH = (8.22)
d
p NA where B is the magnetic field in tesla, I is the current in
Therefore, amperes, RH is the Halls coefficient, d is the width of the
conductor or semiconductor in the direction of the mag-
ni2
n (8.21) netic field in metres and VH is the Hall voltage in volts.
NA
For conductors, the value of Halls coefficient RH is
given by
8.4 HALL EFFECT 1
RH = (8.23)
nq

Hall effect is a phenomenon by which a potential where n is the electron concentration and q is the elec-
difference is created on the opposite sides of a conductor tron charge.
placed in a magnetic field, with the current flowing in For semiconductors with both positive and negative
perpendicular direction to the magnetic field. The poten- carriers, the value of Halls coefficient RH is given by the
tial created is perpendicular to the direction of both the following expression:
magnetic field and the current. Stated differently, if a
pmp2
conductor or a semiconductor carrying current (I) is RH = nmn2 - (8.24)
placed in a transverse magnetic field (B), as shown in
q(nmn + pmp )2
Fig. 8.16, an electric field (e) is induced in a direction
perpendicular to both B and I. Edwin Hall discovered where mn is the electron mobility, mp is the hole mobility,
this effect in the year 1879. n is the electron concentration, p is the hole concentration
and q is the electron charge.
Hall effect is used in the design of instruments such
Y as magnetic field meter, Hall-effect multiplier, etc.
Magnetic field meters are used to measure the magnetic
field. Hall-effect multipliers give an output proportional
to the product of two signals. Here, I and B are made
A
proportional to the two signals.
I + I VH
X 8.5 DRIFT AND DIFFUSION
The carriers CARRIERS
bend towards
side B B
The current in a semiconductor is the sum of the drift
B current and the diffusion current as opposed to a con-
Z
ductor where the current flow is only due to the drift
Figure 8.16| Hall effect. phenomenon. As discussed in Section 8.2, drift current is

IMPORTANT FORMULAS 157
due to the potential gradient in the semiconductor and increases with distance and is negative if the hole con-
is given by the following expression: centration decreases with distance.
J = (nmn + pmp )qe (8.25) Similarly, the electron diffusion current density is

2 given by the following expression
where J is the current density in A/cm , n is the free-
electron concentration in the material (number of free dn
J n = qDn (8.29)
electrons/cm3), p is the hole concentration in the mate- dx
rial (number of holes/cm3), mn is the mobility of an elec- where Dn is the diffusion constant of electrons in cm2/s
tron in the material in cm2/Vs, mp is the mobility of a and dn/dx is the variation of electron concentration with
hole in the material in cm2/Vs, q is the charge of an distance x, which is positive when the concentration of
electron = 1.6 1019 C and e is the applied electric field electrons increases with distance and is negative if the
in V/cm. concentration of electrons decreases with distance.
The drift current density due to holes is given by the The diffusion constant of a carrier is related to its
following expression: mobility and is given by the following expression (also
J p = pmp qe (8.26) known as Einstein equation):

The drift current density due to electrons is given by the Dp D
= n = VT (8.30)
following expression: mp mn
J n = nmn qe (8.27) where VT is the volt equivalent (or thermal voltage) of

Diffusion current is caused by the concentration gradient temperature = kT (k is the Boltzmann constant in eV/K
in the semiconductor, that is, when there is non-uniform and T is the temperature in kelvin).
concentration of charge particles in a semiconductor. Therefore, the total current is the sum of the diffusion
The hole diffusion current density is given by the fol- and drift currents. The total hole current density is given
lowing expression: by the following expression:
J p = pmp qe - qDp
dp dp
J p = -qDp (8.28) (8.31)
dx dx
where Dp is the diffusion constant of holes in cm2/s and The total electron current density is given by the follow-
dp/dx is the variation in hole concentration with dis- ing expression:
J n = nmn qe + qDn
tance x, which is positive when the hole concentration dn
(8.32)
dx
IMPORTANT FORMULAS
1. In an intrinsic semiconductor, n = p = ni 8. Current density in an N-type semiconductor is

-EG0 J N D m n qe
2. ni2 = AT 3 exp
kT 9. Conductivity in an N-type semiconductor is
3. Current density in any material is
s ND mn q
J = (nmn + pmp )qe
4. Conductivity 10. The Fermi level for N-type semiconductor is
s = (nmn + pmp )q N
EF = EC - kT ln C
5. For silicon, the energy band gap [Eg(T)] at tem- ND
2pmnkTq
perature T (K) is 3 /2
Eg (T ) = 1.21 - 3.60 10-4 T

where NC = 2
h2
6. For germanium, the energy band gap [Eg(T)] at 11. Current density in a P-type semiconductor is
temperature T (K) is J NA mp qe
-4
Eg (T ) = 0.785 - 2.23 10 T 12. Conductivity for P-type semiconductor is
7. The probability that an energy level in a semicon- s NA mp q
ductor is occupied by an electron is
13. Fermi level for P-type semiconductor is
1
f (E ) =
E - EF N
EF = EV + kT ln V
1 + exp
kT NA

2p mp kTq
3 /2 20. Drift current in the semiconductor is given by
where N V = 2
h2 J = (nmn + pmp )qe
14. According to law of mass action, product of con-
centration of holes and electrons in any semicon- 21. The hole diffusion current density is given by
ductor is constant and is given by np = ni2 dp
J p = -qDp
15. For an N-type semiconductor, dx
ni2
p
22. The electron diffusion current density is
ND
dn
16. For a P-type semiconductor, J n = qDn
dx
ni2
n 23. The diffusion constant of a carrier is related to its
NA
mobility and is given by Einstein equation
17. The Hall voltage (VH) is given by
BIRH Dp Dn
= = VT
mp mn
VH =
d
18. For conductors, the value of Halls coefficient RH is
24. The total hole current density is given by
given by
1
J p = pmp qe - qDp
RH = dp
nq dx
19. For semiconductors, the value of Halls coefficient
25. The total electron current density is given by
RH is given by
pmp2 J n = nmn qe + qDn
dn
RH = nmn2 -
q(nmn + pmp )2
dx
SOLVED EXAMPLES
1. Consider two energy levels: E1, EeV above the 2. Doping of semiconductor is
Fermi level, and E2, EeV below the Fermi level. P1 (a) the process of purifying semiconductor materials
and P2 are, respectively, the probabilities of E1 being (b) the process of adding certain impurities to the
occupied by an electron and E2 being empty. Then semiconductor material in controlled amounts
(a) P1 > P2 (c) the process of converting semiconductor mate-
(b) P1 = P2 rial into some form of active devices
(c) P1 < P2 (d) one of the steps used in fabrication of ICs
(d) P1 and P2 depend on the number of free Solution. Doping of a semiconductor is a process
electrons of adding certain impurities to the semiconductor
material in controlled amounts to alter its properties
Solution. Given that Fermi level probability Ans. (b)
P1 = E1 and Fermi level probability P2 = E2
We know that 3. The width of forbidden gap in semiconductor mate-
rials is about
1 (a)10 eV (b)100 eV (c) 1eV (d) 0.1eV
f (E ) = (E -EF )/kT
1+e
Solution. Conductors have zero forbidden gap,
where f(E) is the FermiDirac probability function insulators have forbidden gap of greater than 5eV
and EF is the Fermi level. and semiconductor materials have band gap in the
Therefore, P1 < P2 vicinity of 1eV.
Ans. (c) Ans. (c)

SOLVED EXAMPLES 159
4. In an intrinsic semiconductor, the free-electron where T is the temperature in kelvin. Therefore, at

concentration depends on T = 300K,
(a) effective mass of electrons only Eg (T ) = 0.785 - 2.23 10-4 300 = 0.785 - 0.0669
(b) effective mass of holes only
= 0.7181 eV
(c) temperature of the semiconductor Ans. (d)
(d) width of the forbidden energy band of the
semiconductor 6. According to the Einstein relation, for any semi-
conductor the ratio of diffusion constant to mobility
Solution. By law of mass action, of carriers
np = ni2 (a) d
epends upon the temperature of the
semiconductor
where ni is the intrinsic carrier concentration, p
(b) depends upon the type of the semiconductor
is the hole concentration and n is the electron
(c) varies with life time of the semiconductor
concentration.
(d) is a universal constant
We know that
ni2 T 3 /2
Solution. Einstein equation states that
For intrinsic semiconductor, n = p = ni. Therefore,
D D Dp T (K)
ni T 3 /2 = n = = VT =
m mn mp 11600
Ans. (c)
5. The band gap energy of germanium at 300 K is where T is the temperature in kelvin, VT is the
thermal voltage, D is the diffusion constant, m is
(a) 0.785eV (b) 1.121eV the mobility, Dn is the electron diffusion constant,
Dp is the hole diffusion constant, mn is the electron
(c) 1.212eV (d) 0.718eV
Solution. The variation of the band gap energy of mobility and mp is the hole mobility.
germanium with temperature is given by the fol- From the above equation, we see that the ratio
lowing relationship: of diffusion constant to mobility of carriers depends
on the temperature of the semiconductor.
Eg (T ) = 0.785 - 2.23 10-4 T Ans. (a)
1. A pentavalent impurity is added to an intrinsic Therefore, the dopant concentration is

silicon semiconductor with one part in 108 parts. (4.986 1022)/(1 108) = 4.986 1014 atoms/cm3
Ans. (4.986 1014)
Given that the atomic weight of silicon is 28.1,

density is 2.33 g/cm3, Avogadros number is 6.023
1023, effective mass of an electron is 1.08 mass 2. For the intrinsic semiconductor given in Question 1,
of an electron, mass of the electron is 9.11 1031 the resistivity in cm is
kg, mobility of electron is 1300cm2/Vs, Boltzmann
constant is 8.642 105eV/K, Plancks constant is Solution. The conductivity of an N-type semicon-
6.626 1034Js and temperature is 300K. Find the ductor is given by
concentration of donor atoms in atoms/cm3. s = NDmnq = 4.986 1014 1300 1.6 1019
= 0.103 (cm)1
Therefore, resistivity is 1/0.103 = 9.642cm.
Solution. Concentration of donor atoms refers to
the number of donor/cm3 of the semiconductor
Ans. (9.642)
material.
Given that there are 6.023 1023 atoms in a mole 3. For the intrinsic semiconductor given in Question 1,
of an element and atomic weight of silicon is 28.1. the Fermi level of the semiconductor is eV
Therefore, in 1 gram of silicon, the number of atoms below the conduction band.
is 6.023 1023/28.1 = 2.14 1022
Given that density of silicon is 2.33 g/cm3. Solution. The expression for fermi level in an
Therefore, the number of atoms of silicon in 1cm3 N-type semiconductor is given by
are 2.33 2.14 1022 = 4.986 1022.
N
Given that there is one dopant atom per 108 silicon EF = EC - kT ln C
atoms. ND

2.8 1019
160 Chapter 8: Semiconductor Physics EF = EC - 8.642 10-5 300 ln
4.984 1014

2p mnkTq
3 /2 = EC - 0.28 eV
NC = 2
h2 Hence, the Fermi level is 0.28eV below the conduc-
tion band.
2 3.14 1.08 9.11 10-31 Ans. (0.28)

8.642 10-5 300 1.6 10-19 4. Find the concentration of holes (atoms/cm3) in a
= 2 -34 2 atoms/m
3
(6.626 10 )
P-type silicon semiconductor at 300K if its con-
ductivity is 1 (cm)1. (Given that the mobility

of holes in silicon is 500 cm2/Vs)
Solution. For a P-type semiconductor, the expres-
= 2.8 1019 atoms/cm3
sion for conductivity is s = NAmpq
NA = 1/(500 1.6 1019) = 1/(8 1017)
2.8 1019
EF = EC - 8.642 10-5 300 ln = 1.25 1016 atoms/cm3
4.984 1014 Ans. (1.25 1016)

= EC - 0 . 28 eV
PRACTICE EXERCISE
1. Direct band gap semiconductors S2: Ratio of majority to minority carriers in an

(a) exhibit short carrier life time and are used for intrinsic semiconductor is very large.
fabricating BJTs (a) S1 (b) S2
(b) exhibit long carrier life time and are used for (c) Both S1 and S2 (d) Neither S1 nor S2
fabricating BJTs (1 Mark)
(c) exhibit short carrier life time and are used for
5. The concentration of ionized acceptors and donors
fabricating lasers
in a semiconductor are NA and ND, respectively.
(d) exhibit long carrier life time and are used for
If NA > ND and ni is the intrinsic concentration,
fabricating BJTs
the position of the Fermi level with respect to the
(1 Mark)
intrinsic level depends on
2. Which of the following statements is/are true?
(a) NA - ND (b) NA + ND
S1: Conductivity of silicon is less than that of ger-
manium at room temperature (300K). N A ND
(c) (d) ni
S2: As the temperature increases, the Fermi level ni2
of both N-type and P-type semiconductor mate- (2 Marks)
rials moves towards the centre of the forbidden 6. Under high electric fields, in a semiconductor with
energy band gap. increasing electric field,
(a) S1 (b) S2
(c) Both S1 and S2 (d) Neither S1 nor S2 (a) t he mobility of the charge carriers decreases and
the velocity of the charge carriers saturates.
(1 Mark)
(b) the mobility of the carriers and the velocity of
3. Due to illumination by light, the electron and hole the charge carriers, both increase.
concentrations in a heavily doped N-type semi- (c) t he mobility of the charge carriers decreases and
conductor increase by n and p, respectively. If the velocity of the charge carriers becomes zero.
ni is the intrinsic concentration, then (d) the mobility of the carriers increases and the
(a) n < p (b) n > p velocity of the charge carriers becomes zero.
(c) n = p (d) p = ni2 (2 Marks)
(1 Mark) 7. A silicon sample is uniformly doped with 1016 phos-
4. Which of the following statements is/are true? phorus atoms/cm3 and 2 1016 boron atoms/cm3.
If all the dopants are fully ionized, the material is
S1: For the same level of doping, the conductivity
of an N-type semiconductor is same as that of a (a) N-type with carrier concentration of 1016/cm3
P-type semiconductor. (b) P-type with carrier concentration of 1016/cm3

(c) P-type with carrier of 2 1016/cm3 (c) increases at low values of electric field and
(d) N-type with a carrier concentration of 2 10l6/cm3 decreases at high values of electric field exhib-
(2 Marks) iting negative differential resistance
8. The forbidden gap of the semiconductor material (d) increases linearly with electric field at low
values of electric field and gradually saturates
(a) increases with increase in temperature at higher values of electric field
(b) decreases with increase in temperature (2 Marks)
(c) does not vary with temperature
(d) can increase or decrease with increase in tempera- 14. Indicate the false statement.
ture depending upon the semiconductor material (a) T
he resistivity of the semiconductor is of the
(1 Mark) order of 103 cm.
9. Which one of the following is not a semiconductor? (b) Silicon and germanium are semiconductors.
(c) Indium is an acceptor impurity.
(a) Gallium arsenide (b) Indium (d) Arsenic is a donor impurity.
(c) Germanium (d) Silicon (1 Mark)
(1 Mark)
15. The Fermi level of an intrinsic semiconductor is
10. Which one of the following statements justifies the
extensive use of semiconductor materials? (a) in the centre of the forbidden band gap
(b) in the valence band
(a) It is because of their low forbidden energy gap. (c) in the conduction band
(b) It is because of their resistance value which lies (d) anywhere in the valence, conduction and for-
between that of a good conductor and an insulator. bidden energy band gap
(c) It is because of ease of fabrication of semicon- (1 Mark)
ductor material into practical active and pas-
sive devices. 16. According to the law of mass action:
(d) It is because of the fact that they exhibit some (a) T he product of free-electron concentration and
wide-ranging characteristics when certain spec- hole concentration in an extrinsic semiconduc-
ified impurities are added to them in controlled tor is equal to the intrinsic concentration in an
amounts. intrinsic semiconductor.
(1 Mark) (b) The product of free-electron concentration and
11. A semiconductor is irradiated with light such hole concentration in an extrinsic semiconduc-
that carriers are uniformly generated throughout tor is equal to the square of the intrinsic con-
its volume. The semiconductor is N-type with centration in an intrinsic semiconductor.
ND = 1019/cm3. If the excess electron concentra- (c) The product of free-electron concentration and
tion in the steady state is n = 1015/cm3 and if hole concentration in an extrinsic semiconduc-
p = 10ms (minority carriers life time), what is the tor is equal to the square root of the intrinsic
generation rate due to irradiation? concentration in an intrinsic semiconductor.
(d) None of these
(a) 1020 eh pairs/cm3/s
(1 Mark)
(b) 1024 eh pairs/cm3/s
(c) 1010 eh pairs/cm3/s 17. What is the probability that an electron in a semi-
(d) Cannot be determined, as the given data is conductor occupies the Fermi level at any tempera-
insufficient ture (> 0K)?
(2 Marks) (a) 0 (b) 1 (c) 0.5 (d) 1.0
12. À P-type silicon sample has a higher conductivity (1 Mark)
compared to an N-type silicon sample having the 18. In a P-type silicon sample, the hole concentration
is 2.25 1015/cm3. If the intrinsic carrier concen-
same dopant concentration. The above statement is
(a) true tration is 1.5 1010/cm3, then the electron concen-
(b) false tration is
(c) depends on the dopant concentration
(d) depends on the silicon fabric type (a) 0 (b) 1010/cm3
(2 Marks) (c) 105/cm3 (d) 1.5 1025/cm3
(2 Marks)
13. The drift velocity of electrons in silicon
19. Which of the following statements is true?
(a) is proportional to the electric field for all values
of electric field (a) A
n N-type semiconductor has excess of elec-
(b) is independent of the electric field trons and hence has a net negative charge.

(b) A P-type semiconductor has excess of holes and (a) 9.6 cm (b) 1.6 cm
hence has a net positive charge. (c) 2.6 cm (d) 8.6 cm
(c) An N-type semiconductor has excess of elec- (2 Marks)
trons and a P-type semiconductor has excess of 24. For the semiconductor bar given in Question 23,
holes but both of them are neutral. the resistance is
(c) 101 (d) 104
(d) None of these.
(1 Mark) (a) 106 (b) 104
(1 Mark)
20. According to Hall effect, the Hall voltage is propor-
tional to 25. Given that density of copper is 8.96 g/cm3, atomic
weight is 63.546, mobility of electron in copper is
(a) the product of B and I
43 cm2/Vs. The electrical conductivity of copperis
(b) inverse of the product of B and I
(c) I only (a) 8.4 104 (cm)1 (b) 58.4 104 (cm)1
(d) B only (c) 8.4 104 (m)1 (d) 58.4 104 (m)1
(B is the magnetic field and I is the current.) (2 Marks)
(1 Mark) 26. For the copper sample given in Question 25, the
21. The unit of q kT is resistivity is
(a) V (b) V1 (c) J (d) J/K (a) 7 nm (b) 10 nm
(1 Mark) (c) 12 nm (d) 17 nm
(1 Mark)
22. The intrinsic carrier density at 300 K is 1.5
1010/cm3 in silicon for N-type silicon doped to 2.25 27. A sample of germanium is doped with both donor
1015 atoms/cm3, the equilibrium electron and hole and acceptor impurities with donor concentration
densities are of 1014 donor atoms/cm3 and acceptor concentra-
tion of 1015 acceptor atoms/cm3. The resistivity
(a) n = 1.5 1015/cm3, p = 1.5 1010/cm3
of the semiconductor material is (given that the
(b) n = 1.5 1010/cm3, p = 2.25 1015/cm3 mobility of holes and electrons in germanium is
(c) n = 2.25 1015/cm3, p = 1.0 105/cm3 1800 cm2/Vs and 3800 cm2/Vs, respectively)
(d) n = 1.5 1010/cm3, p = 1.5 1010/cm3 (a) 2.867 cm (b) 12.867 cm
(2 Marks) (c) 2.135 cm (d) 22.867 cm
(2 Marks)
23. An N-type silicon bar 0.1 cm long and 100 mm2 in
28. For the germanium sample given in Question 27,
cross-sectional area has a majority carrier concen-
the conduction current density for an applied
tration of 5 1020/m3 and the carrier mobility is
electric field of 1.5 V/cm is
0.13 m2/Vs at 300K. If the charge of an electron
is 1.6 1019 C, then the resistivity of the bar is (a) 15.5232 A/cm2 (b) 1.5232 A/cm2
(c) 0.5232 A/cm2 (d) 5.5232 A/cm2

(1 Mark)
1. A small concentration of minority carriers is 4. The electron concentration in a sample of uniformly

injected into a homogeneous semiconductor crystal doped N-type silicon at 300K varies linearly from
at one point. An electric field of 10 V/cm is applied 1017/cm3 at x = 0 to 6 1016/cm3 at x = 200mm.
across the crystal and this moves the minority car- Assume a situation that electrons are supplied to
riers a distance of 1 cm in 20 ms. Find the mobility keep this concentration gradient constant with
(in cm2/Vs). time. If electronic charge is 1.6 1019C and the
(2 Marks) diffusion constant Dn = 35cm2/s, find the current
density in the silicon (in A/cm2), if no electric field
2. For a semiconductor, given that the concentration is present.
of holes is 1.25 1016 atoms/cm3. The concentra- (2 Marks)
tion of electrons in number of electrons per cubic
centimetre is . (Given that the intrinsic con- 5. Find the resistivity (in kcm) of intrinsic silicon
centration of silicon is 1.5 1010.) at 300K. Given that the intrinsic concentration of
(2 Marks) silicon is 1.5 1010 atoms/cm3 and the mobility of
electrons and holes is 1300cm2/Vs and 500cm2/
3. For the semiconductor given in Question 2, the Vs, respectively. (Charge of an electron can be
ratio of holes to the free electrons is . assumed to be 1.6 1019C.)
(1 Mark) (2 Marks)

Multiple Choice Questions Also, the drift velocity of charge carriers saturates
under high electric fields, with increasing electric field.
1. (c) Direct band gap semiconductors exhibit short
7. (b) Given that ND = n = phosphorus atoms = 1016/cm3
and NA = p = boron atoms = 2 1016/cm3
carrier life time and during the recombination pro-
cess, the energy is released in the form of light,
Hence they are used for fabricating lasers. Therefore, NA >> ND. Hence, the resultant material
will be P type.
2. (c)
Semiconductor carrier concentration = NA ND =
3. (c) Due to illumination by light, electronhole pair 2 1016 1016 = 1016/cm3
generation occurs. So, n = p, where n =
8. (b)
increase in electron concentration due to illumina-
tion by light and p = increase in hole concentra- 9. (b)
tion due to illumination by light.
10. (d)
11. (a) Given that, n = 1015/cm3, tp = 10 ms =
4. (d)
5. (c) Fermi level in P-type semiconductor with 10 106 s
respect to Fermi level of intrinsic semiconductor is Generation rate due to irradiation = n/tp = 1020
N eh pairs/cm3/s
EFi - EFp = kT ln A
ni 12. (b) The given statement is false, because for a
given semiconductor the electron mobility (mn) is
N N always higher than the hole mobility (mp), that is,
EC - EF = kT ln A 2 D
mn > mp.
or,
n
i
Therefore, at constant temperature The conductivity of a given N-type semiconductor
is sn = nqmn
N N
EC - EF A 2 D The conductivity of a given P-type semiconductor
n
i is sp = pqmp
6. (a) Figure below shows the mobility versus electric
field curve. Given that n = p (as the dopant concentration is
same). Also, q = 1.602 1019 C
m
Therefore, sn > sp
13. (d) vd = me, where vd is the drift velocity, m is the
m e 1/2 mobility and e is the applied electric field
Figure below shows the mobility versus electric
field curve.
m e
1
m
1/2
103 104 107 e (V/m) me
We know that vd = me, where vd is the drift velocity,

m is the mobility and e is the applied electric field. m e
1
From the figure above, for high electric field, with
increasing electric field the mobility of charge car-
riers decreases as electric field increases, so
m
1
e 103 104 107 e (V/m)

So, for smaller electric field applied, mobility of 23. (a) Given that l = 0.1 cm = 103 m, A = 100 mm2 =
charge carrier will remain almost constant. So for 100 1012 m2, n = 5 1020/m3, mn = 0.13 m2/Vs
smaller electric field applied, drift velocity (vd) and q = 1.6 1019 C.
increases linearly with electric field.
We know that conductivity = s = nqmn
For large electric field applied, mobility of charge Also, resistivity
carriers is inversely proportional to the electric
1 1
field, so the drift velocity gradually saturates at r= =
higher values of electric field. s (5 10 ) (1.6 10-19 ) (0.13)
20
14. (a) = 0.096 m = 9.6 cm
15. (a) 24. (a) We have

rl
16. (b) Resistance =
A
17. (c) In a semiconductor, the probability that an 9. 6 0. 1
R= -8
106
electron occupies the Fermi level at any tempera- 100 10
ture T > 0K is
25. (b) The concentration of atoms in any material is
f (E ) = 0.5 = 50%
given by
18. (c) By law of mass action,
6.023 1023 Density of the material
np = ni2 Atomic weight
where n is the electron concentration, p is the The atom concentration in copper = 6.023 1023
hole concentration and ni is the intrinsic carrier 8.9/63.546 = 0.849 1023
concentration. Each copper atom contributes one free electron.
Given that p = 2.25 1015/cm3 and ni = 1.5 1010/cm3
Therefore, the concentration of free electrons in
ni2 (1.5 10 )
10 2
2.25 10 20 copper is 0.849 1023.
n= = =
p 2.25 10 15
2.25 1015 In metal, only electrons contribute to the flow of cur-
rent. Therefore, conductivity of a metal is given by
or, n = 105/cm3
s = nmn q
19. (c)
Conductivity of copper = 0.849 1023 43 1.6
20. (a) 1019 = 58.4 104 (cm)1
21. (b) Thermal voltage or volt-equivalent of temperature 26. (d) Resistivity = 1/conductivity = 0.017 10-4 cm
kT = 17 nm
VT = = volts
q 27. (a) The given semiconductor is doped with both
Therefore, the unit of q/kT is volts-1 donor and acceptor impurities. The concentra-
tion of free electrons is approximately equal to the
22. (c) For an N-type semiconductor, electron density
n = ND = 2.25 1015/cm3
donor impurity concentration and the concentra-
tion of holes is approximately equal to the acceptor
Given that, intrinsic carrier concentration impurity concentration.
ni = 1.5 1010/cm3 Therefore, concentration of free electrons n = 1014,
Also, in an N-type semiconductor n ni and concentration of holes p = 1015.
By mass action law, Conductivity s = (nmn + pmp) q = (1014 3800 +
1015 1800) 1.6 1019 = 0.3488 (cm)1
np = ni2
Resistivity = 1/conductivity = 1/0.3488 cm
Therefore, = 2.867 cm
ni2 (1.5 1010 )2 28. (c) Current density in a semiconductor is given by
p= = = 105 atoms/cm3 J = se, where e is the applied electric field.
n 2.25 1015
Therefore,
Therefore, at equilibrium, the electron and hole den-
sities are 2.25 1015 /cm3 and 105/cm3 respectively. J = 0.3488 1.5 A/cm2 = 0.5232 A/cm2

1. We know 4. We have
J n = nqmn e + Dn q
Distance 1 dn
Velocity, vd = = = 50000 cm/s
20 10-6
Time dx
Given e = 0. Therefore,
Drift velocity = vd = me, where m is the mobility
and e is the electric field. J n = Dn q
dn
v dx
m = d =
50000
= 5000 cm2 /V s
e 10 dn 6 1016 - 1017
Now, = = -2 1020
Ans. (5000) dx 200 10-6 - 0
2. Using the mass action law, the concentration of Therefore,
J n = 35 (1.6 10-19 ) (-2 1020 )
free electrons is given by
ni2
n= = -1120 A/cm2
p
Ans. (-1120)
Therefore,
5. The value of conductivity of an intrinsic semicon-
(1.5 1010 )2 ductor is given by
n= = 18000
1.25 1016 s = (mn + mp ) ni q
Ans. (18000)
Therefore, s = (1300 + 500) 1.5 1010 1.6
3. Number of holes 1.25 10 16
1019 = 4.32 10-6 (cm)1
=
Number of free electrons 18000 Resistivity = 1/conductivity = 1/4.32 106 cm
= 6.95 1011 = 231.481 kcm
Ans. (6.95 1011) Ans. (231.481)
1. N-type silicon is obtained by doping silicon with Therefore,

(a) germanium (b) aluminium ni2 1.5 1016 1.5 1016
(c) boron (d) phosphorus p= =
n 5 1020
(GATE 2003: 1 Mark)
= 45 1010 = 4.5 1011/ m3
Ans. (d)
2. The band gap of silicon at 300 K is Ans. (a)
(a) 1.36 eV (b) 1.10 eV 4. An N-type silicon bar 0.1 cm long and 100 mm2 in
(c) 0.80 eV (d) 0.67 eV cross-sectional area has a majority carrier concen-
(GATE 2003: 1 Mark) tration of 5 1020/m3 and the carrier mobility is
0.13 m2/Vs at 300 K. If the charge of an electron
Ans. (b) is 1.6 10-19 coulomb, then the resistance of the
3. The intrinsic carrier concentration of silicon bar is
sample at 300 K is 1.5 1016/m3. If after doping,
(a) 106 ohm (b) 104 ohm
the number of majority carriers is 5 1020/m3, the -1
(c) 10 ohm (d) 10-4 ohm
minority carrier density is
(a) 4.50 1011/m3 (b) 3.33 104/m3
(c) 5.00 1020/m3 (d) 3.00 10-5/m3 Solution. We know that conductivity
(GATE 2003: 1 Mark)
s = nemn + pemp
Solution. From the low of mass action,
As, silicon-bar is N-type, conductivity is given by
ni2 = np
where ni is the intrinsic concentration s nemn

Therefore, resistivity, 6. The impurity commonly used for realizing the base
1 region of a silicon N-P-N transistor is
r=
nemn (a) gallium (b) indium
(c) boron (d) phosphorus
and the resistance of the bar
(GATE 2004: 1 Mark)
rl l Ans. (c)
R= =
A nemn A 7. The resistivity of a uniformly doped N-type silicon
Substituting the given values, we get sample is 0.5 cm. If the electron mobility (mn) is
1250 cm2/Vs and the charge of an electron is 1.6
10-3 1019 C, the donor impurity concentration (ND) in
R=
5 1020 1.6 1019 0.13 100 10-12 the sample is
= 0.96 106 106 (a) 2 1016/cm3 (b) 1 1016/cm3
Ans. (a) (c) 2.5 10l5/cm3 (d) 2 1015/cm3
5. The electron concentration in a sample of uniformly
doped N-type silicon at 300 K varies linearly from Solution. We know that resistivity
1017/cm3 at x = 0 to 6 1016/cm3 at x = 2 m.
r=
1
Assume a situation that electrons are supplied to nqmn
keep this concentration gradient constant with time.
If electronic charge is 1.6 10-19 coulomb and For the given sample, n = ND. Therefore,
the diffusion constant Dn = 35 cm2/s, the current
1 1
density in the silicon, if no electric field is present, is ND = = -
=11016/cm3
qmn r 1.6 10 1250 0.5
19
(a) zero (b) -506 A/cm2
(c) -560 A/cm2 (d) -1120 A/cm2 Ans. (b)
(GATE 2003: 2 Marks) 8. The band gap of silicon at room temperature is
Solution. The current density for N-type semicon- (a) 1.3eV (b) 0.7eV
ductor is given by (c) 1.1eV (d) 1.4eV
(GATE 2005: 1 Mark)
J n = qmn ne + qDn
dn
(1)
dx Ans. (c)
Given that no electric field is present, so e = 0. 9. The primary reason for the widespread use of sili-
Therefore, Eq. (1) reduces to con in semiconductor device technology is
dn (a) abundance of silicon on the surface of the Earth
J n = qDn (2) (b) larger band gap of silicon in comparison to
dx
germanium
From the problem, we have (c) favourable properties of silicon dioxide (SiO2)
(0,1017 cm2) (d) lower melting point
(GATE 2005: 1 Mark)
Ans. (a)
(2 106, 6 1016) 10. A silicon sample A is doped with 10 atoms/cm3
18
of boron. Another sample B of identical dimensions

is doped with 1018 atoms/cm3 of phosphorus. The
(0,0) ratio of electron to hole mobility is 3. The ratio of
conductivity of the sample A to B is
6 1016 10 1016
(a) 3 (b) 1/3
dn
= 6
= 2 1022 (c) 2/3 (d) 3/2
dx 2 10 (GATE 2005: 2 Marks)
Substituting in Eq. (2), we get
Solution. Conductivity of an N-type semicon
J n = 1.6 10 9 35 10 4 2 1022 A/m2
( ) ductor is

= 1120 A/cm2 s n = nqmn

Conductivity of a P-type semiconductor is 14. A heavily doped N-type semiconductor has the fol-
sp = pqmp. lowing data: Holeelectron mobility ratio = 0.4,
doping concentration = 4.2 108 atoms/m3, intrin-
Therefore, sic concentration = 1.5 104 atoms/m3. The ratio
sp mp 1 of conductance of the N-type semiconductor to
= =
sn mn 3 that of the intrinsic semiconductor of same mate-
rial and at the same temperature is given by
Ans. (b)
11. The concentration of minority carriers in an extrin- (a) 0.00005 (b) 2000
sic semiconductor under equilibrium is (c) 10000 (d) 20000
(a) directly proportional to the doping concentration
(b) inversely proportional to the doping concentration Solution. For N-type semiconductor, sn = nqmn
(c) directly proportional to the intrinsic concentration For intrinsic semiconductor, si = niq (mn + mp)
(d) inversely proportional to the intrinsic concentration Therefore,
(GATE 2006: 1 Mark) sn nmn
=
Solution. We know that np = ni2,
where ni is intrinsic si ni (mn + mp )
carrier concentration. For N-type semiconductor,
p is minority carrier concentration. Hence, for a 4.2 108 mn
= = 20000
N-type semiconductor. 1.5 104 mn [1 + (mp mn )]
ni2 1 1 Ans. (d)
p= or p or p
n n ND 15. The electron and hole concentrations in an intrin-
where, ND is the donor atom concentration. sic semiconductor are ni per cm3 at 300K. Now,
if acceptor impurities are introduced with a con-
Similarly, for a P-type semiconductor, n is the centration of NA per cm3 (where NA >> ni), the
minority carrier concentration and is given by electron concentration per cm3 at 300K will be
ni2
or n or n
1 1 (a) ni (b) ni + NA
n= ,
p p NA
ni2
where, NA is the acceptor atom concentration. (c) NA ni (d)
NA
Ans. (b)
12. Under low-level injection assumption, the injected (GATE 2007: 1 Mark)
minority carrier current for an extrinsic semicon-
Solution. By the law of electrical neutrality,
ductor is essentially the
p + ND = n + NA
(a) diffusion current (b) drift current Given that ND = 0, NA >> ni. Therefore, p = NA
(c) recombination current (d) induced current Using law of mass action,
(GATE 2006: 1 Mark)
np = ni2
Ans. (a)
13. The majority carriers in an N-type semiconductor ni2 n2
have an average drift velocity v in a direction or, n = = i
p NA
perpendicular to a uniform magnetic field B. The Ans. (d)
electric field E induced due to Hall effect acts in
the direction 16. Which of the following is true?
(a) v B (b) B v (a) A silicon wafer heavily doped with boron is a

(c) along v (d) opposite to v P+ substrate
(GATE 2006: 2 Marks) (b) A silicon wafer lightly doped with boron is a
P+ substrate
Solution. According to Hall effect, (c) A silicon wafer heavily doped with arsenic is a
Electric force + Magnetic force = 0 P+ substrate
Therefore, (d) A silicon wafer lightly doped with arsenic is a
qE + qv B = 0, or E = v B, or E = B v P+ substrate
Ans. (b) (GATE 2008: 1 Mark)

Solution. Boron is an acceptor impurity, so silicon = 1.6 1019 C, thermal voltage = 26mV and elec-
wafer doped with high concentration of boron is a tron mobility = 1350 cm2/Vs.
P+ substrate. It may be mentioned here that N+ 1V
and P+ refers to heavily doped semiconductor such
that its resistivity levels are of the order of few
milli-ohm-cm.
Ans. (a) ND = 1016/cm3
17. Silicon is doped with boron to a concentration of

4 1017 atoms/cm3. Assume the intrinsic carrier
concentration of silicon to be 1.5 1010/cm3 and x=0 x = 1 m
20. The magnitude of the electric field at x = 0.5 mm is

the value of kT to be 25mV at 300K. Compared
to undoped silicon, the Fermi level of doped silicon
(a) 1 kV/cm (b) 5 kV/cm
(a) goes down by 0.13eV (b) goes up by 0.13eV
(c) 10 kV/cm (d) 26 kV/cm
(c) goes down by 0.427eV (d) goes up by 0.427eV
Solution. Given that the sample is in thermal
Solution. As boron is P-type impurity, therefore Fermi equilibrium, therefore
level goes down. Ei is the Fermi level of intrinsic silicon
v 1
e= = = 106 V/m = 10 kV/cm
N
Ei - EF = kT ln A d 1 10-6
ni
Ans. (c)
= 25 10-3 ln 4 10
17
= 0.427 eV 21. The magnitude of the electron drift current density
1.5 1010 at x = 0.5 mm is
Ans. (c)
(a) 2.16 104 A/cm2 (b) 1.08 104 A/cm2
18. In an N-type silicon crystal at room temperature, (c) 4.32 103 A/cm2 (d) 6.48 102 A/cm2
which of the following can have a concentration of
4 1019 cm3?
(a) Silicon atoms (b) Holes Solution. We have J = NDqmne

(c) Dopant atoms (d) Valence electrons Subsituting different given values in the above
(GATE 2009: 1 Mark) equation, we get
Ans. (c) 1016 (1.6 1019) (1350) (10 103)
J=
19. The ratio of the mobility to the diffusion coefficient = 2.16 104 A/cm2
in a semiconductor has the unit Ans. (a)
(a) V1 (b) cmV1 22. Drift current in semiconductors depends upon
(c) Vcm1 (d) Vs
(a) only the electric field
(GATE 2009: 1 Mark)
(b) only the carrier concentration gradient
Solution. We know that (c) both the electric field and the carrier
D concentration
= VT
m
(d) both the electric field and the carrier concen-
tration gradient
Therefore,
(2011: 1 Mark)
m 1
=
D VT Solution. Drift current density
J = neme
Therefore, the ratio of mobility to diffusion coef- Hence, drift current
ficient in a semiconductor has the units of (volt)-1. I = nemeA
Ans. (a) where, A is the cross-sectional area of the semi-
Linked Answer Questions 20 and 21: The conductor
silicon sample with unit cross-sectional area shown Therefore, I depends upon carrier concentration
below is in thermal equilibrium. The following and electric field.
information is given: T = 300 K, electronic charge Ans. (c)

CHAPTER 9
SEMICONDUCTOR DIODES
In this chapter, the topics PN junction diode, Zener diode, tunnel diode, LED, PIN and avalanche photo diode are
discussed.
9.1 PN JUNCTION line with the N region. The P and the N regions are
referred to as the anode and the cathode, respectively.
Silicon and germanium are the most commonly used
A semiconductor diode is a polarity-sensitive two- materials for fabricating semiconductor diodes.
terminal device comprising a PN junction formed The electrons in the N region and holes in the P region
between a P-type semiconductor material and an N-type combine near the junction, resulting in a region near the
semiconductor material [Fig. 9.1(a)]. We have discussed junction that is devoid of free electrons and holes. This
in Chapter 8, the N-type semiconductor is formed by region of uncovered positive and negative ions is called
introducing pentavalent dopant impurity atoms while the the depletion region due to depletion of free carriers in
P-type semiconductor is formed by introducing trivalent this region. The thickness of this region is of the order
dopant impurity atoms into the intrinsic semiconductor of 0.5 m.
material. Also, in an N-type semiconductor, electrons are Electrons (majority carriers) in the N region and
the majority carriers and holes are the minority carri- negatively charged ions in the P region, near the junc-
ers, whereas in a P-type semiconductor, holes are the tion repel each other. Similarly, holes in the P region
majority carriers and electrons are the minority carriers. (majority carriers) and positively charged ions in the
A PN junction is formed by introducing the donor impu- N region, near the junction also repel each other. An
rities on one side and acceptor impurities on the other effective potential of the order of few tenths of a volt,
side of a single crystal of a semiconductor. Figure 9.1(b) referred to as the contact potential or the barrier poten-
shows the circuit symbol of a PN junction diode. The tial, is developed across the depletion region. However,
arrow is associated with the P region and the vertical some of these holes and electrons have sufficient kinetic

170 Chapter 9: Semiconductor Diodes
9.1.1 Forward-Bias Condition
A semiconductor diode is forward biased by applying a

P-type N-type positive potential to the P region and negative potential
semiconductor semiconductor to the N region as shown in Fig. 9.3(a). This applied
potential causes the electrons in the N region and holes
in the P region to combine with positive and negative
ions, respectively, in the depletion region. This results in
(a) reduction of the width of the depletion region [Fig. 9.3(b)]
and decrease in the potential barrier at the junction. As
the applied bias is increased in magnitude, the width
of the depletion region decreases till a point is reached
(b) where there is a sharp rise in the number of majority
Figure 9.1| (a) PN junction. (b) Symbol of a PN

carriers crossing the junction. In other words, a large
number of holes cross the junction from the P region
junction diode. to the N region and a large number of electrons cross
the junction in the reverse direction, that is, from the
energy to overcome the contact potential and be able to N region to the P region. It may be mentioned here that
pass through the depletion region. This results in a flow holes travelling from left to right constitute a current in
of electrons from the N region to the P region and flow of the same direction as the electrons travelling from right
holes from the P region to the N region. This constitutes to left. This results in exponential rise in the current due
the majority carrier flow vector. to the majority carriers. The current due to the majority
carriers is referred to as the forward current and is in
Also, holes (minority carriers) that are present in the the range of few tens of milliamperes (except for power
depletion region of the N region will pass to the P region. diodes where the current is of the order of few amperes).
Similarly, electrons (minority carriers) that are present Typically, the voltage across the forward-biased diode is
in the depletion region of the P region will pass to the less than 1 V and depends upon the diode material. As
N region. This constitutes the minority carrier flow an example, the forward voltage for silicon and germa-
vector. The relative magnitudes of the minority and nium diodes is typically 0.7 V and 0.3 V, respectively.
the majority flow vectors are such that the net flow in
either direction is zero. This is referred to as the open-
circuit condition of the semiconductor diode where no P N
bias voltage is applied to the diode. In other words,
in the absence of an applied bias voltage, the net flow
+ -
of current in a semiconductor diode is zero. Figure 9.2
shows the PN junction with no applied bias. VD
(a)
Depletion Depletion
Acceptor ions region Donor ions
Majority Hole flow region Electron flow
++
+ + + + _ _ _ _ _ _+
Majority + + + +
++ carriers +_ +_ +_ +_ +_
carriers
+ + ++
+ + + + + + +_
++
+
+
+ + +
_ _ _ _ _ _ +
Minority Minority + + + + +_ + +_ +_ +_ +_ +_
+ + ++
+ +
carriers ++
+

+ +

+
carriers _ _ _ _ _ _ + +
+_ +_ +_ +_ +_
++ _ + + + +_ +
+
_ _ _ _ _ _ +
+ + + +
+ + + + ++
+ + + + ++ + + + + + + + + +_ + +_ +_ +_ +_ +_
++ _ _ _ _ _ _ +
+ + + + ++ + + + + +_ + +_ +_ +_ +_ +_

+ + + +
++ _ _ _ _ _ _+
+ + + + +_ + +_ +_ +_ +_ +_
P-region N-region
ID = 0 (VD = 0) ID = 0 P-region N-region
No bias ID Forward bias ID
Figure 9.2| PN Junction with no applied bias. +(VD = +ve)
(b)
In the subsequent paragraphs, we shall discuss the Figure 9.3| (a) Forward-biased PN junction.
response of the semiconductor diode under forward-bias (b) Electron and hole flow in forward-
and reverse-bias conditions. biased PN junction.

9.2 IDEAL AND PRACTICAL DIODES 171
The flow of the minority carriers remains the same as However, it is a strong function of the diode tempera-
in the case of diode with no-applied bias. The current ture and increases with increase in diode temperature.
contributed by the minority carriers is referred to as the When the applied reverse bias is increased beyond the
reverse saturation current or reverse leakage current and breakdown voltage of the diode, there is a sharp increase
is of the order of few nanoamperes to few microamperes. in the reverse current. This is discussed in detail in
The reverse saturation current is in the opposite direc- Section 9.3.
tion to the forward current. However, its magnitude is
negligible as compared to the forward current. Volt
ampere (VI) characteristics of the diode are discussed 9.2 IDEAL AND PRACTICAL DIODES
in detail in Section 9.3.
9.1.2 Reverse-Bias Condition 9.2.1 Ideal Diode

A diode is said to be reverse biased when an external An ideal diode behaves like a switch that conducts cur-
potential applied across it is such that the positive rent only in one direction from anode to cathode. An ideal
terminal is connected to the N region and the nega- diode acts as a short circuit when forward biased and as
tive terminal is connected to the P region [Fig. 9.4(a)]. an open circuit when reverse biased. Thus, the resistance
This results in widening of the depletion region as of the forward-biased diode is zero and theresistance of
electrons and holes are drawn away from the junction the reverse-biased diode is infinite. Figure 9.5 shows the
due to the polarity of the applied voltage [Fig. 9.4(b)]. VI characteristics of an ideal diode.
Widening of the depletion region reduces the flow of
majority carriers to approximately zero.
I
P N
+
VD
(a)
Depletion V
Hole flow Electron flow Reverse Forward
region biased biased
_ _ _ __
_ _ +_ +_ +_
+ _ _ __ ++ + +
Figure 9.5| VI characteristics of an ideal diode.
++ ++
+ +
_ _ _ _ _ __ +_ +_ +_
+ + + _ _ __ ++ + +
_ _ _ _ _ __ ++ + + +
+_ +_ +_
+_ + + _ _ _ _ + + + +
_ _ _ _ _ __ ++ + + +_ +_ +_ 9.2.2 Practical Diode
+ + + _ _ __ ++ + +
_ _ _ _ _ __ ++ + + +_ +_ +_
+ + + _ _ __ ++ + + The actual diode differs from the ideal diode described
_ _ _ _ _ __ ++ + + +_ +_ +_
+ + + _ _ __ ++ + + in Section 9.2. In the forward-bias condition, the ideal
P-region N-region diode acts as a closed switch, with zero ON resistance
ID _ Reverse bias + ID that allows the current to flow in one direction, that
(VD = ve) is, from anode to cathode. However, practical diodes
do not conduct until a certain value of forward volt-
(b) age is applied to them. This voltage referred to as the
Figure 9.4| (a) Reverse-biased PN junction. cut-in voltage or knee voltage or threshold voltage is of
(b) Electron and hole flow in the order of less than 1 V for semiconductor diodes. Also,
reverse-biased PN junction. the ON resistance of the practical diode is not zero and
varies from few ohms to few hundreds of ohms. In the
The minority carrier flow remains the same as in case reverse-bias state, the practical diode differs from the
of diode with no-applied bias. As mentioned before, this ideal open switch as in this condition a small amount
current is referred to as the reverse saturation current of current referred to as the reverse saturation current
and is of the order of few nanoamperes to few microam- flows through the diode. Also, there is sharp increase in
peres. The reverse saturation current does not signifi- the reverse current when the applied reverse-bias voltage
cantly change with change in the reverse-bias potential. exceeds the reverse breakdown voltage.

9.3 VOLTAMPERE (VI) that must be exceeded before there is sufficient conduc-
CHARACTERISTICS OF A DIODE tion of current through the diode. In other words, cur-
rent flows through the diode when it is forward biased,
with the applied voltage greater than the cut-in voltage
The voltampere (VI) characteristics of a semicon- (Vg) of the diode. The cut-in voltage is 0.7 V in case of
ductor diode both in the forward-bias and reverse- silicon diodes and 0.3 V in case of germanium diodes.
bias conditions is expressed by the following universal
When the applied forward voltage exceeds the cut-in
diode equation, also referred to as the Shockleys diode
voltage, there is a sharp rise in the current through the
equation:
diode. In other words, a very small increment in the
hV T
ID = I 0 (eVD 1) (9.1) forward voltage (VD) results in a very large increase
in the forward current (ID). For positive values of VD,
where VD is the voltage across the diode (V), ID is the we can see from Eq. (9.1), the first term of the equa-
diode current (mA), I0 is the reverse saturation current tion will grow exponentially and overpower the effect
(mA), h = 1 for germanium and silicon (for relatively of the second term. The first term corresponds to the
higher values of diode current) and = 2 for silicon at forward current through the diode and the second term
relatively low levels of diode current, that is, below the corresponds to the reverse saturation current. Thus, the
cut-in voltage or the knee point of the diode characteris- current through the diode varies exponentially with the
tics, and VT is the volt equivalent of temperature (V). It applied voltage, provided that the applied voltage is
may be mentioned here that the value of greater than the cut-in voltage. The forward current is
measured in milliamperes and is generally in the range of
kT few tens of milliamperes.
VT =
q In the reverse-bias mode, the small current that flows
is the reverse saturation current. It is of the order of few
where k is the Boltzmann constant (8.642 105 eV/K), nanoamperes for the silicon diodes and typically 1 A for
q is the electron charge (1.6 1019 C) and T is the the germanium diodes. This current is independent of the
temperature (K). applied reverse voltage till the semiconductor junction
Also, diode voltage (VD) and diode current (ID) are posi- breaks down at a voltage known as the reverse break-
tive when the diode is forward biased and is negative down voltage or the peak inverse voltage. The breakdown
when the diode is reverse biased. of the junction results in a sudden rise of current that
ends up in damaging the diode. Hence, when the diodes
The VI characteristics of a silicon PN junction diode are operated in the reverse-bias mode, their operating
are shown in Fig. 9.6(a) and that of a germanium PN voltage should be less than the breakdown voltage. Some
diode in Fig. 9.6(b). As is evident from the figures, when diodes known as breakdown diodes are designed to oper-
the diode is forward biased there is a minimum voltage ate in the breakdown region.
ID (mA)
30 Forward bias
25
20
15
Reverse breakdown 10
voltage ( 1000 V) 5
VD (V)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
10 nA
20 nA
Reverse saturation 30 nA
current
40 nA
Reverse bias
(a)
ID (mA)
30 Forward bias
25
09-Chapter-09-Gate-ECE.indd 172 20 6/2/2015 11:22:22 AM
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
10 nA
20 nA
Reverse saturation 30 nA
current
40 nA
Reverse bias
(a) 9.4 DIODE RESISTANCE 173
ID (mA)
30 Forward bias
25
20
15
Reverse breakdown 10
voltage ( 300 V)
5
VD (V)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
1 A
2 A
Reverse saturation
current 3 A
Reverse bias 4 A
(b)
Figure 9.6| (a) VI characteristics of a silicon diode. (b) VI characteristics of a germanium diode.
9.3.1 Temperature Dependence of the VI temperature. As an example, the reverse saturation cur-
Characteristics rent of the germanium diode is of the order of 1 A at
25C and increases to around 100 A at 100C. The
Temperature has a significant effect on the VI charac- variation of the reverse saturation current with tempera-
teristics of the diode. Figure 9.7 shows the variation in ture is given by the following expression:
the diode characteristic curve with change in tempera-
ture. As is evident from the figure, the reverse saturation I 0 (T ) = I 0 (T1 ) 2(T T1 )/10 (9.2)
current, reverse breakdown voltage, cut-in voltage and
the diodes forward voltage are a strong function of the
where I0(T) is the reverse saturation current at tempera-
diode temperature.
ture T and I0(T1) is the reverse saturation current at
ID (mA) temperature T1.
T1 T2 T3 T4 The reverse breakdown voltage of the diode increases
with increase in temperature. Also, the cut-in-voltage
(Vg) and the forward voltage across the diode for a given
current decreases with increase in temperature. The
variation of cut-in voltage and the forward voltage with
temperature is given by the following expression:
VD (V) dV
= 2.5 mV/C (9.3)
dT
T1 > T2 > T3 > T4
9.4 DIODE RESISTANCE

T1 T2 T3 T4
ID (A)
Figure 9.7| Temperature dependence of the diode

As the VI characteristics of a diode are non-linear,
the diode resistance varies with change in the applied
VI characteristics.
voltage. Two terms very commonly used to define the
As an approximation, it can be said that reverse satura- resistance of the diode are the static resistance and the
tion current doubles itself for every 10C rise in diode dynamic resistance.

9.4.1 Static Resistance ID (mA)
Static resistance or the DC resistance (R) of the diode

is the resistance offered by the diode when a steady DC
voltage is applied to the diode. This results in the flow of ID1
a steady DC current through the diode. Let us consider
that application of voltage VD1 results in current ID1
through the diode [Fig. 9.8(a)]. Then the static resis- VD (V)
tance of the diode is given by the following expression VD1
VD1
R= (9.4)
ID1
Static resistance of the diode when forward biased will (a)

be higher near the knee region or below it as compared
to the vertical region of the VI characteristics. In the
reverse-biased state, the value of the static resistance ID (mA)
will be very high. Typical values of static resistance for
silicon diodes varied from few tens to hundreds of ohms
in the forward-biased region and from few megaohms to
few hundreds of megaohms in the reverse-biased region.
Id
9.4.2 Dynamic Resistance
VD (V)
Dynamic resistance or the AC resistance of a diode is Vd
defined as the resistance offered by the diode to a time-
varying input signal. The dynamic resistance (rd ) of the
diode having the VI characteristicsshown in Fig. 9.8(b)
is given by the following expression: (b)
DVd
rd = (9.5) ID (mA)
DI d
In other words, the dynamic resistance at a particular ID2

point in the operating region of the diode is defined by
the slope of the tangent drawn at that point.
Dynamic resistance of a diode in the forward-biased
region is
ID1
VD (V)
26h
rd (9.6) VD1 VD2
ID
where h = 1 for germanium and silicon (for relatively

higher values of diode current) and = 2 for silicon at (c)
relatively low levels of diode current, that is, below the
cut-in voltage or the knee point of the diode characteris- Figure 9.8| (a) Static resistance of a diode.
tics, and ID is the forward diode current. (b)Dynamic resistance of a diode.
In the reverse-biased region, the value of the dynamic (c)Average AC resistance of a diode.
resistance of the diode
However, the change in the value of reverse saturation
26h current (I0) is very small with change in the reverse-
rd (9.7) bias voltage from 0 V to the reverse breakdown voltage,
I0
resulting in very high value of dynamic resistance. Hence,
where I0 is the reverse saturation current. for all practical purposes, the diode can be assumed to

9.5 DIODE JUNCTION CAPACITANCE 175
be an open circuit in the reverse-bias region. The typi- d is the separation between the plates. With no applied
cal value of dynamic resistance of silicon diodes is of bias, the width of the depletion region is around 0.5 m
the order of few ohms in the forward-biased region and and the associated capacitance is of the order of 20 pF.
around few hundreds of megaohms in the reverse-biased In the forward-biased state, the width of the depletion
region. region decreases and hence the capacitance increases. In
the reverse-biased condition, the depletion region widens
with the applied reverse voltage so the corresponding
9.4.3 Average AC Resistance
capacitance reduces with increase in applied reverse bias.
This capacitance is referred to as the transition capaci-
Another term that is sometimes used to define the resist-
tance or the space charge capacitance.
ance of a diode is called the average AC resistance. When
a sufficiently large input signal is applied to the diode to Figure 9.9(b) shows the variation of the transition
produce a broad swing as shown in Fig. 9.8(c), the resist- capacitance with the applied reverse voltage. The depend-
ance associated with the diode is called the average AC ence of the diode capacitance on the applied reverse bias
resistance. It is determined by the slope of the straight is made use of in a number of electronic devices and
line formed by joining the two points on the VI charac- systems such as in variable voltage capacitors known as
teristics of the diode corresponding to the maximum and the varactors. The effect of transition capacitance in the
minimum input voltages, and is given by the following forward-biased state is overshadowed by the presence of
expression: diffusion capacitance.
(VD2 VD1 ) C T (pF)

Average AC resistance = (9.8)
(ID2 ID1 )

The static, dynamic and the average AC resistances

20
discussed so far are all contributed by the PN junction.
Other than the junction resistance, the resistance of the
semiconductor material (called body resistance) and (C D + C T) 10
the resistance introduced by the connection between
the semiconductor material and the external metallic
conductor (called contact resistance) are also present.
These resistances together can range from 0.1 to VR (V)
Ideal diode 20 15 10 5
around 2 and in most cases can be ignored.
(a) (b)
9.5DIODE JUNCTION CAPACITANCE Figure 9.9| Diode capacitance.
9.5.2 Diffusion Capacitance

There are two types of capacitances associated with a
junction diode, namely, the transition capacitance (CT) In the forward-biased state, the capacitance that is pre-
and the diffusion capacitance (CD). These capacitances dominant is the diffusion capacitance or the storage
in effect come in parallel with the ideal diode as shown capacitance. It is defined by the equation CD = dq/dv,
in Fig. 9.9(a). For low- and mid-frequency low-power where dq represents the change in the number of minor-
applications, the effect of these capacitances on the diode ity carriers stored outside the depletion region when a
performance is negligible and hence can be ignored. change in voltage dv is applied across the diode. In other
However, in high-frequency and high-power applications, words, it is dependent on the rate at which the charge is
the effect of these capacitances have to be taken into inducted into the P and the N regions just outside the
consideration. depletion region. Its value in the forward-biased region
is in the range of 1020 F. In the reverse-bias region,
9.5.1 Transition Capacitance its value is much smaller than the transition capacitance
and hence the transition capacitance predominates in
The PN junction acts as a parallel plate capacitor with this region.
the P and the N regions as the parallel plates and the Diffusion capacitance affects the switching time of the
depletion region as the insulator or the dielectric. As we diode. The switching time constant of the diode is equal
can recall, the capacitance of a parallel plate capacitor is to (rdCD), where rd is the dynamic forward resistance of
given by the formula Cp = eA/d, where e is the permit- the diode. The value of switching time constant is very
tivity of the dielectric used, A is the area of the plates and small due to the extremely small value of rd. Hence, the

switching time of the diode is not taken into considera- ID (mA)

tion for normal diode applications and it assumes impor-
tance only when the diode is used as a switching device
in very high speed applications.
9.6 DIODE EQUIVALENT CIRCUITS
An equivalent circuit of a device is a combination of VB Ideal VD (V)

VB
elements suitably connected so as to best represent the diode
Figure 9.11| Simplified equivalent diode model.

actual terminal characteristics of the device. The most
accurate equivalent circuit model for a diode is the piece-
wise linear equivalent circuit model (Fig. 9.10) in which
the diode curves are represented by straight-line seg- Another possible simplification model is shown in
ments. From the figure, it is clear that the assumption Fig. 9.12. Here, the curve has been approximated by
has been made that the diode will not conduct till the a straight line through the origin and the slope of the
voltage at the anode exceeds the cathode voltage by the straight line is given by inverse of the static diode resist-
cut-in voltage, which is 0.7 V in case of silicon diodes ance at the point of intersection of the line with the
and 0.3 V for germanium diodes. Hence, a battery volt- diode VI characteristics.
age VB has been introduced in the circuit opposite to
the conduction direction of the diode. The magnitude
of the battery voltage VB is equal to the cut-in voltage ID (mA)
of the diode. When the applied voltage exceeds the bat-
tery voltage VB, the diode starts conducting and the
resistance of the diode is expressed as rd, where rd is
the dynamic ON resistance in the forward-biased con-
A
dition. A line is drawn on the equivalent model curve
with a slope equal to inverse of the value of the dynamic 1/RS
resistance (1/rd). The ideal diode shown in the circuit
is an ideal switch that conducts only in one direction.
The piecewise linear equivalent circuit model is the most RS
accurate equivalent model of a diode. However, it does Ideal
diode VD (V)
not result in the actual duplication of the diode charac-
teristics, especially in the knee region. Also, the model Figure 9.12| Another simplified diode model.
is equally valid for both DC as well as AC applications.
ID (mA) Ideal diode model is the most simple equivalent diode

model. This model is applicable when the applied volt-
age levels are much larger than the diodes cut-in voltage
and the network resistance is of a much larger value than
Piecewise the diodes dynamic ON resistance. The VI character-
linear model istics of an ideal diode were shown in Fig. 9.5. They are
reproduced again in Fig. 9.13 for reference.
VD (V)
rd VB
VB Ideal
ID (mA)
diode
Figure 9.10|Piecewise linear equivalent model of a diode.
When the network resistance is much larger than the

value of the diode resistance rd, then the above model
can be simplified as shown in Fig. 9.11. Here, the diode
resistance is assumed to be zero. The model makes an
assumption that the diode will not conduct till the cut-in VD (V)
voltage is reached and after that it acts as an ideal closed
switch that conducts only in one direction. Figure 9.13| Ideal diode model.

9.7 LOAD LINE ANALYSIS OF ADIODE CIRCUIT 177
9.7 LOAD LINE ANALYSIS OF and diode current (ID). However, these two variables are
ADIODE CIRCUIT the same as the diodes VI characteristic axis variables
[Fig. 9.14(b)]. Therefore, a second relationship between
the two variables is given by the VI characteristic curve
Load line analysis is a graphical method of analysing a of the diode. The intersection of the load line with the
circuit. In this method, a load line is drawn on the actual VI characteristic curve of the diode determines the
characteristic curve or on the equivalent model curve of operating point of the circuit also called the quiescent
the active device used in the circuit. It provides a very point or the Q-point.
accurate method of analysing the circuit when the actual The load line can be drawn by determining its inter-
characteristic curve of the active device is used for analy- cepts on the voltage and the current axis. For VD = 0,
sis. The slope of the load line depends on the applied ID = VI/RL and for ID = 0, VD = VI. The straight line
load. It may be mentioned here that the applied load joining these two points is the load line. The slope of the
generally has an important impact on the point or region line is dependent on the value of load resistance (RL) and
of operation of the device. The active device of concern is given by 1/RL. Thus, for a given input voltage VI,
in this section is the semiconductor diode. the lower the value of the load resistance, the steeper is
the load line, resulting in a higher value of the current
9.7.1 DC Applied Voltage at the Q-point. The process of drawing the load line and
determining the Q-point is better illustrated in Fig. 9.15.
Figure 9.14(a) shows the basic diode circuit where a DC The operating point for the circuit is (VDQ, IDQ), where
input voltage source (VI) is applied to a series connec- VDQ = VI - IDQ RL.
tion of a diode (D) and load resistance (RL). Applying
Kirchoffs voltage law to the circuit, we get ID (mA)
Static VI
VI = VD + IDRL (9.9) curve of diode

VI
D
RL
VD
VI RL IDQ Operating point
ID
Load line
VD (V)
(a) VDQ IDQRL
ID (mA) VI
Figure 9.15| Load line analysis of a diode circuit for

DC input voltage.
9.7.2 AC Applied Voltage
Let us consider the case when a time-varying input

signal is applied to the circuit shown in Fig. 9.16(a). As
the voltage applied is time variant, separate load lines
VD (V)
need to be drawn for the instantaneous values of the
(b) input voltage. The various load lines are parallel to each
other as the value of load resistance RL is fixed. The
Figure 9.14| (a) Simple diode circuit. (b) VI intersection of these lines with the static VI charac-
characteristics of a diode. teristic curve of the diode gives the value of the current
in the circuit corresponding to different instantaneous
where VD is the diode voltage and ID is the diode current. values of the input signal. A better method to deter-
The straight line represented by Eq. (9.9) is called mine the current is to draw the dynamic characteristic
the load line This one equation is not sufficient to deter- curve of the circuit, which is a plot between the diode
mine the two unknown variables, diode voltage (VD) current and the input voltage. Figure 9.16(b) shows the

D procedure for drawing the dynamic characteristic curve.

The load line for the maximum value of the input signal
is drawn. From the Q-point, a horizontal line is drawn.
The point where this line intersects with the vertical line
Vi drawn from the X-axis corresponding to that input volt-
RL
age gives a point on the dynamic curve. The process is
repeated for a few other values of input voltage to yield
sufficient points to construct the dynamic curve.
Let us assume that the waveform shown in Fig.9.17(a)
is applied to the circuit shown in Fig. 9.16(a). The
(a) dynamic curve can be used to draw the output current
waveform as shown in Fig. 9.17(b). The figure is self-
ID (mA) explanatory. It may be mentioned here that the dynamic
Static VI curve curve applies only to the circuit containing the same value
Vi/RL of diode of load resistance for which it is drawn. Also, in the dis-
cussion, we have assumed the diode to be an open circuit
V i/RL in the reverse-bias region. However, the dynamic curve
Dynamic VI for the diode in the reverse-bias region can be drawn on
V i/R L curve similar lines as drawn for the forward-bias region.
V i/R L A
B A 9.8 BREAKDOWN DIODES
C B
D C As discussed earlier in Section 9.3, when the voltage
D applied across the diode in the reverse-biased region
Vi(t) exceeds the breakdown voltage of the diode, there is
V i V i V i Vi
a sharp increase in the current flowing through the
(b) diode. This region is known as the breakdown region.
Breakdown diodes are designed with sufficient power dis-
Figure 9.16| (a) Simple diode circuit. (b) Dynamic VI sipation capabilities to operate in the breakdown region.

curve of a diode. They are generally employed as constant-voltage devices
Vi
0 t
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12
(a)

9.8 BREAKDOWN DIODES 179
ID ID
t
Vi t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12
0
t1 Vi
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t
(b)
Figure 9.17| (a) Input waveform. (b) Output waveform construction of a diode circuit for AC input voltage.
or as voltage references. Depending upon the mechanism, 9.8.1 Avalanche Diodes

which leads to breakdown, they can be further classified
as Zener diodes and avalanche diodes. In the case of avalanche diodes, on application of
The symbol and the VI characteristics of breakdown reverse-bias voltage, the thermally generated carriers
diodes are shown in Figs. 9.18(a) and (b), respectively. have sufficient energies to disrupt the covalent bonds,
As is clear from Fig. 9.18(b), for reverse voltages less thereby resulting in free electrons. These free electrons
than the breakdown voltage (VZ), the diode acts as an knock out more electrons from the adjacent bonds. The
open circuit and for voltages greater than the breakdown process is regenerative and is referred to as avalanche
voltage it acts as a constant voltage reference with the multiplication. Avalanche breakdown mechanism is
voltage across it equal to the breakdown voltage. It may predominant in lightly doped diodes with broad deple-
be mentioned here that the shape of the VI charac- tion region and low-field intensity. Generally, the ava-
teristics is the same for both the Zener and avalanche lanche diodes have breakdown voltages greater than
diodes. The parameters of interest for the breakdown 6 V and their breakdown voltage increases with increase
diodes are the breakdown voltage, dynamic impedance in temperature, that is, they have positive temperature
and the power dissipation capability. coefficient of breakdown voltage. As the temperature
increases, the vibrational displacement of atoms in the
IZ crystal grows, which increases the probability of collision
of carriers with the lattice atoms as they cross the deple-
VZ tion region. Hence, they do not have sufficient energy
VR
to start the avalanche process resulting in increase in
the breakdown voltage. Silicon diodes with avalanche
breakdown phenomenon are available with breakdown
voltages ranging from several volts to several hundreds
of volts and with power ratings up to 50W.
9.8.2 Zener Diodes

Breakdown
(a) region (b) The breakdown phenomenon in the case of a Zener diode
Figure 9.18| (a) Circuit symbol of breakdown diodes.

is the result of electrons breaking their covalent bonds
due to the existence of a strong electric field at the junc-
(b) VI characteristic of breakdown diodes. tion. The new holeelectron pair created increases the

reverse current. It does not involve collisions of carriers voltages up to 20 V to 30 V. The relationship between
with the lattice atoms. A Zener breakdown phenome- the transition capacitance and the applied reverse bias
non occurs for heavily doped diodes having a narrow is expressed by the relationship given by the following
depletion-region width and high field intensity. They expression:
have breakdown voltages below 6 V. With increase K
in temperature, the energy of the valence electrons CT = (9.10)
(Vg + VR )n
increases, making it easier for these electrons to break
the covalent bonds and hence the breakdown voltage where K is the constant (depends on the semiconductor
decreases. Hence, these diodes have a negative tempera- material and the diode construction technique), Vg is the
ture coefficient of breakdown voltage. Diodes with break- knee potential of the diode, VR is the magnitude of the
down voltages between 5 V to 6 V have almost zero applied reverse bias and n = 1/2 for alloy junction and
temperature coefficient of breakdown voltage. It may be 1/3 for diffused junction.
mentioned here that the term Zener diode is generally
used for breakdown diodes even with avalanche break- CT (pF)
down phenomenon.
Both Zener and avalanche diodes are used in voltage 80
regulators to regulate the load voltage against variations
in load current and input voltage. They are used in
these applications beacsue in the breakdown region 60
large change in the diode current produces only asmall
change in the diode voltage. Figure 9.19 shows a simple
voltage regulator circuit employing a Zener diode. 40
The voltage across the load resistor is the same as the
Zener breakdown voltage.
20
R
IZ IL
VR (V)
+
0 2 4 6 8 10 12 14 16
VI RL
Figure 9.20| Characteristics of a varactor diode.
VZ VZ

The circuit symbol and the equivalent circuit of
aractor diodes are shown in Figs. 9.21(a) and (b), respec-
v
tively. RR is the resistance of the diode in the reverse-
Figure 9.19| Simple voltage regulator circuit bias region and is of the order of greater than equal to
using breakdown diode. 1 M. RS is the geometric resistance of the diode and
is of the order of few ohms. The magnitude of CT varies
from few picofarad to around hundred picofarad. In dif-
9.9 VARACTOR DIODES ferent varactor diode types, the values of minimum and
maximum capacitances may vary; however, the ratio of
maximum to minimum capacitance is typically 2.5 to 3.
Varactor diodes are used as variable voltage capaci- Typical application areas of varactor diodes include FM
tors. They are also referred to as varicaps or variable modulators, automatic frequency control devices, adjust-
voltage capacitance diodes or tunable diodes. Their mode able band-pass filters and parametric amplifiers.
of operation depends on the transition capacitance that
exists at the PN junction when the diode is reverse CT
biased. Junction capacitances were discussed in detail
in Section 9.5. Figure 9.20 shows the characteristics of a RS LS
typical commercially available varactor diode. As shown
in the figure, there is a sharp decrease in the transition (0.112 ) RR (1 M) (15 nH)
capacitance initially with an increase in the reverse-bias
(a) (b)
voltage. As the reverse-bias voltage increases further,
the rate of change of capacitance with voltage decreases. Figure 9.21| (a) Circuit symbol of a varactor diode.
Varactor diodes are normally operated with reverse (b) Equivalent circuit of a varactor diode.

9.10 TUNNEL DIODES 181
9.10 TUNNEL DIODES ID (mA)
Tunnel diodes have heavily doped P and N regions,

about 1001000 times dopant concentration than that Peak point
IP
of a typical semiconductor diode. Heavy doping results
in narrowing of the depletion region. The width of the Negative
depletion region of a tunnel diode is around 1001000 resistance
times less than that of a typical semiconductor diode. region
Because of this narrow depletion region, the charge
carriers instead of climbing up the potential barrier
may pierce through the potential barrier resulting in
tunnelling of carriers both in the forward- and the Valley
reverse-bias regions, hence rendering the diode bi- point
directional conduction property. In the forward direc- IV
tion, the current reaches the maximum value IP (called VD (V)
peak current) at a voltage VP (peak voltage). At this VP VV VF
point, referred to as peak point, slope of the VI curve
is zero, that is, di/dv = 0. Beyond the peak point, the
current starts to decrease with increase in voltage as
there are no more carriers available for tunnelling. The
current approaches zero for a forward voltage of 0.4V
to 0.5 V, but then the normal PN junction effect
starts. The forward current of PN junction diode adds Figure 9.22| VI characteristics of a tunnel diode.
to the current due to the tunnelling effect. The current
decreases beyond the peak point till a point, referred to
as the valley point. The region between the peak point
and the valley point has negative resistance character-
istics as the voltage decreases with increase in current.
At the valley point also, the slope of the VI curve is
zero (di/dv = 0). Beyond the valley point, the current
starts increasing again with increase in voltage and
the current reaches the peak value IP again at a volt-
age VF. This is further illustrated in Fig. 9.22, show-
ing the VI characteristics of the tunnel diode. These (a)
characteristics may be considered to be composed of
two characteristics, one due to the PN junction and C
other due to the tunnelling phenomenon. The value of
voltage swing (VF VP) is of the order of 1 V for gal- RS LS
lium arsenide tunnel diodes and 0.45 V for germanium
tunnel diodes.
The symbol of the tunnel diode and its equivalent
circuit in the negative resistance region are shown in R
Figs. 9.23(a) and (b), respectively. The semiconductor
(b)
material used in the construction of tunnel diodes is
either germanium or gallium arsenide. Silicon is not Figure 9.23| (a) Circuit symbol of a tunnel diode.
used for constructing tunnel diodes. This is because (b) Equivalent circuit of the tunnel
the ratio of the peak current to the valley current diode in the negative resistance region.
(IP/IV) in gallium arsenide and germanium is quite
high, approximately 15 for gallium arsenide and 8 for of few nanoseconds to several picoseconds. Because of
germanium. The value in case of silicon is very small their negative resistance characteristics, these diodes
(appoximately 3). were earlier used as microwave oscillators. But now they
Tunnel diodes are used in high-speed applications have been replaced by other devices that have surpassed
such as in computers with switching times of the order them in performance.

9.11 SCHOTTKY DIODES The junction barrier for a Schottky diode, in both
the forward- and reverse-bias regions, is less than that
of the PN junction diode. This results in lower cut-in
Schottky diodes, also known as hot-carrier diodes, have voltage of the order of 0.3 V for silicon-metal Schottky
a metalsemiconductor junction instead of a semicon- diode as compared to a cut-in voltage of 0.7 V for silicon
ductorsemiconductor junction (PN Junction) of a PN junction diodes. Lower junction barrier also results
conventional PN junction diode. Normally, N-type sili- in higher currents at the same applied voltage in both
con is used as the semiconductor while the metal used the forward- and the reverse-bias conditions. Thus, they
can be aluminium, platinum, tungsten or molybdenum. dissipate less power than a normal diode. But this results
This different construction technique renders these in larger reverse saturation current as compared to a
diodes some special characteristics as compared to PN conventional PN junction diode, which is highly unde-
junction diodes such as lower cut-in voltage, increased sirable. Also, the peak inverse voltage (PIV) rating for
frequency of operation, etc. a Schottky barrier diode is less than a comparable PN
Schottky barrier diodes are majority carrier con- junction diode.
duction devices. In both the materials (metal and Schottky diodes are used as high-efficiency rectifiers,
semiconductor), electrons are the majority carriers. which are essential in applications such as switched mode
The circuit symbol and the equivalent circuit model for power supplies (SMPS), switching regulators, etc. The
a Schottky diode are shown in Figs. 9.24(a) and (b), absence of minority carriers in Schottky diodes results in
respectively. The equivalent circuit is an ideal diode in significantly lower value of reverse recovery time (as low
parallel with a capacitor, which is equivalent to the junc- as 20 ns). Thus, they are effective at operating frequen-
tion capacitance. The VI characteristics of a Schottky cies extending up to several gigahertz. Other application
diode as compared to a conventional PN junction diode areas include low-voltage/high-current power supplies,
is shown in Fig. 9.25. AC to DC converters, mixers and detectors in commu-
nication systems.
Ideal diode
9.12 POINT CONTACT DIODES

AND POWER DIODES
Cj
(a) (b)
9.12.1 Point Contact Diodes
Figure 9.24| (a) Circuit symbol of a Schottky diode.
(b) Equivalent circuit of a Schottky diode. These diodes are intended primarily for RF applica-
tions due to their extremely small internal capacitance,
considerably less than that of a conventional junction
ID
diode. They basically have a metalsemiconductor junc-
Schottky PN junction tion and have been replaced by Schottky barrier diodes,
diode diode as Schottky diodes offer lower forward resistance, wide
dynamic range and better noise performance as com-
pared to point-contact diodes.
9.12.2 Power Diodes
VD Power diodes are designed to operate at high power levels

and at high operating temperatures. They are mainly
used as rectifiers. They are generally constructed using
silicon because silicon offers higher current, temperature
and PIV ratings. Such diodes have large junction area
to ensure low forward diode resistance so that the I2R
losses can be reduced. The current capability of power
PN diodes is increased by placing two or more diodes in par-
junction Schottky allel whereas the PIV rating is increased by stacking the
diode diode
diodes in series. Generally, they are mounted in conjunc-
Figure 9.25| VI characteristics of a Schottky diode. tion with heat sinks for thermal management.

9.14PHOTODIODES 183
9.13 LIGHT-EMITTING DIODES where l is the wavelength (in nm) and Eg is the band
gap energy (in eV).
Table 9.1 enlists some of the materials used for
A semiconductor PN junction diode designed to emit making LEDs along with their band gap energies and
light when forward biased is called a light-emitting diode wavelengths.
(LED). When a PN junction is forward biased, the elec-
trons in the N-type material and the holes in the P-type
material travel towards the junction. Some of these holes Table 9.1| Commonly used LED materials.
and electrons recombine with each other and in the pro-
Material Band Gap Wavelength
cess radiate energy. The energy will be released in the
Energy (eV) (nm)
form of either photons of light or heat. In silicon and
germanium diodes, most of the energy is released as heat GaAs 1.43 910
and the emitted light is insignificant. However, in some GaP 2.24 560
materials such as gallium phosphide (GaP), gallium arse-
GaAs60P40 1.91 650
nide (GaAs) and gallium arsenide phosphide (GaAsP)
substantial photons of light are emitted. Hence, these AlSb 1.60 775
materials are used in the construction of LEDs. InSb 0.18 6900
The VI characteristics of LEDs are similar to that of
a normal PN junction diode with the difference that the
cut-in voltage in the case of LEDs is around 1.5 V as com-
pared to 0.7 V for silicon diodes and 0.3 V for germanium 9.14 PHOTODIODES
diodes. Figures 9.26(a) and (b) show the process of light
emission in an LED and its circuit symbol, respectively.
As can be seen from the figure, the conducting surface Photodiode is a junction diode through which signifi-
connected to the P-type material is smaller in size to allow cant current flows when light falls on it. Photodiodes
maximum number of photons to contribute to output are operated either in the reverse-bias mode (referred to
light energy. The wavelength of emitted light is the func- as the photoconductive mode) or with no external bias
tion of band gap energy of the semiconductor material (referred to as the photovoltaic mode). When no light is
and is expressed by the empirical formula as follows: incident on the photodiode, the current flowing through
it is the reverse saturation current. This current is also
1240 referred to as the dark current. When operated in the
l= (9.11)
Eg photoconductive mode, the impinging photons of inci-
dent light create electronhole pairs on both sides of the
Anode junction. The number of electronhole pairs generated is
(+) directly proportional to the number of incident photons.
Emission of light The photo-induced electrons in the conduction band of
the Pregion will move across the junction down the
+ + + + P
potential hill along with the thermally generated minor-
+ + + ity carriers. Similarly, holes produced in the valence
+ band of the Nregion are available to add to the current
+ + + +
+ + + + + Recombination of flow by moving across to the P region. Figures 9.27(a)
electrons and holes and (b) show the photoeffect in a photodiode and its
circuit symbol. Figure 9.28 shows the variation of the
N photocurrent with the incident light. In the figure, IL1,
IL2, IL3 and IL4 are the photo-current levels correspond-
ing to light levels L1, L2, L3 and L4, respectively. When
() Cathode operated in photovoltaic mode, a voltage is developed
(a) across the anode and the cathode terminals. The dark
current in the photovoltaic mode is nearly zero.
The spectral response of photodiodes is a function of
the energy band gap of the material used in its con-
struction. Some of the commonly used materials are sili-
(b)
con (2001100 nm), germanium (5001900 nm), indium
Figure 9.26| (a) Process of light emission in an LED. gallium arsenide (7001700 nm) and mercury cadmium
(b) Circuit symbol of an LED. telluride (190010000 nm).

low light levels. The two possible circuits in photovoltaic

P-side N-side mode are shown in Figures 9.29(a) and (b), respectively.
Electron
Conduction flow The output voltages for these circuits are given by
band Idet R and Idet Rf, respectively, where Idet is the cur-
rent through the photodiode. The circuit in Fig. 9.29(b)
Conduction
band offers better linearity than the circuit in Fig. 9.29(a) as
Valence the equivalent input resistance for the photodiode in
band + + this case is Rf/A, where A is the open loop gain of the
Valence operational amplifier. It is obvious that value of Rf/A
Hole + + + band is much lower as compared to R in case of Fig. 9.29(a).
flow + For a better linear response, the equivalent resistance
across the photodiode should be as small as possible, as is
evident from Fig. 9.30.
+
Vo
(a)
R
l
(a)
Rf
(b)
Figure 9.27| (a) Photo effect in a photodiode. +V
(b) Circuit symbol of a photodiode.
Vo
+
VR (V) 40 30 20 10 V
Dark current
0.2
IL1
L1
0.4
(b)
IL2
Figure 9.29| Application circuits of photodiodes in
L2 0.6
L4 > L 3 > L2 > L1 photovoltaic mode.
IL3 0.8
L3
1.0
IL4 Current (mA)
L4
I (mA) Voltage (V)
Figure 9.28| Variation of photocurrent with the

incident light in a photodiode.
High load line
9.14.1 Photodiode Application Circuits
As discussed above, photodiodes can be operated in two

modes, namely, the photovoltaic mode and the photocon-
ductive mode. In the photovoltaic mode, the photodiode Low load line
is operated with zero external bias voltage and is gen- Figure 9.30| Load line analysis of photodiode in
erally used for low-speed applications or for detecting photovoltaic mode.

9.14PHOTODIODES 185
+Vbias +Vbias
+V
-
Vo
Vo +
-V
R R
(a) (b)
Rf +Vbias
Rf
+V
+V
-
Vo -
+ Vo
+Vbias +
-V -V
(c) (d)
Figure 9.31| Application circuits of photodiodes in photoconductive mode.
Figures 9.31(a), (b), (c) and (d) show four possible The load line for the photodiodes operating in photocon-
circuits using photodiodes in photoconductive mode. In ductive mode is shown in Fig. 9.32. As we can see, circuits
Fig. 9.31(b), the operational amplifier is used as a voltage with lower-resistance load line offer better linearity.
amplifier whereas in Fig. 9.31(c) and (d) the operational Avalanche photodiodes (APDs) are also connected in
amplifier is used in the transimpedance mode. For the cir- a similar manner as normal photodiodes except that a
cuit in Fig. 9.31(b), the output voltage and the effective much higher reverse-bias voltage is required. Also, the
resistance across the photodiode is ID R and R, respec- power consumption of APDs during operation is much
tively. The output voltage and effective resistance across higher than that of PIN photodiodes and is given by
the photodiode in Fig. 9.31(c) and (d) is ID Rf and the product of input signal, sensitivity and reverse-bias
Rf/A, respectively, where ID is the photodiode current voltage. Hence, a protective resistor is added to the bias
and A is the open loop gain of the operational amplifier. circuit (Fig. 9.33) or a current limiting circuit is used.
Current (mA) +Vbias
VR Voltage (V)
High load
line C
Rf
+V

Vo
+
Low V
load line
Figure 9.32| Load line analysis of photodiode in Figure 9.33| Application circuit using avalanche
photoconductive mode. photodiode.

An excessive input voltage, higher than the supply volt- some temperature offset circuit has to be added which
age of the stage following the photodiode, would damage changes the reverse-bias voltage in accordance with the
it, so a protective circuit should be connected so that temperature. As an alternative, a temperature controller
excessive voltages at the input are diverted to the power has to be added to keep the temperature of APD constant.
supply voltage line. For detecting low signal levels, shot noise from the back-
As the gain of APDs change with temperature, so ground light should be limited by using optical filters,
if they are operated over a wide temperature range, better laser modulation and restricted field of view.
IMPORTANT FORMULAS
1. VI characteristic equation or the Shockleys diode 6. Dynamic resistance of a diode is

equation is DVd
rd =
ID = I 0 (eVD hV T
1) DI d
7. Dynamic resistance (r) of a diode in the forward-
biased region 26h ID .
kT
2. VT =
q
8. Average AC resistance of a diode is
3. Variation of reverse saturation current with
(VD2 VD1 )
temperature for a diode is
(ID2 ID1 )
I 0 (T ) = I 0 (T1 ) 2(T T1 )/10 9. The relation between the transition capacitance
and the applied reverse bias of a varactor diode is
4. The variation of cut-in voltage and the forward
voltage of a diode with temperature is K
CT =
(Vg + VR )n
dV
= 2.5 mV/C 10. For an LED, the relation between the wavelength
dT
(in nm) of emitted light and band gap energy (in
5. Static resistance of a diode is eV) of the semiconductor material is
1240
l=
VD1
R=
ID1 Eg
SOLVED EXAMPLES
1. Given that the band-gap energies for silicon and At 25C, for silicon photodiode, Eg = 1.1eV, therefore
germanium photodiodes are 1.1 eV and 0.67 eV, l = 1240/1.1 nm = 1127.27 nm
respectively, at 25C. The cut-off wavelengths of sil- At 25C, for germanium photodiode, Eg = 0.67eV,
icon and germanium photodiodes, respectively, are therefore l = 1240/0.67 nm = 1850.75 nm
(a) 1127.27 nm, 1850.75 nm Ans. (a)
(b) 546.12 nm, 1127.27 nm 2. How will the cut-off wavelength of silicon photo-
(c) 1315.45 nm, 1850.75 nm diode given in Question 1 change if the operating
(d) 1850.75 nm, 2167.91 nm temperature changes from 25 to 100C?
Solution. The cut-off wavelength is given by the (a) 1127.27 nm (b) 1190.11 nm
formula (c) 1192.31 nm (d) 1187.45 nm
1240
l (nm) = Solution. The temperature variation of the band
Eg (eV) gap energy of silicon semiconductor is given by

SOLVED EXAMPLES 187
Eg (T ) = 1.21 3.60 104 T

width of 1 s and energy of 10 mJ is incident on the
active area of the photodiode. The responsivity of
where T is the temperature in kelvin. the photodiode is 0.5 A/W at 1000 nm.
Therefore, band gap energy at 100C is given by (a) 2.5 V (b) 2.25 V
Eg = 1.21 3.60 104 473
(c) 2.75 V (d) 2.0 V
= 1.21 0.17 = 1.04 eV

R2
The cut-off wavelength of silicon photodiodes at 10 k
100C is given by lc = 1240/1.04 nm = 1192.31 nm +12 V
Ans. (c) R1 +V
1 k

3. How will the cut-off wavelength of germanium pho-
todiode given in Question 1 change if the operating
Vo
temperature changes from 25 to 100C? +
(a) 1850.75 nm (b) 1823.53 nm
(c) 1768.67 nm (d) 1951.47 nm R V
50
Solution. The temperature variation of the band
gap energy of germanium semiconductor is given by
Eg (T ) = 0.785 2.23 104 T

where T is the temperature in kelvin. Solution. The incident light pulse has an energy
of 10 mJ and a pulse width of 1 s.
Therefore, band gap energy at 100C is given by Therefore, the input peak power = 10 103/1 =
Eg (T ) = 0.785 2.23 104 473 = 0.785 0.105
10 mW
Output current from the photodiode = 0.5 10
= 0.68 eV 103 = 5 mA
The cut-off wavelength of germanium photodiodes Voltage across the resistance R = 50 5 103
at 100C is given by lc = 1240/0.68 nm = 1823.53 nm = 250 mV
Ans. (b) Gain of the amplifier
4. The diffusion capacitance of a PN junction
R2 10 103
(a) decreases with increasing current and increasing = 1+ = 1+ = 11
R1 1 103
temperature
(b) decreases with decreasing current and increasing Amplitude of the output pulse = 250 103
temperature 11 = 2.75 V.
(c) increases with increasing current and increasing
temperature Ans. (c)
(d) does not depend on current and temperature 6. The change in forward-bias voltage for doubling
the forward current of a germanium semiconductor
Solution. Diffusion capacitance is given by
at 290 K is
tI f
CD = (a) 17.3 mV (b) 1.73 mV
hkT (c) 20.5 mV (d) 205 mV
where, If is the junction current, T is the tempera-
ture and h is the slope efficiency. Solution. The approximate Boltzmanns diode
From the above equation, CD If and CD (1/T). equation is
eV
Therefore, diffusion capacitance of a PN junction
I = I 0 exp
kT
decreases with decreasing current and increasing
temperature.
Ans. (b) Therefore,
5. For the circuit shown in the following figure, find
eV
the amplitude of the output voltage pulse when the I1 = I 0 exp 1
light pulse having wavelength of 1000 nm, pulse kT

ID(mA)
eV kT I2 I
and I2 = I 0 exp 2 or V2 V1 =
10 ln = 25 ln 2 mV
kT e 1
I I1
Hence, Given4.4that I2 = 2I1.
5
I2 e(V V1 ) Therefore, V2 V1 = 25ln2 = A 25 0.693 = 17.3
= exp 2
I1 kT mV
0.82 D
V (V)
0.68 Ans. (a)
0.2 0.4 0.6 0.8 1
(a)
1. Refer to the following figure. Determine the static ID(mA)
resistance of the diode at points A and B in ohms.
ID(mA) 40
40 35
35 30
B
25
30
20
25
B 15
20
10
15 5 A
VD (V)
10
0.2 0.4 0.6 0.8 1 1.2 2
5 A (b)
VD (V)
Ans. (375,45.6)
0.2 0.4 0.6 0.8 1 1.2 2
2. For the data given in Question 1, find the dynamic
Solution. Let us first consider point A (refer to resistance at point A in ohms.
part (a) of the following figure). Solution. The slope of the tangent line at point A
The diode current and voltage at point A are 2 mA gives the dynamic resistance of the diode at point A.
and 0.75 V, respectively. Part (a) of the figure in the solution of Question 1
Static resistance at point A = 0.75/(2 10-3) shows the exploded view of the characteristics near
= 375 . point A.
Let us now consider point B (refer to part (b) of the Dynamic resistance
following figure part).
0.82 0.68 140
= = = 31.8
(4.4 0) 103 4.4 103
The diode current and voltage are 25 mA and 1.14 V,
respectively.
Ans. (31.8)
Static resistance of the diode at point B = 1.14/
(25 10-3) = 45.6 3. For the data given in Question 1, find the dynamic
ID(mA) resistance at point B in ohms.
Solution. The slope of the tangent line at point
10 B gives the dynamic resistance of the diode at
point B (refer to part (b) of figure in solution of
4.4 Question 1).
5
A Dynamic resistance
VD (V)
1.195 1
0.82
0.195
0.68 = = = 9.75
0.2 0.4 0.6 0.8 1 (35 15) 103 20 103
Ans. (9.75)
(a)
ID(mA)
40
35
30 6/2/2015 11:22:40 AM
PRACTICE EXERCISE
1. P-side of a semiconductor diode is applied a 8. The photodiodes are operated in

potential of 0.5 V whereas the N side is applied a (a) reverse-bias condition
potential of 1.0 V. The diode shall (b) zero-bias condition
(a) conduct (b) not conduct (c) either of the two options mentioned in (a) and (b)
(c) conduct partially (d) breakdown (d) none of the two options mentioned in (a) and (b)
(1 Mark) (1 Mark)
2. In a semiconductor diode, the VI relationship is 9. The cut-in voltage for an LED is of the order of

such that (a) 1 V (b) 0.7 V (c) 0.3 V (d) 1.5 V
(a) current varies linearly with voltage (1 Mark)
(b) current increases exponentially with voltage 10. A varactor diode may be advantageous at micro-
(c) current varies inversely with voltage wave frequencies (indicate false answer)
(d) None of these (a) for electronic tuning
(1 Mark) (b) as an oscillator
3. The capacitance appearing across a reverse-biased (c) as a parametric amplifier
semiconductor junction (d) for frequency multiplication
(1 Mark)
(a) increases with increase in bias voltage
(b) decreases with increase in bias voltage 11. For the circuit shown in the following figure, the
(c) is independent of bias voltage capacitance of a varactor diode varies from 5 to
(d) None of these 50 pF. If L = 10 mH, the tuning range of the
(1 Mark) circuit is from Hz to kHz.
RS
4. There are two semiconductor diodes A and B. One
of them is Zener whereas the other is avalanche.
Their ratings are 5.6 V and 24 V, respectively, then C1
(a) A is Zener, B is avalanche V L 10 mH
(b) A is avalanche, B is Zener C2
(c) both of them are Zener diodes
(d) both of them are avalanche diodes
(1 Mark) (a) 318, 1000 (b) 318000, 1000
5. The static resistance of a diode is (c) 318, 1000000 (d) 318000, 1000000
(2 Marks)
(a) its opposition to the DC current flow
(b) its opposition to AC flow 12. The switching speed of P+N junction (having a
(c) resistance of diode when forward biased heavily doped P region) depends primarily on the
(d) None of these (a) mobility of minority carriers in the P+ region.
(1 Mark) (b) lifetime of minority carriers in the P+ region
6. The important specifications of a Zener diode are its (c) mobility of majority carriers in the N region
(d) lifetime of majority carriers in the N region
(a) breakdown voltage and power dissipation
(1 Mark)
(b) breakdown voltage, dynamic impedance and
13. In a Zener diode
power dissipation
(c) breakdown voltage and dynamic impedance (a) only the P region is heavily doped
(d) None of these (b) only the N region is heavily doped
(1 Mark) (c) both P and N regions are heavily doped
(d) both P and N regions are lightly doped
7. Typical value of impurity concentration in a tunnel (1 Mark)
diode is
14. In a junction diode the
(a) 1 part in 108 parts (b) 1 part in 106 parts (a) depletion capacitance increases with increase in
(c) 1 part in 103 parts (d) 1 part in 10 parts the reverse bias
(1 Mark) (b) depletion capacitance decreases with increase
in the reverse bias

(c) depletion capacitance increases with increase in (a) 150 mA (b) 200 mA (c) 1 A (c) 2 A
the forward bias (2 Marks)
(d) depletion capacitance is much higher than the
depletion capacitance when it is forward biased
(1 Mark)
D1 D2
15. The piecewise linear equivalent circuit model for
the diode shown in the following figure comprises of 20W
5V
(a) battery voltage of 0.8 V, resistance of 10 and
an ideal diode
(b) battery voltage of 0.8 V, resistance of 11 and
an ideal diode D4 D3
(c) battery voltage of 0.6 V, resistance of 10 and
an ideal diode
(d) Cannot be determined from given data
20. The diffusion potential across a PN junction
(2 Marks)
ID(mA) (a) decreases with increasing doping concentration
(b) increases with decreasing band gap
(c) does not depend on doping concentrations
20 (d) increases with increase in doping concentration
(1 Mark)
15 21. The static characteristic of an adequately forward-
biased PN junction is a straight line, if the plot is of
10
(ID is the diode current, VD is the diode voltage).
(a) logID versus logVD (b) logID versus VD
5 (c) ID versus logVD (d) ID versus VD
(2 Marks)
22. A50-Hz sinusoidal input voltage with an RMS
0.2 0.4 0.6 0.8 1.0 1.2 1.4 VD(V)
voltage of 1.44 V is applied to the circuit shown
Vottage differential in the following figure, part (a). The diode char-
between points A and B = 50 mV acteristics are shown in part (b). The maximum
16. A Zener diode works on the principle of output current is
(a) tunnelling of charge carriers across the junction (a) 20 mA (b) 24 mA (c) 28 mA (d) 32 mA
(b) thermionic emission (2 Marks)
(c) diffusion of charge carriers across the junction
(d) hopping of charge carriers across the junction
(1 Mark) Diode
RL
50
17. The depletion capacitance Cj of an abrupt PN vin(t) vo(t)
junction with constant doping on either side varies
with reverse-bias VR as
(a) Cj VR (b) Cj VR1 id(mA)
(a)
(c) Cj VR1/2 (d) Cj VR1/3
(1 Mark)
18. For small-signal AC operation, a practical forward- 40
biased diode can be modelled as a (an)
(a) resistance and a capacitance 30
(b) ideal diode and resistance in parallel
(c) resistance and an ideal diode in series 20
(d) resistance
(1 Mark) 10
current through the 20 resistor is (given that vd (V)
the forward voltage of the diode is 0.7 V and its 0.5 1.0 1.5 2.0
dynamic resistance is 2 ) (b)

23. For the data given in Question 22, the peak output kT 1 kT I
voltage across the load resistor is (a) V = sinh ln
(b) V =
q 2 q I0
(a) 1 V (b) 2 V (c) 1.2 V (d) 2.4 V
1
sinh1 (d) V =
kT kT
(2 Marks) (c) V = [exp(1) 1]
q
2 q
24. For a PN junction, match the type of breakdown (2 Marks)
with the phenomenon
26. For the circuit shown in the following figure, if
1. Avalanche breakdown V1 = 10 V, R1 = 1 k, Iknee = 1 mA, the mini-
2. Zener breakdown mum value of R2 so that the Zener diode stays in
3. Punch through the breakdown region is (Given that the breakdown
A. Collision of carriers with crystal ions voltage of the diode = 6 V.)
B. Early effect
C. Rupture of covalent bond due to strong electric (a) 2 k (b) 2.5 k (c) 3 k (d) 4 k
field. (2 Marks)
R1
(a) 1-B, 2-A, 3-C (b) 1-C, 2-A, 3-B +
(c) 1-A, 2-B, 3-C (d) 1-A, 2-C, 3-B
(1 Mark)
25. In the circuit shown in the following figure, the V1 D1 R2 Vout
currentvoltage relationship, when D1 and D2 are
identical, is given by (assume germanium diodes)
+
I
D1 27. For the circuit shown in Question 26, if V1 = 10 V,
R2 = 100 , Iknee = 1 mA and VZ = 6 V, the maxi-
mum value of R1 so that the Zener diode stays in
D2 the breakdown region is
V (a) 56.7 (b) 51.2

(c) 65.6 (d) 80.9
+
(1 Mark)
1. A silicon diode has a forward voltage drop of 5. The small signal capacitance of an abrupt P+N
1 V for a forward DC current of 100 mA. It has a junction is 1 nF/cm2 at zero bias. If the built-in
reverse current of 2 A for a reverse voltage of 5 V. voltage is 1 V, find the capacitance in nF/m2 at a
Find the bulk resistance of the diode in ohms. reverse-bias voltage of 99 V.
(1 Mark) (2 Marks)
2. For the data given in Question 1, find the reverse 6. For the diode circuit of the following figure (a),
resistance of the diode in megaohms. find the operating point in (V, mA). The VI char-
(1 Mark) acteristics of the diode are shown in (b).
3. For a P+N silicon junction with ND= 1016 cm3,
(2 Marks)
the breakdown voltage is 32 V. Find the maximum 100
electric field (V/cm) at the breakdown. (Given
that eSi = 11.9)
100
(2 Marks)
3V D
4. In a uniformly doped abrupt PN junction, the
doping level of the N-side is four (4) times the doping
level of the P-side, find the ratio of the depletion
layer width of N side versus P side.
(1 Mark)
(a)
IF (mA)
30
09-Chapter-09-Gate-ECE.indd 191 25 6/2/2015 11:22:43 AM
3V D 100

(a)
IF (mA) S
1 2
30 I
10 kW
25 20 V 20 V
20
16
8. For the circuit in Question 7 find the diode
10 current I(mA) at t = t0.
(1 Mark)
5
9. In the following figure, silicon diode is carrying a
VF (V) constant current of 1 mA. When the temperature
0 0.4 0.8 1.2 of the diode is 20C, VD is found to be 700 mV. If
(b) the temperature rises to 40C, find VD (in mV).
(2 Marks)
7. Referring to the circuit in the following figure,
the switch S is in position 1 initially and steady- +
state condition exist from time t = 0 to t = t0, the
switch is suddenly thrown into position 2. Find the 1 mA VD
current I (in mA) through the 10 kW resistor at
time t, t = 0.
(1 Mark)
Multiple Choice Question
1. (a) 6. (b) Therefore, the minimum tuning frequency

2. (b) 7. (c) 1 1
fmin = =
2p LCT (max) 2p 10 10 3
25 1012
3. (b) 8. (c)
= 318 kHz
4. (a) 9. (d)
5. (a) 10. (b) 12. (d) The switching speed of a P+N (heavily doped
P region) junction depends on the lifetime of major-
ity carriers (electrons) in the N region (lightly
11. (b) From the circuit, we can see that the two doped region).
varactor capacitances are in series.
13. (c) In a Zener diode, P and N both the regions are
Therefore, CT(min) = 5/2 pF = 2.5 pF and heavily doped. Doping level of Zener diode is of the
order of 1:105
CT(max) = 50/2 pF = 25 pF
14. (b) Depletion width d Reverse bias voltage
Therefore, the maximum tuning frequency
eA
Capacitance = C =
1 d
fmax =
2p LCT (min) Therefore,
1
C
1 d
=
2p 10 103 2.5 1012
= 1 MHz
C
or 1
Reverse bias voltage

15. (a) From part (a) of the following figure, we can 16. (a) A Zener diode works on the principle of tunnel-
see that the cut-in voltage is 0.8 V (approx.). ling of charge carriers across the junction, which
leads to junction breakdown.
The slope of the curve is given by taking two points
A and B in the linear region as shown in part (a) 17. (c) The depletion layer capacitance of a diode is
of the figure. given by
V VB 50 mV CT VR-n
Slope = A = = 10
I A IB 5 mA where n = 1/2 for step graded or abrupt PN
junction. Therefore, CT VR1/2
The piecewise equivalent model is shown in part(b)
of the figure. It comprises of a battery voltage of 18. (d) For small signal AC operation, a practical
0.8 V, resistance of 10 and an ideal diode. The forward-biased diode can be modelled as a
VI characteristic curve for the equivalent model is resistance.
also shown in the figure.
19. (a) The following figure shows the equivalent
ID(mA) circuit of the circuit shown in Question 19, with
each diode being replaced by its equivalent circuit.
20
D1
0.7 V
15
A
2 2
10
B
50 mV
0.7 V
D2
20
5 5V
B
0.2 0.4 0.6 0.8 1.0 1.2 1.4 VD(V) 0.7 V D3
(a)
2 2
0.7 V
0.8 V 10 ldeal D4
diode
ID(mA)
From this figure, we can see that the diodes D1 and
20 D3 are forward biased by a 5V battery whereas
diodes D2 and D4 are reverse biased. Hence, the
current will flow from point A to B and then to C
15 via the 20 resistance and then back to the nega-
tive terminal of the 5V battery.
10 Applying KVL in the 5VD12 0.7V20
D3 2 0.7V loop, we get
5 50.7 2I 20I 0.7 2I = 0
where I is the current through the 20W resistor.

0 0.2 0.4 0.6 0.8 1.0 VD(V)
3.6
Therefore, I = A = 150 mA
(b) 24

20. (d) The diffusion potential across a PN junction is id(t)(mA)
N N 40
VD = KT ln A 2 D
n
i 30 iL (t) mA
20
Therefore, at constant temperature VD NAND.
So, the diffusion potential accross a PN junction 10
increases with increase in doping concentration.
t
0.5 1.0 1.5 2.0 vin(t)(V)
21. (b) Forward current 0 vo(V)
I = I 0 (eVD /hVT 1) 1.2 V

10
As (eVD /hVT 1) 1
t
Therefore, 20
I = I 0 eVD /hVT
vin(t)(V)
Thus,
24. (d)
V D /hV T I
e =
I0 25. (b) From the given figure, we can see that diode D1
is forward biased and diode D2 is reverse biased.
VD I So, the current through diode D1 is forward current
or, = ln = ln(I ) ln(I 0 )
hV T
IF and current through diode D2 is reverse current I0.
I0
So, total current
Therefore, VD = hVTln(I) hVTln(I0). Comparing I = I F + I 0 = I 0 (eVD /hVT 1) + I 0

= I 0 eVD /hVT I 0 + I 0 = I 0 eVD /hVT
this with standard straight-line equation, y = mx + c,
we get
m = hVT, x = ln(I), c = hVTln(I0) and y = VD Therefore,
Therefore, plot of log I (diode current) vs. diode I
voltage (VD) is a straight line. eVD /hVT =
I0
22. (b) and 23. (c) VD I

or, = ln
The RMS voltage of 1.44 V implies a peak value of hV T I0
2 V, and a frequency of 50 Hz implies a time period Hence,
of 20 ms. I
VD = hVT ln
Load line is drawn for the peak value of the input I0
waveform. The load line equation is (2 = vd + id
For germanium diodes, h = 1. Substituting the value
50). The coordinates of the line on the voltage
of VT = kT/q, we get
and the current axes are (2 V, 0) and (0, 40 mA),
kT I
respectively.
or, VD = ln
The procedure is repeated for other values of the q I0
input waveform and the dynamic curve is drawn. The
relevant waveforms are shown in the following figure. Here the diode voltage VD is denoted as V.
From the figure, we see that the maximum output Therefore,
kT I
current is 24 mA. The peak output voltage across
the load resistor is 1.2 V. V = ln
q I0

26. (a) Current through the Zener diode is given by Hence,

6 3
V VZ VZ R < 3 10
ID = +IR1 IR 2 = + 1
2
R1 R2 Therefore, minimum value of R2 = 2 k
27. (c) From the given data,
For the Zener diode to stay in breakdown region,
ID > Iknee. Therefore, 10 6 6 3
+ > 1 10
R 100
10 - 6 6
1
+ > 1 103
1 103 R2 4
Hence,
61 103 <
R1
Therefore, maximum value of R1 = 65.6 .
1. Bulk resistance of a diode is Hence,

V F VB 1 0. 7 C j1
=3
1
= C j2 = = = 0.1 nF/cm2 = 100 nF/m2
IF 100 103 10 10
Ans. (3) Ans. (100)
2. Reverse resistance of a diode is
6. The circuit of Question 6 part (a) can be simplified
VR 5 using the Thevenins theorem. Thevenins equivalent
= 2.5 M
voltage VTH = (3 100/200) = 1.5 V. Thevenins
=
IR 2 106
equivalent resistance RTH = (100 100/200) = 50.
Ans. (2.5) The simplified equivalent circuit is shown in the
3. The width of the space charge region is following figure, part (a).
1 The load line is given by the equation
eV 2
W = 2 mm VTH = VD + ID RTH or 1.5 = VD + ID 50
2p eN d
The co-ordinates of the load line on the x- and
Therefore, the maximum electric field at breakdown the y-axis are (1.5 V, 0) and (0, 30 mA), respec-
tively. The load line superimposed on the VI
4p eN DW
3 105 V/cm
characteristics of the diode is shown in part (b) of
E=
e the following figure.
4. In the step graded diode, by using charge density The operating point is given by the intersection
condition or charge neutrality condition of the load line with the VI characteristics of the
diode. From part (b), we can see that the point is
WN N N 1 (0.8 V, 15 mA).
= A = A = = 0.25
WP ND 4N A 4
50
Ans. (0.25)
5. For abrupt PN junction, Cj VR1/2 where, Cj
is the junction capacitance per unit area and VR is
the reverse bias voltage.
Let Cj1 be the junction capacitance per unit area 1.5 V D
at reverse bias VR1 and Cj2 be the junction capaci-
tance per unit area at reverse bias VR2
Therefore,
C j2 V R1 1+ 0 1 1
= = = =
C j1 VR 2 1 + 99 100 10 (a)

IF (mA) 8. Diode is initially forward biased. At t = t0, the volt-

age is reversed. Therefore, the diode gets reverse
35 biased slowly. The direction of the current reverses
30 at t = t0, but its magnitude remains the same.
Therefore, current at t = t0 is 2mA.
25
Ans. (2)
20
9. For silicon diode
15
dV
2.5 mV/C
10
dT
5
1.5
VF (V)
0.4 0.8 1.2 1.6 Given that T2 T1 = 40 20 = 20C
(b)
Therefore, for constant I, change in diode voltage =
2.5 20 mV = 50 mV
Ans. (0.8,15)
7. At t = 0, the diode is forward biased.
Therefore, current Therefore, new diode voltage VD = 700 50 =
650 mV
20
I= A = 2 mA
10 103 Ans. (650)
Ans. (2)
1. Choose proper substitutes for X and Y to make h = 1 for germanium.

the following statement correct. Tunnel diode and Therefore, for germanium diode, the diode current
avalanche photodiode are operated in X bias and Y is given by
bias, respectively.
VDGe hV T
IGe = I 0Ge (e 1) = I 0Ge (eVDGe /VT 1)
(a) X: reverse, Y: reverse
(b) X: reverse, Y: forward where, I0Ge is the reverse saturation current of the
(c) X: forward, Y: reverse Ge diode.
(d) X: forward, Y: forward
(GATE 2003: 1 Mark) Given that the current through the two diodes are
equal, therefore
Ans. (c)
2. At 300 K, for a diode current of 1 mA, a certain ger-
manium diode requires a forward bias of 0.1435 V,
I 0Si e( VDSi 2VT
)
1 = I 0Ge e( VDGe VT
1 )
whereas a certain silicon diode requires a forward bias Substituting different values in the above equation,
of 0.718 V. Under the conditions stated above, the we get
closest approximation of the ratio of reverse saturation
current in germanium diode to that in silicon diode is
I 0Ge ( V
e DSi
VT
1 )=e 0.718 226103
1
= 4 103
( 1)
=
0.1435 26103
1
(a) 1 (b) 5 I 0Si V VT
e DGe e
(c) 4 103 (d) 8 103
Solution. For silicon at low value of current h = 2. 3. A particular green LED emits light of wavelength
. The energy band gap of the semiconductor
Therefore, for silicon diode, the doide current is 5490 A
material used there is (Plancks constant = 6.626
1034 Js)
given by
VDSi hV T
ISi = I 0Si (e 1) = I 0Si (eVDSi /2VT 1)
(a) 2.26 eV (b) 1.98 eV
where, I0Si is the reverse saturation current of the (c) 1.17 eV (d) 0.74 eV
Si diode. (GATE 2003: 2 Marks)

Solution. Band gap energy of a semiconductor 6. Consider an abrupt P junction. Let Vbi be the built-
material (in eV), which emits light at wavelength l in potential of this junction and VR be the applied
(in mm) is given by reverse bias. If the junction capacitance (Cj) is
1 pF for Vbi + VR = 1 V, then for Vbi + VR = 4 V,
1.24 Cj will be
Eg =
l
(a) 4 pF (b) 2 pF
Given that the LED emits at 5490 A . Therefore, (c) 0.25 pF (d) 0.5 pF
the emission wavelength in line is 5490 104 mm (GATE 2004: 2 Marks)
Therefore, band gap energy of the given semicon- Solution. We know that junction capacitance (Cj)
ductor material (in eV) is is related to the applied reverse bias (VR) by
C j VR1/2
1.24
Eg = = 2.26 eV
5490 104
Therefore,
Ans. (a) C j1 VR2 4
4. The longest wavelength that can be absorbed = = =2
C j2 VR1 1
by silicon, which has the band gap of 1.12 eV,
is 1.1 mm. If the longest wavelength that can be Hence,
absorbed by another material is 0.87 mm, then the
band gap of this material is
C j1 1 1012
C j2 = = F = 0.5 pF
2 2
(a) 1.416 eV (b) 0.886 eV Ans. (d)
(c) 0.854 eV (d) 0.706 eV
(GATE 2004: 2 Marks) 7. A silicon PN junction at a temperature of 20C
has a reverse saturation current of 10 pA. The
Solution. We have reverse saturation current at 40C for the same
1.24 1.24 bias is approximately
Eg = eV = eV = 1.42 eV
l(mm) 0.87 (a) 30 pA (b) 40 pA
(c) 50 pA (d) 60 pA
Ans. (a) (GATE 2005: 1 Mark)
5. In an abrupt PN junction, the doping concentra-
tions on the P side and N-side are NA = 9 1016/ Solution. The reverse saturation current of a PN
cm3 and ND = 1 1016/cm3, respectively. The PN junction diode, doubles itself for every 10C rise in
junction is reverse biased and the total depletion temperature.
width is 3 mm. The depletion width on the P side is Therefore, the reverse saturation current at 40C is
four times the reverse saturation current at 10C.
(a) 2.7 mm (b) 0.3 mm
(c) 2.25 mm (d) 0.75 mm Therefore, reverse saturation current at 40C is
(GATE 2004: 2 Marks) 40pA.
Ans. (b)
8. A silicon PN junction diode under reverse bias has
WN N depletion region of width 10 mm. The relative per-
= A
WP ND mittivity of silicon, er = 11.7 and the permittivity
of free space e0 = 8.85 1012 F/m. The depletion
where, WN is the depletion width of N-side, WP capacitance of the diode per square metre is
(a) 100 mF (b) 10 mF
is the depletion width of P-side, NA is the doping
(c) 1 mF (d) 20 mF
concentration of P-side and ND the doping concen-
tration of N-side. (GATE 2005: 2 Marks)
Therefore,
Solution. Depletion capacitance of a diode
W N D (3106 WP ) 1016
WP = N = e0er A
NA 9 1016 C=
d
Therefore, WP = 0.3 mm where, d is the width of the depletion region and A
Ans. (b) is the area.

The depletion capacitance of the diode per square Solution. Diode retains resistance of forward-bias
metre is given by C/A. From the given data, condition in reverse bias (ideally zero resistance)
for the time interval of storage time.
e e 8.85 1012 11.7 Therefore, during storage time, VR = 5 V
F = 10.35 mF
C
= 0 r =
A d 10 106
Ans. (a)
10 mF
11. Find the correct match between Group 1 and
Ans. (b) Group 2.
9. The values of voltage (VD) across a tunnel diode
Group 1
corresponding to peak and valley currents are VP
E. Varactor diode
and VV, respectively. The range of tunnel diode
F. PIN diode
voltage VD for which the slope of its IVD charac-
G. Zener diode
teristics is negative would be
H. Schottky diode
(a) VD < 0 (b) 0 VD < VP Group 2
(c) VP VD < VV (d) VD VV 1. Voltage reference
(GATE 2006: 1 Mark) 2. High-frequency switch
3. Tuned circuits
Solution. The IVD characteristics of a tunnel
4. Current-controlled attenuator
diode are shown in the following figure.
(a) E-4, F-2, G-1, H-3 (b) E-2, F-4, G-1, H-3
I (c) E-3, F-4, G-1, H-2 (d) E-1, F-3, G-2, H-4
Peak point (GATE 2006: 2 Marks)
IP
Negative Ans. (c)
resistance
region 12. In a P N junction diode under reverse bias, the
+
magnitude of electric field is maximum at
Valley (a) the edge of the depletion region on the P side

point (b) the edge of the depletion region on the N side
IV (c) the P+-N junction
VD (d) the centre of the depletion region on the N side
VP VV (GATE 2007: 1 Mark)
Solution. Electrical field is always maximum at

From the above curve, we can see that the slope of
IVD characteristics is negative for VP VD < VV.
the junction.
Ans. (c)
This region is also referred to as the negative resis-
tance region. 13. A P+-N junction has a built-in potential of 0.8 V.
The depletion layer width at a reverse bias of 1.2 V
Ans. (c)
is 2 mm. For a reverse bias of 7.2 V, the depletion
10. In the circuit shown below the switch was con- layer width will be
nected to position 1 at t < 0, and at t = 0 it is
(a) 4 mm (b) 4.9 mm
changed to position 2. Assume that the diode has
(c) 8 mm (d) 12 mm
zero voltage drop and a storage time ts for 0 < t ts.
VR is given by (all in volts)
1 Solution. Junction potential = Built-in potential
+ + Reverse-bias voltage Therefore, Vj = Vo + VR
Now for abrupt PN junction, depletion width
2
W = kVj1/2
5V
5V 1 k VR Let the depletion width at reverse bias of 1.2 V be
W1 and 7.2 V be W2.
Therefore,
W1 = k(1.2 + 0.8)1/2
and W2 = k(7.2 + 0.8)1/2
(a) VR = 5 V (b) VR = +5 V
(c) 0 VR < 5 V (d) 5 V < VR < 0 V W2 k (8)1/2
(GATE 2006: 2 Marks) Therefore, = =2
W1 k (2)1/2

Hence, W2 = 2W1 = 4 mm Built in potential,

Ans. (a) kT N A N D
Vo = ln 2
14. Which of the following is NOT associated with a q ni
PN junction? where,
(a) Junction capacitance kT
(b) Charge storage capacitance = VT (thermal voltage) = 26 mV
q
(c) Depletion capacitance
Therefore,
(d) Channel length modulation
1022 1023
(GATE 2008: 1 Mark) Vo = 26 103 ln = 0.76 V
Ans. (d) (1.4 1016 )2
Ans. (b)
15. Consider the following assertions: 17. The peak electric field in the device is
S1: For Zener effect to occur, a very abrupt junc- (a) 0.15 mV/cm, directed from P-region to N-region
tion is required. (b) 0.15 mV/cm, directed from N-region to P-region
S2: For quantum tunnelling to occur, a very narrow (c) 1.8 mV/cm, directed from P-region to N-region
energy barrier is required. (d) 1.80 mV/cm, directed from N-region to P-region
Which of the following is correct?
e = q N D (W =WN +WP)
(a) Only S2 is true.
(b) S1 and S2 are both true but S2 is not a reason
for S1. Therefore,
E = dx
(c) S1 and S2 are both true and S2 is a reason for S1. e
(d) Both S1 and S2 are false. e
(GATE 2008: 2 Marks) 1.110 6
e
Ans. (b) = e
dx
0
Common Data for Q. 16 and 17: Consider a silicon 1.6 1019
= 1 1017 1.1 106 102
12 8.25 10 14
PN junction at room temperature having the following
parameters:
Doping of the N-side = 1 1017 cm3 = 0.146 mV/cm 0.15 mV/cm
Depletion width on the N-side = 0.1 m It is directed from N- to P-region, from positive
Depletion width on the P-side = 1.0 m charges of transition region dipole toward the nega-
Intrinsic carrier concentration = 1.4 1010/cm3 tive charges.
Thermal voltage = 26 mV Ans. (b)
Permittivity of free space = 8.85 1014 F/cm
Dielectric constant of silicon = 12 18. Compared to a PN junction with NA = ND = 1014/cm3,
which one of the following statements is TRUE for
16. The built-in potential of the junction a PN junction with NA = ND = 1020/cm3?
(a) is 070 V (b) is 0.76 V (a) Reverse breakdown voltage is lower and deple-
(c) is 0.82 V (d) cannot be estimated tion capacitance is lower.
from the data given (b) Reverse breakdown voltage is higher and deple-
(GATE 2009: 2 Marks) tion capacitance is lower.
(c) Reverse breakdown voltage is lower and deple-
Solution. Given that: tion capacitance is higher.
ND = 1 1017 106/m3 = 1 1023/m3 (d) Reverse breakdown voltage is higher and deple-
Depletion width WN = 0.1 m tion capacitance is higher.
Depletion width WP = 1.0 m (GATE 2010: 2 Marks)
ni = 1.4 1010 106/m3 = 1 1016/m3 Solution. With increase in doping, the reverse
We know that: breakdown voltage decreases and depletion width d
also decreases. As depletion capacitance, C = A/d,
WP N A = WN N D so depletion capacitance increases with increase in
Therefore, doping.
N A = 1 1022/m3
Ans. (c)


19. A silicon PN junction is forward biased with a

1 k
constant current at room temperature. When the
temperature is increased by 10C, the forward-bias i
voltage across the PN junction
+ +
(a) increases by 60 mV 10 V V
(b) decreases by 60 mV
(c) increases by 25 mV
(d) decreases by 25 mV
(GATE 2011: 1 Mark)
Solution. The rate of change of forward-bias voltage The current in the circuit is
of a PN junction with temperature is given by
(a) 10 mA (b) 9.3 mA
dV
= 2.5 mV/C (c) 6.67 mA (d) 6.2 mA
dT (GATE 2012: 1 Mark)
From the above equation, we see that for 10C
increase in temperature, forward voltage across Solution. Applying KVL to the given circuit,
PN junction decreases by 25 mV. we get
Ans. (d) 10 1000i V = 0
20. A Zener diode, when used in voltage stabilization The diode in the given circuit is forward biased and
circuits, is biased in the current through the diode is
(a) reverse-bias region below the breakdown voltage V 0.7
i= A
(b) reverse breakdown region 500

(c) forward-bias region Substituting this value of i in the above equation
(d) forward-bias constant current mode we have
(GATE 2011: 1 Mark)
(V 0.7)
Solution. The following figure shows the charac- 10 1000 V = 0
500
teristics of a Zener diode. Solving the above equation, we get
IZ 11.4
V = = 3. 8 V
3
VZ
VR Therefore, current through the diode is
V 0. 7 3.8 0.7
i= = = 6.2 mA
500 500
Ans. (d)
22. In a forward-biased PN junction, the sequence of
events that best describes the mechanism of cur-
rent flow is
Breakdown
(a) injection and subsequent diffusion and recombi-
region
nation of minority carriers
Both Zener and avalanche diodes are used in voltage (b) injection and subsequent drift and generation
stabilization circuits, to regulate the load voltage of minority carriers
against variations in load current and input volt- (c) extraction and subsequent diffusion and genera-
age. They are used in these applications, because in tion of minority carriers
the breakdown region large change in diode current (d) extraction and subsequent drift and recombina-
produces only a small change in the diode voltage. tion of minority carriers
(GATE 2013: 1 Mark)
Ans. (b)
21. The IV characteristics of the diode in the circuit Solution. In a forward-biased PN junction diode,
given below are due to application of forward bias voltage, minor-
V 0.7 ity carriers are injected from either side of diode,
i= A, V 0.7 V followed by diffusion and finally recombination.
500
Ans. (a)

CHAPTER 10
BJTs AND FETs
This chapter covers all the fundamental topics related to bipolar junction transistors (BJTs), field-effect transistors
(FETs), metal-oxide semiconductor (MOS) devices and insulated gate bipolar transistors (IGBTs).
10.1 TRANSISTOR CONSTRUCTION base region is very lightly doped. The doping of the base
AND TYPES region is around 10 times less than that of the emitter
region. This results in reduced conductivity of the base
region. Bipolar transistors can be classified as NPN and
A bipolar junction transistor (BJT) is a three-layer, PNP transistors depending upon the type of doping
three-terminal semiconductor device having two PN of the three regions. In case of an NPN transistor, a
junctions. It comprises of three differently doped thin layer of P-type material is sandwiched between the
semiconductor regions, namely, the emitter region, the two layers of N-type materials. For a PNP transistor, a
base region and the collector region. The base region thin layer of N-type material is sandwiched between two
is physically sandwiched between the emitter and the layers of P-type materials.
collector regions. BJTs are named so because both holes
and electrons contribute to the flow of current. 10.1.1 NPN Transistor
The width of the base region is much smaller
compared to the width of the emitter and the collector Figure 10.1(a) shows the structure of an NPN transistor.
regions. Typical ratio of the total width of the transis- As is evident from the figure, the collector and the emitter
tor to the width of the base region is of the order of regions are N-type semiconductors and the base region is
few hundreds. The emitter region is the most heavily a P-type semiconductor. The collector, emitter and the
doped, the collector region moderately doped and the base terminals are designated as C, E and B, respectively.

202 Chapter 10: BJTs AND FETs
Base 10.2 TRANSISTOR OPERATION

C
The basic operation of an NPN transistor is described in

Emitter P Collector
E C this section. The operation of a PNP transistor is same
N N B
as that of an NPN transistor except that the roles of
electrons and holes are interchanged and the polarities
of the voltages and the direction of current reversed.
Transistors may be looked upon as two PN junction
B E
diodes connected back to back. The two junctions
(a) (b) are the emitterbase junction and the collectorbase
junction. The fundamentals of semiconductor junction
Figure 10.1| (a) Structure of an NPN transistor. diodes covered in Chapter 9 apply to transistors also and
(b) Circuit symbol of an NPN transistor. will be used to explain the operation of a transistor. As
we have studied in Chapter 9, when the PN junction
diode is open circuit, no current flows through it and
Figure 10.1(b) shows the circuit symbol of an NPN tran- the diode voltage is equal to the diodes contact poten-
sistor. The arrow on the emitter lead specifies the direction tial. Similarly, when no external voltage is applied to the
of the conventional current flow when the emitterbase transistor, the current flowing through the transistor is
junction is forward biased. In an NPN transistor, most of zero and the potential at the two junctions is equal to
the current flow is due to flow of electrons. their respective contact potentials.
Transistors operate in four regions, namely, the active
region, reverse-active region, saturation region and cut-
10.1.2 PNP Transistor off region, depending upon the polarity of voltages
applied to the emitterbase and the collectorbase junc-
Figure 10.2(a) shows the structure of a PNP transistor. tions. In the active region, the emitterbase junction is
The collector and the emitter regions are P-type forward biased and the collectorbase junction is reverse
semiconductors and the base region is an N-type semi- biased. Transistors when operating in the active region
conductor. Figure 10.2(b) shows the circuit symbol of a function as amplifiers. In the reverse-active region, the
PNP transistor. The arrow on the emitter lead specifies biasing condition is reversed, that is, the emitterbase
the direction of the conventional current flow when the junction is reverse biased and the collectorbase region
emitterbase junction is forward biased. In a PNP tran- is forward biased. Transistors are seldom operated in the
sistor, holes contribute mostly to the flow of current. reverse-active region. In the saturation region, both the
emitterbase and the collectorbase junctions are for-
ward biased and in the cut-off region both the junctions
Base
C are reverse biased. When a transistor is used as a switch-
ing device it operates either in the saturation or in the
cut-off region. It acts as a closed switch in the saturation
region and as an open switch in the cut-off region. When
E Emitter N Collector C
B used as an amplifier, the transistor is operated in the
P P
active region.
Let us now discuss the operation of an NPN transistor.
When the emitterbase junction is forward biased with
B E an open collectorbase junction [Fig. 10.3(a)], normal
PN junction diode action takes place. The width of the
(a) (b) depletion region decreases due to the applied bias and
Figure 10.2| (a) Structure of a PNP transistor.
there is a heavy flow of electrons from the N-type emitter
(b) Circuit symbol of a PNP transistor. to the P-type base. As the base is lightly doped, a very
small hole current travels from the P-type base to the
N-type emitter region. The width of the depletion region
NPN transistors are more commonly used as compared is larger in the base region compared to that in the emit-
to PNP transistors as they offer higher current density ter region as the base is lightly doped in comparison
and faster switching times. This is because the electron with the emitter region. If the collectorbase junction
mobility is higher than the hole mobility. is reverse biased with the emitterbase junction open

10.2 TRANSISTOR OPERATION 203
[Fig. 10.3(b)], it behaves like a normal reverse-biased low level of conductivity (as it is lightly doped), only a
junction diode. There is a small current flow due to the very few electrons remain in the base region. Rest of the
minority carriers, that is, the flow of electrons from the electrons diffuse into the reverse-biased basecollector
base region to the emitter region and flow of holes from junction. They travel across the basecollector junction
the emitter to the base. The depletion width increases easily as they appear as minority carriers in the P-type
with the increase in the reverse-bias voltage and is larger base region of the basecollector junction. This is
in the base region as compared to that in the collector referred to as the injection of the minority carriers into
region. the P-type base region. (You will recall that in a reverse-
biased PN junction diode, the minority carriers easily
Majority cross the junction.) These electrons diffuse across the
carriers (electrons) reverse-biased junction to reach the N-type collector and
constitute the collector current (IC). The magnitude of
the base current is of the level of few microamperes as
E C compared to several milliamperes for the collector and
N P N the emitter current.
Applying Kirchoffs current law to the transistor,
considering it as a node
B
I E = IC + I B (10.1)
VEB Open circuit where IE is the emitter current, IC is the collector current
and IB is the base current.
(a)
From Eq. (10.1), we can infer that the emitter current
is the sum of the collector current and the base current.
Minority The collector current comprises of two components: the
carriers majority-carrier component and the leakage-current
component. The majority-carrier component is due to
the electrons that have travelled from the emitter region
E C across the base to the collector region. This component
N P N is equal to (aIE), where a is the fraction of emitter
electrons that reach the collector region. The leakage
current (ICO) is the minority current of the reverse-
B biased basecollector junction with an open-circuit emit-
terbase junction. ICO is in the range of few hundreds of
nanoamperes to few microamperes. The expression for
Open circuit VCB collector current is given by:
IC = aI E + ICO (10.2)
(b)
Figure 10.3| (a) Forward-biased emitterbase junction. Flow of electrons

(b) Reverse-biased collectorbase junction.
Figure 10.4 shows the flow of current in an NPN ICO

transistor in the active region, that is, both the forward
E IE aIE C
and the reverse voltages are applied simultaneously to
the emitterbase and the collectorbase junctions, respec- IB
tively. The emitter current (IE) comprises of electron
N P N
current due to the flow of electrons from emitter to base
and the hole current due to the flow of holes from base B
to emitter. As the base is very lightly doped in compari-
son to the emitter, the emitter current consists mainly
of electrons. Not all electrons crossing the emitterbase VEB VCB
junction reach the basecollector junction as some of
them remain in the base region and constitute the base Figure 10.4| Flow of current in an NPN transistor in
current (IB). As the base region is very thin and has the active region.

Equation (10.2) is valid only in the active region of the 10.3.1.1 Input Characteristics
transistor. The generalized expression for the collector
current in a transistor is given by the following expression: The input characteristics of a transistor are a plot of the
V
input current versus the input junction voltage for differ-
IC = aI E + ICO 1 exp CB (10.3) ent values of output junction voltage. The input charac-
VT teristics of common-base configuration relate the emitter
where VCB is the voltage across the collectorbase junc- current (IE) to the emitterbase voltage (VEB) for vari-
tion and VT is the volt-equivalent of temperature. ous levels of the collectorbase voltage (VCB). Figure
10.6 shows the input characteristics of a common-base
When the collectorbase junction is sufficiently reverse
NPN silicon transistor. The current IE is taken negative
biased, the term exp(VCB/VT) tends to zero and Eq.
as the current flows out of the emitter terminal. The
(10.3) reduces to Eq. (10.2).
input characteristics of PNP transistors are same with
the polarity of the voltages and currents reversed.
10.3 TRANSISTOR CONFIGURATIONS
IE (mA)
VCB = 10 V
Transistors are connected in any of the following three 25 VCB = 20 V
configurations:
1. Common-base (CB) configuration 20 VCB = 1 V
2. Common-emitter (CE) configuration
3. Common-collector (CC) configuration VCB = 0 V
15 VCB = Open
10.3.1 Common Base Configuration
10
In the common-base configuration, the base terminal is
common to both the input and the output sections. Figures
10.5(a) and (b) show the basic circuit of the transistor in 5
the common-base configuration for the NPN and the PNP
transistors, respectively. The directions of currents shown
0.2 0.4 0.6 0.8 1.0 VEB (V)
are the ones used for conventional current flow. Also, the
0
current flowing into the transistor is taken as positive and
the current leaving the transistor is taken as negative. Figure 10.6| Input characteristics of a common-base
transistor.
IE IC
From the figure we can infer that there is a cut-in or
E C threshold voltage below which the value of the emitter
Ri RL current is very small. The typical value of cut-in voltage
B
for silicon and germanium transistors are approximately
VEE IB VCC 0.5 V and 0.1 V, respectively. The curve for open condi-
tion is the same as that for a forward-biased PN junction
diode. Another feature of the input characteristics is
that for a fixed value of collectorbase voltage (VCB), as
(a)
the emitterbase voltage (VEB) increases the value of the
emitter current (IE) increases. This behaviour is the same
IE IC as that of a PN junction diode in the forward-biased
state. As a small change in the emitterbase voltage
E C causes a very large change in the emitter current, the
Ri B RL input resistance (ri) of the common-base configuration
is very small. The value of ri in the linear portion of the
VEE IB VCC input characteristics is of the order of hundred ohms.
Also, it can be interpreted from the figure that for fixed
value of emitterbase voltage (VEB), the emitter current
(b) (IE) increases with increase in the value of the collector
base voltage (VCB). This is because of the early effect
Figure 10.5| Common-base configuration. (a) NPN phenomenon in transistors.
transistor and (b) PNP transistor.

10.3 TRANSISTOR CONFIGURATIONS 205
Early effect or the base width modulation phenomenon for various levels of the emitter current (IE). For a fixed
refers to the change in the width of the base region with value of emitter current, the collector current almost
the change in the collectorbase voltage. As the emitter remains constant with changes in the value of the
base junction is forward biased, the width of the depletion collectorbase voltage. However, near the origin, the
region is negligible. For the reverse-biased collectorbase collector current drops rapidly with the decrease in
junction, the width of the depletion region is substantial. the value of the collectorbase voltage. The output char-
The width of the depletion region increases with increase acteristics can be divided into three regions, namely, the
in the reverse voltage at the collectorbase junction. As active region, the cut-off region and the saturation region.
the base region is lightly doped, the penetration of the
depletion region is much larger in the base region than IC (mA)
in the collector region. As a result of this, the effective IE = -25 mA
Saturation region
width of the base region decreases. This phenomenon 25
of change in the effective width of the base region with
change in the collectorbase voltage is referred to as the IE = -20 mA
20
early effect.
As a result of early effect, at increased reverse IE =-15 mA
otential the rate of recombination of the electrons and
p 15
holes decreases. This results in increase in the value of a. Active region
IE = -10 mA
Also, the concentration of the minority carriers becomes 10
zero at effective base width (WB) instead of WB (Fig.
10.7). Hence, the concentration gradient of minority IE = -5 mA
carriers (Pn) is increased within the base region. As the 5
emitter current is proportional to the gradient of minority
IE = 0 mA
carriers at the emitter junction (JE), the value of emitter
current also increases. 0 4 8 12 16 VCB (V)
Cut-off region
Pn Figure 10.8| Output characteristics of the common-
base transistor.
Active Region
In the active region, the collectorbase junction is
Zero reverse reverse biased while the emitterbase junction is forward
Minority bias biased. The unshaded portion of Fig. 10.8 corresponds
carrier to the active region. The collector current (IC) is almost
concentration Large reverse independent of the collectorbase voltage (VCB) and
bias depends only on the value of the emitter current (IE).
Therefore, the output characteristics curves are straight
parallel lines. As we can see from the figure, the collector
current increases slowly with the collectorbase volt-
age (around 0.5%). This is because of the early effect
JE JC phenomenon. But for most applications, this increase
(WB) can be ignored and the collector current can be consid-
Physical width ered to be constant for a fixed value of emitter current.
of base (WB) The output resistance (ro) offered by the common-base
Figure 10.7| Early effect
configuration is very high as a very large change in the
collectorbase voltage produces a very small change in
the collector current.
10.3.1.2Output Characteristics When the emitterbase junction is open circuited,
emitter current is zero. The collector current that flows
The output characteristics of a transistor are a plot of in this condition is the reverse saturation current (ICO).
the output current and the outputjunction voltage for This condition corresponds to the lowest curve in the
different values of input current. The output characteris- output characteristics. The current ICO is of the order of
tics of common-base configuration (Fig. 10.8) relate the few microamperes for germanium transistors and several
collector current (IC) to the collectorbase voltage (VCB) nanoamperes for silicon transistors.

Cut-Off Region the emitter current (IE), collector voltage (VCB) and the
operating temperature. The voltage gain of the common-
In the cut-off region, both the collectorbase and the
base configuration is in the range of 50300. Therefore,
emitterbase junctions of a transistor are reverse biased.
a common-base transistor acts as a voltage amplifier and
The region below the IE = 0 curve corresponds to the
not as a current amplifier.
cut-off region. In this region, the transistor acts as
an open circuit and does not conduct any current. As When a time-varying input is applied, the point of
mentioned before, the value of collector current at IE = 0 operation moves on the output characteristics curve. In
is equal to the reverse saturation current (ICO). that case, an ac alpha (aac) is defined as the ratio of the
change in the collector current to the change in the emitter
ICO increases rapidly with increase in temperature.
current for a fixed value of collectorbase voltage:
As an example, for a general purpose silicon transistor
I
a ac = C
2N2222, the values of ICO at a collectorbase voltage of (10.7)
50 V for ambient temperature of 25C and 150C are I E VCB = const
10nA and 10 mA, respectively. This implies that there is
a change of the order of 1000 times for 125C change in where aac refers to common-base, short circuit amplifica-
temperature. ICO is also referred to as ICBO, the collector tion factor.
current with base open circuited. ICBO can be ignored in
most transistor applications except for power transistors 10.3.2 COMMON-EMITTER CONFIGURATION
and transistors operating at high temperatures.
The common-emitter configuration has emitter terminal
Saturation Region common to both the input and output sections as shown
in Figs. 10.9(a) and (b) for the NPN and the PNP
In the saturation region, both the collectorbase and the
transistors, respectively. The input signal is applied to
emitterbase junctions are forward biased. The region
to the left of VCB = 0 line corresponds to the satura-
tion region. As is clear from the figure, the collectorbase
voltage (VCB) is slightly negative in the saturation region. IC
VCC
This is because the collectorbase junction is also forward C
biased. There is an exponential increase in the collector
B
current with a small increase in the collectorbase voltage.
IB
Alpha (a) Ri RL
E
Alpha (a) is the fraction of emitter current that contrib-
utes to the collector current. The current equation in a VBB
IE
transistor is given by the following expression:
IC = ICO + aI E (10.4)
Equation (10.4) can be rewritten as follows:
(a)
(I ICO )
a= C (10.5)
(I E 0)

a can be defined as the ratio of the increment in the IC
value of collector current from its value in the cut-off VCC
region to the increment in the value of emitter current C
from its value in the cut-off region. As mentioned before, B
the value of ICO is very small and can be ignored in
IB
the large-signal analysis. Therefore, the current equation RL
reduces to the following expression: Ri E
IC = aI E (10.6) VBB IE
Therefore, a is also referred to as the large-signal current

gain of a common-base transistor. In the active region,
the value of a is nearly equal to 1, the exact value being
between 0.90 and 0.998. Therefore, the current gain of (b)
the transistor in the common-base mode is less than Figure 10.9| Common-emitter configuration for the
unity. The value of a is not constant but varies with (a) NPN transistor and (b) PNP transistor.

10.3 TRANSISTOR CONFIGURATIONS 207
the baseemitter section and the output is taken from the voltage (VCE) for different values of base current (IB).
collectoremitter section. It is the most commonly used The output characteristics of a common-emitter tran-
transistor configuration. Salient features of common-emitter sistor are shown in Fig. 10.11. The output curves for
transistor configuration are high values of voltage and current common-emitter configuration are not as horizontal as
gains, medium value of input and output impedances. that for common-base configuration, indicating that the
collectoremitter voltage has an influence on the value
10.3.2.1Input Characteristics of collector current.
The input characteristics of the transistor in the Beta (b)

common-emitter configuration relate the base current (IB)
to the baseemitter voltage (VBE) for different values of For any transistor, the emitter, collector and base currents
the collectoremitter voltage (VCE). The input character- are related to each other by the following expression:
istics for a common-emitter NPN transistor are shown in
I E = IC + I B (10.8)
Fig. 10.10. We can see from the figure that the magnitude
of base current (IB) is in the range of several tens of micro-
Relationship between collector and emitter current is
amperes. For fixed value of baseemitter voltage (VBE),
also given by
an increase in the value of collectoremitter voltage (VCE)
results in decrease in the value of base current (IB). This is
IC = ICO + aI E (10.9)
because of the early effect, which results in reduction of base
width with increase in the collectoremitter voltage (VCE). Combining Eqs. (10.8) and (10.9), we get
IB (A)
a 1
IC = IB + I (10.10)
VCE = 1 V VCE = 10 V (1 a ) (1 a ) CO
90
80
70 If we substitute
a
b=
60 VCE = 0 V VCE = 20 V
50 (1 a )
40 Then Eq. (10.10) becomes
30
20 IC = bIB + (b + 1)ICO (10.11)

10
b is referred to as the DC forward current transfer
VBE (V)
0 0.2 0.4 0.6 0.8 1.0 ratio or the DC current gain of the transistor. A very
small change in the value of a is reflected as a very
Figure 10.10| Input characteristics of common-emitter
large change in the value of b. The common-emitter
transistor.
characteristics of the transistors of the same type
10.3.2.2Output Characteristics number differ significantly from one device to another.
The value of b varies considerably with changes in
Output characteristics of the common-emitter configura- both the operating temperature and collector current
tion relate the collector current (IC) to the collectoremitter (Fig. 10.12).
IC (mA)
VCE (sat) IB = 100 A
Normalized static forward
10 10
7
IB = 80 A
current transfer ratio,
Saturation 8 4
region
6 IB = 60 A 2
Active region TA = 100C
IB = 40 A
1
4 0.7 TA = 25C
TA = 40C
IB = 20 A 0.4
2
IB = 0 A
0.2
VCE (V)
0 5 10 15 20 0.1 IC (mA)
Cut-off region 0.1 0.4 1 4 10 40 100
Figure 10.11| Output characteristics of common-emitter Figure 10.12| Variation of b with change in temperature
transistor. and collector current.

Active Region Cut-Off Region

As in the case of common-base transistor configura- In the cut-off region, both the collectorbase and the emitter
tion, for common-emitter transistor configuration also base junctions are reverse biased. Also, in the cut-off region, the
the baseemitter junction is forward biased in the active base current is equal to zero (IB = 0). In the common-emitter
region and the collectorbase junction is reverse biased. configuration, for IB = 0, there is a considerable amount of
The active region in the output characteristics (Fig. collector current flowing through the transistor. Its value is
10.11) corresponds to the portion of the graph to the right given by substituting the value IB = 0 in Eq. (10.11). So,
of the line at VCE(sat) and above the curve for IB = 0. I
IC = (b + 1)ICO = CO (10.12)
(1 a )
As can be seen from the figure, the curves of collector
current (IC) for different values of base current (IB)
are not as horizontal and parallel as the curves for the This current is denoted by the symbol ICEO.
common-base configuration. Transistors in the common- For silicon transistors, the value of a near cut-off region
emitter configuration operating in the active mode are is nearly zero. Therefore, the value of collector current is
used as voltage, current and power amplifiers. equal to ICO. Hence, the silicon transistor is in the cut-
As IB >> ICO in the active region, therefore in the off region when IB = 0 both for short circuit (VBE = 0)
active region IC = bIB. and reverse-biased baseemitter junction.
As mentioned before, b is the DC forward current For germanium transistors, the value of a near cut-off
transfer ratio or the DC current gain of the transistor. region may be as large as 0.9. Therefore, the value of the
It is also denoted as hFE. Typical value of b is in the collector current flowing through the transistor can be as
range of 50100. Hence, the common-emitter configura- large as ten times the value of leakage current ICO. Hence,
tion provides high current gain. It also provides a large the germanium transistor is not in the cut-off region for
value of voltage and power gain. IB = 0. A reverse bias needs to be applied to the baseemitter
For AC applications, b (bac) is defined as
junction to bring the transistor to cut-off. The bias volt-
age applied should bring the value of collector current
IC (IC) less than or equal to reverse saturation current (ICO).
bac =
IB Reverse-bias voltage of 0.1 V is sufficient to reduce the
collector current to this value. Therefore, the germanium
for constant common-emitter voltage. transistor is in the cut-off region when IB = 0 for reverse-
bac is referred to as the common-emitter forward- biased baseemitter junction with VBE greater than 0.1 V.
current amplification factor and is also denoted by hfe.
10.3.3COMMON-COLLECTOR CONFIGURATION
Saturation Region
In the common-collector configuration, also known as the
The common-emitter transistor is in the saturation region emitter follower configuration, the collector terminal is common
when both the collectorbase and the emitterbase junctions to both the input and the output sections. Figures 10.13(a)
are forward biased. Magnitudes of collectorbase voltage and (b) show the NPN and PNP transistors connected in
(VCB) and emitterbase voltage (VEB) are equal to the cut-in common-collector configuration. The configuration is similar
voltages of the basecollector and the baseemitter junctions, to the common-emitter configuration with the output taken
respectively. Therefore, the value of VCE (VCB VBE) is few from the emitter terminal rather than the collector terminal.
tenths of volts in the saturation region. The region to the
left of VCE = VCE(sat) line in the output characteristics is
the saturation region. In the saturation region, the value of
the collector current is independent of the base current and IE
VEE
depends on the value of resistor connected between the collec- E
tor terminal and the supply terminal. For the common-emit-
B
ter circuit of Fig. 10.9, the value of collector current in the
saturation region is given by VCC/RL. The minimum base IB
current required to saturate the transistor is given by IC/hFE. C RL
Ri
A parameter which is of importance in the satura-
tion region is the common-emitter saturation resistance VBB IC
(RCE(sat)), which is defined as the ratio of the collec-
toremitter voltage at saturation to the collector cur-
rent (VCE(sat)/IC). The curves to the left of the VCE =
VCE(sat) line can be approximated as straight lines whose
slope can be determined using the value of RCE(sat). (a)
IE
VEE
E
VBB IC
(a) 10.3 TRANSISTOR CONFIGURATIONS 209
10.3.3.2Output Characteristics
IE Output characteristics of the common-collector configu-
VEE ration relate the emitter current (IE) to the emitter
E collector voltage (VEC) for different values of base current
B (IB). Figure 10.15 shows the output characteristics for
an NPN transistor in common-collector configuration.
IB RL The characteristics are similar to that for the common-
C emitter configuration.
Ri
IE (mA)
VBB
IC IB = 100 A
-10
IB = 80 A
-8
(b)
IB = 60 A
-6
Figure 10.13| Common-collector configuration for the
(a) NPN transistor. and (b) PNP IB = 40 A
transistor. -4
IB = 20 A
Common-collector configuration offers high input imped- -2
ance and low output impedance and hence it is used IB = 0 A
for impedance-matching applications, that is, for driving VEC (V)
low-impedance load from a high-impedance source. The 0 -5 -10 -15 -20
voltage gain offered by the common-collector configura- VEC(sat)
Figure 10.15| Output characteristics of the common-

tion is less than unity, and the value of current gain is
high. collector configuration.
10.3.3.1Input Characteristics Gamma (g)

Gamma (g) is the current gain in the common-collector
The input characteristics of common-collector configu- configuration. For any transistor, the emitter, collector
ration relate the base current (IB) to the basecollector and base currents are related to each other by the
voltage (VBC) for different values of the emitter following expression:
collector voltage (VEC). The input characteristics
for a common-collector NPN transistor are shown in I E = IC + I B (10.13)

Fig. 10.14.
Relationship between collector and emitter current is
also given by
IB (A)
IC = ICO + aI E (10.14)
100
VEC = -2 V VEC = -4 V
Combining Eqs. (10.13) and (10.14), we get
80 IB I
IE = + CO (10.15)
(1 a ) (1 a )

60
1
If g = (b + 1) =
40 (1 a )
20 then Eq. (10.15) becomes
IC = g IB + g ICO (10.16)
VBC (V)
0 -1 -2 -3 -4
Table 10.1 gives a qualitative comparison of the three
Figure 10.14| Input characteristics of the common- configurations in terms of current and voltage gains,
collector configuration. input and output impedances.

Table 10.1| Salient features of the three-transistor configurations.

Configuration Current Gain Voltage Gain Input Impedance Output Impedance
Common emitter (CE) High (50100) Very high (500) Medium (800 ) Medium (50 k)
Common collector (CC) High (80100) Appox. Unity High (800 k) Very low (50 )
Common base (CB) Appox. unity High (150) Low (100 ) Very high (500 k)
10.4 EBERSMOLL MODEL OF current flowing through the diodes. They quantify the
TRANSISTORS transport of minority carriers through the base region,
that is, they account for the minority-carrier transport
across the base.
EbersMoll transistor model was developed by Ebers and
B
Moll in the year 1954. It is also known as the coupled
diode model. It is an ideal model for a bipolar transistor
and is applicable for all four regions of transistor opera- aRIR IB aFIF
tion. The model involves two ideal diodes and two ideal
current sources. Figures 10.16(a) and (b) show the IE
EbersMoll model for the NPN and the PNP transistors, E C
IC
respectively.
To understand the model, let us consider the general-
ized current equation of a transistor given in Eq. (10.3). IF = IES [exp (VEB/VT) - 1] IR = ICS [exp (VCB/VT) - 1]
It is repeated here for the convenience of the readers.
(a)
V
IC = ICO 1 exp CB + aI E (10.17)
VT B

The above equation can be rewritten for the active
region as aRIR IB aFIF
V
IC = ICS 1 exp CB + a F I E (10.18) IE
VT E
IC
C

where aF is the common-base current gain in the normal
operating mode (baseemitter junction forward biased
IF = IES [exp (-VEB/VT) - 1] IR = ICS [exp(-VCB/VT) - 1]
and basecollector junction reverse biased) and ICS is the
saturation current of the basecollector diode. (b)
For the reverse-active region, Eq. (10.17) can be Figure 10.16| EbersMoll model for(a) NPN transistor
rewritten as and (b) PNP transistor.
V
I E = I ES 1 exp EB + a R IC (10.19) From Fig. 10.16, the equations for the collector, emitter
VT
and base currents in the EbersMoll model are given by
where aR is the common-base current gain in the inverting IC = IR + a F I F
(10.20)
operating mode (baseemitter junction reverse biased
and the basecollector junction forward biased) and IES I E = I F a R IR (10.21)

is the saturation current of the baseemitter diode.
IB = (1 a R )IR + (1 a F )I F (10.22)
The two diodes shown in Fig. 10.16 represent the
baseemitter and the basecollector diodes and are The EbersMoll parameters are related by the following
connected back to back. The reverse saturation currents expression:
I ESa F = ICSa R
through the baseemitter and the basecollector diodes
(10.23)
are IES and ICS, respectively. Two current sources are in
shunt with the diodes and their values depend upon the This expression is referred to as the reciprocity relation.

10.6 JUNCTION FIELD-EFFECT TRANSISTORS 211
In the discussion above, we have not taken into consid- terminals. JFETs comprise of a semiconductor channel
eration the base-spreading resistance (rbb) of a transistor. embedded into semiconductor layers of opposite polarity.
It is the resistance offered by the base region to the flow of Depending upon whether the semiconductor channel is an
current through it. Typical value of rbb is in the range of N-type semiconductor or a P-type semiconductor, JFETs
100 , and it increases with the increase in the reverse-bias are classified as N-channel or P-channel JFETs, respectively.
collectorbase voltage. Its value also depends on the doping
level of the base region. The effects of rbb are important 10.6.1 Construction and Principle of Operation
at high frequencies. It may be mentioned here that it is
impossible to construct a transistor by simply connecting Figures 10.17(a) and (b) show the cross-sectional view of
two diodes back to back in series. A cascade arrangement N-channel and P-channel JFETs, respectively. As we can
of two diodes exhibit transistor properties only if the carriers see from the figures, in an N-channel JFET, an N-type
injected by one junction diffuse to the second junction. semiconductor material forms a channel between embedded
layers of P-type material, whereas in a P-channel JFET, a
10.5 BIPOLAR JUNCTION TRANSISTORS P-type semiconductor forms a channel between the embed-
VERSUS FIELD-EFFECT TRANSISTORS ded layers of N-type material. Therefore, two PN junctions
are formed between the semiconductor channel and the
embedded semiconductor layers. Ohmic contacts are made
Both bipolar junction transistors (BJTs) and field-effect at the top and bottom of the channel and are referred to
transistors (FETs) are semiconductor devices. The as the drain (D) and the source (S) terminals, respectively.
major difference between the two devices is that BJTs Drain (D)
are current-controlled devices whereas FETs are voltage-
controlled devices. In a BJT, the collector current (IC)
is a direct function of the base current (IB), whereas in
a FET, the drain current (ID) depends upon the gate
source voltage (VGS). In other words, in a BJT the output
current is controlled by the input current whereas in a
FET it is controlled by the input voltage. P N P
Another important difference between the two devices Gate (G)
is that BJTs are bipolar devices whereas FETs are unipolar
devices. In other words, in a BJT both electrons and Depletion N-channel
holes contribute to the flow of current whereas in a FET region
either holes or electrons contribute to the current. In an
N-channel FET, electrons are the current carriers, whereas
in a P-channel FET, holes are the current carriers. Source (S)
The input impedance of FET devices is very high (a)
(of the order of several hundred megaohms) as compared
to that of BJT transistor configurations (varying from Drain (D)
hundred ohms to less than 1 megaohm). Input impedance
is a very important characteristic parameter in the design
of linear AC amplifiers. In addition, FET devices in general
are more temperature stable and smaller in construction as
compared to BJTs. Because of their smaller size, FETs are
extensively used in the fabrication of integrated circuits.
However, the gain of a FET-based amplifier is smaller as N P N
compared to a BJT amplifier, that is, FET amplifiers have Gate (G)
poorer sensitivity to changes in the input signal. Also,
FETs are more sensitive to handling than BJTs. Depletion P-channel
region
10.6 JUNCTION FIELD-EFFECT
TRANSISTORS
Source (S)
Junction field-effect transistor (JFET) is the simplest of the (b)

FETs. It is a three-terminal device where the voltage applied Figure 10.17| Cross-section of an (a) N-channel JFET
at one terminal controls the current through the other two and (b) P-channel JFET.

The channel behaves as a resistive element between its

drain and source terminals. In an N-channel JFET, both the
embedded P-type layers are connected together and form the
gate (G) terminal. Similarly in a P-channel JFET, the gate +
terminal is formed by connecting the two N-type embedded VDS
+ VDD
layers. Figures 10.18(a) and (b) show the circuit symbols for
the N-channel JFET and P-channel JFET, respectively. - -
VGS = 0
In the absence of any externally applied potential,
both the PN junctions are open circuit and a small
depletion region is formed at each of the junctions as
shown in Fig. 10.17. The externally applied potential
between the gate and the source terminals controls the
flow of drain current for a given potential between the (a)
drain and source terminals. The operation of JFET
devices is explained in the subsequent paragraphs.
ID
D D D
Depletion
region
G G e
G VDD
+ P N P
S S e
(a) (b) VGS = 0

Figure 10.18| Circuit symbol of a (a) N-channel JFET e e
and (b) P-channel JFET.
S
10.6.2 Characteristic Curves -
In this section, the principle of operation of an N-channel

JFET is explained. The operation of a P-channel JFET
is similar to that of an N-channel JFET with the polari- (b)
ties of voltages and direction of currents reversed. Let Figure 10.19|(a) Circuit of N-channel JFET with VGS = 0
us consider the situation when a positive drainsource and positive value of VDS. (b) Flow of
voltage (VDS) is applied to the JFET with gate terminal electrons and holes for N-channel JFET
shorted to the source terminal (VGS = 0). with VGS = 0 and positive value of VDS.
Figure 10.19(a) shows the circuit connection. When ID (mA)
the drainsource voltage is applied, the electrons in the
N-channel are attracted to the drain terminal establishing 6
the flow of drain current (ID) as shown in Fig. 10.19(b). IDSS
5 VGS = 0
The value of the drain current (ID) is determined by the Saturation region
value of the applied drainsource voltage (VDS) and the
resistance of the N-channel between the drain and the 4
source terminals. Because of the flow of drain current
3
(ID), there is a uniform voltage drop across the channel
resistance which reverse biases the two PN junctions.
2
This results in an increase in the width of the depletion
region. It may be mentioned here that the depletion region 1
is wider near the drain region than the source region. This
is because the drain current and the channel resistance VDS (V)
establish more reverse-bias voltage at the PN junction 0 VP 5 10 15 20 25
Figure 10.20| ID versus VDS for VGS = 0.
near the drain region than near the source region.

10.6 JUNCTION FIELD-EFFECT TRANSISTORS 213
The drain current (ID) increases linearly with increase in Figure 10.22 shows the circuit connection when both
the drainsource voltage (VDS) till the drainsource volt- drain and gate voltages are applied to the JFET. When
age reaches a value where the saturation effect sets in. a negative bias is applied to the gate terminal, there is an
This is evident from Fig. 10.20, which shows the relation- increase in the width of the depletion region. Therefore,
ship between the drain current (ID) and the drainsource the pinch-off phenomenon occurs at lower values of
voltage (VDS) for zero gatesource voltage (VGS = 0). The drainsource voltage (VDS). Also, the value of satura-
value of VDS where the saturation effect sets in is referred tion drain current decreases further. As the value of VGS
to as the pinch-off voltage (VP). When the drainsource becomes more negative the value of saturation current
voltage reaches the pinch-off voltage, the drain current decreases. The drain current becomes zero for gate
(ID) does not change with further increase in the value of source voltage equal to VP. This voltage is referred
drainsource voltage. This condition is referred to as the to as the gatesource cut-off voltage or the gatesource
pinch-off condition. This happens because the width of pinch-off voltage (VGS(off)).
the depletion regions of the PN junctions has increased In fact, the value of drainsource pinch-off voltages
significantly near the drain region resulting in the reduc- decrease in a parabolic manner with the gatesource
tion of the channel width (Fig. 10.21). Therefore, the voltage becoming more negative. Figure 10.23 shows
drain current essentially remains constant for VDS > VP. the output characteristic curves for the N-channel JFET.
This current is referred to as the drain-to-source cur- The region to the left of the locus of pinch-off voltages is the
rent for short-circuit connection between gate and source ohmic region or the voltage-controlled resistance region.
(IDSS). In nutshell, for drainsource voltage greater than Region to the right of the locus of the pinch-off voltages
the pinch-off voltage (VDS > VP), JFET has the charac- is the saturation region or the constant-current region. In
teristics of a constant current source. the ohmic region, JFET acts as a variable resistor whose
resistance is controlled by the applied gatesource voltage.
Pinch-off
D ID = IDSS
Depletion
region +
+ VDS VDD
VGS - -
VGG
+
G VDD VP
P N P
VGS = 0 Figure 10.22| N-channel JFET biasing circuit.
ID (mA)
S Ohmic
- 6 region Saturation region VGS = 0
IDSS
5
Breakdown
Figure 10.21| N-channel JFET with VGS = 0 and
Locus of pinch-off
4 region
VDS > VP. voltages
VGS = -1 V
3
The gatesource voltage (VGS) is the control voltage for
JFETs in the same way as the base current (IB) is for 2 VGS = -2 V
BJTs. The characteristic curves for a JFET are plot-
ted between the drain current (ID) and the drainsource 1 VGS = -3 V
voltage (VDS) for different values of gatesource voltage VGS = -4 V
(VGS). In case of an N-channel JFET, the voltage VGS is VDS (V)
0 VP 5 10 15 20 25
negative, that is, the gate terminal is made more nega-
tive than the source terminal. Voltage VGS is positive for Figure 10.23| Output characteristic curves of an
P-channel JFETs. N-channel JFET.

The drain resistance (rd) in the saturation region is given Figure 10.25 shows the output characteristic curves for
by the following expression: P-channel JFETs.
ro
rd = (10.24) ID (mA)
(1 VGS VP )2
VGS = 0
where ro is the resistance at VGS = 0, rd is the resistance -6
at a particular value of VGS, and VP is the pinch-off -5
voltage. VGS = +1 V
The relationship between the output current ID in the -4
saturation region for a given value of input gatesource
voltage (VGS) is given by -3 VGS = +2 V
V
2
-2
ID = IDSS 1 GS (10.25)
VP VGS = +3 V
-1
where IDSS is the drain current for short-circuit connec- VGS = +4 V VGS = +5 V
tion between gate and source. VDS (V)
0 -5 -10 -15 -20 -25
This expression is referred to as the Shockleys equa-
tion. As is clear from the equation, there is a non-linear Figure 10.25| Characteristic curve of P-channel JFET.
square law relationship between the output drain cur-
rent (ID) and the input gatesource voltage (VGS) as
opposed to a linear relation between the output collector 10.6.3 Effect of Temperature on JFET
current (IC) and the input base current (IB) in case of Parameters
BJTs. Because of the square law characteristics, JFETs
are very useful devices in radio tuners and TV receivers. JFETs offer better thermal stability as compared to
BJTs. Increase in JFET temperature results in decrease
The transfer characteristics of a FET device is a plot in the depletion region width and decrease in the carrier
between the drain current (ID) and the gatesource voltage mobility. Decrease in the depletion region results in
(VGS) and can be plotted using Shockleys equation increase in channel width, which in turn increases the
or using the output characteristic curves. Figure 10.24 drain current (ID). This results in positive temperature
shows how we can obtain the transfer characteristics coefficient for drain current (ID). Increase in drain
curve using the output characteristics curve. current with temperature results in increase in gate
As mentioned before, P-channel JFETs behave in source cut-off voltage (VGS(off)) with temperature.
the same manner as the N-channel JFETs with the VGS(off) also has a positive temperature coefficient of
direction of currents and polarities of voltages reversed. the order of 2.2 mV/C.
ID (mA) ID (mA)
Ohmic
6 6 region Saturation region
VGS = 0
IDSS
5 5
Locus of pinch-off
4 4 voltages
VGS = -1 V
3 3
2 2 VGS = -2 V
1 1 VGS = -3 V
VGS = -4 V
VGS (V)
VDS (V)
-4 -3 -2 -1 0 0 5 10 15 20
Figure 10.24| Transfer characteristic curves of N-channel JFET.

10.7 METAL-OXIDE FIELD-EFFECT TRANSISTORS 215
Decrease in carrier mobility gives drain current Source (S) Gate (G) Drain (D)
(ID) a negative temperature coefficient. As both the
mechanisms occur simultaneously, the effect of one Metal
mechanism compensates for the other. Therefore, JFETs contact
offer better temperature stability. It is even possible N+ N N+ SiO2
to bias the JFET so as to establish zero temperature
coefficients.
N+-region
N-channel
10.7 METAL-OXIDE FIELD-EFFECT P-substrate
TRANSISTORS
Metal-oxide field-effect transistors (MOSFETs) are Substrate (SS)

another class of FETs. They are named so because the Figure 10.26| Cross-section of an N-channel depletion
metal gate in a MOSFET is insulated from the semicon- MOSFET.
ductor channel by a very thin oxide layer. MOSFETs are
also referred to as insulated gate field-effect transistors The construction of a P-channel depletion MOSFET
(IGFETs). Like a JFET, a MOSFET is also a three- (Fig. 10.27) is similar to that of an N-channel depletion
terminal device where the drain current is controlled by MOSFET with the difference being that the substrate is
the applied gate voltage. an N-type semiconductor while the channel is a P-type
material. Figures 10.28(a) and (b) show the circuit
MOSFETs are further classified into two types
symbols for N-type and P-type depletion MOSFETs,
depending upon their construction and mode of opera-
respectively.
tion, namely, the depletion MOSFET (or DE-MOSFET)
and the enhancement MOSFET (or E-MOSFET). Source (S ) Gate (G) Drain (D)
Metal
10.7.1 Depletion MOSFETs
contact
In a depletion MOSFET, a channel is physically constructed P+ P P+ SiO2
between the drain and the source terminals. Depletion
MOSFETs are further classified as N-channel depletion P+-region
MOSFETs and P-channel depletion MOSFETs depending
on whether the channel material is an N-type semiconductor P-channel
or a P-type semiconductor. N-substrate
The cross-sectional view of an N-channel d epletion
MOSFET is shown in Fig. 10.26. It comprises of a
substrate made of a P-type semiconductor material.
Two N+ type regions linked by an N-channel are Substrate (SS)
Figure 10.27| Cross-section of a P-channel

formed on the substrate. The source and the drain
terminals are formed by connecting metal contacts to
depletion MOSFET.
the two N+ regions as shown in the figure. The gate
terminal is connected to the insulating silicon diox- D D
ide (SiO 2) layer on top of the N-channel. Therefore,
there is no direct electrical connection between
the gate terminal and the channel of a depletion
MOSFET. (In case of enhancement MOSFETs also,
there is no direct electrical connection between the SS
G G
gate terminal and the channel.) There is a capaci-
tance that exists between the gate and the channel
as the metal gate contact and the channel act as
walls of a parallel plate capacitor and the SiO 2 layer S S
forms the dielectric. Hence, the input impedance of
a depletion MOSFET is very high of the order of (a)
10 10 to 10 15 .
D D
10-Chapter-10-Gate-ECE.indd 215 SS 6/30/2015 11:49:47 AM

G G
S S
(a)
D D Source (S ) Gate (G) Drain (D)
+++++++ +++++++ +++++++

SS +++++++++ +++++++
N+ N N+
G G
S S
P-substrate
(b)
Figure 10.28| Circuit symbol of an (a) N-channel
depletion MOSFET and (b) P-channel
depletion MOSFET. Substrate (SS)
Figure 10.30| N-channel depletion MOSFET.

Let us now see how the N-channel depletion MOSFET
operates. When the gate and the source terminals are For positive values of gatesource voltage, electrons
shorted, that is, the voltage VGS = 0 and a positive (minority carriers) in the P-type substrate are attracted
voltage is applied between the drain and the source into the channel and establish new carriers through
terminals, that is, voltage VDS is positive (Fig. 10.29), the collisions between accelerating particles. Thus, the
there is a flow of current in the N-channel as the drain current increases rapidly with increase in the posi-

electrons are attracted by positive potential at the drain tive value of gatesource voltage. As the application of
terminal. The current increases with increase in VDS positive gatesource voltage increases the value of drain
and after a certain value of VDS it becomes constant. current, the region of positive gatesource voltages is
This current is represented as IDSS and is similar to referred to as the enhancement region. The region for
that established in a JFET with VGS = 0. When the zero and negative values of gatesource voltage is referred
gate terminal is at a negative potential as compared to as the depletion region. It may be mentioned here that
to the source terminal, electrons in the N-channel are Shockleys equation as defined for JFETs is applicable
repelled by this negative potential towards the P-type for the depletion MOSFET also in both the depletion
substrate. Also, the holes in the P-type substrate are and the enhancement regions. Figure 10.31 shows the
attracted towards the gate. This results in recombi- output characteristic curves for an N-channel depletion
nation of holes and electrons and there is reduction MOSFET. The transfer characteristics for depletion
in the number of free electrons in the N-channel (Fig. MOSFET can be plotted in a similar fashion for that of
10.30). The higher the negative potential, the more is a JFET. Figure 10.32 shows the transfer characteristics
the rate of recombination and less the number of free for an N-channel depletion MOSFET.
electrons in the channel. Therefore, the drain current
ID (mA)
(ID) decreases with increase in the value of the negative VGS = +2 V
gatesource potential. 7
6
VGS = +1 V
5
+ IDSS
4 VGS = 0
VDS VDD
+ 3
- - VGS = -1 V
VGS = 0
2
VGS = -2 V
1
VGS = -3 V
VGS = -4 V
VDS (V)
0 5 10 15 20 25
Figure 10.29| Circuit connection of N-channel Figure 10.31| Output characteristic curves of
depletion MOSFET. N-channel depletion MOSFET.

10.7 METAL-OXIDE FIELD-EFFECT TRANSISTORS 217
ID (mA) ID (mA)
VGS = +2 V
7 7
6 6
VGS = +1 V
5 5
IDSS
4 4 VGS = 0
3 3
VGS = -1 V
2 2
VGS = -2 V
1 1
VGS = -3 V
VGS = -4 V
0 VDS (V)
-6 -4 -2 0 +2 VGS (V) 5 10 15 20 25
Figure 10.32| Transfer characteristic curves of N-channel depletion MOSFET.
10.7.2 Enhancement MOSFETs The N-channel enhancement MOSFET functions as

follows. When the gatesource voltage is zero and some
The construction of an enhancement MOSFET is simi- positive drainsource voltage is applied, there is no
lar to that of a depletion MOSFET with the difference drain current as there is no channel available for flow of
that there is no physical channel between the source drain current. Enhancement MOSFETs are also called
and drain terminals in the enhancement MOSFET. The normally off MOSFETs as they do not conduct when
invention of enhancement MOSFETs has revolutionized VGS = 0. The drain current flows only when a positive
the computer industry and they are extensively used in voltage is applied to the gate terminal with respect to
digital electronics and computers. Figures 10.33(a) and the source terminal as this induces a channel by drawing
(b) show the cross-section of N-channel and P-channel the electrons (minority carriers) in the P-type substrate
enhancement MOSFETs, respectively. Figures 10.34(a) to accumulate near the surface of the SiO2 layer.
and (b) show the circuit symbols of the N-channel and
P-channel MOSFETs, respectively. The broken line in
the symbol indicates the absence of a channel.
Source (S) Gate (G) Drain (D) Source (S) Gate (G) Drain (D)
Metal Metal
contact contact
N+ N+ P+ P+
SiO2 SiO2
N+-region P+-region
P-substrate N-substrate
Substrate (SS) Substrate (SS)
(a) (b)
Figure 10.33| Cross-section of (a) an N-channel enhancement MOSFET and (b) P-channel enhancement MOSFET.

D D
VGG
+ ++ + ++ G
S D
ID
SS
G G N+ N+
+ + + + + + + VDD
S S
(a) SS
D D
Figure 10.35| Working of N-channel enhancement

MOSFET.
SS
G G
VGG
+++ +++G
S D

ID
S S
N+ N+
(b)
Figure 10.34| Circuit symbol of (a) an N-channel
VDD
enhancement MOSFET and (b) a
P-channel enhancement MOSFET. P-substrate
SS
Also, holes in the P-substrate are forced to move away
from the edge of the SiO2 layer as shown in Fig. 10.35.
As the SiO2 layer is insulating, it prevents the electrons
from being absorbed at the gate terminal. These Figure 10.36| Pinching phenomenon in enhancement
electrons lead to the flow of current between the drain MOSFETs.
and the source terminals. As the value of gatesource
voltage is increased, more and more electrons accumu- ID (mA)
Locus of VDS(sat)
late leading to an enhanced flow of drain current. The VGS = +8 V
level of gatesource voltage that leads to significant 7
flow of drain current is referred to as threshold voltage
6
and is denoted by VTh. For a fixed gatesource voltage, VGS = +7 V
increasing the level of drainsource voltage leads to 5
initial increase in the drain current, which eventu-
ally saturates due to the reduction in the gatedrain 4 VGS = +6 V
voltage (VGD) with increase in the drainsource
voltage (VDS). Reduction in the gatedrain voltage 3
VGS = +5 V
reduces the attractive forces for the free carriers in
2
the induced channel near the drain region, resulting in VGS = +4 V
the reduction of effective channel width near the drain 1 VGS = +3 V
region. This effect is referred to as the pinching effect.
VGS = +2 V
Pinching effect refers to the reduction in the width
of the channel near the drain region with increase in 0 5 10 15 20 25 VDS (V)
the drainsource voltage (Fig. 10.36). The value of the VGS = VT = +1.5 V
drainsource voltage at which the drain current satu- Figure 10.37| Output characteristic curves for an
rates is called VDS(sat). N-channel enhancement MOSFET.

10.8 FET PARAMETERS AND SPECIFICATIONS 219
Figure 10.37 shows the output characteristic curves for 10.8.1.1Drain Resistance
an N-channel enhancement MOSFET. It can be observed
from the curve that the VDS(sat) voltage increases with Static drain resistance (RD) is defined as the ratio of the
the increase in the applied gatesource voltage. The rela- drainsource voltage (VDS) to the drain current (ID).
tionship between VDS(sat) and VGS is given by the follow-
ing expression: VDS
RD = (10.28)
ID

VDS(sat) = VGS VTh (10.26) Dynamic drain resistance (rd) is defined as the ratio of

where VTh is the threshold gatesource voltage. change in the drainsource voltage to the change in the
drain current at a constant gatesource voltage.
Also, the drain current is zero for gatesource voltage
less than the threshold voltage VTh. For voltages greater VDS
rd =
ID
than the threshold voltage, the drain current is given by (10.29)
VGS = const
the following expression:
The typical values of rd lie in the range of 0.11 M for
ID = k(VGS VTh )2 (k is a constant) (10.27) JFET and 1 to 50 k for MOSFETs.

As is clear from Eq. (10.27), the relationship between
10.8.1.2Transconductance (gm)
the drain current and the gatesource voltage is non-
linear and the current is proportional to the square of
Transconductance (gm) is defined as the ratio of the
the voltage. The relationship is shown in Fig. 10.38. The
change in the drain current to the change in the gate
characteristics of Fig. 10.38 are referred to as the trans-
source voltage for a constant drainsource voltage.
fer characteristics.
ID
gm = (10.30)
ID (mA) VGS
VDS = const
7 The transconductance varies with the applied gate

source voltage (VGS) as given in the following equation:
6
V
gm = gm0 1 GS (10.31)
5
VP
4 where gm0 is the transconductance at zero gatesource
3 voltage.
The value of gm is in the range of 0.110 mA/V for
2 JFETs and between 0.1 mA/V 20 mA/V or more for
1 MOSFETs.
VGS (V) 10.8.1.3Amplification Factor (m)

0 2 4 6 8
Figure 10.38| Transfer characteristics of an N-channel Amplification factor (m) is defined as the ratio of the
enhancement MOSFET. change in the drainsource voltage to the change in the
gatesource voltage for a constant value of drain current.
VDS
10.8 FET PARAMETERS AND m= (10.32)
SPECIFICATIONS VGS I D = const

Substituting the value of rd given in Eq. (10.29) and gm
In this section we describe the characteristic parameters given in Eq. (10.30) in Eq. (10.32), we get
and specifications of FETs. VDS VDS ID
m= = = rd gm (10.33)
VGS ID VGS
10.8.1 Characteristic Parameters
Therefore, the amplification factor is the product of the
Parameters used to define the performance of a FET dynamic drain resistance and the transconductance of
device are static and dynamic drain resistance, transcon- the FET. Amplification factor in a JFET can be as high
ductance (gm) and amplification factor (m). as 100.

10.8.2 Differences between JFETs and An effective method to prevent MOSFET damage is
MOSFETs to connect Zener diodes back to back between the gate
and the source terminals so that the gate-to-source volt-
JFETs and MOSFETs are somewhat similar devices but age never exceeds the specified maximum rating. Figure
there are quite a few differences between the two devices 10.39 shows the use of Zener diodes for protection of
in terms of their principle of operation and the value enhancement MOSFETs. Similar configuration can be
of their characteristic parameters. These differences are used for depletion MOSFETs. But the use of Zener
listed as follows diodes results in reduction of input impedance as the
1. JFETs are operated in depletion mode only. impedance of the Zener diode in the reverse-bias mode is
Depletion MOSFETs can be operated in both less than the input impedance of the MOSFET.
depletion and enhancement modes and enhance-
ment MOSFETs are operated in enhancement D
mode.
2. The input resistance offered by MOSFETs is
much higher than that of JFETs. Input resistance
for JFETs is greater than 109 whereas that of
MOSFETs is around 1013 . G
3. JFETs have higher drain resistance than
MOSFETs and hence their characteristic curve
is more flat than that of MOSFETs. Drain resis-
tance for JFETs is in the range of 100 k1 M
while that for MOSFETs is in the range of
1 k50 k.
4. The leakage gate current in MOSFETs is much S
smaller than that in JFETs. The gate current for Figure 10.39| Use of Zener diodes to protect
MOSFETs is in the range of 100 nA10 pA whereas enhancement MOSFET.
that for JFETs is in the range of 100 mA10 nA.
5. MOSFETs are easier to construct and are used
more widely than JFETs.
10.9 DUAL-GATE MOSFET
10.8.3 Handling MOSFETs
In a dual-gate MOSFET, an additional second insulated
Because of the presence of thin SiO2 layer in MOSFETs, gate is provided as compared to a conventional MOSFET.
they are prone to damage if not handled properly. A The flow of current through the MOSFET is controlled
person accumulates static charge from the surround- by voltages at both the gate terminals. As the control
ings. When that person handles a MOSFET device, that is exerted by two gates, the dual-gate MOSFET may
charge can lead to potential difference across the SiO2 be considered to be the counterpart of a tetrode. Figure
layer which can result in its breakdown and establish 10.40(a) shows the cross-section of an N-channel dual-
conduction through it. Therefore, some precautions need gate depletion MOSFET, and Fig. 10.40(b) shows the
to be taken while handling MOSFETs. circuit symbol. The device acts as if two MOSFETs have
A shorting conducting foil or a shorting ring is been connected in series. The N+ region in the middle
c onnected across all the three leads of the device until acts as a drain for MOSFET 1 and a source for the
the device is inserted into the system. The shorting MOSFET 2. For the depletion MOSFET shown in the
ring prevents the development of potential difference figure, the drain current decreases when the gate voltage
between any two device terminals. The person using the at either of the two gate terminals is made negative.
MOSFET should always touch ground before using the It may be mentioned here that the gate terminal 1
device so as to discharge the accumulated charge before provides higher transconductance as compared to the
handling the device. The person who is soldering should gate terminal 2. Because of simultaneous control of two
use a shorting strap to discharge static electricity and gate voltages, the device is used in applications such
also should make sure that the tip of the soldering iron as AGC amplifier, mixers and demodulators. When it
is grounded. Also, the MOSFET should always be held is used in AGC amplifier, the signal to be amplified is
from the casing. In addition, the MOSFET should be connected to gate 1 and the voltage to control the gain
inserted or removed with the supply off. is applied to gate 2.

10.10 VMOS DEVICES 221
Gate-1 (G1) Gate-2 (G2) 10.10 VMOS DEVICES

Source (S) Drain (D)
SiO2 MOSFETs have smaller power-handling capability as

n+ Drain-1 and compared to BJTs. The power-handling capability of a
Source-1 Drain-2
Source-2 MOSFET can be improved if the construction of the
N+ N+ N+ MOSFET is modified as shown in Fig. 10.42(a) and this
Diffused Diffused is referred to as vertical metal-oxide-silicon (VMOS)
channel-1 channel-2 field effect transistor or as power MOSFET. VMOS
has a vertical structure with the channel formed in the
P-substrate
vertical direction rather than the horizontal direction.
The operation of a VMOS device is similar to that of
(a) an enhancement MOSFET. No channel exists between
drain and source terminals, till the gatesource volt-
D age is made positive. For positive values of gatesource
voltage, an N-channel is formed close to the gate [Fig.
10.42(b)] as in case of an enhancement MOSFET.
G1
G2 Source (S) Gate (G) Source (S )
SiO2
S N+ N+
P P
(b)
Figure 10.40| (a) Internal architecture of N-channel N-

dual-gate depletion MOSFET. (b) Circuit
symbol of N-channel dual-gate depletion N+ substrate
MOSFET.
Figure 10.41 shows the transfer characteristics of a Drain (D)

popular N-channel dual-gate depletion MOSFET. The Both the source terminals are internally connected
drain characteristics are similar to that of a conventional
N-channel depletion MOSFET. (a)
ID (mA) Source (S ) Gate (G) Source (S)
28
VG2S = +4 V
SiO2
24 N+
N+ P
P Channel
20
length
16 VG2S = + 2 V
N-
12 VG2S = + 1 V
N+ substrate
8 VG2S = 0
4
VG2S = -1 V Drain (D)
VG1S (V)
-1.5 -1.0 -0.5 0 +0.5 +1.0 (b)
Figure 10.41| Transfer characteristics of an N-channel Figure 10.42| (a) Structure of a VMOS device.
dual-gate depletion MOSFET. (b) Operation of a VMOS device.

However, the channel is formed in the vertical direction. MOSFET (S2) is connected to voltage VSS (between 5
This lets the current carriers to flow between the source V and 15 V) and the source terminal of the N-channel
and the drain terminals. In the absence of gatesource MOSFET (S1) is connected to ground.
voltage or for negative values of gatesource voltages, no Figure 10.44 shows the simplified diagram of the
channel exists and the drain current is zero. Drain and CMOS inverter architecture shown in Fig. 10.43. The
transfer characteristics are the same as shown in case of circuit operates as follows: When the input voltage
planar enhancement MOSFETs. Vin is at logic LOW, the gatesource voltage (VG2S2)
VMOS devices have smaller channel lengths and larger of the P-channel MOSFET is equal to VSS and the
contact area between the channel and the N+ doped MOSFET is in the ON state, providing a low-resistance
regions as compared to MOSFETs, resulting in reduced path between VSS and the output terminal. The gate
resistance levels and hence reduced power dissipation source voltage (VG1S1) of N-channel MOSFET is 0 V,
levels. Also, there are two conductive paths between and therefore it is OFF, resulting in very high impedance
drain to source which also leads to higher current rating. between the output terminal and ground. Therefore, the
Another advantage of VMOS devices is that they have output voltage Vout is equal to the supply voltage VSS,
positive temperature coefficient which reduces the or in other words, the output voltage is at logic HIGH.
possibility of thermal runaway. Also, VMOS devices
VSS
have faster switching times as compared to that of planar
MOSFETs as they have reduced charge storage levels.
10.11 CMOS DEVICES

Q2
Complementary metal-oxide semiconductor (CMOS) are Vin Vout
those semiconductor devices in which both P-type and
N-type enhancement MOSFETs are diffused on to the
same chip. The CMOS configuration has extensive appli-
cations in computer logic design. CMOS devices offer
high input impedance, lower power consumption and Q1
require far less space as compared to BJT-based logic
circuit. However, they offer slower switching speed as
compared to BJTs. Figure 10.44| Simplified diagram of CMOS inverter.
Figure 10.43 shows the basic inverter circuit using
When the input voltage Vin is at logic HIGH, that is,
CMOS configuration. Inverter is a logic circuit that
equal to the supply voltage VSS, the gatesource voltage
inverts the applied input signal, that is, logic LOW and
(VG2S2) of the P-channel MOSFET is 0 V and therefore
logic HIGH levels applied at the input terminals result
the MOSFET is in OFF state. The gatesource voltage
in logic HIGH and logic LOW levels at the output ter-
(VG1S1) of the N-channel MOSFET is equal to supply
minals, respectively. The complementary N-type and
voltage (VSS) and hence it is switched ON, offering
P-type MOSFETs are connected in series, with their
a low-resistance path. The two MOSFETs form a
gate terminals tied together to form the input terminal.
voltage divider, and the output voltage Vout is approxi-
Also, the drain terminals are connected together to form
mately equal to 0V. Therefore, a logic HIGH at the
the output terminal. Source terminal of the P-channel
VSS G2 Vin G1
S2 Vout S1
D2 D1
Metal
contact
N+ P+ P+ N+ N+ P+ SiO2
P-type well
N-type substrate
Figure 10.43| CMOS inverter.

10.12 INSULATED GATE BIPOLAR TRANSISTORS 223
input results in logic LOW at the output. In either state, Collector

one of the MOSFETs is OFF. This results in very low
power dissipation in the device. Special handling pre-
cautions mentioned for MOSFETs are also applicable to
CMOS devices.
10.12 INSULATED GATE BIPOLAR

TRANSISTORS Gate
Insulated gate bipolar transistors (IGBTs) are three-

terminal power semiconductor devices having positive
attributes of both BJTs and MOSFETs. IGBTs offer
fast switching times similar to that of MOSFETs and Emitter
lower on-state voltages and larger blocking voltages sim- Figure 10.46| Simplified equivalent circuit of an
ilar to that of BJTs. They are used in high-efficiency and N-channel IGBT.
fast-switching applications such as switch mode power
supplies, traction motor control and induction heating.
Figure 10.47 shows the typical output characteristics
Figure 10.45 shows the cross-sectional view of an of an N-channel IGBT device. The output characteristics
N-channel IGBT cell. We can see from the figure that are quite similar to that of an N-channel enhancement
the construction of IGBT is very similar to that of power MOSFET. A noteworthy feature on the IGBT charac-
VMOS devices except that the N+ drain is replaced by teristics is the offset of approximately 0.7 V from the
P+ collector layer, thus forming a vertical PNP transis- origin and the steep slope of the rising portion of the
tor. Figure 10.46 shows the simplified equivalent circuit characteristics. The offset is because the ON-state volt-
for the N-channel IGBT. The equivalent circuit shows age across the IGBT is one diode-drop higher than that
an N-channel power MOSFET driving a wide-base PNP of N-channel enhancement MOSFET. The steep slope in
transistor in a Darlington configuration. the transfer characteristics is attributed to the fact that
current flow in an IGBT is due to the flow of both elec-
Gate (G) trons and holes as compared to an N-channel MOSFET
Emitter where the current flow is due to the flow of electrons
Metal only. This reduces the effective resistance to current
contact flow in the drift region. The resulting reduction in the
N+ N+ ON-state voltage is the main advantage of IGBTs over
SiO2 P-body region power MOSFETs.
N-drift region
N+ buffer layer* IC (mA)
P+ substrate Ohmic
region Active region
VGE4
Collector
* Only in Punch Through (PT) IGBT VGE4 > VGE3 > VGE2 > VGE1
Figure 10.45| Cross-section of N-channel IGBT. VGE3

The ON/OFF state of the device is controlled by the
applied gate voltage with respect to the emitter volt-
age. If the gateemitter voltage is less than the thresh- VGE2
old voltage (VTh) of the MOSFET, no inversion layer
is created and the device is in the OFF state. When VGE1
the gateemitter voltage is above the threshold voltage
(VTh), enough electrons will be drawn towards the gate 0 VCE (V)
to form a conductive channel across the body region,
leading to the flow of current between the collector and Figure 10.47| Output characteristics of an N-channel

the emitter terminals. IGBT.

However, IGBTs offer slow switching speeds, especially (PT) IGBTs and those without the N+ buffer layer are
during turn-off. Turn-off in case of IGBTs is done by called non-punch-through (NPT) IGBTs. Punch-through
reducing the gateemitter voltage below the threshold IGBTs are also referred to as asymmetrical IGBTs and
voltage. The electron flow in the IGBT as in an N-channel non-punch-through IGBTs as symmetrical IGBTs.
MOSFET stops abruptly. However, in an IGBT, holes Another problem associated with IGBTs is the occur-
are left in the drift region and they can only be removed rence of latch-up phenomenon. Latch-up refers to the
by process of recombination or by applying a voltage failure mode where the IGBT can no longer be turned
gradient. This results in a tail current in IGBTs during off by the gate voltage. Like MOSFETs, IGBTs also are
turn-off till all the holes are removed. N+ buffer layer is susceptible to gate insulation damage by the electro-
added in some IGBTs to control the rate of recombina- static discharge of energy through the devices. So similar
tion of holes by absorbing trapped holes during turn-off. precautions must be taken while handling IGBTs as
IGBTs with N+ buffer layer are called punch-through taken in case of MOSFETs.
IMPORTANT FORMULAS
1. For a BJT, emitter current I E = IC + IB , where IC 12. The drain resistance (rd) in the saturation region of
is the collector current and IB is the base current. a JFET is
ro
2. For the common-base configuration in the active rd =
region, collector current IC = aI E + ICO. (1 VGS VP )2
13. The relationship between the output current ID in
3. The generalized expression for the collector current the saturation region for a given value of input
in a transistor in common-base configuration is gatesource voltage (VGS) in a JFET is given by
V
IC = aI E + ICO 1 exp CB Shockleys equation
VT V
2
ID = IDSS 1 GS
(IC ICO ) V P
4. a =
(I E 0) 14. Shockleys equation as defined for JFETs is appli-
cable for the depletion MOSFET also in both the
5. AC alpha (aac) is defined as
depletion and the enhancement regions.
I
a ac = C
I E V = const 15. For an enhancement MOSFET,
VDS(sat) = VGS VTh
CB
6. For common-emitter configuration, collector current

IC = bIB + (b + 1)ICO, where For an enhancement MOSFET, the drain cur-
a rent is zero for gatesource voltage less than the
b=
(1 a ) threshold voltage VTh. For voltages greater than
the threshold voltage, the drain current is given by
7. b is referred to as the DC forward current transfer
ID = k(VGS VTh )2
ratio or the DC current gain of the transistor.
Static drain resistance (RD) is defined as
8. For AC applications ac beta (bac) is defined as V
bac = IC IB for constant common-emitter RD = DS
voltage. ID
16. Dynamic drain resistance (rd) is defined as
I
9. IC = (b + 1)ICO = CO VDS
(1 a ) rd =
ID VGS = const
10. For common-collector configuration
IC = gIB + gICO 17. Transconductance (gm) is defined as
ID V
1 = gm0 1 GS
g = (b + 1) =
gm =
where VGS VP
(1 a ) VDS = const
11. EbersMoll model of transistors is an ideal model 18. Amplification factor (m) is defined as
for a bipolar transistor and is applicable for all four VDS
regions of transistor operation. The model involves m= = rd gm
VGS
two ideal diodes and two ideal current sources. I D = const

SOLVED EXAMPLES 225
SOLVED EXAMPLES
1. For the common-base configuration shown in the collectorbase junction and the depletion region
following figure, the value of collector current (IC) generated current, the base current will
is (a) increase (b) decrease
(given that the value of a is 0.95) (c) remain constant (d) depends on the
(a) 0.9 mA (b) 0.8 mA value of b
(c) 0.947 mA (d) 0.847 mA Solution. As the reverse bias increases at CB
(collectorbase) junction, the collector current (IC)
increases and the effective base width decreases.
Therefore, the recombination in base decreases.
RL This results in decrease in base current.
Ri 4.5 V Ans. (b)
5 k
5. The input and output characteristics for a given
BJT are shown in the following figure parts (a)
6V 6V and (b), respectively. From these characteristics,
the input resistance of the BJT in ohms is
(a) 923 (b) 966
(c) 1167 (d) 1024
Solution. The value of load resistance RL = 5 k IB (A) VCE = 5V
The voltage drop across the resistor is 4.5 V.
Therefore, the current flowing through the resistor = 120
4.5/(5 103) A = 0.9 mA
The current flowing through the resistor is the
collector current. 80 dIB
Therefore, collector current is equal to 0.9 mA.
Ans. (a)
40
2. For the common-base configuration given in
Question 1, the value of the emitter current (IE) is dVBE
0 VBE (V)
(a) 0.967 mA (b) 0.867 mA 0.2 0.4 0.6 0.8 1.0
(c) 0.947 mA (d) 0.897 mA (a)
Solution. The emitter current is IC (mA)
Ic 0.9 103 10 VCE = 5V IB = 140 A
= A = 0.947 mA
a 0.95
Ans. (c) IB = 120 A
8
IB = 100 A
3. For the common-base configuration given in
Question 1, the value of base current (IB) is
IB = 80 A
6
(a) 47 mA (b) 67 mA
(c) 50 mA (d) 20 mA dIC dIC
4 IB = 60 A
Solution. The base current
IB = IE IC = (0.947 103) (0.9 103) = 47 mA dVCE IB = 40 A
IB = 20 A
Ans. (a) 2
4. In a transistor having finite b, forward bias across
IB = 0
the baseemitter junction is kept constant and 0 VCE (V)
the reverse bias across the collectorbase junction 2 4 6 8 10
is increased. Neglecting the leakage across the (b)

d VCE = 6.6 V, d IC = 1.2 mA
Solution. Using the linear portion of the input d VCE
= W = 5.5 k
6.6
Rout =
d IC 1.2 103
characteristic, for a change in VBE of 85 mV, the
corresponding change of IB is 88 mA.
Therefore, Ans. (c)
7. Using the data given in Question 5, the large signal
dV 85 103 current gain with VCE = 5 V is
Rin = BE = = 966
d IB 88 106 (a) 56 (b) 57
Ans. (b) (c) 58 (d) 59
6. Using the data given in Question 5, the output Solution. A vertical line at VCE = 5 V intersects
resistance in kilo-ohms at a base current of 80 mA is the graphs for IB = 140 mA and IB = 20 mA at
(a) 4.5 (b) 5.0 IC = 8.3 mA and IC = 1.2 mA, respectively.
(c) 5.5 (d) 6.0 Thus, dIC = (8.3 1.2) mA = 7.1 mA and dIB =
(140 20) mA = 120 mA. The large signal current gain
Solution. From the output characteristics for is given by
IB = 80 mA, a change of VCE from 8 to 1.4 V
results in a corresponding change in IC from 5.2 d IC 7.1 103
hFE = = = 59
to 4 mA. d IB 120 106
Ans. (d)
d VCE = 6.6 V, d IC = 1.2 mA
d VCE
= W = 5.5 k
6.6
Rout =
d IC 1.2 103
1. For the circuit shown in the following figure, find Applying Kirchoffs voltage law to the output
the value of the emitter current (IE) in milliam- section, we get 8 2 103 2.15 103 VCE = 0
peres. (Given that b = 50, VBE = 0.7 V and ICO = VCE = 8 2 103 2.15 103 = 8 4.3 = 3.7 V
0 mA)
VCE = VCB VBE
Therefore,
V2
VCB = VCE + VBE = 3.7 + 0.7 = 4.4 V
8V
For the NPN transistor, positive value of VCB rep-
R1 R2 resents a reverse-biased collectorbase junction and
100 k 2 k hence the assumption that the transistor is in the
active region is correct.
V1
5V IE = IC + IB = 2.15 103 + 43 106 = 2.193 mA
Ans. (2.193)
2. For the circuit given in Question 1, find the value
Solution. The polarity of the voltage V1 applied of collector current (IC) in milliampere.
to the input section forward biases the emitter
base junction. Therefore, the transistor is in active Solution. From the solution of Question1,
region or in the saturation region. Let us assume IC = 2.15 mA
that the transistor is in the active region. Ans. (2.15)
Applying Kirchoffs voltage law to the input sec- 3. For the circuit given in Question 1, find the value
tion, we get 5 100 103 IB VBE = 0 of base current (IB) in mA.
Substituting VBE = 0.7 V, we get IB = (5 0.7)/100 Solution. From the solution of Question 1, IB =
103 A = 43 mA Also, IC = bIB (as ICO 0).
Therefore, IC = 50 43 106 A = 2.15 mA
0.043 mA
Ans. (0.043)

PRACTICE EXERCISE
1. In an N-channel JFET, VGS is held constant. VDS 7. In MOSFET devices, the N-channel type is better
is less than the breakdown voltage. As VDS is than the P-channel type in the following respect:
increased
(a) It has better noise immunity
(a) conducting cross-sectional area of the channel (b) It is faster
(S) and the channel current density (J) both (c) It is TTL compatible
increase (d) It has better drive capability
(b) S decreases and J decreases (1 Mark)
(c) S decreases and J increases 8. For large values of VDS , a FET behaves as a
(d) S increases and J decreases
(2 Marks) (a) voltage-controlled resistor
(b) current-controlled current source
2. In integrated circuits, NPN construction is pre-
(c) voltage-controlled current source
ferred to PNP construction because
(d) current-controlled resistor
(a) NPN construction is cheaper (1 Mark)
(b) to reduce diffusion constant, N-type collector 9. In a MOSFET, the polarity of the inversion layer
is preferred is the same as that of the
(c) NPN construction permits higher packing of
elements (a) majority carriers in the drain
(d) P-type base is preferred (b) minority carries in the drain
(1 Mark) (c) majority carries in the substrate
(d) majority carries in the source
3. Pinch-off voltage for a FET is the drain voltage at (1 Mark)
which
10. The threshold voltage of an N-channel MOSFET
(a) significant drain current starts flowing can be increased by
(b) drain current becomes zero
(c) all free charges get removed from the channel (a) increasing the channel dopant concentration
(d) avalanche breakdown takes place (b) reducing the channel dopant concentration
(1 Mark) (c) reducing the GATE oxide thickness
(d) reducing the channel length
4. Compared to BJT, a JFET has (2 Marks)
(a) lower input impedance 11. The transit time of the current carriers through the
(b) higher voltage gain channel of a JFET decides its characteristics.
(c) higher input impedance and high voltage gain
(d) higher input impedance and low voltage gain (a) source (b) drain
(1 Mark) (c) gate (d) source and drain
(1 Mark)
5. JFET is a
12. The breakdown voltage of a transistor with its
(a) current-controlled device with high input base open is BVCEO and that with emitter open is
resistance BVCBO, then
(b) voltage-controlled device with high input
(a) BVCEO = BVCBO
impedance
(b) BVCEO > BVCBO
(c) current-controlled current source
(c) BVCEO < BVCBO
(d) voltage-controlled voltage source
(d) BVCEO is not related to BVCBO
(1 Mark)
(1 Mark)
6. In a CE transistor amplifier with voltage gain A,
13. A BJT is said to be operating in the saturation
the capacitance Cbc is amplified by
region if
(a) A (b) (1 + A)
(a) both the junctions are reverse biased
(c) (1 + A) (d) A2 (b) baseemitter junction is reverse biased and
(1 Mark) base collector junction is forward biased

(c) baseemitter junction is forward biased and (c) Can be either N-channel or P-channel JFET
basecollector junction reverse biased (d) Cannot be determined
(d) both the junctions are forward biased (1 Mark)
(1 Mark)
19. For the JFET device and data given in Question 18,
14. The EbersMoll model is applicable to the drain resistance is
(a) bipolar junction transistors (a) 20 k (b) 10 k (c) 25 k (d) 50 k
(b) NMOS transistors (2 Marks)
(c) unipolar junction transistors
(d) junction field-effect transistors 20. For the JFET device and data given in Question 18,
(1 Mark) the transconductance is
15. The early-effect in a BJT is caused by (a) 1 mA/V (b) 3 mA/V

(c) 5 mA/V (d) 2 mA/V
(a) fast turn-on
(2 Marks)
(b) fast turn-off
(c) large collectorbase reverse bias 21. For the JFET device and data given in Question 18,
(d) large emitterbase forward bias the amplification factor is
(1 Mark)
(a) 50 (b) 125 (c) 75 (d) 20
16. If a transistor is operating with both of its junc- (1 Mark)
tions forward biased, but with the collectorbase
forward bias greater than the emitterbase forward 22. The expression for the transconductance (gm) of a
bias, then it is operating in the JFET is
V
(a) forward active mode (a) gm = gm 0 1 GS
(b) reverse saturation mode VP
V
(c) reverse active mode 2
(d) forward saturation anode (b) gm = gm 0 1 GS
(1 Mark) VP
17. In a bipolar transistor at room temperature, if the V

(c) gm = gm 0 1 GS
emitter current is doubled, the voltage across its
VP
baseemitter junction (Given that h = 1)
(d) None of these
(a) doubles (2 Marks)
(b) halves
(c) increases by about 20 mV 23. MOSFET can be used as a
(d) decreases by about 20 mV (a) current-controlled capacitor
(2 Marks) (b) voltage-controlled capacitor
18. A given JFET device has a drain current of (c) current-controlled inductor
8 mA when a drain voltage of 5 V is applied to (d) voltage-controlled inductor
it with gatesource terminals shorted. When the (1 Mark)
drain voltage is increased to 10 V, there is a small
24. The effective channel length of a MOSFET in satu-
increase in the drain current and the new value
ration decreases with increase in
of drain current is 8.2 mA. When the gatesource
voltage is made 0.4 V, the drain current decreases (a) gate voltage (b) drain voltage
to 7 mA. The type of JFET is (c) source voltage (d) body voltage
(2 Marks)
(a) N-channel JFET
(b) P-channel JFET
1. The pinch off voltage for a N-channel JFET is 4 V, 2. An N-channel JFET has IDSS = 2 mA and VP = 4 V.
when VGS = 1 V. Find the pinch-off that occurs for Find its transconductance gm (in mA/V) for an
VDS (in V). applied gate-to-source voltage VGS of 2 V.
(1 Mark) (2 Marks)

3. The output characteristics for a FET are shown in VDS = 15 V

the adjoining figure. Given that VDS = 15 V and ID (mA)
VGS = 0.4 V, find the value of rDS in kilo-ohms.
VGS = 0
(2 Marks) 4
4. For the output characteristics for FET given in VGS = -0.2 V

Question 3, find the value of gm in mS.
3 dID dID
(1 Mark) VGS = -0.4 V
5. The pinch-off voltage of a JFET is 5.0 V. Find its
cut-off voltage in volts. dVDS
2 VGS = -0.6 V
(1 Mark)
6. For a transistor, the value of a is specified to be VGS = -0.8 V
0.98 at a particular collectorbase voltage. The 1
value of a increases by 0.5% when the collector VGS = -1.0 V
base voltage is increased. Find the corresponding
percentage change in the value of b.
0 VDS (V)
(2 Marks) 5 10 15 20
1. (c) When VGS is held constant and VDS is increased, 8. (c) For large values of VDS, the drain current
then the depletion width increases. Therefore, the depends upon the value of VGS. Hence, the FET
cross-sectional area of the channel (S) decreases. behaves as a voltage controlled current source.
As current density 9. (d) In a MOSFET, the polarity of the inversion
I layer is the same as that of the majority carriers in
J=
Area of channel(S ) the source.
Therefore, when the cross-sectional area of channel 10. (b) For the N-channel MOSFET, threshold voltage
decreases, the current density J increases. is given by
2. (b) VTh = VTho + g | 1 2f F + VSB | | 2f F |
3. (c)
where, VTho is the threshold voltage for source
shorted to body (VSB = 0), g is the body affect
4. (d)
5. (b) 2qN Axs
g is the body affect parameter = and fF is the substrate
6. (b) Cox
7. (b) Mobility of electrons is higher than the mobil- Fermi potential.
ity of holes, that is, mn > mp Therefore, the threshold voltage of an N-channel
In N-channel MOSFET, the charge carriers are MOSFET can be increased by reducing the chan-
electrons whereas in P-channel MOSFET, the nel dopant concentration of N-type impurities or
charge carriers are holes. by increasing the concentration of acceptor P-type
impactives in the channel region.
Therefore, N-channel MOSFET is faster than the
P-channel MOSFET. 11. (b)

12. (c) The relationship between open base breakdown 19. (c) Drain resistance
voltage (BVCEO) of BJT with open emitter break- VDS
down voltage (BVCBO) is given by rd =
ID VGS = const
1 Therefore,
BVCEO = BVCBO
b
10 5 5
Therefore, BVCEO < BVCBO rd = = = 25 k
8.2 103
8.0 10 3
0.2 10 3
13. (d) In saturation region, both collectorbase junc-
20. (b) Transconductance
tion and emitterbase junction are forward biased.
ID
14. (a) EbersMoll model is a composite model and is gm =
used to predict the operation of BJT in all of its VGS VDS = const
possible modes. Therefore,
15. (c) The process where the effective base width of 7 103 8.2 103 1.2 103
gm = =
the transistor is altered by varying the collector 0. 4 0 0. 4
base junction voltage is called base width modula- = 3 mA/V
tion or early effect.
16. (b) In a transistor when both the junction (Jc andJE) 21. (c) Amplification factor
m = rd gm = 25 103 3 103 = 75
are forward bias and if collectorbase junction volt-
age is greater than emitterbase junction voltage,
then this transistor is in reverse saturation region.
22. (a) The equation for the drain current (ID) in a
17. (c) Emitter current is given by JFET is
I E = I 0 (eVBE /hVT 1) V
2
ID = IDSS 1 GS
Let the emitter current at base-emitter voltage VP
VBE1 be IE1 and at base-emitter voltage VBE2 be IE2. Differentiating both the sides of the equation w.r.t.
Given that IE1 = 2IE1. Therefore, the gatesource voltage (VGS), we get
I (eVBE2 /hVT 1) dID V 1
= 2IDSS 1 GS
2I E1
= 0 V /hV
I E1 I 0 (e BE1 T 1) dVGS VP VP
Therefore, dID
(eVBE2 /hVT 1)
As gm =
2 dVGS
(eVBE1 /hVT 1)
= Therefore,
1
VGS 1
gm = 2IDSS 1
As eVBE2 /hVT 1 >> 1 VP VP
and eVBE1 /hVT 1 >> 1 Let gm0 be the transconductance for VGS = 0.
VBE2 /hV T Therefore,
Therefore, 2 2 =eVeBE2 /hVT 1
VBE1 /hV T
gm 0 = 2IDSS
=
1 1 eVeBE1 /hVT
(V V BE1 )/hV T VP
V )/hV T
(V BE2
or e eBE2 BE1 ==2 2 Substituting the value of gm0 in the expression for
VBE2 VBE1 gm, we get
or = ln 2
hV T V
gm = gm0 1 GS
Substituting, h = 1 and VT = 0.026 V, we get VP
23. (b)
VBE2 VBE1 = 1 0.026 0.693 20 mV
24. (b) At the edge of saturation, that is, when drain-
Hence, the base-emitter voltage increases by 20 mV to-source voltage reaches VDS(sat), the inversion
18. (a) As application of negative gatesource voltage layer charge at the drain end becomes zero (ide-
results in a decrease of the drain current, the JFET ally). The channel is said to be pinched off at the
is an N-channel JFET. drain end.

If the drain-to-source voltage VDS is increased becomes pinched off and the effective channel length
even further beyond the saturation edge so that is reduced.
VDS > VDS(sat), an even larger portion of the channel
1. Given that VP = 4 V and VGS = 1 V 4. For VDS = 15 V and dVGS = 0 (1) = 1 V, the
corresponding change in drain current dID = (4.4
Now, |VDS| = |VP| |VGS| = 4 1 = 3 V
0.6) mA = 3.8 mA
Ans. (3)
d ID
2. We have gm = = 3.8 103 = 3.8 mS
2IDSS VGS d VGS
1 V
gm = Ans. (3.8)
| VP | P 5. Pinch-off voltage = Cut-off voltage
Therefore,
Therefore, cut-off voltage = 5.0 V
2 2 103 (2) Ans. (5)
gm = 1 = 0.5 mA/V
| 4 | (4) 6. Original value of a = 0.98
Ans. (0.5)
Value of b for a = 0.98 is b = a/(1 a) = 0.98/
3. With VGS = 0.4V and dVDS = (20 10) = 10 V, (1 0.98) = 49
the corresponding change in drain current dID =
New value of a = 0.98 + 0.5 0.98/100 = 0.985
(2.7 2.55) mA = 0.15 mA
Value of b for a = 0.985 is b = 0.985/(1 0.985) = 66
d VDS 10
rDS = = = 66.7 k Percentage change in b =
[(66 49)/49] 100%
d ID 0.15 103
= 34.69%
Ans. (66.7)
Ans. (34.69)
1. For an N-channel enhancement-type MOSFET, if The reverse-bias voltage will result in widening of
the source is connected at a higher potential than the depletion region which in turn leads to reduc-
that of the bulk (i.e. VSB > 0), the threshold volt- tion in channel depth as shown in the figure above.
age VTh of the MOSFET will To return the channel to its former state, the gate-
source voltage (VGS) has to be increased. Hence,
(a) remain unchanged (b) decrease
increase in VSB, results in increase in threshold
(c) change polarity (d) increase
voltage VTh.
Solution. Consider the following figure. As the 2. When the gate-to-source voltage (VGS) of a
MOSFET is an N-channel enhancement type MOSFET with threshold voltage of 400 mV, working
MOSFET, the source being at higher potential in saturation is 900 mV, the drain current is
than the substrate, implies that there is reverse observed to be 1 mA. Neglecting the channel width
bias potential between the source and the body modulation effect and assuming that the MOSFET
(VSB > 0V). is operating at saturation, the drain current for an
Substrate applied VGS of 1400 mV is
(a) 0.5 mA (b) 2.0 mA
D
N+ (c) 3.5 mA (d) 4.0 mA
G
P
Solution. For a MOSFET, the drain current (ID),
gate-source voltage (VGS) and threshold voltage
S
N+ (VTh) are related as
Depletion
Induced VSB region
N channel ID = K(VGS VTh )2

Hence, 1 103 = K(0.9 0.4)2

Solution. We have
IC a
b= =
1a
Therefore,
IB
1 10 3 1
K= A/V2 = mA/mV2 When base width increases, recombination in base
0.25 25 104 region increases and a decreases, hence b decreases.
If doping in base region increases, then recombi-
nation in base increases and a decreases, thereby
When VGS = 1400 mV, then
1 decreasing b. Hence, statement S1 is TRUE and

ID = (1400 400)2 = 4 mA statement S2 is FALSE.
25 10 4
Ans. (d)
Ans. (d)
5. Given figure is the voltage transfer characteristic of
3. If for a silicon NPN transistor, the base-to-emitter
voltage (VBE) is 0.7 V and the collector-to-base Vout
voltage (VCB) is 0.2 V, then the transistor is oper-
ating in the
(a) normal active mode (b) saturation mode
(c) inverse active mode (d) cut-off mode
Vin
(GATE 2004: 1 Mark) 0
(a) a n NMOS inverter with enhancement mode
Solution. Given that the BJT is a Si NPN transistor as load
transistor. As base-emitter voltage is 0.7V, the base- (b) an NMOS inverter with depletion mode transis-
emitter junction is forward biased. As the collector- tor as load
base voltage is 0.2V, the basecollector junction (c) a CMOS inverter
is reverse biased as shown in the following figure. (d) a BJT inverter
Therefore, the give NPN transistor is operating in (GATE 2004: 1 Mark)
normal active mode.
Solution. The given figure shows voltage transfer
+ characteristics of a CMOS invertor.
C
VCB = 0.2 V Ans. (c)
6. Consider the following statements S1 and S2.
N
P S1: The threshold voltage (VTh) of a MOS capaci-
B tor decreases with increase in gate oxide thickness.
+
N S2: The threshold voltage (VTh) of a MOS capaci-
tor decreases with increase in substrate doping
VBE = 0.7 V concentration.
E Which one of the following is correct?
Ans. (a) (a) S1 is FALSE and S2 is TRUE
(b) Both S1 and S2 are TRUE
4. Consider the following statements S1 and S2. (c) Both S1 and S2 are FALSE
S1: The b of a bipolar transistor reduces if the base
(d) S1 is TRUE and S2 is FALSE
width is increased.
S2: The b of a bipolar transistor increases if the
Solution. We have
doping concentration in the base is increased. e ox
Cox =
tox
Which one of the following is correct?
where tox is the gate oxide thickness, eox is the per-
(a) S1 is FALSE and S2 is TRUE mittivity of the gate oxide and Cox is the value of
(b) Both S1 and S2 are TRUE MOS capacitor.
(c) Both S1 and S2 are FALSE
QR Q
VTh =f GC 2f F ox
(d) S1 is TRUE and S2 is FALSE
(GATE 2004: 1 Mark) Cox Cox

If Cox decreases, QB/Cox and Qox/Cox increases (a) 1 V and the device is in active region.
and VTh decreases. (b) -1 V and the device is in saturation region.
Also, Cox decreases when tox increases. Therefore, (c) 1 V and the device is in saturation region.
the threshold voltage (VTh of a MOS capacitor (d) 1 V and the device is in active region.
decreases with increase in the gate oxide thickness. (GATE 2005: 2 Marks)
Moreover, the threshold voltage (VTh) of a MOS Solution. From the given figure
capacitor decreases with increase in substrate VGS = VG VS = 3 1 = 2 V
doping concentration. VDS = VD VS = 5 1 = 4 V
Ans. (d)
7. The drain of an N-channel MOSFET is shorted to Also, from the figure, threshold voltage
the gate so that VGS = VDS. The threshold voltage VTh = 1 V
(VTh) of MOSFET is 1 V. If the drain current (ID) Then,
is 1 mA for VGS = 2 V, then for VGS = 3 V, ID is VGS VTh = 2 1 = 1 V
(a) 2 mA (b) 3 mA (c) 9 mA (d) 4 mA
(GATE 2004: 2 Marks) As, VDS (VGS VTh ) N-channel MOSFET will
operate in saturation region.
Solution.
For a MOSFET, ID = K(VGS VTh)2 Ans. (c)
3
Therefore, 1 10 = K(2 1) . Hence, K = 1 mA/V
2 2 10. An N-channel depletion MOSFET has following
two points on its ID - VGS curve
For VGS = 3 V, drain current is given by
(i) VGS = 0 at ID = 12 mA and
ID = 1 103 (3 1)2 = 4 mA (ii) VGS = 6 Volts at ID = 0
Ans. (d)
Which of the following Q-points will give the high-
8. A MOS capacitor made using P-type substrate is est transconductance gain for small signals?
in the accumulation mode. The dominant charge in
the channel is due to the presence of (a) VGS = 6 V (b) VGS = 3 V
(c) VGS = 0 V (d) VGS = 3 V
(a) holes
(GATE 2006: 1 Mark)
(b) electrons
(c) positively charged ions Solution. We have
(d) negatively charged ions
(GATE 2005: 2 Marks) iD V
2
gm =
VGS V and ID = IDSS 1 GS
Solution. In accumulation mode for N-channel MOS = const V
P
DS
having P-substrate, VG is negative. When negative
VG is applied to the gate electrode, the holes in the I D 2I VGS
gm = = DSS 1 V
VGS
P-type substrate are attracted to the semiconduc-
VP P
tor oxide interface. This condition is called carrier
accumulation on the surface. So gm will be maximum when VGS = 0 and given by
Ans. (a)
2IDSS
9. For an N-channel MOSFET and its transfer curve gm 0 =
shown in the figure, the threshold voltage is VP
Ans. (c)
VD = 5V
11. The phenomenon known as èarly effect in a bipo-
D lar transistor refers to a reduction of the effective
ID
base width caused by
(a) electron-hole recombination at the base
VG = 3V (b) the reverse biasing of the base-collector junction
Transfer (c) the forward biasing of emitter-base junction
characteristics G
(d) the early removal of stored base charge during
saturation to cut-off switching
(GATE 2006: 1 Mark)
S
Ans. (b)
1V VGS VS = 1V

12. The DC current gain (b ) of a BJT is 50. Assuming For P-MOSFET transistor:
that the emitter injection efficiency is 0.995, the mPCox WP
base transport factor is ID2 = ( VGS2 VThP )2
2LP
(a) 0.980 (b) 0.985
(5 2.5 1)2 = 45 mA
40
(c) 0.990 (d) 0.995 =
(GATE 2007: 2 Marks) 2
As ID1 = ID2, both transistors are in saturation and
Solution. Given that, I = ID1 = ID2 = 45 mA
b = 50
14. The drain current of a MOSFET in saturation is
Therefore, given by ID = K(VGS VTh)2 where K is a con-
b
a=
50 stant. The magnitude of the transconductance gm is
=
b + 1 51
K(VGS VTh )2
We know that, (a) (b) 2K(VGS VTh)
VDS
a = (b *)g K(VGS VTh )2
ID
where, b * = base transport factor and g = emitter
(c) (d)
VGS VDS VGS
injection efficiency
(GATE 2008: 1 Mark)
Substituting values, we get
a
Solution. We have
50 1
b* = = = 0.9853 0.985 id K(VGS VTh )2
g 51 0.995
gm = =
Ans. (b) VGS VDS = const.
VGS
13. In the CMOS inverter circuit shown, if the trans- = 2K (VGS VTh )
conductance parameters of the NMOS and PMOS
transistor are Ans. (b)
WN W 15. Two identical NMOS transistors M1 and M2 are
kN = kP = mNCox = mPCox P = 40 A/V2 connected as shown below. Vbias is chosen so that
LN LP
both transistors are in saturation. The equivalent
and their threshold voltages are VTHN = |VTHP| = 1 V, I out
Vin
gm of the pair is defined to be at constant
the current I is Vout.
(a) 0 A (b) 25 mA (c) 45 mA (d) 90 mA
(GATE 2007: 2 Marks) Iout
Vout
5V
Vbias M2 gm2
P-MOSFET
2.5 V I
Vin M1 gm1
N-MOSFET
The equivalent gm of the pair is
Solution. Assuming that both P-MOSFET and (a) the sum of individual gms of the transistors
N-MOSFET are in saturation, then (b) the product of individual gms of the transistors
(c) nearly equal to the gm of M1
For N-MOSFET transistor: (d) nearly equal to the gm/g0 of M2
mNCox WN (GATE 2008: 2 Marks)
ID1 = (VGS1 VThN )2 Solution. The equivalent gm is given by
2LN
1 1 1
(2.5 1)2 = 20 2.25 = 45 mA
40
= = +
2 gm gm1 gm2

From the given figure, we have that transistor M2 VG

is always in saturation due to bias applied but Gate
transconductance of transistor M1 (gm1) changes in P+
accordance with Vin.
Now, N
Source W Drain
g g gm1gm2
gm = m1 m2 =
gm1 + gm2 g
gm2 1 + m1 P+
gm2
Gate VG
But gm2 >> gm1, therefore, gm = gm1
Ans. (c) 1 1 2/VP
(a) 4 (b)
2 1 1/(2VP )
16. The measured transconductance gm of an NMOS
transistor operating in the linear region is plotted 1 2/VP 1 (2/ VP )
against the gate voltage VG at a constant drain (c) (d)
voltage VD. Which of the following figures repre- 1 1/(2VP ) 1 (1/ (2VP ))
sents the expected dependence of gm on VG? (GATE 2008: 2 Marks)
gm gm
Solution. The figure shown is of an N-channel
JFET. Hence, the pinch-off voltage VP is positive.
The transconductance gm is given as
2IDSS V
1 G
VP 2IDSSVP VG
VG VG gm =
1
= 2 V VP VP
(a) (b) gm =
Given that VG
gm gm V G = 2 V
Therefore,
2IDSS 2
gm =
VP 1 + V
P
VG VG
From, the above expression, it is clear that the gm
(c) (d) is inversely proportional to pinch-off voltage VP.
(GATE 2008: 2 Marks) When the width W is increased then VP becomes
more negative as more reverse bias is required at
Solution. Given that the NMOS transistor gatedrain junction to reach the pinch-off condi-
is operating in the linear region. Therefore, tion. Hence, as the width W is increased, magni-
VDS < (VGS VP). tude of VP increases and the value of gm reduces.
The transconductance gm is given by, Therefore, the ratio of initial gm and that of modi-
ID fied gm is greater than 1.
gm =
VGS gm (initial)
>1
gm (modified)
or, gm VGS = ID
which is an expression of hyperbola. Only option (a) is greater than 1 and values of
other options is less than 1.
Ans. (d)
Hence, (a) is the correct answer.
17. The cross-section of a JFET is shown in the Ans. (a)
following figure. Let VG be 2 V and let VP be the
initial pinch-off voltage. If the width W is doubled 18. Consider the following two statements about the
(with other geometrical parameters and doping internal conditions in an N-channel MOSFET
levels remaining the same), then the ratio between operating in the active region.
the mutual transconductances of the initial and the S1: The inversion charge decreases from source to
modified JFET is drain.

S2: The channel potential increases from source to 5V

drain.
Which of the following is correct?
(a) Only S2 is true
3V
(b) Both S1 and S2 are false
(c) Both S1 and S2 are true, but S2 is not a reason
for S1 vo
(d) Both S1 and S2 are true, and S2 is a reason for S1
(GATE 2009: 2 Marks) VG
Solution. Consider the following figure of an

N-channel MOSFET.
19. For small increase in VG beyond 1V, which of the
D following gives the correct description of the region
of operation of each MOSFET?
N+
(a) Both the MOSFETs are in saturation region
G P Substrate (b) Both the MOSFETs are in triode region
(c) N-MOSFET is in triode and P-MOSFET in
N+ saturation region
(d) N-MOSFET is in saturation and P-MOSFET
S Inversion layer
is in triode region
As we can see from the figure, inversion layer 20. Estimate the output voltage Vo for VG = 1.5 V.
width is more towards the source side and it is (Hint: Use the appropriate current-voltage equa-
lesser towards the drain side, so the inversion tion for each MOSFET, based on the answer to
charge decreases from source to drain. Therefore, Question 19.)
in order to attract electrons from source to drain, 1 1
large positive voltage needs to be applied at drain (a) 4 V (b) 4 + V
terminal as compared to source terminal. Hence, 2 2
3 3
VD > VS (c) V (d) 4 + V
2 2
or, VDS > 0 (GATE 2009: 2 Marks)
In other words, the channel potential increases Solution. 19 (d) and 20 (d)
from source to drain. This causes the inversion Assuming that both the transistors are in satura-
layer width to increase towards source side as com- tion, then the drain current of N-type MOSFET is
pared to drain side. Hence, the inversion charge 5V
M2
decrease from source to drain.
Ans. (d)
3V N-MOSFET
Linked Answer for Questions 19 and 20:
Consider the CMOS circuit shown in the figure Vo
below, where the gate voltage VG of the N-MOSFET M1
is kept constant at 3V. Assume that, for both
transistors, the magnitude of the threshold voltage
is 1V and the product of the trans-conductance VGS
P-MOSFET
W
parameter and the ratio, that is, the quantity
L
W mNCox W
mCox is 1mA V-2. (VGS1 VThN )2
L ID1 =
2L
1 103
= (1.5 1)2
2
= 0.125 mA [using VGS1 = 1.5V ]

mNCox W
ID1 = (VGS1 VThN )2 SOLVED GATE PREVIOUS YEARS QUESTIONS 237
2L
1 103 21. In the silicon BJT circuit shown below, assume
= (1.5 1)2 that the emitter area of transistor Q1 is half that of
2
transistor Q2.
= 0.125 mA [using VGS1 = 1.5V ]
Also, drain current of P-type MOSFET is
mPCox W R = 9.3 K
ID2 = (VGS2 VThP )2 Io
2L
1 10 -3
= (3 5 + 1)2
2 Q1 Q2
= 0.50 mA (b 1= 700) (b 2= 715)
The two drain currents have to be equal to satisfy
Kirchhoffs current law, as the gate currents are
zero. Further both the MOSFETs, cannot be in
saturation simultaneously. N-MOSFET which has
saturation current of 0.125 mA, cannot carry cur- -10V
rent of 0.50 mA. Hence P-MOSFET is not in satu-
ration. Therefore, N-MOSFET is in saturation and The value of current Io is approximately
P-MOSFET junction is in triode region.
(a) 0.5 mA (b) 2 mA
As the two drain currents are equal, therefore (c) 9.3 mA (d) 15 mA
ID1 = ID2 = 0.125 mA (GATE 2010: 1 Mark)
mPCox W
0.125 10 -3 A =
1
VGS2 VThP VDS2 VDS2 Solution. The given circuit can be represented as
L 2
IR
3 3 VD 5
0.125 10 = 1 10 3 5 + 1 2 (VD 5) Io
R = 9.3 K
0.25 103 = ( VD + 3)(VD 5)
(
= VD2 + 8VD 15 ) Q1 Q2 ( = 715)
61 ( 1 = 700) 2
or, 8VD +
VD2 =0
4 VBE = 0.7
Solving the quadratic equation, we get
10V
61
8 64 4
4 3
VD = =4 V Assuming that both the transistors are in active
2 2 region, the voltage at Q1 base
For the value
3 (VBase )Q1 = 0.7 10 = 9.3 V
VD = 4 V
2
Using VDS = VD 5 and VGS = 3 5 = 2, we have, Current through R
VDS VGS VThP 9.3 V
IR = = 1 mA = IC1
which implies that P-MOSFET will be in satura- 9.3 103
tion. Hence, the valid solution for the quadratic Given that the emitter area of transistor Q1 is equal
equation is to half the emitter area of transistor Q2, that is,
3
VD = 4 + V AQ2
2 AQ1 =
This will result in 2
VDS VGS VThP Therefore, we have

which implies that the P-MOSFET is in the triode (b2 )effective = 2 b2 = 1430
region.

Since the effective value of b for transistor Q2 is So,

double that for transistor Q1, so collector current VDS1 = 6 - Vx and VGS1 = 5 - Vx
of transistor Q2 will also be nearly the double of
that of transistor Q1 that is VGS1 - VTh = 5 - Vx - 1 = 4 - Vx
I o = IC2 = 2 IC1 = 2 mA Therefore,
Ans. (b)
VDS1 > (VGS1 VTh )
22. At room temperature, a possible value for the
mobility of electrons in the inversion layer of a Hence, the transistor is in saturation region.
silicon N-channel MOSFET is Also, given that for the transistor at the bottom
W2
(a) 450 cm2/Vs (b) 1350 cm2/Vs =1
L2
(c) 1800 cm2/Vs (d) 3600 cm2/Vs
(GATE 2010: 1 Mark) Here, the drain is connected to the gate, hence, the
Ans. (b) transistor is in saturation.
23. In a uniformly doped BJT, assume that NE, NB The current flowing through both the transistors is
and NC are the emitter, base and collector dopings the same. Hence,
in atoms/cm3, respectively. If the emitter injection
W V VTh
2
efficiency of the BJT is close to unity, which one of mNCox 1 GS1
the following conditions is TRUE? L1 2
(b) NE >> NB and NB > NC W V VTh
2
(a) NE = NB = NC
= mNCox 2 . GS2
(c) NE = NB and NB < NC (d) NE < NB < NC
2
L 2
Ans. (b) Substituting the different values in the equation
above, we get
24. In the circuit shown below, for the MOS transistor,
mnCox = 100 mA/V2 and the threshold voltage (5 Vx 1)2 (V 1)2
VTh = 1 V. The voltage Vx at the source of the 4 =1 x ( VGS2 = Vx 0)
2 2
upper transistor is
On simplifying the above equation, we get
( )
(a) 1 V (b) 2 V
(c) 3 V (d) 3.67 V 4 Vx2 8Vx + 16 = Vx2 2Vx + 1
6V 3Vx2 30Vx + 63 = 0
Therefore, Vx = 3 V
Ans. (c)
25. For a BJT, the common-base current gain a = 0.98
5V W/L= 4 and the collector-base junction reverse-bias satura-
tion current ICO = 0.6 mA. This BJT is connected
in the common-emitter mode and operated in the
Vx active region with a base drive current IB = 20 mA.
The collector current IC for this mode of operation is
(a) 0.98 mA (b) 0.99 mA
W/L= 1 (c) 1.0 mA (d) 1.01 mA
Solution. We have
IC = bIB + (1 + b)ICO
a 0.98
Solution. Given that for the upper transistor b= = = 49
1a 1 0.98
IC = 49 20 106+ 50 0.6 106= 1.01 mA
W1
=4
L1 Ans. (d)

W V
WW2 V VGS1 + Vb j1
=
W2 W1 VGSV1GS2 + V+ V
b j1 bj2
=
W1 WSOLVED
2 VGS2 + Vbj2 YEARS QUESTIONS 239
= GATE
4 = 2PREVIOUS
W
W2 1
W1 W2 = 2 m m
Common Data for Questions 26 and = 4 =2
W tch=2 2=m[m
10 2(2)] m m = 6 m m
27: The channel resistance of an N-channel JFET
shown in the figure below is 600 , when the full 2
channel thickness (tch) of 10 mm is available for con- As, tch2 = [10R
2(2)1] m m = 6 m m
duction. The built-in voltage of the gate P+N junc- 1 tch
tion (Vbj) is 1 V. When the gate-to-source voltage R
(VGS) is 0 V, the channel is depleted by 1 mm on
As,
(10 10R
t resistance 6)
at VGS = -3 V is
1000 W
Therefore, channel
R2 = 600ch 2=
each side due to the built-in voltage and hence the (10 (610
106 ) )
6
thickness available for conduction is only 8 mm. R2 = 600 = 1000 W

(6 106 )
Ans. (c)
+ Gate 10 3
28. The source of a silicon (ni = 10 per cm ) N-channel
MOS transistor has an area of 1 sq mm and a depth of
VGS
P+
- Source Drain 1 mm. If the dopant density in the source is 1019/cm3,
tch N
the number of holes in the source region with the
P+ above volume is approximately
(a) 107 (b) 100
(c) 10 (d) 0
26. The channel resistance when VGS = 0 V is
(a) 480 (b) 600 Solution. Given that A = 1 1012 m2 and d =
(c) 750 (d) 1000 106 m
(GATE 2011: 2 Marks) Therefore, V = Ad = 1018 m3 = 1012/cm3
Also, given that ND = n = 1019/cm3 and ni = 1010/cm3
Solution. Given that the channel resistance Ro at
tch = 100 m is 600 .
Therefore,
Also, at VGS = 0 V, tch = 8 mm ni2 1020

p= = 19 = 10/cm3
ND 10
1 1
As R A = tch W. Therefore,
1 1
and
,R R ,R Therefore, holes in volume V is H = pV = 1011
A tch A tch
(A is the cross-sectional area of the channel and W As the number of holes cannot be a decimal
is the channel width.) number, therefore, number of holes H = 0.
Therefore, channel resistance R1 at VGS = 0 V Ans. (d)
6
(10 10 ) 29. In the CMOS circuit shown below, the electron
R1 = 6
600 = 750
(8 10 )
and hole mobilities are equal, and M1 and M2 are
Ans. (c) equally sized. The device M1 is in the linear region if
27. The channel resistance when VGS = 3 V is 5V
(a) 360 (b) 917
(c) 1000 (d) 3000 M1
[GATE 2011: 2 Marks]
VTh=1V
Solution. The depletion width of the channel on
one side is directly propostional to the square-root
Vin
of sum of the built-in voltage of the P+N junction
and gate-source voltage.
Therefore,
Vin=1V
W V
M2
W2 VGS1 + Vb j1
=
W1 VGS2 + Vbj2
W2 (a) Vin < 1.875 V (b) 1.875 V < Vin < 3.125 V
= 4 =2 (c) Vin < 3.125 V (d) 0 < Vin < 5 V
W1 (GATE 2012: 2 Marks)
W2 = 2 m m
tch2 = [10 2(2)] m m = 6 m m
1
As, R
tch
(10 106 ) 6/30/2015 11:51:42 AM
R = 600 = 1000 W
Solution. The given inverter is a CMOS inverter 30. The source-body junction capacitance is approximately
and since the threshold voltage values of both
(a) 2 fF (b) 7 fF
N-MOSFET and P-MOSFET transistors are equal,
(c) 2 pF (d) 7 pF
it is also a symmetric inverter. The following graph
shows the I-V characteristics of the inverter.
Solution. Source-body junction capacitance
Vo (V) ID (A)
6 600 eA e e A
Vo ID Cj = = 0 r
5 500 d d
4 400 Here, er = 11.7 as the channel is of Si.

3 300 A = 1 mm 0.2 mm = 0.2 1012 m2
d = Depletion width of PN junction = 10 nm =
108 m
2 200
1 100 Therefore,
0
0 1 2 3 4 0
0 8.9 1012 11.7 0.2 1012
Cj = = 2 pF
Vin (V) 108
Ans. (a)
It shows that:
31. The gate-source overlap capacitance is approximately
(i)For Vin slightly greater than VTh. P-MOSFET
(M1) stays in linear region and N-MOSFET (a) 0.7 fF (b) 0.7 pF
(M2) in the saturation region. (c) 0.35 fF (d) 0.24 pF
(ii)As Vin increases, the drain current increases, (GATE 2012: 2 Marks)
voltage drop across M1 increases and the
output voltage reduces. Solution. Gate-source capacitance
(iii)P-MOSFET (M1) enters into saturation region eA e e A
at a later point. Cg = 1 1 = 0 r1 1
d1 d1
Hence, we have that P-MOSFET M1 is in linear er1 = 3.9 as between gate and source there is SiO2
region for Vin < 1.875 V.
Ans. (a) A1=1 mmd =110620109=21014 m2
d1=1 nm=109 m
Common Data for Questions 30 and
31: In the three-dimensional view of a silicon Therefore,
N-channel MOS transistor shown in the figure, d = 8.9 1012 3.9 2 1014
20 nm. The transistor is of width 1 mm. The deple- Cg =
109
= 0.7 pF
tion width formed at every PN junction is 10 nm. Ans. (a)
The relative permittivities of Si and SiO2, respec-
tively, are 11.7 and 3.9, and e0 = 8.9 1012 F/m.
32. In a MOSFET operating in the saturation region,
the channel length modulation effect causes
(a) an increase in the gate-source capacitance
1 m (b) a decrease in the transconductance
(c) a decrease in the unity-gain cut-off frequency
G (d) a decrease in the output resistance
(GATE 2013: 1 Mark)
1 m
D 1 nm
Solution. In a MOSFET operating in the satura-
0.2 m
tion region, the channel length modulation effect
0.2 m
D d S d causes a decrease in the output resistance.
0.2 m P-substrate 0.2 m
Ans. (d)

CHAPTER 11
LASER BASICS
In this chapter the fundamental topics of lasers including principle of operation of laser, properties of lasers and types
of lasers are discussed.
11.1 INTRODUCTION of a photon. Population inversion is an essential condi-

tion for the stimulated emission process to take place.
Laser is an acronym for Light Amplification by

11.1.1 Absorption and Emission Processes
Stimulated Emission of Radiation. It is undoubtedly
one of the greatest inventions of the second half of the Absorption, spontaneous emission and stimulated
twentieth century. The first laser was demonstrated by emission are all optically allowed transitions. The particle
Theodore Maiman in May 1960 at Hughes Research may make an absorption transition from the lower level
Laboratories. to the higher level [Fig. 11.1(a)]. The emission process
The basic principle of operation of a laser device involves transition from a higher excited energy level to a
is evident from the expanded form of the acronym lower energy level. These are of two types, namely, spon-
`LASER, which says that it produces a light output due taneous emission and stimulated emission. Spontaneous
to stimulated emission of radiation. In case of ordinary emission is the phenomenon in which an atom or a mole-
light such as that from the sun or an electric bulb, dif- cule undergoes a transition from an excited higher energy
ferent photons are emitted spontaneously due to vari- level to a lower level all by itself without any outside
ous atoms or molecules releasing their excess energy on intervention or stimulation and in the process emits a
their own. In case of stimulated emission, an atom or a resonance photon [Fig. 11.1(b)]. The rate of spontaneous
molecule holding excess energy is stimulated by another emission process is proportional to the related Einstein
photon emitted earlier to release that energy in the form coefficient. In case of stimulated emission [Fig. 11.1(c)],

242 Chapter 11: Laser Basics
11.2 TYPES OF LASER SYSTEM

+ E1 E2 + E1 E2
11.2.1 Two-Level Laser System
(a) In a two-level laser system, there are only two levels

involved in the total process. That is, the atoms or
molecules in the lower level, which is also the lower level
of the laser transition, are excited to the upper level by

the pumping or excitation mechanism. The upper level is
+ E1 E2 + E1 E2 also the upper laser level. Once the population inversion
is achieved and its extent is above the inversion thresh-
old, the laser action can take place. A two-level system
(b) is, however, a theoretical concept only as far as lasers
Emitted are concerned. No laser ever has been made to work as
Stimulating a two-level system.
photons

photon
+ E1 E2 + E1 E2 11.2.2 Three-Level Laser System
In a three-level laser system, the lower level of laser

(c) transition is the ground state (the lowermost energy
Figure 11.1| Absorption and emission processes:
level). The atoms or molecules are excited to an upper
level higher than the upper level of the laser transition
(a)absorption, (b) spontaneous emission
and (c) stimulated emission. (Fig. 11.2). The upper level to which atoms or molecules
are excited from the ground state has relatively much
there first exists a photon called stimulating photon shorter lifetime as compared to the lifetime of the upper
having energy equal to the resonance energy (hu). laser level, which is a metastable level. As a result, the
This photon perturbs another excited species (atom excited species rapidly drop to the metastable level. A
or molecule) and causes it to drop to the lower energy relatively much longer lifetime for the metastable level
level, in the process emitting a photon of the same fre- ensures a population inversion between the metastable
quency, phase and polarization as that of the stimulat- level and the ground state provided that at least more
ing photon. It may be mentioned here that stimulated than half of the atoms or molecules in the ground
emission is the basis for photon multiplication and the state have been excited to the uppermost short-lived
fundamental mechanism underlying all laser action. energy level. The laser action occurs between the meta-
stable level and theground state.
According to Boltzmann statistical thermodynamics,
under normal conditions of thermal equilibrium, atoms and
molecules tend to be at their lowest possible energy level Upper level
with the result that population decreases as the energy
level increases. If E1 and E2 are the energy levels associ- Fast non-radiative
ated with level 1 and level 2, where, energy level of level 2 decay
is higher than that of level 1. then the populations of these Metastable level
Pump transition
two levels can be expressed by the following equation: (Upper laser level)
Laser transition
N2 E E1
= exp 2
kT
(11.1)
N1
where k is the Boltzmann constant = 1.38 10-23 J/K
or 8.6 10-23 eV/K, and T is the absolute temperature
in kelvin.
This condition of N2 > N1 is known as population
inversion as under normal conditions, N1 > N2. We shall Ground state
explain in the following paragraphs why population (Lower laser level)
inversion is essential for a sustained stimulated emission
and hence the laser action. Figure 11.2| Three-level laser system.

11.3 GAIN OF LASER MEDIUM 243
Ruby laser is a classical example of a three-level laser. shorter lifetime of the lower laser level. Once it is sim-
One of the major shortcomings of this laser and also all pler to sustain population inversion, it becomes easier to
three-level lasers is due to the lower laser level being operate the laser in the continuous (CW) mode. This is
the ground state. Because under thermodynamic equilib- one of the major reasons why a four-level laser such as
rium conditions, almost all atoms or molecules are in the an Nd-YAG laser or a helium-neon laser can be operated
ground state, it requires at least more than half of this in the continuous mode while a three-level laser such as
number to be excited out of the ground state to achieve a ruby laser can be operated only as a pulsed laser.
laser action. This implies that a much larger pumping Nd-YAG, helium-neon and carbon dioxide lasers
input would be required to exceed population inversion are some of the very popular lasers having a four-level
threshold. This makes it very difficult to sustain popula- energy level structure.
tion inversion on a continuous basis in three-level lasers.
This is why ruby laser cannot be operated in continuous
wave (CW) mode. 11.3 GAIN OF LASER MEDIUM
11.2.3 Four-Level Laser System

When we talk about gain of the laser medium, we basi-
cally talk about the extent to which this medium can
In a four-level laser system (Fig. 11.3), the atoms or
produce stimulated emission. The gain of the medium is
molecules are excited out of the ground state to an upper
defined more appropriately as gain coefficient which is
highly excited short-lived energy level. Remember that
the gain expressed as a percentage per unit length of the
the lower laser level here is not the ground state. In this
active medium. When we say that the gain of a certain
case, the number of atoms or molecules required to be
laser medium is 10% per cm, it implies that 100 photons
excited to the upper level would depend upon the popu-
having the same transition energy as that of excited
lation of the lower laser level, which is much smaller than
laser medium become 110 photons after travelling 1 cm
the population of the ground state. Also, if the upper
of the medium length. The amplification or the photon
level to which the atoms or molecules are initially excited
multiplication offered by the medium is expressed as a
and the lower laser level have a shorter lifetime and the
function of the gain of the medium and the length of the
upper laser level (metastable level) a longer lifetime, one
medium by the following equation:
can visualize that it would be much easier to achieve
GA = eax
and sustain population inversion. This comes from two
(11.2)
major happenings in such a four-level laser. One is rapid
population of the upper laser level, which comes from where GA is the amplifier gain or amplification factor, a
extremely rapid dropping of the excited species from the is the gain coefficient and x is the gain length.
upper excited level where they find themselves in with
excitation input to the upper laser level accompanied by Above expression for gain can be rewritten as given in
the longer lifetime of the upper laser level. The second the following equation:
GA = (ea )x = (1 + a )x
happening is the depopulation of lower laser level due to
fora 1 (11.3)

Therefore, to a reasonably good approximation, we can
Upper level
write
Fast non-radiative Amplification factor = (1 + Gain coefficient)Gain length
decay
Metastable level For any useful laser output, therefore, solution lies in
Laser transition
Pump transition
(Upper laser level) having a very large effective gain length. If we enclose
the laser medium within a closed path bounded by
two mirrors, as shown in Fig. 11.4, we can effectively
increase the interaction length of the active medium
by making the photons emitted by stimulated emission
Lower laser level process travel back and forth. One of the mirrors in the
arrangement is fully reflecting and the other has a small
Faster decay amount of transmission. This little transmission, which
Ground state also constitutes the useful laser output, adds to the
loss component. This is true because the fraction of the
Figure 11.3| Four-level laser system. stimulated emission of photons taken as the useful laser

positive peak after it makes a round trip of the cavity

and returns to the fully reflecting mirror again. If this
happens, then all those photons stimulated by this
photon would also satisfy this condition. This can be
possible if we satisfy the condition given in the following
equation:
Fully Gain Partially
reflecting medium transmissive Round trip length = 2L = nl (11.4)

mirror mirror
where L is the length of the resonator, l is the wave-
Figure 11.4| Lasing medium bounded by mirrors.
length and n is the integer.
The above expression can be rewritten as
output is no longer available for interaction with the nc
excited species in the upper laser level. Quite obviously, f= (11.5)
2L
maximum power that can be coupled out of the system
must not exceed the total amount of losses within the where c is the velocity of the electromagnetic wave and
closed path. For instance, if the gain of the full length f is the frequency.
of the active medium is 5% and the other losses such as
those due to absorption in the active medium, spontane-
ous emission, losses in the fully reflecting mirror (which 11.5 LONGITUDINAL AND
will not have an ideal reflectance of 100%), etc. are 3%, TRANSVERSE MODES
the other mirror can have at the most a transmission
of 2%. In a close system like this, the power inside the
system is going to be much larger than the power avail- The expression for frequency (Eq. 11.5) indicates that
able as useful output. For instance, for 1% transmission there could be a large number of frequencies for differ-
and assuming other losses to be negligible, if the output ent values of integer `n satisfying this resonance condi-
power is 1 mW, the power inside the system would be tion. Most laser transitions have gain for a wide range
100 mW. of wavelengths. Remember that we are not referring to
lasers that can possibly emit at more than one wave-
length such as a helium-neon laser. Here, we are referring
to the gain bandwidth of one particular transition.
11.4 LASER RESONATOR
Therefore it is possible to have more than one resonant
frequency, each one of them called a longitudinal mode,
The active laser medium within the closed path bounded to be simultaneously present unless special measures are
by two mirrors, as shown in Fig. 11.4, constitutes the taken to prevent this from happening. As is clear from
basic laser resonator provided it meets certain condi- the expression for frequency, the intermode spacing is
tions. Also, resonator structures of most practical laser given by c/2L. As a typical case, for a helium-neon laser
sources would be more complex than the simplistic with a cavity length of 30 cm, intermode spacing would
arrangement of Fig. 11.4. As said before, with the help be 500 MHz, which may allow three longitudinal modes
of these mirrors we can effectively increase the interac- to be simultaneously present as shown in Fig. 11.5(a).
tion length of the active medium by making the photons Interestingly, one could reduce the cavity length to a
emitted by stimulated emission process travel back and point where the intermode spacing exceeds the gain
forth within the length of the cavity. One of the mirrors bandwidth of the laser transition to allow only a single
in the arrangement is fully reflecting and the other has longitudinal mode to prevail in the cavity. For instance,
a small amount of transmission for reasons already out- a 10-cm cavity length leading to an intermode spacing of
lined in the previous paragraph. It is clear that if we 1500 MHz would allow only a single longitudinal mode
want the photons emitted as a result of stimulated emis- [Fig. 11.5(b)]. However, we will appreciate that there are
sion process to continue to add to the strength of those other important criteria that decide the cavity length.
responsible for their emission, it would be necessary for Another laser parameter that we are interested in and
the stimulating and stimulated photons to be in phase. that is also largely influenced by the design of the laser
The addition of mirrors should not disturb this condi- resonator is the transverse mode structure of the laser
tion. For example, if the wave associated with a given output. The transverse modes basically tell us about the
photon was at its positive peak at the time of reflection irradiance distribution of the laser output in the plane
from the fully reflecting mirror, it should again be at its perpendicular to the direction of propagation or in other

11.6 LASER CHARACTERISTICS 245
Figure 11.6 shows the spatial intensity distribution of

the laser spot for various transverse mode structures of
the laser resonator.
Gain
l or f
500 MHz 500 MHz
(a)
Gain
l or f
500 MHz
(b)
Figure 11.5| Longitudinal modes.
Figure 11.6| Spatial intensity distribution for various

words along the orthogonal axes perpendicular to the transverse modes.
laser axis.
TEMmn describes the transverse mode structure, where
m and n are integers indicating the order of the mode.
11.6 LASER CHARACTERISTICS
In fact, integers m and n are the number of intensity
minima or nodes in the spatial intensity pattern along Laser radiation can be distinguished from the light from
the two orthogonal axes. Conventionally, the first integer conventional sources on the basis of its special charac-
represents the electric field component and the second teristics and the effects it is able to produce because of
indicates the magnetic field component. Remember that these characteristics. It is these characteristics that have
transverse modes must satisfy the boundary conditions led to explosive growth in the usage of laser devices in
like having zero amplitude on the boundaries. The the last more than 45 years after the invention of this
simplest mode, also known as the fundamental or the magic source of light. These include the following:
lowest order mode, is designated as TEM00 mode.
The two subscripts here indicate that there are no minima 1. Monochromaticity
along the two orthogonal axes between the boundaries. 2. Coherence, temporal and spatial
The intensity pattern in both the orthogonal directions 3. Directionality
has a single maximum with the intensity falling on both
sides following a well-known mathematical distribution 11.6.1 Monochromaticity
called Gaussian distribution. The Gaussian distribution
is given by the following equation: Monochromaticity refers to single frequency or wave-
length property of the radiation. Laser radiation is
2r 2
I (r) = I 0 exp 2 monochromatic and this property has its origin in the
w
(11.6)
stimulated emission process by which laser emits light.
While describing the process of stimulated emission,
where I(r) is the intensity at a distance of r from the we had said that the stimulated photon has the same
centre of the beam and w is the beam radius at 1/e2 of frequency, phase and polarization as those of the stimu-
the peak intensity point, which is about 13.5% of the lating photon. As we shall see in the following paragraphs,
peak intensity. monochromaticity is one of the essential requirements
Also, for the laser radiation to be coherent, though a mono-
2P chromatic radiation is not necessarily coherent. We shall
I0 =
(11.7) see that a coherent radiation is necessarily monochro-
pw2 matic. Table 11.1 shows the wavelength of some of the
where P is the total power in the beam. commonly used lasers.

Table 11.1| Wavelength of commonly used lasers.
Type of Laser Wavelength (nm) Line Width (cm-1) Line Width (nm) Line Width (GHz)
Ruby laser 694.3 11 0.53 330
Ruby laser 692.9 11 0.53 330
Nd-YAG laser 1064 15 0.10.5 25150
Nd-Glass laser 1054 180 20 5400
(Phosphate)
Nd-Glass laser 1062 245 27.7 7370
(Silicate)
Helium-neon laser 632.8 0.05 1.9 10-3 1.4
Helium cadmium laser 441.6 0.1 0.002 3
Carbon dioxide laser 900011000 (main 0.002 0.022 0.06
10600 nm)
Alexandrite laser 720800 (tunable)
Titanium sapphire 6801130 (tunable)
GaAlAs laser 750900
InGaAsP laser 12001600
Excimer laser (XeF) 351 3328 41 99836
Excimer laser (XeCl) 308 3331 31.6 99932
Excimer laser (ArF) 193 0.335 0.00125 10
Excimer laser (KrF) 248 0.3 0.00185 9
Copper vapour laser 510.5 0.077 0.002 2.3
11.6.2 Coherence
same phase and this phase relationship is preserved as a
If we have to mention one property that distinguishes function of time (Fig. 11.7). That is, this phase relation-
the laser radiation from the ordinary light, it is coher- ship is preserved as the radiation wave front travels with
ence. Light is said to be coherent when different photons time. There are two types of coherence called temporal
(or the waves associated with those photons) have the coherence and spatial coherence.
(a) (b)
Figure 11.7| Coherence. (a) Incoherent light waves. (b) Coherent light waves.

11.7TYPES OF LASERS 247
11.6.2.1Temporal Coherence In addition, there are a large number of other varieties

of lasers that do not fit into any of the above-mentioned
Temporal coherence is preservation of phase relationship broad categories. These include dye lasers, excimer
with time and that is what we have been talking under lasers, metal vapour lasers, free-electron lasers, X-ray
coherence till now. Coherence length can be computed lasers, chemical lasers, gas dynamic lasers and so on.
from the known value of wavelength spread from the
following expression: 11.7.1 Solid-State Lasers
l2
Coherence length = (11.8)
2Dl
Solid-state lasers have solid material as the host material.
Neodymium and chromium are the most widely exploited
lasing species in solid-state lasers. While chromium is
11.6.2.2Spatial Coherence
used in ruby, alexandrite and chromium doped GSGG
(gadolinium scandium gallium garnet) lasers, neodymium
Spatial coherence tells about the correlation in phase of
is used in Nd-YAG, Nd-Glass, Nd-YLF and Nd-YVO4
different photons transverse to the direction of travel. It
lasers. Erbium is the lasing species for eye-safe class of
is the area in the plane perpendicular to the direction of
solid-state lasers. Titanium is used in titanium-sapphire
travel over which the radiation preserves the coherence.
lasers.
The spatial coherence depends upon the transverse mode
discrimination property of the laser resonator. Laser radi- In the case of solid-state lasers (though it is true for
ation operating in the lowest order mode (TEM00) will any other laser too), characteristics of host material are
certainly be more spatially coherent than a multimode no less important than those of lasing species. A good
laser radiation. When a laser is operating in a single host material in the case of solid-state lasers should have
transverse mode, the radiation will be spatially coherent such optical, mechanical and thermal properties as to
across the diameter of the beam over reasonable prop- favour homogeneous propagation of light through it and
agation distances. Youngs double slit experiment and thus a good beam quality, high average power operation
formation of fringes thereof is the best illustration of the and capability to withstand severe operating conditions
phenomenon of spatial coherence. of practical laser systems. Amongst crystalline hosts,
common names include yttrium aluminium garnet
(YAG), yttrium lithium fluoride (YLF), gadolinium
11.6.3 Directionality gallium garnet (GGG), gadolinium scandium gallium
garnet (GSGG), yttrium doped vanadate (YVO4),
The directionality of laser radiation has its origin in the sapphire and chrysoberyl. Silicate and phosphate glasses
coherence property of the stimulated emission process. are common among glass hosts.
All photons emitted as a result of stimulated emission
process have the same frequency, phase, direction and
polarization. These photons when emitted carry no infor-
11.7.2 Gas Lasers
mation regarding the location of the excited atom or
Gas lasers have widely varying characteristics includ-
molecule responsible for its emission. It appears as if all
ing wavelength range, power levels and to some extent
photons were emitted from a tiny volume with dimen-
pump mechanisms. Power level varies from fraction of a
sions that are of the order of a wavelength. If a photon
milliwatt (in low-power helium-neon lasers) to megawatt
is emitted off-axis, spatial coherence makes it appear as
level in weapon-class high-power laser. Thousands of gas
if it were emitted from the axis. Similarly, a photon that
laser wavelengths have been discovered from ultraviolet
is emitted away from the beam waist on the same axis,
to far infrared. Gas lasers have Doppler-broadened gain
temporal coherence makes it appear as if it were emitted
versus frequency curve and most gas lasers are excited
from the beam waist.
by electrical discharge.
Active medium in a gas laser is almost invariably a
11.7 TYPES OF LASERS mixture of more than one gases with the gases other
than the lasing species performing certain subtle func-
tions such as assisting in heat transfer like in helium
On the basis of the type of laser medium, there are three in carbon dioxide laser or depopulating the lower laser
major categories of lasers, which include the following: level like helium in helium-neon laser. Also, active media
in different gas lasers may not be in the same form. It
1. Solid-state lasers could be in the form of ionized atoms as in the case of
2. Gas lasers argon-ion and krypton-ion lasers or hot metal vapour as
3. Semiconductor lasers in the case of copper vapour and gold vapour lasers.

Excimer lasers are pulsed lasers capable of providing s pontaneously emitted photon having energy equal to
pulse energies of the order of joules and are the most involved recombination energy stimulates an electron
powerful lasers emitting in ultraviolet. hole pair to recombine to emit a photon of same fre-
Wavelengths emitted by some common gas lasers are quency, phase and polarization as that of stimulating
543, 632.8 and 1153 nm (helium-neon lasers), 900011000 nm photon. This phenomenon is called stimulated emission.
(carbon dioxide lasers), 510 and 578 nm (copper
Surrounding the recombination region, where spontane-
vapour laser), 325, 354 and 442 nm (helium-cadmium
laser), 275305 nm, 333364 nm (argon-ion laser), ous emission is taking place, also called gain medium
335360 nm, 406416 nm and 647 nm (krypton ion laser), by a suitable optical cavity, supports the process of
26003000 nm (hydrogen fluoride laser), 36004000 nm stimulated emission. The cavity in the case of laser
(deuterium fluoride laser), 193 nm (argon fluoride laser) diode is made by cleaving the two ends of the crystal to
and 249 nm (krypton fluoride laser). form perfectly smooth, parallel edges forming a fabry-
perot resonator. As the semiconductors have a high
11.7.3 Semiconductor Lasers refractive index, the smooth surfaces offered by cleaved
ends reflect about 30% of light back into the material
In a semiconductor laser, also called diode laser, emis- to get sustained laser action in a high-gain semicon-
sion of radiation is due to recombination of electrons and
ductor laser material. The stimulated emission produces
holes in a forward-biased PN junction. Only direct band
gap semiconductor materials are suitable for making light amplification as the photons travel back and forth
diode lasers. Compound semiconductors are used for between the two end faces of the cavity. And when the
making diode lasers and most important of these are the gain due to stimulated emission exceeds the losses due
ones that comprise of equal amount of elements from to absorption or imperfect reflections, etc., sustained
IIIa and Va groups of periodic table. Both ternary and lasing action is produced.
quaternary compounds are used.
Light-emitting diodes (LEDs) too operate in the same
The active medium in a semiconductor laser, as way with a major difference in the forward-biased current.
suggested by the name itself, is a semiconductor mate- While the current in case of an LED is of the order of a
rial. These are commonly known as diode lasers as the few milliamperes, the same in case of laser diodes emit-
emission of radiation is due to recombination of holes ting few milliwatts of laser power is of the order of 80
and electrons in a forward-biased PN junction diode. to 100 mA. At low levels of drive current, spontaneous
In the following paragraphs, the operational basics, the emission predominates. When the drive current is more
common semiconductor materials and different types of than the lasing threshold, the light output is predomi-
diode lasers are discussed. nantly due to stimulated emission. Figure 11.8 shows the
As outlined above, emission of radiation in a diode IV characteristics of a typical diode laser.
laser is due to recombination of electrons and holes in a
forward-biased PN junction. When the laser diode, a PN
Forward voltage Vf (V)
junction diode, is forward biased, holes and electrons,

respectively, from P-type region and N-type region are 2 20C
injected into N-type and P-type regions. When elec-
trons and holes are present in the same region, there is a 40C
likelihood of their recombination leading to spontaneous
emission of a photon where energy of emitted photon 1
equals the difference in energy levels of electron and hole
states involved in the recombination. In the process, the
electron may reoccupy the energy state of the hole. The
injected electrons and holes constitute the injection cur-
rent and those involved in recombination process consti-
tute the spontaneously emitted photon output. Laser diode forward current I (mA)
If the injection current exceeds a certain minimum Figure 11.8| IV characteristics of a typical diode laser.
value, called lasing threshold, the number of elec- Some of the popular semiconductor laser types and
trons and holes available for recombination becomes the wavelength region emitted by there are tabulated in
sufficiently large so as to create a possibility where a Table 11.2.

SOLVED EXAMPLES 249
Table 11.2| Some semiconductor lasers and wavelengths emitted.
Semiconductor Laser Junction Type Wavelength Emitted (nm)

AlGaInP/GaAs Heterojunction 620680
Ga0.5In0.5P/GaAs Heterojunction 670680
GaAlAs/GaAs Heterojunction 750870
GaAs/GaAs Homojunction 904
InGaAsP/InP Heterojunction 11001650
IMPORTANT FORMULAS
nc
1. Population levels of two states is given by 4. Round trip length = 2L = nl and f =
2L
N2 E E1
= exp 2
kT
5. The Gaussian distribution is given by the following
N1 equation:
2r 2
2. Amplifier gain or amplification factor: I (r) = I 0 exp 2
w

GA = eax
l2
3. Amplification factor=(1+Gain coefficient)Gain length 6. Coherence length =
2Dl
SOLVED EXAMPLES
1. The transverse mode that is associated with the emission wavelength spectrum of krypton and
least beam divergence is xenon filled flash lamps includes the absorption
lines of solid-state lasers.
(a) TEM00 mode (b) TEM01 mode
Ans. (c)
(c) TEM10 mode (d) TEM03 mode
3. The lasers used for optical pumping of other lasers
Solution. The TEM00 mode has the least beam
divergence. (a) are laser diode arrays
Ans. (a) (b) are pulsed solid-state lasers
(c) include diode lasers, pulsed and CW solid-state
2. Flash lamps suitable for solid-state laser pumping lasers, excimer lasers, metal vapour lasers and
are usually filled with so on.
(a) xenon (d) None of these
(b) krypton
(c) xenon or krypton Solution. All these lasers are used for optical pump-
(d) mixture of xenon and krypton ing of other lasers as they emit radiation in the
optical band.
Solution. Krypton and xenon filled flash lamps Ans. (c)
are suitable for solid-state laser pumping as the

1. A certain helium-neon laser emitting at 633 nm has 2. For the laser given in Question1, find the coherence
a line width of 0.002 nm. Find the coherence length length in centimetre if the same laser was frequency
of the laser in centimetre. stabilized to a frequency uncertainty of 100 kHz.
Solution. We have Solution. We have
l2
c
Coherence length = Coherence length =
2Dl 2Df
Given that l = 633 nm and Dl = 0.002 nm. Given that Df = 100 kHz = 100000 Hz. Therefore,
Therefore,
(633)2 3 108
nm = 108 nm = 10 cm Coherence length = =1500 m = 150000 cm
Coherence length =
2 0.002 2 100000
Ans. (10) Ans. (150000)
PRACTICE EXERCISE
1. Which one of the following is a stable resonator (a) Ga1-x Alx As (b) Gax Al1-x As
configuration? (c) Ga1-x Al Asx (d) Gax Al As1-x
(a) Confocal resonator (1 Mark)
(b) Hemispherical resonator 6. In the case of diode lasers,
(c) Concentric resonator
(a) slope efficiency increases with increase in
(d) All of the above
temperature
(1 Mark)
(b) gain profile shifts towards shorter wavelengths
2. The fundamental transverse mode has the follow- with increase in temperature
ing attributes: (c) slope efficiency decreases with increase in
temperature
(a) It has least power spreading (d) threshold current increases with increase in
(b) It has minimum diffraction loss temperature
(c) It can be focused to smallest possible spot (e) Both (c) and (d)
(d) All of the above (1 Mark)
(1 Mark)
7. In the case of ternary and quaternary compound
3. An unstable resonator is associated with semiconductors used for making laser diodes,
(a) high-gain laser medium (a) total quantity of group IIIa elements is more
(b) large interaction volume than the total quantity of group Va elements
(c) less critical alignment (b) total quantity of group IIIa elements is less
(d) All of the above than the total quantity of group Va elements
(1 Mark) (c) total quantity of group IIIa elements is equal to
the total quantity of group Va elements
4. Parameter that can possibly be used to stabilize (d) None of these
output wavelength in the case of semiconductor (1 Mark)
laser is 8. Which one of the following cannot be categorized
(a) drive current (b) diode temperature as a chemical laser?
(c) Both (a) and (b) (d) None of the above (a) HF laser
(1 Mark) (b) Combustion-driven carbon dioxide gas dynamic
laser
5. The generalized formula for the most commonly (c) Chemical oxygen iodine laser
used ternary compounds in semiconductor diode (d) DF laser
lasers is (1 Mark)

9. Which one of the following solid-state laser host (a) Neodymium (b) Chromium
materials is particularly suitable for diode pumping? (c) Titanium (d) All the above
(a) Yttrium aluminium garnet (YAG) (1 Mark)
(b) Yttrium lithium fluoride (YLF) 11. Which of the following operational modes is likely
(c) Yttrium vanadate (YVO4) to produce the shortest pulse width?
(d) Phosphate glass
(1 Mark) (a) Q-switched (b) Cavity dumped
(c) Quasi-CW (d) Mode locked
10. Of the following, which is the lasing species used in (1 Mark)
the case of solid-state lasers?
1. Find the gain coefficient (cm-1) in case of a helium- emitting at 1.15 mm is 770 MHz. Find the inter-
neon laser if a 50-cm gain length produces amplifi- longitudinal mode spacing in megahertz.
cation by a factor of 1.1. (1 Mark)
(2 Marks)
3. For the data given in Question 2, find the number of
2. Given that Doppler-broadened gain curve of a maximum possible sustainable longitudinal modes.
helium-neon laser with a 50-cm long resonator and (2 Marks)
1. (d) 4. (c) 7. (c) 10. (d)

2. (d) 5. (a) 8. (b) 11. (d)
3. (d) 6. (e) 9. (c)
1. Given that x = 50 cm and amplification factor 3. Width of Doppler-broadened gain curve = 770 MHz
GA = 1.1 Number of longitudinal modes possible within this
Gain coefficient (a) can be computed from GA = eax width = 3 as shown in following figure.
or a = ln(1.1) = 0.0019 cm1

1 1
ln GA =
x 50
Ans. (0.0019)
Gain
2. Resonator length L = 50 cm
Therefore, inter-longitudinal mode spacing = c/2L Threshold
= 3 1010/100 = 300 MHz
f
Ans. (300) 300 MHz 300 MHz
770 MHz
1. Match items in Group 1 with items in Group 2, R. Tunnel diode

most suitably. S. LASER
Group 1 Group 2
P. LED 1. Heavy doping
Q. Avalanche photodiode 2. Coherent radiation

3. Spontaneous emission (a) P-1, Q-2, R-1, S-2 (b) P-2, Q-1, R-1, S-2
4. Current gain (c) P-2, Q-2, R-2, S-1 (d) P-2, Q-1, R-2, S-2
(a) P-1; Q-2; R-4; S-3 (b) P-2; Q-3; R-1; S-4 (GATE 2007: 2 Marks)
(c) P-3; Q-4; R-1; S-2 (d) P-2; Q-1; R-4; S-3 Ans. (b)
(GATE 2003: 2 Marks) 3. Group I lists four different semiconductor devices.
Ans. (c) Match each device in Group I with its characteris-
tic property in Group II.
2. Group I lists four types of PN junction diodes. Group I Group II
Match each device in Group I with one of
the options in Group II to indicate the bias P. BJT 1. Population inversion
condition of that device in its normal mode of Q. MOS capacitor 2. Pinch-off voltage
operation. R. LASER diode 3. Early effect
S. JFET 4. Flat-band voltage
Group I Group II
(a) P-3, Q-1, R-4, S-2 (b) P-1, Q-4, R-3, S-2
P. Zener diode 1. Forward bias (c) P-3, Q-4, R-1, S-2 (d) P-3, G-2, R-1, S-4
Q. Solar cell 2. Reverse bias
R. LASER diode (GATE 2007: 2 Marks)
S. Avalanche photodiode Ans. (c)

CHAPTER 12
DEVICE TECHNOLOGY
In this chapter integrated circuits fabrication process including oxidation, diffusion, ion implantation, photolithography,
N-tub, P-tub and twin-tub CMOS processes are discussed.
12.1 INTEGRATED CIRCUITS good thermal stability because all the components are
integrated on the same chip very close to each other.
However, the large values of resistors and capacitance
Integrated circuit (IC) means that all the components that are required in some linear circuits cannot be formed
are integrated on a same chip. Integrated circuits may be using the monolithic process. Moreover there is no method
classified as either monolithic or hybrid circuits and are available to fabricate transformers or to form large values
described as follows. of inductors in integrated circuit form. However, if these
In monolithic ICs, all transistors and passive ele- components are required in a given application, external
ments are fabricated on a single piece of semiconduc- discrete components can be used with the IC.
tor material, usually silicon. All these components are In hybrid ICs, passive components and the inter-
formed simultaneously by a diffusion process and then connections between them are formed on an insulating
a metallization process is used for interconnecting these substrate. The substrate is used as a chassis for the inte-
components to form the desired circuits. This is followed grated components. Active components such as transis-
by isolation process which ensures electrical isolation tors and diodes, as well as monolithic integrated circuits,
between the components in monolithic ICs. are then connected to form a complete circuit. For this
The monolithic process makes low cost mass pro- reason, low-volume production is best suited for hybrid
duction of ICs possible. Also, monolithic ICs exhibit IC technology.

254 Chapter 12: Device Technology
12.2 INTEGRATED CIRCUIT patterns to be produced. Opaque regions on the mask

FABRICATION PROCESS block the UV light. Regions of the photoresist exposed
to the light undergo a chemical reaction that varies with
the type of resist being employed. In negative resists, the
Integrated circuit fabrication process is a multiple-step areas where the light strikes become polymerized and
sequence of photolithographic and chemical processing more difficult to dissolve in solvents. When placed in
steps during which electronic circuits are gradually cre- a developer (solvent), the polymerized regions remain,
ated on a wafer made of pure semiconducting material. while the unexposed regions dissolve and wash away.
The most commonly used material is silicon; however, Positive resists contain a stabilizer that slows down the
for specialized applications various compound semicon- dissolution rate of the resist in a developer. This stabi-
ductors are used. The fabrication of integrated circuits lizer breaks down when exposed to light, leading to the
consists of the following steps: lithography, etching, preferential removal of the exposed regions. This is fol-
deposition, chemical mechanical polishing, oxidation, ion lowed by oxide removal. Buffered hydrofluoric acid (HF)
implantation and diffusion. may be used to dissolve unprotected regions of the oxide
film. Lastly, the photoresist is removed in a step called
The simple example of the device fabrication pro-
resist strip. This is accomplished by using a chemical
cess may include formation of a silicon dioxide (SiO2)
solution or by oxidizing or `burning the resist in oxygen
layer, its selective removal, introduction of dopant atoms
plasma or a UV ozone system called an asher.
into the wafer surface and dopant diffusion into silicon.
Combination of these and other fabrication steps can
produce complex devices and circuits. This step-by-step 12.2.2 Etching
and layer-upon-layer method of making circuits on a
wafer substrate is called planar technology Etching is used to remove material selectively in order
In the following paragraphs, different steps of IC to create patterns. The pattern is defined by the etching
fabrication are discussed. mask, because the parts of the material, which should
remain, are protected by the mask. The unmasked mate-
rial can be removed either by wet (chemical) or dry
12.2.1 Lithography (physical) etching. If SiO2 is removed with HF, this etch-
ing method is called wet etching. Wet etching is strongly
Lithography uses simple chemical processes to create an isotropic (meaning without preference in direction, and
image. There are different types of lithographic methods, proceeding laterally under the resist as well as vertically
depending on the radiation used for exposure: optical toward the silicon surface), which limits its application,
lithography (photolithography), electron beam lithog- and the etching time can be controlled with difficulty.
raphy, X-ray lithography and ion beam lithography. Because of the so-called under-etch effect, wet etching is
The most common method used is photolithography. not suited to transfer patterns with sub-micron feature
Photolithography is used to transfer a pattern from a size. However, wet etching has a high selectivity (the
photomask to the surface of the wafer using optical radi- etch rate strongly depends on the material) and it does
ation. In other words, it is used to selectively remove not damage the material. On the other side, dry etching
oxide from those areas in which dopant atoms are to be is highly anisotropic but less selective. In dry etching,
introduced. The top surface of the wafer is first coated also known as plasma etching or reactive-ion etching
with a UV light-sensitive material called photoresist. or RIE, the wafer with patterned resist is exposed to a
The photoresist changes its physical properties when plasma, which is an almost neutral mixture of energetic
exposed to light (often ultraviolet) or another source of molecules, ions, and electrons that is usually created by
illumination (e.g. X-ray). The photoresist is developed a radio-frequency (RF) electric field. Dry etching is more
either by (wet or dry) etching or by conversion to vola- capable for transferring small structures.
tile compounds through the exposure itself. The pattern
defined by the mask is either removed or remained after
development, depending if the type of resist is positive 12.2.3 Deposition
or negative.
Liquid photoresist is placed on the wafer, and the A multitude of layers of different materials have to be
wafer is spun at high speed to produce a thin, uniform deposited during the IC fabrication process. The two
coating. After spinning, a short bake at about 90C is most important deposition methods are the physical
performed to drive solvent out of the resist. The next vapour deposition (PVD) or sputtering and the chemical
step is to expose the resist through a photomask and vapour deposition (CVD).
a high-precision reduction lens system using UV light. During PVD, accelerated gas ions sputter par-
The photomask is a quartz photoplate containing the ticles from a sputter target in a low-pressure plasma

12.2 INTEGRATED CIRCUIT FABRICATION PROCESS 255
chamber. Sputtering is performed in a vacuum chamber. 12.2.5 Oxidation

The source material, called the sputtering target, and
the substrate holding the Si wafer form opposing par- Oxidation is a process which converts silicon on the
allel plates connected to a high-voltage power supply. wafer into SiO2. The chemical reaction of silicon and
During deposition, the chamber is first evacuated of oxygen already starts at room temperature but stops
air and then a low-pressure amount of sputtering gas after a very thin native oxide film is formed.
(typically Ar) is admitted into the chamber. Applying
SiO2 layers of precisely controlled thickness are pro-
an inter-electrode voltage ionizes the Ar gas and creates
duced during IC fabrication by reacting Si with either
plasma between the plates. The target is maintained at
oxygen gas or water vapour at an elevated temperature.
a negative potential relative to the substrate, and Ar
In either case, the oxidizing species diffuses through
ions are accelerated toward the sputtering target. The
the existing oxide. Growth of SiO2 using oxygen and
impacting Ar ions cause target atoms or molecules to
water vapour is referred to as dry and wet oxidation,
be ejected from the target. The ejected atoms or mol-
respectively. Dry oxidation is used to form thin oxide
ecules readily travel to the substrate, where they form
films. Wet oxidation, however, proceeds at a faster
the desired thin film. While sputtering is a relatively
rate and is therefore preferred in forming the thicker
simple and satisfactory way of depositing thin film over
oxides. Water vapour diffuses through SiO2 faster than
flat surfaces, it is directional and cannot deposit uni-
oxygen.
form films on the vertical walls of holes or steps in
the surface topography. This is called a step coverage SiO2 layers are used as high-quality insulators or
problem. masks for ion implantation. The ability of silicon to form
The principle of CVD is a chemical reaction of a gas high-quality SiO2 is an important reason why silicon is
mixture on the substrate surface at high temperatures. still the dominating material in IC fabrication.
The need of high temperatures is the most restricting
factor for applying CVD. This problem can be avoided
with plasma-enhanced chemical vapour deposition
(PECVD), where the chemical reaction is enhanced 12.2.6 Doping
with radio frequencies instead of high temperatures. An
important aspect for this technique is the uniformity of The density profile of the dopant atoms in the silicon
the deposited material, especially the layer thickness. (dopant profile) is generally determined in two steps.
CVD has a better uniformity than PVD. Also, CVD First, the dopant atoms are placed on or near the sur-
deposits a much more conformal film, which covers the face of the wafer by ion implantation, gas-source doping
vertical and horizontal surfaces with basically no differ- or solid-source diffusion. This step may be followed by
ence in the film thickness. an intentional or unintentional drive-in diffusion that
transports the dopant atoms further into the silicon
Epitaxy is a very special type of thin-film deposition
substrate.
technology. Whereas the deposition methods described
in the preceding section yield either amorphous or poly- Ion implantation is the dominant technique to intro-
crystalline films, epitaxy produces a crystalline layer over duce dopant impurities into crystalline silicon. It is the
a crystalline substrate. The film is an extension of the most important doping method because of the precise
underlying crystal. control it provides. This is performed with an electric
field which accelerates the ionized atoms or molecules
so that these particles penetrate into the target mate-
12.2.4 Chemical Mechanical Planarization rial until they come to rest because of interactions with
the silicon atoms. Ion implantation is able to control
Processes such as etching, deposition, or oxidation, exactly the distribution and dose of the dopants in
which modify the topography of the wafer surface lead silicon, because the penetration depth depends on the
to a non-planar surface. Chemical mechanical planariza- kinetic energy of the ions which is proportional to the
tion (CMP) is used to plane the wafer surface with electric field. The dopant dose can be controlled by vary-
the help of a chemical slurry. First, a planar surface is ing the ion source. Unfortunately, after ion implanta-
necessary for lithography for correct pattern transfer. tion, the crystal structure is damaged, which implies
CMP enables indirect patterning, because the material worse electrical properties. Another problem is that
removal always starts on the highest areas of the wafer the implanted dopants are electrically inactive, because
surface. This means that at defined lower-lying regions they are situated on interstitial sites. Therefore, after
like a trench the material can be left. Together with ion implantation, a thermal process step referred to as
the deposition of non-planar layers, CMP is an effective annealing is necessary which repairs the crystal damage
method to build up IC structures. and activates the dopants.

12.2.7 Diffusion After the photolithographic process is completed, the

remaining SiO2 is stripped off using HF and we have
After dopant introduction by implantation or gaseous bare wafer with N-well. This is followed by polysilicon
deposition, diffusion process is used to drive the dopant deposition process which deposits a very thin layer of
deeper into silicon. Diffusion is the movement of impurity gate oxide and then using chemical vapor deposition
atoms in a semiconductor material at high temperatures. process a layer of polysilicon is deposited. In this pro-
The driving force of diffusion is the concentration gradi- cess silane gas flows over the heated wafer coated with
ent. There is a wide range of diffusivities for the various SiO2 at a temperature of approx. 650oC. The resulting
dopant species, which depends on how easily the respec- reaction produces a non-crystaline or amorphous mate-
tive dopant impurity can move through the material. rial called polysilicon. The photolithography process
Diffusion is applied to anneal the crystal defects after ion is used to pattern polysilicon. The photolithographic
implantation or to introduce dopant atoms into silicon process is further carried on to diffuse N-type material.
from a chemical vapour source. In the last case, the diffu- N-diffusion forms NMOS source, drain, and N-well con-
sion time and temperature determine the depth of dopant tact. P-diffusion process is used to produce P-diffusion
penetration. Diffusion is used to form the source, drain, mask to form PMOS source, drain and substrate con-
and channel regions in a MOS transistor. But diffusion tacts. Contact cuts are formed by covering the chip
can also have an unwanted parasitic effect, because it with thick field oxide and etching it where contact cuts
takes place during all high-temperature process steps. are needed. Aluminum interconnect layers are deployed
using a process known as sputtering. Aluminium is
evaporated in vacuum with heat for evaporation deliv-
12.3 CMOS FABRICATION ered by electron-beam or ion-beam bombarding. Other
metal interconnects, such as copper, require different
deposition techniques. Description of these techniques is
One of the most popular MOSFET technologies available beyond the scope of the present text.
today is the complementary metal oxide semiconductor
or CMOS technology. The main advantage of CMOS
over NMOS and bipolar technology is the much smaller 12.3.2 P-Well CMOS Process
power dissipation. Unlike NMOS or bipolar circuits, a
CMOS circuit has almost no static power dissipation. The fabrication of P-well CMOS process is similar to
Power is only dissipated in case the circuit actually N-well process except that P-wells act as substrate for
switches. This allows integration of many more CMOS the N-devices within the parent N-substrate. N-well
gates on an IC than in NMOS or bipolar technology, CMOS are superior to P-well because of lower sub-
resulting in much better performance. In CMOS tech- strate bias effects on transistor threshold voltage,
nology, both N-type and P-type transistors are used to lower parasitic capacitances associated with source
realize logic functions. and drain region. In addition latch-up problems can
There are a number of approaches to CMOS fabrica- be considerably reduced by using a low resistivity
tion, including the P-well, the N-well and the twin tub epitaxial P-type substrate. However N-well process
processes. degrades the performance of poorly performing P-type
transistors.
12.3.1 N-Well CMOS Process
The N-well CMOS process starts with a moderately 12.3.3 Twin-Tub Process
doped (with impurity concentration around 2 1021
impurities/m3) P-type silicon substrate. This is followed A combination of P-well and N-well process is the
by photolithographic process, in which oxidation is used twin-tub process. Here we start with a substrate of
to deposit a thin layer of SiO2 over the complete wafer high resistivity N-type material and then create both
by exposing it to high-purity oxygen and hydrogen at N-well and P-well regions. It is possible to preserve the
approx. 1000C. This is followed by application of photo- performance of N-type transistors without compromis
resist coating, masking, removal of photoresist material, ing the P-type transistors. In general, the Twin-tub
acid etching and fabrication of N-well. N-well is formed process allows separate optimization of the N-type and
either by diffusion or ion implantation. P-type transistors

SOLVED EXAMPLES
1. Oxidation is used for (c) NPN construction permits higher packing of

(a) interconnection (b) doping elements
(c) isolation (d) material removal (d) P-type base is preferred
Ans. (c) Ans. (b)
2. Which of the following is most difficult to fabricate 4. ICs are generally made of _________
in an IC?
(a) silicon (b) germanium
(a) Diode (b) Transistor (c) copper (d) None of the above
(c) FET (d) Capacitor Ans. (a)
Ans. (d)
5. Packaging is used for
3. In integrated circuits, NPN construction is pre-
(a) protection
ferred to PNP construction because
(b) safety
(a) NPN construction is cheaper (c) both protection and safety
(b) to reduce diffusion constant, N-type collector (d) None of the above
is preferred Ans. (c)
PRACTICE EXERCISE
1. Which of the following cannot be fabricated on (c) cleaning the surface

anIC? (d) None of the above
(a) Transistors 6. Optical masking is used for
(b) Diodes
(a) pattern transfer
(c) Resistors
(b) protection
(d) Large inductors and transformers
(c) cleaning
2. The various circuit functions in a monolithic IC are (d) None of the above
insulated from each other by
7. Etching is used for
(a) vacuum (b) isolation diffusion
(c) thermoplastic layers (d) All of the above (a) selective removal of the unwanted surface
(b) cleaning
3. The SiO2 layer in an IC acts as _________ (c) interconnection
(a) a resistor (b) an insulating layer (d) None of the above
(c) mechanical output (d) None of the above 8. Monolithic IC comprises of
4. The basic process used to make monolithic inte- (a) active components
grated circuit is referred to as (b) passive components
(a) photolithography (b) junction diffusion (c) both active and passive components
(c) wafer growth (d) zone refining (d) None of these
5. Doping means 9. In monolithic IC

(a) addition of impurity material in semiconductor (a) performance depends on the substrate
band structure (b) performance depends on the interconnects
(b) removing of impurity material in semiconduc- (c) performance depends upon packaging
tor band structure (d) None of the above

1. (d) 4. (a) 7. (a)

2. (b) 5. (a) 8. (c)
3. (b) 6. (a) 9. (a)
1. If P is passivation, Q is N-well implant, R is metal- Solution. To achieve high-quality oxide growth

lization and S is source/drain diffusion, then the (i.e. a uniform film with good dielectric properties),
order in which they are carried out in a standard dry oxidation alone is employed. Hence when gate
N-well CMOS fabrication process is oxide is grown, dry oxidation process is used.
Wet oxidation is used to grow field oxide
(a) P-Q-R-S (b) Q-S-R-P
because the quality of the dielectric properties of
(c) R-P-S-Q (d) S-R-Q-P
the field oxide is not as critical as they are for the
gate oxide. Dry oxidation is slower than the wet
Ans. (b)
oxidation.
2. A silicon wafer has 100 nm of oxide on it and Ans. (b)
is inserted in a furnace at a temperature above
1000C for further oxidation in dry oxygen. The 4. In IC technology, dry oxidation (using dry oxygen)
oxidation rate as compared to wet oxidation (using stem or water
vapour) produces
(a) is independent of current oxide thickness and
temperature (a) superior quality oxide with a higher growth
(b) is independent of current oxide thickness but rate
depends on temperature (b) inferior quality oxide with a higher growth
(c) slows down as the oxide grows rate
(d) is zero as the existing oxide prevents further (c) inferior quality oxide with a lower growth
oxidation rate
(GATE 2008: 1 Mark) (d) superior quality oxide with a lower growth
Ans. (d) rate
(GATE 2013: 1 Mark)
3. Thin gate oxide in a CMOS process is preferably
grown using
Solution. To achieve high-quality oxide growth,
(a) wet oxidation (b) dry oxidation dry oxidation alone is employed. However, dry
(c) epitaxial deposition (d) ion implantation oxidation is slower than the wet oxidation.

PART III: ANALOG CIRCUITS
12
10
Number of Questions
8
Marks 1
6
Marks 2
4
0
2015 2014 2013 2012 2011 2010 2009

260 Part III: ANALOG CIRCUITS
Year Topic
2015 Simple diode circuits
BJTs
Function generators and wave-shaping circuits
Filters
Rectifier
Clamping
Negative feedback
Simple opamp circuits
Sinusoidal oscillators; Criterion for oscillation
Single-transistor and opamp configurations
FET amplifiers
2014 Biasing and bias stability of transistor
Small signal equivalent circuits of BJTs
Simple diode circuits
Amplifiers: single stage and multi-stage
FET amplifiers
Differential amplifier
Feedback amplifier
Clipping, clamping
Filters
Rectifier
2013 Small signal equivalent circuits of BJTs
Small signal equivalent circuits of MOSFETs
Small signal equivalent circuits of analog CMOS
Simple diode circuits
Feedback amplifier
Filters
2011 Small signal equivalent circuits of diodes
Filters
2010 Biasing and bias stability of transisitor
FET amplifiers
BJT amplifier
Frequency response of amplifiers
opamp configuration
Function generators and wave-shaping circuits
Feedback amplifier
555 Timers

CHAPTER 13
SMALL SIGNAL EQUIVALENT CIRCUITS
An equivalent circuit of a device is a combination of elements suitably connected so as to best represent the actual
terminal characteristics of the device. In this chapter, we will study the small signal equivalent circuit of diodes, BJTs,
MOSFETs and analog CMOS.
13.1 DIODES
VB rd Ideal
The most accurate equivalent circuit model for a diode diode
is the piecewise linear equivalent circuit model in which
the diode curves are represented by straight-line seg- ID(mA)
ments. The model is shown in Fig. 13.1. The slope is
equal to inverse of the value of the dynamic resistance,
1/rd. The typical value of rd is 1520 for silicon and
germanium diodes. The model is equally valid for both Piecewise
DC as well as AC applications. linear model
Two more simplified models are shown in Figs. 13.2
and 13.3, respectively. An ideal diode is the most simple VD(V)
VB
equivalent diode model.
Figure 13.1| Piecewise linear equivalent circuit model

of a diode.

262 Chapter 13: Small Signal Equivalent Circuits
13.2 h-PARAMETER MODEL FOR

BJTs
VB Ideal
diode
The h-parameter model is widely used for bipolar junc-
ID(mA) tion transistors at low frequencies and the value of
h-parameters depends upon the operating point, the
operating temperature and the frequency of operation.
13.2.1 h-Parameter Model for the Common-

Emitter BJT Configuration
Figure 13.5 shows the h-parameter equivalent model for

a BJT in the common-emitter configuration.
VD(V)
VB B C
Figure 13.2| Simplified equivalent circuit model of a + hie Ib Ic
+
diode. +
Vbe hreVce hfe Ib hoe Vce
Rs

Ideal
diode
E Ie
ID(mA)
Figure 13.5| h-parameter model for common-emitter
BJT configuration.
A The h-parameter equations for the common-emitter con-

1/Rs figuration are given as
Vbe = hie I b + hre Vce (13.1)

I c = hfe I b + hoe Vce (13.2)
VD(V)
where hie is the input impedance, hfe is the forward cur-
Figure 13.3| Another simplified equivalent circuit
rent transfer ratio, hre is the reverse voltage transfer
ratio and hoe is the output admittance. The values of the
model of a diode.
parameters hie, hfe, hre and hoe are given by the following
set of equations, respectively.
Figure 13.4 shows the V-I characteristics of an ideal diode.
vbe Dvbe
hie = =
ib Dib
(13.3)
ID(mA) V ce = const. V ce = const.
vbe Dvbe
hre = =
vce Dvce
(13.4)
I b = const. I b = const.
ic Dic
hfe = =
ib Dib
(13.5)
V ce = const. V ce = const.
VD(V) ic Dic
hoe = =
vce Dvce
(13.6)
Figure 13.4| V-I characteristics of an ideal diode. I b = const. I b = const.

13.2H-PARAMETER MODEL FOR BJTS 263
Figure 13.6 shows the simplified h-parameter model 13.2.2 h-Parameter Model for the Common-
for the common-emitter BJT configuration. Here, hre Collector BJT Configuration
is assumed to be zero, therefore the magnitude of the
voltage source hreVce is also equal to zero. In other Figures 13.7(a) and (b), respectively, show the complete
words, it results in short-circuit equivalent for the h-parameter model and simplified h-parameter model of
feedback element. In the cases where the value of the common-collector BJT configuration. The h-parameter
1/hoe is very large as compared to the value of load equations for the common-collector BJT configuration
resistance, it is assumed to be open in comparison with are given by
the parallel load to be connected across the output
Vbc = hic I b + hrc V ec (13.7)
terminals.
I e = hfc I b + hoc Vec (13.8)
Ic
B C
13.2.3 h-Parameter Model for the Common-Base
+ +
hie Ib BJT Configuration
Figures 13.8(a) and (b), respectively, show the complete

Vbe hfeIb hoe Vce
h-parameter model and the simplified h-parameter model
for the common-base BJT configuration. The h-parame-
ter equations for the common-base BJT configuration are

given by
E Ie
Veb = hib I e + hrb Vcb (13.9)
Figure 13.6| Simplified h-parameter model for I c = hfb I e + hob Vcb (13.10)
common-emitter BJT configuration.
B E B E
+ + Ie +
hic Ib Ie + hic Ib
+
Vbc hrcVec hfc Ib hoc Vec Vbc hfcIb hoc Vec

C Ic C Ic
(a) (b)
Figure 13.7| (a) h-parameter model and (b) simplified h-parameter model for common-collector BJT
configuration.
E C E C
+ hib Ie + + hib +
Ic Ie Ic
+
Veb hrbVcb hfbIe hob Vcb Veb hfbIe hob Vcb

B Ib B Ib
(a) (b)
Figure 13.8| (a) h-parameter model and (b) simplified h-parameter model for common-base BJT
configuration.

Table 13.1| Approximate conversion formulas for the h-parameters for different BJT configurations.
hic = hie hrc = 1 hfc = (1 + hfe) hoc = hoe
hie hie hoe hfe hoe

hib = hrb = hre hfb = hob =
1 + hfe 1 + hfe 1 + hfe 1 + hfe
hib hib hob hfb hob

hie = hre = hrb hfe = hoe =
1 + hfb 1 + hfb 1 + hfb 1 + hfb
hib 1 hob
hic = hrc = 1 hfc = hoc =
1 + hfb 1 + hfb 1 + hfb
Table 13.2| Typical values of h-parameters for different BJT configurations.
Parameter Common Emitter Common Collector Common Base

hi 16.5 k 16.5 k 2030
hr (1.5 104)(2.5 104) 1 (0.1 104)(3 104)
hf 50250 (50)(250) 1
ho 525 mho 525 mho 0.020.5 mho
Table 13.1 gives the approximate conversion formulae The value of ro is given by
for the h-parameters for the different BJT configurations Vce
and Table 13.2 gives their typical values. ro = (13.11)
I e
The value of re is given by
13.3 re TRANSISTOR MODEL
26 mV
re = (13.12)
Ie
In this section, the re model for the three BJT configu- The typical value of re is in the range of few ohms to 50
rations is discussed. and that of ro is in the range of 4050 k.
13.3.1 re Model for Common-Emitter BJT 13.3.2 re Model for Common-Base BJT
Configuration Configuration
Figure 13.9 shows the re model for the common emitter Figure 13.10 shows the re model for the common-base
BJT configuration. configuration. The output impedance is in the range of
few 100s of kilo-ohms up to mega-ohm range.
B Ib C E Ib C
re Ib ro re aIe
E B
Figure 13.9| re model for common-emitter BJT Figure 13.10| re model for common-base BJT
configuration. configuration.

13.4 EQUIVALENT MODEL OF FETS 265
13.3.3 re Model for Common-Collector BJT The parameters gm, rd and are related by Eq. (3.18):
m = rd gm
Configuration
(13.18)
The model for common-emitter BJT configuration is The low-frequency model of an FET is shown in Fig
applicable to the common-collector BJT configuration. 13.11. As we can see from the figure, it has a Nortons
equivalent output circuit with a voltage-dependent cur-
13.4 EQUIVALENT MODEL OF FETs rent source whose current output is proportional to
the gate-source voltage (Vgs). Also, the input imped-
ance between the gate and the source terminals is
The linear small-signal model for FETs can be obtained infinite because it is assumed that there is no current
on similar lines as that for BJTs. The expression for the flowing through the reverse-biased gate terminal. The
drain current is given by above model is applicable for both JFETs as well as
id id MOSFETs.
I d = Vgs + V ds (13.13)
vgs vds V gs = const.
V ds = const.
The parameter gm is defined as the trans-conductance or G D
+ +
the mutual conductance and is given by Id
id
gm = (13.14) Vgs gmVgs rd Vds
vgs
V ds = const.
It is also designated as yfs or gfs and is also referred to as
forward trans-admittance. The second important param- S S
Figure 13.11| Low-frequency model of an FET.
eter used to define the operation of FETs is the drain
resistance designated as rd. It is defined by Eq. (13.15).
The reciprocal of drain resistance rd is referred to as the
drain conductance (designated as gd). It is also known as
When we compare this model of the FET with that of
output conductance and is also denoted as yos.
the BJT, we find that there are a few major differences.
v First, the value of the current generated by the output
rd = ds (13.15)
id V = const. current source in the case of an FET depends on the input
gs
voltage whereas in the case of a BJT it depends upon the
Therefore,
input current. Second, in the case of an FET, there is
1 no feedback from the output to the input whereas in the
I d = gm Vgs + V (13.16)
rd ds case of a BJT there is feedback between the output and
the input circuits through the parameter hre. Lastly, the
The amplification factor of an FET is defined as
input impedance of an FET is much larger than that of
follows:
v a BJT. In nutshell, FET is more closer to being an ideal
m = ds (13.17) amplifier than a BJT at low frequencies.
vgs
I d = const.
IMPORTANT FORMULAS
26 mV ic ic
1. For a BJT, re = hfe = =
Ie ib ib
V ce = const. V ce = const.
2. For a BJT:
ic ic
hoe = =
vbe vbe vce I b = const.
vce I b = const.
hie = =
ib V ce = const.
ib V ce = const.
3. For a FET:
v v
hre = be = be id
vce I b = const.
vce I b = const. gm =
vgs
V ds = const.

vds 4. For a FET, q = rd gm

rd =
id V gs = const. 5. Formulas in Tables 13.1 and 13.2.
vds
m=
vgs
I d = const.
SOLVED EXAMPLES
1. The following figure shows a diode circuit along Vo(t)

with the input waveform.
Vd(t) 0
10 20 t(ms)
(b)
Diode
RL 8.0
Vi(t) 1 k Vo(t) Vo(t)
(c) 10 20 t(ms)
Vi(t) 8.0
8.0 V Vo(t)
8.0
(d)
0
10 20 t(ms)
(b)
10 20 t(ms)
8.0 V Solution. An ideal diode acts as a short circuit in

the forward-biased region and acts as an open cir-
The waveform for the output voltage Vo(t) is cuit in the reverse-biased region. During the posi-
(assume the diode to be ideal) tive half of the input waveform, the diode acts as
a short circuit and the whole waveform appears
(a) Figure (a) (b) Figure (b) across the load resistance (RL). The negative half
(c) Figure (c) (d) Figure (d) of the input waveform is blocked by the diode and
does not appear across RL.
Ans. (a)
Vo(t)
2. For a common-base BJT configuration having
8.0 Ie = 5 mA and = 0.97, an AC signal of 5 mV
(a) is applied between the base and the emitter
terminals. What is the input impedance?
(a) 5.2 (b) 6
10 20 t(ms) (c) 4.9 (d) 5.7

SOLVED EXAMPLES 267
Solution. The input impedance is Ib
26 mV B C
re = Re
I e mA) AeIb
26 103
=
5 103

= 5.2
E
Ans. (a) (a)
3. For the common-base configuration discussed in
Ie
Question 2, what is the value of voltage gain for a
load of 1 k? E C
Rb
(a) 196 (b) 186.54 AbIe
(c) 175.6 (d) 256.67
B
(b)
Solution. Input current Ii for an input voltage
(Vi) of 5 mV is Given that Re = 2 k and Ae = 100, the values of
3 Rb and Ab are given by
Vi 5 10
Ii = = A
Zi 5. 2 (a) 2 k and 0.99 (b) 200 and 0.99
= 961.54 A (c) 2 k and 100 (d) 20 and 0.99
Vo = I c RL = aI e RL Solution. We know that
= 0.97 961.54 10 6 1 103 Re = hie and Ae = hfe
= 932.7 mV Rb = hib and Ab = hfb
Vo 932.7 10 3 hib =
hie
Av = =
Vi 5 10 3 1 + hfe
Therefore,
= 186.54
2 103
Ans. (b) Rb = hib = 20
1 + 100
4. For the common-base configuration discussed in hfe
Question 2, what is the value of output impedance hfb =
and current gain? 1 + hfe
100
(a) 0, 0.97 (b) , 0.97 Ab = hfb = = 0.99
(c) , 0.97 (d) 0, 0.97 1 + 100 Ans. (d)
6. The current gain of a BJT is
Solution. The output impedance Zo and the
current gain is = 0.97. (a) gm ro (b) gm ro
Ans. (c)
(c) gm rp (d) gm rp
5. The following figures (a) and (b) show the simple
equivalent circuits for a common-emitter and com- Solution. The current gain of a BJT is
mon-base BJT configurations, respectively. hfe = gm rp
Ans. (c)
1. Find the value of hie in ohms for a BJT with Ic = 3 mA where V = kT/q = 25 mV; hfe =150 and Ic = 3 mA.
at room temperature for which kT/q = 25 mV and Therefore,
hfe = 150.
150 25 10 3
Solution. We know that hie =
3 103
V
hie = hfe = 1250
Ic Ans. (1250)

PRACTICE EXERCISE
1. The hybrid equivalent circuit of a transistor has 6. Increase in the value of transistors hfe parameter
results in
(a) Thevenins equivalent circuit at the input and
Nortons equivalent circuit at the output (a) d ecrease in the value of input impedance and
(b) Thevenins equivalent circuit at the input as increase in the value of current gain
well as the output (b) decrease in the values of both the input imped-
(c) Nortons equivalent circuit at the input and ance and the current gain
Thevenins equivalent circuit at the output (c) increase in the values of both the input imped-
(d) None of these ance and the current gain
(1 Mark) (d) increase in the value of input impedance and
decrease in the value of current gain
2. For the following statements, choose the correct
(1 Mark)
answer.
7. Which of the following statement(s) is/are true?
S1: The amplification factor (hfe) is most sensitive
to changes in collector current, whereas output S1: In the case of an FET, there is no feedback
impedance parameter is least sensitive. from the output to the input whereas in the case
S2: Current gain of an amplifier is independent of a BJT there is feedback between the output and
of the input impedance of the amplifier and the the input circuits through the parameter hre.
applied load. S2: In the case of a BJT, there is no feedback from
(a) Both S1 and S2 (b) Only S1 the output to the input whereas in the case of an
(c) Only S2 (d) None FET there is feedback between the output and
(1 Mark) input circuits through the parameter gm.
S3: BJT is a more ideal amplifier as compared to
3. Power gain is maximum in CE configuration
an FET.
whereas it does not have the maximum voltage
gain nor the maximum current gain. Why? S4: FET is a more ideal amplifier as compared to
a BJT.
(a) Because it has both the voltage gain and cur-
rent gain greater than unity. (a) Both S1 and S4 (b) Both S2 and S3
(b) It is its inherent characteristic. (c) Both S1 and S3 (d) Both S2 and S4
(c) It has a very large transimpedance gain (1 Mark)
(d) It has a very large transconductance gain
8. Input and output from a common-base amplifier
(1 Mark)
are fed to an oscilloscope to see their phase rela-
4. The parameter hoe can be determined by tionship. The Lissajous figure is
(a) taking the slope of the output characteristic (a) a straight line (b) an ellipse
curve at the operating point (c) an oblique ellipse (d) a circle
(b) taking the slope of the input characteristic (1 Mark)
curve at the operating point
9. In which of the following transistor configurations,
(c) cannot be determined using the input and
is the input impedance least dependent on the load
output characteristic curves
resistance?
(d) by taking the collector current increment for a
fixed value of collector-emitter voltage (a) Common-emitter configuration
(b) Common-base configuration
(1 Mark)
(c) Common-collector configuration
5. What is the unit of the output conductance (d) Common-emitter with unbypassed emitter
parameter? resistance
(1 Mark)
(a) Ohms (b) It is dimensionless
(c) Mhos (d Ampere 10. The most accurate equivalent circuit model for a
(1 Mark) diode is

(a) piecewise linear equivalent circuit model 1 1

(b) h-parameter model (c) R s + (d)
hoe hoe
(c) Nortons equivalent model
(d) -model (2 Marks)
(1 Mark) 14. Given that the hybrid parameters for the transis-
11. Consider the following statements: tor are hie = 1.5 k, hfe = 150, hre = 1 104 and
hoe = 20 mhos. The values of h-parameters for the
S1: Current gain of an amplifier is independent of common-collector configuration are
the input and the load impedances
S2: BJT's hfe is most sensitive to changes in the (a) hic = 1.5 k, hrc = 1, hfc = 151 and hoc = 20
collector current and hoe is the least sensitive to mhos
changes in the collector current (b) hic = 2.5 k, hrc = 1, hfc = 151 and hoc = 20
mhos
(a) Both S1 and S2 are False
(b) Both S1 and S2 are True (c) hic = 1.5 k, hrc = 1, hfc = 151 and hoc = 10
(c) S1 is True, S2 is False mhos
(d) S1 is False, S2 is True (d) hic = 1.5 k, hrc = 2, hfc = 152 and hoc = 20
(1 Mark) mhos
(2 Marks)
12. The h-parameter equivalent circuit of a BJT is
valid for 15. For the hybrid parameters for the transistor dis-
cussed in Question 14, which of the following state-
(a) large signal operation at low frequency
ments represent the correct values of h-parameters
(b) large signal operation at high frequency
for the common-base configuration?
(c) small signal operation at high frequency
(d) small signal operation at low frequency (a) hib = 15 , hrb = 0.99 104, hfb = 0.99 and
(1 Mark) hob = 20 mhos
(b) hib = 9.93 , hrb = 0.99 103, hfb = 151
13. If Rs is the source resistance, the output resistance
and hob = 13 mhos
(c) hib = 9.93 , hrb = 0.99 104, hfb = 0.99
of an emitter-follower using the simplified hybrid
model would be
and hob = 0.13 mhos
hie + Rs hie + Rs (d) hib = 19.93 k, hrb = 0.99 104, hfb = 0.99
(a) (b) and hob = 1.3 mhos
1 + hfe h fe
(2 Marks)
1. If hib = 25 , hfb = 0.99, then find hie in ohms. ID(mA)
(1 Mark) 20
2. Figures (a) and (b) shown in Multiple Choice
Question 5 show the simple equivalent circuits for 15 A
common-emitter and common-base BJT configura- Voltage differential between
tions, respectively. If Re = 2 k and Ae = 100, find points A and B = 50 mV
10 B
the value of Rb.
(1 Mark) 5
3. Find the value of Ab for the case discussed in
Question 2. 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VD(V)
(1 Mark) (1 Mark)
4. The piecewise linear equivalent circuit model for 5. Find the forward resistance of the diode (in ohms)
the diode shown in the following figure. Find the discussed in Question 4.
cut-in voltage (in mV). (1 Mark)

1. (a) 2. (d) 3. (a) 15. (c) The conversion formulas of h-parameters from
common-emitter to common-base configuration are
4. (a) 5. (c) 6. (c)
given as follows:
7. (a) 8. (a) 9. (b)
hie h h
10. (a) 11. (a) 12. (d) hib = ; hrb = ie oe hre ;
1 + hfe 1 + hfe
13. (a)
hfe hoe
hfb = ; hob =
14. (a) The conversion formulas of h-parameters from 1 + hfe 1 + hfe
common-emitter to common-collector configura-
tion are given as follows:
Substituting the values of hie = 1.5 k, hfe = 150,
hic = hie ; hrc = 1; hfc = (1 + h fe ); hoc = hoe hre = 1 104 and hoe = 20 mhos in the above
Substituting the values of hie = 1.5 k, hfe = 150, formulas, we get
hre = 1 104 and hoe = 20 mhos in the above hib = 9.93 ; hrb = 0.99 104; hfb = 0.99
formulas, we get and hob = 0.13 mhos
hic = 1.5 k; hrc = 1; hfc = 151; hoc = 20 mho
1. We know that 3. We know that

hib
hie = hfe
1 + hfb hfb =
1 + hfe
Therefore,
25 Therefore,
hie = = 2500
1 0.99
Ans. (2500) 100
Ab = hfb = = 0.99 or 1
2. We know that 1 + 100
Re = hie and Ae = hfe
Ans. (0.99, 1)
Rb = hib and Ab = hfb 4. From the given figure, we can see that the cut-in
hie voltage is 0.8 V 800 mV.
hib =
1 + hfe Ans. (800)
5. The forward resistance is
Therefore,
2 103 V A VB 50 mV
Rb = hib = 20 rf = = = 10
1 + 100 I A IB 5 mA
Ans. (20)
Ans. (10)
1. The action of a JFET in its equivalent circuit can be (c) voltage-controlled voltage source
best represented as a (d) voltage-controlled current source
(a) current-controlled current source (GATE 2003: 2 Marks)
(b) current-controlled voltage source Ans. (d)

2. For an NPN transistor connected as shown in the fol- Therefore, IE IC = 1.3 mA. The value of
lowing figure, VBE = 0.7 V. Given that reverse satu- saturation collector-emitter voltage of a transistor
ration current of the junction at room temperature VCE(sat) is approximately 0.2 V. Therefore,
300 K is 1013 A, the emitter current is (h =1)
10 0.2
IC(sat) = 3
A = 0.9 mA
1 10 + 10 10
3
IC
Since IC > IC(sat), the transistor is in saturation.
Ans. (b)
Statement for Linked Answer Questions
4 and 5: In the circuit shown in the following
figure, assume that the voltage drop across a
VBE forward-biased diode is 0.7 V. The thermal volt-
age VT = kT q = 25 mV . The small signal input
ui = Vp cos (wt), where Vp = 100 mV.
(a) 30 mA (b) 39 mA
(c) 49 mA (d) 20 mA
(GATE 2005: 2 Marks) 9900
+
Solution. The transistor acts as a diode when its
two terminals are shorted. IC = IB IE. Therefore,
1)
VBE /hV T
I E = I o (e +

12.7 V
Given that, VBE = 0.7 V, Io = 1013 A, VT at IDC + iac VDC + vac
300K= 26 mV and h =1.
Therefore, vi
3
I E = 1013 [e0.7 /12610 1]
= 49 mA
Ans. (c)
3. For the BJT circuit shown in the following figure,
assume that the b of the transistor is very large
4. The bias current IDC through the diodes is
and VBE = 0.7 V. The mode of operation of the
BJT is (a) 1 mA (b) 1.28 mA
10 k (c) 1.5 mA (d) 2 mA
Solution. For DC biasing, the AC source is

+
10 V
considered as a short circuit. Therefore, the DC
+ voltage across the diodes is
2V 1 k 4 0.7 V = 2.8 V
The DC current is
12.7 2.8
(a) cut-off (b) saturation A = 1mA
(c) normal active (d) reverse active 9900
Ans. (a)
5. The AC output voltage Vac is
Solution. Since b is large, IB 0 and IC IE.
Applying Kirchhoffs voltage law in the base- (a) 0.25 cos (wt)mV (b) 1cos (wt)mV
emitter loop, we get (c) 2 cos (wt)mV (d) 22 cos (wt)mV
2 0.7 = 1 103 IE (GATE 2011: 2 Marks)

Solution. The diode is replaced by its dynamic Solution. The capacitor C1 will trap the negative
resistance for the AC analysis. peak voltage of the input signal (which is 1 V in
this case). Therefore, the voltage across diode D1
hV T will be cos (wt) 1.
rd =
I Ans. (a)
where = 1, VT = 25 mV and I = 1 mA. Therefore, 7. The current Ib through the base of a silicon NPN
rd = 25 . The AC voltage across the diodes is transistor is 1 + 0.1 cos (10000pt) mA. At 300 K,
the r in the small signal model of the transistor
vi v shown in the following figure.
100 = i
9900 + 100 100
V p cos wt Ib
= B C
100
100 cos wt
= mV
100
rp ro
= 1 cos (wt) mV
Ans. (b)
6. The diodes and capacitors of the circuit shown

in the following figure are ideal. The voltage v(t) E
across diode D1 is
C1 D2 (a) 250 (b) 27.5

(c) 25 (d) 22.5
v(t)
(GATE 2012: 1 Mark)
+
D1 Solution.
cos(t) C2
VT V
r = (b + 1)re = (b + 1) = T
Ie Ib
where Ib is the DC current through the base terminal.

Given that, Ib = 1 mA. Also, VT = 25 mV at room
temperature. Therefore,
(a) cos (wt) 1 (b) sin (wt)
25 103
(c) 1 cos (wt) (d) 1 sin (wt) r = = 25
1 103

CHAPTER 14
SIMPLE DIODE CIRCUITS
This chapter discusses simple diode circuits including connecting diodes in series and parallel, clippers, clampers, recti-
fiers, voltage multipliers and voltage regulator circuits.
14.1 CONNECTING DIODES IN available in a single diode. The parallel connected diodes
SERIES must have closely matched forward characteristics lest
they will not have equal division of current. An equal
division of forward current can be forced by using series
Semiconductor junction diodes are connected in series resistors (Fig. 14.2) or balancing inductors with each
to enhance the peak inverse voltage rating beyond what of the parallel connected diodes. The value of resistors
is available in a single diode. In order to ensure that (R) used should be much larger than the forward-biased
there is equal division of reverse voltage across the indi- resistance of the individual diodes.
vidual diodes, the diodes should have closely matched
reverse-biased characteristics. Equal division of reverse
voltage can however be forced by connecting series RC R C R C R C R C
networks across individual diodes (Fig. 14.1). The value
of the resistors (R) used should be much smaller than V/4 V/4 V/4 V/4
the reverse-biased resistance of the individual diodes.
14.2 CONNECTING DIODES IN

PARALLEL D1 D2 D3 D4
+
V
Semiconductor diodes are connected in parallel to
enhance the forward current capability beyond what is Figure 14.1| Diodes in series.

274 Chapter 14: Simple Diode Circuits
D1 14.3 CLIPPING CIRCUITS

R
I/4
D2 The simple series clipper circuits are shown in Figs. 14.3(a)
R
and (b). Biased series clippers are shown in Figs. 14.3(c) to (f).
I/4 Simple parallel clipper circuits are shown in Figs. 14.4(a) and
D3 (b) and biased parallel clippers are shown in Figs. 14.4(c)
R
to (f). In all these figures, the diode is assumed to be ideal.
I/4 The waveforms for clipping circuits of Figs. 14.3(a) and
D4
R (b) and Figs. 14.4(a) and (b) are shown in Figs. 14.5(a),
(b), (c) and (d), respectively, in case the diodes are non-
ideal. Resistance (R) is chosen so that Rf << R << Rr,
I/4
I
+ where, Rf is the forward biased resistance of the diode and
V Rr is the reverse biased resistance of the diode. The opti-
Figure 14.2| Diodes in parallel.
mum value of R is given by geometric mean of Rf and Rr.
R = Rf Rr (14.1)
Vi Vi
Vm Vm
t t
D
Vm D Vm
Vi R Vo Vi R Vo
Vo Vo
Vm
t
Vm
t
(a) (b)
Vi Vi
Vm Vm
t t
V D Vm V D Vm
Vi R Vo Vi R Vo
Vo VmV Vo Vm+V
t V
t
(c) (d)
Vi Vi
Vm Vm
t t
V D Vm V D Vm
Vi R Vo Vi R Vo
Vo Vo
t
V t
(Vm+V) (VmV)
(e) (f)
Figure 14.3| (a) and (b) Simple series clippers; (c), (d), (e) and (f) Biased series clippers.

14.3 CLIPPING CIRCUITS 275
Vi Vi
Vm Vm
t t
R R
Vm Vm
Vi D Vo Vi D Vo
Vo Vo
Vm
t
t
Vm
(a) (b)
Vi Vi
Vm Vm
t t
R R
Vm Vm
Vi D Vo Vi D Vo
Vo Vo
V V V t
t V
Vm
Vm
(c) (d)
Vi Vi
Vm Vm
t t
R R
Vm Vm
Vi D Vo Vi D Vo
Vo Vo
V Vm V Vm
V
t t
V
(e) (f)
Figure 14.4| (a) and (b) Simple parallel clippers; (c), (d), (e) and (f) Biased parallel clippers.

Vi 14.4 CLAMPING CIRCUITS

Vm
0.7 V The clamping circuits are used to clamp either positive or

t
negative extremities of an AC signal to zero. They do not
Vo alter the wave shape and only change the DC level. Figures
14.6(a) and (b) show the negative and the positive clam-
Vm 0.7 per circuits, respectively. The negative clamper clamps the
positive peaks of the AC signal to zero whereas a positive
t clamper clamps the negative peaks to zero. The optimum
value of R is given by geometric mean of Rf and Rr. That is,
(a) R = Rf Rr (14.2)
+
Vi
C
Vi R D Vo
t
0.7 V
Vm Vi
Vo +Vm
t
t
Vm
(Vm 0.7)
Vo t
(b)
Vm
Vi
2Vm
(a)
0.7 V t +
Vm C
R D
Vo Vi Vo
t
0.7 V Vi
Vm +Vm
(c) t
Vm
Vi
Vm Vo
+2Vm
t +Vm
0.7 V
t
Vo
(b)
Vm
Figure 14.6| (a) Negative clamper circuit. (b) Positive
0.7 V
t clamper circuit.
The clamping circuit will function even in the absence
of R if the peak input amplitude remains constant.
(d) Figures 14.7(a) and (b) show the biased negative clam-
Figure 14.5| Clipper circuit waveforms.
per circuits and Fig. 14.7(c) and (d) show the biased
positive clamper circuits.

14.4 CLAMPING CIRCUITS 277
Vi
+Vm
+ t
C Vm
D
Vi R Vo Vo
V +V
t
Vm+V
2Vm+V
(a)
Vi
+Vm
+ t
C Vm
D
Vi R Vo Vo
t
V V
VmV
2VmV
(b)
Vi
+Vm
+ t
C Vm
D
Vi R Vo Vo
V +2Vm+V
+Vm+V
+V
t
(c)
Vi
+Vm
+ t
C Vm
D
Vi R Vo Vo
V +2VmV
+VmV
t
V
(d)
Figure 14.7| (a) and (b) Biased negative clampers. (c) and (d) Biased positive clampers.

14.5 RECTIFIER CIRCUITS the rectifier circuit. It decides the PIV rating of the
diode to be used in the rectifier circuit.
The purpose of a rectifier circuit is to convert the AC voltage 14.5.2 Types of Rectifiers
appearing across the transformer secondary into a unidirec-
tional voltage. There are three basic rectifier circuit configura- There are three types of rectifiers, namely, (1) half-wave
tions. These include (a) half-wave rectifier, (b) conventional rectifier, (2) full-wave rectifier and (3) bridge rectifier.
two-diode full-wave rectifier and (c) bridge rectifier.
14.5.2.1Half-Wave Rectifier
14.5.1 Characteristic Parameters Figures 14.8(a) and (b) show the half-wave rectifier circuits
for positive and negative output voltages, respectively.
14.5.1.1Ripple Frequency
The ripple frequency is the frequency of the unidirec- D1

tional periodic voltage waveform present at the output of +
the rectifier circuit. Higher ripple frequency means lower AC input
Vi(t) RL Vo(t)

ripple factor and less stringent filtering requirement.
14.5.1.2Ripple Factor
The ripple factor (r) is expressed as follows: Vi(t) Vo(t)

Vr(RMS) I r(RMS)
r= = (14.3)
VDC IDC
where Vr(RMS) is the root mean square (RMS) value of t t
ripple voltage, VDC is the DC value of rectified voltage,
Ir(RMS) is the RMS value of ripple current, IDC is the DC
(a)
value of rectified current. Also,
Vr(RMS) = (VRMS2 - VDC2 ) and
D1
I r(RMS) = (IRMS2 - IDC2 ) +
AC input
where VRMS is the RMS value of rectified voltage and Vi(t) RL Vo(t)
IRMS is the RMS value of rectified current, which gives
the following ripple factor:
V I
2 2
r = RMS - 1 = RMS - 1 (14.4) Vi(t)
VDC IDC Vo(t)
14.5.1.3Ratio of Rectification
t t
The ratio of rectification is the ratio of DC power deliv-
ered to the load to the AC power input from transformer
secondary, which is expressed as follows: (b)
IDC Figure 14.8| Half-wave rectifier circuits.
2
(14.5)
IRMS 14.5.2.2Full-Wave Rectifier
14.5.1.4Transformer Utilization Factor
Figures 14.9(a) and (b) show the full-wave rectifier circuit
(TUF)
for positive and negative output voltages respectively.
DC power delivered to the load
TUF = (14.6) 14.5.2.3Bridge Rectifier
AC power rating of transformer secondary
14.5.1.5Peak Inverse Voltage (PIV) Figures 14.10(a) and (b) show the bridge rectifier circuits
for positive and negative output voltages respectively.
The peak inverse voltage (PIV) is the maximum Table 14.1 gives a comparison between different rectifier
reverse voltage appearing across the diodes used in circuits.

14.5 RECTIFIER CIRCUITS 279
D1 IL D2 D1
+ AC input
AC input
RL Vo(t) Vi(t)
Vi(t) IL +
RL Vo(t)
D2 D3 D4
Vi(t) Vi(t)
t t
Vo(t) Vo(t)
t t
(a) (a)
D1 IL
D2 D1
+ AC input IL
AC input
Vi(t) RL Vo(t) Vi(t) +

D2 Vo(t) RL
D3 D4
Vi(t) Vi(t)
t t
Vo(t) Vo(t)
t t
(b) (b)
Figure 14.9| Full-wave rectifier circuits. Figure 14.10| Bridge rectifier circuits.

Table 14.1| Comparison of rectifier circuits. Practically,

IZ (min) = 0.2IZ(Rated)
Parameter Half- Full- Bridge
Wave Wave Rectifier and
Rectifier Rectifier
IZ(max) = 0.8IZ(Rated)
2 Vm 2 Vm
Secondary Vm
voltage The value of R is so chosen that it is large enough
2
Line-to-line that the current through the Zener diode keeps it in
(RMS) reverse breakdown region and is small enough that
Number of 1 2 4 the current through the Zener diode does not destroy
diodes it. If the current through the Zener diode is ID, its
breakdown voltage is VB and its maximum power dis-
sipation is PZ(max), then PZ (max) > IDVB . Also, the
Peak inverse Vm 2Vm Vm
voltage
resistor power rating, PR(max), should be greater than
No load DC Vm 2Vm 2Vm PR (max) > (V I - VZ )I max .
p p p
output
Ripple f 2f 2f Vi
frequency +
Ripple factor 1.21 0.482 0.482 RS C1 D2
Ratio of 0.406 0.812 0.812 +
rectification Vi D1 C2 2Vi Vo = 2Vi RL

TUF 0.287 0.574 0.812
14.6 VOLTAGE MULTIPLIER

CIRCUITS (a)
Vi
+
Figures 14.11(a), (b) and (c) show the circuits of a posi-
tive and negative half-wave voltage doubler and positive RS C1 D2
full-wave voltage doubler, respectively.
Vi D1 C2 2Vi Vo = 2Vi RL
A generalized voltage multiplier is shown in Fig. 14.12. +
14.7 VOLTAGE REGULATOR

(b)
Figure 14.13 shows a simple voltage regulator circuit
employing a Zener diode. The voltage across the load
resistor is the same as the Zener breakdown voltage. +

The Zener diode is so chosen that its reverse breakdown D2 C1 Vi
voltage (VZ) is the output voltage required. When the
Vo= 2Vi RL
input voltage is maximum, the output voltage is regulated
D1 +
by increased value of the current through the Zener diode. C2

Vi
The minimum value of R, that is, Rmin is given as follows: Vi
VI (min) - VZ
Rmin = (14.7)
IZ (max) + I L (min)
where IZ(max) is the maximum Zener current and IL(min) (c)
Figure 14.11| (a) Positive half-wave voltage doubler.
is the minimum load current. The maximum value of R,
that is, Rmax is given by
VI (min) - VZ
(b) Negative half-wave voltage doubler.
Rmax = (14.8) (c) Positive full-wave voltage doubler.
IZ (min) + I L (max)

SOLVED EXAMPLES 281
Tripler R
IZ IL
RS C1 C3 C5
D3 +
Vi D1 VI RL VZ
D4 D5 VZ
D2

C2 C4
Doubler
Figure 14.13| Simple Zener diode based voltage
Quadrupler
Figure 14.12| Generalized voltage multiplier.

regulator circuit.
IMPORTANT FORMULAS
1. Ripple factor is expressed as follows: 2. Ratio of rectification is given by
IDC
2
Vr(RMS) I r(RMS)
r= =
VDC IDC IRMS
V
2
3. Transformer utilization factor is expressed as follows:
= RMS - 1
DC
V DC power delivered to the load
TUF =
vi 10 AC
V power rating of transformer secondary
I
2
= RMS - 1
IDC 4. Formulas listed in Table 14.1.
6V
SOLVED EXAMPLES 5 ms
0 10 ms 10 ms t
1. Refer to the clamping circuit and the input wave-

form of the following figure. 1F Rf =100
Rr =100 M
vi 10 V
vi 100 k D vo
6V
5 ms Which of the following statements is true?

S1: The value of output waveform is always negative.
0 10 ms 10 ms t S2: The value of output waveform is always positive.
1F Rf =100
Rr =100 M
vi 100 k D vo

S3: The value of the output waveform changes from At t = 25 ms: The capacitor voltage will be 8.75
-8.89 V to -2.89 during the third rising edge of V and the output voltage is -2.75 V. As the input
the input waveform. goes low, the output goes to -8.75 V. The capacitor
S4: The value of the output waveform changes from starts discharging to 0 V, the moment input goes low
8.89 V to 2.89 during the third rising edge of the in the third cycle with a time constant of 100 ms.
input waveform. The discharge equation is given as follows:
(t -2510-3 )
(a) Only S1 is true (b) Only S2 is true -
(c) S1 and S3 are true (d) S2 and S4 are true vc = 8.75e 10010-3
Solution. With C = 1 F and Rf = 100 , the At t = 30 ms: The capacitor voltage is 8.32 V.
capacitor (c) would charge to 10 V in about 0.5 ms The output voltage is -8.32 V. Similar calcula-
(100 s being the charging time constant) during tions can be done for the fourth, fifth and the sixth
the 5 ms high time of the first cycle. As the input cycles.
drops to zero, the output too drops by 10 V and Therefore, both statements S1 and S3 are correct.
the output is at 10 V. The capacitor starts Ans. (c)
discharging the moment input goes low in the
second cycle through the resistor R with a time 2. A double diode circuit shown in the following
constant of 100 ms. The discharge equation is figure.
given by
R
t -510-3
- -3
vc = 10e 10010
Vm Z1 VZ1
At t = 10 ms: The capacitor voltage is 9.52 V.
Therefore, output voltage at t = 10 ms is -9.52 V. vi vo
With the beginning of the second cycle, the peak Vm>VZ1, VZ2 VZ2
amplitude of the input waveform is 6 V, therefore Z2
the output can go up to 3.52 V and not zero.
The capacitor starts discharging to 6 V with the
following equation:
The clipped output waveform vo is (Assume for-
(t -1010-3 ) ward biased voltage drops of the Zener diodes to
-
6 + (9.52 - 6)e 10010
-3
vc = be zero.)
vo
At t = 15 ms: The capacitor voltage is 9.35 V and vo
output voltage is -3.35 V. As the input goes low, VZ1
the output voltage goes to -9.35 V. The capacitor VZ1
starts discharging to 0 V, the moment input goes low
in the second cycle with a time constant of 100 ms. (a) t
The discharge equation is given by (a) t
(t -1510-3 ) VZ2
- VZ2
vc = 9.35e 10010-3
vo
At t = 20 ms: The new capacitor voltage will vo
be 8.89 V. The output voltage is -8.89 V. At the Vm
beginning of the third cycle, the output voltage will Vm
(b) VZ1
be 8.89 + 6 = 2.89 V. With the beginning of the (b) VZ1
third cycle, the capacitor starts discharging to 6 V
with the following equation:
t
(t -2010-3 )
- t
vc = 6 + (8.89 - 6)e 10010-3
vo
vo
VZ1
VZ1
(c) t
(c) t
VZ2
VZ2 6/4/2015 5:25:37 PM
Vm vo
(b) VVZ1
m
(b) VZ1
t SOLVED EXAMPLES 283
t
vo not conducting, it discharges through R. The area
under the output curve when the diode is conduct-
v
VZ1 o ing to the area under the output curve when the
diode is not conducting is proportional to the ratio
VZ1 of the charging time to the discharge time which in
(c) t turn is proportional to Rf/R.
t Ans. (a)
(c)
VZ2 4. For the clamping circuit and the input waveform
VZ2 of the following figure, which of the following
vo statements is correct? (Assume the diodes to be
ideal)
v
VZ2 o
VZ2 Rs
(d) t
Rs
100 Rf =100
(d) t 1 F
VZ1 100 Rr =100 M
Rf =100
VZ1 1 F
vi 100 k R RD
r =100 Mvo
vi 100 k R D vo
Solution. The Zener diode Z2 is forward biased

during positive half cycle and the Zener diode Z1 vi
breaks down for vi > VZ1. During the negative half
cycle, the Zener diode Z1 is forward biased and the vi
Zener diode Z2 breaks down for vi more negative 10 V
than -VZ2. 10 V
Ans. (c) T T
2 2 f = 2.5 kHz
3. In the clamping circuit shown in the following T T
figure, the area under the output curve when the 2 2 f = 2.5 kHz
diode is conducting (Af) and the area under the 0 t
curve when it is non-conducting (Ar) are given by
0 t
(Rf is the diodes forward resistance.)
+ (a) A
t the rising edge of the first input cycle, the
C output voltage abruptly rises to +5 V.
(b) At the falling edge of the first cycle, the output
vi R D vo voltage is 1.85 V.
(c) None of the above.
(d) Both (a) and (b) are correct.
Solution. As the voltage across the capacitor

cannot change instantaneously, the output volt-
Af R Af R age, vo, abruptly rises to only +5 V due to the
(a) = f (b) = potential divider arrangement of Rs (= 100 ) and
Ar R Ar Rf
Rf (= 100 ). The capacitor than starts charging
(c) AfAr = RfR (d) None of these towards +10 V with a time constant [(Rf + Rs)
C] = 200 s. The time period of input waveform
Solution. When the diode is conducting, the is 400 s (for f = 2.5 kHz). The capacitor voltage
capacitor charges through Rf and when the diode is at t = 200 s is given by

vc = 10(1 e1 ) = 6.3 V R
+
IZ IL= 10 mA
which gives
10 6.3 Vi DZ Vo RL
vo = = 1.85 V
2
Therefore, both (a) and (b) are correct.

Ans. (d)
Solution.
5. A Zener diode regulator in the following figure
Vi Vo
is to be designed to meet the specifications: (IZ + I L )
IL = 10 mA, Vo = 10 V and V i varies from 30 R
V to 50 V. The Zener diode has V Z = 10 V Therefore,
and IZK (knee current) = 1 mA. For satisfactory For V i = 30 V, we get R 1818
operation For V i = 50 V, we get R 3636
Therefore, option (a) is the correct answer.
(a) R 1800 (b) 2000 R 2200 Ans. (a)
(c) 3700 R 4000 (d) R > 4000
1. The output voltage (in volts) of the circuit shown Therefore, the voltage is
2 310 V = 620 V
in the following figure is
220 F
Ans. (620)
1:1 + 2. In the basic clamper circuit, positive or negative,
+ a resistance R is always connected across the
D2
220 VAC
C1 diode. If the forward-biased and reverse-biased

+220 resistances of the diode were 10 and 10 M,
D1 C2 Vo
F respectively, find the most optimum value of R
(in k).

Solution.
Solution. It is a half-wave voltage doubler circuit.
The peak value of the input waveform is R = Rf Rr = 10 10 106 = 104 W = 10 kW
(220 2 ) V = 310 V Ans. (10)
PRACTICE EXERCISE
1. Which of the following circuit can be used for 2. In a practical clamping circuit, a resistor R is
generating a square wave signal from a sinusoidal placed across the diode. This is
input?
(a) t o provide charging or discharging path for the
(a) Diode clipper (b) Diode clamper capacitor.
(c) Voltage comparator (d) Oscillator circuit (b) to neutralize the effect of diodes forward
(1 Mark) resistance.

(c) to forward bias the diode. (a) F

or a given transformer rating, it would deliver
(d) both (a) and (b). a larger DC power to the load
(1 Mark) (b) For a given transformer rating, it would deliver
lesser DC power to the load
(c) The ratio of DC power delivered to the load
output voltage is
to the AC power available at the input of
rectifier circuit from transformer secondary
R
is large
+ + (d) None of these
(1 Mark)
Z1
7. A double diode circuit is shown in the following
vi vo figure.
Z2
R

Given that the breakdown voltage and cut-in Vm D1 D2

voltage of both Zener diodes is 6V and 0.7V,
vi vo
respectively. The input vi is a sine wave with peak
amplitude of 10 V. Vm>VBB
VBB VBB
(a) |vo| 6.70 V for all vi
(b) For |vi| 10 V, vo = vi
(c) For |vi| 6.7 V, vo = vi
(d) vo 6.7 V for all vi The clipped output waveform is (Assume diodes D1
(1 Mark) and D2 to be ideal.)
4. Which of the following statements is correct?
Vm vi
(a) B
ridge full-wave rectifier offers better perfor-
vi
mance than conventional full-wave rectifier VVBB
m
in terms of transformer utilization and peak VBB vo
inverse voltage requirement for the diodes vo
(a) t
(b) Bridge full-wave rectifier offers poorer perfor- (a) t
mance than conventional full-wave rectifier
in terms of transformer utilization and peak VBB
inverse voltage requirement for the diodes VBB
V m
Vm
(c) Ratio of rectification is proportional to the
square of ripple factor
Vm vi
(d) Ripple frequency of a full-wave rectifier is half
that of a half-wave rectifier VVBB
m vi
VBB vo
(1 Mark)
(b) vo t
5. It is required to deliver an output DC power of (b) t
500 W to a resistive load. The transformer rating
VBB
required in case of half-wave, conventional full-
VBB
V m
Vm
wave and bridge rectifiers, respectively, is
(a) 1.7 kW, 616 W, 871 W
(b) 1.7 kW, 871 W, 616 W vo
(c) 616 W, 1.7 kW, 871 W Vm
(d) 871 W, 616 W, 1.7 W VBB
(2 Marks) (c)
6. If the transformer utilization factor for a particular t

rectifier configuration is small, it implies that
vo
(d) t
VBB
Vm
vo
Vm
VBB
(c)
t
vo vo
(d) t +2V
0 t
VBB
Vm
8V
(2 Marks)
8. The transfer characteristics (i.e., vo versus vi ) for (b)
the two ideal diode clipper circuit shown in the fol-
vo
lowing figure is a
+12V
10 k
+2V
D1 D2 0 t
vi vo (c)
10 k 10 k
(a) Figure (a) (b) Figure (b)
(c) Figure (c) (d) None of these
(2 Marks)
(a) positive ramp with slope of 0.5 10. The following figure shows a clipper circuit along
(b) negative ramp with a slope of -0.5 with its output waveform for a sinusoidal input.
(c) positive ramp with a slope of 1
(b) negative ramp with a slope of -2
R
(2 Marks)
D VR
9. The steady state clamped output waveform for the
circuit shown in the following figure is given by
VR
(Assume a zero forward-biased voltage drop for
diodes).
Which of the following statements is true?
(a) The circuit and the output waveforms are correct
C (b) The circuit and the output waveforms are incorrect
(c) The circuit and the output waveforms are
5V R D correct, if the diode is ideal
vi vo (d) None of these
0
5 V (2 Marks)
+

2V 11. Refer to the circuit shown in the following figure.
4V 4V
vo
+8V
vi R vo
0 t
2V
The output waveform when a sine wave having

(a) peak amplitude of 10 V is applied at its input is

6V
R R
(a) D
vi vo vi D vo
6 V
5.6 V
6V
(g) (h)
(b)
Identify the pairs of the circuits that will produce
the same output.
10 V
(a) (a)-(g), (b)-(e), (c)-(f), (d)-(h)
(b) (a)-(e), (b)-(g), (c)-(f), (d)-(h)
10 V (c) (a)-(g), (b)-(e), (c)-(h), (d)-(f)
(d) (a)-(e), (b)-(f), (c)-(g), (d)-(h)
(c) (2 Marks)
13. Circuit shown in the following figure is a basic
6 V
+
(d) C
6 V
vi R D vo
(1 Mark)
12. The following figures (a)(h) shows eight circuits.
(a) clipping circuit

R R (b) positive clamping circuit
D D
vi vo vi vo (c) negative clamping circuit
(d) two level clipper
5.6 V 5.6 V (1 Mark)
14. If the polarity of the diode in the circuit depicted
(a) (b) in the figure shown in Question 13 is reversed, the
circuit would behave as a
(a) clipping circuit
D D (b) positive clamping circuit
(c) negative clamping circuit
vi R vo vi R vo (d) two level clipper
(1 Mark)
15. Refer to the circuit shown in the following figure.
(c) (d)
C
R R
D +5V D R
vi vo vi D vo vi 0 vo
5.6 V 5V

2V
+
(e) (f)

The steady-state clamped output waveform for the D

circuit is (Assume a zero forward-biased voltage
10 10
drop for diodes.)
2 pF 1 MW 30 pF
vo
0 0
+8V
(a) 3.3 ns (b) 6.6 ns
(c) 1.1 s (d) 66 s
(2 Marks)
0 t
2V 18. Refer to the data and the figure shown in
Question 17. The fall time of the output pulse of
the diode clipper circuit is
(a)
(a) 3.3 ns (b) 6.6 ns
vo (c) 1.1 s (d) 66 s
(1 Mark)
+2V
19. The position of the switch is changed from position 1
0 t
to 2 at t = 0. If the diode in the circuit shown in
the following figure is non-ideal and has storage and
transition times of 100 ns each and forward voltage
8V drop of 0.7 V, the output voltage after time t = 0 is
given by
1
(b)
2
vo D
+12V
5V 3V R vo
+2V
0 t (a) 0 V
(b) -2.3 V for 0 < t < 100 ns, between -2.3 V and 0
(c) V for 100 ns < t < 200 ns and 0 V for t > 200 ns
(c) -3.7 V for 0 < t < 100 ns, between -3.7 V and 0
V for 100 ns < t < 200 ns and 0 V for t > 200 ns
(a) Figure (a) (b) Figure (b) (d) -3 V for 0 < t < 100 ns, between -3 V and 0 V
(c) Figure (c) (d) None of these for 100 ns < t < 200 ns and 0 V for t > 200 ns
(1 Mark) (2 Marks)
16. Refer to the data and the figures shown in 20. The following figure shows a circuit employing
Question 15. If the polarity of the battery in capacitors and diodes.
the circuit is reversed, the steady-state clamped
output waveform for the circuit shown is given
by (assume a zero forward-biased voltage drop C3 D3
for diodes.) Rs D2
(a) Figure (a) (b) Figure (b) RL vo
(c) Figure (c) (d) None of these C1
(1 Mark) vi C2
D1
17. The following figure shows a diode clipper circuit
along with the input and output waveforms. Given
that the ON resistance of the diode is 100 , what What is the minimum voltage rating of different
is the rise time of the output pulse? capacitors?

8V
8V
(a)
(a)
0
2V0 PRACTICE EXERCISE 289
2V
(a) Vm +12V
(b) 2Vm +12V
(c) C1 = Vm, C2, C3 = 2Vm
(d) C1, C3 = 2Vm, C2 = Vm (1 Mark) (b)
21.What is the minimum PIV ratings of the different (b)
diodes shown in the figure of Question 20? +2V
(a) Vm +2V0
(b) 2Vm 0
(c) D1 = Vm, D2, D3 = 2Vm 0
(d) D1 = 2Vm, D2, D3 = Vm (1 Mark) 2V0
2 V
22. What is the output voltage across resistor RL connected
in the circuit shown in the figure of Question 20? (c)
(c)
(a) Vm (b) 3Vm
(c) 7Vm (d) 6Vm (1 Mark)
12V
23. The following figure shows a circuit along with an 12V
input waveform.
+2V
C 0
+5V R D
vi vo (d)
10V
5V 2V 8 V
The output waveform is (2 Marks)
8V 24. If the placement of the Zener diode is reversed, the

output waveform of the circuit shown in Question
23 is given by
(a)
(a) Figure (d) (b) Figure (a)
0 (c) Figure (c) (d) Figure (b)
2V (1 Mark)

+12V
1. Refer to the ideal two-diode clipper circuit 2. For the data and the figure shown in Question 1,
shown in the following figure. The input to this find the minimum values (in volts) of the output
(b)
circuit is a linear ramp varying from 0 to 100 waveform. (1 Mark)
V. Find the maximum values (in volts) of the
+2V 3. The following figure shows a circuit. Given that
output waveform.
0 Vm = 10 V. What is the minimum voltage rating
of capacitor C1 (in volts)?
A B
0 RS C1 C3 C5
2VD1 D2
40 k 60 k D1 D3 D5
(c) Vm D4 D6
D2
vi vo
25 V 75 V
12V C2 C4 C6
Vo
RL
(2 Marks) (1 Mark)

4. For the circuit shown in Question 3, find the mini- 1

mum voltage rating of the capacitors C2, C3, C4,
C5, C6 (in volts) (given that Vm = 10 V). 2
(1 Mark) D
5. Find the minimum PIV ratings (in volts) of the

5V 3V R vo
different diodes of the circuit shown in Question 3.
(Given that Vm = 10 V.)
(1 Mark)
6. What is the output voltage across resistor RL (in
(2 Marks)
volts) in the circuit shown in Question 3? (Given
that Vm = 10 V.) 8. In the circuit shown in Question 6, the switch is
(1 Mark) changed from position 1 to position 2 at t = 0. If
the polarity of the diode is reversed and the diode
is ideal and its storage and transitions times are
switch is changed from position 1 to position 2 at
zero, what is the output voltage (in volts) after
t = 0. If the diode is ideal and its storage and tran-
time t = 0?
sitions times are zero, what is the output voltage
(in volts) after time t = 0? (1 Mark)
1. (c) Transformer utilization factor of a bridge recti-

fier = 0.812
2. (a) Therefore, the transformer rating required for
bridge rectifier = 500/0.812 = 616 W
3. (a) During both positive and negative half cycles,
6. (b)
the maximum value of |vo| is the same:
7. (b) For the given circuit:
During positive half cycle: Z1 is forward biased
and Z2 is reverse biased. Therefore, voltage During positive half cycle: Diode D2 remains
across Z1 = 0.7 V. Z2 acts as an open circuit till reverse biased and the diode D1 is reverse biased
|vi| < 6.7 V, and has a constant voltage of 6 V for vi less than equal to VBB and gets forward
across it when |vi| > 6 V. Therefore, the maxi- biased for vi greater than VBB.
mum value of |vo| is 6.7. During negative half cycle: Diode D1 remains
During negative half cycle: Z2 is forward biased reverse biased and diode D2 is forward biased
and Z1 is reverse biased. Therefore, voltage only for the period where vi is more negative
across Z2 = 0.7 V. Z1 acts as an open circuit till then -VBB.
|vi| < 6.7 V, and has a constant voltage of 6 V
8. (a) As vi increases in the positive direction, D1 is
across it when |vi| > 6 V. Therefore, maximum
forward biased and D2 is reverse biased. Hence, vo
value of |vo| is 6.7 V.
in this case is always equal to vi/2. For the negative
4. (a) values of vi, diode D2 is forward biased and diode
D1 is reverse biased. Again, the output is equal to
5. (b) We have: -vi/2.
Transformer utilization factor of a half-wave rec- 9. (b) In this case, the positive peaks instead of being
tifier = 0.287 clamped to zero are clamped to +2 V.
Therefore, the transformer rating required for
10. (c)
half-wave rectifier = 500/0.287 = 1.7 kW
Transformer utilization factor of a full-wave rec- 11. (a) During both halves of the input sine wave,
tifier = 0.574 one of the Zener diodes is forward biased and the
Therefore, the transformer rating required for other is reverse biased. When the input voltage
half-wave rectifier = 500/0.574 = 871 W amplitude is less than 4 V, the output is zero as

one of the diodes blocks the input voltage. When reversed. As a result, the negative peak is clamped
the input voltage amplitude is greater than 4V, to +2V.
the reverse-biased diode reaches breakdown
17. (b) When the input pulse rises from 0V to 10V,
region and the output voltage is the input voltage
the capacitance 30pF charges through the
minus 4V.
ON resistance of the diode. Therefore, the rise
12. (a) Circuits shown in figures (a) and (g) produce time is
the same output voltage as the diode in circuit
shown in figure (a) remains reversed biased when (2.2 100 30 1012) s = 6.6 ns
the input voltage is less than 5.6V. In figure (g),
the Zener diode goes to the reverse breakdown 18. (d) When the input pulse falls from 10V to 0V,
region when the input voltage is greater than the capacitance 30pF discharges through the
5.6V. 1M resistance. Therefore, the fall time is
Circuits in figures (b) and (e) produce the same
output voltage by applying the logic mentioned (2.2 1 106 30 1012) s = 66 s
above.
For the circuit in figure (c), during the positive 19. (b) During the storage time (from t = 0 to t
values of input voltage, the diode D remains for- = 100ns), the diode conducts and the output
ward biased and during negative inputs, it remains voltage is -2.3V. During the transition time
reverse biased. Therefore, the output voltage is (from t = 100ns to t = 200ns), the diode current
the same as input voltage during positive values of reduces exponentially and its resistance increases
input and is zero for negative values of input. For and at time t = 200 ns, it gets reverse biased.
the circuit in figure (f), during the positive values Therefore, the output voltage reduces exponen-
of input voltage, the diode D remains reverse tially from -2.3V at t = 100ns to 0V at time
biased and the output voltage is the same as input t = 200ns. After t = 200ns, the diode is reverse
voltage and during negative values of input voltage biased therefore, output voltage = 0V.
the diode D is forward biased; therefore, the output 20. (c) The voltages across the capacitor C1 is V1 and
voltage is zero. across capacitors C2 and C3 = 2V1. The voltage
Circuits in figures (d) and (h) produce the same across each diode when it is reverse biased is Vm.
output voltage by applying the same logic men- It is a voltage multiplier circuit with a multiplica-
tioned above for figures (c) and (f). tion factor 3.
13. (c) 21. (a) Refer to Solution of Question 20.
14. (b) 22. (b) Refer to Solution of Question 20.
15. (a) In the absence of the 2V battery, the nega- 23. (d) The circuit acts as a basic negative clamper,
tive extremities of the input waveform would be in the absence of the Zener diode. With the Zener
clamped to zero. In the presence of the battery the diode connected, the output gets clamped to a
waveform will be clamped to -2V. maximum voltage of 2V.
16. (c) The circuit is similar to the one in question 24. (c) With the polarity of the Zener diode reversed,
15 except that the polarity of battery has been the output gets clamped to a maximum of -2V.
1. When the input voltage vi is less than the potential Therefore, for vi < 45V, diode D1 is reverse biased
at node A, the diode D1 is reverse biased. When and diode D2 is forward biased with nodes A and B
diode D1 is reverse biased and the diode D2 is for- at a potential of 45 V.
ward biased, the potential at node A is equal to As vi exceeds 45V, diode D1 gets forward biased
potential at node B. The potential at nodes A and and from then onwards, potential at A is same as
B is equal to vi. Diode D2 remains forward biased as long as vi
does not exceed 75V. Thus, for vi > 45V and vi <
(75 - 25) 60 103
75 - = 45 V 75V, vo is same as vi.
(60 103 + 40 103 )

As vi exceeds 75 V, diode D2 is also reverse biased. 5. The voltage across each diode when it is reverse
From then onwards, the output is constant at biased is Vm, that is, 10 V. Therefore, minimum
75 V. PIV rating = 10 V.
Ans. (75) Ans. (10)
2. From the solution gives for Question 1, the mini- 6. It is a voltage multiplier circuit with a multiplica-
tion factor of 6; therefore, 6 10 V = 60 V.
mum value of output = 45 V.
Ans. (45)
Ans. (60)
3. The capacitor C1 has to face the input voltage Vm.
Therefore, its minimum voltage rating the same as 7. As the storage and transition times of the diode
Vm = 10 V. is zero, the diode gets reverse biased at time t =
Ans. (10) 0, when the switch is changed from position 1 to
position 2. Therefore, the output voltage is vo = 0.
4. These capacitors have to face the two voltages:
Ans. (0)
(1) The voltage Vm and (2) the voltage across the
capacitor C1. Therefore, the minimum voltage rat- 8. The diode gets forward biased immediately as the
ings of these capacitors is 2Vm = 20 V. switch position is changed from 1 to 2. Therefore,
Ans. (20) the output voltage vo is -3 V.
Ans. (-3)
1. The circuit shown in the following figure is best resistance is zero in the breakdown region), the
described as a value of R is
(a) 7 (b) 70
(c) 70/3 (d) 14
Solution. Let Vin be the input voltage, Vo be the

Output output voltage, IZ the diode current and IL the load
current. Then
Vin - Vo
(a) Bridge rectifier R (IZ + I L )
(b) Ring modulator
(c) Frequency discriminator Here, Vin = 12 V; Vo = 5 V; IZ = 0. For IL =
(d) Voltage doubler 100 mA, we have
(GATE 2003: 1 Mark)
Ans. (d) 12 - 5
R< 70 W
2. In the voltage regulator shown in the following 100 10-3
figure, the load current can vary from 100 mA to
500 mA. For IL = 500 mA,
R 12 - 5
R< 14 W
500 10-3
+ Therefore, the maximum value of R is 14 .

Variable Ans. (d)
12V 5V load 100
to 500 mA 3. In a full-wave rectifier using two ideal diodes,
VDC and Vm are the DC and the peak values
of the voltages, respectively, across a resistive
load. If PIV is the peak inverse voltage of the
Assuming that the Zener diode is ideal (i.e., the diode, then the appropriate relationships for this
Zener knee current is negligibly small and Zener rectifier are

Vm The waveform observed across R is

(a) VDC = and PIV = 2Vm
p
2V (a) 6V
(b) VDC = m and PIV = 2Vm
p
2V
(c) VDC = m and PIV = V m
p (b) 6V
V
(d) VDC = m and PIV = 2Vm
p
Ans. (b) 12 V 12 V
4. The Zener diode in the regulator circuit shown in (c)
the following figure has a Zener voltage of 5.8 V
and a Zener knee current of 0.5 mA. The maxi-
mum load current drawn from this circuit ensur- 6 V
ing proper functioning over the input voltage range
between 20 and 30 V is (d)
6 V
1 k
Solution. During the positive half cycle, the

Vi Zener diode is reverse biased. It acts as an open
VZ =5.8V Load
2030V circuit till the input voltage is less than 6V and
output voltage is 0V. When the input voltage is
greater than 6V, the diode starts conducting and
the voltage drop across the diode is 6V. When
the input voltage is negative, the diode is forward
(a) 23.7 mA (b) 14.2 mA biased and the whole of the input appears across
(c) 13.7 mA (d) 24.2 mA the resistance R.
(GATE 2005: 2 Marks) Ans. (b)
Solution. The maximum load current is drawn
when the input voltage is maximum. 6. The correct full-wave rectifier circuit is
Vin (max) - VZ
I L(max) =
- IZ
R
Substituting Vin(max) = 30 V, VZ = 5.8 V, R = 1 k
and IZ = 0.5 mA, we get (a) Input
IL(max) = 23.7 mA
Ans. (a) Output
5. For the circuit shown in the following figure,
assume that the Zener diode is ideal with a break-
down voltage of 6 V.
6V
(b) Input
R VR
12 sin t Output
(c) Input 6/4/2015 10:05:26 AM
(b) Input
Output
10
V = 0.14 V
70
Therefore, the output voltage is
(c) Input
Vo = 7V + 0.14V = 7.14V
Output
When Vi = 16V, the current passing through 200
is given by
16 - 7 3
I = A = A
210 70
The same current flows through the Zener resis-
tance. Therefore, the voltage across Zener resis-
tance is
(d) Input
3
V = 0.43 V
Output 70
Therefore, the output voltage is
Vo = 7 V + 0.43 V = 7.43 V
(GATE 2007: 1 Mark)
Ans. (c)
Ans. (d)
8. In the limiter circuit shown in the following figure,
7. For the Zener diode shown in the following figure,
an input voltage Vi = 10 sin 100pt is applied.
the Zener voltage at knee is 7 V, the knee current
Assume that the diode drop is 0.7 V when it is
is negligible and the Zener dynamic resistance is
10 .
forward biased.
200
1k
+ D1
Vi D 2 Vo
Vi Vo
Z .V

The Zener breakdown voltage is 6.8 V. The maxi-
If the input voltage Vi range is from 10 V to 16 V, mum and minimum values of the output voltage,
the output voltage Vo ranges from respectively, are
(a) 7.00 to 7.29 V (b) 7.14 V to 7.29 V (a) 6.1 V, -0.7 V (b) 0.7 V, -7.5 V
(c) 7.14 to 7.43 V (d) 7.29 to 7.43 V (c) 7.5 V, -0.7V (d) 7.5 V, -7.5V
(GATE 2007: 2 Marks) (GATE 2008: 1 Mark)
Solution. When Vi = 10V, the current through Solution. During the positive half cycle, Diode D1
200 is given by is in the forward-biased region, Zener diode Z and
diode D2 are operating in the reverse-biased region.
10 - 7 1
I = A = A Therefore, the maximum output voltage is
210 70
6.8 V + 0.7 V = 7.5 V
The same current flows through the Zener resis-
tance. Therefore, the voltage across Zener resis- During the negative half cycle, diode D1 is in the
tance is reverse-biased region, Zener diode Z and diode

D2 are operating in the forward-biased region. Solution. It is given that the voltage across the
Therefore, the minimum output voltage is -0.7V. load resistance is RL = 5V. Therefore, the voltage
Ans. (c) across 100 resistance is
9. In the circuit shown in the following figure, the V100 = 10 5 = 5 V
diode is ideal. The voltage V is given by
The current through 100 resistance is
+V V100 5
I100 = = = 50 mA
100 100
1 1
The voltage across load RL is
VR = 5 V = I L (max) R(min)
+
Vi 1A

L
Therefore,
5
R(min) =
I L(max)
Now,
(a) min (Vi, 1) (b) max (Vi, 1) I100 = IZ + I L (max) = 50 mA
(c) min (-Vi, 1) (d) max (-Vi, 1)
(GATE 2009: 2 Marks) Therefore,
Solution. Due to the current source of 1A, the I L (max) = 50 - IZ = 50 10-3 - 10 10-3 = 40 mA
diode is reverse biased by 1V. When the input
voltage Vi is less than -1V, the diode gets forward Therefore,
biased and the voltage V is equal to Vi. When the
= 125 W
5
input voltage Vi is greater than -1V, the diode is Rmin =
40 10-3
reverse biased and the voltage V is equal to 1V.
Therefore, the voltage V is min (Vi, 1). The minimum power rating of Zener diode is
Ans. (a)
PZ = VZ IZ (max)
knee current of the ideal Zener diode is 10 mA. To The maximum current through the Zener diode is
maintain 5 V across RL, the minimum value of RL
(in ) and the minimum power rating of the Zener
IZ (max) = 50 mA
diode (in mW), respectively, are Therefore,
PZ = 5 50 10-3 = 250 mW
Ans. (b)
100
11. A voltage 1000sinwt (in volts) is applied across
IL YZ. Assuming ideal diodes, the voltage measured
across WX (in volts) is
10 V
VZ = 5 V RL
1 k
W Y X
(a) 125 and 125 (b) 125 and 250

(c) 250 and 125 (d) 250 and 250 + 1 k

sin wt+ | sin wt | When VYZ is negative, then all the four diodes are
(a) sin wt (b) forward biased. Since all the diodes are given to be
2
sin wt- | sin wt | ideal, they will act as short circuit. Therefore,
(c) (d) 0 for all t
2 VW = VX
Therefore,
Solution. When VYZ is positive, then all the four V WX = V W - V X = 0
diodes are reverse biased. Therefore,
Hence, for all conditions,
VW = VX = 0
V WX = 0
Hence,
VWX = 0 V Ans. (d)

CHAPTER 15
BIASING AND BIAS STABILITY
Biasing refers to the use of external components such as 15.1 BJT AMPLIFIERS
resistors and capacitors and applying DC voltages to the
transistor so as to establish proper collector current (IC)
and collectoremitter voltage (VCE) in the active region 15.1.1 Common-Emitter Configuration
in case of a BJT and proper drain current (ID) and gate
source voltage (VGS) in case of a FET. The DC collector Common-emitter configuration is the most popular of
current (IC) [drain current (ID)] and the collectoremit- the three BJT amplifier configurations since it offers con-
ter voltage (VCE) [gatesource voltage (VGS)] when no siderable current gain as well as voltage gain. There are
input signal is applied is referred to as the operating several common-emitter biasing circuit configurations,
point or the quiescent point (Q-point). The Q-point is namely, the fixed-bias, emitter-bias, voltage-divider with
set in the middle portion of the output characteristics of emitter-bias and collector-to-base bias circuits.
the transistor, so that the transistor amplifies the input
signal linearly and without distortion. However, the 15.1.1.1Fixed-Bias Circuit
operating point shifts with change in temperature due
to the variations in parameters such as b, ICO and VBE Figure 15.1(a) shows the fixed bias circuit. The resistor
with temperature. RB is of the order of few hundreds of kilo-ohms whereas

298 Chapter 15: Biasing and Bias Stability
typical value of RC is few kilo-ohms. Figure 15.1(b)

shows its DC equivalent circuit. (DC analysis of a circuit (
IC = 0 VCE = VCC IC = 0 ) and
refers to analyzing a circuit so as to establish the operat- V
ing point in the absence of any input AC signal. For the VCE = 0 IC = CC VCE = 0
purpose of DC analysis, the input and output capacitors RC
are considered as open and it is assumed that all AC in Eq. (15.2). The load line is obtained by joining these
sources are zero). two points as shown in Fig. 15.2. The point of intersec-
tion of the load line with the curve corresponding to
VCC the calculated value of IB gives the operating point as
shown in the figure. It may be mentioned here that the
Eq. (15.2) represents the DC load line and the slope of
the DC load line is equal to (1/RC). Also, the AC or
RB RC the dynamic load line is drawn taking into consideration
the load resistance (RL) connected across the output and
AC output doing the small signal analysis. The slope of the AC load
signal
line is equal to
Co
AC input 1
signal
RC RL
Ci
The slope of the AC load line is greater than the DC
load line.
(a) IC(mA)
VCC /RC
VCC
RB IB IC RC
IBQ
+ ICQ Q-point
VCE
+
VBE
VCEQ VCC VCE(V )
Figure 15.2| DC load line for fixed-bias circuit.
(b)
Figure 15.1| (a) Fixed-bias circuit. (b) DC equivalent 15.1.1.3Emitter-Bias or Self-Bias
of the circuit shown in 15.1(a). Configuration
The quiescent point for a fixed-bias circuit is given by
An emitter-bias configuration [Fig. 15.3(a)] also referred
Eq. (15.1):
to as self-bias configuration has an additional emitter
V VBE resistor (RE) between the transistor emitter terminal
ICQ = b CC , VCEQ = VCC ICQRC (15.1) and ground as compared to the fixed-bias circuit. The
RB DC equivalent circuit of the emitter-bias circuit shown
in Fig. 15.3(a) is shown in Fig. 15.3(b). The value of the
15.1.1.2Load Line Analysis input resistance (Ri) for the emitter-bias circuit is given
by Eq. (15.3):
The collector-emitter voltage (VCE) is given by
Ri = RB + (b + 1)RE (15.3)
VCE = VCC ICRC (15.2)
The Q-point for the emitter-bias circuit is given by Eq.
To draw the load line, substitute (15.4):

15.1 BJT AMPLIFIERS 299
VCC VBE of resistor RE, larger collector supply voltage (VCC) is

ICQ = b , VCEQ = VCC ICQ (RC + RE )
RB + (b + 1)RE
needed. Also increase in RE increases the negative feed-
back and reduces the gain of the circuit. For small values
(15.4) of resistor RB, a separate base supply voltage is needed
The load line in this configuration is given by Eq. (15.5): which adds to circuit complexity and is often not fea-
sible. The disadvantages of the emitter-bias circuit are
VCE = VCC IC (RC + RE ) (15.5) removed in the voltage-divider with emitter-bias circuit.
15.1.1.4Voltage-Divider with Emitter-Bias

VCC Configuration
The stability of the emitter-bias configuration is fur-

ther improved if its input side is modified as shown in
RB Fig. 15.4(a). The circuit configuration is referred to as
RC
AC output VCC
signal
Co
AC input
signal
Ci RC
RB1 AC output
signal
RE Co
AC input
signal
Ci
RB2
(a) RE
VCC
(a)
RB IB IC RC
+ VCC
+ VCE
VBE IC RC
RB1 I1
IE RE +
VCE
+
IB
(b) VBE
Figure 15.3| (a) Emitter-bias configuration.

RB2 I2
IE RE
(b) DC equivalent of the circuit shown
in Fig. 15.3(a).
The emitter-bias circuit offers better stability than the

fixed-bias circuit. However, maximum stability is offered
by the circuit when the ratio of the base resistor (RB) to (b)
the emitter resistor (RE), RB/RE is as small as possible. Figure 15.4| (a) Voltage-divider with emitter-bias
Thus, the emitter resistor RE should have a large value configuration. (b) DC equivalent of
or the base resistor RB should be small. For large values circuit in Fig. 15.4(a).

voltage-divider with emitter-bias or simply the voltage- VCC

divider bias configuration. The input resistance, Ri, is
given by Eq. (15.6):
Ri @ (b + 1)RE (15.6) RC
RB
If the value of resistance Ri is much larger than the AC output
resistance RB2, then the Q-point is given by Eq. (15.7): signal
Co
V VBE AC input
ICQ = B ,

RE signal
Ci
VCEQ = VCC ICQ (RC + RE ) (15.7)
where
RB2VCC
VB =
RB1 + RB2 Figure 15.5| Collector-to-base bias configuration.
If the value of Ri is not much larger than RB2, then the

Q-point is given by Eq. (15.8): Another variation of the collector-to-base bias circuit is
to place an emitter resistor (RE) between the emitter
VTH VBE terminal of the transistor and ground. The collector-to-
ICQ = b ,
RTH + (b + 1)RE
base bias configuration with emitter resistor offers better
stability than emitter-bias and collector-to-base bias
VCEQ = VCC ICQ (RC + RE ) (15.8) configurations without emitter resistor.
where Also, the base resistor RB used in collector-to-base bias
RB2VCC RB1RB2 circuit has a smaller value than that used in fixed-bias
VTH = and R TH = or the emitter-bias circuit. Therefore, the base current
RB1 + RB2 RB1 + RB2 changes more in this case with temperature. Hence, the
Voltage-divider bias configuration is the most commonly advantage of better stability factor offered by collector-
used configuration as it provides excellent stabiliza- to-base bias circuit is offset by the larger variation in the
tion against variations in temperature and transistor base current.
gain (b). This is because the emitter resistor introduces
negative feedback in the circuit. However, negative feed- 15.1.2 Common Base Configuration
back results in the reduction of AC gain of the circuit.
This problem can be solved by using a capacitor CE in In the common-base configuration, the input is applied
parallel with resistor RE. (Remember a capacitor acts as to the emitter terminal and the output is taken from the
an open circuit for DC signal and as a short for the AC collector terminal and the base terminal is common to
signal). both the input and the output sections. Figure 15.6(a)
shows the circuit for common-base configuration. The
15.1.1.5Collector-to-Base Bias Configuration DC equivalent of the circuit is shown in Fig. 15.6(b).
The operating point for the common base configuration
In collector-to-base bias configuration, the base bias volt- is given by
age is obtained from the collector of the transistor instead
VEE VBE
of the collector supply voltage (VCC) as shown in Fig. ICQ = , VCBQ = VCC ICQRC (15.10)
15.5. This configuration is also referred to as feedback- RE
bias. The circuit offers better stability of the operating
point against variations in temperature and transistor
15.1.3 Common Collector Configuration
gain b due to negative feedback. The configuration has
voltage-shunt feedback as the output voltage is fed back Common-collector configuration exhibits 100% voltage-
in shunt to the input through base resistor RB. series feedback as the whole output voltage is fed back in
The value of the operating point for collector-to-base series with the input voltage. Figure 15.7(a) shows one of
bias configuration is given by the possible circuits of common-collector configuration.
VCC VBE Figure 15.7(b) shows another possible common-collector
ICQ = b , circuit.
RB + (b + 1)RC The operating point for the circuit in Fig. 15.7(a) is
VCEQ = VCC ICQRC (15.9) given by

15.2 BIAS STABILIZATION IN BJTS 301
Ci Co
AC AC
input output IE IC
signal RE RC signal RE RC
VEE VCC VEE IB VCC
(a) (b)
Figure 15.6| (a) Common-base configuration. (b) DC equivalent of the circuit in Fig 15.6(a).
VCC
RB1
AC input
signal
AC input Ci
AC output
signal RB signal
Ci AC output Co
signal
RB2 Co RE
RE
VEE
(a) (b)
Figure 15.7| Common-collector configurations.
in temperature and transistor gain, b. Transistor gain

VTH VBE
I EQ = (b + 1) , (b) increases with increase in temperature, baseemitter
RTH + (b + 1)RE voltage (VBE) of the transistor decreases with increase in
VCEQ = VCC I EQRE (15.11) temperature at a rate of 2.5 mV/C for constant collec-
tor current and the leakage current (ICO) doubles itself
where for every 10C rise in temperature. As the base current
RB2VCC RB1RB2 IB depends on the baseemitter voltage (VBE), therefore
VTH = and RTH =
RB1 + RB2 RB1 + RB2 it also varies with temperature. The collector current
(IC) is given by the expression
The operating point for the circuit in Fig. 15.7(b) is
given by IC = bIB + (b + 1)ICO
V EE VBE
I EQ = ( b + 1) ,
RB + (b + 1)RE
Therefore, it varies with temperature as all the three
parameters in its expression are temperature dependent.
VCEQ = VEE I EQRE (15.12)
15.2.1 Stability Factor

15.2 BIAS STABILIZATION IN BJTs
Stability factor defines the extent to which the collector
current (IC) of a transistor is stable against variations in
Bias stabilization refers to the ability of the bias circuit the transistor parameters, namely, the leakage current
to maintain a fixed operating point against variations (ICO), transistor gain (b) and baseemitter voltage (VBE).

Three types of stability factors are defined with respect Slca

to transistors, namely, SI , Sb and SV . Smaller value
CO BE
of stability factor indicates good bias stability whereas +1
large value of stability factor indicates poor bias stability.
Ideal value of stability factor is zero.
IC IC
SI = VBE , b const. SV = ICO , b const.
CO
ICO BE
VBE
IC
Sb = (15.13)
b ICO , VBE const.
1
RB
The total change in the collector current (IC) due to RE
Figure 15.8| Variation in stability factor.
changes in leakage current (ICO), transistor gain (b)
and base-emitter voltage (VBE) is given by Eq. (15.14):
IC = SI ICO + Sb b + SV VBE (15.14) Collector-to-base bias configuration: The stability
CO BE
It may be mentioned here that the minimum value of factor is given by Eq. (15.18). Hence, the ratio RB/RC
any of the stability factors is one and higher the value of should be as small as possible for better stability.
the stability factor, poorer is the stability of the circuit
(b + 1)[1 + (RB RC )]
with respect to that parameter. Also, the most sensi- SI = (15.18)
tive stability factor is SI as ICO is most temperature
CO
1 + b + (RB RC )
CO
dependent.
15.2.3 Stability Factor (SVBE)
15.2.2 Stability Factor (SICO)
Fixed-bias circuit: The stability factor (SVBE ) of the

Fixed-bias configuration: For a fixed-bias circuit, the fixed-bias circuit improves as the value of base resistor
collector current (IC) is strongly dependent on change in (RB) increases:
leakage current (ICO) and hence on temperature. Hence, b
the fixed bias circuit offers very poor stability against SV = (15.19)
BE
RB
variations in the leakage current.
Emitter-bias configuration
b /RE
dIC
SI = = b + 1 (15.15) SV = (15.20)
(RB /RE ) + (b + 1)
CO
dICO BE
Emitter-bias configuration: The stability factor (SICO) Voltage-divider with emitter-bias configuration
b /RE
for an emitter-bias circuit as given in Eq. (15.16) varies
from approximately 1 to (b + 1) as the ratio of base SV = (15.21)
resistor RB to emitter resistor RE increases from a very
BE
(RTH /RE ) + (b + 1)
small value to a very large value (Fig. 15.8). Collector-to-base bias configuration:
b /RC
(b + 1)[1 + (RB RE )] SV = (15.22)
(RB /RC ) + (b + 1)
dIC BE
SI = = (15.16)
CO
dICO 1 + b + (RB RE )
Voltage-divider with emitter-bias configuration: The 15.2.4 Stability Factor (Sb)

circuit offers highest stability when the value of emitter
Fixed-bias configuration
resistor (RE) is much larger than the Thevenins
equivalent resistance (RTH). RTH is much smaller than IC1
Sb = (15.23)
the corresponding base resistor (RB) of the emitter-bias b1
configuration.
Emitter-bias configuration
(b + 1)[1 + (RTH RE )] IC1[1 + (RB RE )]
SI = (15.17) Sb = (15.24)
CO
1 + b + (RTH RE ) b1[1 + b2 + (RB RE )]

15.3 BIAS COMPENSATION 303
Voltage-divider with emitter-bias configuration 15.3.2 Diode Compensation for Leakage

IC1[1 + (RTH RE )] Current (ICO)
Sb = (15.25)
b1[1 + b2 + (RTH RE )]
To compensate for the variation in the leakage current
Collector-to-base bias configuration (ICO), the diode is placed across the base-emitter termi-
IC1[1 + (RB RC )] nals of the transistor as shown in Fig. 15.10. The diode is
Sb = (15.26) reverse biased and hence the reverse saturation current
b1[1 + b2 + (RB RC )]
(ID) flows through it. The diode is chosen to be of the
same material as the transistor, so that the reverse satu-
15.3 BIAS COMPENSATION ration current of the diode increases with temperature
at the same rate as the leakage current of the transistor.
The biasing techniques discussed so far offer stability to VCC

the operating point (ICQ, VCEQ) by virtue of negative feed-
back. Although, negative feedback improves stability, but
it also reduces the gain of the circuit. In applications where RB RC
I IC
the reduction in gain is intolerable, compensation tech-
niques are used to reduce the drift in the operating point. +
Compensation techniques make use of temperature-sensitive
VCE
+
devices like diodes, thermistors, transistors, sensitors, etc. to
compensate for changes in the operating point caused due to IB
changes in temperature. In the following sections, we discuss VBE
few of the commonly used compensation circuits. ID
D
15.3.1 Diode Compensation for BaseEmitter
Voltage (VBE)
Figure 15.9 shows a circuit using a diode for compensa- Figure 15.10| Diode compensation for ICO.
tion against variations in base-emitter voltage (VBE) due
to change in temperature. The diode is made of the same
material as the transistor so that there is same varia- 15.3.3 Thermistor Compensation
tion in the transistors baseemitter voltage (VBE) and
diodes forward voltage (VD) due to temperature. Figure 15.11 shows a negative temperature coefficient
thermistor based compensation circuit. Values of the resis-
VCC tances are so chosen as to establish the desired value of col-
lector current (IC) at the normal operating temperature. As
the temperature increases, the value of the thermistor resis-
IC RC tance decreases. This reduces the forward bias and hence
the base and collector currents of the transistor. When the
+ temperature decreases, the thermistor resistance increases
RB which results in increase in the value of baseemitter volt-
VCE age. This, in turn, increases the base and the collector
currents. Therefore, the thermistor compensates for the
IB increase in collector current due to increase in temperature.
IE RE 15.3.4 Operating Point Considerations in

VBE
Thermal Runaway
RD The thumb rule to decide whether the operating point is

VD D in the safe region of operation is that for operating point
+ VDD with collector-to-emitter voltage (VCEQ) less than VCC/2
the circuit is thermally stable as increase in collector
current results in reduced power generation. In the case
of operating points having VCEQ greater than VCC/2, the
Figure 15.9| Diode compensation for VBE. circuit is not inherently thermally stable. In such cases,

VCC VCC
RC
IC RC
RB1
Vo
RB
Vi
RT
RB2 RE
(a)
Figure 15.11| Thermistor compensation.

Vin
it is necessary to check the thermal characteristics of the
VIH
transistor and the circuit design to ensure thermal stabil-
ity. For such circuits to be thermally stable, they should
satisfy the following condition:
1 0V t
[VCC 2IC (RE + RC )](SI )(0.07 ICO ) < (15.27)
CO

Vout
where VCC is the supply voltage, IC is the collector current,
RE is the emitter resistor, RC is the collector resistor,
VCC
SI is the stability factor, ICO is the leakage current and
CO
is the thermal resistance of the transistor. From Eq.
(15.27), we can infer that for small signal transistors the
problem of thermal runaway is not so critical as they
have small values of collector current (IC) and stability
factor (SI ). However, the power transistors have higher 0V t
CO
values of collector current (IC) and stability factor (SI ) (b)
CO
Figure 15.12| Transistor as a switch.

and hence the thermal management is a major problem
in the case of power transistors.
The base current (IBmax) is generally kept to be 2025%
15.4 TRANSISTOR SWITCH more than the value of (ICsat/b) so as to ensure that the
transistor is in deep saturation. The minimum value of
input voltage (VIH) required to drive the transistor into
Another major application of transistors is their use as deep saturation so that it acts as a closed switch is given
switching devices in computers and other control appli- by Eq. (15.29):
cations. Figure 15.12 shows the use of a transistor as
an inverting switch, that is, the transistor output is at VIH = IB(max)RB + VBE (15.29)
logic HIGH level for a logic LOW input applied at its where IB(max) is the maximum base current. The resis-
base terminal and the output is at logic LOW level for a tance offered by the transistor switch when in saturation
logic HIGH input. When a logic LOW input is applied, (Rsat) is given by
the transistor is in the cut-off region and acts as an open
VCE(sat)
switch. It is in the saturation region for a logic HIGH Rsat = (15.30)
input and acts as a closed switch. For a logic HIGH IC(sat)
input signal, the saturation collector current (ICsat) is For input voltage equal to zero, the collector current (IC)
given by Eq. (15.28): is equal to the leakage current (ICO) which is negligible.
V
IC (sat) = CC (15.28) Therefore, the collector voltage is at the logic HIGH
RC level and the collectoremitter resistance is very high in

15.5 JFET AMPLIFIERS 305
the range of several hundreds of kilo-ohms to few mega- 15.5.1 Common Source Configuration
ohms. The circuit thus acts as an open circuit.
Figure 15.13 shows the response of a transistor switch 15.5.1.1Fixed-Bias Configuration
when an input pulse is applied to it. The time delay
between the time the input pulse is applied to the time Figure 15.14(a) shows the fixed-bias circuit for N-channel
the collector current rises to 10% of the final value is JFET and Fig. 15.14(b) shows the DC equivalent of the
called the delay time (td). The time required for the col- circuit.
lector current to rise from 10% to 90% of the final value
is called the rise time (tr). The total time (td+tr) is VDD
known as the turn-on time (ton) of the transistor.
Vin RD
VIH
AC
output
Co signal
AC
input
IC t signal Ci
IC(sat) RG
0.9 IC(sat)
VGG
0.1 IC(sat)
td ts tf t
tr (a)
ton toff
Figure 15.13| Transistor switching characteristics.

VDD
The time interval between the input pulse transition

to the time when the collector current drops to 90% of RD ID
its value at saturation is called the storage time (ts).Fall
time (tf) is the time required by the collector current to
fall from 90% to 10% of the saturation level. Turn-off
time (toff) is defined as the sum of the storage time (ts) +
and the fall time (tf).
VDS
+
When the transistor is used in fast switching applica-
tions, a capacitor (C) is added in parallel to the base
RG VGS
resistor (RB) to reduce the storage time. The capacitor
will act as a short circuit when switching occurs and an
impulse current will flow out of the base at the negative
transition of the input pulse. VGG
15.5 JFET AMPLIFIERS (b)

Figure 15.14| (a) Fixed-bias circuit. (b) DC equivalent
of circuit shown in Fig.15.14(a).
DC biasing of a FET is done to produce the required
gate-to-source voltage (VGS) to get the desired value
The Q-point is given by Eq. (15.31):
of drain current (ID). It may be mentioned here that
VGSQ
2
the phenomenon of thermal runaway does not occur in
= IDSS 1 , VDSQ = VDD IDQRD (15.31)
V
IDQ
FETs. P

The operating point can also be obtained graphically, 15.5.1.3Voltage-Divider Biasing

by superimposing the vertical line VGS = VGG on the
transfer characteristics of the JFET or by superimposing Figure 15.16(a) shows the voltage-divider biasing circuit
the load line on the output characteristic curves of the and Fig. 15.16(b) shows its DC equivalent.
JFET. The load line is defined as follows: The operating point is given by
VDD IDRD VDS = 0 VG VGS
IDQ = , VDSQ = VDD IDQ (RD + RS ) (15.33)
RS
The fixed-bias configuration is not used much as the
wide differences in the minimum and maximum values 15.5.2 Common Drain Configuration
of the JFET parameters make drain current levels
unpredictable with simple fixed-bias circuits. Another The basic circuit for the common drain configuration
disadvantage of the fixed-biasing circuit is that it or the source follower configuration is shown in Fig.
needs an additional supply voltage for biasing the gate 15.17(a). The DC equivalent of the circuit is shown in
terminal. Fig. 15.17(b). The value of drainsource voltage (VDS)
is given by
15.5.1.2Self-Bias Configuration
VDS = VDD IDRS (15.34)
Self-bias configuration is the most commonly used bias-
ing scheme for FETs. Self-bias configuration offers stabi-
lization of the operating point. Figure 15.15(a) shows the 15.5.3 Common Gate configuration
self-bias circuit for an N-channel JFET and Fig. 15.15(b)
shows its DC equivalent circuit. Figure 15.18 shows the common-gate configuration for
The operating point is given by an N-channel JFET. The values of the gatesource and
drainsource voltages are given by Eqs. (15.35) and
(15.36), respectively.
2
I R
IDQ = IDSS 1 + D S , VGS = IDRS (15.35)
VP
VDSQ = VDD IDQ (RD + RS ) (15.32) VDS = VDD ID (RS + RD ) (15.36)
VDD VDD
RD RD
ID
AC output
signal
Co +
AC input
signal VDS
Ci +

VGS
RG RS RG
RD IS = ID
(a) (b)
Figure 15.15| (a) Self-bias circuit. (b) DC equivalent circuit of the circuit in Fig.15.15(a).

15.6 DEPLETION MOSFETS 307
VCC VDD
RD RD
R1 R1 ID
AC
output
Co signal +
AC
input + VDS
signal Ci IG 0
VGS
R2 R2
RS
RS CS
IS = ID
(a) (b)
Figure 15.16| (a) Voltage-divider biasing circuit. (b) DC equivalent circuit of the circuit shown in Fig.15.16(a).
VDD
VDD
ID
AC +
input VDS
signal Ci +
AC IG
output
VGS
Co signal RG
RG
RS RS
IS = ID
(a) (b)
Figure 15.17| (a) Common-drain configuration. (b) DC equivalent circuit of the circuit shown in Fig.15.17(a).
15.6 DEPLETION MOSFETS

AC AC
input Ci Co output
signal signal
RD The biasing schemes for depletion MOSFETs are the
RS
same as that for JFETs due to similarities in their char-
VDD acteristics. The only difference being that the depletion
MOSFETs also operate in enhancement mode, that is,
with positive values of gatesource voltage (VGS) in
Figure 15.18| Common-gate configuration.
addition to the depletion mode.

15.7 ENHANCEMENT MOSFETS VGS = VDS = VDD IDRD (15.37)
15.7.1 Feedback Biasing Configuration 15.7.2 Voltage-Divider Biasing Configuration
Figure 15.19(a) shows the circuit for the feedback biasing Figure 15.20 shows the voltage-divider biasing configura-
configuration and Fig. 15.19(b) shows the DC equivalent tion. The arrangement is the same as that for BJTs and
circuit. Therefore, gatesource voltage (VGS) and drain JFETs.
source voltage (VDS) are equal and are given by
VDD VDD
RD
RD
RG RG ID
AC output
signal +
Co IG
VDS
AC input +
signal VGS
Ci
(a) (b)
Figure 15.19| (a) Feedback biasing configuration. (b) DC equivalent of the circuit in Fig.15.19(a).
VDD
RD
R1
AC output signal
Co
AC input signal
Ci
R2 RS CS
Figure 15.20| Voltage-divider biasing configuration.
IMPORTANT FORMULAS
V VBE
1. For a fixed bias BJT configuration, the operating ICQ = b CC , VCEQ = VCC ICQRC
point is RB

SOLVED EXAMPLES 309
2. For self-bias or emitter-bias configuration, the 7. For a common-collector configuration, the operat-
operating point is ing point is
VCC VBE VTH VBE
ICQ = b , I EQ = (b + 1)

RB + (b + 1)RE
,
RTH + (b + 1)RE
VCEQ = VCC ICQ (RC + RE ) VCEQ = VCC I EQRE
3. Stability factors:
IC IC where
SI = VBE , b const. SV = ICO , b const.
CO
ICO BE
VBE RB2VCC RB1RB2
VTH = , RTH =
IC RB1 + RB2 RB1 + RB2
Sb =
b ICO , VBE const.
4. For a voltage-divider with emitter-bias configura- 8. For BJT circuit to be thermally stable
tion, the operating point is 1
[VCC 2IC (RE + RC )](SI )(0.07 ICO ) <
VTH VBE CO

=b
RTH + ( b + 1)RE
ICQ ,
9. For a fixed-bias FET circuit, the operating point is
VCEQ = VCC ICQ (RC + RE ) 2
VGSQ
where IDQ = IDSS 1 , VDSQ = VDD IDQRD
RB2VCC RB1RB2 VP
VTH = , RTH =
RB1 + RB2 RB1 + RB2 10. For self-bias FET circuit, the operating point is
5. For collector-to-base bias configuration, the oper- 2
ating point is I R
IDQ = IDSS 1 + D S ,
VCC VBE
ICQ = b VP
,
RB + (b + 1)RC VDSQ = VDD IDQ (RD + RS )
VCEQ = VCC ICQRC
11.For a voltage-divider FET circuit, the operating
6. For a common-base configuration, the operating point is
point is
V VBE VG VGS
ICQ = EE , VCBQ = VCC ICQRC IDQ = , VDSQ = VDD IDQ (RD + RS )
RE RS
SOLVED EXAMPLES
1. The following figure shows a collector-to-base bias S1: The operating point is given by (IC = 1.77mA,
circuit. Given that b = 100 and VBE = 0.7 V, which VCE = 4.38 V)
of the following statements is true? S2: The operating point is given by (IC = 1.57mA,
15 V VCE = 4.38 V)
S3: Percentage change in IC = 9.6% and VCE =
23.3% when value of b increases by 50%.
5 k S4: Percentage change in IC = 9.6% and VCE =
200 k AC output 23.3% when value of b increases by 50%.
signal (a) Both S1 and S3 are correct
Co (b) Only S1 is correct
AC input
(c) Both S1 and S4 are correct
signal
Ci (d) Both S2 and S3 are correct
Solution. Base current is given by
1 k VCC VBE
IB =
RB + (b + 1)(RC + RE )

Therefore, Also,
IB = 17.74 A b
SV =
BE
RB
The collector current is
Therefore,
IC = bIB = 1.77 mA
50
SV = = 16.6 105
The value of collectoremitter voltage is BE
300 10 3
VCE = VCC IC (RC + RE ) The total change in the collector current

Therefore, IC = SI ICO + Sb b + SV VBE
CO BE
VCE = 4.38 V
The operating point for b = 100 is 1.77 mA, 4.38 V. where
When the value of b increases by 50%, the value of
ICO = (3 103 0.2) nA = 3 103 nA = 3 A
new b is equal to 150.
The value of collector current is 1.94 mA. b = 125 50 = 75
The value of collectoremitter voltage is 3.36 V.
The operating point for b = 150 is 1.94mA, 3.36V. VBE = (0.32 0.7) V = 0.38 V
The percentage change in the collector current is
Therefore,
1.94 1.77 IC = [51 3 106 + 4 105 75 + (16.6
100% = 9.6% 105)(0.38)] A = 3.22 mA
1.77
Ans. (c)
The percentage change in collectoremitter voltage is
3. The following figure shows a CE amplifier configu-
3.36 4.38
100% = 23.3%
ration. What is the value of the end points of the
load line? (b of the transistor = 165)
4.38
Therefore, both statements S1 and S3 are correct VCC = 18 V

Ans. (a)
2. The total change in collector current when the
temperature changes from +25C to +175C, in a RC
RB1 2.2 k
fixed bias circuit with RB = 300 k and IC = 2 mA
68 k AC output
is (use the data given in the following table) signal
Co
AC input
T (C) ICO (nA) b VBE (V) signal
Ci
25 0.2 50 0.7
RE1
175 3 103 125 0.32 RB2 0.1 k
16 k
(a) 5 mA (b) 0.5 mA CE
RE2
(c) 3.22 mA (d) 0.322 mA
0.7 k 0.1 F
Solution. We know that SICO = b + 1. Therefore,

SICO = 51. Also
IC1
Sb = (a) P oint on the x-axis is VCE = 18 V and point on
b1 y-axis is IC = 6 mA
IC1 and b1 are the values of collector current and (b) Point on the x-axis is VCE = 15 V and point on
transistor gain at 25C. IC1 = 2 mA and b1 = 50. y-axis is IC = 6 mA
Therefore, (c) Point on the x-axis is VCE = 18 V and point on
y-axis is IC = 7.8 mA
2 103
Sb = = 4 105 (d) Point on the x-axis is VCE = 18 V and point on
50 y-axis is IC = 6.2 mA

SOLVED EXAMPLES 311
Solution. Applying Kirchhoffs voltage law to the 5. Introducing a resistor in the emitter of a common-
collectoremitter loop of the equivalent circuit, we get emitter amplifier stabilizes the DC operating point
18 2.2 103 IC VCE 0.8 103 IE = 0 against variations in
Substituting IC = 0 and IE = 0 in the above equa-
(a) only the temperature
(b) only the b of the transistor
tion, we get
VCE = 18 V (c) both temperature and b
(d) None of these
Substituting VCE = 0 and setting IE = IC, we get
Ans. (c)
IC = 6 mA
6. In the circuit shown in the following figure,
Ans. (a)
assume that the transistor is in the active region.
4. For the circuit shown in Question 3, what is the It has a large b and its baseemitter voltage is 0.7
operating point? V. The value of IC is
(a) ICQ = 3.58mA, VCEQ = 8.96 V (a) Indeterminate since RC is not given (b) 1 mA
(b) ICQ = 3.08 mA, VCEQ = 8.76 V (c) 5 mA (d) 10 mA
(c) ICQ = 4.08mA, VCEQ = 8.76 V
(d) ICQ =3.08 mA, VCEQ = 9.76 V 15 V
Solution. Applying Thevenins theorem to the

input section, Thevenins equivalent resistance is
RTH = 68 103 16 103 = 12.95 k RC

10 k
and Thevenins equivalent voltage is IC
18 RB2
VTH =
RB1 + RB2
18 16 103
= = 3.43 V
(68 103 ) + (16 103 ) 5 k 430
Applying Kirchhoffs voltage law to the base-emitter

loop of the equivalent circuit, we get
3.43 12.95 103 IB 0.7 0.8 103 IE = 0
Substituting IE = (b + 1)IB = 166 IB in the Solution. As b is large, it can be assumed that

above equation, we get (b + 1)RE >> RB2. (RB2 in this case is 5 k and
RE is 430 ). Therefore,
2.73 12.95 103 IB 132.8 103 IB = 0
Therefore, IB = 18.7 A.
5 103
Also, IC = bIB. Therefore, VB = 15 3
=5 V
(5 10 ) + (10 10 )
3
IC = 165 18.7 106 A = 3.08 mA
VE = VB VBE = 5 V 0.7 V = 4.3 V
Applying Kirchhoffs voltage law to the collector
emitter loop of the equivalent circuit, we get Now,
18 2.2 10 IC VCE 0.8 10 IE = 0
3 3
VE 4.3
IC IE = = A = 10 mA
Assuming IC IE, for the above equation, we get RE 430
Ans. (d)
VCE = 18 3 103 IC
= 18 3 103 3.08 103
= 18 9.24 = 8.76 V
Ans. (b)

1. The JFET in the circuit shown in the following Solution. In a JFET,

figure has IDSS = 10 mA and Vp = 5 V. Find the
V
2
value of the resistance RS in ohms when the drain ID = IDSS 1 GS
current ID is 5 mA. VP
10 V Therefore,
V
2
5 103 = 10 103 1 GS
5
Therefore,
VGS = 1.5 V
The source voltage is
VS = VG VGS = 0 (1.5) = 1.5 V

RS Therefore,
VS 1. 5
RS = = W = 300 W
ID 5 103
Ans. (300)
PRACTICE EXERCISE
1. For a transistor amplifier to be inherently stable (c) v

oltage-series feedback and current-series feed-
against thermal runaway, the condition is back, respectively
VCC VCC (d) current-series feedback and current-shunt feed-
(a) VCE < (b) VCE > back, respectively (1 Mark)
2 2
4. Thermal runaway is not possible in a FET because
VCC as the temperature of the FET increases
(c) VCE = (d) None of these
2 (1 Mark) (a) the mobility decreases
(b) the transconductance increases
2. The transconductance (gm) of a JFET is given by
(c) the drain current increases
VGS
2 (d) the mobility increases (1 Mark)

(a) gm = gm0 1
VP 5. For the AGC circuit shown in the following figure,

given that r0 is the drain resistance at VGS = 0 V,
VGS
(b) gm = gm 0 1
what is the expression for voltage gain? Assume
VP that VC2 >> VP2.
V
2
= gm 0 1 GS + Vi
(c) gm Vo
VP
V
1/ 2
R1
(d) gm = gm 0 1 GS
VP
(1 Mark)
3. The common-collector bias and emitterbias are
examples of R2
(a) voltage-series feedback VC

(b) voltage-series feedback and voltage-shunt feed-
back, respectively

(a) 1 8. The following figure shows the circuit of a

R1 R1 V transformer coupled power amplifier. Which of the
(b) 1 + + 1 C following statements is true? (Given that transistor
gain b at 25C is 100, leakage current ICO at 25C
R2 r0 2VP
is 1mA, maximum junction operating tempera-
R1 R1 V
(c) 1 + 1 C tureis 100C, baseemitter voltage of the transistor
R2 r0 2VP is 0.7 V)
R1 R2 R1 V
(d) 1 + + + 1 C VCC = 40 V
R2 R1 r0 2VP
(2 Marks) 10 k 20 RL
6. Match an item from Group 1 with the most appro- 10 k
priate item in Group 2 and choose the correct AC output
option among the four given options. Co signal
AC input
Group 1 Group 2 signal Ci
= 100
1: Emitter-bias P: Operating point
2: Transistor switch Q: Negative feedback 5
3: Thermal runaway R: Positive feedback
4: Active region S: Forward-biased base
emitter junction and
reverse-bias collector (a) The circuit is thermally stable.
emitter junction (b) The circuit is thermally stable for JA
T: Cut-off and saturation 6.54C/W at an ambient temperature of 25C.
(c) The circuit is thermally for JA 7.54C/W
U: Zero VBE and VCE
at an ambient temperature of 25C.
(d) The circuit is thermally stable for JA
(a) 1-Q, 2-T, 3-P, 4-S (b) 1-R, 2-T, 3-R, 4-Q 6.54C/W at an ambient temperature of 25C.
(c) 1-U, 2-P, 3-S, 4-R (d) 1-T, 2-Q, 3-P, 4-S (2 Marks)
(1 Mark)
9. An input pulse is applied to the transistor switch
7. Which of the following statements is true? shown in the following figure. What are the min-
S1: Storage time delay in a BJT is due to the reason imum input voltages required to make the LED
that the transistor in saturation has a saturation glow and put the transistor in saturation? (Given
charge of excess minority carriers stored in the base that the minimum current required to make the
region and the transistor cannot respond until this LED glow = 10 mA, voltage across LED = 1.5
excess charge has been removed. V, collectoremitter voltage when transistor is in
S2: Fall time in a BJT is caused due to the time saturation = 0.5 V).
required by the collector current to traverse the
active region. 12 V
S3: Delay time of a BJT is due to the time required
to charge the emitter-junction capacitance so that 200
the transistor is brought from the cut-off to the
active region and the time required to move the Vo
carriers from the base junction to the collector 2 k
junction and the time required by the collector cur- VP =100
rent to rise to 10% of its final value.
S4: Rise time of a BJT is due to the time taken by
the collector current to traverse the active region. LED
(a) S1 and S2 are true
(b) S2 and S3 is true
(c) S1 and S4 are true (a) 2.4 V, 3.45 V (b) 3.45 V, 3.8 V
(d) All the statements are true (c) 2.8 V, 3.8 V (d) 3.8 V, 5 V
(1 Mark) (2 Marks)

10. The following figure shows a circuit using an V1 = 6 V

enhancement MOSFET. Given that the threshold
voltage for the MOSFET is 2 V and ID(ON) = 6
mA for VGS(ON) = 5 V, the value of the operating R3 R4
point is 5 k 1 k
(a) (9.3 mA, 5.7 V) (b) (19.3 mA, 3.7 V)
(c) (9.3 mA, 3.7 V) (d) (8.3 mA, 5.7 V) D1 R1
R5
10 M
(1 Mark) V3
15 k R2
15 V V4
50 k
D2
V2 = 6 V
1 k
1 M
V3
5V
t(ms)
0 1 2 3 4 5 6
V4
5V
t(ms)
0 2 4 6
11. Identify the circuit shown in the following figure.
The value of current Iout is The output waveform across resistor R5 is (Assume
VCE(sat) = 0).
Vref
VR5
Vout
Rref Iref 6V
(a)
Iout 1 4 5 t(ms)
VR5
5V
(b)
1 4 5 t(ms)
t(ms)
(c)
5 V
(a) Current limiter, Iout = Vref/Rref. 1 4 5
VR5
(b) Current mirror and Iout = Iref.
1 4 5
(c) Astable multivibrator, Iout = 0 for ouput LOW VR5
and Iout = Vref/Rref for output HIGH. (d) t(ms)
6 V
(d) None of these.
(1 Mark)
VR5
12. Refer to the simple logic circuit and input wave-
form shown in the following figures. (2 Marks)

13. For the circuit shown in the following figure, find Vin Vo
the value of Vout. (Assume baseemitter voltage of R
transistor = 0.7 V.)
VC RL
8V
3 kW
Which of the following statements is TRUE?
(a) The circuit shown is a voltage amplifier and

Vo rd RL
=
2 kW Vin (rd RL ) + R(rd + RL )
10 V
(b) For VC = 0.5VP, Vo= 3.78 V and for VC = VP,
Vout Vo = 4.55 V
(c) Both (a) and (b)
(a) +5.14 V (b) 5.14 V (d) None of these
(c) 6.14 V (d) +6.14 V (2 Marks)
(1 Mark) 16. An experimental set-up using a JFET gave the fol-
14. What are the values of voltages VD and VC for the lowing readings:
circuit shown in the following figure? Given that With VGS = 0 V and VDS = 15 V, ID = 15 mA
b is 100, VBE = 0.7 V, saturation drain current of With VGS = 0 V and VDS = 10 V, ID = 14 mA
JFET is 10 mA and the pinch-off voltage is 5 V. With VGS = 1 V and VDS = 15 V, ID = 13 mA
15 V Which of the following statements is true?

(a) D
rain resistance = 5 k and transconductance
= 2 mA/V.
RD (b) Amplification factor = 10 and the JFET is an
2 kW N-channel JFET
ID (c) Both (a) and (b)
R1 VD
(d) None of these
7.5 k W (1 Mark)
RG 17. The following figure shows the output characteris-
1M W VC
tics of a certain CE amplifier circuit. Four choices
for the operating point are given. Which is the pre-
ferred option?
IC(mA)
IB = 60 A
R2
2.5 kW RE IC(max)
1 kW
IB = 50 A
IB = 40 A
50
40
(a) VC = 5.99 V, VD = 8.9 V
C IB = 30 A
(b) VC = 5.99 V, VD = 8.7 V 30
(c) VC = 6.99 V, VD = 9.9 V D
(d) VC = 5.99 V, VD = 8.9 V 20 IB = 20 A PD(max)
(2 Marks) IB = 10 A
15. The following figure shows a JFET based circuit. 10
(Given that RL = 100 k, R = 10 k, the resis- B IB = 0 VCE (V)
tance of the JFET at zero gatesource voltage is A
10 k). VCE(sat) 5 10 15 20 VCE(max)

(a) Operating point A (b) Operating point B 24 V

(c) Operating point C (d) Operating point D
(1 Mark)
2 kW
18. A given FET device has a drain current of 8 mA 1000 kW
when a drain voltage of 5 V is applied to it with
gate-source terminals shorted. When the drain volt-
age is increased to 10 V there is a small increase
in the drain current and the new value of drain
current is 8.2 mA. When the gatesource voltage is
200 kW
made 0.4 V the drain current decreases to 7 mA. 1.2 kW
What is the FET type?
(a) N-channel JFET
(b) P-channel JFET
(c) N-channel enhancement MOSET (a) 4.75mA (b) 3.25mA
(d) N-channel depletion MOSFET (c) 5.75mA (d) 3.75mA
(1 Mark) (1 Mark)
19. The amplification factor of the FET discussed in 21. What is the value of VDSQ in the case discussed in
Question no. 18 is Question 20?
(a) 100 (b) 75 (a) 12 V (b) 10 V

(c) 50 (d) 150 (c) 12 V (d) 9 V (1 Mark)
(1 Mark) 22. What is the value of VGSQ in the case discussed in
Question 20?
20. For the circuit shown in the following figure, it is
given that the saturation drain current is 5 mA and (a) 11.5 V (b) 0.5 V
the pinch-off voltage of the JFET is 4 V. What is (c) 2 V (d) 1.5 V
the value of IDQ? (1 Mark)
1. Find the output voltage (Vout) of the circuit gatesource pinch-off voltage = 5 V. What is the
(in mV) shown in the following figure (given that value of resistor RS (in ohms) so as to have the
VBE voltage for transistors Q1 and Q2 is 0.7 V). operating point as IDQ = 5 mA and VDSQ = 10 V.
15 V
VDD
RB1
1 kW RD
R1
AC
Q2 output
1.7 V signal
Co
Q1 Vout AC
input
RE signal
RB2 Ci
1 kW
100
IE1
R2
RS
CS
(2 Marks)
2. In an N-channel JFET based voltage-divider com-
mon-drain configuration shown in the following
figure, VDD = 28 V, R1 = 1 M, R2 = 0.5 M,
saturation drain current of the JFET = 10 mA and (2 Marks)

3. The following figure shows a BJT biasing circuit. 4. The output voltage of the circuit depicted in the
Find the output voltage of the circuit (in mV) figure shown in Question 3, when the adjust ter-
when the adjust terminal of the potentiometer is at minal of the potentiometer is at middle position
full down position (position C). (position B), is mV.
10 V (1 Mark)
5. The output voltage of the circuit depicted in the
500
figure shown in Question 3, when the adjust ter-
minal of the potentiometer is at top most position
Vout (position A), is mV.
A
61 kW (1 Mark)
= 100
B
100 kW
C
(1 Mark)
1. (a) 6. (a)
2. (b) 7. (d)
3. (c) 8. (b) For the circuit shown in the given figure, IC =
374 mA and VCE = 30.65 V. Since VCE > VCC/2,
4. (a)
the circuit is not inherently thermally stable. The
5. (b) quiescent power generated is given by
We know that the drain resistance is VCEQ ICQ = 30.65 374 103 = 11.46 W
ro
rd = The power dissipation capability is given by
(1 VGS VP )2
TJ TA
In this example, VGS = VC and also VC2 >> JA
VP2. Therefore,
For thermal stability is
ro ro
rd =
(1 VC VP )2

(1 2VC VP ) 100 25
11.46
JA
The gain is
Therefore,
R1 R1
1+ = 1+
R2 || rd R2 rd / R2 + rd (JA) 6.54C/W
R1(R2 + rd ) It may be noted that the transformer-coupled
= 1+
R2 rd transistor amplifiers are very much susceptible to
R1 R1 thermal runaway as they have very small DC resis-
= 1+ + tance in the collector circuit (transformer primary
R2 rd
and the emitter resistor).
R1 2V R
= 1+ + 1 C 1 9. (a) The minimum current required to make the
R2 VP r0 LED glow is 10 mA and the voltage drop across

the LED is 1.5 V. Therefore, the collector current Therefore, the transistor is not conducting and the
required to make the LED glow is 10 mA. Since for collectoremitter voltage is 6 V.
the transistor b = 100, the required base current When both inputs are HIGH, then both diodes D1
(IB) is 100 A. Applying KVL at base-emitter loop, and D2 are not conducting and the base voltage is
we get determined by voltages V1 and V2 and resistors R1,
VP 2 103 100 106 0.7 1.5 = 0
R2 and R3.
The base voltage can be determined using superpo-
Therefore, VP = 2.4 V. When the transistor is in sition theorem. Assuming V1 = 0, the voltage due
saturation, VCE(sat) = 0.5 V. to V2 at the base terminal is
Applying KVL at collector-emitter loop, we get (5 103 + 15 103 ) 6
VB2 = = 1.7 V
200 IC(sat) 0.5 1.5 = 0 5 103 + 15 103 + 50 103
Therefore, IC(sat)= 50 mA and IB(sat) = 500 A. Assuming V2 = 0, the voltage due to V1 at the base
The value of IBmax is kept 1.25 times this value of IB(sat) terminal is
to ensure that the transistor is in saturation.
Therefore, IBmax = 625 A. 50 103 6
VB1 = = 4.3 V
VP = 0.7 + 1.5 + 2 103 625 106 = 3.45 V 5 103 + 15 103 + 50 103
The base voltage VB is
10. (a) We know that for an enhancement MOSFET,
4.3 V 1.7 V = 2.6 V
ID = k(VGS VT ) 2
(1) This base voltage drives the transistor into satu-
ration. As is given, the value of collectoremitter
Therefore, voltage when the transistor is in saturation is zero.
The waveform across R5 is the same as that of the
6 103
k= = 0.67 103 A/V = 0.67 mA/V collectoremitter voltage of the transistor.
(5 2)
2
13. (b) Vout= 10 + 2 103 IC
Also, 8 0. 7
IE = = 2.43 mA
VGS = VDD IDRD 3 103
Since IE IC, we get
Therefore,
VGS = 15 ID 1 103 = 15 1000ID Vout= 10 + 2 103 2.43 103 V = 5.14 V
Substituting this value of ID in Eq. (1), we get
14. (d) The figure shows the voltage-divider transistor
ID = 0.67 103 (15 1000ID 2)2 configuration with an additional JFET connected
Therefore, between the base and the collector terminals.
The value of b RE = 100 1 103 = 105
2 106ID2 55000ID + 338 = 0 The value of 10 R2 = 10 2.5 103 = 2.5 104
Since the value of b RE is much larger than 10 R2,
Solving for ID, we get ID = 9.3 10-3 A = 9.3 mA. approximate analysis can be done to analyze the
Also, voltage-divider transistor configuration.
VDS = VDD IDRD
15 2.5 103
VB = = 3.75 V
2.5 103 + 7.5 103
Therefore,
VDS = 15 9.3 103 1 103 = 5.7 V V E = VB VBE = 3.75 0.7 = 3.05 V

VE 3.05
IE = = = 3.05 mA
11. (b) The circuit is a current mirror circuit and RE 1 103
Iout = Iref.
IC I E = 3.05 mA
12. (a) When either or both of the inputs are low, then
one or both of the diodes D1 and D2 are conduct- From the figure given, we have
ing. Therefore, the voltage at R1-R3 node is 0.7 V. ID = IS = IC = 3.05 mA

The drain voltage is When VC = VP, we note that rd tends to .

Therefore,
VD 15 ID 2 103
Vo RL 100 103
= = = 0.91
That is, Vi RL + R (100 103 ) + (10 103 )
VD = 15 3.05 103 2 103 Hence,
Vo = 5 0.91 = 4.55 V
= 15 6.1 = 8.9 V
As the current through the gate resistor is zero, 16. (c) The drain resistance is
there is no voltage drop across the resistor RG. The dVDS
value of collector voltage VC is
dID V = const.
VC = VB VGS
GS
15 10
= 3
= 5 k
In a JFET, the drain current is given by (15 10 ) (14 103 )
2
V The transconductance is
ID = IDSS 1 GS
VP dID
That is, dVGS VDS = const.
(15 103 ) (13 103 )

2
V
3.05 103 = 10 103 1 GS = = 2 mA/V
5 0 (1)
Therefore, The amplification factor is
5 103 2 103 = 10
VGS = 2.24 V
The FET is an N-channel JFET since increase in
Hence, VDS for fixed VGS leads to increase in drain current.
VC = 3.75 (2.24) = +5.99 V 17. (d) As the point D is in the middle of the charac-
teristic curves, it is the best operating point.
15. (c) If the value of the drain resistance of the FET 18. (a) Since the application of negative gatesource
is rd, then the ratio Vo to Vi is given by voltage results in the decrease of the drain current,
the JFET is an N-channel JFET.
Vo rd RL rd RL
= =
Vi (rd RL ) + R (rd RL ) + R(rd + RL ) 19. (b) The drain resistance is
VDS
The value of the resistance (rd) is given by the rd =
expression ID V = const.
GS
rd =
ro 10 5
= 3
= 25 k
) (8.0 103 )
2
VGS (8.2 10
1
VP The transconductance is
where, ro is the resistance at VGS = 0. The control ID
gm =
VGS V =const.
voltage is applied between the gate and the source
terminals; therefore, DS
3
VC = VGS 7 10 8.2 103
= = 3 mA/V
(0.4) 0
When VC = 0.5VP, we get
rd = 4 ro = 40 k The amplification factor is
m = rd gm = 25 103 3 103 = 75
5 40 103 100 103
Vo =
(40 10 100 10 ) + [(10 103 ) {(40 103 ) + (100 103 )}]
3 3
20. (d)
5 4000 106
= 21. (a)
(4000 106 ) + (1400 106 )
= 3.78 V 22. (b)

1. We have 10 V
VE1 = VB1 VBE = 1 V

500
Therefore, 100 k
VE1 Vout
1
I E1 = = A = 10 mA 61 k
RB2 100 = 100
Also
VC1 = 15 RB1 IC1
= 15 1 103 10 103 = 5 V
We know that
Ans. (10000)
VC1 = VB2
4. The following figure (a) shows the circuit.
Therefore,
(50 103 ) (50 103 )
RTH = = 25 k
VE2 = VB2 VBE = 5 0.7 = 4.3 V = 4300 mV (50 103 ) + (50 103 )
Ans. (4300)
10 50 103
VTH = =5 V
2. In a JFET, (50 103 ) + (50 103 )
V
2
The simplified circuit is shown in the following
ID = IDSS 1 GS
VP figure (b). Applying Kirchhoffs voltage law to the
input circuit, we get
That is,
5 25 103 IB 61 103 IB 0.7 = 0
V
2
5 103 = 10 103 1 GS Therefore,
5
4.3
IB = 103 A = 50 A
Therefore, VGS = 1.5 V. 86
In the voltage-divider configuration,
Also IC = b IB. Therefore,
R VDD
VG = 2 IC = 100 50 106 A = 5 mA
R1 + R2
Applying Kirchhoffs voltage law to the output sec-
that is, tion of the circuit and solving for output voltage
(Vout), we get
0.5 106 28
VG = Vout= 10 500 5 103 = 7.5 V = 7500 mV
(0.5 106 ) + (1 106 )
28 10 V
= = 9.33 V
3
The value of the resistance RS is obtained as 500
follows: 50 k
V VGS Vout
RS = G 61 k
ID = 100
9.33 (1.5)
= = 2.166 k = 2166
5 103
Ans. (2166) 50 k
3. The following figure shows the circuit. Therefore,VBE

= 0. Hence, the transistor is not conducting. So the
output voltage is equal to the supply voltage i.e. 10
V = 10000 mV. (a)

10V Also,
IC = b IB = 100 152 106 A = 15.2 mA
500 Therefore,
Vout= 10 500 15.2 10-3 = 10 7.6 = 2.4 V
Vout = 2400 mV
25 k 61 k 10 V
5V = 100
500
Vout
61 k
(b) = 100
5. The following figure shows the circuit. Applying 100 k

Kirchhoffs voltage law to the input section, we get
10 0.7
IB = A = 152 A
61 103
Ans. (2400)
1. In the amplifier circuit shown in the following ICQ increases directly with b, with all other param-
figure, the values of R1 and R2 are such that the eters remaining the same. Therefore, the new value
transistor is operating at VCE = 3 V and IC = 1.5 of ICQ is obtained as follows:
mA when its b is 150. For a transistor with b of
200
ICQ = 1.5
150
200, the operating point (VCE, IC) is mA = 2 mA
VCC = 6 V For the old value of b = 150, VCEQ = 3 V. Therefore,

ICQ RC = 6 V 3 V = 3 V
R2
R1 Therefore,
3
RC = = 2 k
1.5 10 3
Therefore, the new value of VCEQ is obtained as
follows:
VCEQ = 6 (2 103 2 103) = 2 V
Ans. (a)
(a) (2 V, 2 mA) (b) (3 V, 2 mA) 2. Generally, the gain of a transistor amplifier falls at
(c) (4 V, 2 mA) (d) (4 V, 1 mA) high frequencies due to the
(GATE 2003: 2 Marks) (a) internal capacitances of the device

(b) coupling capacitor at the input
Solution. (c) skin effect
V VBE (d) coupling capacitor at the output
ICQ = b CC , VCEQ = VCC ICQRC (GATE 2003: 1 Mark)
RB Ans. (a)

3. The circuit using BJT with b = 50 and VBE = 0.7 V (c) IC = 1 mA, VCE = 2.5 V
is shown in the following figure. The base current (d) IC = 0.5 mA, VCE = 3.9 V
IB and collector voltage VC are respectively (GATE 2004: 2 Marks)
Solution. The Thevenins equivalent circuit is
20 V shown in the following figure.
2 k
430 k VCC = 5 V
VC 2.2 k IC
IB R
10 F
TH
+
VBE

40 F VTH + 300
1 k IE
The Thevenins voltage is

(a) 43 A and 11.4 V (b) 40 A and 16 V
1 103
(c) 45 A and 11 V (d) 50 A and 10 V VTH = 3
5 = 1V
(1 10 ) + (4 10 )
3
Solution. As the value of b is very large, IB can be ignored.
VCC VBE Therefore,
IB =
RB + (b + 1)RE
VTH VBE 1 0. 7
=
20 0.7 300
IE = A = 1 mA
= 3
A = 40 A RE
(430 10 ) + (51 1 10 )
3
Applying Kirchhoffs voltage law in the collector
VC = VCC bIBRC emitter loop, we get
= 20 50 40 106 2 103 = 16 V 5 2.2 103IC VCE 300IC = 0
Ans. (b)
Therefore,
4. Assuming that the b of the transistor is extremely
large and VBE = 0.7 V, IC and VCE in the following VCE = 5 2.2 103IC 300IC = 2.5 V
circuit, respectively, are Ans. (c)
5V 5. Assuming VCE(sat) = 0.2V and b = 50, the mini-
mum base current (IB) required to drive the tran-
IC sistor connected in the circuit shown the following
figure to saturation is
4 k 2.2 k
3V
IC
+
VCE 1 k

IB
1 k 300
(a) 56 A (b) 140 A

(a) IC = 1 mA, VCE = 4.7 V (c) 60 A (d) 3 A
(b) IC = 0.5 mA, VCE = 3.75 V (GATE 2004: 1 Mark)

Solution. Solution.
VCE = VCC ICRC Under DC conditions, VDS= 2V
V
2
0.2 = 3 IC 1 103 ID = IDSS 1 GS
Therefore, IC = 2.8 mA. Also V P
(2)
2
= 10 103 1
IC
b= A = 5.625 mA
IB (8)
Therefore, VDS = VDD IDRD
2.8 10 3
= (20 5.625 103 2 103 ) V = 8.75 V
IB = A = 56 A
50
Ans. (a)
Ans. (a)
8. Transansconductance in milli-Siemens (mS) and
voltage gain of the amplifier, respectively, are
Common Data Questions 6, 7 and 8: For the
circuit shown in the following figure, it is given (a) 1.875 mS and 3.41
that rd = 20 k, IDSS = 10 mA, VP = 8 V. (b) 1.875 mS and 3.41
(c) 3.3 mS and 6
20V (d) 3.3 mS and 6
2 k Solution.
2
gm = ID IDSS
VP
D
2
G = (5.625 10 3 10 10 3 ) S
S 8
2 M = 1.875 mS
Vi Vo
Also,
2V Av = gm (rd RD )
+
Therefore,
20
Zi Zo Av = (1.875 103 ) 103 = 3.41
11
6. Zi and Zo of the circuit, respectively, are Ans. (b)
20 9.For an N-channel MOSFET and its transfer curve

(a) 2 M and 2 k(b) 2 M and k shown in the following figures, the threshold voltage is
11
20 VD = 5 V
(c) Infinity and 2 M (d) Infinity and k D
11 ID
characteristics

Transfer
VG = 3 V
Solution.
G
20
Zi = 2 M and Zo = (20 10 2 10 ) = k
3 3
11
S 1V VGS
Ans. (b)
VS = 1V
7. ID and VDS under DC conditions, respectively, are
(a) 1 V and the device is in active region
(a) 5.625 mA and 8.75 V
(b) 1 V and the device is in saturation region
(b) 7.500 mA and 5.00 V
(c) 1 V and the device is in saturation region
(c) 4.500 mA and 11.00 V
(d) 1 V and the device is in active region
(d) 6.250 mA and 7.50 V

Solution. From the graph, it is clear that the 11. The value of DC current IE is
threshold voltage is
(a) 1 mA (b) 2 mA
VTH = 1 V (c) 5 mA (d) 10 mA
From the given figure,
Solution. The Thevenins equivalent circuit is
VGS = 3 1 = 2 V shown in the following figure.
VCC = 9V
VDS = 5 1 = 4 V
Since VDS > (VGS VTH), the MOSFET is in 3 k IC

saturation region.
Ans. (c)
IB R TH
10. An N-channel depletion MOSFET has following
two points on its ID VGS curve: (i) VGS = 0 at ID +
= 12 mA and (ii) VGS = 6 V at ID = 0. Which of VBE IE
the following Q-points will give the highest trans- +

conductance gain for small signals? VTH 2.3 k
(a) VGS = 6 V (b) VGS = 3 V
(c) VGS = 0 V (d) VGS = 3 V
(GATE 2006: 1 Mark) The Thevenins resistance is
(20 103 ) (10 103 )
Solution. For an N-channel depletion MOSFET, RTH = = 6.67 k
(20 103 ) + (10 103 )
V
2
ID = IDSS 1 GS . The Thevenins voltage is
VP
10 103
The depletion MOSFET works for both positive VTH = 9 = 3 V
(20 103 ) + (10 103 )
as well as negative values of VGS. Its transconduc-
tance gain increases as VGS increases, therefore the Since the value of b is very large, IB can be ignored.
maximum gain is at VGS = 3 V for the values of VGS Therefore,
given. VTH VBE 3 0. 7
IE = = = 1 mA
2.3 103
Ans. (d) RE
Statement for Linked Answer Questions 11
and 12: In the transistor circuit shown in the fol- Ans. (a)
lowing figure, VBE 0.7 V, re = 25 mV/IE and b 12. Midband voltage gain of the amplifier is
and all the capacitances are very large. approximately
VCC = 9 V (a) 180 (b) 120
(c) 90 (d) 60
3 k
20 k Solution.
Vo Midband voltage gain
CC2 R
Av = C
2re
3 103
= = 60
CC1
(2 25 103 ) / (1 103 )
IE 3 k
10 k
CE Ans. (d)
2.3 k
transistors M1 and M2 are identical NMOS tran-
sistors. Assume that M2 is in saturation and the
output is unloaded.

VDD 12V
Ibias RE 3 k
100 k
IX Vout vo(t)
Va vi(t) 100 nF
M1 M2
100 nF
Is
10 F
20 k 900 k
The current IX is related to Ibias as

(a) IX = Ibias + IS (b) IX = Ibias
Vout
(c) IX = Ibias IS (d) IX = Ibias VDD
Solution. The best approximate answer for the
RE output voltage vo(t) is
hfe RC
(GATE 2008: 2 Marks) vo (t) = Av vi (t) = vi (t)
hie
Solution. It is a current mirror circuit. Therefore,
150 3 103
= (A cos 20t + B sin 106 t)
I X = IS 3 103
For NMOS transistors, gate current = 0 = 150 + (A cos 20t + B sin 106 t)
Since, the output coupling capacitor is large, we get
Therefore,
IG1 = IG2 = 0 vo (t) = 150 (B sin 106 t)
Ans. (d)
From the circuit, we see that
15. In the circuit shown in the following figure, capaci-
I bias = IS + IG1 + IG2 tors C1 and C2 are very large and shorts at the
input frequency, vi is a small input. The gain mag-
Substituting the values of IG1 and IG2 in the above nitude |vo/vi| at 10 M rad/s is
equation, we get
I bias = IS + 0 + 0 5V
Therefore,
I X = I bias
10 H 2k 1nF
Ans. (b)
6
14. A small signal source vi (t) = A cos 20t + B sin 10 t +
is applied to a transistor amplifier as shown in the C2
following figure. The transistor has b = 150 and hie
= 3 k. Which expression best approximates vo(t)? Q1
(a) vo (t) = 1500 (A cos 20t + B sin 10 t)

6 +
2.7 V vo 2k
(b) vo (t) = 150 (A cos 20t + B sin 10 t)

6
2k
(c) vo (t) = 1500 (B sin 10 t)
6 vi C1

(d) vo (t) = 150 (B sin 10 t)
6

(a) maximum (b) minimum (a) 20 (b) 30

(c) unity (d) zero (c) 40 (d) 50
(GATE 2011: 1 Mark)
Solution. It is given that b is very large. Therefore,

Solution. Whenever we use a bypass capacitor in
parallel with emitter resistor RE in a common emitter
configuration with emitter resistor it increases the IC = IE = 1 mA
voltage gain with increase in frequency as compared
to common emitter configuration without emitter VE = IERE = 1 103 500 = 0.5 V
resistor. The resonant frequency for the circuit is
and VBE = 0.7 V
1 1
w= = = 10 M rad/s
10 106 109
LC Therefore,
VR2 = VBE + VE = 0.7 + 0.5 = 1.2 V

The gain is maximum at the resonant frequency;
hence, option (a) is correct. It is a self-bias circuit and hence
Ans. (a) R2
VR 2 = VCC
16. In the circuit shown in the following figure, the R1 + R2
silicon NPN transistor Q has a very high value of Therefore,
b. The required value of R2 (in k) to produce IC
R2
= 1 mA is 1.2 = 3
60 103 + R2
VCC = 3V
R2 = 40 k
Ans. (c)
R1 = 60 k IC
R2 RE = 500

CHAPTER 16
AMPLIFIERS
This chapter discusses the different types of amplifiers including single-stage and multistage amplifiers, differential amplifiers,
operational amplifiers, feedback amplifiers and power amplifiers.
16.1 AMPLIFIERS AN in input current, is the gain parameter. The input and
INTRODUCTION output circuits of a current amplifier are represented by
Nortons equivalent circuits. For a true current ampli-
fier, the input resistance should ideally be zero and the
Based on the input and the output parameters of inter- output resistance should ideally be infinite.
est, the amplifiers are classified as voltage amplifiers, In the case of a transresistance amplifier, ratio of the
current amplifiers, transresistance amplifiers and trans- change in output voltage to change in input current is
conductance amplifiers. the gain parameter. The gain parameter has the units of
In the case of a voltage amplifier, voltage gain, which resistance. The input and output circuits of a transresis-
is the ratio of the change in output voltage to change tance amplifier are respectively represented by Nortons
in input voltage, is the gain parameter. The input and and Thevenins equivalent circuits. For a true transresis-
output circuits of a voltage amplifier are represented by tance amplifier, the input and output resistances of the
Thevenins equivalent circuits. For a true voltage ampli- amplifier should ideally be zero.
fier, its input resistance should ideally be infinite and the In the case of a transconductance amplifier, ratio of
output resistance should ideally be zero. the change in output current to change in input volt-
In the case of a current amplifier, current gain, which age is the gain parameter. The gain parameter has the
is the ratio of the change in output current to change units of conductance. The input and output circuits of a

328 Chapter 16: Amplifiers
transconductance amplifier are respectively represented Ai is the current gain without taking the source resis-
by Thevenins and Nortons equivalent circuits. For a tance (Rs) into account. The overall current gain
true transconductance amplifier, the input and output taking Rs into account (Ais) is given by Eq. (16.2).
resistances of the amplifier should ideally be infinite. Rs
Ais = Ai (16.2)
Zi + Rs
16.2 SINGLE-STAGE AMPLIFIERS When Rs , Ais Ai. Therefore, Ai is the cur-
rent gain for an ideal current source, that is, the
In this section, the single-stage BJT and FET amplifiers one with infinite internal resistance.
are discussed. 2. Input Impedance (Zi)
Vi hhR
16.2.1 Analysis of a Transistor Amplifier Using Zi = = hi + hr Ai R L = hi r f L (16.3)
Ii 1 + ho R L
Complete h-Parameter Model
3. Voltage Gain (Av)
Figure 16.1 shows a generalized transistor-based ampli-
Vo AR
fier where the transistor is replaced by its h-parame- Av = = i L (16.4)
ter model. As we can see from the figure, resistor RL Vi Zi
is the external load and Vs is the input signal source. The voltage gain (Avs) taking Rs into account is
The important parameters of any amplifier are the cur- given by
rent gain, input impedance, voltage gain and the output
Vo V Zi
impedance. A vs = = Av i = Av (16.5)
Vs Vs Zi + Rs
1. Current Gain or Current Amplification (Ai)
When Rs 0 then Avs Av. In other words, Av
I hf is the voltage gain for an ideal voltage source, that
Ai = L = (16.1)
Ii 1 + ho R L is, the one with zero internal resistance.
Ii Io
+ IL
+
hi
Rs +
+ Vi h r Vo hf Ii ho Vo RL
Zi Zo
Vs

Figure 16.1| Generalized transistor-based amplifier.
VCC
Io
RC
RB +
Ii Ib Ic Io +
Ii Vo
Co Vi RB hie hfeIb hoe RC Vo
Vi
Zo

Ci Zi
Zo
Zi
(a) (b)
Figure 16.2| (a) Fixed-bias configuration. (b) Simplified h-parameter equivalent model of fixed-bias circuit shown in
Fig.16.2 (a).

16.3 ANALYSIS OF TRANSISTOR CONFIGURATIONS USING SIMPLIFIED h-PARAMETER MODEL 329
4. Output Admittance (Yo) 4. Current gain (Ai)
Io hf hr hfe (RB1 RB2 )

Yo = = ho (16.6) Ai = (16.14)
Vo hi + Rs (RB1 RB2 ) + hie
V s = 0, RL =
The output impedance Zo is the reciprocal of admit-

VCC
tance Yo. In this expression, it is assumed that the
load RL is external to the amplifier. If the effect of
load resistor RL is included, then the total output Io
impedance is given by the parallel combination of
Zo and RL. RC
RB1
Vo
16.3 ANALYSIS OF TRANSISTOR Ii C Co
i
CONFIGURATIONS USING SIMPLIFIED Vi
h-PARAMETER MODEL Zo
Zi RB2
16.3.1 Common-Emitter Configuration RE CE
16.3.1.1Fixed-Bias Configuration
Figure 16.2(a) shows the circuit diagram of the fixed-

bias configuration and Fig. 16.2(b) shows the simplified (a)
h-parameter equivalent model.
1. Input impedance (Zi)
+ +
Zi = RB hie (16.7) Ii Ib Ic Io
2. Output impedance (Zo) Vi RB1 hie hfeIb hoe RC Vo

RB2
Zo = RC (1/hoe ) (16.8)

Zi Zo
3. Voltage gain (Av)
Vo hfe[RC (1/h oe )]
Av = = (16.9)
Vi hie
(b)
Figure 16.3| (a) Voltage-divider configuration.
4. Current gain (Ai)
Io h RB
Ai = = fe (16.10) (b)Simplified h-parameter equivalent
Ii RB + hie model of circuit in Fig.16.3 (a).
Assuming RB >>hie, A i hfe
16.3.1.3Emitter-Bias Configuration with
16.3.1.2Voltage-Divider Configuration Unbypassed Emitter Resistor
Figure 16.3(a) shows the voltage-divider configuration Figure 16.4(a) shows the circuit diagram of the emitter-
and Fig. 16.3(b) shows its simplified h-parameter equiva- bias configuration with unbypassed emitter resistor and
lent model. Fig. 16.4(b) shows its simplified h-parameter equivalent
1. Input impedance (Zi) model.
Zi = (RB1 RB2 ) hie (16.11) 1. Overall input impedance (Zi)
2. Output impedance (Zo) Zi = RB hie + (hfe + 1)RE (16.15)

Zo = RC (1/hoe ) (16.12)
3. Voltage gain (Av) 2. Voltage gain (Av)
hfe [RC (1/hoe )] Vo hfeRC
Av = (16.13) Av = = (16.16)
hie Vi hie + (hfe + 1)R E

3. Current gain (Ai) 1. Overall input impedance (Zi)

Io hfe RB Zi = RB [hie + (hfe + 1)RE ] (16.19)
Ai = = (16.17)
Ii RB + hie + (hfe + 1)RE
2. Output impedance (Zo)
4. Output impedance
1 Zo = RE [hie (hfe + 1)] (16.20)
Zo = RC (16.18)
hoe 3. Voltage gain (Av)
Vo RE
16.3.2 Common-Collector or Emitter-Follower Av = = (16.21)
Vi RE + hie /(hfe + 1)
Configuration
Figure 16.5(a) shows the emitter-follower configuration
and Fig. 16(b) shows its simplified h-parameter equiva- Io (hfe + 1)I b (hfe + 1)RB
Ai = = = (16.22)
lent model. Ii Ii RB + Zi
VCC
Io
RC
RB
+ +
Vo Ii Ib Ic Io
Ii
Co
hie hfeIb hoe
Vi
Ci Vi RB RC Vo
Zi Zo
Zi Zi Zo
RE RE Ie

(a) (b)
Figure 16.4| (a) Emitter-bias configuration with unbypassed emitter resistor. (b) Simplified h-parameter equivalentmodel
of circuit in Fig. 16.4 (a).
VCC
RB
+ I Ib Ic
i
Ii
hic hfc Ib hoc
Vi
Ci Vi RB
Co
Vo
Io Zi Zi Ie +
Io Vo
Zi RE Zo RE Zo

(a) (b)
Figure 16.5| (a) Emitter-follower configuration. (b) Simplified h-parameter equivalent model of circuit in Fig. 16.5 (a).

16.4 ANALYSIS OF FET AMPLIFIERS 331
16.3.3 Common-Base Configuration 16.4 ANALYSIS OF FET AMPLIFIERS

Figure 16.6(a) shows the circuit diagram of common-
base configuration and Fig. 16.6(b) shows its simplified 16.4.1 Common-Source FET Amplifier
h-parameter equivalent model.
The common-source FET amplifier is shown in Fig.
1. Input impedance (Zi) 16.7(a) and its equivalent circuit is shown in Fig. 16.7(b).
Zi = RE hib = RE [hie /(hfe + 1)] (16.23) The voltage gain Av is given by
V mRD
Av = o =
2. Output impedance (Zo)
(16.26)
Vi rd + RD
Zo = RC (1/hob ) RC (16.24)
For the common-source amplifier with an unbypassed
3. Voltage gain (Av) source resistor (RS), the voltage gain is given by
Vo h R
= fe C mRD
Av = (16.25) Av = (16.27)
Vi hie rd + RD + (m + 1)RS
Io h R 16.4.2 Common-Drain FET Amplifier
Ai = = fb E
Ii RE + hib
The common-drain FET amplifier and its equivalent cir-
hfb RE
= hfb (4.25) cuit are shown in Fig. 16.8(a) and (b), respectively. The
RE + hie (1 + hfe ) voltage gain (Av) is given by
Ii VDD
Co
Ii Co
Vi C Vo
i RD Id
Io Vi Ie Ic Io Vo
Ci
RE RC G
hfb Ie V RC +
Zi Zo RE hib
Co hobo Zo gmVgs
Zi
VEE VCC Vi = Vgs r
Vi
Ci I

b
S
(a) (b)
VDD (a) (b)
Co
Ii Co
RD Id
Vo
Io Vi Ie Ic Io Vo G D
Ci Vo + Id +
RC Co gmVgs
Zo RE hib hfb Ie hob RC
Zi Zo Vi = Vgs rd RD Vo
Vi
VCC Ci

Ib S S
(b) (a) (b)

Figure 16.6| (a) Common-base configuration. Figure 16.7| (a) Common-source FET amplifier.
(b) Simplified h-parameter equivalent (b) Equivalent circuit of circuit in
model of circuit in Fig. 16.6 (a). Fig. 16.7 (a).

VDD
D
G
+
gmVgs rd
Vi
Vi
S
Vo +
RS Id Vo
RS Id

(a) (b)
Figure 16.8| (a) Common-drain FET amplifier. (b) Equivalent circuit of (a).
Vo mRS where Av is the overall voltage gain, Av1 is the voltage

Av = = (16.28)
rd + (m + 1)RS
gain of stage 1 amplifier with the input impedance of stage
Vi
2 amplifier acting on it, Av2 is the voltage gain of stage 2
For the common-drain amplifier with an unbypassed amplifier with the input impedance of stage 3 amplifier
drain resistor (RD), the voltage gain is given by acting on it and its source impedance is the output imped-
mRS ance of stage 1 amplifier, Avn is the voltage gain of stage
Av = (16.29)
rd + RD + (m + 1)RS n amplifier with the load impedance acting on it and its
source impedance is the output impedance of stage (n 1)
As the value of is very large, therefore the term amplifier. The overall current gain is given by
(m + 1)RS >> (rd + RD). Therefore, Eq. (16.29) can by
approximated as Z
Ai = Av i1 (16.32)
mRS m RL
Av 1 (16.30)
(m + 1)RS m +1 where Zi1 is the input impedance of the stage 1 amplifier
and RL is the load resistance.
16.5 MULTISTAGE AMPLIFIERS
16.5.1 BJT Cascade Amplifier
The multistage amplifiers are used when the gain of a Figure 16.10 shows a cascaded three-stage RC-coupled
single-amplifier stage is not sufficient for the intended BJT amplifier. Let the h-parameters of the transistor Q1
application or the input or/and the output impedances be hie1, hfe1, hre1 and hoe1; of transistor Q2 be hie2, hfe2,
of the amplifier are not of the correct magnitude for the hre2 and hoe2 and that of transistor Q3 be hie3, hfe3, hre3
intended application. Figure 16.9 shows a generalized and hoe3.
cascaded or multistage amplifier configuration.
The voltage gain of the third stage is given by
The overall gain (Av) is given by
hfe3 [RC3 (1/hoe3 )] hfe3 RC3
Av = Av1 Av2 Avn (16.31) Av3 = (16.33)
hie3 hie3
+ +
Zi1 Zi2 Zi3 Zin
Vi Av1 Av2 Av3 Avn RL Vo
Zo1 Zo2 Zo3 Zon
Figure 16.9| Generalized cascaded amplifier configuration.

16.5 MULTISTAGE AMPLIFIERS 333
VCC
RC1 RC2 RC3

RB1 RB3 RB5
Vo
Cc1 Cc2 Co
Vi
Ci Q1 Q2 Q3
RB2 RB4 RB6

RE1 CE1 RE2 CE2 RE3 CE3
Figure 16.10| Cascaded three-stage RC-coupled BJT amplifier.
Similarly, the gain for the second stage Av2, assuming

( )
Zi = RB1 RB2 hie1 (16.37)
(1/hoe2)>> RB5 RB6 RC2 hie3 is given by
The output impedance of the amplifier is equal to the
hfe2 ( RB5 RB6 RC2 hie3 ) output impedance of the last amplifier stage.
Av2 = (16.34)
hie2
Zo = RC3 (1/hoe3 ) (16.38)
The gain for the first stage Av1, assuming (1/hoe1)>>
(RB3 RB4 RC1 hie2 is given by )
16.5.2 FET Cascade Amplifier
hfe1 ( RB3 RB4 RC1 hie2 )
Av1 = (16.35)
hie1 Figure 16.11 shows a cascaded three-stage RC-coupled
The overall voltage gain Av is given by JFET amplifier. The gains of the first, second and third
stages are given by Eqs. (16.39a), (16.39b) and (16.39c),
Av = Av1 Av2 Av3 (16.36) respectively.
The overall input impedance of the amplifier is the same
as the input impedance of stage 1 amplifier. Av1 = gm1RD1 (16.39a)
VDD
RD1 RD2 RD3
Vo
Cc1 Cc2 Co
Vi Q3
Q1 Q2
Ci
RG1 RG2 RG3

RS1 CS1 RS2 CS2 RS3 CS3
Figure 16.11| Cascaded three-stage RC-coupled JFET amplifier.

Av2 = gm2RD2 (16.39b) It offers other advantages like increased value of input
impedance and reduced value of output impedance.
Av3 = gm3RD3 (16.39c) Figure 16.13 shows a circuit configuration employing a
Darlington pair.
where RD1, RD2 and RD3 are the drain resistors for stage-1,
stage-2 and stage-3 amplifiers, respectively; gm1, gm2 and VCC
gm3 are the transconductance values for stage-1, stage-2
and stage-3 amplifiers respectively. The overall gain (Av)
is given by Ii
Q1
Av = Av1 Av2 Av3 (16.40) Vi
The input impedance Zi of the cascaded amplifier is the

same as the input impedance of the stage-1 amplifier, Zi
which is given by Zi2 Q2
Io
Zi = RG1 (16.41) Vo
Zo
The output impedance (Zo) is given by the output RE2
impedance of the last amplifier stage:
Zo = RD3 (16.42)
Figure 16.13| Circuit configuration employing a
A combination of FET and BJT stages can also be used
Darlington pair.
to provide both high values of voltage gain as well as
input impedance. The current gain for the second transistor Q2 is given by
Io 1 + hfe2
Ai2 = = 1 + hfe2 (16.44)
16.5.3 Darlington Amplifier I b2 1 + hoe2RE2
The input resistance of the second stage is given by
The Darlington amplifiers (Fig. 16.12) refer to the con-
nection of two BJTs wherein their collector terminals Zi2 = hie2 + (1 + hfe2 )RE2 (1 + hfe2 )RE2 (16.45)
are tied together and the emitter terminal of one of the
Zi2 is the effective load resistance for the first-stage tran-
transistors is connected to the base terminal of the other
sistor Q1 and the current gain for the first stage (Ai1) is
transistor. In other words, the Darlington connection
given by
can be considered as two cascaded emitter followers,
with the first stage having an infinite emitter resistance. I e1 I 1 + hfe1
Ai1 = = b2 =
If the individual transistors have current gains of b1 and Ii Ii 1 + hoe1Zi2
b2, then the Darlington connection provides an approxi- 1 + hfe1 1 + hfe1
mate current gain (bD) given by
1 + hoe1(1 + h fe2 )RE2 1 + hoe1hfe2RE2
b D = b1 b 2 (16.43) The overall current gain (Ai) is given by
Io I I
C Ai = = o b2
Ii I b2 Ii
C

(1 + hfe2 )
1 + hfe1
(16.46)
1 + hoe1 fe2 E2
h R
B Assuming that the h-parameters for both the transistors
Q1 B are equal, that is, hfe1 = hfe2 = hfe and hoe1 = hoe2 = hoe,
the above equation can be rewritten as
(1 + hfe )2
Ai @
Q2 1 + hoe hfe RE2 (16.47)

E
The overall voltage gain (Av) is less than unity, because
E it consists of two emitter followers in cascade, each offer-
Figure 16.12| Darlington amplifier. ing values of voltage gain slightly less than unity.

16.5 MULTISTAGE AMPLIFIERS 335
Vo h
FET-based cascode amplifier, common-source amplifier
1 ie
Av = (16.48) is followed by common-gate amplifier as shown in
Vi Zi2 Fig. 16.15(b).
The overall input impedance (Zi) is given by VCC
AR (1 + hfe )2RE2
Zi = i E2 Ai RE2 (16.49)
Av 1 + hoe hfe RE2
RB1
The output impedance (Zo) is given by
Vi
RS + hie hie
Zo 2
+ (16.50) Ci
(1 + hfe ) 1 + hfe Q1
where Rs is the value of the source resistance (not shown RB2 Io
Q2 Vo
in Fig. 16.13). In deriving the above equations, we have
omitted the biasing network for transistor Q1 to sim- Zi Zi Co
Zo
plify the analysis. The biasing network mainly affects the RE2
input impedance of the network. Figure 16.14(a) shows
one possible biasing arrangement. The overall input
impedance (Zi) is given by (a)
Zi = Zi R (16.51)
VCC
where R = RB1 RB 2 . The value of R (i.e., the paral-
lel combination of RB1 and RB2) is much less than the
value of Zi. Therefore, the overall input impedance (Zi)
RB1
is appreciably smaller than Zi. This nullifies one of the Ci
major advantages offered by a Darlington amplifier that Vi
it offers high input impedance.
Figure 16.14(b) shows another biasing configuration RB3 Q1
that removes this disadvantage. Now,
Zi
Io
Zi Q2
R = RB1 RB2 + RB3 Vo
RB2 Co
Zo RE2
The value of R is still less than Zi. The value of R can be
substantially improved if we add a capacitor CB in addi-
tion to resistor RB3 [Fig. 16.14(c)]. The effective value of
RB3 can be calculated by making use of Millers effect.
(b)
RB3
RB3(eff) = (16.52)
1 Av
VCC
As the value of voltage gain (Av) is close to unity, value
of RB3(eff) becomes very large. The effect of the voltage
gain (Av) approaching unity on the resistor RB3(eff) is RB1
referred to as bootstrapping. For unity value of Av both Ci
ends of RB3 increase by the same potential as if RB3 were Vi Q2
pulling it by its bootstraps.
RB3 Q1
Zi
16.5.4 Cascode Amplifier Zi CB Io
Vo
The cascode amplifiers are two-stage amplifiers compris- RB2 Zo Co
ing a transconductance amplifier followed by a current RE2
buffer. They offer advantages such as high inputoutput
isolation, high input impedance, high output impedance
and large bandwidth. In a BJT cascode amplifier config-
(c)
uration, the common-emitter transistor is followed by a
common-base transistor [Fig. 16.15(a)]. In the case of an Figure 16.14| Darlington amplifier configurations.

VCC
VDD
RB1 RC
RD
Vo
Vo
Co
Co
Vi Q1 Q2
Ci Q2
RB2
RE CE RB CB Vi Q1
Ci
(a) (b)
Figure 16.15| (a) BJT-based cascode amplifier configuration. (b) FET-based cascode amplifier configuration.
16.6 DIFFERENTIAL AMPLIFIERS +VCC
Figure 16.16 shows the basic single-stage differential

amplifier configuration. If two different input signals V1 RC RC
and V2 are applied to the non-inverting and inverting
+
inputs, respectively, then the output (Vo) is given by
Vo
Vo = Ad (V1 V2 ) (16.53)
V1 Q1 Q2 V2
where Ad is the differential gain of the amplifier. The
value of differential gain Ad is given by
RC
Ad = (16.54)
re RE
where re is the dynamic resistance of the base-emitter
junctions of the two transistors. The common mode gain
Ac is given by VEE
Ac =
RC
(16.55) Figure 16.16| Basic single-stage differential amplifier.
2RE
Therefore, the common mode rejection ratio (CMRR) is
given by 16.7 OPERATIONAL AMPLIFIERS
Ad 2RE
CMRR = = (16.56)
Ac re An operational amplifier popularly known as an opamp
is basically a high-gain differential amplifier capable of
It is evident from the expression for CMRR that the amplifying signals right down to DC. The capability of
value of RE should be as high as possible. That is why the opamp to amplify signals down to DC lies in the use
in practical opamp circuits, RE is replaced by a constant of direct coupling mechanism in the internal architec-
current source (Fig. 16.17). ture of the device. That is why it is also called a direct-
A current mirror configuration is also used to implement coupled or a DC amplifier. Figure 16.19 shows the circuit
a constant current source (Fig. 16.18). representation of an opamp.

16.7 OPERATIONAL AMPLIFIERS 337
+VCC Figure 16.20 shows the block schematic arrangement of

the internal circuit of a typical opamp with a differential
input and a single-ended output.
RC RC
Vo Class-B
Vin Differential Gain Vout
push-pull
amplifier stages
V1 V2 output stage
Q1 Q2
Figure 16.20|Block schematic arrangement of an opamp.
R2 The output voltage Vout is given by

Vout = AOL Vin (16.57)
+ Q3
where AOL is the open-loop voltage gain of the opamp,
VZ that is, the voltage gain in the absence of any negative
R1 feedback.
16.7.1 Ideal Opamp Versus Practical Opamp

VEE
Figure 16.21(a) shows the Thevenins equivalent circuit
Figure 16.17| Single-stage differential amplifier with a model of a practical opamp. Figure 16.21(b) shows the
constant current source. Thevenins equivalent representation of an ideal opamp.
The ideal opamp model makes the following three
assumptions.
+VCC
1. Input resistance, Ri = .
RC RC 2. Output resistance, Ro = 0.
3. Open-loop gain, Ad = .
Vo
From the three above-mentioned primary assumptions,
R
V1 V2 other assumptions can be derived.
Q1 Q2 1. Since Ri = , II = INI = 0. (II and INI are the cur-

rents in the inverting and the non-inverting inputs
of the opamp).
2. Since Ro = 0, Vo = Ad Vd
3. For the linear mode of operation of opamp and a
D Q3 finite output voltage and infinite differential gain,
VEE Vd = 0.
Figure 16.18| Single-stage differential amplifier with a
4. Since the output voltage depends only on differen-
tial input voltage, it rejects any voltage common
current mirror.
to both inputs. Therefore, the common mode gain
= 0.
+V 5. The bandwidth and slew rate are also infinite as no
frequency dependencies are assumed.
Non-inverting 6. The drift is also zero.
input +
Output
16.7.2 Performance Parameters
Inverting
input
16.7.2.1Bandwidth
V
Figure 16.19| Circuit representation of an opamp.

The frequency response curve of a typical opamp looks
like the graph shown in Fig. 16.22. The high-frequency

II

VI VI

+ +
Ro
Vd Ri AdVd Vd AdVd
Vo Vo
+
VNI VNI +
INI
(a) (b)
Figure 16.21| Thevenins equivalent circuit model of (a) a practical opamp and (b) an ideal opamp.
110
100
90
Differential open loop gain (dB)
80
70
60
50
40
30
20
10
0
10 f (Hz)
1 10 100 1k 10 k 100 k 1M 10 M
(a)
Figure 16.22| Frequency response curve of a typical opamp.
roll-off is attributed to capacitive effects appearing in 16.7.2.2Slew Rate

shunt. Beyond cut-off, the frequency falls at a rate of
6 dB per octave or 20 dB per decade. When the opamp is The slew rate is defined as the rate of change of output
used in the closed-loop mode, the bandwidth increases at voltage with time. It is determined by applying a step
the cost of the gain. The bandwidth is usually expressed input and monitoring the output as shown in Fig. 16.23.
in terms of the unity gain crossover frequency (also The incapability of the opamp to follow rapidly rising
called gain-bandwidth product). It is the frequency at and falling input is, respectively, due to the minimum
which the closed-loop gain of the opamp becomes unity. charge and discharge times required by an internally

16.7 OPERATIONAL AMPLIFIERS 339
connected capacitor across the output. This capacitor has

a value that guarantees stable operation of the opamp
AOL
down to a gain of unity. In the case of an uncompensated
opamp, this capacitor needs to be connected externally.
In that case, we have a control on the slew-rate speci-
fication. We can sacrifice stability to achieve a higher
Gain (dB)
slew rate. Slew rates of up to 10 V/s are usually avail-
able in general-purpose opamps. The slew rate limits the
large signal bandwidth. The peak-to-peak output voltage
swing for a sinusoidal signal (Vp-t-p), slew rate (SR) and
bandwidth (highest frequency, fmax) are interrelated by
the following equation:
SR
fmax =
p Vp-t-p (16.58)
0
fT
Frequency (Hz)
Figure 16.24| Relation between the open-loop gain and

dV the operating frequency of an opamp.
dt
t=0 t=0
Vin + 16.7.2.5Power Supply Rejection Ratio
Vout
The power supply rejection ratio (PSRR) is defined as
the ratio of change in the power supply voltage to cor-
responding change in the output voltage. Similar to
Figure 16.23| Slew rate measuring circuit.
CMRR, we can realize that PSRR too is a DC parameter
and its value falls with increase in frequency.
16.7.2.3Open-Loop Gain 16.7.2.6Input Impedance

The open-loop gain is the ratio of single-ended output The input impedance is the impedance looking into the
to the differential input in the absence of any positive input terminals of the opamp and is mostly expressed
or negative feedback. The ratio of the open-loop gain to in terms of resistance only. In the case of real devices,
the closed-loop gain (which depends upon the applica- it could vary from hundreds of kilo-ohms for some low-
tion circuit) is called the loop gain. The gain error at grade opamps to tera-ohms for high-grade opamps.
any given frequency is given by the ratio of the closed-
loop gain to the open-loop gain. Thus a higher open-loop
gain gives a smaller error for a given closed-loop gain. 16.7.2.7Output Impedance
The practical opamps have open-loop gain in the range
of 10,000 to 100,000. Figure 16.24 shows the relation The output impedance is defined as the impedance
between the open-loop gain and the operating frequency. between the output terminal of the opamp and ground
and is in the range of 10 to 100 .
16.7.2.4Common Mode Rejection Ratio
16.7.2.8Settling Time
The common mode rejection ratio (CMRR) is a measure
of the ability of the opamp to suppress common mode The settling time is a parameter specified in the case
signals. The ratio CMRR is usually expressed as of high-speed opamps or the opamps with a high value
of gain-bandwidth product. It is expressed as the time
Ad taken by the opamp output to settle within a specified
CMRR = (16.59)
Ac percentage of the final value, usually 0.1% or 0.01% of
the final expected value, in response to a step at its input.
In decibels, CMRR is given by The settling time is usually specified for opamp wired as
a unity gain amplifier and it worsens for a closed-loop
Ad
CMRR (in dB) = 20 log
Ac
(16.60) gain greater than 1.

16.7.2.9Offsets and Offset Drifts 16.7.3.6Norton Opamps or Current

Differencing Opamps
We need to apply a DC differential voltage externally
to the inputs of the opamp to get a zero output. This While in a conventional opamp, the input stage is a
externally applied input is referred to as the input offset differential amplifier to achieve inverting and non-
voltage. This parameter may be as large as 5 mV in general- inverting input functions, in the case of a Norton opamp
purpose opamps and as small as 200 V in low offset (Fig. 16.25), the non-inverting input function is derived
opamps. The input offset voltage is often a function of from the inverting input function by using a current
power supply voltages. This variation is expressed in mirror configuration. The non-inverting input current is
terms of PSRR. The output offset voltage is the voltage derived from the one entering at the inverting input.
at the output with both the input terminals grounded. Differential input current is considered in the case of a
Another offset parameter is the input offset current. It Norton opamp and they operate from a single supply.
is the difference between the two bias currents flowing
towards the inputs of the opamp. Yet another important
opamp parameter is the input bias current. It is defined
as the average of the two bias currents flowing into the
+
two input terminals of the opamp.
Figure 16.25| Norton opamp.

16.7.3 Types of Opamps
16.7.3.7Instrumentation Opamps
16.7.3.1General-Purpose Opamps
An instrumentation opamp [Fig. 16.26(a)] is a differen-
The term general-purpose opamp is generally used with tial amplifier with a very high value of input impedance,
reference to that category of opamps which has moderate very large CMRR and extremely low values of offsets
or say reasonably good values for all the key parameters. and offset drifts. Gain in an instrumentation opamp, if
we so call it, is usually set with a single resistor whereas
in a conventional opamp, the same in achieved with the
16.7.3.2High-Speed Opamps
help of two resistors. Typical internal schematic of an
instrumentation opamp is shown in Fig. 16.26(b). It is
The high-speed opamps have high slew rate and band-
a combination of three opamps and the output opamp
width specifications of the order of hundreds of volts per
has been wired as a differential amplifier with its non-
microsecond and few GHz, respectively.
inverting and inverting inputs fed from the outputs of the
other two opamps wired as non-inverting amplifiers.
16.7.3.3Precision Opamps The gain setting resistor (Rgain) is connected external to the
device. Thus the two major problems in a conventional
Precision opamps have extremely low offsets (several opamp, namely, the low effective input impedance load-
tens of microvolts) and a very high value of open-loop ing on to the signal source with comparatively high
differential gain of the order of 120 dB. value of output impedance and the gain setting requir-
ing simultaneous adjustment of two resistors leading to
16.7.3.4Power Opamps inaccuracies are overcome. Instrumentation opamps are
used for amplifying low-level differential signals with
Opamps with supply voltage rating of the order of sev- high value of common mode content.
eral hundred volts and current delivering capability of
16.7.3.8Isolation Opamps
the order of several amperes are called power opamps.
An isolation opamp is again a differential input, single-
16.7.3.5Opamps Comparators ended output amplifier with its output electrically iso-
lated from the input. Isolation impedance as high as 1012
These have much faster response time (typically from a and isolation voltage of about 1000 V are common.
few ns to several tens of ns) than that of a conventional The differential amplifier in an isolation opamp may be
general purpose opamp (typically of the order of 1 s). an ordinary differential amplifier or an instrumentation
Comparator, in which one of the inputs is normally a amplifier. Figure 16.27 shows the circuit symbol of iso-
reference voltage, switches between two states at the lation opamp. There are transformer-coupled isolation
output depending upon whether the value of the other opamps mainly used in applications where linearity, gain
input is higher or lower than the reference voltage. accuracy, etc. are important and there optically coupled

16.8 FEEDBACK IN AMPLIFIERS 341
V1 +

R1
R2 R3

Rgain Vo
+
R2 R3
R1
+
V2
+
(a) (b)
Figure 16.26| Instrumentation opamp.
isolation opamps used in applications where speed and feedback is equal to the percentage variation in
bandwidth are important. gain without feedback divided by the desensitivity
parameter D.
+ 2. Effect on bandwidth: The bandwidth increases with

the introduction of negative feedback.

(BW )f = BW (1 + bA) (16.63)
Figure 16.27| Isolation opamp.
where (BW)f is the bandwidth with feedback and
BW is the bandwidth without feedback.
16.8 FEEDBACK IN AMPLIFIERS
3. Effect on non-linear distortion: The non-linear dis-
tortion decreases by the desensitivity factor D =
The gain with feedback Af is related to the gain without (1 + bA).
feedback A by 4. Effect on noise: The noise decreases with feedback
A as given in Eq. (16.64):
Af = (16.61)
1 + bA
N
where b is the feedback factor. Nf =
1 + bA
(16.64)
16.8.1 Advantages of Negative Feedback where Nf is the noise with feedback and N is the
noise without feedback.
1. Desensitivity (or Stability) of gain
5. Effect on input resistance: In the case of voltage-
dAf 1 dA

(1 + bA ) A
= (16.62) series and current-series feedback, the input resis-
Af tance with feedback Rif is given by Eq. (16.65):
where |(1 + bA)| is called the desensitivity param-
eter D. Thus, the percentage variation in gain with Rif = Ri (1 + bA) (16.65)

where Ri is the input resistance without feedback. 16.8.2 Feedback Topologies

The input resistance in the case of voltage-shunt
and current-shunt feedback is given by Eq. (16.66): Based on the nature of sampled signal and the mode in
which it is fed back to the input, there are four feedback
Ri topologies. These include the following:
Rif = (16.66)
1 + bA 1. Voltage-series feedback topology (also known as
seriesshunt topology)
Hence, the input resistance increases with introduc- 2. Voltage-shunt feedback topology (also known as
tion of voltage-series and current-series feedback and shuntshunt topology)
decreases for voltage-shunt and current-shunt feedback. 3. Current-series feedback topology (also known as
6. Effect on output resistance: The output resistance seriesseries topology)
with feedback (Rof) in the case of voltage-series 4. Current-shunt feedback topology (also known as
and voltage-shunt feedback is given by Eq. (16.67) shuntseries topology)
and current-series and current-shunt feedback by
Eq.(16.68): 16.8.2.1Voltage-Series (Series-Shunt)
Feedback
Ro
Rof = (16.67)
1 + bA In the case of voltage-series (series-shunt) feedback,
output voltage is sampled and mixed in series with the
Rof = Ro (1 + bA) (16.68) externally applied input signal (Fig. 16.28).
The gain parameter is given by
Hence, the output resistance decreases with
introduction of voltage-series and voltage-shunt AV
AVf = (16.69)
feedback and increases for current-series and cur- (1 + bAV )
rent-shunt feedback. where AV is voltage gain without feedback taking into
Most of the above-mentioned advantages account the load resistance RL, AVf is the voltage gain
(increased linearity, increased bandwidth etc.) with feedback taking into account the load resistance
come at the cost of reduced gain. Closed-loop gain RL, and b is the feedback factor. The input resistance
is smaller than the open-loop gain and the quan- with feedback (Rif) is given by
tum of reduction depends upon the open-loop gain
Ri
and the feedback factor. It, in fact, depends upon = Ri (1 + bAV ) (16.70)
{
1 bAV (1 + bAV ) }
Rif =

the product of the two called the loop gain.
Rs Ii Io
Ro +
Is
+ +
Vs Vi Ri AvVi Vo RL

Vf +
+
+
bVo Vo

Figure 16.28| Voltage-series or seriesshunt feedback.

16.8 FEEDBACK IN AMPLIFIERS 343
where Ri is the input resistance without feedback and AV with feedback RMf in terms of transresistance without
is the voltage gain without feedback taking load resis- feedback RM and the feedback factor b.
tance (RL) into account. AV is given by
RM
RL RMf =
1 + bRM
(16.73)
AV = Av (16.71)
Ro + RL
The input resistance with feedback (Rif) is given by
where Av is the open-circuited voltage gain without feed-
back, that is, the voltage gain without feedback without Ri
taking load resistance (RL) into account. The output Rif = (16.74)
resistance with feedback (Rof) is given by 1 + bRM
Ro where Ri is the input resistance without feedback and

Rof = (16.72)
1 + bAv RM is the transresistance taking load resistance RL into
account. RM is given by
where Ro is the output resistance without feedback and
Rof is the output resistance with feedback with RL= .
RL
Considering the effect of load resistance RL, the output RM = Rm (16.75)
resistance with feedback is given by parallel combination Ro + RL
of Rof and RL.
where Rm is the open-circuit transresistance, that is,
Common-drain and common-collector amplifier con- without taking the load resistance RL into account and
figurations are examples of voltage-series feedback
can be expressed as Rm = lim RM. The output resis-
having 100% feedback with the result that the closed RL
loop gain is approximately unity. A non-inverting ampli- tance with feedback (Rof) is given by
fier circuit configured around an opamp is yet another
example of voltage-series feedback. Ro
Rof = (16.76)
1 + bRm
16.8.2.2Voltage-Shunt (ShuntShunt)
Feedback Remember that Rof is the output resistance with feed-
back with RL = . Considering the effect of load resis-
In the case of voltage-shunt (shuntshunt) feedback, tance RL, the output resistance with feedback Rof is
output voltage is sampled and mixed in shunt with the given by parallel combination of Rof and RL.
externally applied input signal (Fig. 16.29). Common-emitter amplifier with collector-to-base
The gain parameter in this case is the transresistance. feedback as shown in Fig. 16.30 is an example of voltage-
Equation (16.73) gives the expression for transresistance shunt feedback.
Ro +
Ii
+
Is Rs Vi Ri RmIi Vo RL

If
If +
bVo Vo
Figure 16.29| Voltage-shunt (shuntshunt) feedback.

VCC Rif = Ri (1 + b GM ) (16.78)

where Ri is the input resistance without feedback, GM
RC is the transconductance taking load resistance RL into
RB account. GM is expressed as follows:
+ Ro
Co GM = Gm (16.79)
Q1 Ro + RL
+ where Gm is the short-circuit transconductance, that is,
Rs Ci Vo
without taking the load resistance RL into account. It is
+ Vi also expressed as Gm = lim GM. The output resistance
Vs RL 0
with feedback (Rof) is given by
Rof = Ro (1 + b Gm ) (16.80)
Figure 16.30| Common-emitter amplifier with where Ro is the output resistance without feedback.
collector-to-base feedback. Remember that Rof is the output resistance with feed-
Figure 16.31 shows the opamp version of voltage-shunt back with RL = . Considering the effect of load resis-
feedback topology. The circuit shown is that of an invert- tance RL, the output resistance with feedback Rof is
ing amplifier. The input current given by (Vs/Rs) flows given by parallel combination of Rof and RL.
through the feedback resistance Rf to produce an output Common-emitter amplifier with unbypassed emit-
voltage equal to (-Is Rf). The gain parameter is the ter resistor is an example of current-series feedback.
transresistance Rf. Similarly, common-source amplifier with unbypassed
Rf source resistor is also a case of current-series feedback.
Also, an opamp wired as a non-inverting amplifier, where
the output taken is current across the feedback resistor
+V is an example of current-series feedback.
Rs Is

Vo 16.8.2.4CurrentShunt (ShuntSeries)
+ + Feedback
Vs V In the case of current-shunt (shuntseries) feedback,
output current is sampled and mixed in shunt with the
externally applied input signal (Fig. 16.33). The gain
parameter in this case is the current gain. Equation
(16.81) gives the expression for current gain with feed-
Figure 16.31| Opamp-based inverting amplifier. back AIf in terms of current gain without feedback AI
and the feedback factor b.
16.8.2.3Current-Series (SeriesSeries) AI
AIf = (16.81)
Feedback 1 + bAI
The input resistance with feedback (Rif) is given by
In the case of current-series (seriesseries) feedback,
Ri
the output current (usually a voltage proportional to the Rif = (16.82)
output current) is sampled and mixed in series with the 1 + bAI
externally applied input signal (Fig. 16.32). where Ri is the input resistance without feedback. AI is
The gain parameter in this case is the transconduc- the current gain without feedback taking load resistance
tance and is given by RL into account. AI is given by
Ro
GM AI = Ai (16.83)
(Ro + RL )
GMf = (16.77)
1 + b GM
where GMf is transconductance with feedback, GM is where Ai is the current gain without taking the load resis-
transconductance without feedback and b is the feed- tance RL into account. In fact, it is the short circuited
back factor. The input resistance with feedback (Rif) is current gain. It can also be expressed as Ai = lim AI
RL 0
given as The output resistance with feedback (Rof) is given by

16.9 POWER AMPLIFIERS 345
Rs Ii Io
+
Is
+
Vs Vi Ri Ro Vv RL
GmVi
Vf +
+ Io
bIo

Figure 16.32| Current-series (seriesseries) feedback.
Ii +
Io
Is Rs Vi Ri AiIi Ro Vo RL
If Io
If
bIo
Figure 16.33| Current-shunt (shunt-series) feedback.
Rof = Ro (1 + bAi ) (16.84) current amplifier. This circuit too has current-shunt
feedback. The feedback factor in this case is given by
where Ro is the output resistance without feedback. [R1/(R1 + R2)].
Remember that Rof is the output resistance with feed-
back with RL= . Considering the effect of load resis-
tance RL, the output resistance with feedback Rof is 16.9 POWER AMPLIFIERS
given by the parallel combination of Rof and RL.
A cascade arrangement of two common-emitter amplifier
stages with feedback from emitter of the second stage to Large signal or power amplifiers provide power amplifi-
the base of the first stage is an example of current-shunt cation and are used in applications to provide sufficient
feedback. Figure 16.34 shows opamp-based inverting power to the load or a power device. The output power

+V
Io
Vo
Is + Input
t
signal
V RL
R2
R1
Current
Figure 16.34| Opamp-based inverting current amplifier.

in the active
device
delivered by these amplifiers is of the order of few watts

to few tens of watts.
t
360
16.9.1 Classification
16.9.1.1Class A Amplifiers Figure 16.35| Input and output waveforms of class A

amplifiers.
The active device in a class A amplifier is so biased that
it operates over the linear region of its output charac- VCC
teristics during the full period of the input cycle and the
output signal is an amplified replica of the input signal
with no clipping. Class A amplifiers offer very poor effi-
ciency and a theoretical maximum of 50% efficiency is
possible in these amplifiers. They are generally used for RB1 RC
implementing small-signal amplifiers.
Figure 16.35 shows the input and output waveforms Vo
of class A amplifiers. There are three class A amplifier Co
configurations. These configurations are discussed in the
Vi Power
following paragraphs.
Ci transistor
Class A amplifier with direct-coupled resistive load:
A simple transistor amplifier shown in Fig. 16.36 is a
class A amplifier with direct-coupled resistive load or a RB2
series-fed class A amplifier. The AC output power deliv- RE
ered to the load (Po) is given by
2
Po = Vce(RMS)I c(RMS) = I c(RMS) RC (16.85)
where Vce(RMS) is the RMS value of the collectoremitter Figure 16.36| Class A amplifier with direct-coupled
voltage, Ic(RMS) is the RMS value of the collector current resistive load.
and RC is the load resistance. The maximum efficiency is given by the ratio of the
The maximum value of power output [Po(max)] is maximum AC output power given in Eq. (16.86) to the
given by input power given in Eq. (16.87). The maximum value of
V (VCC /RC ) VCC
2 efficiency is equal to 25%.
Po(max) = CC = (16.86) Transformer-coupled class A amplifier: Class A amplifier
8 8RC
with transformer-coupled load employs a transformer-
The value of input power (Pi) given by coupled output stage as shown in Fig. 16.37. This config-
VCC V 2 uration offers better efficiency as compared to a class A
Pi = VCC ICQ = VCC = CC (16.87) amplifier with a resistive load. This is so because in the
2RC 2RC case of direct coupling, the transistor quiescent current

passes through the load resistance which results in wastage collector current values are IC(max) and IC(min), respec-
of power as it does not contribute to the AC component tively, then the AC power developed across the trans-
of the output power. In the case of a transformer-coupled formers primary Po is given by
load, the primary of the transformer has negligible DC
resistance; therefore, there is negligible power loss. [VCE(max) VCE(min) ] [IC(max) IC(min) ]
Po = (16.89)
8
VCC
The power delivered to the load (Po) is then given by the
product of the transformers efficiency and the power devel-
N1 N2 oped across the transformers primary given in Eq. (16.89).
RB1 RL V1 V2 RL As the efficiency of efficient transformers is well above 90%,
the power delivered to the load (Po) can also be approxi-
mated by Eq. (16.89). The efficiency (h) is given by
VCE(max) VCE(min)
h = 50
Vi
%
Power (16.90)
Ci transistor VCE(max) + VCE(min)
Therefore, the upper limit for theoretical efficiency for

RB2 RE a transformer-coupled class A power amplifier is 50%
which is twice that of a class A amplifier with direct-
coupled resistive load.
Class A pushpull amplifiers: Figure 16.38 shows the
Figure 16.37| Transformer-coupled class A amplifier.
circuit configuration of a class A pushpull amplifier. In
this configuration, the DC component and the even har-
monic terms get cancelled. The main source of distortion
The output AC power delivered to the load (Po) can be is the third harmonic component instead of the second
determined using harmonic component.
V2(RMS)2 16.9.1.2Class B amplifiers

Po = (16.88)
RL
In a class B amplifier, the active device is biased at zero
where V2(RMS) is the RMS value of the voltage across DC level. Therefore, it provides an output signal vary-
the transformers secondary. If the maximum and the ing over one-half of the input signal cycle as the active
minimum collectoremitter voltages are VCE(max) and device conducts for only one-half of the input signal
VCE(min), respectively, and the maximum and minimum cycle (Fig. 16.39). To obtain output for full input cycle,
Q1
Rs Ic1
T1
+ T2
R1
+ Vi1 N1
Vi N2

RL
R2 VCC
Vi2 N1
+
Q2 Ic2
Figure 16.38| Class A pushpull amplifier.

Current
in the active
Input device
t t
signal 180
Figure 16.39| Input and output waveforms of class B amplifier.
Q1
Ic2
Rs
T1
+ T2
+ Vi1 N1
Vi N2 RL

VCC N1
Vi2
+
Q2 Ic2
Figure 16.40| Transformer-coupled pushpull class B amplifier.
pushpull configuration is used. It may be mentioned PNP) to obtain a full-cycle output across the load with
here that class B amplifiers offer higher efficiency than each transistor operating for half cycle (Fig. 16.41).
class A amplifiers using a single active device.
A number of circuit arrangements are possible for
obtaining class B operation. These include transformer- Rs
coupled pushpull configuration, complementary-symmetry Ic1
Q1
pushpull configuration and quasi-complementary push
pull configuration. + +
VCC1
Transformer-Coupled pushpull class B amplifier: Figure Vi
16.40 shows the circuit for a transformer-coupled pushpull
class B amplifier. The maximum possible conversion effi- RL
ciency is equal to 25p which is equal to 78.5% as com-
pared to that of 50% in class A amplifiers. There is no
even-harmonic distortion. The principal contributor to the Ic2
harmonic distortion is the third harmonic distortion com- +
VCC2
ponent. Crossover distortion refers to the non-linearity in
the output signal when the output signal crosses from posi-
tive to negative or from negative to positive. The output Q2
of the transistor collector current is not a perfect half-sine-
wave and it results in crossover distortion.
Complementary-symmetry pushpull class B amplifier: Figure 16.41| Complementary-symmetry pushpull
They make use of complementary transistors (NPN and class B amplifier.

Quasi complementary-symmetry pushpull class B ampli- They sacrifice some efficiency over class B amplifiers
fier: Quasi complementary-symmetry pushpull class B but they offer better linearity than class B amplifiers.
amplifier is shown in Fig. 16.42. One of the main advan- However, they offer much more efficiency than class A
tages of using the quasi complementary-symmetry con- amplifiers. Figure 16.43 shows the waveforms of class
figuration is that it employs matched NPN transistors as AB amplifiers.
high current devices and does not require a high-power Class AB amplifiers do not suffer from the problem of
PNP transistor as required in case of complementary- crossover distortion as in these amplifiers a small current
symmetry pushpull amplifiers. It may be mentioned flows even at zero input signal level. Figure 16.44 shows
here that quasi complementary-symmetry pushpull the configuration of a class AB pushpull amplifier.
class B amplifier is the most popular form of power
amplifiers. 16.9.1.4Class C Amplifiers
16.9.1.3Class AB Amplifiers Class C amplifiers conduct for less than 50% of the input
signal (Fig. 16.45) resulting in a very high efficiency upto
In a class AB amplifier, the amplifying device con- 90%. However, they are associated with a very high level
ducts for a little more than half of the input waveform. of distortion at the output.
+VCC
R1 Q1
C1
Darlington
pair
Q3 C3
Vi
R2
Q2
+
Feedback
C2 RL Vo
pair
R3
Q4
Figure 16.42| Quasi complementary-symmetry pushpull class B amplifier.
Current
in the active
Input device
t t
signal >180
Figure 16.43| Input and output waveforms of class AB amplifiers.

Q1 Ic1
Rs R1
T1
T2
+
+ RE
Vi1 N1
Vi N2 RL

Vi2 R2 VCC N1
+ RE
Q2
Ic2
Figure 16.44| Class AB pushpull amplifier.
Current
in the active
Input device
t t
signal
Figure 16.45| Input and output waveforms of class C amplifiers.
+VCC are widely used as radio frequency (RF) and intermedi-

ate frequency (IF) amplifiers. They offer very high effi-
ciencies of the order of 90%.
16.9.1.5Class D Amplifiers
L C
Class D amplifiers use the active device in switching mode
to regulate the output power. Hence, these amplifiers offer
Vo high efficiency (of the order of 90%) and do not require heat
sinks and transformers. These amplifiers use pulse width
modulation (PWM), pulse density modulation or sigma
Vi delta modulation to convert the input signal into a string
of pulses. Class D amplifiers can be built using two basic
RFC topologies, namely, the half-bridge topology and the full-
bridge topology. The half-bridge topology makes use of two
VBB active devices whereas the full-bridge topology makes use
of four active devices.
Figure 16.46| Tuned-mode class C amplifier.
16.9.1.6Other Classes of Amplifiers
Class C amplifiers operate in two modes, namely, the
tuned mode (Fig. 16.46) and the untuned mode. Only Class E and class F amplifiers are switching power
a small portion of the input cycle is passed through the amplifiers offering very high efficiency levels. They are
amplifier. This distorts the input signal and hence class used at very high frequencies where the switching time
C amplifiers are not used for audio applications. They is comparable to the duty time.

16.9.2 Power Amplifier Characteristics A3

D3 = 100% (16.98)
The main characteristics that define the performance A1
of a power amplifier are efficiency, distortion level and The fourth harmonic distortion component (D4) is given by
output power.
A4
D4 = 100% (16.99)
16.9.2.1Efficiency A1
The total harmonic distortion (D) is given by the square
The efficiency of an amplifier is defined as the ability of root of the mean square values of the individual harmonic
the amplifier to convert the DC power of the supply into components.
an AC signal power that can be delivered to the load.
The expression for efficiency is given by D = D22 + D32 + D42 + (16.100)
P
h = o 100% (16.91) The power delivered at the fundamental frequency (P1) is
Pi
A12RL
where Po is the AC power delivered to the load and Pi P1 = (16.101)
the DC input power. 2
The total power output (P) is given by
16.9.2.2Harmonic Distortion RL
P = (A12 + A22 + A32 + ) (16.102)
2
The harmonic distortion refers to the distortion in the
amplitude of the output signal of an amplifier caused due Therefore,
to the non-linearity in the characteristics of the active
P = (1 + D22 + D32 + ) P1 = (1 + D2 ) P1 (16.103)
device used for amplification. The distortion is more in
the case of a large input signal level. Equations (16.92)
to (4.96) give the values of amplitude components of the 16.9.3 Thermal Management of Power
DC, the input signal, second, third and fourth harmonic Transistors
components of the input signal.
1 The power transistors are used as active devices in power
A0 = (I max + 2I+1/2 + 2I1/2 + I min ) IQ (16.92) amplifiers. The maximum power that can be handled by
6
an active device is related to its junction temperature,
1
A1 = (I max + I+1/2 I1/2 I min ) (16.93) as the power dissipated by the device causes an increase
3 in its junction temperature. The average power dissi-
1 pated by the transistor (PD) can be approximated by
A2 = (I max 2IQ + I min ) (16.94)
4 Eq. (16.104):
1 PD = VCE IC (16.104)
A3 = (I max 2I+1/2 + 2I1/2 I min ) (16.95)
6
where VCE is the collectoremitter voltage and IC is the
1
A4 = (I max 4I+1/2 + 6IQ 4I1/2 + I min )(16.96) collector current. This power dissipation is allowed upto
12 a certain temperature, above which the value of power
where, dissipation capability decreases linearly with increase in
Imax is the output current for maximum value of input signal. temperature such that it reduces to zero at the maxi-
Imin is the output current for minimum value of input signal. mum device case temperature. Larger the power handled
IQ is the output current for zero value of input signal. by the transistor, higher is the case temperature. It may
I+1/2 is the output current at one half the maximum posi- be mentioned here that the silicon transistors offer larger
tive value of input signal. maximum temperature ratings than germanium tran-
I-1/2 is the output current at one half the maximum nega- sistors. Figure 16.47 shows the typical power derating
tive value of input signal. curve for a silicon power transistor.
The second harmonic distortion component (D2) is given
Therefore, the limiting factor in the power-handling
by
capability of a transistor is its maximum permissible
A2 collector junction temperature. Power transistors gener-
D2 = 100% (16.97)
A1 ally have large metal cases to provide a large area from
which the heat generated by the device may be trans-
The third harmonic distortion component (D3) is given ferred. The power-handling capability of the device can
by be enhanced either by the use of heat sinks or by making

use of thermoelectric coolers. Thermoelectric coolers

PD(max) are solid-state heat pumps and are used in applica-
tions which require cooling below the ambient tem-
Maximum power
perature, or where temperature cycling or precise

dissipated
temperature stabilization is required. Thermoelectric

coolers are based on the Peltier effect, according to
which the DC current applied across two dissimilar
materials results in a temperature differential. These
coolers transfer heat from one side of the active device
0 50 100 150 200 Case
temperature (C)
to the other side against the temperature gradient.
The cooling effect depends upon the amount of DC
Figure 16.47| Typical power derating curve for a current and how well the heat from the hot side can
silicon power transistor. be removed.
IMPORTANT FORMULAS
1. For single-stage amplifier, the current gain or the 9. For a Darlington amplifier, the voltage gain is
current amplification is
Vo h
hf Av = 1 ie
Ai = Vi Z i2
1 + ho RL
10. For a Darlington amplifier, the overall input
2. For single-stage amplifier, the input impedance is
impedance is
hhR
Zi = hi + hr A i RL = hi r f L (1 + hfe )2RE2
Ai RE2
1 + ho RL Zi = Ai RE2
Av 1 + hoe hfe RE2
3. For single-stage amplifier, the voltage gain is
AR
Av = i L 11. For a Darlington amplifier, the output impedance
Zi is
4. For single-stage amplifier, the voltage gain taking Rs + hie hie
Rs into account is Zo 2
+
(1 + hfe ) 1 + hfe
V Zi
A vs = Av i = Av 12. For an opamp:
Vs Zi + R s
SR
fmax =
5. For single-stage amplifier, the output admittance is p Vp-t-p
hf hr
Y o = ho 13. The common mode rejection ratio is
hi + Rs
A
6. For a multistage amplifier, the overall gain (Av) is CMRR (in dB) = 20 log d
given by Ac
A v = A v1 A v2 A vn
14. For the negative feedback amplifiers:
7. For a multistage amplifier, the overall current gain A
Af =
1 + bA
is given by
Z
A i = A v i1 15. For the negative feedback amplifiers:
RL
(BW )f = BW (1 + bA)
8. For a Darlington amplifier, the current gain is
16. For the negative feedback amplifiers:
(1 + hfe )2
Ai
1 + hoe hfe RE2
N

Nf =
1 + bA

SOLVED EXAMPLES 353
17. For the voltage-series and current-series feedback 19. For voltage-series and voltage-shunt feedback
amplifiers: amplifiers:
Rif = Ri (1 + bA) Ro
Rof =
1 + bA
18. For the voltage-shunt and current-shunt feedback
amplifiers: 20. For current-series and current-shunt feedback
amplifiers:
Ri
Rif = Rof = Ro (1 + bA)
1 + bA
SOLVED EXAMPLES
1. Calculate the efficiency of the amplifier circuit Therefore,

shown in the following figure. The input voltage VCEQ = VCC ICQRC IEQRE
= (25 403.2 10-3 25 403.2 10-3 10) V
applied is such that it produces a base-current
of 10 mA peak. Given that the transistors base
emitter voltage is equal to 0.7 V and b is equal to 40. = 10.91 V
25 V The input power is
Pi = VCC ICQ
= 25 403.3 10-3 W
25 = 10.08 W
2 k
Vo The output power is
Co IC(p)2 RC
Vi Po =
Ci 2
Therefore,
IC(p) = b IB(p)
10
= 40 10 10-3 A
= 400 mA
Thus,
(400 103 )2 25
(a) 25.4% (b) 18.7%
(c) 19.84% (d) 21.23% Po = W = 2W
2
Solution. Let VCC = 25V. The value of base cur- Therefore, the efficiency is
rent at the Q-point is given by
P 2
h= o 100% = 100% = 19.84%
VCC 0.7 Pi 10.08
IBQ =
RB + (b + 1)RE Ans. (c)
25 0.7 2. Refer to circuit shown in the following figure. Which
= A
2 10 + 41 10
3 of the following statements is correct? Given that
= 10.08 mA the h-parameters of the transistor are hie = 1 k,
hfe = 100, hoe = 40 10-6 mhos.
The value of collector current at Q-point is S1: Input impedance is less than 1 k and output
-3
ICQ = b IBQ = 40 10.08 10 A impedance is less than 2 k
S2: The value of current gain is approximately 47
= 403.2 mA and the value of voltage gain is approximately 179.

15V The current gain Ai is given by
hfe RF1[RF2RC(1/hoe )]
Ai =
2 k (RF1 + hie )[RF2RC(1/hoe ) + RC ]
100 k 50 k 100 100 103 (50 103 2 10325 103 )
=
(100 103 + 1 103 ) (50 103 2 103 25 103 + 2 103 )
Vo
10 F
107 1.79 103
= = 46.76
Vi 101 103 3.79 103
10 F
0.01 F Ans. (c)
Zo
3. For the circuit shown in the following figure, what
Zi
is the value of voltage gain? Given that gm = 0.05,
b = 100.
(a) S1 only (a) 100 (b) 80
(b) S2 only (c) 44.44 (d) 40
(c) both S1 and S2
(d) Both S1 and S2 are incorrect Vo
RB1
Solution. The AC equivalent circuit for the ampli- Vs 2.5 k
fier is shown in the following figure.
Ii Io RC = 2 k
RB2
Vi Ib Vo 2.5 k RE2
CE
2.5 k
0.1F
100 k 1 k 100Ib 25 k 50 k 2 k
Zi Zo
Solution. We now that
The input impedance is b = gm rp
Zi = RF1 hie Therefore,

= 100 10 1 10
3 3
100
rp = = 2 k
= 0.99 kW 0.05
The output impedance (Zo) is given by The voltage across the base terminal is
Zo = RF2 RC (1/hoe ) 25 103 || 2 103

Vb = Vs
= 50 1032 10325 103 (25 103 || 2 103 ) + ( 2.5 103 )
= 1.79 103 2
Vs
= 1.79 kW 4. 5
The voltage gain Av is given by Also,

hfe [ RF2 RC (1/hoe )] Vo = gm Vb RC
Av =
hie
Therefore,
-100 1.79 103
= 2
1 103 Vo = 0.05 Vs 2 103 = (44.44)Vs
= 179 4.5

SOLVED EXAMPLES 355
Hence, swing of 8 mA. The output characteristics of the

Vo transistor are shown in the following figure (b).
Av = = 44.44
Vs
12 V
Ans. (c)
4. A voltage amplifier is a cascade arrangement of
30 10
three identical amplifier stages each having an open
10 k 8
loop gain of A1. The output from the final stage is
fed back in series and phase opposition with the
input of the first stage to get an overall closed loop AC input
gain of Af. What is the relation between the overall signal
Ci
open loop gain A in terms of open loop gain stabil-
ity |dA1/A1| of individual stages and overall closed
loop gain stability |dAf/Af|. 1 k 10
dA1 A1
(a) A = A f
dA A
f f
dA1 A1
2 (a)
(b) A = 3A f
dA A
f f
IC(mA)
dA1 A1 IB = 14 mA
(c) A = 3A f
dA A 300
f f IB = 12 mA
dA1 A1
(d) A = 9A f
dA A
250 IB = 10 mA
f f
200
IB = 8 mA
Solution. Open loop gain, A = A13. Therefore, 150
dA = 3A12dA1. This gives IB = 6 mA
dA dA 3dA1 100
= 3A12 31 = IB = 4 mA
A
A 1 A1
50
IB = 2 mA
Now,
VCE (V)
dAf 1 dA 5 10 15 20 25
=
Af 1 + bA A (b)
Therefore,
dAf 1 3dA1 (a) 300 mW (b) 387.5 mW
= (c) 3.875 W (d) 38.75 mW
Af 1 + bA A1
Also, Solution. The DC load line is obtained by draw-
1 A ing a vertical line from the point (0, VCC), that is,
= f
1 + bA A from (0, 12 V). The intersection of this DC load
line with the curve corresponding to base current of
Therefore, 8 mA gives the operating point. From the following
dA1 /A1 figure, we can determine that the operating point is
A = 3A f
dA /A ICQ = 160 mA and VCEQ = 12 V.
f f
Ans. (c) The effective AC resistance seen by the primary is
N
2
30
5. What is the AC power delivered to the speaker in 2
RL = 1 RL = RL
the circuit shown in the following figure (a)? The
N2 10
value of the quiescent base current is 8 mA and the
input signal results in a peak-to-peak base current = 9 8 W = 72 W

IC(mA)
DC load line IB = 14 mA
300
AC load line IB = 12 mA
IC(max)=260 mA
250
IB = 10 mA
200
IB = 8 mA
Operating point
ICQ =160 mA
150
IB = 6 mA
100
IB = 4 mA
IC(min)= 60 mA
50
IB = 2 mA
VCE(max) VCE(min)V (V)
Po =20 CEIC(max) IC(min)
5 10 15 25
VCE(min) =4.5V VCE(max) =20V 8
(20 4.5) (260 103 60 103 )
VCEQ =12V
=
8
The AC load line is drawn with a slope of 1/72 15.5 200 103
= = 387.5 mW
going through the operating point. The intercept of 8
the load line on the y-axis is Ans. (b)
V 3 12
ICQ + CC = 160 10 + 72 A
6. The first dominant pole encountered in the
RL frequency response of a compensated opamp is
= 160 103 + 166.667 103 A
approximately at

(a) 5 Hz (b) 10 kHz
= 326.67 mA (c) 1 MHz (d) 100 MHz
The AC load line is drawn by joining the operating Ans. (a)
point (ICQ = 160 mA, VCEQ = 12 V) and the point
7. Negative feedback in an amplifier
(IC = 326.67 mA, VCE = 0). The AC load line is
shown in the above figure. The peak-to-peak base (a) reduces gain
current swing is 8 mA. Therefore, the peak base (b) increases frequency and phase distortions
current swing is 4 mA. The maximum and mini- (c) reduces bandwidth
mum values of the collector current and collector (d) increases noise
emitter voltage can be obtained from the graph Ans. (a)
shown in the above figure. VCE(min) = 4.5 V;
VCE(max) = 20 V; IC(min) = 60 mA and IC(max) = 8. In the cascade amplifier shown in the following
260 mA. The AC power delivered to the load is figure, if the common-emitter stage (Q1) has a
obtained as follows: transconductance, gm1, and the common-base stage
(Q2) has a transconductance (gm2), then the overall
VCE(max) VCE(min) IC(max) IC(min)
Po = transconductance g = (io/vi) of the cascade ampli-
fier is
8
(20 4.5) (260 103 60 103 ) (a) gm1 (b) gm2
=
8 (c) gm1/2 (d) gm2/2
15.5 200 103
= = 387.5 mW
8

SOLVED EXAMPLES 357
Q2 +15 V
io
vo
Vo
RL +
vi Q1
15V
Solution. We have (a) 0 V (b) 5 mV

io i i i (c) +15 V or 15 V (d) +50 V or 50 V
g= = c2 e2 c1 gm1
vi vi vi vi Solution. We have
Ans. (a)
Vo= Vio A
9. Cross-over distortion behavior is characteristic of
Here, Vio = 5 mV and A = 10,000; therefore,
(a) class A output stage
(b) class B output stage Vo = 5 10-3 10000 V = 50 V
(c) class AB output stage
(d) common-base output stage However, as the supply of the opamp is 15 V, the
Ans. (b) output voltage is limited to 15 V.
Ans. (c)
10. In the differential amplifier shown in the following
figure, if the source resistance of the current source 12. The ideal opamp has the following characteristics
IEE is infinite, then the common-mode gain is
(a) Ri = , A = , Ro = 0
(b) Ri = 0, A = , Ro = 0
VCC (c) Ri = , A = , Ro =
(d) Ri = 0, A = , Ro =
Ans. (a)
13. In a negative feedback amplifier using voltage-series

R R (i.e., voltage sampling, series mixing) feedback.
(a) Ri decreases and Ro decreases
Q2 (b) Ri decreases and Ro increases
Vin1 Vin2
(c) Ri increases and Ro decreases
Q1 (d) Ri increases and Ro increases
(Ri and Ro denote input and output resistances,
respectively.)
IEE Ans. (c)
14. A 741-type opamp has a gain-bandwidth product of

VEE 1 MHz. A non-inverting amplifier using this opamp
and having a voltage gain of 20 dB will exhibit a
(a) zero (b) infinite 3-dB bandwidth of
(c) indeterminate (d) finite.
Ans. (a) (a) 50 kHz (b) 100 kHz
(c) 1000/17 kHz (d) 1000/7.07 kHz
11. If the opamp shown in the following figure has an
input offset voltage of 5 mV and an open-loop volt- Solution. Gain-bandwidth = 1 106 Hz; Gain = 20
age gain of 10,000, then Vo will be dB = 10. Therefore, 3-dB bandwidth is

Gain-bandwidth 1 106 VDD = +10 V

= = 100 kHz
Gain 10
ID = 1 mA
Ans. (b)
15. An amplifier using an opamp with a slew rate, SR = RD = 3 k

1 V/s has a gain of 40 dB. If this amplifier has C2
tofaithfully amplify sinusoidal signals from DC to
20 kHz without introducing any slew rate induced +
distortion, then the input signal level must not
C1 Vo
exceed

(a) 795 mV (b) 395 mV +
(c) 79.5 mV (d) 39.5 mV
Solution. Vi R = 1 M
G
RS = 2.5 k CS
SR = 2pAVm fm

Therefore,
SR
Vm =
2pAfm
Solution. The voltage gain is
where A is the gain, Vm is the maximum value of A v = gm RD
input signal and fm is the input frequency. The gain
in dB is 40. Therefore, where
2IDSS VGS
20 log A = 40 gm = 1
VP VP
A = 100 Now,
VGS = VG VS = 0 IDRS = 1 10-3 2.5
Therefore,
103 V = 2.5 V
1 106
Vm = V = 79.5 mV Thus,
2 p 100 20 103
2IDSS VGS
gm = 1
Ans. (c) VP VP
2 10 103 2.5
1 5 = 2 mS
16. The voltage gain Av = Vo /Vi of the JFET ampli- =
fier shown in the following figure is (IDSS = 10 mA, 5
Vp = 5 V; assume C1, C2 and CS to be very large.) Therefore,
(a) +18 (b) -18 Av = 2 10-3 3 103 = 6
(c) +6 (d) -6 Ans. (d)

5 R/2
1. If the unity gain bandwidth of the operational R/2
amplifier shown in the following figure is 10 MHz,
then what is the bandwidth (in kHz) of the opamp- Vo
based amplifier? Vi +

Solution. We know that Solution. The input impedance is

Unity gain bandwidth = Gain Bandwidth 9 103 + (10 103 || 100 103) 18 k
The gain is given by Ans. (18)
R 5R/2 3. An amplifier has an open-loop gain of 100, an input

1 + F = 1 + = 6 impedance of 1 k, and an output impedance of
R R/2 100 . A feedback network with a feedback factor
The bandwidth is of 0.99 is connected to the amplifier in a voltage-
10 106 series feedback mode. What is the new input
Hz =1670 kHz impedance (in ohms)?
6
Solution. For voltage-series feedback amplifiers,
(Ans. 1670)
2. What is the approximate mid-frequency input Rif = Ri (1 + bA)
impedance (in k) of the JFET amplifier given in Therefore,
the following figure?
Rif = 1000 (1 + 0.99 100) = 1,00,000
15V (Ans. 100000)
4. For the case discussed in Question 3, what is the
100 k 3 k new output impedance (in ohms)?
AC Solution. For the voltage-series feedback amplifiers,

9 k output
signal Ro
Rof =
RL 1 + bA
Vi Therefore,
10k 3 k
=1 W
100
Rof =
1 + 0.99 100
Ans. (1)
PRACTICE EXERCISE
1. A cascade arrangement of relaxation oscillator and 3. The output behavior in the case of two identical
an integrator makes a differential amplifier configurations shown in the
following figures (a) and (b) was observed to be
(a) triangular waveform generator slightly different even though they were fed with
(b) square waveform generator identical differential inputs as shown in the Figures.
(c) sawtooth waveform generator Which opamp specification is responsible for this?
(d) pulse generator
(1 Mark) 1 Vp p
100 k
10 V
2. Introduction of hysteresis in a comparator makes it 10 k

(a) prone to false triggering caused by noisy input 10 k Vo
signal 10 V +
(b) immune to false triggering caused by noisy
100 k
input signal
(c) a square waveform generator
(d) none of these
(1 Mark) (a)

100 k 8. Heat sinks are used in power transistors to
1 Vp p (a) reduce the transistor power

(b) reduce the junction temperature
10 k
5V
(c) increase the ambient temperature
(d) increase the collector current
10 k Vo (1 Mark)
5V +
9. The circuit diagram shown in the following figure
100 k consists of transistors in
(a) parallel connection (b) cascade connection
(c) Darlington connection (d) cascade connection
(b)
C
(a) Voltage offset
(b) Current offset
(c) CMRR
(d) Both voltage and current offsets
(1 Mark) Q2
4. In one of the following feedback topologies, the
input impedance increases with introduction of
feedback.
(a) Voltage shunt feedback B Q1
(b) Current shunt feedback
(c) Voltage series feedback
(d) None of these
(1 Mark)
5. A voltage amplifier has an open loop gain of 100. E
If 10% negative feedback were introduced in the (1 Mark)
amplifier, then an 11% change in open loop gain 10. The following figure shows the basic circuit arrange-
would cause ment of one of the amplifiers types. It is
(a) 1% change in closed loop gain (a) a common-collector amplifier
(b) 11% change in closed loop gain (b) a common-emitter amplifier
(c) 1.1% change in closed loop gain (c) a common-base amplifier
(d) 0.1% change in closed loop gain (d) none of these
(1 Mark)
6. One of the following amplifier configurations has VCC
an inherent current-series feedback.
(a) Emitter follower
(b) Common base amplifier RB1
(c) Common emitter amplifier with bypassed emit-
ter resistor
(d) Common emitter amplifier with unbypassed
emitter resistor AC input
(1 Mark) signal
Ci AC output
7. It is desired to design a voltage controlled current
source. What type of negative feedback should pref- signal
Co
erably be introduced to make it a stable source? RB2
RE
(a) Voltage-series feedback
(b) Current-series feedback
(c) Current-shunt feedback
(d) Voltage-shunt feedback
(1 Mark) (1 Mark)

11. In a CC amplifier, the voltage gain was found (a) 6.6 (b) 6.6
moving more or less closer to unity as the peak of (c) 5.7 (d) 5.7
the excitation signal was increased. Is it true? VDD
(a) Yes
(b) No
(c) Depends on the circuit values RD = 10 k
Cc
(d) Depends upon the value of b
(1 Mark) Vo
12. The value of voltage gain for a CE amplifier is

R2 = 9 M
given by
(a) -gmRC, provided hre >> hie
(b) -RE/RC, provided hfe is large and hie << hfeRE
+
(c) -RC/RE, provided hfe is large and hie << hfeRC Vs RS = 1 k CS
(d) -RC/RE, provided hfe is large and hie << hfeRE R1 = 1 M

(RC is the resistor placed between the collector
terminal and the supply voltage, RE is the resis-
tor placed between the emitter terminal and the
ground) (2 Marks)
(1 Mark)
18. The following figures (a)(d) show some circuit
13. Input and output from a CE amplifier are fed to configurations. Which of the following statements
an oscilloscope to see their phase relationship. The are true?
Lissajous figure is
+VCC
(a) a straight line making an obtuse angle with the
positive x-axis
(b) an ellipse
(c) a circle
(d) a figure-eight pattern R3 R5 R7 R9
C3 C6
(1 Mark)
C1 Vo
14. An amplifiers overall voltage-gain is almost the
Q1 Q2 C5
same as the transistors voltage gain provided Vi
(a) hoRL << 1 (b) hoRL >> 1
R6 C2 R2
(c) hoRL = 1 (d) hoRL is infinite R4 R8 R10 C4
(1 Mark)
15. A cascade amplifier having three stages has sound-
to-noise (S/N) ratio of 60 dB for the first stage, 50
dB for the second stage and 40 dB for the third R1
state. The S/N ratio of the cascaded amplifier is
(a) 40 dB (b) 60 dB
(a)
(c) 150 dB (d) 50 dB
(1 Mark)
Rf
16. What is the percentage reduction in gain of an ampli-
fier due to introduction of 20 dB of negative feedback?
+V
(a) 100% (b) 90%
(c) 75% (d) 50% + Vo
(1 Mark) V
17. The following figure shows FET-based common
source amplifier circuit with voltage-series feedback
provided by series combination of R1 and R2. FET
is characterized by gm = 4000 S and rd = 10 k.
What is the value of voltage gain with feedback? (b)

VCC 15 V
RC1 RC2 RC = 470
RS +
Vo
+ Q1 Q2 Co
Vo
Vs R
Re Q2

(c) Vi
Ci Q1
+V
R1 R2

Vo RE
Ii +
V 15V
RL 15V
R2 (2 Marks)
21. Four different performance characteristics with ref-

R1 erence to operational amplifiers are shown in the
following figures (a)(d). Each of the characteris-
tics is related to one or more than one important
parameters of opamps. Identify the parameters
(d) that can be determined or calculated from the
given performance characteristics.
S1: Figure (a) shows voltage-series feedback and
figure (b) shows voltage-shunt feedback
S2: Both figures (c) and (d) show current-shunt AOL
feedback
S3: Figure (a) shows voltage-shunt feedback and
figure (b) shows voltage-series feedback
Gain (dB)
S4: Both figures (c) and (d) show current-series

feedback.
(a) S1 is TRUE (b) Both S1 and S2 are TRUE
(c) S2 is TRUE (d) Both S3 and S4 are TRUE
(1 Mark)
19. How much percentage of maximum power can be
dissipated by a transistor for an operating temper- 0
ature equal to its maximum junction temperature? Frequency (Hz) fT
(a) 100% (b) 10% (a)

(c) 50% (d) 0%
(1 Mark)
20. For the amplifier circuit shown in the following
dV
figure, what are the values of resistors RE and R1
such that the operating point of both the transis- dt
tors is ICQ = 10 mA and VCEQ = 10 V. Given that t=0 t=0
the value of b = 100, VBE of each transistor is Vin +
0.7V and R2 = 10 k. Vo

(a) RE = 530 , R1 = 6 k
(b) RE = 6.3 k, R1 = 7.5 k
(c) RE = 2.3 k, R1 = 3.74 k
(d) RE = 530 , R1 = 7.5 k
(b)

+V

C Vo
output swing (V)
+
Peak-to-peak
R
V L
R
Vi
(2 Marks)
0 23. The mid-frequency input impedance of the
Frequency (Hz) JFET amplifier given in the following figure is
(c) approximately
(a) 18 k (b) 9 k
Input voltage (V) Output voltage (V)
(c) 10 k (d) 3 k
Input over-drive
5 mV +V
15 V
Vin
100 k 3 k
+
Vo
Input over-
drive 100 mV
V AC
Input over-
9 k output
drive 20 mV signal
RL
Vi
10 k 3 k
(d)
(1 Mark)
(a) Figure (a): Open loop gain and unity crossover
24. A self-bias JFET amplifier is shown in the follow-
ing figure, Given that IDSS = 10 mA, Vp = 5 V,
frequency; Figure (b): Slew rate; Figure: (c)
rd = 50 k, VGSQ = 2.5 V and IDQ = 2.5 mA.
Response time; Figure (d): CMRR.
(b) Figure (a): CMRR; Figure (b): slew rate;
Figure (c): Response time; Figure (d): Power
bandwidth. VDD
(c) Figure (a): Open loop gain and unity crossover
frequency; Figure (b): Slew rate; Figure (c): RD = 3 k
Power bandwidth; Figure (d): Response time.
(d) Figure (a): Open loop gain and unity crossover Vo
frequency; Figure (b): Input and output offset Co
voltages; Figure (c): Response time; Figure (d):
Power bandwidth. Vi
(2 Marks) Ci
22. For the circuit shown in the following figure, the Zi RG = 2 M RS = 1 k

phase angle between Vo and Vi at w = 1/ LC is Zo
(Given that the opamp is ideal and R = L/C .
p
(a) (b) p
2
3p
(c) 2p (d) What is the value of Zi and Zo?
2

(a) 1 M, 1 k (b) 1.75 M, 1.1 k 28. The following figure shows a common collector
(c) 2 M, 0.97 k (d) 2 M, 2 k amplifier.
(2 Marks)
+VCC
value of Av?
(a) -1.95 (b) 1.95 R1
(c) -2.22 (d) +2.22 Rs Cc
Q1
(1 Mark) +
+ Cc
26. The following figure shows an amplifier circuit. Ri
Vs +
Vi
VCC R2 Re
Vo

RB1 RC
AC output
signal What is the value of gain of the amplifier?
AC input Co
Re
signal
Ci (a) AV hfe
RL Rs + hie
Re
(b) AV hfe +
RB2 RE CE
Rs + hie
R1 R2
(c) AV hfe
What is the slope of the DC load line? Rs + hie
1 1 1 1 Re
(a) + (b) + (d) AV hre
RL RC RC RE Rs + hie

(1 Mark)
1 1
(c) (d)
RC C E
R + R 29. What are the input resistance and the output resis-
tance of the amplifier depicted in the figure shown
(2 Marks) in Question 28?
27. For the circuit depicted in the figure of Question Rs + hie
(a) Rif = (Rs + hie ), Rof =
26, what is the slope of the AC load line? hfe
1 1 1 Rs + hie
(a) (b)
(b) Rif = Rs + hie + hfe Re , Rof =
+ hfe
L
R R C L
R + RC
Rs + hie
1 1 (c) Rif = Rs + hie + hfe Re , Rof =
(c) (d) hfe + Re
RL RC
(d) Rif = , Rof = 0
(1 Mark) (2 Marks)
1. Refer to circuit shown in the following figure. The hie = 1.5 k, hfe =100, hre = 1 10-4 and hoe = 25
values of the h-parameters of the transistor are A/V. What is the value of input impedance (in ohm)?

10 V 4. For the circuit in shown in Question 1, find the

value of overall current gain.
Io (1 Mark)
RB = 400 k RC = 4 k 5. If the unity gain bandwidth of the operational
amplifier shown in the following figure is 10 MHz,
Ii then the bandwidth of the opamp-based amplifier
Ci +
in kHz is .
+
RS = 0.5 k 5R
Vo
+ Vi
Vs Zi Zi Zo
R

Vo
Vi +
(1 Mark)
value of output impedance (in ohm)? (1 Mark)
(1 Mark)
value of overall voltage gain?
(1 Mark)
1. (a) 14. (a)

2. (b) 15. (b) The S/N ratio of the cascaded amplifier is pri-
marily determined by the S/N ratio of the first
3. (c)
stage. Therefore, S/N ratio of the given cascaded
4. (c) amplifier is 60 dB.
5. (a) 16. (b)
Af
6. (d) dB of feedback = 20 log
A
7. (d)
8. (b) Af
Therefore, 20 = 20 log
9. (b) A
10. (a) Af
Therefore, log = 1
11. (a) A
12. (a) or Af = 0.1A
13. (d)

(A Af ) 10 103
Percentage reduction in gain = 100% 3
0.9 10 A = 0.8 mA

A
(A 0.1A) 100
= 100%
A The voltage drop across R1 is (15 9) V = 6 V.
= 900% The value of resistor R1 is
gm (rd R D )(rd RD )
gm 6
= 7.5 kW
Voltage
17. (a) gain
Voltage gain feedback
without without feedback
= =
+SR
(rd + RD(r+d R ) D + RS ) 0.8 10 3
4000
A= A =

-6
10 103
10 -6
(
1010 3 3
1010 ( 3
10 10
) ) 21. (c)

( ( ) )
104000
10 103 10 33 22. (d) The output voltage is given by
1 10
3 3 3
+ 1010 10+ 10
+ 1 10
10 +
6 8 6 R + jwL R + jwL
4000
10 400 Vo = V i = jw C Vi
8
104000 1010 400
= = = = = 19.0477
= 19.0477 R + (1/jw C ) jwRC + 1
21 10 21 10
3 3 21 21
Given that
1 106 1 106 1
factor b factor b 6=
1
Feedback
Feedback = = 6 =
1 10 +191010 + 9 10
66 10 10 w=
1
Therefore,
Therefore, voltage
voltage gain withgain with feedback
feedback LC
19.047719.0477 19.047719.0477 Therefore,

Af = Af = = = = 6.56 = . 6 6. 6
66.56
1 1 C R + j(L/ LC )
+ ()19
1 + (191.0477 .0477 ) 2.90477 2.90477 V o = j
10 10 Vi
LC ( jRC / LC ) + 1
C R LC + jL jRC + LC
18. (a)
= j V i
L jRC + LC
V i =
jRC + LC
19. (d) A transistor dissipates zero power when oper-
ating at its maximum junction temperature.
(1 j) (1 j)(1 j) 2 j
= j
Maximum power that can be dissipated by a tran- = = =
sistor for an operating temperature equal to its 1+ j (1 + j)(1 j) 2
maximum junction temperature is zero.
Hence, the phase angle between Vo and Vi is p/2
20. (d) The DC voltage drop across the resistor RC is or 3p/2.
given by
23. (a) The input impedance is
470 10 10-3V = 4.7 V
9 k + (10 k || 100 k) 18 k
Therefore, the voltage drop across the resistor RE is 24. (c) The input impedance (Zi) is given by Zi = RG.
[15 4.7 10 10 (- 15)] V = 5.3 V Therefore, Zi = 2 M.
The output impedance can be calculated as
The value of resistor RE is approximately equal to
Vo
Zo =
W = 530 W
5.3
Io
10 103 V i =0
The voltage at the base of transistor Q1 is given by For Vi = 0, Vo = I d RD and Vgs = I d RS . For
[-15 + 5.3 + 0.7] V = 9 V Vi = 0, the current through resistor rd is equal to
Vrd Vo + V gs I d (RD + RS )
For a good bias stability, the current through resis- I = = =
tor R2 >> IBQ1. The value of R2 should not be so rd rd rd
large such that this condition is not met and also it Applying Kirchhoffs current law at the drain node
should not be too small to have an undue load on (D), we get
the power supply. The current through R2 is
I d + I o = I + gm Vgs
9
3
A = 0.9 mA Therefore,
10 10
R + RS
The current through resistor R1 is I o = I d 1 + gm RS + D
rd

Therefore, 26. (d) For the DC analysis, the output capacitor Co

RD is considered as open. Therefore, slope of the load
Zo = line is
1 + gm RS + [ (RD + RS ) rd ]
1
The value of gm is given by
C
R + RE
VGSQ
gm = gmo 1 27. (a) For the AC analysis, the resistor RE is bypassed
Vp
due to the effect of capacitor CE and the load resis-
tor RL becomes effective. Therefore, the slope of
where, the AC load line is
2IDSS
gmo = 1 1
Vp +
RL RC
2 10 103
= 28. (a) The voltage gain is
5
= 4 mS Output voltage
AV =
Therefore, Input voltage
( 2.5)
gm = 4 103 1 The output voltage is
5
= 2 mS

hfe I b Re (assuming Ic Ie)
Thus,
and the input voltage is Vs. Therefore,
3103
Zo = hfe I b Re Vs
1 + (2103 1103 ) + [(3103 + 1103 )/(50 103 )]
Re
hfe
Rs + hie I b
AV = = Rs + hie
Vs
= 0.97 kW
25. (a) Applying Kirchhoffs voltage law to the input 29. (b) The desensitivity factor is
section, we get
Re R + hie + hfe Re
Vgs = Vi I d RS D = (1 + bAV ) = 1 + hfe = s
Rs + hie Rs + hie
Applying Kirchhoffs current law to the drain node
(D), we get Therefore, the voltage gain with feedback is
V VRS
I d = gm Vgs + o AVf =
hfe Re
rd Rs + hie + hfe Re
The output voltage Vo is given by
The input impedance is
Vo = I d RD
Vgs = Vi VRS
Ri = (Rs + hie )
Also, VRS = I d RS ,
Therefore, the input resistance with feedback is
Therefore, Id is given by
Rif = Ri D = Rs + hie + hfe Re
gm Vi
Id =
1 + gm RS + [ (RD + RS ) rd ] We are interested in the resistance looking into the
The voltage gain Av is emitter. Therefore, Re is the load resistance in the
present case. Hence, Ro = Re. This gives
Vo gm RD
Av = = Ro R (Rs + hie )
Vi 1 + gm RS + [ (RD + RS ) rd ] Rof = = e
D Rs + hie + hfe Re
210 -3 3103
=
1 + (2103 1103 ) + [(3103 + 1103 )/(50 103 )] Rof = lim Rof =
Rs + hie
= 1.95 Re hfe

1. The input impedance Zi is 100 4103

=
Zi = hie
hfe hre RC 1.5103 + (1.5103 25106 100 1104 ) 4103
1 + hoe RC
4
4105
100 1 10 4 10 3 =
= 1.5 103 6
1.5103 + 0.0275 4103
1 + 25 10 4 10 3
4105
= 1.5 10
40
3 = = 248
1. 1 1.61103
= 1500 36.36
= 1.464 kW = 1464W
Ans. (-248)
Ans. (1464) 4. The current gain Ai is
2. The output impedance Zo is the parallel combina- Ai =
hfe
tion of Zo and RC. Now, Zo is given by 1 + hoe RC
1 100
Zo = =
hoe [hfe hre (hie + Rs ) ] 1 + 25 106 4 103
1 = 90.91 = 91
= 6
25 10 [(100 1 104 )/(1.5 103 + 500)] Ans. (-91)
5. We know that
= 50 kW
1
Unity gain bandwidth = Gain Bandwidth
=
25 106 5 106
The overall output impedance is The gain is
Zo = (50 10 || 4 10 ) = 3.7 10 = 3.7 k
3 3 3 RF 5R
= 1 +
= 3700 R
1+ =6
R
Ans. (3700)
The bandwidth is
3. The voltage gain Av is
10 106
V hfe RC Hz = 1670 kHz
Av = o =
Vi hie + (hie hoe hfe hre )RC 6 Ans. (1670)
1. If the input to the ideal comparator shown in the From the figure, we can see that the output is
following figure is a sinusoidal signal of 8 V (peak- HIGH when the input voltage is less than 2V.
to-peak) without any DC component, then the Crossover point when the input voltage is increas-
output of the comparator has a duty cycle of ing and Vi = 2V occurs at point sin wt = 1/2.
Therefore, wt = p/6. Crossover point when the
Input input voltage is decreasing and Vi = 2 occurs at
Output point wt = p (p/6) = 5p/6. Let TON be the ON
Vref = 2 V + time of the output waveform, that is, when the
output is HIGH and T be the total time period of
(a) 1/2 (b) 1/3 the output waveform. The duty cycle is
[(5p /6) (p /6)] = 1

(c) 1/6 (d) 1/12
TON
(GATE 2003: 1 Mark) =
T 2p 3
Solution. Given that the input is a sine wave with
peak-to-peak voltage of 8V, that is, Ans. (b)
Vi = 4 sin w t
2. An amplifier without feedback has a voltage gain of
50, input resistance of 1 k and output resistance

of 2.5 k. The input resistance of the current-shunt The total gain of the amplifier (in dB) is
negative feedback amplifier using the above ampli- 20 log 80000 98 dB
fier with a feedback factor of 0.2 is
Ans. (c)
(a) 1/11 k (b) 1/5 k (c) 5 k (d) 11 k
(GATE 2003: 2 Marks) 5. An ideal opamp is an ideal
(a) voltage-controlled current source
Solution. In the current-shunt amplifier, (b) voltage-controlled voltage source
Ri (c) current-controlled current source
Rif =
1 + bAi
(d) current-controlled voltage source
(GATE 2004: 1 Mark)
where Solution The ideal opamp is a voltage-controlled
R
voltage source.
1 103
Ai = i Av = 50 = 20 Ans. (b)
Ro 2.5 10
3
6. Voltage-series feedback (also called series-shunt
Therefore, feedback) results in
1 103 1
= kW
(a) increase in both input and output impedances
Rif =
1 + (0.2 20) 5 (b) decrease in both input and output impedances
(c) increase in input impedance and decrease in
Ans. (b)
output impedance
3. If the differential voltage gain and the common (d) decrease in input impedance and increase in
mode voltage gain of a differential amplifier are output impedance
48 dB and 2 dB, respectively, then its common (GATE 2004: 1 Mark)
mode rejection ratio is
Solution. In a voltage-series feedback amplifier,
(a) 23 dB (b) 25 dB (c) 46 dB (d) 50 dB the input impedance increases by a factor (1 + Ab)
(GATE 2003: 1 Mark) and the output impedance decreases by the factor
(1 + Ab). Hence, option (c) is the correct answer.
Solution. We know that Ans. (c)
CMRR = Ad Ac 7. The effect of current-shunt feedback in an ampli-
where Ad and Ac are the differential and common fier is to
mode gains in dBs, respectively. Therefore, (a) increase the input resistance and decrease the
CMRR = (48 2) dB = 46 dB output resistance
Ans. (c) (b) increase both input and output resistances
(c) decrease both input and output resistances
4. Three identical amplifiers with each one having a (d) decrease the input resistance and increase the
voltage gain of 50, input resistance of 1 k and output resistance
output resistance of 250 are cascaded. The open- (GATE 2005: 1 Mark)
circuit voltage gain of the combined amplifier is
Solution. In a current-shunt feedback amplifier, the
(a) 49 dB (b) 51 dB (c) 98 dB (d) 102 dB input impedance decreases by the factor (1 + Ab)
(GATE 2003: 2 Marks) and the output impedance increases by the factor
(1 + Ab). Hence, option (d) is the correct answer.
Solution. The voltage gain of the first stage is
Ans. (d)
(1 103 )
50 = 40 8. The cascade amplifier is a multistage configuration of
250 + (1 103 )
(a) CCCB (b) CECB
The voltage gain of second stage is
(c) CBCC (d) CECC
(1 103 )
50
(GATE 2005: 1 Mark)
= 40
250 + (1 103 ) Ans. (b)
The voltage gain of third (output) stage is 50. The 9. The voltage eo indicated in the following figure has
total gain of the amplifier is been measured by an ideal voltmeter. Which of the
following can be calculated?
40 40 50 = 80,000

11. In an ideal differential amplifier shown in the fol-

1 M lowing figure, a large value of (RE)
VCC
eo RC RC
+
1 M
V1 V2
(a) Bias current of the inverting input only
(b) Bias current of the inverting and non-inverting RE
inputs only VEE
(c) Input offset current only
(a) increases both the differential and common-
(d) Both the bias currents and the input offset current
mode gains
(b) increases the common-mode gain only
Solution. Let IB1 and IB2 be the currents through (c) decreases the differential-mode gain only
the non-inverting and inverting terminals, respec- (d) decreases the common-mode gain only
tively. Let V1 and V2 be the voltages at the non- (GATE 2005: 2 Marks)
inverting and inverting terminals.
Solution. Common mode gain
V1 = IB1 1 106
R
Due to virtual earth, V2 = V1. Applying Kirchhoffs ACM = C
2RE
voltage law around the inverting terminal loop,
eo = V2 + IB2 1 106 = (IB2 IB1) 1 106
Differential mode gain
ADM = gm RC
Therefore, output voltage is directly proportional
to the difference of the two currents and hence is a Thus only common-mode gain depends on RE.
measure of the offset current. From the expression for common mode gain, it
Ans. (c) is clear that it is inversely proportional to RE.
Therefore, for large values of RE, common mode
10. The input resistance Ri of the amplifier shown in gain decreases.
the following figure is Ans. (d)
Common Data for Questions 12, 13 and 14:
30 k In the transistor amplifier circuit shown in the follow-
ing figure, the transistor has the following param-
10 k eters: bDC = 60, VBE = 0.7 V, hie , hfe . The
capacitance CC can be assumed to be infinite.
Vo
12 V
+
Ideal operational 1 k
Ri
amplifier 53 k
(a) 30/4 k (b) 10 k +
(c) 40 k (d) Infinite 5.3 k
(GATE 2005: 1 Mark)
Solution. Since the inverting terminal is at vir- CC Vc
tual ground, the current flowing through the volt- Vs
age source is
Vs
Is =
10 103
Input resistance Ri of the amplifier is given by 12. Under the DC conditions, the collector-to-emitter
voltage drop is
V
Ri = s = 10 kW
Is (a) 4.8 V (b) 5.3 V (c) 6.0 V (d) 6.6 V
Ans. (b) (GATE 2006: 2 Marks)

Solution. Applying Kirchhoffs voltage law to the 15. The input impedance (Zi) and the output imped-
base emitter loop, we get ance (Zo) of an ideal transconductance (voltage
I
controlled current source) amplifier are
12 0.7 = 1 103 I E + 53 103 E
60 + 1 (a) Zi = 0, Zo = 0 (b) Zi = 0, Zo =
(c) Zi = , Zo = 0 (d) Zi = , Zo =
Therefore, IE = 6 mA. (GATE 2006: 1 Mark)
Applying Kirchhoffs voltage law to the collector-
emitter loop, we get Solution. For a true transconductance amplifier,
3 the input and the output resistances of the ampli-
VCE = 12 6 10 1 10 = 6 V
3
fier are infinite.
Ans. (c)
Ans. (d)
13. If bDC is increased by 10%, the collector-to-emitter
voltage drop 16. In a transconductance amplifier, it is desirable to have a
(a) increases by less than or equal to 10% (a) large input resistance and a large output resistance
(b) decreases by less than or equal to 10% (b) large input resistance and a small output resistance
(c) increases by more than 10% (c) small input resistance and a large output resistance
(d) decreases by more than 10% (d) small input resistance and a small output resistance
Solution. New b = 66. From the calculation in

Solution. For a true transconductance amplifier,
the input and the output resistances of the ampli-
solution of Question 12, we get new values of IE =
fier are infinite.
6.31 mA and VCE = 5.7 V. The percentage change
Ans. (a)
in VCE is
6 5. 7
Common Data for Questions 17 and 18: Consider
100 = 5% the common-emitter amplifier shown in the following
6 figure with the following circuit parameters: b = 100,
Ans. (b)
gm =0.3861A/V,ro=,rp=259,Rs=1k,RB=93k,
14. The small-signal gain of the amplifier Vc/Vs is RC = 250 , RL = 1 k, C1 = and C2 = 4.7 F.
(a) -10 (b) -5.3 (c) 5.3 (d) 10 +10 V
RB RC
Solution. For small-signal gain of the amplifier,
capacitance CC is considered as short circuited.
Given that hie and hfe , therefore ampli- C2
fier circuit can be drawn as shown below
C1 +
Rs
Vo RL
53 kW +
5.3 kW B C
Vs

+
ib
Vs hre Vc 1 kW
hfe ib 17. The resistance seen by the source Vs is
E (a) 250 (b) 1258 (c) 93 k (d)
If we make hie and hfe equal to , then circuit will be Solution. The equivalent model of the BJT-based
same as the ideal opamp with Ri = and AV = . circuit is given in the following figure.
Assuming of the vitual ground condition and Rs
applying KCL at node B, we get Vo
C
0 Vs 0 Vc gm V o
Rin Is
+ =0 +
5.3 10 3
53 103 Vs RB r V RC RL
Vc
Therefore, = 10
Vs
Ans. (a)

We know that (a) T

he input resistance Ri increases and the mag-
b nitude of voltage gain AV decreases
hie = (b) The input resistance Ri decreases and the mag-
gm
nitude of voltage gain AV increases
Therefore, (c) Both input resistance Ri and the magnitude of
voltage gain AV decrease
100
hie = = 259
0.3861
(d) Both input resistance Ri and the magnitude of
voltage gain AV increase
(GATE 2010: 1 Mark)
The resistance seen by the source Vs is
Solution. The equivalent circuit of given
Rs + (RB || hie) = [1000 + (93000 || 259)] amplifier circuit (when CE is connected, RE is
= 1258 short-circuited)
Ans. (b)
Vo
18. The lower cut-off frequency due to C2 is
+
(a) 33.9 Hz (b) 27.1 Hz gm v RC
(c) 13.6 Hz (d) 16.9 Hz Vs RB r v
Solution. The lower cut-off frequency due to C2
1 Input impedance is Ri = RB rp
fLC =
2p(RC RL )C2
2
Voltage gain is AV = gmRC
Now, if CE is disconnected, resistance RE appears
Substituting RC = 250 , RL = 1000 and C2 = in the circuit
4.7 F in the above equation, we get Vo
fLC2 = 27.1 Hz +
Ans. (b) gm v
Vs RB r v RC
19. The amplifier circuit shown in the following figure

uses a silicon transistor. The capacitors CC and CE
can be assumed to be short at signal frequency and
the effect of output resistance Ro can be ignored. If
CE is disconnected from the circuit, which one of RE
the following statements is TRUE?
VCC = 9 V Input impedance

Rin = RB [rp + (b + 1)RE]
From the above expression it is clear that when
capacitance CE is decreased, input impedance
RB = 800 k RC = 2.7 k increases.
gm RC
Vo Voltage gain AV =
1 + gm RE
CC CC
Hence, voltage gain decreases when the capacitance
b = 100 CE is disconnected.
Vi
Ans. (a)
Vs 20. In the silicon BJT circuit shown in the following
RE = 0.3 k CE figure, assume that the emitter area of transistor
Ri Q1 is half that of transistor Q2. The value of cur-
Ro rent Io is approximately
(a) 0.5 mA (b) 2 mA (c) 9.3 mA (d) 15 mA
(GATE 2010: 1 Mark)

Solving the above equation, we get, IE = 1 mA.

The value of emitter current remains the same irre-
spective of whether the switch is closed or open.
R = 9.3 k
Applying Kirchhoffs current law at the collector
Io junction,
Icap + 0.5 mA = 1 mA
Q1 Q2 Therefore, Icap = 0.5 mA. The value of capacitor
( b 1 = 700 ) ( b 2 = 715 ) current remains the same irrespective of whether
the switch is closed or open. The collector voltage
is given by
VC = VCE + VE
Given that, when the transistor is in saturation,
10V VCE(sat) = 0.7 V. Therefore, the collector voltage
when the transistor is in saturation is
Solution. The current (I) through resistor R is
VC = 0.7 + IERE
0 (10) 0.7
I = = 0.7 + 1 103 4.3 103 = 5 V
A = 1 mA
9.3 103 The collector voltage VC is equal to the voltage
across the capacitor (Vcap). The voltage across the
Since the emitter area of transistor Q1 is half that
capacitor is related to the capacitor current by
of transistor Q2,
I cap t
Io = 2 I = 2 mA Vcap =
C
It may be mentioned here that the circuit is that Substituting the values of Icap, C and Vcap in the
of a current mirror where the output current is a above equation, we get
mirror image of the input current provided that 5 5 106
t= s = 50 ms
0.5 103 s
both the transistors are identical.
Ans. (b)
Therefore, the time required by the transistor to
21. For the BJT, Q1, in the circuit shown in the follow- leave the active region and reach the saturation
ing figure, b = , VBEon = 0.7 V, VCE(sat) = 0.7 V. region is the time required by the collector volt-
The switch is initially closed. At time t = 0, the age or the capacitor voltage (as both are equal) to
switch is opened. The time t at which Q1 leaves the reach 5 V which is equal to 50 ms.
active region is Ans. (c)
5V 22. The voltage gain Av, of the circuit shown in the
following figure is (Given that hie = 1 k)
0.5 mA
13.7 V
12 k
5V 5 F
t=0 Vo
Q1 C
100 k
C
b = 100
4.3 k 10 k
Vi
10V
(a) 10 ms (b) 25 ms (c) 50 ms (d) 100 ms

(a) Av 200 (b) Av 100
Solution. Applying Kirchhoffs voltage law at the
baseemitter junction, we get (c) Av 20 (d) Av 10
5 0.7 IE 4.3 103 + 10 = 0 (GATE 2012: 2 Marks)

Solution. The equivalent circuit is shown below. Voltage gain
Vo V V
= o i
10 kW io
V i V i
iL Av =
Vi
+
+ 100 kW hie
100 kW
12 kW = Av 10.172 103
Vi 1Av 11
= 972 10.172 103
Av
Vi Vo
hfe ib
= 9.88

Hence, Av 10.
The resistor 100 k between the collector and the Ans. (d)
base terminals is equivalent to the connection of
23. In a voltagevoltage feedback as shown below,
100 which one of the following statements is TRUE if
kW
1 Av
the gain k is increased?
resistance at the input terminal and the connection of + V1 + Ao + Vout

Vin

kW 100 k W
100

1 (1/Av )
resistance at the output terminal.

Now, load resistance
RL = (100 103 ) (12 103 ) = 10.7 k W Vf = kVout + +

k
Current gain
io (a) T
he input impedance increases and output
Ai = = hfe = b = 100
ib impedance decreases.
(b) The input impedance increases and output
Input resistance
impedance also increases.
Vi (c) The input impedance decreases and output
Ri = h = 1.1 kW impedance also decreases.
ib ie
(d) The input impedance decreases and output
Voltage gain impedance increases.
(GATE 2013: 1 Mark)
Av =
Vo io RL AR
= = i L
Vi ib Ri Ri Solution. The given configuration is a voltage
100 10.7 10 3 series feedback configuration. The input impedance
= is given by
1.1 103
= 972 Rif = Ri(1 + A0k)
Therefore, the equivalent resistance of 100 k resistor Therefore, the input impedance increases when k
on input side is is increased.
The output impedance is given by
100 103
= 102.77 W
1 (972) Rof =
Ro
1 + Aok
Therefore,
Therefore, the output impedance decreases when k
Vi 102.77 3
Vi = = Vi 10.172 10 is increased.
10 103 + 102.77 Ans. (a)

CHAPTER 17
FREQUENCY RESPONSE OF AMPLIFIERS
This chapter discusses the frequency response of ampli- VCC

fiers. The low-frequency response is limited by the cou-
pling and the bypass capacitors as they can no longer be
considered as short circuits. The high-frequency response
is affected by the stray capacitive elements associ- RC
ated with the active device. Moreover, as the number
of amplifier stages increases, the low- and the high- R1
frequency response gets further limited.
Ci Co Vo
+ Q1
17.1 LOW-FREQUENCY RESPONSE Rs
OF BJT AMPLIFIERS Ri RL
R2 Vi
+
RE CE
In the low-frequency region of operation, a BJT or an Vs
FET amplifiers response is affected by the R-C com-
binations formed by the network capacitors including
the coupling capacitors and bypass capacitors and the
network resistive elements. Figure 17.1 shows the voltage- Figure 17.1| Voltage-divider BJT amplifier
divider BJT amplifier configuration. Ci is the input- configuration.

376 Chapter 17: Frequency Response of Amplifiers
coupling capacitor and is connected between the applied 1 1

fLC = (17.6)
2p (Ro + RL )Co 2p (RC + RL )Co
input source and the active device. Co is the output- o
coupling capacitor and is connected between the output
of the active device and the active load. The output voltage Vo will be 70.7% of its mid-band
value at the frequency fLC assuming that Co is the
o
only capacitive element controlling the low-frequency
17.1.1 Effect of Input-Coupling Capacitor response.
The capacitor Ci forms an RC network as shown in Fig.
C +
17.2. The resistance Ri is the input resistance of the +
Co
amplifier as seen by the source and is given by parallel
combination of R1, R2 and hie. ro R C VC Ro RL Vo
Ri = R1R2hie (17.1)

The voltage Vi is given by
Figure 17.3| Effect of output-coupling capacitor.

Ri
Vi = Vs (17.2)
Rs + Ri jXC
1
At mid and high frequencies, the reactance of capacitors

Ci and Co will be sufficiently small to permit a short-
17.1.3 Effect of Bypass Capacitor
circuit approximation. Therefore, the input voltage at
Figure 17.4 shows the network as seen by the bypass
mid-band frequencies (Vi-mid) is given by
capacitor CE. The value of the equivalent resistance Re
Ri
Vs
is given by
Vi-mid = (17.3)
Rs + Ri
Re = RE [ (Rs + hie ) hfe ] (17.7)
The cut-off frequency established by the capacitor Ci is
given by where
1
fLC =
i
(17.4) Rs = Rs R1 R2
2p (Ri + Rs )Ci
At fLC , the voltage Vi will be 0.707 times the voltage The cut-off frequency as established by resistance Re and
i
Vi-mid assuming that Ci is the only capacitive element capacitor CE is given by
effecting the low-frequency response.
1
fLC = (17.8)
E
2pRe CE
+
Ci
Rs
(Rs+ hie)
Vi R1R2 hie
+ Ri hfe RE Re CE
Vs

Figure 17.2| Effect of input-coupling capacitor. Figure 17.4| Determining the effect of bypass capacitor
on the low-frequency response.
17.1.2 Effect of the Output-Coupling Capacitor
The effect of bypass capacitor CE can be explained
qualitatively by considering that at low frequencies the
Figure 17.3 shows the simplified configuration highlight-
capacitor CE acts like an open circuit and whole value
ing the effect of Co on the low-frequency response of the
of the resistor RE appears in the gain equation, resulting
amplifier. Ro is the total output resistance and is given by
in minimum value of gain. As the frequency increases,
Ro = RC ro (17.5) the reactance of the capacitor CE decreases resulting in
decrease in the value of parallel impedance of resistor
The cut-off frequency as established by Co is given by RE and capacitor CE. The gain is maximum when the

17.2 LOW-FREQUENCY RESPONSE FET AMPLIFIERS 377
impedance of the capacitor CE reduces so much that it 1 1

fLC = =
2p (Ri + Rsignal )Ci 2p (RG + Rsignal )Ci
can be considered as a short circuit. i
It may be mentioned here that the input- and the

(17.9)
output-coupling capacitors and the bypass capacitors
affect only the low-frequency response. At the mid-band In most of the applications, the value of resistor RG
frequency range they are considered as short-circuit is much larger than the value of the resistor Rsignal.
equivalent and do not affect the gain at these frequen- Therefore, the low cut-off frequency (fLCi) is primarily
cies. If the cut-off frequencies offered by them are far determined by the values of resistor RG and capacitor Ci.
apart then the highest cut-off frequency due to the three
capacitors essentially determines the cut-off frequency
+
of the entire system. If the cut-off frequencies are near Ci
to each other, then the effect will be to raise the lower RSignal
cut-off frequency of the entire system, that is, there is an
interaction between the capacitive elements resulting in Vi RG
+ Ri
increased lower cut-off frequency for the entire system. Vs

17.2 LOW-FREQUENCY RESPONSE
FET AMPLIFIERS
Figure 17.6| Determining the effect of input-coupling
capacitor on the low-frequency response.
The low-frequency response of FET amplifiers is quite
similar to that of BJT amplifiers discussed in Section 17.1.
In the case of FET amplifiers also, there are three capac- 17.2.2 Effect of Output-Coupling Capacitor
itors that affect the low-frequency response, namely, the
coupling capacitor Ci between the source and the FET, Figure 17.7 shows the network as seen by the output-coupling
the coupling capacitor Co between the FET and the capacitor Co. The output resistance (Ro) is determined by
load and the source capacitor Cs. Figure 17.5 shows the
circuit of a JFET-based common-source amplifier. The Ro = RD rd (17.10)
fundamental equations and the procedure apply to other
The resulting cut-off frequency fLC is given by
amplifier configurations as well. o
1 1
fLCo = = (17.11)
VDD 2p (Ro + RL )Co 2p (RD rd + RL )Co
RD +
Co
rd RD Ro RL Vo
Co Vo

+ Q1
Ci
RSignal RL
Ri
Figure 17.7| Determining the effect of output-coupling
+ RG Vi
Rs Cs capacitor on the low-frequency response.
Vs

17.2.3 Effect of Source Capacitor
Figure 17.5| JFET-based common-source amplifier.
The equivalent network seen by the source capacitor Cs
is shown in Fig. 17.8.
17.2.1 Effect of Input-Coupling Capacitor The equivalent resistance as seen by the capacitor Cs is
given by
Figure 17.6 shows the equivalent network seen by the
Rs (rd + RD RL )
input-coupling capacitor Ci. The cut-off frequency as Req = (17.12)
determined by the capacitor Ci is given by Rs (1 + gm rd ) + rd + RD RL

behaves in quite a different manner to what it does at

low frequencies. At low frequencies, it is assumed that
the transistor responds to the input voltage and cur-
rent instantly as the diffusion time of the carriers is
Req Cs
very small as compared to the rise time of the input
signal. However, at high frequencies this is not the case
and hence the h-parameter model is not valid at high
frequencies. A commonly used method at high frequen-
cies is the hybrid-p model or the Giacoletto model. This
Figure 17.8| Determining the effect of source capacitor model gives a fairly good approximation of the transis-
on the low-frequency response. tors behavior at high frequencies.
As the value of resistance rd is very large, assuming rd Figures 17.9(a) and (b) show the circuit of a common-
= , we get emitter NPN BJT amplifier and its hybrid-p model,
respectively. The node B is an internal node and is not
Req = Rs (1/gm ) (17.13) physically accessible. All the components, both capaci-
tive as well as resistive, are assumed to be independent
The cut-off frequency due to the capacitor Cs is defined as of frequency. They are dependent on the quiescent oper-
ating conditions, but under a given bias condition they
1 do not vary much for small input signal variations.
fLC = (17.14)
S
2pReq Cs The various circuit components are the base-spreading
resistance (rbb), conductance between terminals B and E
(gbe), conductance between terminals C and E (gce), con-
17.3 HIGH-FREQUENCY RESPONSE ductance between terminals B and C (gbc), current source
OF BJT AMPLIFIERS between terminals C and E (gmVbe), collector-junction bar-
rier capacitance (Cc) and diffusion capacitance between ter-
minals B and C (Ce). The ohmic base-spreading resistance
In this section, the high-frequency response of different (rbb) is represented as a lump parameter between the exter-
BJT-based amplifier configurations will be discussed. nal base terminal (B) and the node B. The conductance
(gbe) takes into account the increase in the recombination
17.3.1 High-Frequency Model for the base current due to the increase in the minority carriers in
Common-Emitter Transistor Amplifier the base region. gce is the conductance between the collec-
tor and the emitter terminals. The conductance (gbc) takes
At high frequencies, the h-parameter model of a BJT is into account the feedback effect between the output and
not applicable because at high frequencies the transistor the input due to the early effect. The early effect results in
VCC
Ic RC rbc = 1/gbc
Ib rbb Ic
B B C
Vo +
C Cc
B
Vi
Ib Vbe rbe = 1/gbe Ce Vberce = 1/gce gmVbe Vce
E
Ie

E E
(a) (b)
Figure 17.9| (a) Common-emitter NPN BJT amplifier. (b) Hybrid-p model of the common-emitter NPN BJT amplifier
of Fig. 17.9(a).

17.3HIGH-FREQUENCY RESPONSE OF BJT AMPLIFIERS 379
modulation of the width of the base region due to varying 17.3.1.2Variation of Hybrid-p Parameters
collectoremitter voltage which in turn causes a change in
the emitter and the collector currents as the slope of the The variations in the values of hybrid-p parameters with
minority-carrier distribution in the base region changes. change in collector current (IC), collectoremitter volt-
Small changes in the value of voltage Vbe cause excess age (VCE) and temperature (T) are listed in Table 17.1.
minority carriers, proportional to the voltage Vbe, to be
injected in to the base region. This results in small-signal Table 17.1| Variations in the values of hybrid-p
collector current. Hence, the magnitude of the collec- parameters.
tor current for shorted collector and emitter terminals
is proportional to the voltage Vbe. The current genera- Parameter IC VCE T
tor gmVbe takes into account this effect. Note that gm gm Linear Independent Inverse
is the transconductance of the transistor and Cc is the
collector-junction barrier capacitance. Sometimes, this rbb Decreases Complex Increases
capacitance is split into two parts, namely, the capaci- relation
tance between C and B terminals and the capacitance rbe Inverse Increases Increases
between C and B terminals. The capacitance between C
and B terminals is also referred to as the overlap-diode Ce Linear Decreases Complex
capacitance. relation
The relation between hie, rbb, rbe and rbc is given by Cc Independent Decreases Increases
hie = rbb + rb e rb c (17.15)

Since rbc >> rbe, Eq. (17.15) can be approximated as
17.3.1.3Common-Emitter Short-Circuit
Current Gain
hie = rbb + rb e (17.16)
Let us consider a single-stage common-emitter amplifier
The relation between rbe, hre and rbc is given by
with the value of the collector resistor (RC) equal to zero.
rb e (1 hre ) = hre rb c (17.17) In this case as the collector resistor acts as the load resistor,
4 this means that the load is short circuit. Figure 17.10(a)
Since the value of hre is in the range of 10 , that is, shows the circuit connection and Fig. 17.10(b) shows
hre << 1, Eq. (17.17) can be approximated by the hybrid-p equivalent model for the circuit. The input
source is a sinusoidal source and furnishes a sinusoidal
rb e = hre rb c or gb c = hre gb e (17.18) input current Ii. The load current produced is IL. The
The relation between gce, hoe, hfe and gbc is given by equivalent model shown in the figure can be simplified
to that shown in Fig. 17.10(c). The assumptions made
gce = hoe (1 + hfe )gbc (17.19) in the simplified model are that the conductance gbc can
be neglected as the value of gbc<<gbe. The conductance
Since the value of hfe >> 1, Eq. (17.19) can be approxi- gce has also been removed as it is placed across short-
mated as circuited terminals. Another approximation is that the
current is delivered directly to the output through the
gce hoe hfe gbc hoe gm hre (17.20) conductance gbc and capacitance Cc has been neglected.
rbe can be expressed in terms of hfe and gm as The parameters of interest are the b-cut-off frequency
(fb) and the short-circuit gain bandwidth product (fT).
hfe gm Here, fb is the frequency at which the value of short-
rb e = or gb e = (17.21) circuit common-emitter gain reduces to 0.707 times its
gm hfe
mid-band value. In other words, at the b-cut-off fre-
quency, the short-circuit common-emitter current gain
17.3.1.1Transistors Transconductance (gm)
is 3 dB below its mid-band value. Thus, fb represents
the maximum attainable current-gain bandwidth for the
The transconductance of a transistor (gm) is defined as
common-emitter amplifier. The actual maximum band-
the ratio of the change in the value of collector current
width depends upon the circuit connections. The value
to change in the value of voltage Vbe for constant value
of current gain Ai is given by
of collectoremitter voltage.
hfe
Ic Ai = (17.23)
gm = (17.22) 1 + j(f /fb )
VT

VCC rbc = 1/gbc

B Ii rbb B C
Vo + +
Rs Cc
+ Vbe rbe= 1/gbe Vbe rce= 1/gce IL

+ Ce gmVbe
Vs Vi

E E
(a) (b)
Ii B C
B
gbe Ce Cc gmVbe IL
E
E
(c)
Figure 17.10| (a) Common-emitter amplifier with short-circuit load. (b) Hybrid-p equivalent model for the circuit in
Fig. 17.10 (a). (c) Simplified hybrid-p equivalent model for the circuit in Fig. 17.10(a).
The value of fb is given by fT (MHz)

gb e
fb = (17.24)
2p (Ce + Cc ) 400
As we can see from Eq. (17.23), the value of Ai is
equal to hfe at zero and low frequencies. Remember 300
that hfe is the low-frequency short-circuit current gain of
the common-emitter configuration. 200
The frequency fT is the frequency at which the mag-
nitude of the short-circuit current gain in the common- 100
emitter amplifier becomes unity or 0 dB. As the value of
hfe >> 1, the magnitude of the current gain Ai becomes
unity at the frequency given by the product of hfe and fb. 10 100 IC (log scale) mA
Therefore, fT is given by
Figure 17.11| Variation of the frequency fT with
hfe gbe gm
fT hfe fb (17.25) collector current IC.
2p (Ce + Cc ) 2p (Ce + Cc )
The expression for current gain Ai can be written as The a -cut-off frequency is the frequency at which
hfe
the short-circuit current gain value in the common-base
Ai (17.26) configuration drops by 3-dB to its value at low frequen-
1 + jhfe (f /fT ) cies. It is represented as fa . It may be mentioned here
The parameter fT is a strong function of the collector that the transistor used in common-base configuration
current of the transistor. The variation of fT with collec- has a much higher value of 3-dB frequency as compared
tor current (IC) is highlighted in Fig. 17.11. to the transistor used in common-emitter configuration,

although the latter has much higher value of gain. In circuit of the network shown in Fig. 17.12(a). The input
other words, the value of f is much larger than the impedance Zin is given by
value of fb.
Z
hfe fb (Ce + Cc ) Zin = (17.28)
fa (17.27) 1 A
Ce
where, A is the gain of the circuit where feedback
impedance is connected.
17.3.1.4Millers Theorem
The impedance Zin appears in parallel with the input
Let us consider a circuit configuration shown in Fig. terminals of the network.
17.12(a). An impedance (Z) is connected between the The output impedance Zout is given by
input and the output nodes. This impedance is also
referred to as the feedback impedance. This impedance Z
Zout = (17.29)
has an effect on the functioning of the circuit. According 1 (1/A)
to Millers theorem, the circuit with feedback impedance
can be replaced by an equivalent circuit such that the 17.3.1.5Common-emitter Current Gain
feedback impedance is split into two impedances: one with Resistive Load
between the input terminal and the ground (Zin) and
the other between the output terminal and the ground Figure 17.13(a) shows the circuit diagram of the com-
(Zout). Figure 17.12(b) shows the Millers equivalent mon-emitter configuration when the load resistor (RL)
I1 Z I2
1 2
1 2
Z Z
Zin =
(1 A) Zout =
(1 1/A)
G
G
(a) (b)
Figure 17.12|(a) Circuit configuration with feedback impedance. (b) Millers equivalent circuit of the network in Fig. 17.12(a).
VCC
RL rbc=1/gbc
B Ii rbb B C
Vo + +
Rs Cc
rbe=
+ Vbe rce= gm IL
1/gbe
+ Vbe Ce RL
Vi 1/gce Vbe
Vs

E E
(a) (b)
Figure 17.13| (a) Circuit diagram of common-emitter configuration with load resistance (RL). (b) Hybrid-p equivalent
model of the circuit in Fig. 17.13(a).

is not equal to zero and Fig. 17.13(b) shows its hybrid-p In practical situations, the output time constant is
equivalent model. The conductance gbc can be replaced negligible as compared to the input time constant and
by its Millers equivalent components. The conductance hence can be ignored. The upper 3-dB frequency in this
component due to gbc on the input side is given by gbc case is given by
(1 K), where K = Vce/Vbe. The value of K is equal 1
to gmRL. The conductance component due to gbc on fH =
2p rb e [Ce + Cc (1 + gm RL )]
(17.34)
the output side is given by gbc [(K 1)/K]. The Millers
component of the capacitance Cc on the input side is It may be mentioned here that if the transistor works
given by Cc(1 K) and on the output side is given by into a highly capacitive load, then the output time con-
Cc[(K 1)/K]. Figure 17.14 shows the equivalent cir- stant will also be predominant and cannot be ignored.
cuit with components gbc and Cc being replaced by their Equation (17.34) has been derived by neglecting the
Millers equivalent components. effect of the source resistance (Rs). The value of source
resistor has a very strong influence on the upper 3-dB
The circuit has two time constants, one associated
frequency. The upper 3-dB frequency taking into account
with the input section and the other associated with the
Rs and base-spreading resistor rbb is given by
output section. As the value of K >> 1, the value of
[(K 1)/K] 1. Therefore, gbc [(K 1)/K] gbc and Cc 1
fH =
[(K 1)/K] Cc. The total load resistance RL is given by
(17.35)
2p [(Rs + rbb ) rbe ][Ce + Cc (1 + gm RL )]
RL = RL (1/gb c ) (1/gce ) (17.30) When the effect of biasing resistors is taken into account,
the term Rs in Eq. (17.35) is replaced by Rs, where Rs is
In most cases, the value of gbc << gce (rbc 45 M a parallel combination of Rs and biasing resistors.
and rce 80100 k); therefore, gbc can be ignored from
the output section. The value of load resistor RL is in the
range of 25 k. Therefore, the conductance gce can be 17.3.2 High-Frequency Response of Common-
neglected as compared to 1/RL. Therefore, resistor RL RL. Collector Transistor Amplifier
The input conductance (gi) is given by
Figure 17.15(a) shows the common-collector transistor
gi = gbe + gbc (1 K ) (17.31) amplifier. Capacitance CL is included in parallel with the
load resistor RL as the common-collector transistor due
The output time constant (toc) is given by to its low output resistance is often used to drive capaci-
tive loads. Figure 17.15(b) shows the hybrid-p equiva-
toc = RL Cc RL Cc (17.32)
lent model for the common-collector amplifier shown in
The input time constant (tic) is given by Fig. 17.15(a).
Applying Millers theorem to the hybrid-p equivalent
1
tic = [Ce + Cc (1 + gm RL )] circuit of Fig. 17.15(b), we get the equivalent circuit as
gi shown in Fig. 17.15(c). The parameter K is given by the
1 ratio of voltages Vec and Vbc (i.e., K=Vec/Vbc). The
[Ce + Cc (1 + gm RL )] (17.33) input time constant tic is given by
gbe
In most of the cases, the magnitude of the capacitance 1
gbc(1 K) is very small as compared to the value of gbe.
tic = (Rs + rbb ) Cc + Ce (1 K ) (17.36)
gbe (1 K )
Therefore, gi gbe.
B Ii rbb B C
+
rbe=
Vbe 1/gbe gbc(1 K) C (1 K) Ce Vbe gbc(K1)/K Cc(K1)/K
rce= gm
R IL
c 1/gce Vb e L

E E
Figure 17.14| Simplified hybrid-p model making use of Millers theorem for the model shown in Fig. 17.13(b).

VCC
rbe=1/gbe
Ib rbb Ie E
Rs B B
+
+ Ce
+ Vo
Vs Vi Vbc Cc Vbc gmVbe RL CL
RL
CL

C C
(a) (b)
Ib rbb Ie E
B B
+
Vbe Cc Ce(1 K) gbe(1 K) Vbc gbe(K1)/K Ce(K 1)/K RL CL

gmVbe

C C
(c)
Figure 17.15| (a) Common-collector amplifier. (b) Hybrid-p equivalent model of the common-collector amplifier.
(c) Simplified hybrid-p equivalent model of the common-collector amplifier.
Since the low-frequency gain of the emitterfollower con- the upper 3-dB frequency is determined mostly by the
figuration is approximately equal to unity, (1 K) 0. output circuit alone. The impedance of the output cir-
Therefore, the expression for tic can be approximated by cuit (Zo) is given by
tic (Rs + rbb )Cc

1 1
(17.37) Zo = RL
gb e (K 1)/K jw[CL + {Ce (K 1)/K }]
The output time constant (toc) is given by
(17.41)
1 Substituting (K 1) 0, we get
toc = RL
gbe (K 1)/K 1
Zo RL (17.42)
CL + Ce (K 1)/K (17.38) jw CL
The amplifier gain is given by
Since the value of (K 1) 0, the above equation can
be simplified as g R 1
A = m L (17.43)
1 + gm RL 1 + (jf /fH )
toc RL CL (17.39)
where
Since we have assumed that the output load is highly 1 + gm RL
capacitive, the value of CL >> Cc. Hence, fH =
2p CL RL
RL CL >> (Rs + rbb )Cc (17.40) The value of fH can be expressed as
1 + gm RL g
This implies that the value of output time constant (toc) fH = m (17.44)
is much larger than the input time constant (tic). Hence, 2pRL CL 2pCL

From Eq. (17.25), the value of unity gain bandwidth (fT) 17.4.1 Common-Source Amplifier at High
is given by Frequencies
gm
fT = (17.45) Figure 17.17(a) shows the circuit diagram for the com-
2p (Ce + Cc )
mon-source JFET amplifier and Fig. 17.17(b) shows its
Since the value of Ce for a transistor is much larger than high-frequency equivalent model.
Cc, fT can be approximated by
gm VDD
fT (17.46)
2p Ce
Substituting this value of fT in Eq. (17.44), we get

RL
f C
fH T e (17.47) Vo
CL
Since the input impedance between terminals B and C

is much large as compared to (Rs+rbb), K is approxi-
mately the overall voltage gain (Avs), that is, +
Vs

V
K Avs = ec (17.48)
Vs
17.4 HIGH-FREQUENCY RESPONSE

OF A FET AMPLIFIER (a)
Cgd
The high-frequency response of an FET amplifier is G D
similar to that of a BJT amplifier. Figure 17.16 shows +
+
the high-frequency model for an FET (JFET as well
as MOSFET). The high-frequency model is similar to
the low-frequency model with the addition of junction Vs Cgs gmVs Cds rd RL Vo
capacitances.
Cgd
G D
+ S S
+
(b)
Figure 17.17| Common-source JFET amplifier:
Vgs Cgs Cds rd Vds
gmVgs (a) Circuit diagram of a common-source
JFET amplifier. (b) High-frequency
model.
S S The value of voltage gain (Av) is therefore equal to
Figure 17.16| High-frequency model of an FET. Vo gm + Y gd

Av = = (17.49)
The capacitance Cgs represents the barrier capaci- Vs GL + Y ds + gd + Y gd
tance between the gate and the source terminals. Cgd At low frequencies, the FET capacitances can be
is the barrier capacitance between the gate and the neglected and hence Yds = Ygd = 0. Therefore, the value
drain terminals. Cds is the drain-to-source capacitance of gain at low frequencies is given by
of the channel. These capacitors offer high impedance at
gm gm RL rd
lower frequencies and can be considered as open circuit. Av = = = gm RL (17.50)
However, at high frequencies, due to these capacitances GL + gd RL + rd
feedback exists between the input and output circuits where
and voltage amplification drops rapidly as the frequency
increases. RL = RL rd

17.5 AMPLIFIER RISE TIME AND SAG 385
The input admittance (Yi) is therefore given by At low frequencies, the value of reactance offered by the
capacitances Cgs, Cds and Csn is infinity. Therefore, at low
Y i = Y gs + (1 A v )Y gd = Y gs + (1 + gm RL ) Ygd (17.51) frequencies, the value of voltage gain (Av) is given by
The input capacitance (Ci) is given by gm Rs
Av = (17.55)
Ci = Cgs + (1 A v )Cgd = Cgs + (1 + gm RL)Cgd (17.52) 1 + (gm + gd )Rs
This input capacitance is important in the case of cas- As we can see from Eq. (17.55), the value of Av is slightly
caded amplifiers where the input impedance of a stage less than unity as generally gmRs >> 1.
acts in shunt across the output impedance of the preced- The input admittance (Yi) is obtained by using the
ing stage. As the reactance of a capacitance decreases Millers theorem in a manner similar to that done for the
with frequency, the input impedance decreases; hence, common-source FET amplifier. The expression for (Yi)
the gain of the cascaded amplifier also decreases with is given by
increase in frequency.
Y i = jw Cgd + jw Cgs (1 Av ) jw Cgd (17.56)
The output impedance is obtained by the impedance
looking into the drain and the source terminals, with One of the major advantages of the common-drain ampli-
the input voltage (Vi) set equal to zero. With Vi = 0, fier over the common-source amplifier is that it offers
the resistance rd and capacitances Cds and Cgd are in lower input capacitance as compared to the common-
parallel. Therefore, the output admittance (Yo) is given by source amplifier.
The output admittance (Yo) can also be determined
Y o = gd + Y ds + Y gd (17.53)
in a manner similar to that for the common-drain FET
amplifier. It is given by
17.4.2 Common-Drain Amplifier at High
Frequencies Y o = gm + gd + jw CT (17.57)
Figure 17.18(a) shows the circuit of a common-drain or

a source-follower amplifier. Figure 17.18(b) shows its 17.5 AMPLIFIER RISE TIME AND SAG
small-signal high-frequency equivalent circuit.
The output voltage Vo is given by the product of the
short-circuit current and the impedance between the 17.5.1 Rise Time
source and the ground terminals. By carrying out analy-
sis in a manner similar to that for the common-source Let us consider that the step input applied has a pulse
amplifier, the expression for the voltage gain (Av) for a width of tp. Figure 17.19 shows the response of the
common-drain amplifier is given by amplifier to the leading and the falling edge of the step
input. The amplifier acts as a low pass filter to the lead-
(gm + jw Cgs )Rs ing and the falling edges of the input signal. The transfer
Av = (17.54)
1 + [gm + gd + jw (Cgs + Cds + Csn )]Rs
function of the amplifier to the leading edge of the input
signal is given by
VDD
Cgs
G S
+
+
+ Vo Cgd rd Rs
Vs Cds Csn Vo
Vs
Yi gmVgs Yo
Rs

D N D
(a) (b)
Figure 17.18| (a) Common-drain amplifier. (b) Small-signal equivalent of a common-drain amplifier.

V o = V (1 et /R1C1 )
17.5.2 Tilt or Sag
(17.58)
where R1 and C1 are the resistive and the capacitive The response of the amplifier to the flat portion of the
elements limiting the high-frequency response of the step input (Fig. 17.20) is affected by the high-pass circuit
amplifier. of the amplifier. The transfer function is expressed as
The rise-time (tr) of the amplifier is given by the time Vo = Vet /R2C2 (17.62)
required by the output signal to rise from 10% of its final
where R2 and C2 are the resistive and the capacitive ele-
value to 90% of its final value. It is an indication of how
ments limiting the low-frequency response of the ampli-
fast the amplifier responds to the fast rising edges of the
fier. For time t, much larger than the time constant
input signal. The value of the rise time is given by
R2C2, Eq. (17.62) can be approximated as
t
2.2 0.35
tr = 2.2R1C1 = =
Vo = V 1
(17.59)
2pfH fH (17.63)
R2C2
where fH is the upper cut-off frequency of the amplifier.
Therefore, the rise time of an amplifier is inversely Vi
proportional to the upper 3-dB cut-off frequency. The upper
3-dB cut-off frequency of the amplifier (fH) required V
to amplify the step input signal with pulse width tp,
without much distortion is given by
1
fH = (17.60)
tp
t
tp
Substituting this value of fH in Eq. (17.59), we get
Vo
tr = 0.35tp (17.61)
V
V
Vi
V
t
tp
Figure 17.20| Response of the amplifier to the flat

portion of the step input.
t From Fig. 17.20, the percentage tilt or sag in the output

tp voltage is given by
V V tp
P = 100% = 100% (17.64)
Vo V R2C2
where, tp is the pulse width of the sequance
V
0.9V
17.6 FREQUENCY RESPONSE OF
CASCADED AMPLIFIER STAGES
0.1 V In a multistage amplifier, the lower cut-off frequency is

t
tp determined by the stage having the highest value of the
tr lower cut-off frequency and the upper cut-off frequency
Figure 17.19| Response of the amplifier to the leading

is determined by the stage having the lowest value of the
upper cut-off frequency. This also results in reduction of
and the falling edges of the step input. the overall bandwidth of the amplifier.

17.6.1 Low-Frequency Response of Cascaded then the bandwidth may increase with increase in the
Amplifier Stages number of stages.
Let the gain of each individual stage in the mid-

frequency region be Av(mid) and the gain in the low-fre- 17.6.2 High-Frequency Response of Cascaded
quency region be Av(low). Let the overall mid-frequency Amplifier Stages
gain be Av(mid)-overall and the overall low-frequency gain
beAv(low)-overall. Also, the lower and the upper cut-off fre- The upper cut-off frequency (fHn) for `n identical non-
quencies for the individual stages are fL and fH, respec- interactive stage amplifiers is given by
tively, and the lower and the upper cut-off frequencies
for the overall amplifier are fLn and fHn, respectively. fHn = fH 21/ n 1 (17.68)

n
A v(low)-overall 1
= (17.65) where fH is the upper cut-off frequency of each individual
A v(mid)-overall (1 jfL / f ) stage.
Let the frequency at which the magnitude of the expres- If in a multistage amplifier, the input impedance
sion given by Eq. (17.65) becomes 1/ 2 (3dB) be fLn. of the stages is low enough to act as an apprecia-
Therefore, ble shunt on the output impedance of the stages
1 1 p receding them, then it is no longer possible to
= (17.66)
2 n 2 isolate the stages. Under such conditions, individ-
[1 + (f /f ) ]
L Ln
ual 3-dB frequencies for different stages cannot be
On solving Eq. (17.66), we get obtained in isolation. The 3-dB frequency in this case
fL is obtained by considering the effect of each of the
fLn = (17.67)
21/ n 1 stages p roceeding and following them.
It may be mentioned here that increase in the number It may be mentioned here, that the above discussion and
of stages is not always associated with decrease in the formulae are valid for `n identical non-interactive stage
bandwidth. If the value of mid-band gain is kept fixed amplifier.
IMPORTANT FORMULAS
1. The lower cut-off frequency for BJT amplifiers due 6. The lower cut-off frequency for FET amplifiers due
to input-coupling capacitor is to source capacitor is
1 1
fLC = fLC =
i 2p (Ri + Rs )Ci S
2p [Rs (1/gm ) ]CS
2. The lower cut-off frequency for BJT amplifiers due 7. hie = rbb + rb e rb c
to output-coupling capacitor is 8. r be (1 hre ) = hre r bc
1
fLC For hre << 1, rb e = hre rb c or gb c = hre gb e
o 2p (RC + RL )Co
9. gce = hoe (1 + hfe )gbc . For hfe >> 1,
3. The lower cut-off frequency for BJT amplifiers due
to bypass capacitor is gce hoe hfe gbc hoe gm hre
1 hfe g
fLC =
E
2pRe CE 10. rb e = or gb e = m
gm h fe
4. The lower cut-off frequency for FET amplifiers due
to input-coupling capacitor is Ic
11. gm = .
1 VT
fLC =
i
2p (RG + Rsignal )Ci 12. Formulas listed in Table 17.1.
5. The lower cut-off frequency for FET amplifiers due hfe
13. The current gain is Ai = , where
to output-coupling capacitor is 1 + j(f /fb )
1 gb e
fLC = fb = .
o
2p (RD rd + RL )Co 2p (Ce + Cc )

hfe gbe gm Common-Source Amplifier at High Frequencies

14. fT hfe fb .
2p (Ce + Cc ) 2p (Ce + Cc ) 28. Voltage gain Av is
15. The current gain is Vo gm + Y gd
hfe Av = =
Ai Vs GL + Y ds + gd + Y gd
1 + jhfe (f /fT )
hfe fb (Ce + Cc ) 29. Voltage gain at low frequencies is
16. fa . gm gm RL rd
Ce Av = = = gm RL
Z GL + gd RL + rd
17. Using Millers theorem, Zin = and
1 A
Z 30. The input admittance is Y i = Y gs + (1 A v )Y gd
= Y gs + (1 + gm RL ) Ygd .
Zout =
1 (1/A)
Common-Emitter Current Gain with Resistive Load 31. The input capacitance is Ci = Cgs + (1 A v )Cgd
= Cgs + (1 + gm RL)Cgd .
18. gi = gbe + gbc (1 K )
32. The output admittance is Y o = gd + Y ds + Y gd .
19. The output time constant is
toc = RL Cc RL Cc Common-Drain Amplifier at High Frequencies
20. The input time constant is 33. The voltage gain is
1 (gm + jw Cgs )Rs
tic = Ce + Cc (1 + gm RL ) Av =
gi 1 + [gm + gd + jw (Cgs + Cds + Csn )]Rs
1
Ce + Cc (1 + gm RL )
34. At low frequencies,
gbe gm Rs
Av =
21. The upper 3-dB frequency is 1 + (gm + gd )Rs
1 35. The input admittance is
fH =
2p rb e [Ce + Cc (1 + gm RL )] Y i = jw Cgd + jw Cgs (1 A v ) jw Cgd
High-Frequency Response of Common-Collector 36. The output admittance is
Transistor Amplifier Y o = gm + gd + jw CT
22. The input time constant is
High and Low Frequency Response of Amplifiers
1
tic = (Rs + rbb ) Cc + Ce (1 K ) 37. The rise time is
gbe (1 K ) 2. 2 0.35
(Rs + rbb )Cc
tr = 2.2R1C1 = =
2pfH fH
23. The output time constant is 38. The upper cut-off frequency is

1
{CL + [Ce (K 1)/K ]}
1
toc = RL
fH =
gbe (K 1)/K
tp

39. tr = 0.35tp
RL CL
40. The percentage tilt or sag in the output voltage is
24. The impedance of the output circuit is
V - V tp
P = 100% = 100%
Zo = RL
1 1 V R2C2
gbe (K 1)/K jw CL + {Ce (K 1)/K}
41. The lower cut-off frequency (fLn) for n identical
g R 1 non-interactive stage amplifiers is
25. A = m L
1 + gm RL 1 + (jf /fH )
.
fL
fLn =
1 + gm RL g 21/ n 1
26. fH = m .
2p RL CL 2p CL 42. The upper cut-off frequency (fHn) for n identical
gm non-interactive stage amplifiers is
27. fT = .
2p (Ce + Cc ) fHn = fH 21/ n 1

SOLVED EXAMPLES 389
SOLVED EXAMPLES
1. For the circuit shown in the following figure, the The value of input resistance Ri is given by
value of transistors h-parameters are hie = 1 k, h h R
hre = 1 104, hfe = 100 and hoe = 25 1061. Ri = hie re fe L
1 + hoe RL
15 V 1 10 -4 100 9.61 103
= 1 103
1 + 25 106 9.61 103
= 1000 77.5 = 922.5 W 923W
96.1
RC 10 k = 1000
1.24
250 k
Vo The current gain is given by
RB hfe 100
RS Ai = =
1 + hoe RL 1 + 25 106 9.61 103
+ 5 k 100
= = 80.63 81
Vs R Ri 1.24
i
The value of voltage gain is given by
Ai RL 80.63 9.61 103
Av = = = 839.95 840
Ri 922.5
What are the values of input impedances Ri and Ri?
(a) 631 , 509 (b) 923 , 225 The equivalent impedance of RB as seen from the
(c) 1024 , 412 (d) 871 , 429 input terminals (RBI) is given by
RB 250 103
RBI = =
1 Av [1 (839.95)]
Solution. The resistor RB is the feedback resistor
between the input and the output terminals. It can
be replaced by the Millers equivalent components 250 103
as shown in the following figure. The equivalent = = 297.28 W
840.95
impedance of RB as seen from the output terminals
(RBO) is given by RB/[1 (1/Av)]. Av is the volt- The value of Ri is
age gain from base to collector. Since the value of
voltage gain is much larger than 1, the value of Ri RBI = 922.5 297.28 = 224.83 225
RBO RB 250 k. Ans. (b)
2. For the given data and the circuit shown in
15 V Question 1, what are the values of amplifier voltage
gain (Av) and system voltage gain (Avs)?
RC 10 k (a) 840, 36 (b) 790, 25
(c) 840, 36 (b) 790, 25
From the solution of Solved Example 1, value of
voltage gain
RS
Av 840
+ 5 k RBO
The system voltage gain Avs is given by
Vs RBI
Ri

Ri Ri
A vs = A v
Ri +Rs
224.83
= 839.95 3
The effective load resistance is 224.83 + 5 10
RL = RC RBO = 10 103 || 250 103 = 36.12 36
= 9.61 103 = 9.61 k Ans. (a)

3. For the given data and the circuit shown in Therefore,

Question 1, what are the values of amplifier cur- 1
fLC =
2 p (1.26 103 + 1 103 ) 5 106
rent gain (Ai) and system current gain (Ais)? i
(a) 81, 29 (b) 91, 19 = 14.08 Hz

(c) 91, 29 (d) 81, 19 The cut-off frequency due to capacitor CE is
Solution. From the solution of Solved Example 1, 1
the value of current gain is fLC =
E
2pRe CE
Ai 81
where Re
The system current gain is
Re = RE [( Rs R1 R2 + hie )/hfe ]
RBI RBO = 1103 [( 1103 40 103 10 103 + 1.5103 )/100 ]
Ais = Ai
Ri + RBI BO
R + RL
= 23.33 W
297.28 250 103
= 80.63 Therefore,
922.5 + 297.28 250 103 + 10 103
1
= 18.89 19 fLC = = 682 Hz
E 2 p (23.33) 10 106
Ans. (d)
The cut-off frequency due to capacitor Co is given
4. What is the lower cut-off frequency of the BJT by
amplifier shown in the following figure. Given that 1
the h-parameters of the transistor are hie = 1.5 k fLC =
o 2p (RC + RL )Co
and hfe = 100.
1
= = 26.53 Hz
18 V 2p (4 10 + 2 103 ) 1 106
3
As we can see fLCE is significantly higher than fLCo and

fLCi, hence, fLCE is the predominant factor in deter-
mining the low-frequency response for the complete
RC
system. Hence, the cut-off frequency for the overall
R1 4 k
system is approximately equal to 682 Hz.
40 k Co
Vo Ans. (c)
Ci 1 F 5. An amplifier has a single-pole high-frequency trans-
fer function. The rise time of its output response to
Rs 5 F a step input is 35 ns. The upper 3-dB frequency
1 k
RL (in MHz) for the amplifier to a sinusoidal input is
R2 2 k approximately at
+ 10 k RE CE
Vs 1 k 10 F
(a) 4.55 (b) 10
(c) 20 (d) 28.6

Solution. We have
350
BW (MHz) =
(a) 14.1 Hz (b) 26.5 Hz tr (ns)
(c) 682 Hz (d) None of these Therefore,
Solution. The cut-off frequency due to the capacitor 350
BW = MHz = 10 MHz
Ci is 35
1 Ans. (b)
fLCi =
2(Ri + Rs )Ci 6. An NPN transistor (with C = 0.3 pF) has a unity-
where gain cut-off frequency fT of 400 MHz at a DC bias
current IC = 1 mA. The value of its Cm (in pF) is
Ri = R1 R2 hie = 40 103 10 103 1.5 103 approximately (VT = 26 mV)
= 1.26 k (a) 15 (b) 30

(c) 50 (d) 96

SOLVED EXAMPLES 391
Solution. We have 8. An NPN BJT has gm = 38 mA/V, Cm = 10-14 F, Cp

1 = 1013 F, and DC current gain bo = 90. For this
fT =
2pRCm transistor, fT and fb are
1 I (a) fT = 1.64 108 Hz and fb = 1.47 1010 Hz

gm = = C (b) fT = 1.47 1010 Hz and fb = 1.64 108 Hz
R VT
(c) fT = 1.33 1012 Hz and fb = 1.47 1010 Hz
(d) fT = 1.47 1010 Hz and fb = 1.33 1012 Hz
Therefore, (2 Marks)
IC gm
fT = Solution. fT =
2p V T Cm 2p (Cm + Cp )
Therefore,
Therefore,
38 103
1 103 fT =
Cm = F = 15 pF 2 p (1014 + 4 1013 )
Hz
2 p 26 103 400 106

Ans. (a) = 1.47 1010 Hz
7. The current gain of a bipolar transistor drops at fT

and fb =
high frequencies because of b
(a) transistor capacitance Therefore,
(b) high current effects in the base 1.47 1010
fb = Hz = 1.64 10 Hz
8
(c) parasitic inductive elements
(d) the early effect 90
Ans. (a) Ans. (b)
1. Refer to the BJT-based amplifier shown in the fol- Since bRE > 10R2, an approximate analysis can be
lowing figure. What is the value of the mid-band carried out to find the value of the operating point.
voltage gain? VCCR2
VB = =4V
VCC =16 V R1 + R2
Therefore,
VE = VB 0.7 = 3.3 V
R1 RC 2.2 k and
30 k VE 3. 3
Co IE = = A = 1.65 mA
Vo RE 2 103
1 F
Ci 26 103
re = = 15.76 W
b=100 1.65 103
Rs 1 F +
The mid-band gain is
16 k RL
4 k Vo R R
+ R2 RE Av = = C L = 90
Vi CE Vi re
Vs 10 k 2 k Ans. (90)

Ri 2. For the BJT-based amplifier shown in the figure of
Question 1, what is the value of input impedance
in k?
Solution. The value of bRE is Solution. The input impedance is
100 2 k = 200 k Zi = R1 R2 b re = 1320 = 1.32 k
and 10R2 = 100 k Ans. (1.32)

3. For the BJT-based amplifier shown in the figure of The cut-off frequency due to the emitter capacitor
Question 1, what is the 3-dB lower cut-off frequency CE is given by
of the amplifier in Hz? 1
fLC =
E
Solution. The lower cut-off frequency is given by 2p Re CE
the highest of the lower cut-off frequencies due to where
the input and output-coupling capacitors and the
emitter capacitor. The cut-off frequency due to the Re = RE [(Rs b ) + re ]
input-coupling capacitor (Ci) is given by
1 Rs = Rs R1 R2 = 0.89
fLC = = 6.86 Hz
i 2p(Rs + Ri )Ci Therefore, Re= 24.4
Hence,
The cut-off frequency due to the output-coupling 1
capacitor (Co) is given by fLC =
E
= 327 Hz
2pRe CE
1 Therefore, the lower cut-off frequency is due to CE
fLC = = 25.7 Hz
o 2p(RC + RL )Co which is equal to 327 Hz.
Ans. (327)
PRACTICE EXERCISE
1. Which of the following statement(s) is/are true? (c) independent of the emitter-bias current.
(d) proportional to the square of emitter-bias current.
(1)The low-frequency response of an amplifier is (1 Mark)
due to the bypass and the coupling capacitors.
4. The rise time of an amplifier is
(2)The high-frequency response of an amplifier is
due to the bypass and the coupling capacitors. (a) inversely proportional to the upper 3-dB cut-off
frequency.
(3)The low-frequency response of an amplifier is (b) directly proportional to the upper 3-dB cut-off
due to the junction capacitances and the stray- frequency.
wiring capacitances. (c) independent of the upper 3-dB cut-off frequency.
(4)The high-frequency response of an amplifier is (d) proportional to the square root of the upper
due to the junction capacitances and the stray- 3-dB cut-off frequency.
wiring capacitances. (1 Mark)
(a) Both (1) and (4) (b) Both (2) and (3) 5. The value of -cut-off frequency
(b) All of these (d) None of these (a) is smaller than the b-cut-off frequency.
(1 Mark) (b) is greater than the b-cut-off frequency.
2. The voltage gain of an amplifier decreases at 20 (c) can be more or less than the b-cut-off frequency.
dB/decade above 100 kHz. If the mid-band fre- (d) is equal to the b-cut-off frequency.
quency gain is 80 dB, what is the value of the volt- (1 Mark)
age gain at 2 MHz? 6. The conductance (gbc) takes into account the
(a) 60 dB (b) 52 dB (a) r esistance between the emitter and the collector
(c) 54 dB (d) 64 dB terminals.
(2 Marks) (b) conductance between the base and collector
3. The emitter diffusion capacitance for a transistor is due to flow of majority carriers.
(c) reduction in the flow of emitter current.
(a) proportional to the emitter-bias current. (d) feedback effect between the output and the
(b) inversely proportional to the emitter-bias input due to the early effect.
current. (1 Mark)

7. The Ohmic base spreading resistance is represented as (a) 2.22 80.38 (b) 2.22 80.38
(c) 3.22 80.38 (d) 3.22 80.38
(a) the increase in the recombination base current
(2 Marks)
due to the increase in the minority carriers in
the base region. 12. What is the expression for voltage gain and 3dB
(b) the conductance between the collector and the frequency neglecting the base spreading resistance,
emitter terminals. for the circuit shown in the following figure?
(c) a lump parameter between the external base
terminal and the node B. VCC
(d) the feedback effect between the output and the
input due to the early effect.
RL
(1 Mark)
8. Generally, the gain of a transistor amplifier falls at Vo
high frequencies due to the
(a) internal capacitances of the device CL
(b) coupling capacitor at the input Vi
(c) skin effect
(d) coupling capacitor at the output
(1 Mark)
gm RL 1
9. Each RC circuit causes the gain to drop at a rate of
1 + jw (Cm + CL )RL 2p (Cm + CL )RL
(a) ,
(a) 20 dB/decade
(b) 10 dB/decade gm RL 1
1 + jw (Cm /b + CL )RL 2p (Cm /b + CL )RL
(c) 6 dB/decade (b) ,
(d) depends upon the value of R and C
(1 Mark) bgm RL 1
1 + jw (Cm + CL )RL 2p (Cm + CL )bRL
(c) ,
10. A three-stage amplifier with identical stages has an
gm RL
overall lower and upper 3-dB cut-off frequencies of
1
10 Hz and 10 kHz, respectively. What is the band- (d) ,
width of the individual stages assuming that the 1 + jw CL RL 2p CL RL
stages are non-interactive stages? (2 Marks)
(a) 19605 Hz (b) 9990 Hz 13. For the cascaded amplifier shown in the figure
(c) 21564 Hz (d) 19500 Hz below, what is the overall upper cut-off frequency
(2 Marks) of the amplifier? Given that hfe of each transistor
is 100, hie is 850 , rbe is 600 , rbb is 250 , Cc
is 10 pF, Ce is 50 pF and gm = 1.50 103 mhos.
11. What is the value of voltage gain of the common-
source MOSFET amplifier at operating frequency of
20 MHz with drain resistance (RD) of 100 k. The (a) 2.9 MHz (b) 3.8 MHz
MOSFET parameters are gm = 1.5 mA/V, rd = (c) 4.5 MHz (d) 1.8 MHz
50 k, Cgs = 2.5 pF, Cds = 1.0 pF and Cgd = 2.8 pF. (2 Marks)
15 V
RC3
RB1 RC1 RC2
RB3 RB5 10 k
2 k 1 k 1.5 k Co
2 k 2 k
+
Rs Ci C1 C2 0.1 F
+ 500 0.1 0.1 F 0.1 F

+
Q1 Q2 Q3
F Vo
Vs Vi RB2 RB4 RB6
200 300 RE2 CE2 300
RE1

CE1 RE3 CE3
200 0.1 F 100 0.1 F 100 0.1 F


14. The following figure shows a common-emitter 18. For the common-drain MOSFET amplifier dis-
amplifier with an external capacitor CC connected cussed in Question 17, what is the value of voltage
between the base and the collector terminals. gain at operating frequency of 20 MHz?
Different parameters of the transistor are given as
(a) 0.581, +5.37 (b) 0.581, 5.37
gm = 5 mS, r = 20 k, C = 1.5 pF and Cm =
(c) 0.595, +5.37 (d) 0.478, 5.37
0.5 pF. What is the mid-band voltage gain and the
(2 Marks)
upper cut-off frequency of the amplifier?
19. The bandwidth of a single-stage amplifier extends
25 pF from 10 Hz to 100 KHz. What is the lower cut-off
frequency where the voltage gain is down by 1 dB
CC from its mid-band value?
(a) 20.5 Hz (b) 10 Hz
10 k (c) 4.5 Hz (d) 19.65 Hz
(2 Marks)
10 k
+ 20. What is the upper cut-off frequency where the volt-
Vi VCC
age gain is down by 1 dB from its mid-band value
in the case discussed in Question 19?
(a) 50 kHz (b) 100 kHz
(c) 51 kHz (d) 200 kHz
(a) 33.33, 0.1 Mrad/s (b) 22.23, 0.1 Mrad/s (2 Marks)
(c) 33.33, 0.2 Mrad/s (d) 22.23, 0.2 Mrad/s
(2 Marks) 21. Given a transistor with the following specifications:
gm = 38 mmhos, rbe = 5.9 k, hie = 6 k, rbb =
15. The cut-off frequency of a bipolar transistor 100 , Cbc = 12 pF, Cbe = 63 pF, fT = 80 MHz
increases with and hfe = 224 at 1 kHz. What is the value of -cut-
(a) increase in width of the emitter region off frequency and the value of common-emitter
(b) increase in width of the collector region short circuit gain at that frequency?
(c) decrease in width of the base region (a) 95.91 MHz, 0.838 0.21
(d) increase in width of the base region (b) 85.91 MHz, 0.838 0.21
(1 Mark) (c) 95.91 MHz, 0.838 0.21
16. The upper cut-off frequency of an RC-coupled (d) 85.91 MHz, 0.838 0.21
amplifier mainly depends upon (2 Marks)
(a) coupling capacitor 22. For the transistor discussed in Question 21, what is
(b) emitter bypass capacitor the b-cut-off frequency and the value of common-
(c) output capacitance of signal source emitter short circuit gain at that frequency?
(d) inter-electrode and stray shunt capacitances (a) 358.63 kHz, 158.39 45
(1 Mark) (b) 358.63 kHz, 158.39 45
17. Given a common-drain MOSFET amplifier with (c) 237.53 kHz, 126.78 45
source resistance (Rs) of 1 k. The MOSFET (d) 237.53 kHz, 126.78 45
parameters are gm = 1.5 mA/V, rd = 50 k, Cgs = (2 Marks)
2.5 pF, Cds = 1.0 pF, Cgd = 2.8 pF and Csn = 2.7 23. For the transistor discussed in Question 21, what
pF. What is the value of voltage gain at operating is the value of common-emitter short circuit gain
frequency of 20 kHz? at fT?
(a) 0.595, 0 (b) 0.478, 0 (a) 1 0.43 (b) 1 12
(c) 0.595, 180 (d) 0.478, 180 (c) 1 0 (d) 1 0.26
(1 Mark) (1 Mark)

1. For the cascaded amplifier shown in the following 2. For an amplifier having a single-pole high-frequency
figure, what is the overall upper cut-off frequency transfer function, the 3-dB bandwidth is 350 MHz.
(in kHz) of the amplifier? Given that hie for each What is the rise time of the amplifier (in s) in
transistor is 1000 , rbe is 800 , rbb is 200 , Cc response to a step-input function?
is 5 pF, Ce is 40 pF and gm = 60 103 mhos.
(1 Mark)
(1 Mark)
15 V
RC3
RC1 RC2
RB1 RB3 RB5 1 k
1 k 1 k Co
2 k 2 k 2 k
+
Rs Ci C1 C2 0.1 F
500 0.1 + Q1 0.1 F Q2 0.1 F Q3

+
F RB4 RB6
Vo
Vi RB2
200 RE2
Vs
200 RE1 200 RE3

CE1 CE2 CE3
100 0.1 F 100 0.1 F 100 0.1 F

1. (a) 10. (a) The lower cut-off frequency (fLn) for n identical
non-interactive stage amplifiers is
2. (c) It is given that the gain decreases at a rate of
20 dB/decade. Therefore, the gain decreases at a fL
rate of 6 dB/octave. Also, it is given that the mid- fLn =
band gain is 80 dB and the gain starts decreasing
1/n
2 1
at rate of 20 dB/decade above 100 kHz. Therefore, Given that n = 3 and fLn = 10 Hz. Therefore,
gain at 1 MHz is
Mid-band gain 20 dB = 60 dB fL = 10 0.257 = 5 Hz
Therefore, the gain at 2 MHz is The upper cut-off frequency (fHn) for n identical
Gain at 1 MHz 6 dB = 54 dB non-interactive stage amplifiers is
3. (a)
fHn = fH 21/n 1
4. (a)
5. (b) Given that fHn = 10 kHz and n = 3. Therefore,
6. (d) 10, 000

fH = = 19610 Hz
7. (c) 0.257
8. (a) Therefore, the bandwidth is

9. (a) 19610 5 = 19605 Hz

11. (c) For operating frequency of 20 MHz, we have Therefore, the voltage gain Av is given by
Y gs = jw Cgs = j 2 p 20 10 2.5 10 6 12 Vo gm RL
Av = =
1 + jp (Cm + CL )RL
= j3.14 104 W1
Vi
Y ds = jw Cds = j 2 p 20 106 1.0 1012 Therefore, 3-dB frequency is given by

4 1
= j1.26 10 W 1
Y gd = jw Cgd = j 2 p 20 106 2.8 1012 2p (Cm + CL )RL
= j3.52 104 W1 13. (a) Solution. The overall cut-off frequency can be
1 1 determined by determining the upper cut-off fre-
gd = = quency for each stage.
rd 50 103
= 2 105 W1
The upper cut-off frequency for the third stage
amplifier (fH3 ) is given by
1 1
GD = =
100 103
RD 1
2pR3 Ce + Cc (1 + gm RC3 )
fH3 =
= 1 105 W1
(RC2 RB5 RB6 + rbb3 ) rbe3
(RC2 RB5 RB6 + hie3 )
The value of voltage gain (Av) is given by R3 =
gm + Y gd
Av =
GD + Y ds + gd + Y gd Therefore,
1.5 103 + j3.52 104 (1500 2000 300 + 250 ) 600
(1500 2000 300 + 850 )
= 5 4 5 4
R3 =
110 + j1.26 10 + 210 + j3.5210
=
1.5 10 3
+ j3.52 10 4
(222.2 + 250 ) 600
(222.2 + 850 )
5 4
=
3 10 + j4.78 10
= 264.24 W
Multiplying and dividing by (3 105j 4.78 104),
we get 1
fH3 = Hz
23.1414264.24 [50 1012 + 10 1012
( 1.5103 + j3.52104 )(3105 j4.78104 )
(1 + 1.5103 10 103 )]
Av =
(3 105 + j4.78 104 ) (3 105 j4.78 104 )
4.5108 + j7.17 107 + j10.56 109 + 16.83108 =
1
Hz
23.1414264.24 50 1012 + 160 1012
= 10 8
910 + 22.8510
12.33108 + j7.28107 = 2.9 MHz
=
22.94108 The upper cut-off frequency for the second stage
(fH2 ) is given by
Therefore, 1
(12.33 10 8 )2 + (7.28 107 )2 2pR2 Ce + Cc (1 + gm RL2 )
fH2 =
Av = = 3.22
22.94 10 8
The effective value of load resistance for the second
stage (RL2 ) is given by
Hence,
7.28107
Av = tan1 1
= tan (-5.9) = 80.38
12.33108
RL2 = RC2 R B5 R B6 hie3
12. (a) Input voltage RL2 = 1500 2000 300 850 W = 176.15 W
Vi = Vb e
Output voltage The value of R2 is given by
Vo = gm Vbe
RL (RC1 RB3 RB4 + rbb2 ) rbe2
(RC1 RB3 RB4 + hie2 )
R2 =
1 + jw (Cm + CL )RL

Therefore, (133.33 + 250 )

600
(1000 2000 300 + 250 )
R1 =
(133.33 + 850 )
600
(1000 2000 300 + 850 )
R2 =
383.33
= 600 = 233.897 W
983.33
(206.9 + 250 )
600
(206.9 + 850 )
= 1
fH1 =
2 3.1414 233.897 [50 1012 + 10 1012
456.9
= 600 (1 + 1.5 103 166.95)]]
1056.9
1
= 259.38 =
23.1414233.897 50 1012 + 13.51 1012

1
fH2 =
23.1414259.38[50 1012 + 10 1012
= 10.714 MHz
(1 + 1.5103 176.15)] The overall upper cut-off frequency is limited by

the cut-off frequency of the third stage since it is
1 more than three times less than the cut-off fre-
=
23.1414259.38 50 1012 + 12.6 1012 quency of the other two stages.
The overall upper cut-off frequency is approxi-
1 mately 2.9 MHz
+ = 9.795 MHz
102090.12 1012 14. (a) The equivalent circuit of the amplifier is shown
The upper cut-off frequency for the first stage (fH1 )
is given by
1 10 k rbb 25 pF
2pR1 Ce + Cc (1 + gm RL1 )
fH1 =
Cp
Vi rp Cp g m Vp 10 k
The effective value of load resistance for the first
stage (RL1 ) is given by
RL1 = RC1 R B3 R B4 hie2
The equivalent circuit can be further simplified as
Therefore, shown in the figure below using Millers theorem.
RL = 1000 2000 3000 850
The capacitance between the input terminals Ci is
given by
= 166.395 Ci = Cp + (1 + gm RL )Cm
The value of ( R1 ) is given by Therefore, Ci = (1.5 + 1300.5) pF = 1302 pF.
(RS )
R B1 R B2 + rbb1 rbe1
Vo =
gm Vp 10 103
1 + jw 25.5 1012 10 103
(RS )
R1 =
R B1 R B2 + hie1
gm Vp 10 103
=
Therefore, 1 + jw 25.55 108
(500 2000 200 + 250 ) 600 gm Vp 10 103
(500 2000 200 + 850 )
R1 =
=
1 + j(w /w Ho )
10 k rbb
Ci
Vi rp Cp 1300.5 pF gmVp Co= 25.2 pF 10 k

where where
108 30 103 104
w Ho = rad/s = 39.2 Mrad/s w Hi = rad/s = 0.115 Mrad/s
25.5 2604
Now,

Therefore,
Vp = Vo Vp gm 10 103
Vi

10 103 + r + r (1 + jw 13021012 20 103 )
0.666
=
1 + j(w w Hi )
bb p Vp Vi 1 + j(w w Ho )
rp
12 Solving the above equation, we get
1 + jw 1302 10 20 103 Vo 33.33
=
Substituting the value of r and rbb in the above Vi [1 + ( jw /0.115 106 )] [1 + ( jw /39.2 106 )]
equation and solving it, we get
The mid-band voltage gain is
Vp 20 103
= Vo
Vi 10 103 + 20 103 + jw 2604 104 = 33.33
Vi
Multiplying and dividing by 30 103 and rear-
ranging terms, we get The upper cut-off frequency is given by the lower of
the two frequencies 0.115 Mrad/s and 39.2 Mrad/s.
Vp 0.666
= Therefore, the upper cut-off frequency is 0.115
Vi 1 + j(w w Hi ) Mrad/s 0.1 Mrad/s.
15. (a)
16. (d)
17. (a) Voltage gain of a common-drain amplifier is given by
( gm + jw Cgs ) Rs
1 + gm + gd + jw ( Cgs + Cds + Csn ) Rs
Av =

At 20 kHz
(1.5 103 + j 2 p 20 103 2.5 1012 ) 1 103
1 + 1.5 103 + (1 50 10+3 ) + j 2 p 20 103 ( 2.5 1012 + 1.0 1012 + 2.7 1012 ) 1 103
Av =

(1.5 + j100p 10 ) 6
=

1.5 + 314.2 10 j6
1 + 1.5 103 + 0.02 103 40p 103 j ( 6.2 1012 ) 1 103 2.52 + j779.15 10
= 6

The imaginary terms are negligible as compared to the real terms, therefore
1.5
Av = = 0.595
2.52
18. (b) At 20 MHz,
(1.5 10-3 + j 2 p 20 106 2.5 1012 ) 1103
1 + 1.5 103 + (1 50 10+3 ) + j 2 p 20 106 ( 2.5 1012 + 1.0 1012 + 2.7 1012 ) 1 103
Av =

(1.5 + j314.16 10 )3
1 + 1.52 + j 2 p 20 109 ( 6.2 1012 )

=

1.5 + 0.314 j (1.5 + 0.314 j )(2.52 0.779 j )
(2.52 + 0.779 j )(2.52 0.779 j )
= =
2.52 + 0.779 j
( 3. 78 1. 169 j + 0 .79 j + 0.245 )
=
6.35 + 0.607
4.025 0.379 j
=
6.96

Magnitude of gain
f
2
( 4.025 ) 2
+ ( 0.379 )
2
4.04 Hence, 1 + = 1.22
fH
Av = = = 0.581
6.96 6.96
f
2
0.379
Phase Av = tan1 = tan (0.094 )
1 or f = 0.259
4 . 025 H
= 5.37 Therefore, f = 51 kHz
19. (d) The low-frequency response of an amplifier is 21. (a)
given by
Av hfe 224
Av(low) = fa = =
fL 2prbe Cbe 2 p 5.9 103 63 1012
1 j f
= 95.91 MHz
At the frequency (f) where the gain is down by 1dB gbe
fb =
Av(low) 2p (Cb e + Cb c)
20 log = 1
Av
where
= 1.69 104
Avlow 1 1
Therefore, = 0.89 gbe = =
Av rbe 5.9 103
1 fL Therefore,
or 1.22 = 1 j
1.69 104
Hence, 0.89 =
fL f
1 j fb =
f 2 p (63 1012 + 12 1012 )
Therefore, = 358.63 kHz
f
2 The common-emitter short-circuit current gain is
1.22 = 1 + L
f
given by
hfe
Ai =
Given that fL = 10 Hz, therefore 1 + j(f/fb )
10
2 For f = f,
1.22 = 1 +
f

224
Ai =
Hence, f = 19.65 Hz {
1 + j (95.91106 )/(358.63103 ) }
=-
20. (c) The high frequency response of an amplifier is 224
given by 1 + 267.43 j
Av
Av(high) = 224
f Ai = = 0.838
1 + j f 1 + (267.43)2
2
H
Ai = 90 tan1(267.43)
The frequency (f) at which the gain decreases by 1 = 90 89.786 = 0.21
dB the gain is given by
22. (b) From the solution of Question 21, fb =
Av(high)
20 log = 1 358.63 KHZ
Av
For f = fb,
Av(high)
=-
224 224
Ai =
{ }
Therefore, = 0.89
Av 1 + j (358.6310 )/(358.6310 )
3 3 1+ j
Therefore, 224
1 Ai = = 158.39
0.89 = 2
f
2
1+ Therefore,
fH Ai = 90 tan1(1) = 90 45 = 45

224
23. (d) fT = hfe fb =
1 + 224 j
= 224 358.63 103 = 80.333 MHz 224
Ai = =1
For f = fT, 12 + 2242
224
Ai =
{ }
Therefore,
1 + j (80.333 106 )/(358.63 103 ) Ai = 90 tan1 (224) = 90 89.744 = 0.256
1. The overall upper cut-off frequency can be determined by determining the upper cut-off frequency for each stage.
The upper cut-off frequency for the third stage amplifier (fH3) is given by
1
fH3 =
2pR3 [Ce + Cc (1 + gm RC3 )]
where
(RC2 RB5 RB6 + rbb3 ) rbe3 (1000 2000 200 + 2000 ) 800
R3= = = 245.34 W
(RC2 RB5 RB6 + hie3 ) (1000 2000 200 + 1000 )
Therefore,
1
fH3 = 12
= 1.88 MHz
2 3.1414 245.34 [40 10 + 5 1012 (1 + 60 103 1 103 )]
The upper cut-off frequency for the second stage (fH2) is given by
1
fH2 =
2p R2 [Ce + Cc (1 + gm RL2 )]
The effective value of load resistance for the second stage ( RL2 ) is given by
RL2 = RC2 RB5 RB6 hie3
= 1000 2000 200 1000 = 133.33
The value of R2 is given by

(RC1 RB3 RB4 + rbb2 ) rbe2 (1000 2000 200 + 2000 ) 800
R2 = = = 245.34 W
(RC1 RB3 RB4 + hie2 ) (1000 2000 200 + 1000 )
Therefore,
1
fH2 = 12
= 7.632 MHz
2 3.1414 245.34 [40 10 + 5 1012 (1 + 60 103 133.33)]
The upper cut-off frequency for the first stage (fH1) is given by
1
fH1 =
2p R1 [Ce + Cc (1 + gm RL1 )]
The effective load resistance for the first stage (RL1) is given by
RL1 = RC1 RB3 RB4 hie2 = 1000 2000 200 1000 = 133.33

The value of R1 is given by

(Rs RB1 RB2 + rbb1 ) rbe1 (500 2000 200 + 200 ) 800
R1 = = = 235.292 W
(Rs RB1 RB2 + hie1 ) (500 2000 200 + 1000 )
1
fH1 = 12
= 7.967 MHz
2 3.1414 235.292[40 10 + 5 1012 (1 + 60 103 133.33)]
The overall upper cut-off frequency is limited by the cut-off frequency of the first stage as it is around four times less
than the cut-off frequencies of the other two stages. The overall upper cut-off frequency is approximately 1.88 MHz,
that is, 1880 kHz.
Ans. (1880)
2. Rise time (in s) = 0.350/Bandwidth (in MHz) = 0.350/350s = 0.001s
Ans. (0.001)
1. A bipolar transistor is operating in the active C

region with a collector current of 1 mA. Assuming
that the b of the transistor is 100 and the thermal
voltage (VT) is 25 mV, the transconductance (gm) 7 pF
and the input resistance (rp) of the transistor in
the common emitter configuration, are
(a) gm = 25 mA/V and rp = 15.625 k
(b) gm = 40 mA/V and rp = 4.0 k
(c) gm = 25 mA/V and rp = 2.5 k
(d) gm = 40 mA/V and rp = 2.5 k 1 pF
(GATE 2004 : 2 Marks) V
0
Solution.
IC
gm =
VT 2. The gate oxide thickness in the MOS capacitor is
Therefore, (a) 50 nm (b) 143 nm

(c) 350 nm (d) 1 mm
1 103 (GATE 2007 : 2 Marks)
gm = A/V = 40 mA/V
25 103
Solution. The capacitance is given by
Also, b = gm rp . Therefore,
eA
W = 2.5 kW
100 C=
rp =
40 103
d
Ans. (d) Therefore,

3.5 1013 104
7 1012 =
Common Data Question 2, 3 and 4: The follow-
ing figure shows the high-frequency capacitance-voltage d
(C-V) characteristics of a metal/SiO2/silicon (MOS)
capacitor having an area of 1 104 cm2. Assume that where d is the gate oxide thickness (in cm).
the permittivities (or) of silicon and SiO2 are 1 Therefore, d = 50 nm.
1012 F/cm and 3.5 1013 F/cm, respectively. Ans. (a)

3. The maximum depletion layer width in silicon is 5. The AC schematic of an NMOS common source
(a) 0.143 m (b) 0.857 m
stage is shown in the following figure, where part of
(c) 1 m (d) 1.143 m
the biasing circuits has been omitted for simplicity.
For the N-channel MOSFET M, the transconduc-
tance gm = 1 mA/V, and body effect and chan-
nel length modulation effect are to be neglected.
Solution. The capacitance is given by
The lower cut-off frequency (in Hz) of the circuit is
eA approximately at
C=
d
Therefore, RD = 10 k
12 4
1 10 10
1 1012 = Vo
d Vi
C = 1 F
where d is the depletion width (in cm). Therefore, M RL = 10 k
d = 104 cm = 1 m.
Ans. (c)
4. Consider the following statements about the C-V (a) 8 (b) 32
characteristics plot: (c) 50 (d) 200
S1: The MOS capacitor has a N-type substrate. (GATE 2013: 2 Marks)
S2: If positive charges are introduced in the oxide,
the C-V plot will shift to the left. Solution. The lower cut-off frequency fL is given
Then which of the following is true? by
(a) Both S1 and S2 are true 1
fL =
(b) S1 is true and S2 is false 2p(RL + RD )C
(c) S1 is false and S2 is true
1
(d) Both S1 and S2 are false = = 8 Hz
(GATE 2007: 2 Marks) 2 3.14 (10 10 + 10 103 ) 1 106
3
Ans. (d) Ans. (a)

CHAPTER 18
SIMPLE OPAMP CIRCUITS
This chapter discusses the simple opamp circuits including the inverting and non-inverting amplifiers, voltage follower,
summing and difference amplifiers, averager, integrators and differentiators, recitifiers, clippers and clampers, peak
detector circuit, absolute value circuit, comparators (including window comparator), phase shifters, instrumentation
amplifiers, non-linear amplifiers, relaxation oscillators, current-to-voltage, voltage-to-current converters and active
filters. Opamp-based oscillators are discussed in Chapter 20.
18.1 INVERTING AMPLIFIER R2
I
An inverting amplifier is the one, which in addition R1
to changing the amplitude of the signal, changes the Vi
polarity of the input signal in the case of DC input and I Vo
+
reverses the phase of the input signal in the case of AC
input. Figure 18.1 shows the basic circuit diagram of an
inverting amplifier configured around an opamp.
The ideal closed-loop voltage gain (ACL) is given by
Figure 18.1| Inverting amplifier.
R
ACL = 2 (18.1) The actual expression for the closed-loop gain ACL for the
R1 inverting amplifier circuit shown in Fig. 18.1 is given by

404 Chapter 18: Simple Opamp Circuits
AOL R2 R2 R2
ACL = (18.2) ACL = 1 + (18.7)
R1 + R2 + AOL R1 R1 + ( R2 AOL ) R1
R1 R2
where AOL is the open-loop gain of the opamp. This
implies that when ratio R2/AOL is much smaller than
i i
R1, the gain expression reduces to the gain expression of

Eq. (18.1). The input impedance of this circuit is same
as the input resistance value, R1. The output impedance
Vo
of this circuit (Ro) is approximated as
Vi +
R + R2
Ro = 1 ROL Figure 18.3| Non-inverting amplifier.
(18.3)
R1AOL
where ROL is the open-loop output impedance of the The actual gain expression in the case of a non-inverting
opamp. amplifier is given by
AOL (R1 + R2 )
ACL = (18.8)
R2 R1 + R2 + AOL R1
R1
Vi The input impedance (Ri) of this configuration is given by
C1 Vo
+ R1
C2 Ri = RIL AOL
R1 + R2
= RIL Loop gain (18.9)

where RIL is the open-loop input impedance and the loop
Figure 18.2| Inverting amplifier for AC applications. gain is
Open-loop gain
If the inverting amplifier shown in Fig. 18.1 is needed
to amplify AC signals only, the circuit may be modified Closed-loop gain
to include coupling capacitors in series with input and
The output impedance (Ro) can be computed from the
output as shown in Fig. 18.2. The frequency response of
following equation:
this amplifier does not extend down to zero. The cou-
pling capacitors give a lower cut-off frequency depending ROL
Ro = (18.10)
upon the values of R1 and C1 on the input side and RL Loop gain
(load resistance) and C2 on the output side. The lower where ROL is the open-loop output impedance of the
cut-off frequency may be taken to be equal to higher of opamp.
the two values. The two cut-off frequencies are given by
Eqs. (18.4) and (18.5). In case the non-inverting amplifier shown in Fig. 18.3
is needed to amplify AC signals only, the circuit may
1 be modified to include coupling capacitors C1 and C2 in
fCL1 = (18.4)
2pR1C1 series with input and output, respectively, and a bypass

1 capacitor C3 as shown in Fig. 18.4. The coupling capaci-
fCL2 = (18.5) tors give a lower cut-off frequency depending upon the
2pRL C2 values of R3 and C1 on the input side and RL (load

The closed-loop bandwidth or upper cut-off frequency resistance) and C2 on the output side. The two cut-off
(fCH) is given by Eq. (18.6). frequencies are given by the following equations:
Unity gain cross-over frequency 1
fCH = (18.6) fCL1 = (18.11)
ACL 2pR3C1

1
fCL2 = (18.12)
18.2 NON-INVERTING AMPLIFIER 2pRL C2

The bypass capacitor produces a lower cut-off frequency
Figure 18.3 shows a non-inverting amplifier for DC given by
applications. The ideal closed-loop voltage gain (ACL) 1
fCL3 = (18.13)
is given by 2pR1C3


18.4 SUMMING AMPLIFIER 405
The lower cut-off frequency may be taken as the highest low because due to unity closed-loop gain, input errors
of the three values. The upper cut-off frequency is given are not amplified.
by the ratio of unity gain cross-over frequency to the
closed-loop gain.
18.4 SUMMING AMPLIFIER
C3 R1 R2
A summing amplifier produces an output that is equal
to the sum of input signals multiplied by corresponding
Vo voltage gain values. In the case of voltage gain being
Vi + unity for all input signals, the circuit becomes an adder
C2
circuit.
C1
R1 R4
R3
V1
I
I1
R2
Figure 18.4| Non-inverting amplifier for AC signals.
V2 Vo
+
I2 R
3
18.3 VOLTAGE FOLLOWER V3
I3 R5
The voltage follower is nothing but a non-inverting
amplifier circuit with unity gain. Figure 18.5 shows the
Figure 18.6| Inverting-type summing amplifier.
basic voltage-follower circuit.
Figure 18.6 shows circuit diagram of three input invert-

ing-type summing amplifier. The output voltage Vo is
given by
Vo R R4 R4
Vi + V o = 4 V1 + V2 + V3 (18.14)
R1 R2 R3
Figure 18.5| DC voltage-follower circuit. If R1 = R2 = R3 = R4 = R , then
A voltage-follower circuit has many advantages. Owing Vo = (V1 + V2 + V3 ) (18.15)

to its extremely high input impedance, extremely low
output impedance and unity gain; it acts as an ideal A non-inverting summing amplifier can be constructed
interface between a high impedance source and a low from its inverting counterpart by cascading it with a
impedance load. Also, unity closed-loop gain leads to a unity gain inverting amplifier (Fig. 18.7).
very high closed-loop bandwidth equal to the unity gain An alternative non-inverting adder circuit, where the
cross-over frequency. The output offset error is also very summing has been done at the non-inverting input, is
R4 R7
R1
V1 R6
R2
V2 + Vo1 Vo2
R3 +
V3
R5
Figure 18.7| Non-inverting summing amplifier.

shown in Fig. 18.8. The given circuit behaves like a non- Vo = V2 V1 (18.18)
inverting amplifier with a gain of 1 to both the inputs.
Figure 18.10 shows an alternative configuration for
designing a subtractor circuit, with output voltage Vo
2R
equal to V1 V2.
R
R R
R Vo
+ R

V1 R
V2
R V1
+ R
V2 + Vo
R
Figure 18.10| Alternative form of subtractor circuit.
Figure 18.8| Non-inverting adder with single opamp.

The output voltage Vo is given by 18.6 AVERAGER
Vo = V1 + V2 (18.16)
An averager circuit produces an output that is equal to
If the adder circuit shown in Fig. 18.8 were to be used average of the amplitudes of the applied input signals.
for adding n inputs, the feedback resistor value would be Figure 18.11 shows the generalized form of an averager
equal to nR. circuit for n inputs. The circuit configuration is simi-
lar to that of an inverting-type summing amplifier. The
output voltage Vo is given by
18.5 DIFFERENCE AMPLIFIER
V + V2 + V3 + + V n
(SUBTRACTOR) Vo = 1 (18.19)
n
A non-inverting averager may be built by connecting a
A difference amplifier produces an output that is equal unity gain inverting amplifier at the output of the circuit
to the difference of the two input signals multiplied by shown in Fig. 18.11.
corresponding voltage gain values. In the case of voltage
gain being unity for the two input signals, the circuit
becomes a subtractor circuit. Figure 18.9 shows the gen- R
eralized form of a difference amplifier. nR
V1
R2 nR Vo
V2 +
R1
V1
Vo nR
V2 + Vn
R3 Figure 18.11| Averager circuit.
R4
18.7 INTEGRATOR
Figure 18.9| Difference amplifier.
An integrator circuit is the one that produces an output
The output voltage Vo is given by proportional to the integral of the input. Figure 18.12
R4 R2 R2 shows the circuit diagram. Since non-inverting input ter-
Vo = 1 + V2 V1 (18.17)
R3 + R4 R1 R1
minal has been grounded, virtual earth appears at RC
junction. Thus, the voltage Vo effectively is the voltage
For R1 = R2 = R3 = R4 = R, across the capacitor C. The output voltage Vo is given by

18.8 DIFFERENTIATOR 407
RC i
V dt = K Vi dt
1
Vo = (18.20) 18.8 DIFFERENTIATOR

where A differentiator circuit is the one that produces an output
proportional to the differential of the input. Figure 18.14
1
K = shows the circuit diagram. Since non-inverting input ter-
RC minal has been grounded, virtual earth appears at RC
junction. Thus, the voltage Vo effectively is the voltage
C across resistor R.
I R
R
Vi C I
I Vo Vi
+ I Vo
+
Figure 18.12| Integrator.

Figure 18.14| Differentiator.
The basic integrator circuit suffers from DC insta-
bility problems. The circuit offers a very high gain
The output voltage Vo is given by
to DC which means that even in the absence of any
dVi dV
Vo = RC
input, small input offset voltage might cause the
=K i (18.22)
output to go to positive or negative saturation. This dt dt
problem can be overcome by connecting a relatively
where
large value resistor across C. This resistor limits the
DC gain to a lower value and it may be chosen to be K = RC
10 times the input resistor. Non-inverting integrator The basic differentiator circuit has a tendency to go
may be built by connecting a unity gain inverting into oscillations at relatively higher frequencies. The prob-
amplifier at the output of inverting integrator circuit lem can be overcome by connecting a resistor in series with
shown in Fig. 18.12. the input capacitor. The resistor limits the gain at higher
frequencies. The value of this resistor may be chosen to be
C in the range of one-tenth to one-hundredth of the feedback
resistor. Non-inverting differentiator may be built by con-
R necting a unity gain inverting amplifier at the output of
V1 inverting differentiator circuit shown in Fig. 18.14.
R Vo Figure 18.15 shows the schematic arrangement of a sum-
V2 + ming differentiator. The circuit produces an output propor-
V2 tional to the sum of the differentials of multiple inputs.
R dV dV dV
Vo = RC 1 + 2 + 3 (18.23)
dt dt dt
Figure 18.13| Summing integrator.
R
Figure 18.13 shows another variation of integrator cir-
C I
cuit. The circuit produces an output proportional to sum
of integrals of multiple inputs. That is,
V1
I1 Vo
C
( V1dt + V2dt + V3dt)
V2 +
Vo = K (18.21) I2
V3
I3
where C
1
K = Figure 18.15| Summing differentiator.
RC

18.9 RECTIFIER CIRCUITS positive or in negative direction, the output tends to

go to negative or positive saturation, respectively. It is
therefore not necessary for the input to exceed the diode
The conventional rectifier circuits do not produce an drop to produce the output. However, maximum values
ideal rectified waveform at the output due to forward- of peak positive output and peak negative output are
biased voltage drop across the diode, which is 0.7 V in Vsat 0.7 and Vsat + 0.7, respectively.
the case of silicon diodes. This problem is overcome in The two half-wave rectified outputs can be summed
opamp-based rectifier circuits. Figure 18.16 shows the up in another opamp stage to get a full-wave rectified
generalized half-wave rectifier circuit built around an output as shown in Fig. 18.17.
opamp. The circuit functions as follows. Owing to non-
inverting input of the opamp being at ground potential, Figure 18.18 shows an alternative circuit arrangement
during positive half cycles, diode D1 is forward-biased for building a full-wave rectifier. During the positive half
and the diode D2 is reverse-biased. The positive half cycle of the input signal, the diode is reverse-biased and
cycles appear as negative half cycles due to phase inver- therefore the feedback resistor is disconnected from the
sion. Similarly, during negative half cycles, diode D1 is output of the opamp. The positive half cycles appear
reverse-biased and diode D2 is forward-biased with the as such at the output. During the negative half cycles,
result that negative half cycles appear as positive half the diode is forward-biased. The negative half cycles get
cycles again due to phase inversion. Remember that the inverted and again appear as positive half cycles. Thus
moment input increases by a few milli-volts either in the output is a full-wave rectified signal.
Vo1 Vi
R2 D1
R3 t
R1 D2 Vo1
Vo2
t
+
Vi Vo2
t
Figure 18.16| Half-wave rectifier.
D1 R5
R2
R4 Vi

Vo
t
R3 +
R6
R1 Vo
D2 R7
+ t
Vi
Figure 18.17| Full-wave rectifier.

18.11 CLAMPER CIRCUITS 409
Figure 18.20(a) shows a negative clipper circuit. The circuit

R1 R2 functions as follows. During the positive half cycles and also
for input voltages less negative or equal to Vref, diode D1
Vo is reverse-biased. The input appears as such at the output.
Vi + For input voltages more negative than Vref, diode D1 is
forward-biased and the output gets clamped at the refer-
ence voltage. The input and output waveforms are shown
in Fig. 18.20(b). When the polarity of the reference voltage
is reversed, clipping occurs above zero voltage. The output
Figure 18.18| Full-wave rectifier an alternative waveform in this case is also shown in Fig. 18.20(b).
arrangement.
R1
18.10 CLIPPER CIRCUITS Vi D1
Vo
Vref +
Figure 18.19(a) shows a positive clipper circuit, a clip-
per circuit that clips positive half cycles above a certain (a)
positive reference voltage. The circuit functions as fol-
lows. During the positive half cycles, for input voltages Vi
less than or equal to reference voltage (Vref), the opamp Vm
output goes to positive saturation and diode D1 is reverse- Vref
biased with the result that the input appears as such at t
the output. The situation is same during negative half
cycles. When the input voltage exceeds the reference volt- Vo
age, the opamp output goes to negative saturation and Vm
the diode gets forward-biased. The output gets shorted to
t
inverting input and the output is clamped to Vref. The Vref
input and output waveforms are shown in Fig. 18.19(b).
If the polarity of the reference voltage is reversed in the Vo
clipper circuit shown in Fig. 18.19(a), the clipping occurs Vm
below zero voltage as shown in Fig. 18.19(b). Vref
t
(b)
Figure 18.20| Negative clipper circuit and relevant
R1
Vi D1
waveforms.
Vo
Vref +
18.11 CLAMPER CIRCUITS
(a)
Vi
Figure 18.21 shows the positive clamper circuit that
Vref clamps the negative peaks to zero. The circuit operates as
t follows. During the first negative half cycle, diode D1 gets
Vm forward-biased and capacitor C charges through resis-
Vo tance R and the forward-biased diode to the peak of the
negative half cycle voltage. During the positive cycle, the
Vref diode gets reverse-biased. There is no rapid discharge path
t
for the capacitor and in this case, the output equals the
Vm input voltage plus the voltage across the capacitor. The
Vo negative peaks are thus clamped to zero voltage. If the
non-inverting input is applied a reference voltage (Vref),
t
Vref positive or negative, the negative peaks are clamped at
Vm Vref instead of zero. Figure 18.22 shows the negative clam-
per circuit that clamps positive peaks to zero. Again, if
(b) the non-inverting input is applied a reference voltage Vref,
Figure 18.19| Positive clipper circuit and relevant positive or negative, the positive peaks are clamped at
waveforms. Vref instead of zero.

Vi
+Vm
t
C R
Vi D1 Vm
Vo Vo
+
+2Vm
+Vm
t
Figure 18.21| Positive clamper circuit.
Vi
+ Vm
t
C R
Vi D1 Vm
Vo Vo
+ t
Vm
2Vm
Figure 18.22| Negative clamper circuit.
The conventional clamper circuit cannot function as detectorcircuit. As we can see, it is essentially a clipper
a clamper if the peak input signal is less than 0.7 V. circuit with a parallel resistorcapacitor connected at
The opamp-based clamper circuit has no such limitation. its output. The clipper here reproduces the positive half
Itfunctions as if the diode is ideal. This implies that the cycles. During this period, the diode is forward-biased.
circuit can be used to clamp even milli-volt signals. The capacitor rapidly charges to the positive peak from
the output of the opamp through the ON resistance of
the forward-biased diode. As the input starts decreas-
18.12 PEAK DETECTOR CIRCUIT ing beyond the peak, the diode gets reverse-biased, thus
isolating the capacitor C from the output of the opamp.
The capacitor can now discharge only through the resis-
Peak detector circuit produces a voltage at the output tor R connected across it. The value of the resistor R is
equal to peak amplitude (positive or negative) of much larger than the forward-biased diodes ON resis-
the input signal. Figure 18.23 shows a positive peak tance. The purpose of this resistor is to allow a discharge
R2 R4
D1
R3 Vo
R1 +
Vi +
C R
Figure 18.23| Peak detector circuit.

18.14 COMPARATOR 411
path so that the output can respond to changing ampli- Thus, the output voltage always equals the absolute
tudes of the signal peaks, decreasing amplitudes of the value of theinput.
signal peaks to be more precise. The buffer circuit con-
nected ahead of the capacitor prevents any discharge
of the capacitor due to loading effects of the following 18.14 COMPARATOR
circuit. The circuit can be made to respond to the nega-
tive peaks by reversing the polarity of the diode. Rest of
A comparator circuit is a two-input, one-output building
the circuit is the same.
block that produces a high or low output depending upon
The parallel RC circuit time constant is typically 100 the relative magnitudes of the two inputs. An opamp can
times the time period corresponding to the minimum be very conveniently used as a comparator when used
frequency of operation. The RC time constant also con- without negative feedback. Because of very large value
trols the response time. The response time is nothing but of open-loop voltage gain, it produces either positively
the time needed to respond to a decreasing amplitude. saturated or negatively saturated output voltage depend-
Surely, a large time constant would make the response ing upon whether the amplitude of the voltage applied at
more sluggish. An attempt to reduce the time constant the non-inverting input terminal is more or less positive
to improve the response time increases the output ripple. than the voltage applied at the inverting input terminal.
The chosen time constant is a compromise of the two
One of the inputs of the comparator is generally applied
conflicting requirements. Slew rate is the primary speci-
a reference voltage and the other input is fed with the input
fication that needs to be looked into while choosing the
voltage that needs to be compared with the reference volt-
right opamp for the clipper portion. The desired slew
age. In a special case where the reference voltage is zero, the
rate is such that the slew rate limited frequency, which
circuit is referred to as zero-crossing detector. Figure 18.25
is a function of peak-to-peak output swing and the slew
shows the basic circuit arrangement of a non-inverting type
rate, is at least equal to the highest frequency of opera-
of zero-crossing detector along with its transfer character-
tion. The peak-to-peak voltage swing at the output of
the opamp is equal to Vpk (Vsat) = (Vpk + Vsat).
istics. Here, R is the current limiting resistor. It is called a
non-inverting zero-crossing detector because an input more
Here, Vpk is the maximum peak amplitude of the input
signal and Vsat is the maximum negative.
positive than zero leads to a positively saturated output
voltage. Diodes D1 and D2 connected at the input are to
protect the sensitive input circuits inside the opamp from
18.13 ABSOLUTE VALUE CIRCUIT excessively large input voltages. Some opamps are specially
designed and optimized for use as comparators. These
devices have in-built protection diodes and therefore do
Figure 18.24 shows one possible opamp configuration not require external diode clamps.
that produces at its output a voltage equal to the abso-
lute value of the input voltage. The circuit shown is a R
dual half-wave rectifier circuit discussed earlier followed Vi +
by a difference amplifier. Vo

D1 R
R D1 D2
R
Vo
A2
R +
Vi R
D2
A1 Vo
+
+Vsat
Figure 18.24| Absolute value circuit.
When the applied input is of positive polarity (say, +V), Vi
diode D1 is forward-biased and diode D2 is reverse-biased.
A simple mathematics shows that the output Vo in this Vsat
case is equal to +V. When the applied input is of nega-
tive polarity (say, V), diode D1 is reverse-biased and
diode D2 is forward-biased. The output voltage Vo=V. Figure 18.25| Non-inverting zero-crossing detector.

R
Vi Vi +
Vo R1 Vo
+ +VCC
D1 D2
R2
Figure 18.28| Non-inverting comparator with positive

Vo reference voltage.
R2
+Vsat +VCC
R1 + R2
Figure 18.29 shows the circuit diagram of non-inverting
Vi
comparator for a negative reference voltage. The refer-
ence voltage Vref is given by
Vsat
R2
VCC
R1 + R2
Figure 18.26| Inverting zero-crossing detector.
The inverting-type voltage comparators can similarly be
built for positive and negative reference voltages.
Figure 18.26 shows the inverting type of zero-crossing
detector along with its transfer characteristics. In this Vi +
case, the input voltage slightly more positive than zero R1 Vo
produces a negatively saturated output voltage. One VCC
common application of zero-crossing detector is to con-
vert sine wave signal to a square wave signal. Figures R2
18.27(a) and (b), respectively, show relevant waveforms
for non-inverting and inverting type of zero-crossing
detector circuits.
Figure 18.29| Non-inverting comparator for negative
reference voltage.
Vi Vi
18.14.1 Opamp Comparator
t t
In the preceding paragraphs, we have discussed about
the use of general-purpose opamps as voltage compara-
tors. As outlined earlier, there are opamps that are par-
Vo Vo
+Vsat ticularly designed and optimized for use as comparators.
+Vsat
General-purpose opamp when used as a comparator suf-
t t fers from slew rate limitation. Relatively lower slew rate
forces the transition time from one state to the other to
be prohibitively large. Though this problem can be over-
Vsat Vsat come by using a high-speed opamp with a higher slew
rate specification, a better design approach to overcome this
(a) (b) limitation is by eliminating the compensation capacitor.
Figure 18.27| Waveforms of zero-crossing detector. It may be mentioned here that comparator works as a
non-linear circuit and therefore elimination of compen-
In the generalized case, reference voltage may be a posi- sation capacitor has no derogatory effect on the perfor-
tive or a negative voltage. Figure 18.28 shows the circuit mance. With compensation capacitor removed, the only
diagram of non-inverting comparator for a positive refer- capacitance remaining is the stray capacitance across the
ence voltage. In this case, Vref is given by output. Thus, slew rates can be very high.

18.14 COMPARATOR 413
+VCC 18.14.2 Comparator with Hysteresis

D2
Q4 When the input signal to comparator contains noise,
transitions at the output around the trip point tend to
R1 become highly erratic. Instead of being smooth from one
Output
Input (+) state to the other, transition around the trip point is a
cluster of pulses with randomly varying pulse width. The
problem becomes particularly severe if the input signal
were changing slowly. This phenomenon is demonstrated
Input () in Fig. 18.31.
Q1 Q2
Figure 18.32(a) shows the circuit schematic of an
inverting comparator with hysteresis along with its
Q5 transfer characteristics. The circuit functions as follows.
Let us assume that the output is in positive saturation.
D1 Q3
The voltage at the non-inverting input in this case is
R1
Figure 18.30| Basic circuit schematic arrangement of Vsat
R1 + R2
opamp comparator.
Now, the input signal needs to be more positive than this
Another important parameter of a comparator is its
voltage for the output to go to negative saturation. Once
ability to operate from a single supply and interface
the output goes to negative saturation, voltage fed back
conveniently with popular logic families. Circuit of
to non-inverting input becomes
opamp comparator is tailored to meet these two require-
ments. Figure 18.30 shows the simplified schematic R1
Vsat
diagram of opamp comparator. As seen in the figure, R1 + R2
the output has an open-collector output stage. For the
output stage to work properly, the output terminal The input signal amplitude needs to become more nega-
needs to be connected to the positive supply voltage tive than this for the output to go to positive saturation.
through an external resistor called pull-up resistor. It In this manner, the circuit offers a hysteresis of
is called pull-up resistor as it pulls the output voltage R1
2Vsat
R1 + R2
to the supply voltage when the output transistor Q5
(in Fig. 18.30) is in cut-off state. Not all comparators
have an open-collector output stage. In fact, pull-up The non-inverting comparator with hysteresis can be
resistor slows down the response time of the compara- built by applying the input signal to the non-inverting
tor. There are opamp comparators with active pull-up input as shown in Fig. 18.32(b). The operation of the
output stage that are capable of producing relatively circuit can be explained on lines similar to that of its
much faster switching times. These comparators need inverting counterpart. The upper trip point (UTP) and
dual power supplies. the lower trip point (LTP) are, respectively, given by
V V
Threshold
Input
Threshold
Output
Output Input
t t
(a) (b)
Figure 18.31| Erratic transitions caused by noisy input signal: (a) Ideal input signal; (b) noisy input signal.

Vo
Vi
Vo +Vsat
+
R2 Vi
R1 O
Vsat
(a)
Vo
+Vsat

Vo
+
Vi
Vi
O
R1 R2
Vsat
(b)
Figure 18.32| (a) Inverting comparator with hysteresis; (b) Non-inverting comparator with hysteresis.
R R there are two reference voltages called the lower and the
+Vsat 1 and Vsat 1
R2 R2 upper trip points. Output is in one state when the input
is inside the window created by the lower and upper
The hysteresis in this case is trip points and in the other state when it is outside the
window. Figure 18.33 shows the basic circuit diagram of
R one such window comparator. The circuit functions as
2Vsat 1
R2 follows: When the input voltage is less than the voltage
reference corresponding to the LTP, output of opamp A1
is at +Vsat and that of opamp A2 is at Vsat. Diodes
18.14.3 Window Comparator D1 and D2, respectively, are forward- and reverse-biased.
Consequently, the output across RL is at +Vsat. When
In the case of conventional comparator, the output the input voltage is greater than the reference voltage
changes state when the input voltage goes above or below corresponding to the UTP, the output of opamp A1 is at
the preset reference voltage. In a window comparator, Vsat and that of opamp A2 is at +Vsat. Diodes D1 and
D2, respectively, are reverse- and forward-biased with the
result that the output across RL is again at +Vsat. When
the input voltage is greater than the LTP voltage and
LTP + D1
lower than the UTP voltage, the output of both opamps
A1 is at negative saturation with the result that diodes D1
and D2 are reverse-biased and the output across RL
is zero.
Vi Vo
Figure 18.34(a) shows the transfer characteristics of
+ this window comparator. The transfer characteristics
RL
A2 shown in Fig. 18.34(b) can be obtained if we interchange
UTP the positions of LTPs and UTPs and the comparators
D2
used are the ones with an open-collector output. In this
Figure 18.33| Window comparator.

case, a pull-up resistor will be connected from the output
pin of the comparator to the supply terminal.

18.15 PHASE SHIFTERS 415
Vo
Vo
+Vsat +Vsat
Vi Vi
LTP UTP LTP UTP
(a) (b)
Figure 18.34| Transfer characteristics of window comparator.
18.15 PHASE SHIFTERS Figure 18.37 shows the circuit diagram of lead-type
phase shifter. The circuit shown here is just the redrawn
version of lagging-type phase shifter shown in Fig. 18.35
Figure 18.35 shows the circuit diagram of single opamp- with positions of RP and CP interchanged. The phase
based lagging-type phase shifter circuit. The output lags difference (q) is given by
the input by an angle (q) given by Eq. (18.24).
R q (in degrees) = 2tan1(wRPCP) (18.25)
R
For this circuit, when RP = 1/wCP; q = 90, when RP>>
Vo 1/wCP; q = 180 and when RP << 1/wCP; q = 0.
Rp
Vi + The cascade arrangement of two lead-type filter stages
can be used for varying phase shift over full 360.
Cp
Figure 18.35| Lagging-type phase shifter. R
q (in degrees) = 2tan1(wRPCP) (18.24)

R
where w = 2pf and f being the frequency of the input
signal. Vi CP Vo
+
A simple circuit can be used of shift the phase of the
input signal over a wide range by varying RP with 0
and 180 being the extremes. For RP << 1/wCP, the RP
phase shift is near zero (it is 0 when RP = 0, which is
not practical). For RP >> 1/wCP, q approaches 180
(q = 180 only for RP = infinity which is again not
feasible.) For RP = 1/wCP, q = 90. Two such sections
Figure 18.37| Lead-type phase shifter.
can be used in cascade to vary the phase shift over full
360. Figure 18.36 shows the circuit diagram.
R R R R

Vi RP RP Vo
+ +
CP CP
Figure 18.36| Two-stage lagging-type phase shifter.

18.16 INSTRUMENTATION equal. The result is that point A is floating. This fur-
AMPLIFIER ther implies that A1 and A2 act like voltage followers. In
other words, common-mode gain ACM of the preampli-
fier stage is unity. The tolerance specification of R1 and
Instrumentation amplifier is nothing but a differential R2 has no effect on the common-mode gain of the pre-
amplifier that has been optimized for DC performance to amplifier stage.
nearly approach the DC performance of an ideal opamp. On the other hand, when a differential signal is
As a result, instrumentation amplifier is characterized by applied to the input, the signals appearing at two R1-R2
a high differential gain, high CMRR, high input imped- and R3-R4 junctions are equal and opposite creating a
ance and low input offsets and low temperature drifts. virtual ground at point A. The differential gain of this
Figure 18.38 shows the classical internal schematic stage is therefore (1 + R2)/R1.
arrangement of an instrumentation amplifier. The two The difference amplifier stage has a common-mode
input opamps are wired as non-inverting amplifiers to gain equal to (2R/R), where R represents how
provide gain and very high input impedance and the closely the resistors are matched. Differential gain of
output opamp is wired as difference amplifier with unity this stage is unity. If we combine the results, we can
gain. The resistors used in the output stage are ultra- say that the overall common-mode gain is equal to the
high precision, low temperature drift resistors. common-mode gain of the difference amplifier stage and
We shall analyze the circuit shown in Fig. 18.38 for the overall differential gain is equal to the differential
common-mode and differential-input performance. The gain of the pre-amplifier stage. That is, the differential
circuit can be divided into two distinct parts, namely, gain is given by
the pre-amplifier comprising opamps A1 and A2 and the R
Av = 1 + 2 (18.26)
difference amplifier configured around A3. Let us assume R1
that the common-mode input is Vin(CM). Owing to
same positive voltage applied to both the non-inverting Since point A is a virtual ground and not a mechanical
inputs, the voltages appearing at the output of opamps ground, we can use a single resistor instead of two sepa-
A1 and A2 and also at R1-R2 and R3-R4 junctions are rate resistors. If this single resistor were RG, then
Vin(CM) + R R
+ A1

R2
R1

A A3 Vo
Vi
+
R3 = R1
R4 = R2

A2

Vin(CM) + R R
Figure 18.38| Instrumentation amplifier.

18.18 RELAXATION OSCILLATOR 417
RG 18.18 RELAXATION OSCILLATOR

R1 = R3 =
2
Therefore, Relaxation oscillator is an oscillator circuit that produces

a non-sinusoidal output whose time period is dependent on
2R2 the charging time of the capacitor connected as a part of the
Av = 1 + (18.27)
RG oscillator circuit. Opamps adapt very well to construction

The overall common-mode gain is given by of relaxation oscillator circuits that produce a rectangular
output. Figure 18.40 shows the basic circuit arrangement
2DR of an opamp-based relaxation oscillator circuit.
ACM = (18.28)
R
In the integrated circuit instrumentation opamps, all the R
components except RG are integrated on the chip. Here,
RG is connected externally and is used to control the
voltage gain. Vo
C +
R2
18.17 NON-LINEAR AMPLIFIER
In the case of a non-linear amplifier, the gain value is a

non-linear function of the amplitude of the signal applied R1
at the input. For example, the gain may be very large
for weak input signals and very small for large input
Figure 18.40| Relaxation oscillator.
signals, which implies that for a very large change in
the amplitude of input signal, resultant change in ampli-
tude of output signal is very small. A simple method to The circuit functions as follows. Let us assume that the
achieve non-linear amplification is by connecting a non- output is initially in positive saturation. As a result,
linear device such as a PN junction diode in the feedback voltage at non-inverting input of opamp is
path (Fig. 18.39). The amplifier thus becomes a semi-log R1
amplifier as the forward current through silicon diodes +Vsat
R1 + R2
varies as log of applied voltage.
With zero voltage, the diodes act as open circuit and This forces the output to stay in positive saturation
the gain is high due to minimum feedback. When the as the capacitor C is initially in fully discharged state.
amplitude of input signal is large, diodes offer very small Capacitor C starts charging towards +Vsat through R.
resistance and thus gain is low. Such a circuit may typi- The moment the capacitor voltage exceeds the voltage
cally cause output voltage to change in the ratio of 2:1 appearing at the non-inverting input, the output switches
for an input change of 1000:1. Resistance R1 decides the to Vsat. The voltage appearing at non-inverting input
compression ratio. Higher the value of resistor R1, lesser also changes to
is the compression ratio. A common application of such R1
a non-linear amplifier is in AC bridge balance detectors. Vsat
R1 + R2
The capacitor starts discharging and after reaching zero,
it begins to charge towards Vsat. Again, as soon as
D1 it becomes more negative than the negative threshold
appearing at non-inverting input of the opamp, the
D2 output switches back to +Vsat. The cycle repeats there-
Vi after. The output is a rectangular wave.
C1 R1 Vo The expression for time period of output waveform
+ can be derived from the exponential charging and dis-
charging process and is given by
1+ B
T = 2RC ln
Figure 18.39| Non-linear amplifier.
(18.29)
1 B

where Opamp wired as transimpedance amplifier very closely

R1 approaches a perfect current-to-voltage converter.
B= Figure 18.43 shows the circuit arrangement. The circuit
R1 + R2 is characterized by voltage-shunt feedback. The expres-
Figure 18.41 shows the relevant waveforms. The time sions for output voltage, closed-loop input and output
period of output may be conveniently varied by varying impedances are given as follows:
the resistance value of R. AOL
Vo = Ii R (18.30)
+Vsat B 1 + AOL
For AOL >> 1, Eq. (18.30) simplifies to
0
t
Vsat B Vo = Ii R (18.31)

+Vsat R
Zin = (18.32)
1 + AOL

t Ro
Zo = (18.33)
Vsat 1 + AOL

T where Ro is the output impedance of the opamp.
Figure 18.41| Relevant waveforms of relaxation R
oscillator.
Ii
Relaxation oscillator forms the basis of waveform-
generation circuits configured around opamps. For
example, a triangular waveform generator may be built
by cascading the relaxation oscillator block with an inte- Vo
Ii +
grator block as shown in Fig. 18.42.
R5
R1
Figure 18.43| Current-to-voltage converter.
C2

+ R4 18.20 VOLTAGE-TO-CURRENT
+ Vo CONVERTER
C1
R3 The voltage-to-current converter is a case of a transcon-
R2 ductance amplifier. An ideal transconductance amplifier
makes a perfect voltage-controlled current source or a
voltage-to-current converter. Opamp wired as trans-
conductance amplifier very closely approaches a perfect
voltage-to-current converter. Figure 18.44 shows the
basic circuit arrangement. The circuit is characterized
Figure 18.42| Triangular waveform generator. by current-series feedback. Expressions for output volt-
age, closed-loop input and output impedances are given
as follows.
18.19 CURRENT-TO-VOLTAGE Vi
CONVERTER Io = (18.34)
R1 + [(R1 + R2 )/AOL ]

For AOL >> 1, Eq. (18.34) simplifies to the following
Current-to-voltage converter is nothing but a tran- equation:
simpedance amplifier. An ideal transimpedance ampli-
V
fier makes a perfect current-to-voltage converter as it Io = i (18.35)
has zero input impedance and zero output impedance. R1


18.21 ACTIVE FILTERS 419
R C
+ Vi + Vi

Vo
Vi C R
Io R2
(a)
R1
R C
Vi Vi +
Figure 18.44| Voltage-to-current converter.
+
Vo Vo

Closed-loop input impedance isCgiven by R
R1
Zin = Ri 1 + AOL (18.36)
R1 + R2
where Ri is the input impedance of the opamp.(a) Closed- (b)
loop output impedance is given by Figure 18.45| First-order active filters: (a) low pass;
R1 (b) high pass.
Zo = R1 1 + AOL
(18.37)
R1 + R2 6n dB per octave or 20n dB per decade. Operation of the
Voltage-to-current converter shown in Fig. 18.44 oper- high-pass circuit can also be explained on similar lines.
ates with a floating load, which is not always convenient. The filters shown in Fig. 18.45 can also be config-
Monolithic opamps specially designed as transconduc- ured so as to have the desired amplification of the input
tance amplifiers to feed single-ended load resistances are signal. Low-pass and high-pass filter circuits with gain
commercially available. are shown in Figs. 18.46(a) and (b), respectively. The
voltage gain Av is given by Eq. (18.39).
1
fc = (18.38)
18.21 ACTIVE FILTERS 2pRC
R3
Av = 1 + (18.39)
In this section, we will briefly describe opamp circuits R2

used to build low-pass, high-pass, band-pass and band-
The single-order filters shown in Figs. 18.45 and 18.46
reject active filters. We will confine our discussion to
employ non-inverting type of amplifier configuration.
the first- and second-order filters. The order of an active
These filters could also be implemented using inverting
filter is determined by number of RC sections (or poles)
amplifier configuration. The relevant circuits are shown
used in the filter, which for a few exceptions equals the
in Fig. 18.47. The cut-off frequency and mid-band gain
number of capacitors.
values in the case of low-pass filter are, respectively,
given by Eqs. (18.40) and (18.41).
18.21.1 First-Order Filters
1
fc = (18.40)
The simplest low-pass and high-pass active filters are con- 2pR2C1

structed by connecting lag and lead type of R-C sections, R2
respectively, to the non-inverting input of the opamp Av = (18.41)
R1
wired as a voltage follower. Figures 18.45(a) and (b),
respectively, show such first-order low-pass and high-pass The same in the case of high-pass filter are given by Eqs.
filter circuits. The cut-off frequency in both cases is given (18.42) and (18.43).
by Eq. (18.38). The gain rolls off at a rate of 6 dB per
octave or 20 dB per decade beyond the cut-off point. The 1
fc = (18.42)
output is 0.707 times the input when the signal frequency 2pR1C1

is such as to make capacitive reactance equal to the resis- R2
tance value. This is called the cut-off frequency. Roll-off Av = (18.43)
rate beyond the cut-off point in the case of n-order filter is R1


R1 C1
Vi + Vi +
Vo Vo
C1
R1
R3 R3
R2 R2
(a) (b)
Figure 18.46| First-order filters with gain: (a) low pass; (b) high pass.
C1
R2
R1 R2 C1 R1
Vi Vi
Vo Vo
+ +
(a) (b)
Figure 18.47| First-order filters using inverting configuration: (a) low pass; (b) high pass.
18.21.2 Second-Order Filters R1 R2
Figure 18.48 shows the generalized form of a second-

order Butterworth active filter. Butterworth filter, also
called maximally flat filter, offers a relatively flat pass Z1 Z2 Vo
and stop band response but has the disadvantage of rela- +
Vi
tively sluggish roll-off. Other commonly used filters are
the Chebychev and Cauer filters. Chebychev filters offer
Z3 Z4
much faster roll-off but their pass band has ripple. Cauer
filters have rippled pass and stop bands. There are other
types of filters such as Bessel filters with their unique
properties. Discussion on all these types is beyond the Figure 18.48| Generalized form of second-order
scope of this chapter. Butterworth filter.
In the case of generalized form of second-order
Butterworth filter as shown in Fig. 18.48, we have the
following: The value of pass band gain (Av) can be determined
from
1. If Z1 = Z2 = R and Z3 = Z4 = C, we get a second-
order low-pass filter. R1
Av = 1 + (18.45)
2. If Z1 = Z2 = C and Z3 = Z4 = R, we get a second- R1

order high-pass filter.
The cut-off frequency is given by Band-pass filters can be formed by cascading the high-pass
and the low-pass filter sections in series. These filters are
1 simple to design and offer large bandwidth. To construct
fc = (18.44)
2pRC a narrow band-pass filter, one needs to employ multiple

C1 behavior of the circuit is as follows. Very low frequency

signals find their way to the output via the low-pass filter
formed by R1-R2-C3. Very high frequency signals reach
the output through the high-pass filter constituted by
R2 C1-C2-R3. In an intermediate band of frequencies, both
R1 C2
filters pass the signal to some extent but the negative
Vi phase shift introduced by low-pass filter is cancelled out
Vo by an identical positive phase shift by high-pass filter
+
R3 with the result that at any instant, the net signal reach-
ing the non-inverting input and hence the output is zero.
R4 The component values of the twin-T network are chosen
according to the following equations:
R4
Figure 18.49| Narrow band-pass filter.
feedback as shown in Fig. 18.49. At very low frequencies,

C1 and C2 offer very high reactance. As a result, the input C1 C2 Vo
signal is prevented from reaching the output. At very high +
frequencies, the output is shorted to the inverting input,
R3
which converts the circuit to an inverting amplifier with
zero gain. Again, there is no output. Thus at both very R1 R2
low and very high frequencies, the output is zero. At some Vi
intermediate band of frequencies, the gain provided by C3
the circuit offsets the loss due to the potential divider
R1-R3. Mathematical expressions governing the design of
Figure 18.50| Second-order band reject filter.
the filter circuit are given in Eqs. (18.46) to (18.48):
2Q
Resonant frequency, fR = (18.46) R
2pR2C R1 = R2 = R, R3 = (18.49)
2
where Q is the quality factor. For C1 = C2 = C, the qual-
ity factor is given by C1 = C2 = C , C3 = 2C (18.50)

R R
1/ 2
Q= 1 2 (18.47) 0 R4 (R1 + R2 ) (18.51)

2R3
1
The voltage gain is fR = (18.52)
2pRC
Q
Av = (18.48)
2pR1fR C 18.21.3 Sine Wave Oscillators

Figure 18.50 shows the circuit diagram of second-order
band reject filter. It uses a twin-T network that is con- Opamps adapt well to use in building sine wave oscilla-
nected in series with the non-inverting input of the tors, for example, in building RC oscillators (such as RC
opamp. A twin-T network offers very high reactance at phase-shift oscillator and Wien bridge oscillator) and LC
the resonance frequency and very low reactance at fre- oscillators (such as Hartley oscillator and Colpitt and
quencies off-resonance. This phenomenon explains the Clapp oscillators). The opamp-based sine wave oscilla-
behavior of the circuit. Another way of explaining the tors are discussed in detail in Chapter 20.
IMPORTANT FORMULAS
1. The actual voltage gain of an opamp-based invert- AOL R2 R2

ACL =
ing amplifier is R1 + R2 + AOL R1 1
R + ( R2 AOL )

2. The ideal voltage gain of a non-inverting amplifier is 6. For an integrator circuit,
RC i
V dt = K Vi dt
R2 1
ACL = 1 + Vo =
R1
3. The actual gain expression in the case of a non- 7. For a differentiator circuit,
inverting amplifier is
dVi dV
AOL (R1 + R2 ) Vo = RC =K i
ACL = dt dt
R1 + R2 + AOL R1
8. The cut-off frequency of low-pass and high-pass fil-
4. The ideal voltage gain of an opamp-based inverting ters is given by
amplifier is
1
R fC =
ACL = 2 2pRC
R1 9. Resonant frequency of bandpass filter,
5. For an averager circuit,
2Q
V + V2 + V3 + + V n
fR =
Vo = 1 2pR2C

n
SOLVED EXAMPLES
1. The following figure shows an inverting amplifier Slew rate

fmax =
2pVo(max)
using an opamp. Given that R1 = 10 kW and R2 =
100 kW and the slew rate of the opamp is 0.5 V/ms.
For an input signal with peak amplitude varying
Solving this equation, we get
from 100 to 300 mV, what is the maximum possi-
fmax = 26.5 kHz
ble input signal frequency that would be faithfully
Ans. (a)
amplified?
2. For the amplifier circuit shown in the following
R2 figure, the output Vo is
R1 R

R
V4
Vo 2R Vo
+ V3
Vi +
V2
4R
V1
8R
(a) 26.5 kHz (b) 500 kHz V V V

(a) Vo = V4 + 3 + 2 + 1
8
(c) 1 MHz (d) 10 kHz 2 4
V V V
Solution. The largest input signal amplitude is (b) Vo = V4 + 3 + 2 + 1
300 mV. The corresponding output signal is 2 4 8
100 103 V V V
300 10 3 (c) Vo = V4 + 3 + 2 + 1
10 103
= 3000 mV = 3 V
8 4 2
The highest sine wave frequency that would be V V V

(d) Vo = V4 + 3 + 2 + 1
faithfully amplified is given by 16 8 4

SOLVED EXAMPLES 423
Solution. Let us assume that Vo1, Vo2, Vo3 and That is,
Vo4 are the outputs, respectively, for only V1, V2, 1 + 0.825
T = 2 10 103 0.01 106 ln
V3 and V4 present one at a time with other inputs 1 0.825
grounded, Then,
= 0.469 ms
R
Vo 4 = V4 = V4 Therefore,
R
R V 1
= V3 = 3 f = -3
Hz = 2.13 kHz
0.469 10
V o3
2R 2
R V2
V o2 = V2 = The peak-to-peak amplitude of output is
4R 4
R V1 2Vsat = 25 V
Vo1 = V1 = Ans. (d)
8R 8
4. For the opamp-based amplifier shown in the fol-
With all inputs present simultaneously, lowing figure, what is the value of voltage gain and
V V V the input impedance? Given that open loop gain
Vo = V4 + 3 + 2 + 1 and the input impedance of the opamp are 80 dB
2 4 8
and 1 MW, respectively.
Ans. (b)
3. Refer to the relaxation oscillator circuit shown R2
in the following figure. What is the peak-to-peak 100 k
amplitude and frequency of the square wave output
given that saturation output voltage of the opamp
is 12.5 V at power supply voltages of 15 V. R1
1 k +V

10 k
Vo
Vi +
Vo
0.01 F + V
(a) 99, 100 MW (b) 99.99, 100 MW

10 k (c) 99, 90 MW (d) 99.99, 102 MW
47 k
Solution. The open loop gain is
(a) Peak-to-peak amplitude = 25 V and frequency A = 80 dB = 10,000

= 2.03 kHz The feedback factor is
(b) Peak-to-peak amplitude = 30 V and frequency
R1 1 103
b =
= 2.03 kHz 1
= =
R1 + R2 (1 10 ) + (100 10 ) 101
(c) Peak-to-peak amplitude = 30 V and frequency 3 3
= 2.13 kHz
(d) Peak-to-peak amplitude = 25 V and frequency Therefore, the desensitivity factor is
= 2.13 kHz
10000
D = 1 + bA = 1 + = 100.0099
Solution. The feedback factor b is given by 101
47 103
= 0.825 The gain with feedback is
47 103 + 10 103
10, 000
The time period T of the output waveform is = 99.99
givenby 100.0099
1+ b The input impedance of the opamp is 1 MW.
T = 2RC ln
1 b Since, the circuit uses series feedback, the input

impedance would increase by the desensitivity Therefore,

factor. Therefore, input impedance with feedback is 500 103 -3
Vo (off ) = 1 + 0.5 10 1.25 V
1 10 100.0099 = 100 MW
6
200
Ans. (b)
Ans. (b)
5. For the circuit shown in the following figure, IF is
7. In the following figure, assume the opamps to be
given by
ideal. The output Vo of the circuit is
RF
10 F
IF 10 mH
R1 10
Vs 100
Vo
Vs = 10 cos(100t) +
Vo
+ +
Vi
t
(a) Vi
RF

V
(b) i (a) 10 cos (100t) (b) 10 cos (100t ) dt
R1(RF + R1 ) R1 0
1 1
t
(c) 104 cos (100t ) dt (d) 104
Vi d
(c) (d) Vi + cos (100t)
R1 RF
RF 0
dt

Solution. Let the output voltage of the first

Solution. The current IF is the same as the cur- opamp be V2. Applying KCL at the inverting node
rent through resistance R1, as the input impedance of the first opamp, we get
of the opamp is infinite. The voltage at inverting 0 Vs 0 V2 V2
terminal of the opamp is Vi. Therefore, the current = =
IF is given by 10 wL 100 10 103
V Therefore,
IF = i
R1 Vs
Ans. (b) V2 = = cos (100t)
10
6. Refer to the circuit shown in the following figure. Applying KCL at the inverting node of the second
The opamp is ideal except that the input offset opamp, we get
voltage of the opamp is 0.5 mV. What is the output
voltage of the circuit shown? 0 V2 0 Vo Vo Vo
= =
=
100 1/w C 1 / [100 (10 10 )] 1000
6
Therefore,
500 k
200
Vo = 10V2 = 10cos(100t)
Ans. (a)
Vo 8. In the circuit shown in the following figure, Vo is

+
+15V
(a) 1 V (b) 1.25 V
(c) 0.625 V (d) 2.5 V
+1V Vo
+
Solution. The output voltage Vo(off) due to input
R
offset voltage Vi(off) is given by
15V
R
Vo (off ) = 1 + F Vi (off )
R1 R

SOLVED EXAMPLES 425
(a) 1 V (b) 2 V Solution. The output is in positive saturation.

(c) +1 V (d) +15 V Therefore,
Vo = +15 V
Ans. (d)
1. The following figure shows an opamp-based circuit. Vo A

=
Find the value of output voltage (in volts) when Vs 1 + [(R1 /R2 ) (1 + A)]
the switch S is open.
where A is the open loop gain of the opamp.
R1 R2
Vi Therefore,
Vo 100 100
1V 5 k 50 k = = =
Vs 1 + [(1 10 / 10 10 )(1 + 100)]
3 3 1 + (101 / 10)
Vo 100 100
= = = 9
Vs 1 + [(1 10 o/ 10 10 )(1 + 100)]
V3 3 1 + (101 / 10)
10 k 10 k
+ Ans. (-9)
R3 R4 4. An opamp has a gain-bandwidth product of
S 1 MHz. A non-inverting amplifier using this opamp
and having a voltage gain of 20 dB will exhibit a
3-dB bandwidth (in kHz) of .
Solution. When the switch is open,
R R
Solution.
Vo = Vi 1 + 2 + Vi - 2 = Vi = 1 V
Gain Bandwidth = 1 106
R1 R1
Ans. (1) Gain = 20 dB = 10
2. For the opamp-based circuit depicted in the figure Therefore, the bandwidth is
shown in Question 1, find the value of output volt- 1 106
age (in volts) when the switch S is closed. Hz = 100 kHz
10
Solution. When the switch is closed, the voltage Ans. (100)
at non-inverting input is 0 V. Therefore,
5. An amplifier using an opamp with a slew-rate
R
Vo = Vi 2 = 10 V
SR= 1 V/ms has a gain of 40 dB. If this ampli-
R1 fier has to faithfully amplify sinusoidal signals from
Ans. (-10) DC to 20 kHz without introducing any slew-rate
induced distortion, then the input signal must not
3. The inverting opamp shown in the following figure has exceed mV.
an open-loop gain of 100. The closed-loop gain Vo/Vs is
Solution. Let the input signal be given by
10 k
Vi = AVm sin 2pft
R2
Now,
A = 40 dB = 100
1 k
Slew rate
+
Vs R1 Vi SR = AVm2pfm
+ Vo
Therefore,
1
Vm = -6
= 79.5 mV
10 100 2 p 20 103
Solution. The expression for closed loop gain is
given by Ans. (79.5)

PRACTICE EXERCISE
1. The following figure shows transfer characteristics (c) Four-bit D/A converter
of some opamp circuit. It could possibly be (d) Multiple input inverting amplifier
(1 Mark)
Vo
4. Refer to the clamping circuit shown in the following
+Vsat figure. What is the peak value of the clamped wave-
form at the output? Assume the diode to be ideal.
Vo
0 C1
D1
Vsat Vi
10 sin314t +
RL Vo
(a) an inverting comparator
(b) a non-inverting comparator 1k
(c) an inverting amplifier with hysteresis
(d) a non-inverting amplifier with hysteresis
(1 Mark) (a) 20 V (b) 20 V
(c) 10 V (d) 10 V
2. Refer to the transfer characteristics shown in the (1 Mark)
following figure. Identify the circuit.
5. In a non-inverting amplifier, when the feedback
Vo resistance equals the resistance connected from
inverting input to ground, the closed-loop gain is
+Vsat
(a) 1 (b) 2
(c) infinity (d) less than 1
Vi (1 Mark)
6. In an opamp circuit, N DC inputs are connected
Vsat to the inverting input through individual resis-
tances, which are of the same value. The feedback
resistance connected from output to inverting input
(a) Inverting comparator is of resistance value that is (1/N)th of the input
(b) Non-inverting comparator resistance value. Non-inverting input is grounded.
(c) Inverting zero-crossing detector The output in this case is
(d) Non-inverting zero-crossing detector
(a) indeterminate from given data
(1 Mark)
(b) average of all inputs
3. Refer to the opamp circuit shown in the following (c) sum of all inputs
figure. The circuit performs the function of which (d) none of these
important building block? (1 Mark)
7. In an inverting summer circuit using opamp, DC
R R voltages of +1 V, 2 V and +2 V are, respec-
D tively, applied to the input through 10 kW, 20 kW
2R Vo and 50kW resistors. If the feedback resistance were
C +
50kW, the output voltage would then be
(b) 2 V
B
4R (a) +2 V
A (c) 3 V (d) +3 V
8R (1 Mark)
(a) Four-input inverting summer 8. The following figure shows opamp-based inte-
(b) Four-input inverting averager grator circuit. If this circuit were to integrate a

symmetrical pulse waveform of 200 ms time period (c) current-controlled voltage source
and if the DC gain of the integrator were to be lim- (d) voltage-controlled current source
ited to 100, what would be the values of C1 and R2? (1 Mark)
12. The following figure shows a non-inverting ampli-
fier using an opamp. What is the value of the cur-
C1
rent flowing through the feedback resistor?
10 k R2
Vi
R1 RF
Vo
+ R1

Vo
Vi +
(a) 0.1 mF, 1 MW (b) 0.01 mF, 1 MW

Vi Vo
(a) (b)
(c) 0.1 mF, 100 kW (d) 0.01 mF, 100 kW R1 RF
(2 Marks) Vi Vo
(c) (d)
9. Refer to the opamp-based inverting amplifier cir- RF R1
cuit shown in the following figure. Which type of (1 Mark)
negative feedback is employed and what is the tran-
13. An opamp having a slew-rate specification of
simpedance gain? Given that transimpedance, input
1 V/ms has been connected in the voltage follower
impedance and output impedance parameters of the
opamp are 100 MW, 10 MW and 100 W respectively.
configuration. The input is a unit step of voltage
applied at instant t = 0. What is the output mag-
100 M nitude at t = 500 ns?
(a) 1 V (b) 0.5 V
(c) 0 V (d) Positive supply voltage
100 k +V (2 Marks)
Vi
14. JFET input opamps differ from BJT input opamps
Vo in the sense that
+
V (a) T
hey have much higher input impedance and
much lower input bias currents
(b) They have extremely high CMRR and slew rate
ratings
(c) They are capable of single supply operation
(a) Voltage shunt, 50 MW (d) They have extremely low input noise
(b) Voltage shunt, 900 MW (e) They have extremely low offset voltages
(c) Current series, 990 kW (1 Mark)
(d) Current series, 900 kW
(2 Marks) 15. The opamp circuit shown in the following figure
has the highest CMRR when
10. It is required to design opamp-based circuit that
generates an output Vo=sint cost from the Rs1 R1 R2
available inputs V1 = sint and V2 = cost. Which Vin1
building blocks can be used for designing the same?
(a) Integrator configuration
(b) Differentiator configuration
(c) Both integrator and differentiator configurations Rs2 R3 Vo
(d) None of the above Vin2 +
(1 Mark)
11. An operational amplifier is an example of R4
(a) current-controlled current source
(b) voltage-controlled voltage source

Rs1 R Rs1 + R1 R + R3 (a) Vo = V3 + V4 V2 V1

(a) = 1 (b) = s2
Rs2 R3 R2 R4 (b) Vo = V3 + V4 V2 V1
(c) Vo = V3 V4 + V2 + V1
(c)
R1 R
= 3 (d)
Rs1 + R1 R + R3
= s2 (d) Vo = V3 V4 V2 V1
R2 R4 R2 R2 + R3 (2 Marks)
(2 Marks) 19. Refer to the half-wave circuit shown in the fol-
lowing figure and the associated rectified output
16. For current-to-voltage converter circuit shown
waveform. What is the value of V1 and V2 given
in the following figure, choose the correct
that opamp has an open-loop gain of 100 dB and
answer. Given that the opamp has open-loop
diode D1 has a cut-in voltage of 0.7 V?
trans-impedance gain of 100,000, input impedance
of 100 kW and output impedance of 100 W. (a) V1 = 10 V, V2 = 7 mV
(b) V1 = 100 V, V2 = 70 mV
(c) V1 = 1 V, V2 = 70 mV
(d) V1 = 1 V, V2 = 7 mV
100 k

Vo
A + + D1
Vo

Vi 1N4007
S1: Output voltage = 1 V. 1k RL

S2: Closed-loop input impedance, Zin = 1 W and 10 sin314 t
closed-loop output impedance, Zo = 0.001 W.
(a) S1 is the correct statement
(b) S2 is the correct statement
(c) Both S1 and S2 are correct statements
(d) None of these
(1 Mark)
V1
17. Which of the following statements are true?
S1: The large signal bandwidth of an opamp is lim- V2
t
ited by its slew rate specifications
S2: The large signal bandwidth of an opamp is lim-
ited by its gain bandwidth product
(2 Marks)
S3: If the decoupling capacitors are not connected
at the supply pins of the opamp, its gain is affected 20. The following figure shows a low pass filter circuit.
S4: If the decoupling capacitors are not connected What are the cut-off frequency and the gain value
at the supply pins of the opamp, PSRR specifica- at four times the cut-off frequency?
tion of the opamp is affected
(a) 15.7 kHz, 8.8 dB (b) 15.9 kHz, 8.8 dB
(a) S1 and S3 are true (b) S1 and S4 are true (c) 15.1 kHz, 8.8 dB (d) 15.9 kHz, 8.9 dB
(c) S2 and S3 are true (d) S2 and S4 are true
(1 Mark)
10 k
18. What is the output voltage Vo for the amplifier +
Vi
circuit shown in the following figure?
Vo
V1 1000 pF
R R
V2
R Vo
V3 +
R 100 k
V4 10 k
R
R
(2 Marks)

21. Refer to the circuit and input waveform shown in the following figures.
+5 V
20
100 k 100 k
15 k 100 k
+5 V
100 k
Vi A1 A3 Q1
100 k + A2 +
10 k + I
Vi
+1 V
50 t (ms)
0 25 75 100 125 150
1V
The waveform of current (I) across the laser diode is
I(mA) I(mA)
200 150
150 100
(a) (b)
100 50
0 0
25 50 75 100 125 t(ms) 25 50 75 100 125 t(ms)
I(mA) I(mA)
200 150
150 100
(c) (d)
100 50
0 0
25 50 75 100 125 t(ms) 25 50 75 100 125 t(ms)
(2 Marks)

22. Refer to the instrumentation amplifier circuit 25. Refer to the voltage-follower circuit shown in the
shown in the following figure. Resistors R1 and following figure. Given that the opamp used has a
R2, respectively, have tolerance specifications of unity gain cross-over frequency of 1 MHz and the
0.001% and 0.05%. Determine the CMRR of this voltage observed across the load of 10 W is 99.5 mV.
instrumentation amplifier (in dB). R
+ + Vo
+ R2 R2

100 k 100 k
Vin 100 mV
R1 ptp RL
10
100 k
Vi RG
100 k + Vo
1 k
What is the no-load output voltage?
R1
R2 R2 (a) 100 mV (b) 100 mV
(c) 77 mV (d) 77 mV
+
100 k 100 k (1 Mark)
(a) 100 dB (b) 101 dB bandwidth?
(c) 106 dB (d) 109 dB (a) 1 MHz (b) 10 MHz
(2 Marks) (c) 100 kHz (d) 10 kHz
23. Refer to the amplifier circuit shown in the follow- (1 Mark)
ing figure. What is the voltage gain of the amplifier 27. For the case discussed in Question 25, what is the
when the variable terminal of the potentiometer is closed-loop output impedance?
at point A?
(a) 10 W (b) 1 W
(c) 0.05 W (d) 0.5 W
R nR (1 Mark)
28. For the comparator circuit shown in the following
figure, diodes D1 and D2 have forward-biased volt-
age drop equal to 0.7 V each. What is the state of
+ Vo LED-1 and LED-2 (whether ON or OFF) when the
nR/n1 switch SW-1 is in position A?
Vin
A
+V R1
+
V SW1 D2 Vo
B D1
B A LED1 LED2
Potentiometer
(a) n (b) (n + 1)
(a) LED-1 ON, LED-2 OFF
(c) n (d) (n + 1)
(b) LED-1 ON, LED-2 ON
(1 Mark)
(c) LED-1 OFF, LED-2 ON
24. Refer to the amplifier circuit in Question 23. (d) LED-1 OFF, LED-2 OFF
What is the voltage gain of the amplifier when (2 Marks)
the variable terminal of the potentiometer is at
29. For the comparator circuit depicted in Question28,
point B?
diodes D1 and D2 have forward-biased voltage drop
(a) n (b) (n + 1) equal to 0.7 V each. What is the state of LED-1
(c) n (d) (n + 1) and LED-2 (whether ON or OFF) when the switch
(2 Marks) SW-1 is in position-B?

(a) LED-1 ON, LED-2 OFF Vo Vo

(b) LED-1 ON, LED-2 ON +15 V +15V
(c) LED-1 OFF, LED-2 ON
(d) LED-1 OFF, LED-2 OFF
(2 Marks)
30. The following Figures (a), (b) and (c) give three Vi
5 V 0 0
different opamp configurations. Three different +5 V +5 V
transfer characteristics are given in Figures (i), (ii)
and (iii).
15 V 15 V
+15 V
(i)
5V 10 k
+
Vo +15 V Vo Vo
5 k
+15 V +15V
15 V +
Vo +15 V
Vi Vo

+15 V +
15 V
Vi Vi Vi
5 V 5 V
0 0
V
+5 +5 V
2V +
15 V
(a) 15 V (b) 15 V 0 2V 5
10 k
+15 V (ii)
+15 V 10 k +15 V
5 k
+ 5V + V10 k
Vo o +15V Vo
+15 V +15 V Vo
+ 5 k +
15 V +15 V
Vo Vi + 5 k +15 V
15 V Vo + 15 V
V
o
+15 V Vi Vo

+
+15 V Vi 15 V Vi
+
5 V 0 Vi+5 V +5 V 0
15 V 5 V

+ Vi
(c)
15 V2 V + Vi
(a) 15 V 15 V (b)
15 V 0 2V 5V
(a)k
10 (b)
(iii)
10 k
+15 V Match the opamp configuration with the transfer
5 k characteristics.
+ +15 V
5 k
Vo + (a) F igure (a) Fig. (iii); Fig. (b) Fig. (ii);
+
Vo Fig.(c) Fig. (iii)
Vi + (b) Figure (a) Fig. (i); Fig. (b) Fig. (ii);
15 V
Vi Fig.(c) Fig. (iii)
15 V
(c) Figure (a) Fig. (ii); Fig. (b) Fig. (iii);
Fig.(c) Fig. (i)
(d) Figure (a) Fig. (iii); Fig. (b) Fig. (i),
(c) Fig.(c) Fig. (ii)
(c) (2 Marks)

31. Figures (a), (b) and (c) shown in Question 30 give 33. Given an opamp with output saturation voltages
three different opamp configurations. Identify the of 10 V and slew rate of 10 V/ms. What is the
circuit configurations of these three figures: highest input frequency that would yield output
(a) Figure (a) Window comparator; Fig. (b)
waveform transition time of not more than 10% of
Non-inverting Schmitt trigger; Fig. (c)
half of the time period of input signal?
Inverting Schmitt trigger. (a) 1 kHz (b) 10 kHz
(b) Figure (a) Window comparator; Fig. (b) (c) 25 kHz (d) 50 kHz
Inverting Schmitt trigger; Fig. (c) Non- (2 Marks)
inverting Schmitt trigger.
(c) Figure (a) Non-inverting Schmitt trigger;
34. The following figure shows an opamp circuit. Given
Fig. (b) Window comparator; Fig. (c)
that the opamp is ideal and R2/R1 = 5.
Inverting Schmitt trigger. R1
(d) Figure (a) Inverting Schmitt trigger; Fig. R2
(b) Non-inverting Schmitt trigger; Fig. R2
R1

(c) Window comparator.
(1 Mark) Vs1 + Vo
Vs2 +
32. Given an opamp with output saturation voltages of
10 V and slew rate of 10 V/ms. Which of the cir- What is the mathematical operation performed by
cuits shown in the following figures is a non-inverting the amplifier circuit?
zero-crossing detector with a hysteresis of 100 mV?
(a) Adder (b) Multiplier
(c) Subtractor (d) Divider
R2 (1 Mark)
R1
35. For Vs1 = 5 V and Vs2 = 3 V, what is the output
Vi +
voltage Vo of the opamp circuit in Question 34?
Vo
(a) 12 V (b) 11 V
R2 /R1 = 199
(c) 15 V (d) 18 V
(1 Mark)
(a) 36. The following figure shows a non-inverting type of
window comparator configured around comparator
IC LM 339, which is a quad comparator. What is
the lower trip-point of the comparator?
R2
R1 +5 V
Vi +
+12 V
Vo
100 k
R2 /R1 = 99
+
1 k
(b) 33 k Vo
R2 +12 V
Vi +
R1 100 k
Vi
+ +12 V
Vo
R2 /R1 =59 15 k
(c )
(a) Fig. (a) (b) Fig. (b) (a) 1.565 V (b) 2.977 V
(c) Fig. (c) (d) None of these. (c) 3.05 V (d) 4.77 V
(2 Marks) (1 Mark)

37. What is the upper trip-point of the comparator

depicted in the figure shown in Question 36? 10 k
Vi +
(a) 1.565 V (b) 2.977 V 1000 pF Vo
(c) 3.05 V (d) 4.77 V
(1 Mark)
38. The transfer characteristics of the window com-
parator in Question 36 are given by 100k
10k
Vo
(a) First-order low pass filter
(b) First-order high pass filter
(c) Second-order low pass filter
(a) +5 V
(d) Second-order low pass filter
(1 Mark)
Vi 40. For the filter circuit shown in Question 39, deter-
1.565V 2.977 V mine the gain value at 128 kHz.
(a) 8 dB (b) 2.8 dB
Vo (c) 9.3 dB (d) 9.7 dB
(2 Marks)
41. The following figure shows an opamp-based cir-
cuit. Given that the open-loop gain of the opamp
(b) +12 V is 120dB.
+15 V

Vi
1.565V 2.977 V
Vo
+
10 A
Vo 15 V
100 k
(c) +5 V
What is the value of O/P voltage?
(a) 1 V (b) 1 V
Vi
1.565V 2.977 V (c) 0 V (d) +15 V
(1 Mark)
42. The figure in Question 41 shows an opamp-based
Vo circuit. Given that the open-loop gain of the opamp
is 120 dB. What is the input impedance seen by the
photodiode?
(d) +12 V (a) 100 kW (b) Infinite

(c) 0.1 W (d) 0 W
(1 Mark)
Vi 43. For the opamp based circuit depicted in Question 41.
1.565V 2.977 V What is the feedback amplifier configuration
employed?
(1 Mark)
(a) Voltage-shunt (b) voltage-series
39. The following figure shows a filter circuit. Identify (c) Positive feedback (d) No feedback
the filter circuit? (1 Mark)

44. Refer to the circuit shown in the following figure, (a) Transimpedance
Given that a light pulse having wavelength of 1000 (b) Transconductance
nm, pulse width of 1 s and energy of 10 mJ is incident (c) Voltage follower
on the active area of the photodiode. The respon- (d) Non-inverting amplifier
sivity of the photodiode is 0.5A/W at 1000 nm. In (1 Mark)
which configuration, the opamp is being used?
amplitude of the voltage pulse across resistor R?
R2
10 k (a) 250 MV (b) 500 MV
+12 V (c) 250 MV (d) 500 MV
(1 Mark)
R1 +V
1 k 46. For the case discussed in Question 44, what is the
amplitude of the voltage pulse at the output of the
Vo opamp?
+ (a) +2 V (b) +2.5 V
(c) +2.75 V (d) +3 V
R V (1 Mark)
50
1. An operational amplifier has a slew rate specifica- 3. Refer to the laser diode drive circuit shown in the
tion of 50 V/ms. An input signal having a frequency following figure. The laser diode is operated in the
of 10 MHz is applied at its input terminal. What is pulsed output mode with the two values of drive
the peak value of the output signal in volts given current corresponding to the two voltage levels of
that the supply voltages of the opamp are +15 V the pulsed signal applied at the input. What is the
and 15 V? laser diode current in mA corresponding to low
value of control signal?
(1 Mark)
2. The following figure shows an opamp-based con-
+5V
stant current source. What is the value of resistor
R (in ohms), so that a current of 10 mA flows 5 k
through the laser diode?
15V
R 100 pF
100 k

15V
1V +
100 k

+1 V 100 k 5 V 0.1
0
2.5 V + 5 k
Laser
15 V diode
(1 Mark) (2 Marks)

4. Refer to the laser diode drive circuit shown in gain of the circuit when the voltage applied to the
Question 3. The laser diode is operated in the gate of JFET is 0 V?
pulsed output mode with the two values of drive
(1 Mark)
current corresponding to the two voltage levels of
the pulsed signal applied at the input. What is the 6. Refer to the inverting amplifier circuit shown in
laser diode current in mA corresponding to high Question 5. Given that JFET has RDS = 500 W
value of control signal? and VGS(off) = 5 V. What is the voltage gain of
the circuit when the voltage applied to the gate of
(2 Marks)
junction FET is 5 V?
5. Refer to the inverting amplifier circuit shown in
(1 Mark)
the following figure. Given that JFET has RDS =
500 W and VGS(off) = 5 V. What is the voltage
Vin
R R
100 k 100 k

100 k Vo
+
R
VGS
1. (b)
The transimpedance with feedback is
RM 108
= 50 MW
2. (c)
RMf = =
3. (c) 1 + bRM 1 + (108 108 )
4. (a) 10. (c)
5. (b) 11. (b)

12. (a) The output voltage is
6. (b)
R
7. (b) Vo = 1 + F Vi
R1
8. (a)
The current flowing through the feedback resistor
9. (a) The feedback is of voltage shunt type. The RF is given by
transimpedance is
Vo Vi V
RM = 100 MW = 108 W = i
RF R1
The feedback factor is 13. (b)
1 14. (a)
b = 8 1 = 108 1
10 15. (b)

16. (c) The output voltage is The gain at frequency four times the cut-off fre-
6
10 10 100 10 = 1 V
3 quency will be 12 dB below the value of mid-band
gain. Therefore, the gain in dB at four times the
The closed-loop input impedance is cut-off frequency is
100 103 20.8 12 = 8.8 dB
= 1W
R
Zin = =
1 + AOL 1 + 100, 000
The closed-loop output impedance is 21. (a) The circuit is a laser diode driver circuit. The
laser diode current is
Ro
= 0.001 W
100
5 VE
Zout = =
1 + AOL 1 + 100, 000
A
17. (b) 20 103
where VE is the voltage at Q1-emitter. Now, VE is
18. (a) Let us assume that Vo1, Vo2, Vo3 and Vo4 are equal to voltage at inverting input of amplifier A3.
the outputs, respectively, for V1, V2, V3 and V4 Now, A1 is a unity gain inverting summer and A2
present one at a time with other inputs grounded. is a unity gain inverting amplifier. The voltage at
non-inverting input of A3 is therefore sum of VIN
With only V1 present and all other inputs grounded,
the output Vo1 = V1.
and voltage appearing across 10 kW resistor at the
input of A1. The voltage across 10 kW resistor is
With only V2 present and all other inputs grounded,
the output Vo2 = V2. 5 10 103
V = 2V
With only V3 present and all other inputs grounded, 25 103
voltage appearing at non-inverting input is given by
Therefore, at positive peak of VIN,
V3 (R / 2) V3
= VE = 2 + 1 = 3 V
R + (R / 2) 3
and at negative peak of VIN,
This gives the output Vo3 = V3.
Similarly, with only V4 present and all other inputs VE = 2 1 = 1 V
grounded, the output Vo4 = V4. For VIN = 0 V, we have
When all inputs are present simultaneously, output
Vo equals algebraic sum of Vo1, Vo2, Vo3 and Vo4. VE = 2 V
That is, Therefore, at the positive peak of VIN, the laser
Vo = V3 + V4 V2 V1 diode current I is
19. (a) V1 = 10 V and V2 = 0.7/AOL, where AOL is the 53
A = 100 mA
20 103
open-loop gain of opamp:
AOL= 100 dB = 100,000 and at the negative peak of VIN, the laser diode
current is
Therefore,
5 1
A = 200 mA
20
0.7 V
V2 = = 7 mV
100, 000
Therefore, the output waveform is similar to that
given in option (a).
20. (b) The cut-off frequency is
1 22. (c) The differential gain is
fC =
2p 10 10 1000 10 -12
3
2R1
105 Av = 1 +
= = 15.915 kHz RG
2p
Therefore,
The gain is
2 100 103
1 + 100 103 Av = 1 + = 201
Av = = 11 = 20.8 dB 1 103
10 103
The gain at cut-off frequency in dB is The common mode gain is
20.8 3 = 17.8 dB (2R2/R2) = (2 Tolerance of R2)

Therefore, the common-mode gain is Therefore, the opamp output goes to negative sat-
uration with the result that LED-1 is OFF and
2 0.0005 = 0.001
LED-2 is ON.
That is,
30. (d)
201
CMRR = = 201,000
0.001 31. (b)
Thus, 32. (a)
CMRR (in dB) = 20log 201000 106 dB
33. (c)
23. (c) When the variable terminal of the potentiome-
ter is at A, the non-inverting terminal is grounded. 34. (c)
The amplifier is a simple inverting amplifier with a R R R
voltage gain of (nR/R) = n. Vo = Vs1 1 + 1 2 + Vs2 1 + 2
R2 R1 R1
24. (a) When the variable terminal of the potentiom- Therefore, the circuit is a subtractor.
eter is at B, the non-inverting terminal has input
Vin applied to it. Voltage gain in this condition is 35. (a) Vo = (5 1.2 5) + (3 6) = 12 V.
equal to a non-inverting voltage gain of
36. (a) The LTP is given by
nR
1+
nR (2n - 1)
= 2n 12 15 103
= 1.565 V
15 103 + 100 103
and an inverting voltage gain of (nR/R) = n.
Therefore, the net voltage gain in this condition is 37. (b) The UTP is given by
2n n = n 12 33 103
= 2.977 V
25. (b) The no-load output voltage is 100 mV since the 33 103 + 100 103
voltage gain is unity. 38. (a) It is obvious from the explanations given in the
Solution of Questions 36 and 37.
26. (a) Bandwidth = (Unity gain cross-over frequency)/
gain. As gain is unity, bandwidth = 1 MHz. 39. (a) The circuit is a first-order low pass filter.
27. (c) The load current is 40. (b) The cut-off frequency is
3
99.5 10 fC =
1
2p 10 10 1000 10 -13
= 9.95 mA 3
10
Therefore, closed-loop output impedance is 105
= Hz = 15.915 kHz
2p
100 103 99.5 103
= 0.05 W The mid-band gain is
9.95 103 100 103
Av = 1 + = 11 = 20.827 dB
28. (a) When switch SW-1 is in position A, the voltage 10 103
appearing at non-inverting input is +0.7 V (equal Now,
to forward-biased voltage drop across D1). That is, 128 kHz
voltage at non-inverting input is more positive with 8
15.9 kHz
respect to voltage at inverting input. Therefore,
opamp output goes to positive saturation with the The gain at frequency eight times the cut-off fre-
result that LED-1 is ON and LED-2 is OFF. quency will be 18 dB below the value of mid-band
gain. Therefore, the gain at eight times the cut-off
29. (c) When switch SW-1 is in position B, the volt- frequency is
age appearing at non-inverting input is 0.7 V 20.827 18 = 2.827 dB
(equal to forward-biased voltage drop across D2).
41. (b) Output voltage is
That is, the voltage at non-inverting input is more
negative with respect to voltage at inverting input. 10 106 100 103 = 1 V

42. (c) The open loop gain of the opamp is 120 dB = 10 103
106. The input impedance seen by the photodiode is = 10 MW
1
100 103 The output current from the photodiode is
W = 0.1 W
106 0.5 10 103 = 5 MA
43. (a) The feedback topology is voltage-shunt. The voltage across the resistance R IS
44. (d) The current of the photodiode is converted into 50 5 103 = 250 MV
voltage through the resistor provided. The voltage 46. (c) The gain of the amplifier is
across the resistor is applied to the non-inverting
R2 10 103
input of the opamp. The op-amp work as A non- = 1+ = 11
1 103
1+
inverting amplifier. R1
45. (c) The incident light pulse has energy of 10 mJ The voltage amplitude of the output pulse is
and pulse width of 1 s. Therefore, the input peak 250 103 11 = 2.75 V
power is
1. We have Hence,
dv ID = 0.5 A = 500 mA
= 50 V/ms = 50 106 Ans. (500)
dt
It is given that the input frequency is f = 10 MHz. 4. When the control signal is high, the input voltage
The output voltage is v = Vo sin wt, where Vo is is 2 V. Let ID be the current through the diode.
the peak value of the output waveform. Therefore, Therefore,
dv
= Vow cos wt 5 103
ID 0.1 = 2
dt 100 103
The maximum value of dv/dt is
Hence,
Vow = 50 106 ID = 1 A = 1000 mA
Ans. (1000)
Therefore,
5. When VGS = 0, the JFET is conducting and its
50 106
Vo = = 0.8 V RDS = 500 W. Since the externally connected drain
2 p 10 106 resistance is much larger than RDS, the non-invert-
Ans. (0.8) ing terminal is grounded for all practical purposes.
2. The voltage at the inverting terminal of the opamp Therefore, the voltage gain is
is the same as the voltage at the non-inverting ter- 100 103
minal. Therefore, the voltage across resistor R is = 1
100 103
15 2.5 = 12.5 V Ans. (-1)
The current through the laser diode is the same as 6. When VGS = 5 V, the JFET is in cut-off state.
the current through resistor R. Therefore, The circuit in this case acts like both a non-invert-
= 10 103
12.5 ing amplifier and an inverting amplifier simultane-
R ously. The non-inverting voltage gain is
Hence, 100 103
R = 1250 W 1+ =2
Ans. (1250) 100 103
and the inverting voltage gain is
3. When the control signal is low, the input voltage
100 103
= 1
100 103
is 1 V. Let ID be the current through the diode.
Therefore,
5 103 This gives an overall voltage gain of 1.
ID 0.1 = 1
100 103 Ans. (1)


1. If the opamp shown in the following figure is ideal, The output of the comparator is HIGH when Vi >
the output voltage Vout will be equal to 2 V. At Vi = 2 V,
1
sin wt =
2
5 k
Therefore,
p p 5p
wt = or p - =
6 6 6
2V 1k Therefore,

5p p 2p
TON = = and T = 2p
+ Vout 6 6 3
3V 1k Therefore, the duty cycle is
8 k TON 2p / 3 1
D= = =
T 2p 3
Ans. (b)
(a) 1 V (b) 6 V 3. The circuit shown in the following figure is a
(c) 14 V (d) 17 V
Solution.
8 103 5 103 5 103 R R Vout
Vout = 1 + 3 2 V= 16 10 = 6 V
3 in
+
(8 10 ) + (1 10 )
3 3
1 10
3
1 10
103 5 103 5 103 C C
1 + 3 2 = 16 10 = 6 V
+ (1 103 ) 1 103 1 103
10 3 5 10
3
3
3 2 = 16 10 = 6 V
10 1 103 (a) low-pass filter (b) high-pass filter
Ans. (b) (c) band-pass filter (d) band-reject filter
2. If the input to the ideal comparator shown in the (GATE 2004: 1 Mark)
following figure is a sinusoidal signal of 8 V (peak- Solution. The filter configuration is a second-
to-peak) without any DC component, then the order low pass filter.
output of the comparator has a duty cycle of Ans. (a)
4. In the opamp circuit given in the following figure,
Input + the load current iL is
Output
Vref = 2V
R1 R1
1 1 Vs
(a) (b)
2 3
+
1 1
(c) (d) R2
6 12
(GATE 2003: 1 Mark) R2
Solution. The input signal Vi is given by RL
Vi = 4 sin wt iL

Vs Vs Indicate the correct transfer characteristics assum-

(a) (b) ing ideal diodes with zero cut-in voltage
R2 R2
Vs Vs Vo
(c) (d) +10V
RL R1
Solution. Let the output voltage of the opamp be 8 V +5 V

Vo and the voltage at the non-inverting terminal (a) Vi
be V. Applying KCL at the non-inverting terminal
of the opamp, we get
V V V Vo
+ + =0
R2 RL R2
Solving the above equation, we get 10 V
2V V V +10V Vo
+ = o
R2 RL R2
Applying KCL at the inverting terminal of the
opamp, we get
V Vs V Vo 5 V +8 V
+ =0 (b) Vi
R1 R1
Vs 2V = V o
10V
Substituting the value of Vo in the above equation,
we get
2V V 2V Vs +5V Vo
+ =
R2 RL R2
The current iL is given by V/RL. Therefore, from
the above equation, we get
Vs 5V +5 V
i L= (c) Vi
R2
Ans. (a)
5. Given the ideal operational amplifier circuit shown
+10V 10 V
+10V Vo
Vi
Vo
+
5V +5V
(d) Vi
10 V
2 k
0.5 k
2 k 5V

Solution. Let us assume that the output voltage (c) High pass, 10,000 rad/s
is positive, that is, +10 V. The lower diode con- (d) Low pass, 10,000 rad/s
ducts in this situation and the voltage at the non- (GATE 2005: 2 Marks)
inverting terminal of the opamp is
10 k
2 103
10 = 8 V
2 103 + 0.5 10 3
When the input voltage Vi at the inverting termi- 10 k

nal exceeds +8 V, the output goes from positive
saturation voltage, +10 V, to the negative satura-
tion voltage, 10 V. The upper diode conducts in
Vo
this situation and the voltage at the non-inverting Vi +
terminal of the opamp is 1 F
2 103
10 = 5 V
2 103 + 2 103 1k
When the input voltage Vi at the inverting termi-

nal goes below 5 V, the output goes from negative
saturation voltage, 10 V, to positive saturation
voltage, +10 V. Therefore, the transfer character-
istics shown in option (b) are correct. Solution. From the diagram it is clear that the
Ans. (b) circuit is a high-pass filter. The cut-off frequency in
6. The input resistance Ri of the amplifier shown in rad/s is given by
the following figure is 1
rad/s = 1000 rad/s
1 10 1 106
3
30 k Ans. (a)
10 k capacitor C is initially uncharged. At t = 0, the
switch S is closed. The voltage VC across the
capacitor at t = 1 ms is
+
C = 1 F
S
+
VC
R1
30
(a) kW (b) 10 kW 1 k
4
(c) 40 kW (d) Infinite Vo
+
(GATE 2005: 1 Mark)
10 V
Solution. The input resistance of an inverting
amplifier with ideal opamp is the series resistance
connected to the inverting terminal of the opamp
(In the figure above, the opamp is supplied with
15 V and the ground has been shown by the
through the input voltage source. Therefore, the
symbol )
input resistance is 10 kW.
Ans. (b)
(a) 0 V (b) 6.3 V
7. The opamp circuit shown in the following figure is
(c) 9.45 V (d) 10 V
a filter. The type of filter and its cut-off frequency
are, respectively,
(a) High pass, 1000 rad/s Solution. Applying KCL at the inverting node of
(b) Low pass, 1000 rad/s the opamp, we get

10 Statement for Linked Answer Questions 10

= C C = 106
dV VC
3
1 10 1 103
and 11: Consider the opamp circuit shown in the
dt
following figure.
VC at t = 1 ms is
10 1 103 R1
VC = = 10 V
1 103 1 106 R1
Ans. (d)
9. In the opamp circuit shown in the following figure, Vi Vo

assume that the diode current follows the equation +
I = I s exp ( V VT ) . For Vi = 2 V, Vo = Vo1, and
R
for Vi = 4 V, Vo = Vo2. The relationship between C
Vo1 and Vo2 is
10. The transfer function Vo(s)/Vi(s) is

2 k
Vi 1 sRC 1 + sRC
(a) (b)
Vo 1 + sRC 1 sRC
1 1
+ (c) (d)
1 sRC 1 + sRC
(a) Vo2 = ( 2 )Vo1 (b) Vo2 = e2Vo1
(c) Vo2 = Vo1 ln 2 (d) Vo1 Vo2 = VT ln 2 Solution. The output voltage Vo is given by
(GATE 2007: 2 Marks) R 1 sC R1
Vo (s) = 1 Vi (s) + 1 + V (s)
R1 R + 1 sC R1 i
Solution. As the input impedance of the opamp
is very high, the current through the resistor 2 kW Solving the above equation, we get the transfer
(IR) is equal to the current through the diode (ID). function as
Applying KCL at the inverting node of the opamp, Vo (s) 1 sRC
=
we get V i (s) 1 + sRC
0 Vi V 0 Vo Ans. (a)
3
= I s exp D = I s exp
2 10 VT VT 11. If Vi = V1 sin (wt) and Vo = V2 sin (wt + f ) , then
0 Vi VD 0 Vo the minimum and maximum values of f (in radi-
= I s exp V = I s exp V ans) are, respectively,
2 103 T T p p p
(a) and (b) 0 and
Solving the above equation and rearranging the 2 2 2
terms, we get
p
Vi (c) p and 0 (d) and 0
Vo = VT ln
2 103 I
2
s (GATE 2007: 2 Marks)
It is given that when Vi = 2 V, we get Vo = Vo1
and when Vi = 4 V, we get Vo = Vo2. Therefore, Solution.
Vo (s)
w = = (1 sRC ) (1 + sRC )
2
Vo1 = VT ln and
2 10 I
3
s
V i (s)
4 = tan1w RC tan1w RC
Vo2 = VT ln
2 103 I = 2 tan1 w RC
s
Therefore,
2 4 The minimum value of f occurs when w .
Vo1 Vo2 = VT ln + VT ln = VT ln 2 Therefore, fmin = p.
2 10 I s 2 10 I s
3 3
The maximum value of f occurs when w = 0.
Therefore, fmax = 0.
4
+ VT ln = VT ln 2
Is 2 10 I s
3
Ans. (d) Ans. (c)

12. For the opamp circuit shown in the following 0 Vi (s) 0 Vo (s)
R1 + Ls R2 ( R2Cs + 1)
figure, Vo is + =0
Therefore, the transfer function of the circuit is

2 k
Vo (s) R2 R2
1k = =
V i (s) ( R1 + Ls)( R2Cs + 1) 2
R2 LCs + (R1R2C + L)
Vo (s) R2 R2
= =
1V
+ V i (Vs)o ( R1 + Ls)( R2Cs + 1) R2 LCs2 + (R1R2C + L)s + R1
1k This is equivalent to the transfer function of a sec-
1k ond-order low pass filter, which is given by
A
2
Bs + Cs + D
Therefore, the circuit given is that of a low-pass
(a) 2 V (b) 1 V filter.
(c) 0.5 V (d) 0.5 V Ans. (b)
14. Consider the Schmidt trigger circuit shown in the
following figure. A triangular wave which goes from
Solution. The voltage at the non-inverting input
12 V to +12 V applied to the inverting input of
of the opamp is
the opamp. Assume that the output of the opamp
1 103 swings from +15 V to 15 V. The voltage at the
1
1 103 + 1 103
= 0.5 V non-inverting input switches between

The output voltage is +15 V
2 10 3 2 10 3 10 k
Vo = 1 + 1 + 0.5
1 103 1 103

= 2 + 1.5 = 0.5 V Vi
Ans. (c)
Vo
13. The opamp circuit shown in the following figure
represents a +
10 k
C
10 k
R2
15 V

Vi R1 L (a) 12 V and + 12 V (b) 7.5 V and + 7.5 V
Vo (c) 5 V and + 5 V (d) 0 V and 5 V
+ (GATE 2008: 2 Marks)
Solution. Let the voltage at the non-inverting

input be Vni. Applying KCL at the non-inverting
node of the amplifier, we get
(a) High-pass filter (b) Low-pass filter Vni 15 Vni (15) Vni Vo
+ + =0
10 103 10 103 10 103
(c) Band-pass filter (d) Band-reject filter
Therefore,
Solution. Applying KCL at the inverting terminal Vo
of the opamp, we get Vni =
3

Since the output voltage swings from 15 V to +15 V, 10 V

the input voltage at the non-inverting input of the
opamp swings from 5 V to +5 V.
Ans. (c) 5 k
15. Consider the circuit (shown in the following
figure) using an ideal opamp. The I-V charac-
teristics of the diode is described by the relation V +
I = I o (eV /VT 1) where VT = 25 mV, Io = 1 mA

and V is the voltage across the diode (taken as
positive for forward bias).
1.4 k 5V
D 4 k
(a) Positive feedback, V = 10 V

Vi = 1V (b) Positive feedback, V = 0 V
(c) Negative feedback, V = 5 V
100 k (d) Negative feedback, V = 2 V
Vo (GATE 2009: 2 Marks)
+
Solution. From the circuit, we see that the feed-
back is negative feedback. The given circuit can be
redrawn as shown in the following figure.
For an input voltage Vi = 1 V, the output volt-
age Vo is 10V
(a) 0 V (b) 0.1 V
(c) 0.7 V (d) 1.1 V I 5 k
5V
Solution. As the input impedance of the opamp is
very high, the current flowing through the diode is V +

the same as the current flowing through the 100 kW +
resistor. Therefore, VBE
0 Vi
+
= I o (eV /V T 1) 1.4 k
5V
100 103
V

Substituting the value of Vi = 1 V, VT = 25 mV I
and Io = 1 mA and solving the above equation, we get
V = 59.9 mV
Applying KCL at the inverting terminal of the The current I is
opamp, we get 10 5
I= = 1 mA
0 (1) 0 + 59.9 10 Vo
3
5 103
+ =0
100 103 4 103 V = V+
The voltage is VBE = 1.4 + 0.6 = 2 V
V = 1.4 103 1 103 = 1.4 V

Vo = 0.1 V
Ans. (b) The voltage V is
16. In the circuit shown in the following figure, the V = V + VBE = 1.4 + 0.6 = 2 V
opamp is ideal, the transistor has VBE = 0.6 V and
b = 150. Decide whether the feedback in the circuit
Ans. (d)
is positive or negative and determine the voltage V 17. Assuming the opamp to be ideal, the voltage gain
at the output of opamp. of the amplifier shown in the following figure is


ii
R1 R1
Vo
+ R2 +
Vi
+ +
R3 vo

R2 R3
(a) (b) Therefore, the output voltage is vo = R1iL. Hence,
R1 R1 the given circuit is a high-pass filter.

Ans. (d)
R R R + R3
(c) 2 3 (d) 2
R
19. The transfer characteristic for the precision recti-
1 R1 fier circuit shown in the following figure is (assume
(GATE 2010: 1 Mark) ideal opamp and practical diodes)
Solution. The given circuit is that of an inverting +20 V

amplifier with a load resistor (R3) connected at the R
ouput. Therefore, the gain of the amplifier is
R
2
R1 D2
4R
Ans. (a)
18. The circuit below implement a filter between the
input current ii and output voltage vo. Assume vi
R vo
that the opamp is ideal. The filter implemented is a +
D1
L1
ii vo
R1
10
+ + (a)
vo
vi
10 5 0
(a) low-pass filter (b) band-pass filter
(c) band-stop filter (d) high-pass filter
vo
(GATE 2011: 1 Mark)
Solution. At w = 0, XL1 = jwLL1 = 0. Hence, the
circuit can be redrawn as shown below
(b) 5
R1 vi
ii 10 5 0

vo
+ +
vo

(c) 5
Therefore, the output voltage vo = 0 at w = 0. At vi
w = , XL1 = . Hence, the circuit can be redrawn 0 +5
as shown in the following figure:
vo
10
(d)

(c) 5
vi
0 +5
vo
w=
1
rad/s
R1C
10 Ans. (b)
(d)
21. In the circuit shown in the following figure, what
is the output voltage (Vout) if a silicon transistor Q
vi
0 +5 and an ideal opamp are used?
(a) 15 V (b) 0.7 V (c) +0.7 V (d) +15 V
Solution. For vi < 5 V, diode D2 is conducting
and diode D1 is not conducting. Q
+15V
At vi = 10 V, applying KCL at the inverting ter- 1 k
minal of the opamp, we get
0 20 0 (10) 0 vo
+ + =0 + + Vout
4R R R

5V
Therefore, vo = +5 V. At vi = 5 V, applying
15V
KCL at the inverting terminal of the opamp, we get
0 20 0 (5) 0 vo
+ + =0
4R R R Solution. The output of the opamp is negative as
Therefore, vo = 0 V. For vi > 5 V, both diodes are the input appearing at the inverting input of the
conducting. So, vo = 0 V. opamp is more than the input at the non-inverting
Ans. (b) terminal. The transistor Q is conducting as Vout,
20. The circuit shown is a which is also the emitter voltage is negative and
the base terminal of the transistor Q is at zero
R2 potential. Since the transistor Q is conducting, VBE
C R1 = 0.7 V. Since VB = 0 V, VE = Vout = 0.7 V.
+ +5V + Ans. (b)
Input Output
+
5V opamps are ideal. Vout (in volts) is
(a) 4 V (b) 6 V (c) 8 V (d) 10 V
1 k 1 k
(a) Low-pass filter with f3dB =
1
rad/s 2 V
(R1 + R2 )C
+15 V +15V
1 +
(b) High-pass filter with f3dB = rad/s
R1C + 15 V Vout

(c) Low-pass filter with f3dB =
1
rad/s 1 k 15V
R1C
1 +1V 1 k 1 k
(d) High-pass filter with f3dB = rad/s
(R1 + R2 )C
Solution. The transfer function of the given cir-
Solution. The output voltage of the first opamp is
cuit is
R2 R2sC (R2 /R1 )s 1 1 + 1 10 2 1 10 = 4 V
3 3
(O/P)
1 103
1 103
T (s) = = = =
(I/P) R1 + (1/Cs) R1sC + 1 s + (1/R1C )
(O/P) R2 R 2 sC ( R2 /R1 ) s The output voltage of the second opamp is
T (s) = = = =
(I/P) R1 + (1/Cs) R1sC + 1 s + (1/R1C ) 1 10
3
4 1 + = 8V
1 103
It is the transfer function of the high-pass filter
with cut-off frequency Ans. (c)

CHAPTER 19
FILTERS
In this chapter, we discuss the passive low-pass and high-pass filters. The active filter configurations have been dis-
cussed in Chapter 18.
19.1 PASSIVE LOW-PASS FILTERS the frequency at which output amplitude is 0.707 times
(or 3 dB below) the nominal maximum amplitude. The
ratio vo/vi becomes 0.707, when the resistance (R) equals
19.1.1 Basic RC Low-Pass Filter capacitive reactance (XC). Therefore, the cut-off fre-
quency (fuc) is given by Eq. (19.2):
Figure 19.1 shows the basic RC low-pass circuit com-
1
fuc =
2pRC
prising of a single section RC circuit with output taken (19.2)
across the capacitor. The output voltage is given by
Eq.(19.1):
R
XC
vo = v (19.1)
(R 2 + X 2 ) i
C
Qualitatively, since the output is taken across the capac- vi C vo

itor and the reactance of a capacitor is inversely pro-
portional to the frequency, the output voltage will fall
with increase in frequency (Fig. 19.2). That is how an
RC network of the type shown in Fig. 19.1 behaves as
a low-pass circuit. The upper 3-dB cut-off frequency is Figure 19.1| RC low-pass circuit.

448 Chapter 19: Filters
Figure 19.2 shows the frequency response of a RC low- 10% to 90% of the impressed transition or step. From the
pass circuit. exponential charging relationship, it can be verified that
vo
vi vi
V
1
vo
0.707 vo =V (1et/RC )
f 0 t
fuc
Figure 19.2| Frequency response of a RC low-pass (a)
circuit.
vi
19.1.1.1Step Input V
Vtp
For a step input vi, as shown in Fig. 19.3(a), the output vo
voltage vo, which is also voltage across C, rises exponen- Vtp(e(ttp)/RC )
tially towards the final value of V with a time constant
RC. The output voltage vo is given by Eq. 19.3:
vo = V (1 et/RC ) (19.3) vo =V (1et/RC )
This expression is valid only when the capacitor is ini- 0 tp t

tially fully discharged. If the capacitor were initially
charged to a voltage Vo, less than V, then the exponen- (b)
Figure 19.3| (a) Step response of low-pass circuit.
tial charging equation would be given by Eq. (19.4):
vo = [V (V Vo )et/RC ] (19.4) (b) Pulse response of low-pass circuit.
If this input step occurs at time t = t1, then Eq. (19.5) tr = 2.2RC (19.9)
represents the charging process: The relationship between the upper 3-dB cut-off frequency
vo = V [1 e(tt1 )/RC ]
fuc (MHz) and the rise time tr (ms) is given by Eq. (19.10):
(19.5)
0.35
fuc = (19.10)
tr
19.1.1.2Pulse Input This expression indicates that higher the upper 3-dB
cut-off frequency, smaller is the rise time. Therefore, for
For the pulse input (vi) as shown in Fig. 19.3(b), the output
a faithful reproduction of fast transitions, fuc should be
(vo) during the high time of the pulse is given by Eq. (19.6):
as high as possible.
vo = V (1 et/RC ) (19.6)
19.1.2 RC Low-Pass filter Circuit
At t = tp, the amplitude of the output voltage is given as an Integrator
by Eq. (19.7):
tp /RC
vo (t = tp) = V (1 e
In the given RC circuit, if the product RC is much larger
) = Vtp (19.7)
than the time period T of the applied input, the capaci-
The output vo during the low time of the pulse is given tor voltage (or the output voltage in the present case)
by Eq. (19.8): would change by only a very small amount as the input
goes through a complete cycle. The output voltage vo
(t tp )/RC
vo = Vtp (e ) (19.8) across the capacitor is given by Eq. (19.11):
1 1 v 1
The quality with which this network reproduces fast vo = idt = i dt =
RC i
v dt (19.11)
transitions is expressed by the magnitude of the rise time C C R
tr, which is the time taken by the output to change from In fact, if RC 15T, the integration is near ideal.

19.2PASSIVE HIGH-PASS FILTERS 449
It may be mentioned here that the basic RL circuit vo

(Fig.19.4) behaves as an integrator circuit, if the time vi
constant L/R were much larger than the time period of
the input waveform. 1
L 0.707
vi i R vo
f
flc
Figure 19.6| Frequency response of high-pass circuit.
Figure 19.4| Basic RL circuit.
is its effect on the flatter portions of the waveform. The

19.2 PASSIVE HIGH-PASS FILTERS effect of different lower 3-dB cut-off frequencies in a
high-pass RC circuit for a pulsed waveform input are
depicted in Fig. 19.7.
19.2.1 Basic RC High-Pass Filter
Figure 19.5 shows the basic RC high-pass circuit. The vi

operation of this circuit can be explained on lines similar
to the description of RC low-pass circuit. The output T
voltage (vo) is given by Eq. (19.12): t
vo
R v
vo = (19.12)
(R 2 + X 2 ) i
C RC << T
t
(flc very high)
C vo
vi R vo RC comparable
t to T
(flc intermediate)
Figure 19.5| RC high-pass circuit.

vo
Since the reactance of a capacitor is inversely propor- RC >> T

tional to the frequency, it would increase with decrease t
(flc very low)
in frequency. Consequently, the output voltage falls with
decrease in frequency of the input waveform thus lending Figure 19.7| Effect of lower 3-dB cut-off frequency
the circuit shown in Fig. 19.5 its high-pass characteris- on pulsed waveform input.
tics as shown in Fig. 19.6. The frequency where the ratio
vo/vi falls to 0.707 of its maximum value is known as the 19.2.2 RC High-Pass Filter as Differentiator
lower 3-dB cut-off frequency.
The lower 3-dB cut-off frequency (flc) is given by Eq. (19.13): A differentiator circuit is the one in which the output
response is proportional to differential of the input excita-
1 (19.13)
flc = tion. In other words, output is proportional to the slope of
2pRC the input. In the case of the RC circuit shown in Fig.19.5
The lower 3-dB cut-off frequency flc affects the low fre- where the output is taken across R, if the time constant
quency response due to the high-pass nature of the cir- RC is much smaller than the input waveform time period,
cuit. Lower the lower 3-dB cut-off frequency, less severe it is safe to assume that whole of input vi appears across

C only, as the input goes through one complete cycle.

The output voltage vo is given by Eq. (19.14): R
dv dv
vo = RC i i (19.14)
dt dt vi L vo
i
This explains that RC high-pass circuit behaves as a dif-
ferentiator under specified conditions.
It may be mentioned here that the basic RL circuit (Fig.
19.8) behaves as a differentiator if the time constant L/R
were much smaller than the input waveform time period. Figure 19.8| RL differentiator circuit.
IMPORTANT FORMULAS
1. The upper 3-dB cut-off frequency fuc of a basic RC 2. The lower 3-dB cut-off frequency of a basic RC
low-pass filter is high-pass filter is
1 1
fuc =
2pRC
flc =
2pRC
SOLVED EXAMPLES
1. Refer to the circuit and the graph given in the fol- Solution. The time taken for the output voltage,
lowing figures. In what time will the output rise vo, to rise from 1 V to 9 V is equal to the rise time,
from 1V to 9V? tr. That is,
tr = 2.2RC = 2.2 1 103 0.01 106 = 22 s
1 k
Ans. (a)
2. The basic low-pass RC circuit has 3-dB cut-off
frequency of 3.5 kHz. If this circuit were fed at
vi 0.01 F vo the input with a 20 V step, in what time will the
output rise to 12.6 V starting from the time of
receiving the step?
(a) 43.7 s (b) 45.5 s
(c) 55.5 s (d) 49.5 s
vi (V) Solution. The 3-dB cut-off is 3.5 kHz. The rise time is
= 104 s
0.35 0.35
10 =
fC 3.5 103
Therefore, 2.2RC = 104, which gives
104
RC = = 45.5 ms
2. 2
t1 t The output will rise to 12.6 V (which is 63% of the
final value of 20 V) in 45.5 s (which is equal to
(a) 22 s (b) 2 s time constant).
(c) 20 s (d) 10 s Ans. (b)
1. What is the time constant of a low-pass RC filter Solution. Time constant of an RC low-pass filter is
with R =1 k and C = 1 F (in s)? RC = 1 103 1 106 = 103 s = 1000 s
Ans. (1000)

PRACTICE EXERCISE
1. A 100 s pulse is applied to the RC high-pass cir- (c) either a differentiator or an integrator circuit
cuit shown in the following figure. What is the time (d) None of these
taken by output pulse to go to near zero after the (1 Mark)
input pulse goes low? 3. A high-pass circuit can also possibly be
vi
(a) an integrator circuit
(b) a differentiator circuit
10 V (c) either a differentiator or an integrator circuit
(d) None of these
(1 Mark)
4. A low-pass circuit with a relatively higher upper
3-dB cut-off frequency shall
t(s)
0 100 (a) have relatively more sluggish step response
(b) have relatively steeper step response
0.1F (c) behave more like an integrator
(d) None of these
(1 Mark)
5. A low-pass circuit is fed with a periodic waveform
of time period T. For this circuit to function like an
vi 10 k vo
integrator, the necessary condition to be satisfied is
(a) RC = T (b) RC << T
(c) RC >> T (d) None of these
(1 Mark)
(a) 1 ms (b) 2 ms
(c) 10 ms (d) 100 ms 6. An RC integrator circuit with an upper 3-dB cut-
(2 Marks) off frequency of 3.5 kHz will respond to a step input
with a rise time of
2. A low-pass circuit can also possibly be
(a) 100 s (b) 10 s
(a) an integrator circuit (c) 100 ms (d) Indeterminate from given data
(b) a differentiator circuit (2 Marks)
1. Refer to the following figure. What is the ampli-

tude (in volts) of vo at the time of input pulse 10 k
going low?
vi (V)
10 vi 0.1 F vo
(2 Marks)
2. Refer to the figure shown in Question 1. What is
the amplitude (in volts) of vo, 1 ms after the input
pulse has gone low?
t(ms)
0 1 (2 Marks)

1. (b) The output voltage at the time of termination we can calculate the required time for the output
of input pulse, that is, at t = 100 s can be calcu- to decay to zero to be 1.9 ms 2 ms.
lated from the following:
2. (a)
(104/RC ) (104/103 ) 10
vo = 10 10 [1 e ] = 10e = = 9 3. (b)
e0.1
4 4
/103 )
e(10 ] = 10e(10
/RC ) 10 4. (b)
=9 V
=
e0.1 5. (c)
As the input pulse goes to zero, the output goes to
1 V as the voltage across capacitor cannot change 6. (a) Cut-off frequency is
instantaneously. The output then gradually rises
1
towards zero as the capacitor discharges. = 3500
Since the input and output are isolated by a block- 2pRC
ing capacitor, the output will always have a zero DC Therefore,
or average value. That is, area under the positive
= 45.5 106 s = 45.5 s
portion must equal area under the negative portion. 1
RC =
Assuming the charge and discharge process to be 2p 3500
linear which is a valid assumption when the circuit
Therefore, the rise time is 2.2RC = 100 s.
time constant is much larger than the pulse width,
1. The time constant is 2. When the input pulse goes low, the capacitor starts
R C = 10 103 0.1 106 = 103 s = 1 ms

discharging as per
(t tp )/RC
In general, the charging process is governed by the vo = V [e ]
expression
Here, V = 6.31 V and tp = 1 ms. Now, vo will be
vo = V (1 et/RC ) 36.9% of V, 1 ms after the capacitor starts dis-
charging as 1 ms happens to be equal to circuit
The pulse goes low at t = 1 ms, which is also equal
time constant. Therefore, the output voltage after
to the RC time constant.
1 ms is
For t = RC, the output voltage vo is 63.1% of the
input voltage, V. Therefore, 0.369 6.31 V = 2.33 V
vo = 6.3 V Ans. (2.33)
Ans. (6.3)

CHAPTER 20
SINUSOIDAL OSCILLATORS
The topics discussed in this chapter include oscillator

+

fundamentals such as the Barkhausen criterion for oscil- Vin E A Vout
lations, popular oscillator circuit configurations, which
include different types of RC, LC and crystal oscillators
and oscillator frequency stability considerations. b
20.1 CONDITIONS FOR (a)

OSCILLATIONS BARKHAUSEN

+ E
CRITERION Vin A Vout
+
An oscillator circuit is essentially an amplifier circuit b

with a frequency selective feedback network. The feed-
back network feeds a fraction of the amplifier output
back to its input in such a way as to satisfy the two fun- (b)
damental requirements of occurrence of sustained oscil- Figure 20.1| Canonical form of feedback systems.
lations. These requirements are commonly known by the (a)Negative feedback system
name of Barkhausen criterion. (b) Positive feedback system.

454 Chapter 20: Sinusoidal Oscillators
Barkhausen criterion can be best explained by consider- In practice, loop gain is kept slightly greater than
ing the canonical form of negative and positive feedback unity to ensure that oscillator works even if there is a
systems as shown in Figs. 20.1(a) and (b), respectively. slight change in the circuit parameters due to ageing,
The transfer function in the case of negative feedback replacement or any other reason. Moreover, there is no
system of Fig. 20.1(a) is given by harm in keeping loop gain slightly greater than unity
Vout as the output cannot increase infinitely as it appears
A
= (20.1) because the output amplitude will be limited due to
Vin (1 + bA) onset of non-linearity of active device used. However, if
In the case of a positive feedback system, the transfer bAis much larger than unity, the oscillator output will
function is given by Eq. (20.2): have lot of distortion.
Vout Sinusoidal oscillators are classified on the basis of
A
= (20.2) type of frequency selective network used in the feed-
Vin (1 bA) back loop. The different types of sinusoidal oscilla-
If bA = 1 = 1180 in the case of negative feed- tors include RC oscillators, LC oscillators and crystal
back system and bA = 1 = 10 in the case of positive oscillators.
feedback system, the system works like an oscillator. In
the case of the former, the conditions specify magnitude
of loop gain as unity and loop phase-shift as 180. In 20.2 RC OSCILLATORS
the case of latter, the conditions specify magnitude of
loop gain as unity and loop phase-shift as 0 or 360.
Thecondition for the magnitude of the loop gain is the In the case of RC oscillators, multiple RC sections are
same in the two cases. If we carefully examine the two used to provide the required phase-shift. The prominent
cases, we shall find that the loop phase-shift condition is candidates in the category of RC oscillators include the
also the same as phase inversion implied by the negative RC phase-shift oscillator, Twin-T oscillator, Wien bridge
sign at the summing point restores the overall phase- oscillator, Bubba oscillator and quadrature oscillator.
shift up to the point of amplifier input to be the same.
Essentially the two conditions mean the following: 20.2.1 RC Phase-Shift Oscillator
1. The magnitude of loop gain is unity, which ensures
that feedback signal has the same magnitude as The basic RC phase-shift oscillator comprises of a single
that of the input signal. stage amplifier whose output is fed back to its input
2. The magnitude of loop phase-shift is such that the through a feedback network. The amplifier portion is
feedback signal is in phase with the input signal usually implemented by either a bipolar junction tran-
when it reaches the input of the amplifier. sistor based common emitter amplifier stage, junction
FET based common source amplifier stage or an oper-
These two conditions define what is known as Barkhausen
ational amplifier wired as an inverting amplifier. The
criterion of oscillations. Satisfying Barkhausen criterion
feedback network comprises of a cascade arrangement
ensures that oscillator circuits do not need an external
of three identical sections of either lag- or lead-type RC
applied input signal. Instead they use fraction of the
network. Figure 20.2 shows the circuit schematic of an
output signal as the input signal.
RC phase-shift oscillator using a common-emitter ampli-
In practical oscillator circuits, the summing point
fier stage and a lag type of RC feedback network.
is an adder and therefore the Barkhausen criterion of
Figure 20.3 shows another version of RC phase-shift
oscillations is written as follows:
oscillator in which the amplifier portion is implemented
1. |bA| = 1. That is, loop gain should be unity using an operational amplifier configured as an inverting
2. bA = 0 or integral multiple of 360. That is, amplifier. In both cases, the amplifier provides a
loop phase-shift should be zero or integral multiple phase-shift of 180 at the frequency of operation, which
of 360. means that the feedback network must also provide
The process of generation of oscillations is initiated due an additional phase-shift of 180 at the operating fre-
to some inevitable noise present at the amplifier input. The quency to satisfy the loop phase-shift condition of the
amplified output due to noise has all frequency components. Barkhausen criterion. Also the gain to be provided by
Since the feedback network is a frequency selective one and the amplifier stage must at least equal the inverse of
the loop phase-shift condition is satisfied only at one fre- the attenuation factor of the feedback network. In fact,
quency, the signal fed back to the input has a single fre- in the phase-shift oscillator, while the amplifier gain is
quency component at which the loop phase-shift condition dictated by the feedback network attenuation factor, the
of the Barkhausen criterion is satisfied. This leads to the phase-shift provided by the amplifier stage decides the
oscillator circuit producing a sinusoidal output. phase-shift to be provided by the feedback network.

20.2 RC OSCILLATORS 455
VCC Figure 20.4 shows circuit schematic of RC phase-

shift oscillator using lead type of phase-shift network.
Thecircuit uses opamp-based amplifier stage. The
RC oscillator circuit using transistorized amplifier stage
R1 Co would be similar to the one shown in Fig. 20.2 except
Vout for the feedback network.The oscillation frequency (w)
Ci
Q1 is given by
1
R2 w= (20.5)
RE CE 6RC
The feedback factor (b) is given by
1
b = (20.6)
R R R 29
C C C
R2
+V
Figure 20.2| Lag-type RC phase-shift oscillator using R1
common-emitter amplifier.
Vout
+
R2 V
+V C C C
R1

+ Vout R R R
V
R R R
Figure 20.4| Lead-type op-amp based RC phase-shift
oscillator.
C C C The buffered RC phase-shift oscillator comprises of
voltage follower stages coupled with each RC section and
overcomes the loading effect of different RC sections in
the conventional phase-shift oscillator. The oscillation
frequency of a buffered lag-type RC phase-shift oscilla-
Figure 20.3| Lag-type RC phase-shift oscillator using tor is given by Eq. (20.7) and the minimum value of the
operational amplifier. amplifier gain for s ustained oscillations is 8.
The oscillation frequency (w) is given by 3

f= (20.7)
2pRC
6
w= (20.3)
RC In the case of lead type of RC network, the oscillation
frequency of a buffered RC phase-shift oscillator would
The feedback factor (b) is given by be given by Eq. (20.8):
1
b =
1
(20.4) f= (20.8)
29 2p 3RC

An RC phase-shift oscillator has limitations when it Frequency (f/fc)

1
comes to designing a variable frequency oscillator as it 0
is impractical to simultaneously vary three capacitance
values equally. Also, adjustment of resistance values is
not recommended as variation of resistance values will
alter the loop gain of the oscillator circuit and there is 20
likelihood of it not satisfying Barkhausen criterion for
sustained oscillations. However, higher df/dw resulting
from steep phase versus frequency slope provided by the
40
three-section RC network gives a reasonably high fre-
quency stability.
20.2.2 Bubba Oscillator 60
Bubba oscillator is a slight variation of the buffered RC

phase-shift oscillator with the difference between the two
is that the Bubba oscillator uses four RC sections in the
feedback network with each RC section contributing a Gain (dB)
phase difference of 45.
(a)
20.2.3 Twin-T Oscillator

+90
The twin-T oscillator employs a twin-T type of notch
filter network as the frequency selective component in
the feedback network. Figure 20.5 shows the basic circuit
Phase
schematic of a twin-T oscillator. The circuit employs
both positive as well as negative feedback. The positive
feedback necessary to produce oscillations is provided by
a voltage divider network of R1 and R2. The negative 0
feedback is through the frequency selective twin-T 1 (f/fc)
0.01 (f/fc) 100
network. Figure 20.6 shows the magnitude and phase
response of the twin-T network as a function of normal-
ized frequency, fc.
+V 90
C C
(b)
R R Figure 20.6| (a)Magnitude and (b) phase response of
+ Vout
twin-T network.
R/2 2C V
20.2.4 Wien bridge Oscillator
R1 Wien bridge oscillator is the most widely used RC oscil-

R2
lator configuration for low frequency applications due to
simplicity of the circuit, very good frequency stability
and its amenability to variable frequency operation. The
Figure 20.5| Twin-T oscillator. only major disadvantage is its relatively higher amplitude
distortion unless special measures are taken to minimize
The oscillation frequency is given by it. The basic Wien bridge oscillator circuit comprises of
1 a single stage amplifier whose output is fed back to its
w= (20.9) input through a feedback network. The amplifier portion
RC

20.3 LC OSCILLATORS 457
is usually implemented by an operational amplifier wired The common LC oscillators are Armstrong oscillator,
as a non-inverting amplifier. The feedback network Hartley oscillator, Colpitt oscillator and Clapp oscillator.
comprises of a cascade arrangement of a series RC and
a parallel RC network. Figure 20.7 shows the circuit
schematic of the basic Wien bridge oscillator configured 20.3.1 Armstrong Oscillator
around an operational amplifier.The frequency of
oscillation is expressed by Eq. (20.10): Armstrong oscillator also known as Meissner oscillator
uses magnetic coupling as means of feeding part of output
1
w= (20.10) signal back to input to provide oscillations. It is also
R1C1R2C2 called a Tickler oscillator due to use of magnetic coupling
between the tickler coil and the coupling coil. Tickler coil
R4 is the name given to a small coil connected in series with
the plate circuit of a vacuum tube and coupled inductively
+V to the grid circuit to provide feedback. In the case of a
bipolar junction transistor or a FET, the tickler coil is
placed in series with collector or drain circuit and is induc-
tively coupled to the base or gate circuit. A capacitor is
Vout placed across either the tickler coil or the coupling coil to
+ form a tank circuit that decides the operating frequency.
R3 R4 Figures 20.8(a) and (b) show the basic circuit arrange-
ments in the two cases with N-channel junction FET
V
C1 used as the active device. Biasing components are omitted
for the sake of simplicity.The frequency of oscillation is
primarily determined by the tank circuit and is given by
C2 Eq. (20.13):
R2
1
f= (20.13)
2p LC
where L is the inductance of the coupling coil in the case

Figure 20.7| Basic Wien bridge oscillator. of circuit shown in Fig. 20.8(a) and that of tickler coil
in the case of circuit shown in Fig. 20.8(b). In practice,
In the Wien bridge oscillator, R1 = R2 = R and C1 = C2 the frequency of oscillations is slightly different from
= C. In that case, the magnitude of attenuation factor the one computed by using Eq. (20.13) because of stray
b is given by capacitances, loading of tank circuit, etc. The feedback
1
b = (20.11) factor in this case is given by ratio of mutual inductance
3 between the two coils to the inductance in the tank
This implies that the amplifier gain should at least be circuit. The minimum gain required to start oscillations
equal to 3. Also, in this case is reciprocal of the feedback factor.
1
w= (20.12)
RC +V +V
20.3 LC OSCILLATORS L C
In the case of LC oscillators, the operating frequency is deter-

mined by an LC tank circuit and is given by 1/(2p LC ).
The exact frequency of oscillation is determined by
L C
1 Q2

2p LC Q2 + 1
where Q is the quality factor of the tank circuit. The
amplifier may be configured around a bipolar transistor, (a) (b)
a junction FET, a MOSFET or an operational amplifier. Figure 20.8| Basic Armstrong oscillator configurations.

20.3.2 Hartley Oscillator The magnitude of the feedback factor b is given by

L
A Hartley oscillator uses a tapped or split coil for the b = 2 (20.15)
purpose of generating feedback signal. The current flow L1
through one section of the tapped coil induces a voltage Equations (20.14) and (20.15) imply that the feedback
in the other section to provide feedback. The feedback network introduces a phase-shift of 180 and a signal
signal is 180 out of phase with the one that produces it. attenuation by a factor of L2/L1 at the operating
Figure 20.9 shows the circuit schematic of Hartley frequency (w) provided that
oscillator configured around a bipolar junction transis- 1
tor. Incidentally, the circuit shown is that of a series-fed w=
oscillator. Figure 20.10 shows Hartley oscillator config- (L1 + L2 )C
ured around an opamp. This further implies that the amplifier must provide a
gain of >(L1/L2) to satisfy the loop gain criterion and
+V a phase-shift of 180 to satisfy the loop phase-shift
criterion. The advantage of using Hartley oscillator lies
RFC in its capability to generate a wide range of frequencies
R1 and its easy tunability.
Output 20.3.3 Colpitt Oscillator

Q1
Colpitt oscillator uses a pair of capacitors and an inductor
L1 in the tank circuit to produce the regenerative feedback
signal. In fact, the feedback network in this case is an
C electrical dual of the feedback network of Hartley oscil-
R2 RE CE
L2 lator. Figures 20.11 and 20.12 show the Colpitt oscillator
circuits configured around a bipolar junction transistor
and an opamp respectively. An FET could also be used
as the active device instead. As is obvious from the two
circuit schematics; the output signal is developed across
Figure 20.9| Hartley oscillator configured around a C1 and the feedback signal is generated across C2.
bipolar junction transistor.
+V
R2
RFC
R1
Output
+V
Q1
R1 Output C1
+ L
R2 RE CE
V
C2
L2 L1
Figure 20.11| Colpitt oscillator configured around a
bipolar junction transistor.
C The oscillation frequency is given by
Figure 20.10| Hartley oscillator configured around 1
opamp. w= (20.16)
LC1C2 /(C1 + C2 )
The frequency of oscillation is given by At this frequency,
w=
1 C
(20.14) b = 1 (20.17)
C2
(L1 + L2 )C

20.4 CRYSTAL OSCILLATOR 459
R2 (C3 in Clapp oscillator) adjustment does not alter the

attenuation factor in Clapp oscillator. The attenuation
factor is decided by C1 and C2. In the case of Colpitt
+V oscillator, any attempt to vary the frequency by varying
R1 either C1 or C2 might cause cessation of oscillations over
Output a portion of desired frequency range.
+ +V
RFC
V R1
Output
C2 C1 Q1
L
C1 L
Figure 20.12| Colpitt oscillator configured around R2
opamp.
RE CE
The feedback network introduces a phase-shift of C2 C3
180 and signal attenuation by a factor of C1/C2 at the
operating frequency w provided that
1
w=
LC1C2 /(C1 + C2 ) Figure 20.13| Clapp oscillator.
This further implies that the amplifier must provide

a gain of >(C2/C1) to satisfy the loop gain criterion 20.4 CRYSTAL OSCILLATOR
and a phase-shift of 180 to satisfy the loop phase-shift
criterion. In practice, the operating frequency is affected
by the junction capacitance whose Miller components In the case of a crystal oscillator, a quartz crystal with
appear across C1 and C2. This is overcome in Clapp the desired value of resonant frequency forms part of the
oscillator configuration. frequency selective feedback network. Crystal oscillator
is the natural choice when the accuracy and stability of
20.3.4 Clapp Oscillator oscillation frequency is of paramount importance.
Figure 20.14 shows the circuit representation and AC
A Clapp oscillator circuit (Fig. 20.13) is a slight modification equivalent circuit of the quartz crystal. Here, R, L and
of the Colpitt oscillator circuit configuration. The feedback CS, respectively, represent the resistance, inductance
circuit in the case of Clapp oscillator uses an extra capaci- and capacitance of the piezoelectric crystal element.
tor (C3 in Fig. 20.13) in series with the coil. The function Here, CM represents the mounting capacitance. It is, in
of C3 is to minimize the effect of junction capacitance fact, the capacitance due to the parallel-plate capacitor
on the operating frequency. The operating frequency f is formed by the connecting electrodes and the piezoelec-
given by Eq. (20.18): tric element constituting the dielectric. Typically, R is in
the range of few hundreds of ohms to a few kilo-ohms,
1 1 1 1 1 L is of the order of few tens of milli-henries to few henries,
f= + + (20.18)
2p L C1 C2 C3 CS is a very small fraction of a picofarad and CM is few
picofarads. The Q-factor of the crystal is given by
If C3 is chosen to be much smaller than either C1 or wL 1
Q= =
w CSR
C2, then the expression for frequency f simplifies to Eq.
R
(20.19):
The crystal exhibits two resonant frequencies. One is
1
f= (20.19) the series resonant frequency fS. It is the frequency at
2p LC3 which the inductive reactance of inductance L equals the
capacitive reactance of capacitance CS. It is expressed
Remember that we still need C1 and C2 to provide
by Eq. (20.20).
the required phase-shift for regenerative feedback. Clapp
1
oscillator is preferred over Colpitt oscillator for designing fS = (20.20)
variable frequency oscillators. The tuning element 2p LCS

Since CS is much smaller than CM, CP is only marginally

less than CS with the result that fS and fP are very close
to each other.
The two resonant frequencies described in the previous
paragraph are the fundamental resonant frequencies.
CM Remember that the specified crystal frequency is
between fS and fP. This area of frequencies between fS
and fP is known as the area of usual parallel resonance
or simply parallel resonance. A crystal can also resonate
at harmonics of the fundamental frequency called
R L CS overtones. The fundamental resonant frequency of the
Figure 20.14| Circuit representation and AC crystal is usually limited to less than 30 MHz due to the
equivalent circuit of quartz crystal. smallest physical dimension the crystal can be cut to.
The operation in the overtone mode allows stable output
Figure 20.15 shows the plot of reactance versus at much higher frequencies.
frequency for the equivalent circuit shown in Fig. 20.14. As is evident from the impedance versus frequency
Quite understandably, the impedance is a capacitive characteristics of the crystal, depending upon the
reactance below the series resonant frequency and an circuit characteristics, it can act like a capacitor, an
inductive reactance above it. The second resonant inductor, a series tuned circuit or a parallel tuned cir-
frequency called the parallel resonant frequency (fP) cuit. There are a large number of crystal oscillator
occurs at a value where the inductive reactance equals circuit configurations depending upon the mode in
the capacitive reactance due to equivalent capacitance which the crystal is used. In one of the categories of
of the tank circuit. The parallel resonance occurs at crystal oscillator circuits, crystal is connected in series
a frequency where the circulating loop current is at with the LC tank circuit in the feedback path. Each of
its maximum. Since the circulating loop current flows the LC oscillator circuits (Armstrong, Hartley, Colpitt
through series combination of CS and CM, the equiva- and Clapp) can be configured as a crystal controlled
lent capacitance of the parallel tuned circuit is given oscillator by connecting a crystal in series with the
by Eq. (20.21): tank circuit.
CM CS
CP = (20.21)
(CM + CS ) +V
The parallel resonant frequency is given by Eq. (20.22):

RFC
Crystal
1
fP = (20.22)
2p LCP
Output
XL
Cds
RG Cgs
fS fP f
Figure 20.16| Basic Pierce oscillator.
Figure 20.16 shows the basic circuit implementation of

XC a Pierce Oscillator. A field effect transistor (JFET or
MOSFET) is used as the active device and the crys-
tal along with the interelectrode capacitances (Cgs) and
Figure 20.15| Reactance versus frequency plot. (Cds) constitute the feedback network.

IMPORTANT FORMULAS
1. Barkhausen criterion of oscillations is |bA| = 1 and 11. In the Wien bridge oscillator, when R1 = R2 = R
bA = 0 or integral multiple of 360. and C1 = C2 = C, magnitude of attenuation factor
b is
2. The oscillation frequency (w) of RC phase-shift
oscillator with lag type of phase-shift network is
1
b =
6 3
w=
RC 12. For a Armstrong Oscillator, the frequency of
oscillation is
3. The feedback factor (b) of RC phase-shift oscillator
with lag type of phase-shift network is
1
f=
1
b = 2p LC
29
13. For a Hartley Oscillator, frequency of oscillation is
4. The oscillation frequency of phase-shift oscillator
using lead type of phase-shift network is 1
w=
1 (L1 + L2 )C
w=
6RC
14. For a Harley oscillator, the magnitude of the
5. The feedback factor (b) of phase-shift oscillator feedback factor b is
L
using lead type of phase-shift network is
b = 2
1 L1
b =
29
15. For a Colpitt Oscillator, the oscillation frequency is
6. The oscillation frequency of a buffered lag-type RC
1
phase-shift oscillator is w=
LC1C2 /(C1 + C2 )
3
f= 16. For a Colpitt oscillator, at an oscillation frequency
2pRC
C
7. The minimum value of the amplifier gain for b = 1
sustained oscillations in a buffered lag-type RC C2
phase-shift oscillator is equal to 8.
17. For a Clapp Oscillator, the operating frequency is
8. For lead-type of RC network, the oscillation
frequency is 1 1 1 1 1
f= + +
2p L C1 C2 C3
1
f=
2p 3RC 18. For a crystal oscillator, the series resonant fre-
quency is
9. For Twin-T Oscillator, the oscillation frequency is
1
1 fS =
w= 2p LCS
RC
19. For a crystal oscillator, the parallel resonant
10. For a Wien bridge Oscillator, the frequency of
frequency is
oscillation is
1 1
w= fP =
R1C1R2C2 2p LCP

SOLVED EXAMPLES
1. The circuit shown in the following figure employs +V

positive feedback and is intended to generate
sinusoidal oscillation. If at a frequency fo, |B(f)| = RFC 0.1 F
|Vf(f)/Vo(f)| = 1/6 and B(f) =0, then to sustain 10 k
oscillation at this frequency Output
0.1 F
0.01 F
R2
Q1 1 nF
R1 10 k 0.1
1 k F
10 H
+ +
0.1 F
Network V(f)
+ B(f) Solution. The oscillator is an LC oscillator and
Vf(f) has the configuration of Clapp oscillator with an
additional capacitor in the inductor leg.
Ans. (b)
3. What is the frequency of oscillations for the
oscillator circuit shown in the figure depicted in
(a) R2 = 5R1 (b) R2 = 6R1 Question 2?
(c) R2 = R1/6 (d) R2 = R1/5
(a) 1.32 MHz (b) 1.58 MHz
Solution. Applying KCL at the inverting input of (c) 1.79 MHz (d) 1.68 MHz
the opamp, we get
Solution. The frequency of oscillations is given by
B(f )Vo (f ) 0 B(f )V o (f ) V o (f )
+ =0
R1 R2 1
f=
2p LC
Therefore,
B(f ) B(f ) 1 In this case, C is given by

+ =0
R1 R2
1 1 1 1
=
+
+
Substituting the value of B(f) as 1/6, we get C 0.01 10 6
0.1 10 6
1 109
R2 = 5R1
which gives
Ans. (a)
C = 0.0009 F
2. Refer to the oscillator circuit shown in the following
figure. Which oscillator configuration is this? Therefore,
(a) Hartley oscillator 1
(b) Clapp Oscillator f= = 1.68 MHz
(c) Colpitts oscillator 2 10 106 0.0009 106
(d) Armstrong oscillator Ans. (d)

1. For the twin-T oscillator shown in the following figure, That is, the changed value of frequency is
what is the oscillation frequency (Hz) if all compo- 1.592 103
nent values in the twin-T network are doubled? = 398 Hz
4
Ans. (398)
2. Refer to the Armstrong oscillator circuit shown
in the following figure. What is the oscillation
+V
frequency (in Hz) if the loaded Q-factor of the tank
circuit were given to be 5?
+
+V

RFC
0.1 F 0.1 F
10 k
V
R R
3.6 H
0.1 F
0.1 F
C C 10 k
1 k
10 k 0.01 F
The frequency of oscillations without taking

Solution. The oscillation frequency is given by Q-factor into account is
1 1
f=
2p LC
f=
2pRC
1
If we compare the given twin-T network with the = = 265.3 kHz
standard form of twin-T, we shall find that 2p 3.6 106 0.1 106
R = 2 10 103 = 20 k The Q-factor of the tank circuit is 5. The frequency

of oscillation will reduce by a factor equal to
0.01 106
and C = = 0.005 F Q2
2
Therefore, Q2 + 1
1 Therefore, the new frequency of oscillations will be

f= 6
= 1.592 kHz
2p 20 10 0.005 10
3
52
265.3 103 = 260 kHz = 260, 000 Hz
When all component values are doubled, the 52 + 1
oscillation frequency will be reduced to one-fourth. Ans. (260000)
PRACTICE EXERCISE
1. Pick the odd-one out. 2. If in an oscillator, the amplifier portion is a two-

stage common-emitter configuration, what should
(a) Hartley oscillator(b) Colpitts oscillator
be the phase-shift to be introduced by the feedback
(c) Clapp oscillator (d) Wein-bridge oscillator
network at the oscillation frequency for sustained
(1 Mark)
oscillations?

p 100 k
(a) rad (b) 2 rad
2
p +V
(c) 3p rad (d) rad
3 (1 Mark) R

3. According to the frequency stability criterion, Output
+
(a) higher df/dw means the higher frequency
stability V
(b) higher df/dw means the lower frequency 0.1 H 1 H
stability
(c) frequency stability is independent of df/dw L2 L1
(d) higher value of Q-factor means the lower 1 nF
frequency stability
(1 Mark)
C
4. Refer to the RC oscillator circuit shown in the (a) 3.8 MHz (b) 4.2 MHz
following figure. (c) 4.8 MHz (d) 3.2 MHz
(1 Mark)
R3 R4 =2.2 k
7. For the Hartley oscillator depicted in the figure shown
in Question 6, what is the maximum acceptable value
of resistance (R) for oscillations to start?
+V
(a) 100 k (b) 10 k (c) 1 k (d) 100
(1 Mark)
8. The following figure shows a buffered RC oscillator
+
R1 =1 k circuit. What is the frequency of oscillation?
V 1.2 M
C1 =0.1 F
RG +V +V
+ 10 k
A1 +

A2
10 nF

C2 R2 V V
1 nF 100 k
+V 10 k
+V
10 k +
10 k + A3
A4
What is the operating frequency? 10 nF
10 nF 10 nF V
(a) 1.592 kHz (b) 2.452 kHz V
(c) 1.912 kHz (d) 3.189 kHz
(1 Mark)
(a) 1.431 kHz (b) 1.592 kHz
5. For the RC oscillator circuit shown in the figure
(c) 1.612 kHz (d) 1.932 kHz
depicted in Question 4, what is the preferred value
(1 Mark)
of R3?
(a) 200K (b) 300K 9. For the buffered RC oscillator circuit depicted in
(c) 400K (d) 100K the figure shown in Question 8, what is the value
of resistance RG?
(1 Mark)
(a) 290 k (b) 220 k
6. Refer to the Hartley oscillator shown in the (c) 300 k (d) 330 k
following figure. What is the operating frequency? (2 Marks)

10. The following figure shows the circuit diagram of a 13. The minimum value of b of a transistor to be used
quadrature oscillator. The peak amplitude of the signal in three sections RC phase-shift oscillator is
appearing at the output of A1 is 2V. What is the oper-
(a) 44.5 (b) 33.9
ating frequency of the oscillator shown in the figure?
(c) 54.9 (d) 65.1
C1 4.7 nF (1 Mark)
+V 14. The m of the FET used in a phase-shift oscillator

10 k
should be
R1 A1
+ (a) less than 12 (b) greater than 29
10 k R2
V +V (c) greater than 89 (d) less than 89
+ (1 Mark)
C2 A2 15. Refer to the oscillator shown in the following figure.
4.7 nF
Does the given oscillator circuit resemble any stan-
V dard oscillator configuration?
R3 C3
10 k +V
4.7 nF
RFC
(a) 4.512 kHz (b) 3.386 kHz R1
(c) 3.214 kHz (d) 4.125 kHz
C3
0.01 F
(2 Marks)
C1
11. For the case discussed in Question 10, what is the L R1
10 H
phase-difference between the signals appearing at Q1
C4 R2
R3 0.1 F
the outputs of opamps A1 and A2?
C2
(a) 90 (b) +90
(c) 180 (d) 0
(1 Mark)
12. For the case discussed in Question 10, what is the (a) Hartley oscillator (b) Clapp Oscillator
peak amplitude of the signal at the output of A2? (c) Colpitts oscillator (d) Armstrong oscillator
(1 Mark)
(a) 2 V (b) 3 V
(c) 2V (d) 3V
(2 Marks)
1. Refer to the oscillator shown in Question 15 above. R1

What is the frequency of oscillations (in kHz)?
(1 Mark) +V
R2=22 k
2. Refer to the oscillator shown in Question 15 above.
What is the required minimum value of amplifier
+ Output
gain?
(1 Mark)
V
3. Refer to the Colpitt oscillator circuit shown in the
following figure. What is the oscillation frequency C2=680 pF C1=220 pF
(in kHz)?
L=1 mH
(1 Mark)

4. For the Colpitt oscillator circuit shown in Question 3,

what is the minimum value of R1 required (in kilo +V
ohms) for sustained oscillations?
(1 Mark) +

5. Refer to the twin-T oscillator shown in the follow-
ing figure. What is the frequency of output signal V
(in kHz)? R R
C C
10 k 0.01 F
(2 Marks)
1. (d) Therefore, the minimum value of required gain is

1.02. That is,
2. (b) A two-stage common-emitter amplifier provides R
a phase-shift of 2 rad.Therefore, the feedback 1 + 4 = 1.02
R3
network must not introduce any more phase-shift
R4
or introduce phase-shift equal to multiples of 2 = 0.02
radians in order to satisfy the Barkhausen criterion R3
for sustained oscillations. Therefore,
2.2 103
3. (a) R3 = = 110 k
0.02
4. (a) It is a Wien bridge oscillator. The operating Since the required gain has to be slightly greater
frequency is given by than 1.02, the preferred value of R3; therefore,
1 should be slightly less than 110 k. Thus, from the
w= given options R3 is chosen to be 100k.
R1C1R2C2
6. (c) The frequency of oscillations is given by
Therefore,
1
f=
w=
1
= 104 2p LC
6 9
1 10 0.1 10
3
100 10 1 10
3
L = L1 + L2 = 1.0 106 + 0.1 106 = 1.1 H
1 4 and C = 1 nF
= 10 rad/s
6
100 103 1 10and
9
hence Therefore,
1
w 104 f= = 4.8 MHz
f= = Hz = 1.592 kHz 2p 1.1 106 1 109
2p 2p
5. (d) The attenuation provided by feedback network 7. (b) The feedback factor is
is given by L2 0.1 106
= = 0. 1
R2C1 L1 1.0 106
b = Therefore, the minimum required gain is 10. Now,
R1C1 + R2C2 + R2C1
the gain is
100 103 0.1106 100 103
=
103 0.1106 + 100 103 109 + 100 103 0.1106
R
Therefore maximum value of R is
102 1 105
= 4 4 2
= = 104 = 10 k
10 + 10 + 10 1.02 10

8. (b) The circuit shown is that of Bubba oscillator. It Substituting the values of R and C, we get
employs four RC sections isolated from each other 1
f= = 3.386 kHz
with opamp buffers. The frequency of oscillation is 2p 10 10 4.7 109
3
given byf = 1/2pRC since each of the four sections
contributes a phase-shift of 45. Therefore, 11. (a) The transfer function from output of A1 to
1 junction of R2C2 is given by
f= = 1.592 kHz
2p 10 103 10 109 1
1 + R2C2s
9. (a) The quadrature outputs may be taken from the
outputs of opamps A2 and A4. Outputs of A2 and At w = 1/R2C2, it produces a phase-shift of 45.
A4 will be 90 apart. Each RC section provides The transfer function from junction of R2C2 to
attenuation of (1/ 2 ) at the operating frequency. the output of A2 is given by
Since the RC sections are buffered, the attenuation 1 + R3C3s
provided by feedback network will be R3C3s
1
4
1
= 4 At w = 1/R3C3, it produces a phase-shift of 45.
2 Since R2C2 = R3C3, the phase-shift from output of
Therefore, the gain of the amplifier should be A1 to the output of A2 will be 90.
slightly more than 4. This implies that
12. (c) It is clear from the transfer functions mentioned
1.2 106
>4 above that the two networks, respectively, provide
RG attenuation and gain of 1/ 2 and 2. Therefore, the
peak amplitude of signal at junction of R2C2 is 2/ 2 =
Therefore, the input resistance RG should be slightly
less than 300k. That is 290k is the correct choice. 2 V and that at the output of A2 is 2 2 = 2V.
10. (b) The frequency of oscillation is given by 13. (a)
1 14. (b)
f=
2pRC 15. (c)
1. The feedback circuit in this case is also a tank The frequency of oscillations can be computed from
circuit comprising of a pair of series connected 1
capacitors C1 and C2 and an inductor L. f=
Also, the amplifier has been wired in common base 2p LC
configuration. Note that the base terminal is effec- where
tively grounded for AC signal through capacitor C4. C1 C2
The output in this case appears across series C1 + C2
combination of C1 and C2. It appeared across C1 only
Now,
in the case of Colpitt oscillator configured around
common emitter amplifier. The feedback signal 0.01 10 6 0.1 106
C= = 0.009 F
appears across C2 in both cases. 0.01 106 + 0.1 106
The feedback factor in this case is therefore given by
Therefore,
C1 C2 / ( C1 + C2 )
b=
1
= 530.5 kHz
6
C2 2p 10 10 0.009 106
which simplifies to Ans. (530.5)
C1 2. The feedback factor is
C1 + C2
0.01 10 6
b=
1
6 6
=
0.01 10 + 0.1 10
The required minimum value of amplifier gain is 11
therefore
Also, the required minimum value of the amplifier
C1 + C2 gain is 11.
C1 Ans. (11)

680 1012
3. The frequency of oscillation in a Colpitt oscillator C2
is given by = = 3.09
C1 220 1012
1 R1
f= = 3.09
C C2
2p 1 L
R2
C1 + C2 R1 = R2 3.09 = 68 k
Ans. (68)
C1 = 220 pF and C2 = 680 pF, L = 1 mH. 5. The operating frequency (f) is given by
1
f =
Therefore,
2pRC
1 If we compare the given twin-T network with the
f=
220 1012 680 1012 standard form of twin-T, we shall find that
2p 1 10
13
220 1012 + 680 1012 R = 2 10 103 = 20 k

= 390.37 kHz 0.01 106
and C = = 0.005 F
Ans. (390.37) 2
Therefore,
4. Amplifier gain should be equal to or greater than 1
f= = 1.592 kHz
C2/C1. Therefore, minimum value of gain is equal 2p 20 10 0.005 106
3
to (C2/C1). Ans. (1.592)
1. The oscillator circuit shown in the following figure 2.1 k

has an ideal inverting amplifier. Its frequency of 1 k
oscillation (in Hz) is
Vo
+
1 k
1 k
C C C
Solution. Let the voltage at the non-inverting input
R R R of the opamp be Vi. Let the capacitor be denoted as
C and both the 1k resistors as R. Applying KCL
at the non-inverting input of the opamp, we get
Vi Vi Vi Vo
R 1 jw C R + (1 jw C )
(GATE 2003: 2 Marks) + + =0
1 1
(a) (b) On solving the above equation, we get
2p 6RC 2pRC
Vo jw C 1
1 1 = 2 2 + R2 + 3
(c) (d) Vi R w C
6RC 6 (2pRC )
Ans. (a) For oscillations to occur, imaginary part should be
zero. Therefore,
jw C
2. The value of C required for sinusoidal oscillations
1
of frequency 1 kHz in the circuit shown in the 2 2 + R2 = 0
following figure is R w C
1 Hence for oscillations to occur,
(a) (b) 2 F 1
1 1
2p C= = 3 = mF
1 wR 2 p 10 10
3
2p
(c) F (d) 2p 6 F
2p 6
Ans. (a)

CHAPTER 21
FUNCTION GENERATORS AND WAVE-SHAPING CIRCUITS
This chapter discusses the multivibrator circuits and the 555 timer based circuits.
21.1 MULTIVIBRATORS multivibrator is identical to that of a flipflop. Figure 21.1(a)

shows the basic bistable multivibrator circuit. This is the
fixed bias type of bistable multivibrator. Other configu-
A multivibrator such as the familiar sinusoidal oscil- rations are self-bias type and the emitter-coupled type.
lator is a circuit with regenerative feedback with the However, operational principle of all types is the same.
difference that it produces a pulsed output. There are In the circuit arrangement shown in Fig. 21.1(a), it
three basic types of multivibrator circuits. These include can be proved that both the transistors (Q1 and Q2)
bistable multivibrator, monostable multivibrator and cannot be simultaneously ON or OFF. If Q1 is ON,
astable multivibrator. the regenerative feedback ensures that Q2 is OFF and
when Q1 is OFF, the feedback drives transistor Q2 to
21.1.1 Bistable Multivibrator the ON state. Whenever there is a tendency of one of
the transistors to conduct more than the other, it will
A bistable multivibrator circuit is the one in which both end up with that transistor to saturation and driving
LOW and HIGH output states are stable. Irrespective of the other transistor to cut-off. Now, if we take output
the logic status of the output, LOW or HIGH, it stays from Q1 collector, it will be LOW (= VCE1(sat)) if Q1 was
in that state unless a change is induced by applying an initially in saturation. If we apply a negative going trigger
appropriate trigger pulse. The operation of a bistable to Q1-base to cause a decrease in its collector current,

470 Chapter 21: Function Generators and Wave-Shaping Circuits
a regenerative action would set in, which would drive Q2 bistable multivibrator circuit shown in Fig. 21.1(a) with
to saturation and Q1 to cut-off. As a result, output goes the Schmitt trigger circuit shown in Fig. 21.2, we find that
to HIGH (= +VCC) state. The output will stay HIGH till coupling from Q2-collector to Q1-base in case of bistable
we apply another appropriate trigger to initiate a transi- multivibrator circuit is absent in case of Schmitt trigger
tion. Figure 21.1(b) shows the relevant timing diagrams. circuit. Instead, resistance Re provides the coupling.
+V
+VCC CC
VCC
IIc1 IIc2
c1 C C c2 C
C11 C22 RC1 RC2
R
RC1 R
C1 RC2
C2 Vo
V = Vc1 R R V = Vc2 R2
Vo1
o1 = Vc1 R11 R22 Vo2
o2 = Vc2 Vin
Q1 Q2
Q
Q11 Q
Q22
R
R33 R
R44
Trigger Trigger RE R1
Trigger Trigger
I/P 1
I/P 1 I/P 22
I/P

VVBB
BB
Figure 21.2| Schmitt trigger.

(a)
(a)
Trigger
Trigger
I/P Schmitt trigger circuit shown in Fig. 21.2 exhibits
I/P 11 tt
hysteresis and Fig. 21.3 shows the transfer characteristics
of the Schmitt trigger circuit. The lower trip point (VLT)
Q and upper trip point (VUT) of these characteristics are,
Vc1 QQ11-ON
-ON Q22-ON
Q -ON Q11-ON
Q -ON Q22-ON
Q -ON respectively, given by Eqs. (21.1) and (21.2):
V -OFF
c1 Q22-OFF
Q
Q11-OFF
-OFF Q
Q22-OFF
-OFF Q
Q11-OFF
-OFF
VCC RE
VLT = + 0.7 (21.1)
tt (RE + RC1 )
V
Vb1
b1 VCC RE
tt VUT = + 0.7 (21.2)
(RE + RC2 )
V
Vc2 Vo
c2
VCC
tt
V
Vb2
b2
tt
VCE(sat) 0 Vin
VLT VUT
(b)
Figure 21.3| Transfer characteristics of the Schmitt
(b)
Figure 21.1| (a) Bistable multivibrator;
trigger circuit.
(b)Timing waveforms for the bistable
multivibrator of Fig. 21.1(a).
21.1.2 Schmitt Trigger 21.1.3 Monostable Multivibrator
Schmitt trigger circuit is a slight variation of the bistable In a monostable multivibrator (also known as mono-
multivibrator circuit shown in Fig. 21.1(a). Figure 21.2 shot), one of the states is stable and the other is
shows the basic Schmitt trigger circuit. If we compare the quasi-stable. The circuit is initially in the stablestate.

21.1 MULTIVIBRATORS 471
It goes to the quasi-stable state when appropri- +VCC

ately triggered. It stays in the quasi-stable state for
a certain time period, after which it comes back to RC1 R RC2
C1
the stable state. Figure 21.4 shows the basic monos-
table multivibrator circuit. The moment we apply a
C
trigger, Q2 goes to cut-off and Q1 starts conducting.
Vo
But now there is a path for capacitor (C) to charge R1
from VCC through R and the conducting transistor.
The polarity of voltage across C is such that Q2-base Q2
potential rises. The moment Q2-base voltage exceeds Q1
R2
the cut-in voltage, it turns Q2 ON, which due to cou-
pling through R1 turns Q1 OFF. And we are back
to the original state, the stable state. Figure 21.5 Trigger VBB
shows the relevant timing diagrams. Whenever, we I/P
trigger the circuit into the other state, it does not Figure 21.4| Monostable multivibrator.
Trigger
pulses
+VP
t
Vc1 Q2-ON Q1-ON Q2-ON Q1-ON Q2-ON
Q1-OFF Q2-OFF Q1-OFF Q2-OFF Q1-OFF
+VCC
t
Vb1 T
+VP
Vc2
+VCC
t
Vb2
VCC
Figure 21.5| Timing waveforms of monostable multivibrator.
stay there permanently and returns back after a time the other state called quasi-stable state. The width of
period that depends upon R and C. Larger the time the quasi-stable state is given by Eq. (21.3):
constant (RC), larger is the time for which it stays in T = 0.693 R C (21.3)

21.1.4 Astable Multivibrator The ON time (T2) of transistor Q1 which is equal to the
OFF time of transistor Q2, which is given by
In case of an astable multivibrator, neither of the two
states is stable. Both output states are quasi-stable. The T2 = R1C1 ln 2 = 0.694R1C1 (21.4)
output switches from one state to the other and the circuit
functions like a free running square wave oscillator. Similarly, the ON time (T1) of transistor Q2 which is equal
Figure 21.6 shows the basic astable multivibrator circuit. to the OFF time of transistor Q1 is given by Eq. (21.5):
The value of resistors R1 and R2 are typically 10 times the
value of RC1 and RC2, respectively. The time periods for T1 = R2C2 ln 2 = 0.694R2C2 (21.5)
which the output remains LOW and HIGH depends upon
R2C2 and R1C1 time constants, respectively. For R1C1=
The total time period of the wave is T which is given by
R2C2, the output is a symmetrical square waveform.
Eq. (21.6):
Figure 21.7 shows the relevant timing diagrams.
VCC T = T1 + T2 = 0.694(R1C1 + R2C2 ) (21.6)
RC1 R1 R2 RC2 For R1 = R2 = R and C1 = C2 = C, the time period is

equal to
Vo = VC2
C1 C2 T = 1.388RC
Q1 Q2 and the frequency (f) is given by
1
f=
Figure 21.6| Astable multivibraor.
1.388RC
Q1-ON Q2-ON Q1-ON Q2-ON Q1-ON Q2-ON

Vc2 Q -OFF Q1-OFF Q2-OFF Q1-OFF Q2-OFF Q1-OFF
2
t
Vb2 T1 T2
T
Vc1
t
Vb1
Figure 21.7| Timing waveforms of astable multivibrator.

21.2 555 TIMER 473
21.2 555 TIMER the charging time of capacitor C from +V CC /3 to

+2V CC /3 and discharging time of the capacitor C
from +2V CC /3 to +V CC /3 respectively. These are
The IC timer 555 is one of the most commonly used given by Eqs. (21.7) and (21.8), respectively:
general purpose linear integrated circuits. Figure 21.8
shows the internal schematic of timer IC 555. It comprises HIGH-state time period, THIGH = 0.69 (R1 + R2 ) C
of two opamp comparators, a flipflop, a discharge tran-
(21.7)
sistor, three identical resistors and an output stage.
The resistors set the reference voltage levels at the non-
inverting input of the lower comparator and invert- LOW-state time period, TLOW = 0.69 R2 C (21.8)
ing input of the upper comparator at +VCC/3 and
+2VCC/3, respectively. Outputs of two comparators feed The relevant waveforms are shown in Fig. 21.9(b).
SET and RESET input of the flipflop and thus decide The time period (T) and frequency (f) of the output
the logic status of its output and subsequently the final waveform are, respectively, given by Eqs. (21.9) and
output. The flipflops complementary outputs feed the (21.10), respectively:
output stage and the base of the discharge transistor.
This ensures that when the output is HIGH, the discharge Time period, T = 0.69 (R1 + 2R2 ) C (21.9)
transistor is OFF and when the output is LOW, the
discharge transistor is ON.
1
Frequency, f = (21.10)
0.69 (R1 + 2R2 ) C
21.2.1 Astable Multivibrator Using Timer
IC 555 Remember that when the astable multivibrator is
powered, first cycle HIGH-state time period is about
Figure 21.9(a) shows the basic 555 timer based 30% longer as the capacitor is initially discharged and
astable multivibrator circuit. The HIGH-state and it charges from 0 to 2VCC/3 rather than from +VCC/3
LOW-state output time periods are governed by to +2VCC/3.
VCC (Pin-8)
Vref (int)
5 k
Control 2V Reset (Pin-4)
3 CC
(Pin-5)
Threshold +
(Pin-6)
5 k FF
1V
3 CC +
Trigger
(Pin-2)
Discharge
(Pin-7)
5 k Output
Output (Pin-3)
stage
Discharge
transistor
Ground (Pin-1)
Figure 21.8| Internal schematic of timer IC 555.

Vo
+VCC
tHIGH tLOW
R1
8 4 3 t
7 Vo 0
Vc
R2 555
2,6 5 1 2V
3 CC
C 0.01 F 1V
3 CC
t
(a) (b)
+VCC
+VCC
R1 4,8 3 Vo
D
7 8 4 3 Vo 7
555
D R2 555 R2 R1
2,6 5 1 2,6
5 1
C 0.01 F 0.01
C
F
(c) (d)
Figure 21.9|(a) Astable multivibrator. (b) Relevant waveforms for the astable multivibrator in Fig. 21.9 (a). (c)
(d)Modified astable multivibrator circuits.
In case of the astable multivibrator circuit shown in 21.2.2 Monostable Multivibrator Using Timer
Fig. 21.9(a), HIGH-state time period is always greater than IC 555
the LOW-state time period. Figure 21.9(c) and (d) show two
modified circuits where HIGH-state and LOW-state time Figure 21.10(a) shows the basic monostable multivibrator
periods can be chosen independently. For the astable multi- circuit configured around timer 555. A trigger pulse is
vibrator circuits shown in Fig. 21.9(c) and (d), the two time applied to terminal 2 of the IC, which should initially be
periods are given by Eqs. (21.11) and (21.12). kept at +VCC. A HIGH at terminal 2 forces the output to
LOW-state. A HIGH-to-LOW trigger pulse at terminal 2
HIGH-state time period = 0.69 R1 C (21.11) holds the output in the HIGH-state and simultaneously
allows the capacitor C to charge from +VCC through
LOW-state time period = 0.69 R2 C (21.12) R. When the capacitor voltage exceeds +2VCC/3, the
output goes back to the LOW-state. Every time, the
For R1 = R2 = R, timer is appropriately triggered, the output goes to
T = 1.38 R C HIGH-state and stays there for a time period taken by
capacitor C to charge from 0 to +2VCC/3. This time
1 period, which equals the monoshot output pulse width,
f= (21.13)
1.38 R C is given by Eq. (21.14):

21.2 555 TIMER 475
+VCC
Trigger
input
t
+VCC
Vo T
R
8 4
6,7 3 Vo Output
Vc C 555 t
Trigger 2 Vc
5 1
2 V
3 CC
0.01
mF
t
(a) (b)
Figure 21.10| (a) Monostable multivibrator circuit configured around timer IC 555 and (b) relevant waveforms of
the circuit shown in fig. 21.10 (a).
T = 1.1 R C (21.14) Figure 21.11(a) shows the monoshot configuration that

can be triggered on the trailing edges of the trigger wave-
Figure 21.10(b) shows the relevant waveforms for the form. Figure 21.11(b) shows relevant waveforms.
circuit shown in Fig. 21.10(a). The pulse width of the Figure 21.12(a) shows the monoshot configuration
trigger input should be less than the HIGH-time of the that can be triggered on the leading edges of the trigger
monoshot output. Also, it is often desirable to trigger a waveform. Figure 21.12(b) shows relevant waveforms.
monostable multivibrator either on the trailing (HIGH- For the circuits shown in Figs. 21.11 and 21.12 to
to-LOW) or leading edges (LOW-to-HIGH) of the trig- function properly, values of R1 and C1 for the differen-
ger waveform. In order to achieve that, we shall need an tiator should be chosen carefully. Firstly, differentiator
external circuit between the trigger waveform input and time constant should be much smaller than the HIGH-
terminal 2 of timer 555. The external circuit ensures that time of the trigger waveform for proper differentiation.
terminal 2 of the IC gets the required trigger pulse cor- Secondly, differentiated pulse width should be less than
responding to the desired edge of the trigger waveform. the expected HIGH-time of the monoshot output.
VCC
R1 D R
4,8
2 3 Vo VCC
Trigger Trigger
I/P C1
555 6,7 I/P
0
+0.7
C VCC
1 5
0.01 F At
pin-2
0
(a) (b)
Figure 21.11| (a) Timer IC 555 monoshot configuration triggered on the trailing edges and (b) relevant waveforms.

VCC VCC
R3 Trigger
2 4 8 R I/P
C1 R2 0
Trigger VCC
I/P 555 6,7 After
Q differentiator
0
0.7
R1 D 3 Vo
1 5
C At Pin-2 VCC
0.01 F
0
(a) (b)
Figure 21.12| (a) Timer IC 555 monoshot configuration triggered on the leading edges; (b) relevant waveforms.
IMPORTANT FORMULAS
1. For a Schmitt trigger circuit, the lower trip point 5. For an astable multivibrator, the output frequency is
(VLT) is
VCC Re
1
f=
VLT = + 0.7 1.388RC
(Re + RC1 )
6. For an astable multivibrator using timer IC 555:
2. For a Schmitt trigger circuit, the upper trip point
(VUT) is HIGH-state time period, THIGH = 0.69(R1 + R2 )C
VCC Re
VUT =
(Re + RC2 )
+ 0.7 LOW-state time period, TLOW = 0.69 R2 C
3. For a monostable multivibrator, the width of the Time period, T = 0.69 (R1 + 2R2 ) C
quasi-stable state is
1
Frequency, f =
T = 0.693RC 0.69 (R1 + 2R2 ) C
4. For an astable multivibrator, the output time period is
7. For a monostable multivibrator using timer IC 555:
T = 1.388RC
Output pulse width T = 1.1RC
SOLVED EXAMPLES
1. In the case of an IC timer based monostable to generate the desired output pulse of the given
multivibrator circuit, the requirement for the width. In the case if the condition is not met, the
trigger pulse appearing at trigger terminal of IC output pulse does not go low after being triggered
timer is the following: high by the input trigger pulse. It goes low when the
input trigger pulse goes back to its original state.
(a) Trigger pulse width should be equal to the
Ans. (b)
intended output pulse width
(b) Trigger pulse width should be less than the 2. A Schmitt trigger circuit is a type of
(a) Bistable multivibrator circuit
(c) Trigger pulse width should be greater than the
(b) Monostable multivibrator circuit
(c) Astable multivibrator circuit
(d) None of these.
(d) None of these
Solution. In the case of IC timer monostable mul-
tivibrator circuit, the trigger pulse appearing at Solution. The Schmitt trigger circuit is a slight
trigger terminal of IC timer should be less than the variation of the bistable multivibrator circuit. The
intended output pulse width for the multivibrator coupling between the collector terminal of one

SOLVED EXAMPLES 477
t ransistor to base terminal of the other transistor (a) S1 only

present in bistable multistable multivibrator is (b) S2 only
absent in case of Schmitt trigger circuit. Instead, a (c) Both S1 and S2
resistor provides the coupling. (d) Both S1 and S2 are incorrect.
Ans. (a)
Solution. For an astable multivibrator shown in
3. Refer to the astable multivibrator circuit shown the given figure,
in the following figure. It is given that VCC = +5 THIGH = 0.69 (R1 + R2 ) C
V, R1 = 2R2. If the LOW-state time period of the
output waveform were 1 ms, which of the following For an astable multivibrator shown in the given
statements is correct? figure,
TLOW = 0.69 R2 C
+VCC
Given the TLOW = 1 ms and R1 = 2R2. Therefore,
R1 THIGH = 3 ms
8 4 3 Vo Therefore, the time period is
7
R2 555 T = 0.69 (R1 + 2R2 ) C = 4 ms
2,6 5 The duty cycle is

1
THIGH 3 103
0.01 F
= = 0.75
3 103 + 1 103
C
THIGH + TLOW
Hence, both statements S1 and S2 are correct.

Ans. (c)
S1: Time period of the output waveform is 4 ms.
S2: Duty cycle of the output waveform is 0.75.
1. Refer to the monostable multivibrator circuit The trigger waveform is a symmetrical one; it has
shown in the following figure. Trigger terminal HIGH and LOW time periods of 50 s each. Since
(pin 2 of the IC) is driven by a symmetrical pulsed the LOW-state time period of the trigger waveform
waveform of 10 kHz. What is the frequency of the is less than the expected output pulse width, it
output waveform (in Hertz)? can successfully trigger the monoshot on its trailing
VCC edges. Since the time period between two successive
10 k trailing edges is 100 s and the expected output
pulse width is 110 s; therefore only alternate
trailing edges of trigger waveform shall trigger the
4,8
monoshot. The frequency of output waveform is
6,7
3
Output 10
555 kHz = 5 kHz = 5000 Hz
Trigger 2
input 2 Ans. (5000)
5 1 2. For the case discussed in Question 1, what is the
0.01 duty cycle of the output waveform?
F 0.01 (a) 0.5 (b) 0.75 (c) 0.25 (d) 0.55
F
Solution. The time period of output waveform is
1
s = 200 s
5 103
Solution. The frequency of trigger waveform is 10 kHz.
Therefore, the time period between two successive Therefore, the duty cycle of output waveform is
leading or trailing edges is 100 s.
110 106
The expected pulse width of monoshot output is = 0.55
8 200 106
1.1RC = 1.1 10 10 4
= 110 s Ans. (0.55)

PRACTICE EXERCISE
1. What is the hysteresis voltage for the Schmitt (c) to provide ac coupling
trigger circuit shown in the following figure? (d) All of these
(1 Mark)
90 k 3. A retriggerable monostable multivibrator is
10 k
+15 V designed for an output pulse width of 400 s. If it
were fed with eleven trigger pulses with successive
Vo trigger pulses separated by 10 s, the output pulse
+ + width would be
+
2V 15 V (a) 100 s (b) 400 s

VS (c) 500 s (d) 200 s
(1 Mark)
4. A pulsed waveform shown in the following figure (b)

is applied to the RESET terminal of astable mul-
(a) 3.6 V (b) 2 V (c) 3 V (d) 4 V tivibrator circuit shown in the following figure (a).
What is the output waveform?
(2 Marks)
(a) Figure (i)
2. The commutating capacitors are used in a bistable
(b) Figure (ii)
multivibrator
(c) Figure (iii)
(a) for improving the speed of response (d) None of these
(b) for filtering out spurious noise (2 Marks)
+VCC
14.5 k
7 8 3 Vo
14.5
k 555
2,6 4
5 1
0.01 F
0.01 F
1ms 1ms
(a) (b)
100 s
100 s
1ms 1ms
(i)
100 s
1ms 1ms 1ms

(ii) (iii)

5. The monostable configuration shown in the follow- (c) pin to pin replacement of 555
ing figure was designed by someone to generate a (d) a dual timer containing two independent 555
pulse whenever it was triggered by the available timers
trigger pulse as shown. The circuit did not seem to (1 Mark)
work. What would be wrong with the circuit?
8. What are the upper and the lower trip points for
(a) T rigger pulse width appearing at pin 2 of the IC the Schmitt trigger circuit shown in the following
is greater than the expected output pulse width figure?
(b) Trigger pulse width appearing at pin 2 of the
IC is less than the expected output pulse width 90 k
(c) Trigger pulse width appearing at pin 2 of the
IC is equal to the expected output pulse width
+15 V
(d) The circuit is wrongly designed. 10 k
(2 Marks) +
+VCC Vo
+
6V
1 k VS 15 V
8 4
6,7 5V
3 Vo
1 F 555
2
5 1 (a) 0.6 V and 0.5 V (b) 0.5 V and 0.6 V
10ms (c) +15 V and 15 V (d) +1.5 V and 1.5 V
0.01 F (2 Marks)
9. In a conventional astable multivibrator, the timing
capacitor charges and discharges between
6. For the comparator circuit shown in the following (a) 0 and VCC/3 (b) 0 and 2/3VCC
figure, which of the following statements is true? (c) 1/3VCC and 2/3VCC (d) 0 and VCC
(1 Mark)
S1: For Vi > Vref, Vo = +Vz and for Vi < Vref, Vo
= Vz 10. For the bistable multivibrator shown in the following
figure, which of the following statements is/are true?
S2: For Vi > Vref, Vo = +V and for Vi < Vref, Vo
= V
+VCC
+V
IC1 IC2
+ C1 C2
Vo RC1 RC2
+
+ VZ
Vi V Vo1= VC1 R1 R2 Vo2= VC2
Vref
VZ

Q1 Q2
R3 R4
(a) S1
(b) S2 Trigger Trigger
(c) Sometimes S1 and sometimes S2 I/P 1 I/P 2
(d) None of these VBB
(2 Marks)
7. The timer IC 556 is nothing but
S1: Whenever there is a tendency of one of the
(a) an improved version of timer IC 555 transistors to conduct more than the other, it will
(b) another timer IC like 555 made by another end up with that transistor going to saturation and
company driving the other transistor to cut-off.

S2: Both of the output states are stable and 14. Refer to the circuit shown in the figure depicted in
undergo a change only when a transition is induced Question 13. Assume the diode D to be ideal. The
by means of an appropriate trigger pulse. High time of the output waveform is given by
(a) S1 (b) S2 (a) 0.4R1C (b) 0.69R1C
(c) Both S1 and S2 (d) None of these (c) 1.1R1C (d) 0.69 (R1 + R2)C
(1 Mark) (1 Mark)
11. Refer to the circuit shown in the following figure. 15. Refer to the circuit shown in the figure depicted in
In the stable state, the voltage at the collector ter- Question 13. Assume the diode D to be ideal. What
minal of transistor Q1 is is the duty cycle of the output waveform?
(a) R2/(R1 + R2) (b) R1/(R1 + R2)
+VCC
(c) R1/R2 (d) 50%
(2 Marks)
RC1 R C1 RC2
16. Refer to the circuit shown in the following figure.
C The value of C1 = 0.01 F, R1 = 10 k, output
Vo pulse width = 50 s. Input waveform is a square
R1 waveform of 10 kHz. At which instants will the
triggering take place?
Q1 Q2
R2 VCC
R3
Trigger VBB R
Trigger 2 4 8
I/P
I/P R2
(a) Nearly zero (b) VCC 555 6,7
C1 Q
(c) VCC/2 (d) None of these
R1 D 3 Vo
(1 Mark) 1 5
C
12. For the circuit shown in the figure depicted in 0.01 F
Question 11, in the stable state, the voltage at the
collector terminal of transistor Q2 is
(a) Nearly zero (b) VCC
(a) It will be triggered on every leading edge (low
(c) VCC/2 (d) None of these
to high) of the input waveform
(1 Mark)
(b) It will be triggered on every alternate leading
13. Refer to the circuit shown in the following figure. edge of the input waveform
Assume the diode D to be ideal. In the free running (c) It will be triggered on every alternate trailing
multivibrator configuration, the timing capacitor edge of the input waveform
charges and discharges during operation between (d) None of these
(1 Mark)
+VCC
R1
7 8 4 Vo 1. For the case discussed in Question 16 above, what

3
is the duty cycle of the output waveform?
D R2 555 (1 Mark)
2,6 5 1 2. For the the case discussed in Question 16 above, what
is the frequency (in kHz) of the output waveform?
C 0.01 F 10 (1 Mark)
k
3. If in the circuit shown in the following figure, R
(a) 0 and VCC/3 (b) VCC/3 and VCC and C were so chosen that every time monoshot
(c) 1/3VCC and 2/3VCC (d) VCC/4 and VCC/2 is triggered, the output pulse width is 150 s. The
(2 Marks) value of C1 = 0.01 F, R1 = 10 k, the output

pulse width = 50 s. The input waveform is a 5. For the figure shown in the following figure, what
square waveform of 10 kHz. What is the frequency is the output voltage in volts at t = 10 s?
of the output waveform (in hertz)? (a) 0 V (b) 10 V
(2 Marks) (c) 25V (d) 50V
VCC (1 Mark)
R3 10 F
R
Trigger 2 4 8
I/P R2
555 6,7 +15V
C1

Q
R1 D 3 Vo
1 5 Vo
C +
0.01 F 15V
2M

ON-time to OFF-time ratio? 50V
(1 Mark)
1. (c) When the output voltage Vo is at positive satu- When the RESET input is LOW, the output is
ration, the voltage at the non-inverting terminal of forced to LOW-state. When the RESET input is
the opamp is given by HIGH, astable waveform appears at the output.
HIGH and LOW time periods of the astable multi-
10 103 90 103
+15 + 2 vibrator are determined as follows:
10 10 + 90 10
3 3
10 10 + 90 10
3 3
HIGH-time = 0.69 14.5 103 0.01 106 =
= 1.5 + 1.8 = 3.3 V 100 s
When the output voltage Vo is at negative s aturation, LOW-time = 0.69 14.5 103 0.01 106 =
the voltage at the non-inverting terminal of the 100 s
opamp is given by The astable output is thus a 5 kHz symmetrical
waveform. Every time RESET terminal goes HIGH
10 103 90 103
15 + 2 for 1.0 ms, five cycles of 5 kHz waveform appear at
10 103 + 90 103
10 10 + 90 10
3 3
the output.
= 1.5 + 1.8 = 0.3 V
5. (a) For the monoshot based on 555 timer to work
Therefore, the hysteresis voltage is properly, the trigger pulse width appearing at pin-2
3.3 0.3 = 3 V of the IC should be less than expected output pulse
width. The output pulse width is 1.1RC = 1.1ms. It
2. (a) is given that the input pulse width is equal to 10 ms.
3. (c) The output pulse width is Therefore, the trigger pulse width appearing at
pin 2 of the IC is greater than the expected output
10 10 s + 400 s = 500 s pulse width. Hence the circuit is not working properly.
4. (a) The circuit shown in the figure (a) is an astable 6. (a)For Vi > Vref, the opamp goes to positive satu-
multivibrator with a 500 Hz symmetrical waveform ration. The output voltage Vo is limited by the top
applied to its RESET terminal. The RESET Zener diode and is equal to + VZ. When Vi < Vref,
terminal is alternately HIGH and LOW for 1.0 ms. the opamp goes to negative saturation. The output

voltage Vo is limited by the bottom Zener diode 13. (d) Refer to the internal structure of 555 IC shown
and is equal to VZ in Fig. 21.8. The 10 k resistor at pin5, changes
the reference voltage at negative input of top com-
7. (d)
parator to VCC/2 and at the positive input of lower
8. (a) The output voltage, when the opamp is in posi- comparator to VCC/4. Therefore the timing capaci-
tive saturation, is given by tor charges between VCC/4 to VCC/2.
Vo = 6 V 14. (a) The HIGH time of the output waveform is
given by the time required by the capacitor C to
The output voltage, when the opamp is in negative charge from VCC/4 to VCC/2 through resistor R1.
saturation, is given by Therefore, tHIGH = 0.4 R1C
Vo = 5 V 15. (b) The LOW time of the output waveform is given
by the time required by the capacitor C to dis-
Therefore, the upper trip point is
charge from VCC/2 to VCC/4 through resistor R2.
Therefore, tLOW = 0.4R2C.
10 103
6 V = 0.6 V
10 103 + 90 103 tHIGH
Duty cycle D =
Therefore, the lower trip point is tHIGH + tLOW
0.4R1C
=
10 10 3 0.4R1C + 0.4R2C
5 V = 0.5 V
10 103 + 90 103 R1
=
R1 + R2
9. (c)
10. (c)
16. (a) The time period of the input waveform is
11. (a) When the output is in stable state, the transis-
100s. The 555 timer is triggered on the leading
tor Q1 is in saturation. Therefore, the voltage at
edges of the input waveform. As the output pulse
the collector terminal of Q1 is nearly zero.
width (50s) is less than the time between leading
12. (b) When the output is in stable state, the transis- edges and the differentiator time constant is small,
tor Q2 is in cut-off. Therefore, the voltage at the therefore, triggering takes place at every leading
collector terminal of Q2 is nearly VCC. edge.

tON
1. Duty cycle D = 100% 4. tON = 150 ms and tOFF = 50 ms
t
ON + tOFF Hence, tON/tOFF = 3
50 106
= 100% = 50% Ans. (3)
100 106
Ans. (50) 5. The capacitor gets charged through a constant
2. The frequency of the output waveform is same as current
that of input waveform. Therefore it is 10 kHz
Ans. (10) 50
A = 25 A
3. Since, the output pulse width is greater than the 2 106
time period of the input waveform and less than
twice the time period of the input waveform. The voltage Vo is the voltage across the capacitor
Therefore, the 555 timer is triggered on alternate is
leading pulses. Therefore, the frequency of output
waveform is 5 kHz or 5000 Hz. It
Vo =
Ans. (5000) C

Therefore, Ans. (25)
25 106 10
Vo = = 25 V
10 106
1. An ideal sawtooth voltage waveform of frequency 9V

500 Hz and amplitude 3 V is generated by charging
30 k
a capacitor of 2 F in every cycle. The charging 4 8
requires (Reset) (Supply)
6 (Threshold)
(a) Constant voltage source of 3 V for 1 ms
(b) Constant voltage source of 3 V for 2 ms (Output) 3
10 k
(c) Constant current source of mA for 1 ms
(d) Constant current source of 3 mA for 2 ms 2 (Trigger)
(GATE 2003: 2 Marks) (Gnd)
1
(Discharge)
7
Solution. A sawtooth waveform is generated 12 k
across the capacitor when it is charged by a
0.01 F
constant current source. The time period of the VC
sawtooth waveform is
1 1
T = = s = 2 ms
f 500
The voltage across the capacitor when it is charged Solution. In the astable multivibrator circuit
by a constant current source (I) is given by based on 555 timer IC, the capacitor voltage VC
varies from VCC/3 to 2VCC/3. Here VCC = 9V,
therefore voltage VC varies between 3V to 6V
dV
I =C
dt Ans. (b)
3. Consider the Schmidt trigger circuit shown below:

Substituting the different values in the equation
above, we get
+15 V
6 3
I = 2 10 = 3 mA 10 k
2 103
Vi
Hence, option (d) is correct. Vo
+
Ans. (d) 10 k
2. An astable mutlivibrator circuit using IC 555 timer
is shown in the following figure. Assume that the 10 k
circuit is oscillating steadily. The voltage VC across 15 V
the capacitor varies between
(a) 3 V to 5 V (b) 3 V to 6 V A triangular wave which goes from 12 V to 12 V

(c) 3.6 V to 6 V (d) 3.6 V to 5 V is applied to the inverting input of the opamp.
(GATE 2008: 2 Marks) Assume that the output of the opamp swings from

+15 V to 15 V. The voltage at the non-inverting R1

input switches between
(a) 12 V and +12 V (b) 7.5 and +7.5 V
(c) 5 V and +5 V (d) 0 V and 5 V
Vo(t)
+
Solution. Let the voltage at the non-inverting
R3
input be V1. Applying KCL at non-inverting input C
end, we get
15 V1 Vo V1 V1 (15)
+ = R2 R4
10 10 3
10 10 3
10 103
Therefore,
Vo
15 V1 + Vo V1 = V1 + 15 or V1 =
3
(a) Only the frequency.
Since Vo swings from 15 V to +15 V, V1 switches (b) Only the amplitude.
between 5 V and +5 V. (c) Both the amplitude and the frequency.
Ans. (c) (d) Neither the amplitude nor the frequency.
4. In the following astable multivibrator circuit, (GATE 2009: 2 Marks)
which properties of vo(t) depend on R2? Ans. (a)

CHAPTER 22
POWER SUPPLIES
Power supplies are often classified as linear power supplies or switched mode power supplies depending upon the nature
of regulation circuit.
22.1 CONSTITUENTS OF A LINEAR unidirectional output. Commonly used rectifier circuits

POWER SUPPLY include the half-wave rectifier, conventional full-wave
rectifier requiring a tapped secondary winding and the
bridge rectifier.
A linear power supply essentially comprises of a mains The rectifier voltage always has some AC content
transformer, a rectifier circuit, a filter circuit and a known as power supply ripple. The filter circuit smoothens
regulation circuit (Fig. 22.1). The transformer provides the ripple of the rectifier voltage. The regulator circuit
voltage transformation and produces across its secondary is a type of feedback circuit that ensures that the output
winding(s) AC voltage(s) required for producing the DC voltage does not change from its nominal value due
desired DC voltages. It also provides electrical isolation to change in line voltage or load current.
between the input power supply, that is, AC mains and In a linearly regulated power supply, the active device
the DC output. The step-down transformers required for used in the regulator, usually a bipolar transistor, is
generating common DC voltages and load current ratings operated anywhere between cut-off and saturation. The
are commercially available. The step-up transformers commonly used regulator circuit configurations include
for generating higher output voltages could be custom emitter-follower regulator, series-pass transistor regulator
designed. and shunt regulator. Emitter-follower and series-pass regu-
The rectifier circuit changes the AC voltage appearing lators are, in fact, now available in IC packages in both fixed
across transformer secondary to DC or more precisely a output voltage as well as variable output voltage varieties.

486 Chapter 22: Power Supplies
AC Regulator DC
Mains transformer Rectifier Filter

Figure 22.1| Constituents of a linear power supply.
All power supplies have in-built protection circuits. The 22.2.1 Inductor Filter
common protection features include current limit, short
circuit protection, thermal shutdown and crowbaring. The The fact that an inductor offers high reactance to AC
rectifier circuits have been discussed in Chapter 14 and components is the basis of filtering provided by inductors.
hence they are not covered in this chapter. Figure 22.2(a) shows the full-wave rectifier circuit with
an inductor filter. The load current waveforms with and
22.2 FILTERS without filter are shown in Fig. 22.2(b).
The expression for ripple factor (g) is given by
RL
g= (22.1)
The filter in a power supply helps in reducing the ripple 3 2(wL)
content (the amplitude of AC component), which in
the rectifier waveform is so large that the waveform where g equals RL/1333L for power line frequency of
can hardly be called a DC. Inductors, capacitors and 50 Hz and RL/1600L for power line frequency of 60Hz.
inductor-capacitor combinations are used for the purpose Here, L is measured in henry and R is measured in
of filtering. ohms.
(Filter)
D2 D1
AC
input RL
iL
D3 D4
(a)
iL
Im
Without filter
2Im
IDC
p
With filter
wt
0 f p 2p 3p
(b)
Figure 22.2| Inductor (or choke) filter.

22.2 FILTERS 487
As is clear from the above expression, the ripple The ripple factor (g) equals 2887/CRL for power
factor is directly proportional to load resistance (RL). line frequency of 50 Hz and 2406/CRL for a power line
That is, ripple content increases with increase in load frequency of 60 Hz. Here, C is measured in microfarads
resistance. In other words, choke filter is not effective and RL is in ohms. It may be mentioned here that the
for light loads (or high values of load resistance) and above expression for ripple factor holds good in the case of
is preferably used for relatively higher load currents. It an ideal capacitor with a zero equivalent series resistance
may also be noted that with inductive filtering, the load (ESR). In the case of practical capacitors, the ESR is
current never drops to zero. If the value of inductance is easily of the order of several ohms or even a few tens
suitably chosen, the flow of current through the diodes of ohms for the large values of capacitance encountered
and the secondary of the transformer is much more even in filter capacitors. In such cases, the ripple factor
than it would have been without the filter. This leads to deteriorates from the value computed from Eq. (22.2).
ratio of rectification of almost unity due to rms and DC The ESR should also be considered while computing the
values of the filtered current waveform to be almost the repetitive peak current during the charging process and
same and an improved transformer utilization factor. also the surge current that would flow when the power
is initially switched on and the filter capacitor is fully
22.2.2 Capacitor Filter discharged.
The filtering action of a capacitor connected across

22.2.3 LC Filter
the output of the rectifier comes from the fact that it
offers a low reactance to AC components. Figure 22.3(a) We have seen that while an inductance filter is effective
shows capacitor filter connected across the output of a only at heavy load currents, and a capacitor filter pro-
full-wave rectifier. The AC components are bypassed to vides adequate filtering only for light loads. The perfor-
ground through the capacitor and only the DC is allowed mance of inductor and capacitor filters deteriorates fast
to go through to the load. The capacitor charges to the as the load resistance is increased in the case of former
peak value of the voltage waveform during the first or decreased in the case of the latter. Apparently, an
cycle and as the voltage in the rectified waveform is on appropriate combination of L and C could give us a filter
the decrease, the capacitor voltage is not able to follow that would provide adequate filtering over a wide range
thechange as it can discharge only at a rate determined of load resistance RL values.
by CRL, the time constant. In the case of light loads Figure 22.4 shows an LC filter connected across the
(or high values of load resistance), the capacitor would output of a full-wave rectifier. If the value of inductance
discharge only a little before the voltage in the rectified L in the LC filter is small, the filter will predominantly
waveform exceeds the capacitor voltage thus charging it be a capacitor filter and the capacitor will repetitively
again to the peak value [Fig. 22.3(b)]. The ripple content charge to the peak value and cut off the diodes. The cur-
is inversely proportional to C and RL. rent in this case is in the form of short pulses only. An
The ripple can be reduced by increasing C for a given increase in value of inductance allows the current to flow
of RL. For heavy loads when RL is small, even a large for longer periods. If the inductance is further increased,
capacitance value may not be able to provide ripple we reach a stage where one diode or the other is always
within acceptable limits. conducting with the result that the current and voltage
VRMS 1
Ripple factor, g = = (22.2) to the input of LC filter are full-wave rectified waveforms.
VDC 4 3fCRL This is known as the critical value of inductance, LC.
vL
D2 D1
Vm
AC With filter
input vL C 2Vm
p
RL
(Filter)
D3 D4 VDC Without filter
T/2 t
T1 T2
(a) (b)
Figure 22.3| Capacitor filter.

(Filter) LC sections. The filter can be analysed in the same

fashion as it was done in the case of a single section filter.
2 XC 1 XC2
Ripple factor, g = (22.5)
3 X X
D1 L
L1 L2
AC
RL For L1 = L2 = L and C1 = C2 = C
input C
g=
2
(22.6)
D2
48w L C 2
4 2
The ripple factor equals 3/L2C2 for power line frequency

of 50 Hz and 1.45/L2C2 for power line frequency of
Figure 22.4| LC filter. 60Hz. Here, L is in heny and C in microfard. The value
of critical inductance is as it is in the case of single sec-
2XC 2 2 1
tion filter.
Ripple factor, g =
1
= 2 =
2 LC
3XL
3 4w LC 12w 22.2.4
CLC Filter (p-Filter)
2XC 2 2 1
g=
1
3 4w 2 LC = 12w 2 LC
= (22.3)
Figure 22.6 shows the CLC filter, which is basically a
3XL
capacitor filter followed by an LC section. The ripple
The above expression proves that the ripple factor in a characteristics of this filter are similar to those of
choke input LC filter is independent of RL. Eq. (22.3) two-section LC filter and the expression for ripple factor
reduces to 1.2/LC for power line frequency of 50 Hz can be written as
and 0.83/LC for a power line frequency of 60 Hz. In this
X XC 1
expression, L is in henry and C is in microfarad. The Ripple factor, g = 2 C (22.7)
value of critical inductance is given by RL XL 1
R
LC = L (22.4) The circuit however suffers from the problem of high
3w diode peak currents, poorer regulation and a ripple that is
where LC equals RL/942 for a power line frequency of dependent upon load resistance. In the case of very small
50 Hz and RL/1131 for a power line frequency of 60Hz. load current, one may replace the inductance(L) with
Here, R is in ohms and LC is in henry. In practice, L a resistance equal in value to the inductive reactance at
should be about 25% higher than LC to take care of the ripple frequency of 2w.
approximation made in writing the expression. This
v(t)
gives L RL/754 (for power line frequency of 50 Hz)
and RL/905 (for power line frequency of 60 Hz).
v(t)
wt
+
wt L1
v(t) C C1 RL
+
L1 L2
RL
Figure 22.6| CLC or p-type filter.
v(t) C1 C2

22.3 LINEAR REGULATORS
Figure 22.5| Two-section LC filter with full-wave
rectified input.
The regulator circuit in the power supply ensures that the
Multiple LC sections can be used to further smoothen load voltage (in the case of voltage regulated power sup-
the output. Figure 22.5 shows one such filter using two plies) or the load current (in the case of current regulated

22.3 LINEAR REGULATORS 489
power supplies) is constant irrespective of variations in 22.3.2 Series-Pass Regulator

line voltage or load resistance. In the present section
are discussed different types of voltage regulatorcircuits. The emitter-follower regulator circuit discussed in the pre-
Three basic types of linear voltage regulator configura- vious section is also a type of series-pass regulator where
tions include the emitter-follower regulator, series-pass the conduction of the series transistor decides the voltage
regulator and shunt regulator. Each one of these is drop across it and hence the output voltage. The Zener
briefly described in the following paragraphs. diode provides the reference voltage that controls the
conduction of the transistor depending upon the output
22.3.1 Emitter-Follower Regulator voltage. Figure 22.9 shows the basic constituents of an
improved series-pass type linear regulator that is capable
Figure 22.7 shows the basic positive output emitter- of providing much better regulation specifications. The
follower regulator. The emitter voltage, which is also the series-pass element, a bipolar transistor in the circuit
output voltage, remains constant as long as the base shown, again works like a variable resistance with the
voltage is held constant. A Zener diode connected at the conduction of the transistor depending upon the base cur-
base ensures that the base voltage is held constant. The rent. The regulator circuit functions as follows.
regulated output voltage in this case is (VZ 0.6) V. A small fraction of the output voltage is compared
The baseemitter voltage ofthe transistor is assumed to with a known reference DC voltage (Vref) and their dif-
be 0.6V. Figure 22.8 shows theemitter-follower regula- ference is amplified in a high gain DC amplifier. The
tor circuit for negative output voltages. The regulated amplified error signal is then fed back to the base of
output voltage in this case is(VZ 0.6) V. If the load the series-pass transistor to alter its conduction so as
current is so large that it is beyond the capability of to maintain essentially a constant output voltage. The
a Zener diode to provide the requisite base current, a regulated output voltage in this case is given by
R + R2
Darlington combination can be used instead of a single
Vref 1
R2
transistor series-pass element.
+ Q + Series-pass element
R + Q +
R R1
Unregulated RL Regulated Amplifier
input (Vi) output (Vo)
+ RL
Unregulated + Regulated
VZ input (Vi) Vref output (Vo)
R2

Figure 22.7| Emitter-follower regulator for positive

Figure 22.9| Series-pass linear regulator.
output voltages.
As the output voltage tends to decrease due to
decrease in input voltage or increase in load current, the
Q
error voltage produced as a result of this causes the base
current to increase. The increased base current increases
R
transistor conduction thus reducing its collector-emitter
voltage drop, which compensates for the reduction in the
Unregulated RL Regulated
output voltage. Similarly, when the output voltage tends
to increase due to increase in input voltage or decrease in

load current, the error voltage produced as a consequence
VZ
is of the opposite sense. It tends to decrease transistor
+ + + conduction thus increasing its collector-emitter voltage
drop again maintaining a constant output voltage. The
regulation provided by this circuit depends upon the
Figure 22.8| Emitter-follower regulator for negative stability of the reference voltage and the gain of the DC
output voltage. amplifier.

+ Q1 +
R4
R3 R1
R5 Q2
Unregulated RL Regulated
Q3 +
D1 R2
VZ
R6

Figure 22.10| Series-pass linear regulator with overload protection.
22.3.3 Current Limiting in Series-Pass Linear limiting current is as per the preset value. There can be
Regulators other possible circuit configurations that can provide the
desired protection function.
The power dissipated in the series-pass transistor is the A common form of current limiting feature practiced in
product of its collectoremitter voltage and the load cur- linearly regulated power supplies is the foldback current
rent. As the load current increases within a certain range, limiting. It is a form of over-current protection where
the collectoremitter voltage decreases due to the feed- the load current reduces to a small fraction of the limit-
back action keeping the output voltage as constant. The ingvalue the moment the load current exceeds the limiting
series-pass transistor is so chosen that it can safely dis- value. This helps in drastically reducing the dissipation in
sipate the power under normal load conditions. If there series-pass transistor in the case of short circuit condition.
is an overload condition due to some reason or the other, Figure 22.11 shows a comparison of voltage versus load
the transistor is likely to get damaged if such a condi- current curve in the case of simple conventional current
tion is allowed persist for long. In the worst case, if there limiting and foldback current limiting.
were a short circuit on the output, the whole of unregu- Other types of protection features that are usually
lated input would appear across the series-pass element built into power supplies include crowbaring and
increasing the power dissipation to prohibitively large thermal shutdown. Crowbaring is a type of over-voltage
magnitude eventually destroying the transistor. Even a protection and thermal shutdown disconnects the input
series connected fuse does not help in such a case, as to the regulator circuit in the event of temperature of the
the thermal time constant of transistor is much smaller active device/s exceeding a certain upper limit.
than that of the fuse. Thus, it is always desirable to
build overload protection or current limiting protection
Load voltage
in the linearly regulated power supply design. One such

conventional current limiting configuration is shown in Simple
current
Fig. 22.10.
limiting
Under normal operating conditions, transistor Q3 is
in saturation. Thus, it offers very little resistance to Foldback
current
the load current path. In the event of an overload or a
limiting
short circuit, diode D1 conducts thus reducing the base
Maximum
drive to transistor Q3. Transistor Q3 offers an increased
value of
resistance to the flow of load current. In the event of a load current
short circuit, the whole of input voltage would appear
across Q3. Transistor Q3 should be so chosen that it Load current
can safely dissipate power given by the product of Figure 22.11| Foldback current limiting.
worst case unregulated input voltage and the limiting
value of current. Diode D1 and transistor Q3 should 22.3.4 Shunt Regulator
preferably be mounted on the same heat sink so that
baseemitter junction of Q3 and diodes PN junction are In the case of a shunt type linear regulator (Fig. 22.12),
equally affected by temperature rise and the short circuit the regulation is provided by a change in the current

22.4 LINEAR IC VOLTAGE REGULATORS 491
R1 output voltage (positive and negative) IC regulators

are commercially available in a wide range of voltage,
+ + current and regulation specifications. These have built-in
(IS + IL) +
IS IL protection features such as current limit, thermal shut-
VZ down and so on.

Unregulated Regulated 22.4.1 General Purpose Precision Linear Voltage
Q RL
input (Vi) output (Vo) Regulator
R2 IC723 is one such general-purpose adjustable output

voltage regulator that can be used in positive or negative
output power supplies as series, shunt and switching
regulator. The internal schematic arrangement of IC723
resembles the typical circuit for a series-pass linearreg-
Figure 22.12| Shunt regulator. ulator and comprises of a temperature compensated
reference, an error amplifier, a series-pass transistor
and a current limiter with access to remote shutdown.
through the shunt transistor to maintain a constant Regulator circuits with enhanced load current capability
output voltage. The regulated output voltage in a shunt can also be configured around regulator IC723 with the
regulated linear power supply is the unregulated input help of external bipolar transistors.
voltage minus the drop across resistance R1. Now,
the current through R1 is the sum of load current IL
andcurrent through shunt transistor IS. As the output
22.4.2 Three-Terminal Regulators
voltage tends to decrease, the base current through
In their basic operational mode, three-terminal regulators
the transistor reduces with the result that its collector
require virtually no external components. These are
current IS also decreases. This reduces drop across R1
available in both fixed output voltage (positive and nega-
and the output voltage is restored to its nominal value.
tive) as well as adjustable output voltage (positive and
Similarly, tendency of the output voltage to increase is
negative) types in current ratings of 100 mA, 500 mA,
accompanied by an increase in current through the shunt
1.5 A and 3.0 A. The popular fixed positive output
transistor consequently increasing voltage drop across
voltage regulator types include LM/MC78XX-series
R1, which in turn maintains a constant output voltage.
and LM 140XX/340XX-series three-terminal regulators.
The regulated output voltage is given by VZ + VBE.
LM117/217/317 is a common adjustable positive output
A Darlington combination in place of shunt transistor
voltage regulator type number. Popular fixed negative
enhances the current capability.
output voltage regulator types include LM/MC79XX-
A shunt regulator is not as efficient as a series regula-
series and LM 120XX/320XX-series three-terminal regu-
tor for the simple reason that the current through the
lators. LM137/237/337 is a common adjustable negative
series resistor in the case of shunt regulator is the sum
output voltage regulator type number. A two-digit number
of load current and shunt transistor current and it dis-
in place of `XX indicates the regulated output voltage.
sipates more power than the series-pass regulator with
An important specification of three terminal regulators
same unregulated input and regulated output specifica-
is the dropout voltage, which is minimum unregulated
tions. In a shunt regulator, the shunt transistor also dis-
input to regulated output differential voltage required for
sipates power in addition to the power dissipated in the
the regulator to produce the intended regulated output
series resistor. The only advantage with a shunt regula-
voltage. It is in the range of 1.5 V to 3 V and is lower
tor is its simplicity and that it is inherently protected
for regulators with lower load current delivery capability
against overload conditions.
and lower regulated output voltage value. For example,
5 V regulator has a dropout voltage specification of 2
22.4 LINEAR IC VOLTAGE V against 3 V for a 24 V regulator for the same cur-
REGULATORS rent delivery capability. Also, a 100 mA output regulator
has a drop voltage specification of 1.7 V against 3 V for
1500mA regulator for the same regulated output voltage.
The contemporary regulator circuits are almost exclu- Figure 22.13 shows the basic application circuits
sively configured around one or more ICs known as using LM/MC78XX-series and LM/MC79XX-series
IC voltage regulators. IC voltage regulators are avail- three-terminal regulators. Here, C1 and C2 are decou-
able to meet a wide range of requirements. Both fixed pling capacitors where C1 is generally used when the
output voltage (positive and negative) and adjustable regulator is located far from the power supply filter.

LM/MC 78XX LM/MC 79XX
+
I/P O/P
+ I/P O/P
COM COM
Vi C1 C2 Vo Vi C1 C2 Vo
+ +
Figure 22.13| Basic application circuits using three-terminal regulators.
Typically, a 0.22 mF ceramic disc capacitor is used for output voltage is adjustable from 1.2 V to 37 V. In
C1. Also C2 is typically a 0.1 mF ceramic disc capacitor. the high-voltage version of this series of regulators desig-
LM140XX/340XX series and LM 120XX/320XX series nated as LM 137HV/237HV/337HV, the output voltage is
regulators are also used in the same manner. In the case adjustable from 1.2 V to 47 V.
of fixed output voltage three-terminal regulators, if the
common terminal instead of being grounded were applied LM/MC 78XX
a DC voltage, the regulated output voltage in that case LM 340 XX
+ I/P O/P +
would be greater than the expected value by a quantum
equal to the voltage applied to the common terminal. COM
Figure 22.14 shows the application of fixed output
three-terminal regulator as a constant current source. Vi C1 Vreg
R
The load current in this case is given by [Vreg/R + IQ] 0.22 F
where IQ is the quiescent current, typically 8 mA for IQ Iout
78XX-series regulators.
LM117/217/317 is an adjustable output three-terminal
positive output voltage regulator and is available in cur-
rent ratings of 500 mA, 1000 mA and 1500 mA. The Figure 22.14| Three-terminal regulator as a constant
output voltage is adjustable from 1.2 V to 37 V. In the current source.
high voltage version of this series of regulators designated
as LM 117HV/217HV/317HV, the output voltage is 22.4.3 Boosting Current Delivery Capability
adjustable from 1.2 V to 57 V.
LM137/237/337 is an adjustable output three-terminal The load current delivery capability of three-terminal
negative output voltage regulator and is available in cur- regulators can be increased by using an external
rent ratings of 500 mA, 1000 mA and 1500 mA. The transistor. Figure 22.15(a) shows the typical circuit where
R Q1 78XX R Q1
79XX

I/P O/P I/P O/P
+ +
COM COM
Vi RL Vo Vi RL Vo
+ +
(a) (b)
Figure 22.15| Use of external transistor to boost current delivery capability.

22.5 SWITCHED MODE POWER SUPPLIES 493
an external transistor is used to boost the load current 22.5.2.1Self-Oscillating Flyback DC-to-DC
delivery capability of the regulator. In this case, as long Converter
as VBE(Q1) remains below its cut-in voltage, the regulator
functions in its usual manner as if there were no external Figure 22.16 shows the circuit arrangement in a
transistor. As the VBE (Q1) attains the cut-in voltage due self-oscillating type or ringing choke type flyback
to an increasing load current, Q1 conducts and bypasses DC-to-DC converter. A switching transistor, a converter
part of load current through it. In fact, the magnitude of transformer, a fast recovery rectifier and an output filter
load current allowed to go through the regulator equals capacitor make up a complete DC-to-DC converter. It is
VBE (cut-in)/R. The rest of the current passes through the a constant output power converter.
external transistor. An NPN transistor can be used to do
the job in the case of n
egative output voltage regulators Vin
as shown in Fig. 22.15(b).
LP
22.5 SWITCHED MODE POWER
SUPPLIES
D1
Q1
In a switched mode power supply, the active device that
LS C1 Vo
provides regulation is always operated in a switched mode,
that is, it is operated either in cut-off or in saturation.
The input DC is chopped at a high frequency (typically
10100 kHz) using an active device (bipolar transistor,
power MOSFET, IGBT or SCR) and the converter trans-
former. The transformed chopped waveform is rectified
and filtered. A sample of the output voltage is used as
feedback signal for the drive circuit for the switching
transistor to achieve regulation. Figure 22.16| Self-oscillating type flyback DC-to-DC
converter.
22.5.1 Different Types of Switched Mode During the conduction time of the switching transis-
Power Supplies tor, the current through the transformer primary starts
ramping up linearly with a slope equal to Vin/LP where
Switched mode power supplies are designed in a variety LP is the primary inductance. The voltages induced in
of circuit configurations depending upon the intended the secondary and the feedback windings make the fast
application. Almost all switching supplies belong to recovery rectifier diode D1 reverse biased and hold the
one of the following three broad categories, namely, conducting transistor ÒN. When the primary current
flyback converters, Forward converters and Pushpull reaches a peak value IP, where the core begins to saturate,
converters. There are variations in the circuit configu- the current tends to rise very sharply. This sharp rise
ration within each one of these categories of switched in current cannot be supported by the fixed base drive
mode power supplies. For instance, in the category provided by the feedback winding. As a result, the switch-
of flyback converters, we have the self-oscillating fly- ing transistor begins to come out of saturation. This is a
back converters and the externally driven flyback con- regenerative process that ends up in the transistor getting
verters. Again, in the externally driven type flyback switched off. The magnetic field due to the current flow-
converters, there are isolation and non-isolation type ing in the primary winding collapses, thus reversing the
configurations. polarities of the induced voltages. The fast recovery recti-
fier diode D1 is now forward biased and the stored energy
is transferred to the capacitor and the load through the
22.5.2 Flyback Converters secondary winding. Thus, energy is stored during the
ON-time and transferred during the OFF-time.
The self-oscillating type flyback DC-to-DC converter The output capacitor supplies the load current during
is the most basic converter based on the flyback prin- the ON-time of the transistor when no energy is being
ciple. The other type is the externally driven flyback transferred from the primary side. It is a constant output
DC-to-DC converter. The two types are described in the power converter and the power that the converter can
following paragraphs. deliver to the load is equal to 1 2 LP IP2 f h,

which is the product of energy stored in the primary of Vin

the converter transformer, the switching frequency (f)
and the conversion efficiency (h). Here, LP and IP are, 1: n
Vo
respectively, the primary inductance and peak value of
primary current. The output voltage reduces as the load LP LS RL
increases and vice versa. Utmost care should be taken
C
to ensure that the load is not accidentally taken off the
converter. In that case, the output voltage would rise
without limit till any of the converter components gets
damaged. It is suitable for low output power applications Drive Q1 R1
due to its inherent nature of operation and may be used circuit
with advantage up to an output power of 150 W. It is
characterized by high output voltage ripple.
22.5.2.2Externally Driven Flyback

DC-to-DC Converter
A variation of this circuit is the externally driven fly- + Vref

back converter (Fig. 22.17). The basic principle remains R2
the same. Energy is stored during the on-time and Feedback loop
transferred during the off-time of the active device.
The feedback loop consisting of a comparator and the
resistance divider provides the voltage sense as well as Figure 22.17| Basic externally driven flyback
some degree of regulation. converter.
22.5.3 Forward Converter D5 is forward biased and diodes D6 and D7 are reverse
biased. Most of the energy in a forward converter is
Forward converter is another popular switched mode stored in the output inductor rather than the transformer
power supply configuration. Figure 22.18 shows the basic primary used to store energy in a flyback converter.
circuit diagram of an off-line forward converter. There When the transistor switch is turned off, the magnetic
are some fundamental differences between a flyback con- field collapses. Diode D5 is reverse biased and diodes D6
verter and a forward converter. In the case of circuit and D7 are forward biased. As the current through an
diagram shown in Fig. 22.18, when the transistor switch inductance cannot change instantaneously, the output
is turned on, the polarities of the transformer windings current continues to flow through the output and the
(as indicated by the position of dots) are such that diode forward biased diode D6 provides the current path.
D5 L1
D6 Vo
C2
D1 D2
D7
C1
AC
input D4 D3 Sense
PWM Isolation
circuit
Q1
Figure 22.18| Basic off-line forward converter.

22.6 SWITCHING REGULATORS 495
Unlike a flyback converter, current in a forward current tends to rise sharply, which is not supported by
c onverter flows from the energy storage element during a more or less fixed base bias. The transistor starts to
both halves of the switching cycle. Thus, for the same come out of saturation. This is a regenerative process and
output power, a forward converter has much less output ends up in switching off transistor Q1 and switching on
ripple than a flyback converter. Controlling the duty transistor Q2. Thus transistor Q1 and Q2 switch on and
cycle of the transistor switch provides output regulation. off alternately. When Q1 is on, energy is being stored in
In the absence of the third winding and diode D7, a good the upper half of the primary and the energy stored in the
fraction of energy stored in the transformer primary immediately preceding half cycle in the lower half of the
is lost. This effect is more severe at higher switching primary winding (when transistor Q2 was on) is getting
frequencies. The third winding and the forward biased transferred. Thus, the energy is stored and transferred
diode D7 return the energy, which would otherwise be at the same time. The voltage across secondary is a
lost and reset the transformer core after each operating symmetrical square waveform, which is then rectified and
cycle. This not only increases the converter efficiency filtered to get the DC output.
but also makes the converter transformer core immune As the primary is centre-tapped, and only half of the
to saturation problems. primary winding is active at a time, the main trans-
former is not utilized as well as it is in the case of other
22.5.4 PushPull Converter forms of pushpull converter, like half-bridge and full-
bridge converters. Also, in a pushpull converter, switch-
Pushpull converter is the most widely used switched ing transistors operate at collector stress voltages of at
mode power supply configuration belonging to the family least twice the DC input voltage. As a result, a push
of forward converters. There are several different circuit pull converter is not a highly recommended choice for
configurations within the pushpull converter sub-family. off-line operation. The self-oscillating pushpull convert-
These circuits differ only in the mode in which the trans- ers are frequently used along with a voltage multiplier
former primary is driven. These include the conventional chain to design a high voltage low current power supply.
two-transistor, one-transformer pushpull converter (both Apushpull converter that has wider applications than
self-oscillating and extremely driven type) two-transistor, its self-oscillating counterpart is the extremely driven
two-transformer pushpull converter, half bridge converter pushpull converter (Fig. 22.20).
and full bridge converter.
Figure 22.19 shows the conventional self-oscillating
type of pushpull converter. Base resistors RB1 and RB2 22.6 SWITCHING REGULATORS
are equal in magnitude. Its operation can be explained
by considering it equivalent to two alternately operating
self-oscillating flyback converters. When transistor Q1 is The commonly used switching regulator configurations
in saturation, energy is stored in the upper half of the pri- include step-down or buck regulator, step-up or boost
mary winding. When the linearly rising current reaches a regulator and inverting regulator also called buck-boost
value where the transformer core begins to saturate, the regulator.
D1 D2
RB1
R2 R1
D4 C1 Vo
Q1 D3
RB2
Vin
Q2
Figure 22.19| Basic self-oscillating type pushpull converter.

D1
Q1 Vin
C1 Vo
D2
Q2
Figure 22.20| Externally driven pushpull converter.
22.6.1 Buck Regulator pulse width modulation of transistor switch. It is a very

popular circuit configuration for fabrication of high
Figure 22.21 shows the basic buck regulator. It resembles efficiency three-terminal switching regulators.
the conventional forward converter except for the fact
that it does not use a transformer and there is no input 22.6.2 Boost Regulator
output isolation. The output voltage is always less than
the input voltage and is given by Vo = DVin, where The step-up switching regulator, also called the boost
D is the duty cycle (= TON/T) of the drive waveform regulator (Fig. 22.22), is based on flyback principle.
to the transistor switch. The regulation is achieved by It resembles the basic flyback converter except that it
IQ1 L1 Io
Vo
Q1 R1
Vin D1 C1
Vref
ID1 R2 +
Error

Vs amplifier
PWM
+
Figure 22.21| Buck regulator.
L1
IL1 ID1
Vo
Vin D1
R1
C1 Vref
R2
Q1 +
Vs Error amplifier

PWM
+
Figure 22.22| Boost regulator.

22.8 REGULATED POWER SUPPLY PARAMETERS 497
is non-isolating type. The energy storage and trans- 1. Linear power supplies are well known for their
fer element in this case is an inductor rather than a extremely good line and load regulation, low
transformer. The output voltage in this case is given by output voltage ripple and almost negligible (radio-
frequency interference) RFI/electromagnetic inter-
Vin T
Vo = = Vin ference (EMI).
1D TOFF 2. Switching power supplies have much higher effi-
where D is the duty cycle and T is the total time period ciency (typically 8090% against 5060% percent in
which is equal to TON + TOFF. the case of linear supplies) and reduced size/weight
for a given power delivering capability. Quite often,
22.6.3 Inverting Regulator compactness and efficiency are two major selection
criteria. An improved efficiency and reduced size/
An inverting regulator (Fig. 22.23) is another circuit con- weight are particularly significant when designing
figuration based on the flyback converter principle. For a a power supply for a portable system where there
positive input, it produces a negative output. The energy is a requirement of a number of different regulated
is stored in inductor L1 during the conduction time of the output voltages.
transistor. The diode D1 is reverse biased during this time 3. Also, unlike linear supplies, efficiency in switching
period. The stored energy is transferred during OFF-time supplies does not suffer as the unregulated input to
of the transistor. The circuit delivers a constant output regulated output differential becomes large.
power to the load. The output voltage is given by Po RL . 4. In portable systems operating from battery
The regulation of the output voltage, which is equal to packs and requiring higher DC voltages for their
Vin (Ton/Toff) is achieved by controlling the duty operation, the switching supply is the only option.
cycle of the drive waveform. In the inverting regulator We cannot use a linear regulator to change a given
configuration, it is possible to have an output voltage unregulated input voltage to a higher regulated
that is either less than or greater than the input volt- output voltage.
age. It is also sometimes referred to as buck-boost regula-
tor. Unlike the boost regulator, during the turn-off time
period, the decaying current ramp does not flow through 22.8 REGULATED POWER SUPPLY
the source of input DC. The output power delivery capa- PARAMETERS
bility of inverting regulator is therefore given by
1
Po = (L1 IP2 f ) The characteristic parameters that define the quality of
2 a regulated power supply include load regulation, line or
source regulation, output impedance or resistance and
22.7 LINEAR VERSUS SWITCHED ripple rejection factor.
MODE POWER SUPPLIES
22.8.1 Load Regulation
Some of the salient features of linear and switched mode Load regulation is defined as change in regulated output
power supplies are presented in the following paragraphs voltage of the power supply as the load current varies
for the purpose of comparison between the two. from zero (no load condition) to maximum rated value
Vo
D1
R1
Q1
Vin L1 C1 Vref
R2 +
Error amplifier
+
PWM
Vs
Figure 22.23| Inverting regulator.

of load (full load condition). It is usually expressed as a divider. The load voltage decreases with decrease in load
percentage of full load voltage. That is, resistance value. An ideal power supply has an output
V V FL impedance of zero, which renders the output voltage
Percentage load regulation = NL 100

VFL independent of the load resistance value.
The practical power supplies very nearly approach
Since VFL VNL, load regulation may be expressed as a the ideal condition because of emitter-follower nature
percentage of no load voltage. of regulator circuit characterized by low output imped-
ance, which is further reduced by a factor of (1 + loop
22.8.2 Line Regulation gain) due to voltage feedback. Loop gain is product of
output voltage feedback factor and the gain of the error
Line regulation is defined in terms of variation of reg- amplifier. Output impedance is typically of the order of
ulated output voltage for a specified change in line milli-ohms.
voltage. It is also usually expressed as percentage ofnom-
inalregulated output voltage. As an example, if the
22.8.4 Ripple Rejection Factor
nominal regulated output voltage of 10 V varies by 1%
for a specified variation in line voltage, line regulation in The ripple rejection factor is defined as the ratio of ripple
that case would be (0.2/10) 100 = 2%. in the regulated output voltage to the ripple present in
unregulated input voltage:
22.8.3 Output Impedance VRipple (output)
Ripple rejection factor =
The output impedance is an important parameter of a VRipple (input)
regulated power supply. It determines load regulation of
the power supply. The regulated power supply may be When expressed in decibels, the ripple rejection is
represented by a Thevenins equivalent circuit compris- VRipple (output)
ing of a voltage source equal to the open circuit volt- 20 log dB
VRipple (input)
age across power supply output terminals in series with
impedance equal to the output impedance of the power Ripple in unregulated input is nothing but a periodic
supply. The voltage appearing across the load resistance variation in input voltage. It manifests at the output
is equal to the open circuit voltage minus drop across with a reduced value. Again, the factor by which ripple
output impedance of the power supply. The voltage is reduced equals the desensitivity factor (1 + loop gain)
drop increases with increase in load current resulting due to negative feedback. That is,
in reduction of voltage across the load. Another way of VRipple (input)
explaining the same is that the output impedance of the VRipple (output) =
power supply and the load resistance form a potential 1 + loop gain
IMPORTANT FORMULAS
1. The ripple factor for an inductor filter is 4. The critical inductance for an LC filter is
RL R
g= LC = L
3 2(wL) 3w
5. For a filter with two LC sections, the ripple factor is
2. The ripple factor for a capacitor filter is
2 XC 1 XC 2
g =
3 XL 1 XL 2
V(RMS) 1
g= =
VDC 4 3fCRL
6. For a CLC filter (p-filter), the ripple factor is
3. The ripple factor for an LC filter is X XC 1
g = 2 C
2XC 2 2 1 RL XL 1
g=
1
= =
3XL 3 4w 2 LC 12w 2 LC 7. For a series-pass regulator:
2XC 2 1 2 1 R + R2
= 2 = Vo = Vo = Vref 1
R2
=
3 4w LC 12w LC
3XL 2

SOLVED EXAMPLES 499
8. For a buck regulator: 11. The percentage load regulation is
VNL V FL
Vo = DVin
where D is the duty cycle (= Ton/T) of the drive. 100
VFL
9. For a boost regulator:
12. The ripple rejection factor is
V T
Vo = in = Vin VRipple (output)
1D Toff
VRipple (output)
or 20 log dB
10. For an inverting regulator:
VRipple (input) VRipple (input)
T VRipple (input)
Vo = PoRL = Vin on 13. VRipple (output) =
Toff 1 + loop gain
SOLVED EXAMPLES
1. Refer to the emitter-follower regulator circuit The current through resistor R1 is

shown in the following figure. Assume b of the 18 12.7
transistor = 50, VBE = 0.7 V, forward voltage drop = 53 mA
100
of diode D1 = 0.7 V, Zener diode voltage (VZ) =
12 V. What is the regulated output voltage? A part of this current flows towards the base ter-
minal of transistor Q1 and the rest flows through
the series combination of Zener diode and diode D1.
+
+ Now, the load current is
R1 12
Q1 = 12 mA
100 1000
The base current of transistor Q1 is
Vi = 18V RL = 1 k Vo 12 10 3 0.012
= = 0.24 mA
VZ (1 + b ) 51
Therefore, the current through Zener diode is
53 103 0.24 103 = 52.76 mA
D1
Ans. (b)
3. The following figure shows the basic shunt regula-
tor circuit. Assume VBE = 0.7 V. What is the value
(a) 12 V (b) 13.4 V of the regulated output voltage?
(c) 5 V (d) 24 V
RS = 10
+ +
Solution. The regulated output voltage is +
Vo = VZ + VD1 VBE = 12 + 0.7 0.7 = 12 V VZ = 14.3 V
Ans. (a)
Vi = 24 4 V RL Vo
2. What is the current through the Zener diode in the
case discussed in Question 1? Q1
(a) 53 mA (b) 52.76 mA

(c) 53.24 mA (d) 10 mA
Solution. We have
(a) 13.7 V (b) 12 V
VCE = 18 12 = 6 V (c) 15 V (d) 20 V

Solution. The regulated output voltage is voltage falls from 24 VDC to 23.8 VDC as the load
changes from no load to full load condition for the
Vo = VZ + VBE(Q ) = 14.3 + 0.7 = 15 V
1 nominal value of input voltage. What is the value
Ans. (c) of line regulation?
4. What is the maximum power dissipation in resistor (a) 1% (b) 4.2%
RS in the case discussed in Question 3? (c) 5.7% (d) 1.5%
(a) 15 W (b) 17 W
Solution. The line regulation in percentage is
(c) 20 W (d) 23 W
24.5 23.5
100% = 4.16% 4.2%
Solution. We know that RS dissipates maxi- 24
mum power when the unregulated input voltage Ans. (b)
has maximum value. Now, maximum unregulated
input voltage is 28 V Therefore, the maximum
value of load regulation?
power dissipation is
(a) 0.5% (b) 0.84%
(28 15)2
= 16.9 W 17 W (c) 0.96% (d) 1%
10
Ans. (b) Solution. The load regulation in percentage is
5. A regulated power supply operates from 220 20 24 23.8

100% = 0.84%
VAC. It produces a no load regulated output volt- 23.8
age of 24 0.5 VDC. Also, the regulated output Ans. (b)
1. A regulated power supply provides a ripple rejec- Solution. The output impedance is given by ratio
tion of 80 dB. If the ripple voltage in the unregu- of change in output voltage for known change in
lated input were 2 V, what is the value of output load current. From the given characteristic curve,
ripple (in mV)? the output impedance is
24 23.5
= 0.05 W
Solution. The ripple rejection in dB is 0.5
=
10 0
Output ripple
10
20 log = 80 dB Ans. (0.05)
Input ripple 3. Refer to the three-terminal regulator circuit shown
Therefore, in the following figure. What is the power dissi-
pated in LM7812 and the transistor (in watt)?
Output ripple
= 104
Output ripple
= 4 or
Take VBE(Q ) = 0.7 V.
log 1
Input ripple Input ripple
Therefore, the output ripple is

2 104 V = 0.2 mV
Ans. (0.2) Q1 LM 7812
2. The following figure shows load voltage versus load + I/P O/P +
1 COM
current characteristics of a regulated power supply.
What is the output impedance of the power supply Vi = 15V Vo
5
(in ohms)?

24
23.5
voltage (V)
Load
Solution. The load current is

12
= 2.4 A
5
10
Load current (A)

The current through regulator is Therefore, the power dissipated in the regulator is
(14.3 12) 0.7 = 1.61 W
0. 7 Ans. (1.61)
= 0.7 A
1
The current through external transistor is powerdissipated in the transistor (inwatts)? Take
VBE (Q1) = 0.7 V.
2.4 0.7 = 1.7 A
Solution. Refer to the Solution of Question 3.
The voltage appearing at regulator input is Power dissipated in the transistor is
PD(Q1) = VCE(Q1)IC(Q1) = (12 15)( 1.7) = 5.1 W
15 0.7 = 14.3 V Ans. (5.1)
PRACTICE EXERCISE
1. The no load and rated load output voltage in a (a) Figure (a) (b) Figure (b)
regulated power supply are the same. Its output (c) Figure (c) (d) Figure (d)
impedance is therefore (1 Mark)
(a) extremely small (b) zero 4. In a series-pass linear regulator, voltage drop across
(c) infinite (d) extremely large series-pass element
(1 Mark) (a) is independent of changes in output voltage.
2. One of the following filter types is suitable only for (b) changes directly with changes in output voltage.
large values of load resistance. (c) changes inversely with changes in output
voltage.
(a) Capacitor filter (b) Inductor filter (d) changes logarithmically with changes in output
(c) Choke-input filter (d) p-Type CLC filter voltage.
(1 Mark) (1 Mark)
5. The type of linear voltage regulator that is inher-
3. One of the characteristic curves shown in the fol-
ently immune to overload condition is
lowing figures is for voltage regulating type lin-
early regulated power supply with foldback current (a) emitter-follower regulator
limiting. (b) series-pass regulator with error amplifier in
V V feedback loop
V V (c) shunt regulator
(d) None of these
(1 Mark)
6. A voltage regulator provides a ripple rejection of
60 dB. If the ripple in the unregulated input were
I I 0.5 V, the ripple in the regulated output would be
I I
(a) (b) (a) 0.5 mV (b) 60 mV
(a) (b) (c) 1 mV (d) 5 mV
(1 Mark)
V V
V V 7. A DC-to-DC converter having a conversion effi-
ciency of 80% is delivering a power of 16 W to the
load. If the converter were producing an output
voltage of 400 V from an input of 20 V, what would
be the current drawn from the 20 V source?
I I
I I (a) 1000 mA
(c) (d) (b) 500 mA
(c) (d)

(c) 200 mA (a) 25 V (b) 20 V

(d) Cannot be determined from given data. (c) 15 V (d) 12 V
(1 Mark) (2 Marks)
8. Refer to the regulator circuits shown in the follow-
ing figure. Determine the output voltage given that 11. Refer to the three-terminal regulator circuit shown
VBE of transistors is 0.6 V. in the following figure. What is the regulated
output voltage given that VZ = 3.3 V and VD =
+15 V 0.7 V?
Q1
R
1 k 10 k LM7805
Q2 I/P O/P
+ +
RL COM
Vo

10 k 12 V VZ Vo
3.9 V C1 C2
VD
(a) 1.2 V (b) 3.9 V
(c) 8.8 V (d) 9 V
(1 Mark)
9. The following figure shows the basic buck regula-
tor configuration. It produces a regulated output (a) 9 V (b) 7.6 V
voltage of +12 V. If the unregulated input voltage (c) 9 V (d) +7.6 V
at a certain time is +24 V, what is the on-time of (1 Mark)
the drive waveform appearing at the base terminal
of the switching transistor? Assume a switching 12. In a flyback type of DC-to-DC converter, the
frequency of 10 kHz. energy is stored in the primary winding of the
switching transformer during
Vin L1 Vo (a) turn-on time of the switching device.

(b) turn-off time of the switching device.
Q1 D1 C1
(c) both turn-on and turn-off times of the switch-
ing device.
(d) None of these.
(1 Mark)
PWM Sense
13. The following figure shows the basic boost regulator
(a) 150 s (b) 100 s circuit using a pulse width modulated drive wave-
(c) 50 s (d) 250 s form control (Vin = 12 V). For the drive waveform
(2 Marks) shown in the circuit, what is the output voltage?
10. Refer to the opamp-based series-pass regulator What is the changed on-time of the drive wave-
circuit shown in the following figure. What is the form when the unregulated input voltage changes
regulated output voltage? to +18 V.
+ + Vin Vo
50
L1 D1
s
Q1 R1 = 20 k
s
50
R3 = 1 k
C1
Vi = 1824V Vo PWM
+
+ R2 = 30 k Q1
VZ = 9V
Sense

(a) 25 V, 50 ms (b) 30 V, 40 ms
(c) 50 V, 50 ms (d) 24 V, 25 ms + Q1 +
22 k
(2 Marks)
14. The following figure shows the basic emitter-follower 470

Q2
type of voltage regulator circuit. Given that the 470
Zener diode is to be biased at least at 10 mA at all
times and VBE of transistor Q1= 0.6 V. What is the
A RL = 10
18 V
regulated output voltage? 100 Vo
Q3 B
+ + 470
5.6 V
R Q1
(a) 11.31 V (b) 12.35 V
18 22 V 120 Vo (c) 13.26 V (d) 14.75 V
+ (2 Marks)
19. What is the maximum possible regulated output
12.6V voltage in the case discussed in Question 18?

(a) 13.72 V (b) 12.39 V
(c) 13.26 V (d) 15.31 V
(1 Mark)
(a) 10 V (b) 12 V 20. An emitter-follower regulator circuit is shown in
(c) 15 V (d) 9 V the following figure. Given that transistors Q1 and
(1 Mark) Q2 in the Darlington pair have b of 10 and 100,
respectively, forward voltage drop of diodes D1
15. For the case discussed in Question 14, what is the andD2 is 0.6 V, VBE (Q1) = 0.6 V and VBE (Q2) =
value of R given that transistor (b) is equal to 100? 0.6 V. What is the regulated output voltage Vo and
current IZ?
(a) 535 (b) 655
(c) 455 (d) 325
(2 Marks)
16. The output voltage of a regulated power supply

drops by 1 V from no load to rated full load of 1A. Q1
The no load output voltage of the power supply 1 k
is 24 V. What is the load regulation of the power
supply?
Q2
RL = 30
(a) 2.3% (b) 3.2%
(c) 3.4% (d) 4.3% 36 V 24 V Vo
(1 Mark)
17. What is the output impedance of the power supply IZ

in the case discussed in Question 16? D1
(a) 2 (b) 0.5

(c) 1 (d) 3 D2
(1 Mark) + +
18. Refer to the series-pass regulator circuit shown in

the following figure. Assume VBE (Q1) = VBE (Q2) = (a) 24 V, 10 mA (b) 24 V, 10 mA
VBE (Q3) = 0.6 V. What is the minimum regulated (c) 24 V, 100 mA (d) 24 V, 100 mA
output voltage? (2 Marks)

21. A DC power supply has a no-load voltage of 30 V, (c) 3700 R 4000

and a full-load voltage of 25 V at a full-load cur- (d) R > 4000
rent of 1 A. Its output resistance and load regula- (2 Marks)
tion, respectively are
(a) 5 and 20% (b) 25 and 20%
R
(c) 5 and 16.7% (d) 25 and 16.7% + + IL = 10mA
(1 Mark) I2
22. A Zener diode regulator shown in the following

figure is to be designed to meet the specifications:
IL = 10 mA, Vo = 10 V and Vin varies from 30 V Vin DZ Vo RL
to 50 V. The Zener diode has VZ = 10 V and IZK
(knee current) = 1 mA. For satisfactory operation
(a) R 1800
(b) 2000 R 2200
1. The following figure shows the basic inverting reg- 3. Refer to the three-terminal regulator circuit shown
ulator circuit using a pulse width modulated drive in the following figure. What is the regulated
control. What is the output voltage (in volts) if the output voltage in volts given that VD = 0.7 V?
switching frequency were 10 kHz?
(2 Marks)
Vin = 18 V
Vo LM7912
40 I/P O/P

s Q1 D1
COM
T = 1/f L1 C1
PWM
18 V C1 C2 Vo
D
Sense
2. For the series-pass regulator circuit shown in the

following figure, what is the range (minimum and +
maximum) over which the regulated output voltage
(in volts) is adjustable? Assume VBE (Q2) = 0.7 V.
(2 Marks) (1 Mark)
+ Q1 + 4. The percentage regulation of an ideal power

R4 R1 supplyis .
R3
= 330 = 10 k
Q2 A
Regulated 5. The following figure shows the basic ringing choke
Vi = 405V RL output type of flyback DC-DC converter along with the
P drive waveform across the feedback winding and
= 10 k (Vo)
B the primary current waveform. From the data
+ given in the circuit diagram, what is the output
R2 voltage across the load resistance RL if the conver-
VZ = 9.3V
= 10 k sion efficiency were 80%?

(2 Marks)

+24 V are: VZ = 9.5 V, VBE = 0.3 V, b = 99. Neglect the

current through RB. Then, find the maximum power
iP
25 A iP dissipated in the Zener diode, PZ (in watts).
D (2 Marks)
50 t 20
s 50
s LP = 48 H RL +
= 100 k IC
4.7 F
IZ
Q
RB
VZ
Vin = 20 30 V Vo = 10 V
RB

6. The transistor shunt regulator shown in the following
figure has a regulated output voltage of 10 V, when 7. For the case discussed in Question 7, the maximum
the input varies from 20 V to 30 V. The relevant power dissipated in the transistor (in watts).
parameters for the Zener diode and the transistor (1 Mark)
1. (b) which gives

9
2. (a) Vo = = 15 V
0.6
3. (d) 11. (a) Vo = 5 + VZ + VD = 5 + 3.3 + 0.7 = 9 V
4. (b) 12. (a)
5. (c) 13. (d) From the given drive waveform, the duty cycle is
6. (a)
50 106
D= = 0.5
50 106 + 50 10 -6
7. (a)
8. (d)
The output voltage Vo in the case of boost regula-
9. (c) The output voltage in the case of buck regulator configuration is given by
tor is given by
Vin 12
T
Vo = = = 24 V
1 D 1 0. 5
Vo = Vin on = Vin Ton f
T
When the input voltage changes to +18 V, the
Therefore, new value of duty cycle D required to maintain the
Vo output voltage at +24 V is given by
12
Ton = = = 50 m s
Vin f 24 104 24 =
18
1D
10. (c) The regulated output voltage is the one for which gives
which voltage at the inverting input of opamp 18
equals the Zener voltage. That is, D=1 = 0.25
24
Vo 30 103 Therefore, the changed value of on-time is given by
= 9 or 0.6 Vo = 9
30 103 + 20 103 0.25 100 106 = 25 ms

14. (b) Vo = 12.6 VBE = 12.6 0.6 = 12 V. Therefore

Vo = 13.72V
15. (a) The emitter current is
Therefore, the maximum possible output voltage
12 = 13.72 V.
IE = = 10 mA
120 20. (b) Given that: Output voltage
Therefore, the base current is Vo = VZ1 VD1 VD2 + VBEQ1 + VBEQ2
3
IE 10 10 = 24 0.6 0.6 + 0.6 + 0.6
IB = = 0.1 mA
b 100 = 24V
The least current flows through the resistor R, Output load current = 24/30 A = 800 mA
when the input voltage is minimum, that is, Output load current = Emitter current of Q1
Base current of Q1 = 800/b1 = 80 mA
Vi = 18 V
Base current of Q2 = Emitter current of Q2
The current through the resistor R is Base current of Q2 = 80/b2 mA = 0.8 mA
Current flowing through 1 k resister
IB + IZ = 10.1 mA = I Z + I B2
For Vi = 18 V, we get = IZ + 0.8 mA
18 12.6
= 535
Applying Kirchhoffs voltage law to the input
R=
10.1 103 circuit
36 + 1(IZ + 0.8) + 24 + 0.6 + 0.6 = 0
(V V FL ) IZ + 0.8 = 36 25.2
16. (d) Load regulation = NL 100%
VFL = 10.8
VNL VFL = 1V and VFL = VNL 1 = 23V Therefore
1 IZ = 10 mA
Load regulation = 100%
23
= 4.35% 21. (b) The output resistance is
VFL VNL 30 25
17. (c) Full-load current = 1A = = 5
Voltage drop in full load condition = 1V I FL 1
Output impedance of the power supply = 1/1 W The load regulation is
=1W
VNL VFL 30 25
100% = 100% = 20%
18. (a) The potential at point A = VZ + VBE(Q ) VFL 25
1
= 5.6 + 0.6 = 6.2 V 22. (a) For a satisfactory operation of the Zener diode
Therefore regulator, we have
(Vo ) 570 Vin Vo
= 6.2V IZk + I L
1040 R
Therefore When Vin = 30 V, we have
6.2 1040 30 10
Vo =
570
= 11.31V (1 103 + 10 103 )
R
Therefore, the minimum possible output voltage Therefore, R 1818
= 11.31V
When, Vin = 50 V, we have
50 10
(1 103 + 10 103 )
19. (a) The potential at point B = VZ + VBE(Q1 )
= 5.6 + 0.6 = 6.2 V R
Therefore Therefore, R 3636

(Vo ) 470 and R 1800 satisfies both the above-mentioned
= 6. 2 V
1040 conditions.


1
f= Hz = 10 kHz
50 10 + 50 106
6
1. The output voltage is given by
T
Vo = Vin ON Therefore, the power stored is
TOFF
48 106 25 25 10 103 = 150 W
1
From the given drive waveform,
2
Toff = 40 s The power delivered to load resistance RL is
150 0.8 = 120 W
Now, f = 10 kHz, which gives
1
T = 4 s = 100 s If Vo were the voltage across RL, then
10
Therefore, V o2
= 120
TON = 100 106 40 106 = 60 s RL
which gives which gives
60 10 6 Vo = 120RL = 120 100 110 V
Vo = 18 = 27 V
40 10 6 Ans. (110)
Ans. (27)
6. The maximum power is dissipated in the Zener
2. The range over which the output voltage is adjust- diode and the shunt transistor, when the input
able is given by moving the position of the potenti- voltage is maximum. Let the current through the
ometer P from A to B. The regulated output voltage 20 resistor be denoted as I, through Zener diode
when the potentiometer P is at position A is given by as IZ, through base terminal as IB, through collec-
tor terminal as IC and through emitter terminal
10 103 + 20 103
(9.3 + 0.7) = 15 V as IE. Let the voltage across the Zener diode be
20 103
denoted as VZ and the collector voltage be denoted
as VC. When Vin = 30 V, we have
The regulated output voltage when the potentiom-
eter P is at position B is given by 30 10
I= =1 A
10 103 + 20 103 20
(9.3 + 0.7) = 30 V

Now, IE = IC + IZ (given that the current through
10 103 resistor RB = 0, we have IB = IZ). Also,
Therefore, the regulated output voltage is adjust- IC = bIB = bIZ
able in the range 1530 V.
Therefore,
Ans. (1530)
IE = (b + 1)IZ = 100IZ
3. LM 7912 is a negative output voltage regulator
withan output voltage of 12V. Since a diode is and I = IC + IZ = IE
connected to the COM input of the regulator, there-
fore the output voltage Vo = 12 0.7= 12.7 V Therefore,
Ans. (12.7) I
IZ = = 0.01 A
4. In an ideal supply, there is no change in the output 100
voltage due to change in either load resistance or The power dissipated in the Zener diode is therefore
input current. Hence, its regulation in zero.
Ans. (0) PZ = VZIZ = 9.5 0.01 = 0.095 W
5. The power delivered by the converter of this type is Ans. (0.095)
given by the product of power stored in the primary 7. Refer to the solution of Question6 and
of the switching transformer and the conversion effi-
ciency. That is, the power delivered is given by IC = bIB = bIZ = 0.99 A
Power stored Conversion efficiency Therefore, the power dissipated in the shunt tran-
The power stored is sistor is
1 PT = VCEIC = 10 0.99 = 9.9 W
LP IP f
2
2 Ans. (9.9)
Now,

1. The output voltage of the regulated power supply 500 mA. Assuming that the Zener diode is ideal
shown in the following figure is (i.e., the Zener knee current is negligibly small and
Zener resistance is zero in the breakdown region),
+ the value of R is
R
1 k
15 V DC +
VZ = 3 V +
Unregulated
power Variable
12 V load
source 5V
20 k 40 k Regulated 100 mA to
DC output 500 mA

(a) 7 (b) 70
(a) 3 V (b) 6 V
(d) 14
70
(c) 9 V (d) 12 V (c)
Solution. The voltage at the non-inverting termi- Solution. For a satisfactory operation of the Zener
nal of the opamp is 3 V due to the Zener diode. diode regulator, we have
The voltage at the inverting terminal of the opamp I = IZ + IL where I is the current through resistor
is the same as that at the non-inverting terminal R, IZ is the Zener diode current and IL is the load
due to virtual earth. The current flowing through current.
the 20 k resistor is Also, I = IZ(min) + IL(max).
The value of maximum load current = 500 mA.
3 3 Also, IZ(min)=0, therefore, I = IL(max).
A= mA
20 10 3 20
Vin VZ
I =
The regulated DC output voltage is R
Here, Vin = 12 V and VZ =5 V
103 20 103 + 103 40 103 = 9 V
3 3
12 5
20 20 Therefore, = 500 103
R
Ans. (c) Hence, R = 14
2. In a full-wave rectifier using two ideal diodes, VDC Ans. (d)
and Vm are the DC and the peak values of the volt- 4. The Zener diode in the regulator circuit shown in
ages, respectively, across a resistive load. If PIV the following figure has a Zener voltage of 5.8 V
is the peak inverse voltage of the diode, then the and a Zener knee current of 0.5 mA. The maxi-
appropriate relationships for this rectifier are mum load current drawn from this circuit ensur-
Vm ing proper functioning over the input voltage range
(a) VDC = , PIV = 2Vm between 20 V and 30 V is
p
(b) VDC =
2Vm
, PIV = 2Vm 1000
p
2V Vi VZ = 5.8 V
(c) VDC = m , PIV = Vm
p 20 30 V Load
Vm
(d) VDC = , PIV = Vm
p
Ans. (b) (a) 23.7 mA (b) 14.2 mA
3. In the voltage regulator shown in the following (c) 13.7 mA (d) 24.2 mA
figure, the load current can vary from 100 mA to (GATE 2005: 2 Marks)

Solution. The maximum load current will be 6. If the unregulated voltage increases by 20%, the
drawn when the input voltage is maximum, that is, power dissipation across the transistor Q1
Vi = 30 V (a) Increases by 20% (b) Increases by 50%
Therefore, (c) Remains unchanged (d) Decreases by 20%
30 5.8 = (IL + 0.5 103) 1000
Hence, Solution. New unregulated input voltage is 18 V.

IL = 23.7 mA Therefore,
Ans. (a) VCE = 18 9 = 9 V
Common Data for Questions 5 and 6: A reg- Also, IC = 0.9 A. The power dissipated in the tran-
ulated power supply, shown in the following figure, sistor is
VCEIC = 9 0.9 = 8.1 W
has an unregulated input (UR) of 15 V and gener-
ates a regulated output Vout. Use the component
values shown in the figure. The percentage increase in the power dissipated is
therefore
15 V (UR)
8.1 5.4
Q1 100 = 50%
+ 5.4
Ans. (b)
1 k 10 Vout
12 k 7. For the circuit shown in the following figure,

assume that the Zener diode is ideal with a break-
+
down voltage of 6 V.

6V
6V +
24 k
12 sin w t R VR
5. The power dissipation across the transistor Q1

shown in the figure is
(a) 4.8 W (b) 5.0 W
(c) 5.4 W (d) 6.0 W The waveform observed across R is
(GATE 2006: 2 Marks) 6V
Solution. The voltage at the non-inverting input
terminal of the opamp is 6 V. Therefore, the volt- (a)
age at the inverting terminal of the opamp is 6 V. 6V
Therefore,
6 (12 103 + 24 103 )
(b)
Vout = =9V
(24 103 )
Now, 12 V
VCE = 15 Vout = 15 9 = 6 V
12 V
Therefore, (c)
VE V 9 9
+ E = + = 0.9 A
IC =
12 10 + 24 10
3 3 10 36 10 3 10 6 V
The power dissipated in the transistor is (d)
VCEIC = 6 0.9 = 5.4 W 6 V

Ans. (c) (GATE 2006: 2 Marks)

Solution. When 0 < wt < p/6, diode is OFF and Solution. When Vi = 10 V, the current flowing
no conduction takes place. Therefore, VR = 0. through the circuit is
When p/6 < wt < p, the diode is in the reverse
breakdown region, VZ = 6 V. Therefore, 10 7 3
A= A
210 210
VR = 12 sin wt 6
When p < wt < 2p, the diode is conducting, The output voltage is
VZ=0. Therefore, 3
Vo = 7 + 10 = 7.14 V
VR = 12 sin wt 210
Ans. (b) When Vi = 16 V, the current flowing through the
circuit is
8. For the Zener diode shown in the following figure,
the Zener voltage at knee is 7 V, the knee current 16 7 9
A= A
is negligible and the Zener dynamic resistance is 210 210
10. If the input voltage (Vi) range is from 10 V
The output voltage is
to 16 V, the output voltage (Vo) ranges from
9
Vo = 7 + 10 = 7.43 V
210
200 + Ans. (c)
9. A Zener diode, when used in voltage stabilization
circuits, is biased in
Vi Vo
(a) r everse bias region below the breakdown
voltage
(b) reverse breakdown region
(c) forward bias region
(a) 7.00 to 7.29 V (b) 7.14 V to 7.29 V (d) forward bias constant current mode
(c) 7.14 to 7.43 V (d) 7.29 to 7.43 V (GATE 2011: 1 Mark)
(GATE 2007: 2 Marks) Ans. (a)

PART IV: DIGITAL ELECTRONICS
9
8
Number of Questions
7
6
5 Marks 1
4 Marks 2
3 Total number of questions
2
1
0
2015 2014 2013 2012 2011 2010 2009

512 PART IV: DIGITAL ELECTRONICS
Year Topic
2015 Counters
Logic gates
Microprocessor (8085): Programming
Microprocessor (8085): Memory and I/O interfacing
Microprocessor (8085): DACs
Sequential circuits: Latches and flip-flops, counters
Multiplexers
Boolean algebra
2014 Minimization of Boolean functions
ADCs
Sample and hold circuits
Boolean algebra
Sequential circuits: Latches and flip-flops, counters
Logic gates
Combinational circuits
Multiplexers
Arithmetic circuits
2013 Logic gates
2012 Multiplexers
Arithmetic circuits
Latches and flip-flops
2011 Logic gates
Multiplexers
D/A converter
2010 Logic gates
Multiplexers
Decoders
2009 Logic gates
Multiplexers
Decoders
Minimization of Boolean functions

CHAPTER 23
BOOLEAN ALGEBRA
This chapter discusses the number systems, Boolean algebra and the techniques for minimization of Boolean functions.
23.1 NUMBER SYSTEMS 23.1.1 Decimal Number System
The decimal number system is a radix-10 number system

One of the most important characteristics of a number and therefore has ten different digits or symbols. These
system is the Radix or Base of the number system. The are 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9. All higher numbers after
decimal number system that we are so familiar with can 9 are represented in terms of these 10 digits only.9s
be said to have a radix of ten as it has ten independent complement of a given decimal number is obtained by
digits, that is, 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9. Similarly, subtracting each digit from 9. For example, 9s comple-
binary number system with only two independent digits, ment of (2496)10 would be (7503)10. 10s complement is
0 and 1, is a radix-2 number system. The octal and hexa- obtained by adding 1 to 9s complement. 10s comple-
decimal number systems have a radix (or base) of 8 and ment of (2496)10 is (7504)10.
16, respectively. Radix of the number system also deter-
mines the other two characteristics. Place values of dif-
ferent digits in the integer part of the number are given by 23.1.2 Binary Number System
r0, r1, r2, r3 and so on starting from the digit adjacent to
radix point. For the fractional part, these are r1, r2, r3 The binary number system is a radix-2 number system
and so on again starting with the digit next to the radix with 0 and 1 as the two independent digits. All larger
point. Here, (r) is the radix of the number system. Also, binary numbers are represented in terms of 0 and 1.
maximum numbers that can be written with (n) digits in Starting from the binary point, the place values of dif-
a given number system equals rn. ferent digits in a mixed binary number are 20, 21, 22 and

514 Chapter 23: Boolean algebra
so on (for the integer part) and 21, 22, 23 and so be (C40)16. 16s complement is obtained by adding 1 to
on (for the fractional part). 1s complement of a binary 15s complement. 16s complement of (2AE)16 would be
number is obtained by complementing all its bits, that (D52)16
is, by replacing 0s by 1s and 1s by 0s. For example,
1s complement of (10010110)2 is (01101001)2. 2s com- 23.2 REPRESENTATION OF BINARY
plement of a binary number is obtained by adding 1 to NUMBERS
its 1s complement. 2s complement of (10010110)2 is
(01101010)2.
The different formats used for binary representation of
23.1.3 Octal Number System both positive and negative decimal numbers include (a)
Sign-bit magnitude method (b) ls complement method
The octal number system has a radix of 8 and therefore and (c) 2s complement method.
has eight distinct digits. The independent digits are 0, 1,
2, 3, 4, 5, 6, and 7. The next ten numbers that follow 7, 23.2.1 Sign-Bit Magnitude
for example, would be 10, 11, 12, 13, 14, 15, 16, 17, 20
and 21. In fact, if we omit all the numbers containing the In the sign-bit magnitude representation of positive
digits 8 or 9 or both from the decimal number system, and negative decimal numbers, the most significant bit
we end up with octal number system. The place values (MSB) represents the 'sign with `0 denoting a plus sign
for different digits in the octal number system are 80, 81, and `1 denoting a minus sign. The remaining bits rep-
82 and so on (for the integer part) and 81, 82, 83 and resent the magnitude. In eight-bit representation, while
so on (for the fractional part). 7s complement of a given MSB represents the sign, remaining seven bits repre-
octal number is obtained by subtracting each octal digit sent the magnitude. For example, eight-bit representa-
from 7. For example, 7s complement of (562)8 would be tion of +9 would be 00001001 and that for 9 would be
(215)8. 8s complement is obtained by adding 1 to 7s 10001001. An n-bit binary representation can be used to
complement. 8s complement of (562)8 would be (216)8. represent decimal numbers in the range of (2 n1 1)
to +(2n1 1). That is, eight-bit representation can be
23.1.4 Hexadecimal Number System used to represent decimal numbers in the range of 127
to +127 using sign-bit magnitude format.
The hexadecimal number system is a radix-16 number
system and its 16 basic digits are 0, 1, 2, 3, 4, 5, 6, 7, 8, 23.2.2 1s Complement
9, A, B, C, D, E, and F. The place values or weights of
different digits in a mixed hexadecimal number are 160, In the 1s complement format, the positive numbers
161, 162 and so on (for the integer part) and 161, 162, remain unchanged. The negative numbers are obtained
163 and so on (for the fractional part). The decimal by taking 1s complement of the positive counter parts.
equivalent of A, B, C, D, E and F are 10, 11, 12, 13, 14 For example, +9 will be represented as 00001001 in eight-
and 15, respectively, for obvious reasons. Hexadecimal bit notation and 9 will be represented as 11110110,
number system provides a condensed way of represent- which is 1s complement of 00001001. Again, n-bit nota-
ing large binary numbers stored and processed inside tion can be used to represent numbers in the range of
the computer. One such example is in representing (2n1 1) to +(2n11) using 1s complement format.
addresses of different memory locations. Let us assume Eight-bit representation of 1s complement format can
that a machine has 64K memory. Such a memory has be used to represent decimal numbers in the range of
64K (= 216 = 65536) memory locations and needs 65536 127 to +127.
different addresses. These addresses can be designated
as 0 to 65535 in decimal number system and 00000000 23.2.3 2s Complement
00000000 to 11111111 11111111 in the binary number
system. Decimal number system is not used in comput- In the 2s complement representation of binary numbers,
ers and the binary notation mentioned here appears too the MSB represents the sign with a `0 used for a plus
cumbersome and inconvenient to handle. In the hexa- sign and `1 for a minus sign. The remaining bits are used
decimal number system, 65536 different addresses can be for representing magnitude. The positive magnitudes are
expressed with four digits from 0000 to FFFF. Similarly, represented in the same way like we do in case of sign-bit
the contents of the memory when represented in hexa- or ls complement representation. The negative magni-
decimal form are very convenient to handle. 15s comple- tudes are represented by 2s complement of their posi-
ment is obtained by subtracting each hexadecimal digit tive counterparts. +9 would be represented as 00001001
from 15. For example, 15s complement of (3BF)16 would and 9 would be written as 11110111. Note that if 2s

23.3 NUMBER CONVERSIONS 515
complement of the magnitude of +9 gives the magnitude 3. The decimal equivalent of the hexadecimal number
of 9, then the reverse process is also true, that is, 2s (1E0.2A)16 is determined as follows:
complement of magnitude of 9 gives the magnitude of For the integer part 1E0, the decimal equivalent is
+9. n-bit notation of 2s complement format can be used to
represent all decimal numbers in the range of +(2n1 1) 0 160 + 14 161 + 1 162 = 0 + 224 + 256
to (2n1). 2s complement format is very popular as
= 480
it is very easy to generate 2s complement of a binary
number and also because arithmetic operations are rela- For the fractional part 2A, the decimal equivalent is
tively easier to perform when the numbers are repre-
sented in 2s complement format. 2 161 + 10 162 = 0.164
Therefore, the decimal equivalent of (1E0.2A)16 is

23.3 NUMBER CONVERSIONS (480.164)10
23.3.2 Decimal-to-Binary Conversion

23.3.1 Finding Decimal Equivalent
As outlined earlier, the integer and the fractional parts
The decimal equivalent of a given number in another are worked on separately. For the integer part, the binary
number system is given by the sum of all the digits mul- equivalent can be found by successively dividing the inte-
tiplied by their respective place values. The integer and ger part of the number by 2 and recording the remain-
fractional parts of the given number should be treated ders till the quotient becomes 0. The remainders written
separately. Following are some examples: in the reverse order constitute the binary equivalent. For
the fractional part, it is found by successively multiply-
1. The decimal equivalent of the binary number ing the fractional part of the decimal number by 2 and
(1001.0101)2 is determined as follows: recording the carry till the result of multiplication is `0.
For the integer part 1001, the decimal equivalentis The carry sequence written in forward order constitutes the
binary equivalent of fractional part of the decimal number.
If the result of multiplication does not seem to be heading
1 20 + 0 21 + 0 22 + 1 23 = 1 + 0 + 0 + 8 towards zero in case of fractional part, the process may be
=9 continued only till the requisite number of equivalent bits
has been obtained. This method of decimalbinary conver-
For the fractional part .0101, the decimal equiva- sion is popularly known as the double-dabble method. The
lent is process can be best illustrated with the help of an example
as follows: Let us find the binary equivalent of (13.375)10:
0 2 1 + 1 22 + 0 23 + 1 24
Integer part = 13
= 0 + 0.25 + 0 + 0.0625
= 0.3125 Divisor Dividend Remainder
2 13
Therefore, the decimal equivalent of (1001.0101)2
is (9.3125)10 2 6 1
2 3 0
2. The decimal equivalent of an octal number 2 1 1
(137.21)8 is determined as follows:
For the integer part 137, the decimal equivalent is 0 1
7 80 + 3 81 + 1 82 = 7 + 24 + 64 Therefore, the binary equivalent of (13)10 is (1101)2

= 95 For the fractional part 0.375, we get
0.375 2 = 0.75 with a carry of 0

For the fractional part .21, the decimal equivalent is
0.75 2 = 0.5 with a carry of 1
2 81 + 1 82 = 0.265 0.5 2 = 0 with a carry of 1
Thus, the binary equivalent of (0.375)10 is (.011)2

Therefore, the decimal equivalent of (137.21)8 is
(95.265)10 Therefore, the binary equivalent of (13.375)10 is (1101.011)2

516 Chapter 23: BOOLEAN ALGEBRA
23.3.3 Decimal-to-Octal Conversion 23.3.5 Octal-to-Binary and Binary-to-Octal

Conversion
The process of decimal-to-octal conversion is similar to
what it is in case of decimal-to-binary conversion. The An octal number can be converted into its binary equiv-
progressive division in case of the integer part and pro- alent by replacing each octal digit by its three-bit binary
gressive multiplication while working on the fractional equivalent. Binary number can be converted into an
part here is by `8 which is the radix of the octal number equivalent octal number by splitting the integer and the
system. Again, integer and fractional parts of the deci- fractional parts in groups of three bits starting from the
mal number are treated separately. The process can be binary point on both sides. 0s can be added to complete
best illustrated with the help of an example as follows: the outside groups if needed. The process can be best
Let us find the octal equivalent of (73.75)10: illustrated with the help of an example as follows: Let
us find the binary equivalent of (374.26)8 and the octal
Integer part = 73 equivalent of (1110100. 0100111)2
Divisor Dividend Remainder Given octal number is (374.26)8

The binary equivalent of (374.26)8 is
8 73
8 9 1 (011 111 100.010 110)2 = (011111100.010110)2
8 1 1
0s if any on the extreme left of the integer part and
0 1 extreme right of the fractional part of the equivalent
binary number should be omitted. Therefore,
The octal equivalent of (73)10 = (111)8 (011111100.010110)2 = (11111100.01011)2

For the fractional part 0.75, we get
Given binary number is (1110100. 0100111)2 whose
0.75 8 = 0 with a carry of 6 octal equivalent is determined as follows:

(1110100.0100111)2 = (1 110 100.010 011 1)2
The octal equivalent of (0.75)10 = (.6)8
= (001 110 100.010 011 100)2
Therefore, the octal equivalent of (73.75)10 = (111.6)8 = (164.234)8
23.3.4 Decimal-to-Hexadecimal Conversion 23.3.6 Hexadecimal-to-Binary and Binary-to-

Hexadecimal Conversion
The process of decimal to hexadecimal conversion is also
similar. Since the hexadecimal number system has a base A hexadecimal number can be converted into its binary
of 16, the progressive division and multiplication factor equivalent by replacing each hexadecimal digit by its
in this case is 16. The process is illustrated further with four-bit binary equivalent. A given binary number can
the help of an example as follows: Let us determine the be converted into an equivalent hexadecimal number by
hexadecimal equivalent of (82.25)10: splitting the integer and the fractional parts in groups
of four bits starting from the binary point on both
Integer part = 82 sides. 0s can be added to complete the outside groups,
if needed. The process can be best illustrated with the
Divisor Dividend Remainder help of an example as follows: Let us find the binary
16 82 equivalent of (17E.F6)16 and hexadecimal equivalent of
(1011001110.011011101)2.
16 5 2
Given hexadecimal number is (17E.F6)16
0 5
The binary equivalent of (17E.F6)16 is
The hexadecimal equivalent of (82)10 = (52)16 (0001 0111 1110.1111 0110)2

= (000101111110.11110110)2= (101111110.1111011)2
For the fractional part 0.25, we get
0.25 16 = 0 with a carry of 4 0s if any, on the extreme left of the integer part
and extreme right of the fractional part have been
Therefore, the hexadecimal equivalent of (82.25)10 is (52.4)16 omitted.

23.4 FLOATING POINT NUMBERS 517
The given binary number is representation increases the range of numbers, from the
smallest to the largest, that can be represented using a
(1011001110.011011101)2= (10 1100 1110.0110 1110 1)2 given number of digits. Floating point numbers are in
general expressed in the form
The hexadecimal equivalent of the given binary
number is N = m be (23.1)
(0010 1100 1110.0110 1110 1000)2 = (2CE.6E8)16 where m is the fractional part called mantissa, e is the
integer part called exponent and b is the base of the
23.3.7 Hexadecimal-to-Octal and Octal-to- number system or numeration. The fractional part m is
Hexadecimal Conversion a p-digit number of the form (d.dddd...dd) with each
digit d being an integer between 0 and (b 1) inclusive.
For the hexadecimaloctal conversion, the given hexadeci- If the leading digit of m is non-zero, then the number is
mal number is first converted into its binary equivalent said to be normalized.
which is further converted into its octal equivalent. An Equation (23.1) in the cases of decimal, hexadecimal and
alternative approach is first to convert the given hexadeci- binary number systems, respectively, will be written as
mal number to its decimal equivalent and then convert the
decimal number to an equivalent octal number. Former Decimal system: N = m 10e (23.2)
method is definitely more convenient and straight forward. Hexadecimal system: N = m 16 e
(23.3)
For the octalhexadecimal conversion, the octal Binary system: N = m 2 e
(23.4)
number may first be converted into an equivalent binary
number and then the binary number transformed to its For example, decimal numbers 0.0003754 and 3754 will
hexadecimal equivalent. The other option is first to con- be represented in floating point notation as 3.754 104
vert the given octal number to its decimal equivalent and 3.754 103, respectively. A hexadecimal number
and then convert the decimal number to its hexadecimal 257.ABF will be represented as 2.57ABF 162. In the
equivalent. The former approach is definitely the pre- case of normalized binary numbers, the leading digit,
ferred one. Two types of conversions are illustrated in which is the MSB, is always `1 and thus does not need
the following example: Let us find the octal equivalent of to be stored explicitly. Therefore, if the numbers are
(2F.C4)16 and the hexadecimal equivalent of (762.013)8: required to be normalized, binary numbers 11011.011
and .00011011 will be written in floating point notation
Given hexadecimal number = (2F.C4)16 as .11011011 25 and .11011 23, respectively.
The binary equivalent of (2F.C4)16 is Also, while expressing a given mixed binary number
(0010 1111.1100 0100)2 = (00101111.11000100)2 as a floating point number, the radix point is so shifted
as to have the MSB immediately to the right of radix
= (101111.110001)2 point as a `1. Both mantissa as well as exponent can
= (101 111.110 001)2 have a positive or a negative value.
= (57.61)8 As an example, the mixed binary number (110.1011)2
will be represented in floating point notation as .1101011
The given octal number = (762.013)8 23 = .1101011 e + 0011. Also, .1101011 is the man-
The binary equivalent of (762.013)8 equivalent is tissa and e + 0011 implies that the exponent is +3. As
another example, (0.000111)2 will be written as .111e
(111 110 010.000 001 011)2 0011 with .111 being the mantissa and e 0011 imply-
ing an exponent of 3. Also, (0.00000101)2 may be
written as .101 25 = .101e 0101, where .101
= (111110010.000001011)2
= (0001 1111 0010.0000 0101 1000)2 is the mantissa and e 0101 indicates an exponent of
= (1F2.058)16 5. If we wanted to represent the mantissas using eight
bits, then .1101011 and .111 would be represented as
.11010110 and .11100000.
23.4 FLOATING POINT NUMBERS
23.5 BCD NUMBERS
Floating point notation can be used to conveniently rep-
resent both large and small fractional or mixed num-
bers. This makes the process of arithmetic operations Binary coded decimal, abbreviated as BCD, is a type of
on these numbers relatively much easier. Floating point binary code used to represent a given decimal number in

an equivalent binary form. The BCD equivalent of a dec- ignoring the carry, if any. That is, if the MSB and
imal number is written by replacing each decimal digit in the bit adjacent to it are both `1, then the corre-
integer and fractional parts by its four-bit binary equiva- sponding Gray code bit would be a `0.
lent. As an example, the BCD equivalent of (23.15)10 is 3. The third MSB, adjacent to second MSB, in the
written as (0010 0011.0001 0101)BCD. The BCD code gray code number is obtained by adding the second
described above is more precisely known as 8421 BCD MSB and the third MSB in the binary number and
code with 8, 4, 2 and 1 representing the weights of dif- ignoring the carry, if any.
ferent bits in the four-bit groups starting from MSB and 4. The process continues till we obtain the LSB of
proceeding towards least significant bit (LSB). the Gray code number by the addition of the LSB
A given BCD number can be converted into an equiv- and the next higher adjacent bit of the binary
alent binary number by first writing its decimal equiva- number.
lent and then converting it into its binary equivalent. The conversion process is further illustrated with the
While the first step is straightforward, the second is as help of an example showing step-by-step conversion of
explained in the previous section. As an example, we (1011)2 into its gray code equivalent.
shall find the binary equivalent of the BCD number 0010
1001.0111 0101 Binary :1011
Gray code : 1
BCD number: 0010 1001.0111 0101
Binary :1011
Corresponding decimal number: 29.75
Gray code : 1 1
Binary equivalent of 29.75 can be determined to be
11101 for the integer part and .11 for the fractional Binary :1011
part. Gray code : 1 1 1
Therefore, (0010 1001.0111 0101)BCD = (11101.11)2 Binary :1011
The process of binary-to-BCD conversion is the same Gray code : 1 1 1 0
as the process of BCD-to-binary conversion executed in
A given Gray code number can be converted into
reverse order. A given binary number can be converted
its binary equivalent by going through the following
into an equivalent BCD number by first determining its
steps.
decimal equivalent and then writing the corresponding
BCD equivalent. As an example, we shall find the BCD 1. Begin with the MSB. The MSB of the binary
equivalent of the binary number 10101011.101 number is the same as the MSB of the Gray code
number.
The decimal equivalent of this binary number can be 2. The bit next to the MSB (second MSB) in the
determined to be 171.625 binary number is obtained by adding MSB in the
The BCD equivalent can then be written as 0001 0111 binary number to the second MSB in the Gray
0001.0110 0010 0101 code number and disregarding the carry, if any.
3. The third MSB in the binary number is obtained
by adding second MSB in the binary number to
23.6 GRAY CODE NUMBERS the third MSB in the Gray code number. Again,
carry, if any, is to be ignored.
The conversion process is further illustrated with
It is an unweighted binary code in which two succes-
the help of an example showing step-by-step con-
sive values differ only by one bit. Due to this feature,
version of Gray code number 1110 into its binary
the maximum error that can creep into a system using
equivalent:
binary Gray code to encode the data is much less than
the worst-case error encountered in the case of straight Gray code : 1 1 1 0
Binary : 1
binary encoding instead.
A given binary number can be converted into its Gray
Gray code : 1 1 1 0
code equivalent by going through the following steps:
Binary : 1 0
1. Begin with the MSB of the binary number. The
MSB of the gray code equivalent is the same as the Gray code : 1 1 1 0
MSB of the given binary number. Binary : 1 0 1
2. The second MSB, which is adjacent to MSB, in the
Gray code : 1 1 1 0
gray code number, is obtained by adding the MSB
and the second MSB of the binary number and Binary : 1 0 1 1

23.7 BOOLEAN ALGEBRA AN INTRODUCTION 519
23.7 BOOLEAN ALGEBRA AN (P + Q) (R + S ) (P + Q + R) (23.6)

INTRODUCTION
The complement of a variable is not considered as a
separate variable. Each occurrence of a variable or its
Boolean algebra, quite interestingly, is simpler than the complement is called a literal. In Eqs. (23.5) and (23.6)
ordinary algebra that we have studied at high school. above, there are eight and seven literals, respectively. A
Boolean algebra too is composed of a set of symbols and term is the expression formed by literals and operations
a set of rules to manipulate these symbols. But, this is at one level. Equation (23.5) has five terms including
the only similarity between the two forms of algebra. four AND terms and the OR term that combines the
Key differences include the following: first level AND terms.
1. In ordinary algebra, the alphabetical symbols,
which are considered as variables, could take on
23.7.2 Equivalent and Complement of Boolean
any number of values including infinity. In Boolean
algebra, the alphabetical symbols can take on either
Expressions
of the two values, that is, 0 and 1.
Two given Boolean expressions are said to be equivalent
2.The values assigned to a variable have a numeri-
if one of them equals `1 only when the other equals `1
cal significance in ordinary algebra whereas in its
and also one equals `0 only when the other equals `0.
Boolean counterpart, they have a logical significance.
They are said to be complement of each other if one
3. While ` and `+, respectively, are the signs of
expression equals `1 only when the other equals `0 and
multiplication and addition in ordinary algebra, in
vice versa. The complement of a given Boolean expres-
Boolean algebra, ` means an AND operation and
sion is obtained by complementing each literal, that is,
`+ means an OR operation. For instance, A+B
changing all ` to `+ and all `+ to `, all 0s to 1s and
in ordinary algebra is read as À plus B while the
all 1s to 0s. The following examples give some Boolean
same in Boolean algebra is read as À OR B. Basic
expressions and their complements:
logic operations such as AND, OR and NOT are
Given Boolean expression: A B + A B
discussed at length in Chapter 24.
(23.7)
4. More specifically, Boolean algebra captures the
essential properties of both logic operations such
as AND, OR and NOT and set operations such Corresponding complement: (A + B) (A + B) (23.8)
as intersection, union and complement. As an
illustration, the logical assertion that both a state- Given Boolean expression: (A + B) (A + B) (23.9)
ment and its negation cannot be true has a counter-
part in set theory, which says that the intersection
of a subset and its complement is a null (or empty) Corresponding complement: A B + A B (23.10)
set.
When ORed with its complement, a Boolean expression
5. Boolean algebra may also be defined to be a set
yields `1 and when ANDed with its complement it yields
A supplied with two binary operations of logical
`0. The ` sign is usually omitted in writing Boolean
AND (), logical OR (V), a unary operation of
expressions and is implied merely by writing the literals
logical NOT () and two elements, namely, logi-
in juxtaposition. For instance, AB would normally be
cal FALSE (0) and logical TRUE (1). This set is
written as AB.
such that for all elements of this set, the postulates
or axioms relating to the associative, commuta-
tive, distributive, absorption and complementation 23.7.3 Dual of a Boolean Expression
properties of these elements hold good. These pos-
tulates are described in the following sections. The dual of a Boolean expression is obtained by
r eplacing all ` by `+ operations, all `+ operations by `
23.7.1 Variables, Literals and Terms in Boolean operations, all 0s by 1s, all 1s by 0s and leaving
Expressions all literals unchanged. The following examples give
some Boolean expressions and the corresponding dual
Variables are the different symbols in a Boolean expres- expressions:
sion. They may take on the value `0 or `1. For instance,
in Eq. (23.5), A, B and C are the three variables. In Eq. Given Boolean expression: A B + A B (23.11)
(23.6), P, Q, R and S are the variables.
A+AB +AC +ABC (23.5) Corresponding dual expression: (A + B) (A + B) (23.12)

Given Boolean expression: (A + B) (A + B) (23.13) 23.8.2.2Theorem 2: Operations with `0

and `1
Corresponding dual expression: A B + A B (23.14)
(a) 1 X = X and
(b) 0 + X = X
Duals of Boolean expressions are mainly of interest in the
(23.16)
study of Boolean postulates and theorems. Otherwise,
there is no general relationship between the values of
Here, `X could be a variable, a term or even a large
dual expressions. That is, both of them may equal `1
expression. According to this theorem, ANDing a
or `0. One may even equal `1 while the other equals
Boolean expression to `1 or ORing `0 to it makes no
`0. The fact that dual of a given logic equation is also a
difference to the expression:
valid logic equation, leads to many more useful laws of
Boolean algebra. The principle of duality has been put to For X = 0, LHS = 1.0 = 0 = RHS
ample use during the discussion on postulates and theo-
rems of Boolean algebra. The postulates and theorems, For X = 1, LHS = 1.1 = 1 = RHS
to be discussed in the paragraphs to follow, have been Also
presented in pairs with the one being dual of the other.
1(Boolean expression) = Boolean expression
0 + (Boolean expression) = Boolean expression
23.8 POSTULATES AND THEOREMS
OF BOOLEAN ALGEBRA For example,
1(A + BC + CD) = 0 + (A + BC + CD)

= A + BC + CD
23.8.1 Postulates
The important postulates of Boolean algebra are as follows: 23.8.2.3Theorem 3: Idempotent or

Identity Laws
1.1 1 = 1, 0 + 0 = 0
2.1 0 = 0 1 = 0, 0 + 1 = 1 + 0 = 1 (a) X X X X = X and
3.0 0 = 0, 1 + 1 = 1 (b) X + X + X + + X = X (23.17)
4.1 = 0, 0 = 1 Theorems 3(a) and 3(b) are known by the name of

idempotent laws which are also known as identity
laws. Theorem 3(a) is a direct outcome of an AND
23.8.2 Theorems of Boolean Algebra gate operation whereas Theorem 3(b) represents an
OR gate operation when all the inputs of the gate
The various theorems of Boolean algebra can be used to have been tied together. The scope of idempotent
simplify complex Boolean expressions and also to trans- laws can be expanded further by considering `X to
form the given Boolean expression into a more useful be a term or an expression. Following is an example
and meaningful equivalent expression. The theorems are showing simplifying a Boolean expression using idem-
presented as pairs with the two theorems in a given pair potent laws:
being dual of each other.
(A B B + C C ) ( A B B + A B + C C )
23.8.2.1Theorem 1: Operations with `0
and `1 = (A B + C ) (A B + A B + C )
= (A B + C ) (A B + C )
(a) 0 X = 0 and
= AB+C
(b) 1 + X = 1 (23.15)
Here, `X is not necessarily a single variable it could 23.8.2.4Theorem 4: Complementation Law

be a term or even a large expression. Following are some
examples: (a) X X = 0 and
0(AB + BC + CD) = 0, 1 + (AB + BC + CD) = 1 (b) X + X = 1 (23.18)
0(A+ BC) = 0, 1 + A + BC = 1
According to this theorem, in general, any Boolean
where A, B and C are Boolean variables. expression when ANDed to its complement yields `0 and

23.8 POSTULATES AND THEOREMS OF BOOLEAN ALGEBRA 521
when ORed to its complement yields `1 irrespective of the result of first and second variables with the third
the complexity of the expression: variable or by ORing the first variable with the result
of ORing of second and third variable or even by ORing
For X = 0, X = 1. Therefore, X X = 0 1 = 0 the second variable with the result of ORing of first and
For X = 1, X = 0. Therefore, X X = 1 0 = 0 third variable. According to Theorem 6(b), when three
variables are being ANDed, it is immaterial whether you
Hence, Theorem 4(a) is proved. Since Theorem 4(b) is dual do this by ANDing the result of ANDing of first and
of Theorem 4(a), its proof is implied. Following are some second variables with the third variable or by ANDing
examples showing application of complementation law: the result of ANDing of second and third variables
with the first variable or even by ANDing the result of
(A + BC )(A + BC ) = 0 and (A + BC ) + (A + BC ) = 1
ANDing of third and first variables with the second vari-
(A B C ) (A B C ) = 0 and (A B C ) + (A B C ) = 1 able. For example,
23.8.2.5Theorem 5: Commutative Laws AB + (CD + EF ) = CD + (AB + EF ) = EF + (AB + CD)
(a) X + Y = Y + X and
AB (CD EF ) = CD (AB EF ) = EF (AB CD)
(b) XY = YX (23.19)
Theorem 5(a) implies that the order in which vari- Theorems 6(a) and (b) are further illustrated by logic
ables are added or ORed is immaterial. That is, result diagrams of Figs. 23.1(a) and (b).
of A OR B is same as that of B OR A. Theorem 5(b)
implies that order in which variables are ANDed is 23.8.2.7Theorem 7: Distributive Laws
also immaterial. Result of A AND B is same as that
of B AND A. (a) X (Y + Z ) = X Y + X Z and
(b) X + YZ = (X + Y ) (X + Z ) (23.21)
23.8.2.6Theorem 6: Associative Laws
Theorem 7(b) is the dual of Theorem 7(a). Distribution
(a) X + (Y + Z ) = Y + (Z + X ) = Z + (X + Y ) and
law implies that a Boolean expression can always be
(b) X(YZ ) = Y (ZX ) = Z(XY ) (23.20) expanded term by term. Also, in the case of expression
being sum of two or more than two terms having a common
Theorem 6(a) says that when three variables are being variable, the common variable can be taken common in
ORed, it is immaterial whether you do this by ORing a similar way that we do in the case of ordinary algebra.
Y X
X+(Y+Z) Z+(X+Y )
Z Y
X Z
(a)
Y X
X(YZ) Z(XY )
Z Y
X Z
(b)
Figure 23.1| Associative laws.

X
Y
X(Y+Z) Y
XY+XZ
Z
X
Z
(a)
X
Y
X+YZ Y
Z (X+Y )(X+Z )
X
(b)
Figure 23.2| Distributive laws.
Theorems 7(a) and (b) are further illustrated by factor. The expression then reduces to this common
logic diagrams shown in Figs.23.2(a) and (b). As an factor. This interpretation can be usefully employed to
illustration, Theorem 7(a) can be used to simplify simplify many a complex Boolean expression. As an illus-
(AB + AB + AB + AB) as follows: tration, let us consider the following Boolean expression:
(AB + AB + AB + AB) = A(B + B) + A(B + B) ABCD + ABCD + ABCD + ABCD

= A 1+ A 1 = A + A = 1 + ABCD + ABCD + ABCD + ABCD
Theorem 7(b) can be used to simplify (A + B)(A + B) In the above expression, variables B, C and D are present
in all the eight possible combinations and variable À is
(A + B)(A + B) as follows: the common factor in all the eight product terms. With
the application of theorem 8(a), this expression reduces
(A + B)(A + B)(A + B)(A + B) = (A + B B)(A + B B) to À. Similarly, with the application of Theorem 8(b),
= (A + 0)(A + 0) ( A + B + C ) ( A + B + C ) ( A + B + C ) (A + B + C )
= AA = 0
also reduces to À as variables `B and `C are present
in all the four possible combinations in sum terms and
variable À is the common factor in all the terms.
23.8.2.8Theorem 8
23.8.2.9Theorem 9
(a) XY + XY = X and
(a) (X + Y ) Y = XY and
(b) (X + Y )(X + Y ) = X (23.22)
(b) XY + Y = X + Y (23.23)
It is a special case of theorem 7 as
XY + XY = X(Y + Y ) = X 1 = X and 23.8.2.10Theorem 10: Absorption Law or

Redundancy Law
(X + Y )(X + Y ) = X + Y Y = X + 0 = X
(a) X + XY = X and
This theorem, however, has another interesting inter-
(b) X(X + Y ) = X (23.24)
pretation. Referring to Theorem 8(a), there are two two-
variable terms in the LHS of the expression. One of the Proof of absorption law is straightforward:
variables `Y is present in all possible combinations in
this expression while the other variable `X is a common X + X Y = X (1 + Y ) = X 1 = X

23.8 POSTULATES AND THEOREMS OF BOOLEAN ALGEBRA 523
Theorem 10(b) is dual of Theorem 10(a) and hence proved. case of product-of-sums expression will be redundant.
The crux of this simplification theorem is that if a For example,
smaller term appears in a larger term, then the larger
term is redundant. Following examples further illustrate ABC + ACD + BCD + BCD + ACD
the underlying concept: = ABC + ACD + BCD
A + AB + ABC + ABC + CBA = A and Here, the last two terms are redundant.
(A + B + C ) (A + B) (C + B + A) = A + B
23.8.2.13Theorem 13: De Morgans
23.8.2.11Theorem 11 Theorem
(a) ZX + ZXY = ZX + ZY and (a) [X1 + X2 + X3 + + Xn ] = X1 X2 X3 Xn

(b) (Z + X ) (Z + X + Y ) = (Z + X ) (Z + Y ) (23.25) (23.27)
A useful interpretation of this theorem is that when a (b) [X1 X2 X3 Xn ] = [X1 + X2 + X3 + + Xn ]

smaller term appears in a larger term except for one of the (23.28)
variables appearing as a complement in the larger term,
then the complemented variable is redundant. Following According to the first theorem, complement of a sum
example further illustrate the underlying concept: equals product of complements while according to the
second theorem, complement of a product equals sum
(A + B) (A + B + C ) (A + B + D) of complements. Figures 23.3(a) and (b) show logic dia-
= (A + B) (B + C ) (A + B + D) gram representation of De Morgans theorem. While the
first theorem can be interpreted to say that a multi-input
=(A + B) (B + C ) (B + D)
NOR gate can be implemented as a multi-input bubbled
AND gate; the second theorem, which is dual of the first,
23.8.2.12Theorem 12: Consensus Theorem can be interpreted to say that a multi-input NAND gate
can be implemented as a multi-input bubbled OR gate.
(a) XY + XZ + YZ = XY + XZ and
De Morgans theorem can be proved as follows: Let us
(b) (X + Y ) (X + Z ) (Y + Z ) = (X + Y ) (X + Z ) assume that all variables are in logic `0 state. In this case,
(23.26)
A useful interpretation of Theorem 12 is as follows. If in a LHS = [X1 + X2 + X3 + + Xn ]
given Boolean expression, we can identify two terms with = [0 + 0 + 0 + + 0 ] = 0 = 1
one having a variable and the other having its comple-
ment, then a term that is formed by product of remain-
RHS = X1 X2 X3 Xn
ing variables in the two terms in case of sum-of-products
expression or by a sum of the remaining variables in = 0 0 0 0 = 111 1 = 1
X1 X1
X2 X2
Xn Xn
(a)
X1 X1
X2 X2
X3 Xn
(b)
Figure 23.3| De Morgans theorem.

Therefore, LHS = RHS. Now, let us assume that any 23.8.2.16Theorem 16

one of the (n) variables, say (X1), is in logic HIGH state.
(a) f (X, X, Y , Z , ) = X f (1, 0, Y , Z , )
LHS = [X1 + X2 + X3 + + Xn ]
+ X f (0, 1, Y , Z , ) (23.32)
= [1 + 0 + 0 + + 0 ] = 1 = 0
(b) f (X, X, Y , Z , ) = [X + f (0, 1, Y , Z , )]
RHS = X1 X2 X3 Xn
[X + f (1, 0, Y , Z , )] (23.33)
= 1 0 0 0 = 0 1 1 1 = 0
The proof of Theorem 16(a) is straight forward and is
Therefore, LHS = RHS. The same holds good when more given as follows:
than one or all variables are in logic `1 state. Therefore,
theorem 13(a) stands proved. Since Theorem 13(b) is dual f (X , X , Y , Z , )
of Theorem 13(a), same also stands proved. Theorem
= X f (X , X , Y , Z , ) + X f (X , X , Y , Z , )
13(b) though can be proved on similar lines.
= X f (1, 0, Y , Z , ) + X f (0, 1, Y , Z , )
23.8.2.14Theorem 14: Transposition
Theorem Also,
f (X , X , Y , Z , )
(a) XY + XZ = (X + Z )(X + Y ) and
= [X + f (X , X , Y , Z , )] [X + f (X , X , Y , Z , )]
(b) (X + Y )(X + Z ) = XZ + XY (23.29) = [X + f (0, 1, Y , Z , )] [X + f (1, 0, Y , Z , )]
This theorem can be applied to any sum-of-products or 23.8.2.17Theorem 17: Involution Law
product-of-sums expression having two terms provided
that a given variable in one term has its complement in X = X (23.34)
the other. For example,
It is an elementary theorem that goes by the name of
involution law which says that complement of comple-
AB + AB = (A + B)(A + B) and
ment of an expression leaves the expression unchanged.
AB + AB = (A + B)(A + B) Also, dual of dual of an expression is the original
expression. This theorem forms the basis of finding the
Incidentally, the first expression is the representation equivalent product-of-sums expression for a given sum-
of a two-input EX-OR gate while the second expres- of-products expression and vice versa.
sion gives two forms of representation of a two-input
EX-NOR gate.
23.9 SIMPLIFICATION OF BOOLEAN
23.8.2.15Theorem 15 FUNCTIONS
(a) X f (X, X, Y , Z , ) = X f (1, 0, Y , Z , ) (23.30)
The primary objective of all simplification procedures
(b) X + f (X , X , Y , Z , ) = X + f (0, 1, Y , Z , ) is to obtain an expression that has minimum number of
terms. Obtaining an expression with minimum number
(23.31) of literals is usually the secondary objective. In case there

is more than one possible solution with same number of
According to Theorem 15(a), if a variable X is multiplied terms, the one having minimum number of literals is the
by an expression containing X and X in addition to other choice. There are two major techniques used for simpli-
variables, then all Xs andXs can be replaced by 1s fying Boolean functions, which are as follows:
and 0s, respectively. This would be valid as X X = X
and X 1 = X . Also, X X = 0 and X 0 = 0 .
1. QuineMcCluskey tabular method
2. Karnaugh map method
According to Theorem 15(b), if a variable X is added
to an expression containing terms having X and X in Before we discuss these techniques we will briefly describe
addition to other variables, then all Xs can be replaced sum-of-products and product-of-sums Boolean expres-
by 0s and all Xs can be replaced by ls. This is again sions. The given Boolean expression will be in either of
permissible as X + X as well as X + 0 equals X. Also, the two forms and the objective will be to find a mini-
both X + X and X + 1 equal `1. mized expression in the same or the other form.

23.9 SIMPLIFICATION OF BOOLEAN FUNCTIONS 525
23.9.1 Sum-of-Products and Product-of-Sums them, they are also used in the application of minimi-
Boolean Expressions zation techniques such as QuineMcCluskey tabular
method and Karnaugh mapping method for simplifying
The sum-of-products expression, which is also known as a given Boolean expression. The expanded form, sum-of-
minterm, contains the sum of different terms with each products or product-of-sums, is obtained by including all
term being either a single literal or a product of more possible combinations of missing variables. As an illus-
than one literal. It can be obtained from the truth table tration, let us consider the following sum-of-products
directly by considering those input combinations which expression:
produce logic `1 at the output. Each such input combina-
tion produces a term. The different terms are given by AB +BC +ABC +AC
product of corresponding literals. The sum of all terms
gives the expression. It is a three-variable expression. Expanded versions of
Product-of-sums expression, which is also known as different minterms can be written as follows:
1. A B = A B(C + C ) = A B C + A B C
maxterm, contains the product of different terms with
each term being either a single literal or a sum of more
than one literal. It can be obtained from the truth table 2. B C = B C(A + A) = B C A + B C A
by considering those input combinations that produce
logic `0 at the output. Each such input combination 3. A C = A C(B + B) = A C B + A C B
gives a term and product of all such terms gives the
expression. Different terms are obtained by taking sum The term A B C is a complete term and has no miss-
of corresponding literals. Here, `0 and `1 do mean the ing variable. Therefore, the expanded sum-of-products
uncomplemented and complemented variables, respec- expression is given by
tively, unlike sum-of-products expressions where `0 and
`1 do mean complemented and uncomplemented vari- ABC +ABC +ABC +ABC
ables, respectively. +ABC +ABC +ABC
= ABC +ABC +ABC +ABC
Transforming given product-of-sums expression into
an equivalent sum-of-products expression is a straight
forward process. Multiplying out the given expression +ABC +ABC
and carrying out the obvious simplification provides the
equivalent sum-of-products expression. For example, As another illustration, consider the following product-
of-sums expression.
(A + B) (A + B) = A A + A B + B A + B B
(A + B) (A + B + C + D)
= 0+AB+BA+0 = AB+AB
It is four-variable expression with A, B, C and D being
A given sum-of-products expression can be trans-
the four variables. (A + B) in this case expands to
formed into an equivalent product-of-sums expression
by (a) taking dual of given expression (b) multiplying
out different terms to get the sum-of-products form (c) (A + B + C + D) (A + B + C + D) (A + B + C + D)
removing redundancy and (d) taking a dual to get the (A + B + C + D)
equivalent product-of-sums expression. For example, let
us consider the example, A B + A B : Therefore, the expanded product-of-sums expression is
given by
Dual of given expression = (A + B) (A + B)
(A + B + C + D) (A + B + C + D) (A + B + C + D)
(A + B) (A + B) = A A + A B + B A + B B
(A + B + C + D) (A + B + C + D)
= 0+AB+BA+0 = AB+AB
(A + B + C + D) (A + B + C + D)
Dual of (A B + A B) = (A + B) (A + B) =
(A + B + C + D) (A + B + C + D)
Therefore, A B + A B = (A + B) (A + B)
23.9.3 Canonical Form of Boolean Expressions

23.9.2 Expanded Forms of Boolean Expressions
An expanded form of Boolean expression, where each
Expanded sum-of-products and product-of-sums forms term contains all Boolean variables in their true or
of Boolean expressions are useful not only in analyzing complemented form, is also known as the canonical

form of the expression. As an illustration, f (A B, C ) The binary numbers represented by different sum terms
(A B C + A B C + A B C ) is a Boolean function of are 0011, 1011, 1100 and 0111 (True and complemented
three variables expressed in canonical form. This func- variables here represent `0 and `1, respectively). These
tion after simplification reduces to A B + A B C and numbers when arranged in ascending order are 0011,
loses its canonical form. 0111, 1011 and 1100. Therefore,
f (A, B, C , D) = P 3, 7, 11, 12
23.9.4 S and P Nomenclature
and
S and P notations are used to represent sum-of-products f (A, B, C , D) = P 0, 1, 2, 4, 5, 6, 8, 9, 10, 13, 14, 15.
and product-of-sums Boolean expressions, respectively.
Let us consider the following Boolean function.
23.9.5 QuineMcCluskey Tabular Method
f (A, B, C , D) = ABC + ABCD + ABCD + ABCD
QuineMcCluskey tabular method of simplification is
We shall represent this function using S notation. The based on the complementation theorem, which says that
first step is to write expanded sum-of-products given by
XY + XY = X (23.35)
f (A, B, C , D)
where X represents either a variable or a term or an
= ABC(D + D) + ABCD + ABCD + ABCD expression and Y is a variable. This theorem implies
= ABCD + ABCD + ABCD + ABCD + ABCD that if a Boolean expression contains two terms that
differ only in one variable, then they can be combined
The different terms are then arranged in the ascend- together and replaced by a term that is smaller by one
ing order of the binary numbers represented by vari- literal. Same procedure is applied for the other pairs of
ous terms with true variables representing a `1 and a terms wherever such a reduction is possible. All these
complemented variable representing a `0. The expres- terms reduced by one literal are further examined to see
sion becomes if they can be reduced further. The process continues till
the terms become irreducible. The irreducible terms are
f (A, B, C , D) called prime implicants. An optimum set of prime impli-
= ABCD + ABCD + ABCD + ABCD + ABCD cants that can account for all the original terms then con-
stitutes the minimized expression. The technique can be
The different terms represent 0001, 0101, 1000, 1001 applied equally well for minimizing sum-of-products and
and 1111. Decimal equivalent of these terms enclosed product-of-sums expressions and is particularly useful for
in the S then gives the S notation for the given Boo- Boolean functions having more than six variables as it
lean function. That is, f (A, B, C , D) = 1, 5, 8, 9, 15.

can be mechanized and run on a computer. On the other
hand, Karnaugh mapping method, to be discussed later, is
The complement of f(A, B, C, D), that is, f(A, B, a graphical method and becomes very cumbersome when
C, D) can be directly determined from S notation by the number of variables exceeds six. The step-by-step
including the left out entries from the list of all pos- procedure for application of Quine-McCluskey tabular
sible numbers for a four variable function. That is, method for minimizing Boolean expressions, both sum-of-
f (A, B, C , D) = 0, 2, 3, 4, 6, 7, 10, 11, 12, 13, 14 . products and product-of-rums, is outlined as follows:
1. The Boolean expression to be simplified is expanded
Let us now take the case of a product-of-sums Boolean
function and its representation in P-nomenclature. Let
if it is not in the expanded form.
2. The different terms in the expression are divided
us consider the following Boolean function:
into groups depending upon number of 1s they
f (A, B, C , D) have. True and complemented variables in a sum-
of-products expression mean `1 and `0, respec-
= (B + C + D)(A + B + C + D)(A + B + C + D) tively. Reverse is the case for product-of-sums
expression. The groups are then arranged in the
The expanded product-of-sums Boolean function is given ascending order, that is, beginning with a group
by having least number of 1s in its included terms.
Terms within the same group are also arranged in
(A + B + C + D)(A + B + C + D) the ascending order of the decimal numbers repre-
(A + B + C + D)(A + B + C + D) sented by these terms.

As an illustration, consider the following expression. any optional terms. In case there are any, they are
also considered while forming groups. This com-
A B C + A B C + A B C + AB C + A B C pletes the first table.
The grouping of different terms and arrangement of 3.The terms of the first group are successively matched
different terms within the group are shown as follows: with those in the next adjacent higher order group
to look for any possible matching and consequent
reduction. The terms are considered matched
AB C 000 First-group when all literals except for one match. The pairs
of matched terms are replaced by a single term
where the position of unmatched literals is replaced
A BC 100 nd-group
Secon by `. These new terms formed as a result of the
matching process find a place in the second table. The
terms in the first table that do not find a match are
Third-group called the prime implicants and are marked with an
ABC 011
asterisk sign (*). The matched terms are ticked ().
A BC 101 4. Terms in the second group are compared with
those in the third group to look for possible match.
Again, terms in the second group that dont find a
ABC 111 Fourtth-group match become the prime implicants.
5. The process continues till we reach the last group.
This completes first round of matching. The terms
As another illustration, consider a product-of-sums resulting from the matching in the first round are
expression given by recorded in the second table.
(A + B + C + D)(A + B + C + D)(A + B + C + D) 6. The next step is to perform matching operations
in the second table. While comparing the terms
(A + B + C + D)(A + B + C + D) for a match, it is important that a dash ` is also
(A + B + C + D)(A + B + C + D) treated like any other literal, that is, the dash signs
also need to match. The process continues onto the
The formation of groups and arrangement of terms third, fourth tables and so on till the terms become
within different groups for the product-of-sums irreducible any further.
expression are given as follows: 7. An optimum selection of prime implicants to
account for all the original terms constitutes the
ABC D terms for the minimized expression. Although,
optional (also called `dont care) terms are consid-
ered for matching, they do not have to be accounted
ABC D 0000 for once prime implicants have been identified.
We shall illustrate the entire process of simplification
with the help of an example. Consider the following sum-
ABC D 0011
of-products expression:
ABC D 0101
ABC D 1010 ABC + ABD + ACD + BCD + ABCD
In the first step, we write the expanded version of the

ABC D 0111 given expression. It can be written as follows:
ABC D 1110
ABCD + ABCD + ABCD + ABCD +
ABC D 1111 ABCD + ABCD + ABCD +
ABCD + ABCD
The formation of groups, placement of terms in different

It may be mentioned here that the Boolean expres- groups and first round matching are shown in tabular
sions that we have considered above did not contain form as follows:

A B C D A B C D A B C D
0 0 0 1 0 0 0 1 0 0 1
0 0 1 1 0 1 0 0 0 0 1
0 1 0 0 0 0 1
0 1 0 1 0 0 1 1 0 1 0
0 1 1 0 0 1 0 1 0 1 0
0 1 1 1 0 1 1 0 1 0 0
1 0 0 1 1 0 0 1
1 1 0 0 0 1 1
1 1 0 0
0 1 1
1 1 0 1 0 1 1 1 1 0 1
1 1 0 1 0 1 1
1 0 1
1 1 0
The second round of matching begins with the table Each prime implicant is identified by a letter. Each
shown on the extreme right above. Each term in the prime implicant is then examined one by one and the
first group is compared with every term in the second terms it can account for are ticked as shown. The next
group. For instance, the first term in the first group step is to write a product-of-sums expression using the
(001) matches with the second term in the second prime implicants to account for all the terms. In the
group (011) to yield (0 1), which is recorded in present illustration, it is given as follows:
the next table as shown below. The process continues till
all terms have been compared for a possible match. Since (P + Q)(P)(R + S)(P + Q + R + S)
this new table has only one group, the terms contained (R)(P + R)(Q)(S)(Q + S)
therein are all prime implicants. In the present example,
the terms in the first and second tables have all found a Obvious simplification reduces this expression to PQRS
match. But that is not always the case. which can be interpreted to mean that all prime impli-
cants, that is, P, Q, R and S are needed to account for
A B C D all the original terms. Therefore, the minimized expres-
0 1 * sion is
0 1 *
0 1 * AD + CD + AB + BC
1 0 *
As another illustration, let us consider a product-of-sums
The next table is what is known as prime implicant expression given by
table. The prime implicant table contains all the original
terms in different columns and all the prime implicants
(A + B + C + D)(A + B + C + D)(A + B + C + D)
recorded in different rows shown as follows.
(A + B + C + D)(A + B + C + D)
0001
0011
0100
0101
0110
0111
1001
1100
1101
The procedure is similar to what has been described in

case of simplification of sum-of-products expressions.
0 1 P AD The resulting tables leading to identification of prime
implicants are given as under.
0 1 Q CD
The prime implicant table is constructed after all prime
0 1 R AB
implicants have been identified to look for optimum set
of prime implicants needed to account for all the original
1 0 S BC terms. The prime implicant table shows that both the
prime implicants are the essential ones.

A B C D A B C D A B C D A B C D
0 1 0 1 0 1 0 1 0 1 1 1 1
1
1
0 1 1 1 1 0
0 1 1
1 1
1 1 0 1
1 1 0 1 1
1 1 1 0
1 1 1 0 1 1 1
1 1 1 1
1 1 1
1 1 1 1
The choice of terms identifying different rows and col-

0101
0111
1101
1110
1111
Prime
umns of a Karnaugh map is not unique for a given number
implicants
of variables. The only condition to be satisfied is that the
111
designation of adjacent rows and adjacent columns should
be the same except for one of the literals being comple-
11 mented. Also, the extreme rows and extreme columns are
considered adjacent. Some of the possible designation styles
for two-, three- and four-variable minterm Karnaugh maps
are given in Figs. 23.4, 23.5 and 23.6, respectively.
The minimized expression is
B B B B
(A + B + C )(B + D) A
A
A A
23.9.6 Karnaugh Map Method
(a) (b)
Karnaugh map (K-map) is a graphical representation of
the logic system. It can be drawn directly from either
minterm (sum-of-products) or maxterm (product-of- B B B B
sums) Boolean expressions. Drawing a Karnaugh map A A
from truth table involves an additional step of writing
the minterm or maxterm expression depending upon A A
whether it is desired to have minimized sum-of-products
or a minimized product-of-sums expression. (c) (d)
Figure 23.4| Two-variable Karnaugh map.
23.9.6.1Construction of Karnaugh Map
B C B C B C BC B C BC B C B C
An n-variable Karnaugh map has 2n squares and each
A A
possible input is allotted a square. In case of a minterm
Karnaugh map, `1 is placed in all those squares for A A
which the output is `1 and `0 is placed in all those
squares for which the output is `0. For simplicity, 0s (a) (b)
are omitted. An X is placed in squares corresponding
to `dont care conditions. In the case of a maxterm B C B C BC B C BC B C B C B C
Karnaugh map, a `1 is placed in all those squares for
which the output is `0 and a `0 is placed for input A A
entries corresponding to a `1 output. Again 0s are
A A
omitted for simplicity and an X is placed in squares
corresponding to `dont care conditions. (d)
(c)
The process of construction of 2, 3 and 4 variable
Karnaugh maps is illustrated in the following examples. Figure 23.5| Three-variable Karnaugh map.

The style of row identification need not be the C D CD CD CD CD C D CD CD

same as that of column identification as long as it
meets the basic requirement with respect to adjacent AB AB
terms. It is however a practice to adopt a uniform
AB AB
style of row and column identification. Also, the
style shown in Figs. 23.4(a), 23.5(a) and 23.6(a) is AB AB
more commonly used. Some more styles are shown in
Fig. 23.7. A similar discussion applies for maxterm AB AB
Karnaugh maps.
(a) (b)
Having drawn the Karnaugh map, the next step is to
form groups of 1s as per the following guidelines: CD CD CD C D CD CD C D CD
1. Each square containing a `1 must be considered AB AB
at least once, though it can be considered as often
as desired. AB AB
2. The objective should be to account for all the AB AB

marked squares in the minimum number of
AB AB
groups.
3. The number of squares in a group must always be (c) (d)
Figure 23.6| Three-variable Karnaugh map.

a power of 2, that is, groups can have 1, 2, 4, 8, 16,
squares.
4. Each group should be as large as possible which however not necessary to account for all optional
means that a square should not be accounted for entries. Only those optional combinations that can
by itself if it can be accounted for by a group of two be used to advantage should be used.
squares; a group of two squares should not be made
Having made groups with all 1s having been accounted for,
if the involved squares can be included in a group
the minimum `sum-of-products or the `product-of-sums
of four squares and so on.
expressions can be written directly from Karnaugh map.
5.Optional entries can be used in accounting for all of Figures 23.8, 23.9 and 23.10 illustrate the construction of
1-squares to make optimum groups. Optional entries minterm and maxterm Karnaugh maps for two-, three- and
are marked `X in the corresponding squares. It is four-variable Boolean expressions, respectively.
C C D
C D CD CD CD
AB
A
AB
B B
AB
A
AB
CD
C D CD CD CD AB 00 01 11 10
AB 00
AB 01
AB 11
AB 10
Figure 23.7| Different styles of row and columns identification.

Truth table B B
A 1 A B C Y BC B C BC BC
A B Y A 1 1 0 0 0 1 A 1 1
0 0 0 Sum-of-products K-map 0 0 1 0 A 1 1
0 1 1 0 1 0 1 Sum-of-products K-map
1 0 1 B B 0 1 1 0
1 1 1 A 1 0 0 1
A 1 B+ C B+ C B+ C B+ C
1 0 1 0
Product-of-sums K-map A 1 1
1 1 1
Figure 23.8| Two-variable Karnaugh maps.
0 A 1 1
1 1 1 0
Products-of-sums K-map
Figure 23.9| Three-variable Karnaugh maps.
Truth table
A B C D Y
0 0 0 0 1 CD CD CD CD
0 0 0 1 1 AB 1 1
0 0 1 0 0
AB 1 1
0 0 1 1 0
AB 1 1
0 1 0 0 1
AB 1 1
0 1 0 1 1
0 1 1 0 0 Sum-of-products K-map
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0 C+D C+D C+D C+D
1 0 1 1 0 A+B 1 1
1 1 0 0 1 A+B 1 1
1 1 0 1 1 A+B 1 1
1 1 1 0 0 A+B 1 1
1 1 1 1 0 Products-of-sums K-map
Figure 23.10| Four-variable Karnaugh maps.
IMPORTANT FORMULAS
1. X + Y = Y + X 15. XY + XY = X
2. XY = YX 16. (X + Y )(X + Y ) = X
3. X X = 0 17. (X + Y ) Y = XY
4. X + X = 1 18. XY + Y = X + Y
5. X X X X = X 19. X + XY = X
6. X + X + X + + X = X 20. X(X + Y ) = X
7. 1 X = X 21. ZX + ZXY = ZX + ZY
8. 0 + X = X
22. (Z + X ) (Z + X + Y ) = (Z + X ) (Z + Y )
9. 0 X = 0
10. 1 + X = 1 23. XY + XZ + YZ = XY + XZ
11. X + (Y + Z ) = Y + (Z + X ) = Z + (X + Y ) 24. (X + Y ) (X + Z ) (Y + Z ) = (X + Y ) (X + Z )
12. X(YZ ) = Y (ZX ) = Z(XY ) 25. [X1 + X2 + X3 + + Xn ] = X1 X2 X3 Xn
13. X (Y + Z ) = X Y + X Z 26. [X1 X2 X3 Xn ] = [X1 + X2 + X3 + +Xn ]
14. X + YZ = (X + Y ) (X + Z ) 27. XY + XZ = (X + Z )(X + Y )

28. (X + Y )(X + Z ) = XZ + XY 32. f (X , X , Y , Z , )

29. X f (X , X , Y , Z , ) = X f (1, 0, Y , Z , ) = [X + f (0, 1, Y , Z , )][X + f (1, 0, Y , Z , )]
30. X + f (X , X , Y , Z , ) = X + f (0, 1, Y , Z , ) 33. X = X
31. f (X, X, Y , Z , ) = X f (1, 0, Y , Z , )
+ X f (0, 1, Y , Z , )
SOLVED EXAMPLES
1. Consider an arbitrary number system with inde- the equivalent binary number should be omitted.
pendent digits as 0, 1 and A. The sixth number in Therefore,
this number system would be
(011111100.010110)2 = (11111100.01011)2
(a) AA (b) A1 Ans. (a)
(c) 100 (d) 1A
4. Octal equivalent of hexadecimal number 2E.C1
Solution. The first three numbers are 0, 1 and A. would be
The fourth, fifth and sixth numbers would be 10,
(a) 212.602 (b) 56.602
11 and 1A, respectively. The seventh, eighth and
(c) 56.623 (d) 6F.C4
ninth numbers in the same manner would be A0,
A1 and AA, respectively. The process continues Solution. The given hexadecimal number is
and the next number after AA would be 100 as all (2E.C1)16 whose binary equivalent is
possible 2-digit numbers have been exhausted.
Ans. (d) (0010 1110.1100 0001)2 = (00101110.11000001)2
2. Find the decimal equivalent of a binary number = (101110.11000001)2

10001110, which has been represented in 2s com- = (101 110.110 000 010)2
plement form. = (56.602)8
(a) -114 (b) +114 Therefore, the octal equivalent of the given hexa-
(c) +142 (d) None of these decimal number is (56.602)8.
Solution. MSB bit is `1 which indicates a minus Ans. (b)
sign. The decimal equivalent is 5. Number of bits required to encode the decimal
02 +12 +02 +02 +12 +
0 1 2 3 4 numbers from 0 to 9999 in straight binary and
BCD codes would be, respectively,
1 25 +1 26 = 0 + 2 + 0 + 0 + 16 + 32 +
(a) 16 and 14 (b) 14 and 20
64 = 114 (c) 14 and 16 (d) 8 and 16
Therefore, 10001110 represents 114.
Ans. (a) Solution. The total number of decimals to be rep-
resented is
3. Binary equivalent of the octal number 374.26 is
10000 = 104 = 213.29
(a) 11111100.01011 (b) 11101100.01011
(c) 11111100.10111 (d) 11111100.01001 Therefore, the number of bits required for straight
binary encoding is 14 and the number of bits
Solution. The given octal number is (374.26)8. required for BCD encoding is 16.
The binary equivalent of (374.26)8 is Ans. (c)
(011 111 100.010 110)2= (011111100.010110)2 6. Binary equivalent of Gray code number 1111 would be
0s, if any, on the extreme left of the integer part (a) 1100 (b) 1101
and the extreme right of the fractional part of (c) 0100 (d) 1010

SOLVED EXAMPLES 533
Solution. The binary equivalent of Gray code

(a) (AC + AD + ABC ) (b) (A C + A D + AB)
number 1111is as given below.
Gray : 1 1 1 1 (c) (A C + A D + BC ) (d) (AC + AD + AC )
Binary : 1
Solution. Let us consider the group of four 1s on
Gray : 1 1 1 1 the top left of the map which yields a term A C.
Binary : 1 0 Also let us consider the group of four 1s, two on
Gray : 1 1 1 1 the extreme top left and two on the extreme top
Binary : 1 0 1 right. This group yields a term A D. The third
group of two 1s is in the third row of the map. The
Gray : 1 1 1 1 third row corresponds to intersection of A, B and
Binary : 1 0 1 0 C as is clear from the map. Therefore, this group
Ans. (d) yields a term ABC. The simplified Boolean expres-
7. The complement of [(AB + C )D + E ]F is sion is given by
(AC + AD + ABC )
(a) [(A + B) C + D ] E + F
The Karnaugh map with grouping is shown in the
(b) [(A + B).C + D ] + F following figure.
(c) [A + B + D ] E + F C C
(d) [(A + B) C + D ] E + F
1 1 1
Solution. The complement of [(AB + C )D + E ]F A
is given by [(A + B) C + D ] E + F 1 1 1
Ans. (a) B B
1 1
8. The Boolean expression [1 + LM + LM + LM ] A
[(L + M )(LM ) + LM (L + M )] can be simplified to
(a) 1 (b) 0
D
(c) LM (d) L + M
D
Solution. We know that (1 + Boolean expression) Ans. (a)
= 1. Also, (LM ) is the complement of (L + M ) and
(LM ) is the complement of (L + M ). Therefore, 10. (AB + CD) is a simplified version of the Boolean
the given expression reduces to
expression ABCD + ABCD + AB only if there
1.(0 + 0) = 1.0 = 0 were a `dont care entry. What is it?
Ans. (b) (a) ABD (b) BCD
9. Identify the simplified Boolean expression for the (c) ABC (d) ABCD
Karnaugh map shown in the following figure.
C Solution. The expanded version of the given
expression is given by
1 1 1
ABCD + A BCD +

1 1 1 AB(C D + CD + CD + CD)
B ABCD + A BCD + ABC D +
1 1 =
A ABCD + ABCD + ABCD
The Karnaugh map for this Boolean expression is

D shown in the following figure.

CD CD CD CD Now, if it is to be simplified version of the given

expression, that is,(AB + CD), then the lowermost
AB 1 square in the CD column should not be empty. This
implies that there is a `dont care entry. This has
1 1 1 1 been reflected in the map by putting X in the rel-
AB
evant square. With the groups formed along with the
`dont care entry, the simplified expression becomes
AB 1 the one stated in the problem.
Ans. (d)
AB
1. Find the decimal equivalent of 00001110 repre- 4. What is the Gray code equivalent of the decimal 13?
sented in 2s complement form.
Solution. The binary equivalent of the decimal 13
Solution. MSB bit is `0 which indicates a plus can be determined to be 1101 as follows:
sign. Magnitude bits are 0001110. The decimal Binary :1101
equivalent is Gray : 1
Binary :1101
0 20 + 1 21 + 1 22 + 1 23 + 0 24 Gray : 1 0
+ 0 25 + 0 26 = 0 + 2 + 4 + 8 + 0 Binary :1101
+ 0 + 0 = 14 Gray : 1 0 1
Binary :1101
Therefore, the decimal equivalent of 00001110 is +14.
Gray :1011
Ans. (14)
Ans. (1101)
2. Determine the hexadecimal equivalent of (82.25)10
5. How would the 16-bit BCD representation of
decimal number 27 look like?
Solution. The integer part is 82.
Solution. In BCD representation, each decimal
Divisor Dividend Remainder digit is represented by its four-bit binary equiva-

16 82 lent. Therefore, first, 27 is written as 0027 if it were
to be a 16-bit representation. Therefore, the BCD
16 5 2 equivalent of the decimal number 27 would like
0 5
0000 0000 0010 0111 = 0000000000100111
Ans. (0000000000100111)
The hexadecimal equivalent of (82)10 = (52)16. 6. Simplify: (AB + CD) [(A + B) (C + D)]
The fractional part of the given number is 0.25.
Therefore, Solution. Let (AB + CD) = X. Then, the given
0.25 16 = 0 with a carry of 4 expression reduces to X X . Therefore,
Therefore, the hexadecimal equivalent of (82.25)10 (AB + CD) [(A + B) (C + D)]
is (52.4)16
Ans. (52.4) = (AB + CD) (AB + CD) = 0
Ans. (0)

3. Find the binary equivalent of (28E.F3)16 7. What is the 2s complement representation of 17?
Solution. Given hexadecimal number is (28E.F3)16 Solution. Binary representation of +17 is 010001.
whose binary equivalent is Therefore, 2s complement representation of 17
(0010 1000 1110.1111 0011)2 is 101111.
= (001010001110.11110011)2 Ans. (101111)
= (1010001110.11110011)2 8. Given that the Boolean function represented by
Ans. (1010001110.11110011) notation S0, 2 is the same as the Boolean function

represented by the notation P A, B. What is the D

value of B? D
Solution. CD CD CD CD
AB 1 1
0, 2 = AB + AB = B(A + A) = B
P 1, 3 = (A + B)(A + B) = AA + AB + BA + BB A
AB 1 1 1
= AB + AB + B = B
B B
Therefore, AB 1 1 1
0, 2 =P 1, 3 A
AB 1 1
That is A = 1 and B = 3. Hence, the value of B is 3.
Ans. (3) Therefore, the number of 1s are 10.
9. Minimizing a given Boolean expression using Ans. (10)
QuineMcCluskey tabular method yields the fol- 10. The expanded form of the Boolean function:
lowing prime implicants: - 0 - 0, - 1- 1, 1 - 1 0 ABCD + A BCD + AB contains how many
and 0 - 0 0. What is the total number of `1 terms minterms?
in the corresponding Karnaugh map?
Solution. The expanded version of the given
Solution. As is clear from the prime implicants, expression is
the expression has four variables. If the variables ABCD + A BCD +
are assumed as A, B, C and D, then the given prime
implicants correspond to the following terms. AB(C D + CD + CD + CD)
ABCD + A BCD + ABC D +
(i) - 0 -0 B D (ii) - 1 - 1 BD =
ABCD + ABCD + ABCD
(iii) 1 - 1 0 ACD (iv) 0 - 0 0 ACD
Therefore, number of minterms in the expanded
The Karnaugh map can now be drawn as shown in form of the given Boolean expression is 6.
the following figure. Ans. (6)
PRACTICE EXERCISE
1. In the Karnaugh map for an eight-variable Boolean 4. A B + A B is equal to

(a) (A + B)( A +B) (b) A B + A B
function, a certain group corresponds to a term
having two literals. It should be a group of
(c) (A + B) (A + B)
(d) None of these
(a) 64 (b) 32 (c) 128 (d) 16 (1 Mark)
(2 Marks)
5. The equality (A + B + C ) = A B C is better
2. The complement of the complement of Boolean
known as
function AB + AB will be
(a) Involution law (b) Absorption law
(a) A B + A B (b) A B (c) De Morgans law (d) Complementation law
(c) A B + A B (d) None of these 6. The QuineMcCluskey tabulation method of sim-
(1 Mark) plification of Boolean functions is based on
3. A + A B + A B C + A B C D simplifies to
(a) De Morgans theorem
(b) Absorption law
(a) 1 (b) 0 (c) Complementation theorem
(c) A + B (d) A (d) Involution theorem
(1 Mark) (1 Mark)

7. If f (A + B + C + D) were a Boolean function, 9. If the complement of a certain Boolean function is

then f (A + B + C + D) + f(A + B + C + D) A B + A B , then, the dual of the Boolean func-
would equal tion would be
(a) 1 (b) 0 (a) (A + B) (A + B) (b) A B + A B
(c) (A + B + C + D) (d) None of these
(1 Mark) (c) A B + A B (d) None of these
(2 Marks)
8. Amongst the following four-bit groups, the only
invalid BCD code is 1001, 0111, 1000 and 1010 10. If f (A, B, C) = S1, 2, 3, 4, 5, 6, 7 and there are no
`dont care entries, then f(A, B, C) would equal
(a) 0111 (b) 1001
(c) 1010 (d) 1000 (a) A + B + C (b) A + B + C
(1 Mark) (c) ABC (d) A B C
(2 Marks)
1. Simplify the Boolean function: A B + A B + 6. An arbitrary number system has a radix of 32 with
AB+AB 0 to 9 and A to V as its independent digits, 0 being
the first and V being the 32nd digit. Determine the
(1 Mark)
equivalent of decimal number 128 in this arbitrary
2. A certain Boolean function has a value of `1 for number system.
given logical status of its different variables. What (2 Marks)
will be the value of its dual?
7. Find the octal equivalent of hexadecimal number 13.34
(2 Marks)
(1 Mark)
3. How many numerical entries the Boolean expres-
8. Simplify:
sion (AB + BC + AC) have in sigma notation?
(1 Mark) ABC +ABC +ABC +ABC
4. What will be the maximum number of terms in a +ABC +ABC +ABC +ABC
five variable minterm Boolean expression?
(1 Mark) (1 Mark)
5. How many terms will appear in an equivalent 9. Simplify:

P-nomenclature of the Boolean function S1, 4, 7?
1+ AB + B C + AB C + AB C + AB C
(1 Mark)
(1 Mark)
1. (c) Group of 2 will give a term having literals 4. (a) The answer is obvious if we do simple multi-
equal to one less than the maximum number of plication and substituting A A = 0 and B B = 0.
variables. Every successive higher group will have
5. (c) The answer is hidden in the statement of
one less than the maximum number of variables.
De Morgans theorems.
In general, group of 2n will have number of liter-
als equal to n less than the maximum number of 6. (c) Complementation theorem is the basis of sim-
variables. plification by QuineMcCluskey method.
2. (c) The complement of the complement of a 7. (a) A Boolean function added to its complement
Boolean function is the same Boolean function. equals 1.
3. (d) The term A is appearing in all the terms. 8. (c) Only binary equivalents of decimal numbers 0
Therefore, the remaining terms are redundant. to 9 are valid BCD numbers.

9. (a) If the complement of the Boolean expres- (A + B) = ( A B ) + (A B). Its dual would then
sion was A B + A B , then the original Boolean be (A + B) (A + B).
10.(d) The complement of S1, 2, 3, 4, 5, 6, 7 equals S0,
expression would be (A B) + A B = (A + B ) where S0 = A B C .
1. When a Boolean function contains all possible 6. The corresponding number can be determined by
minterms, it simplifies to 1. successively dividing 128 by 32 and recording the
Ans. (1) remainders. Remainders written in reverse order
give the desired equivalent, 40.
2. 1. Ans. (1) Ans. (40)
3. The given Boolean expression is first expanded. The 7. First, find the binary equivalent and then convert
term ABC appears thrice and can be replaced by it to its octal equivalent, which is 23.15.
one only. The number of entries that remains are 4. Ans. (23.15)
Ans. (4) 8. The given Boolean function contains all possible
5 three-variable terms; therefore, the simplified value
4. 32 (= 2 ).
Ans. (32) equals 1.
Ans. (1)
5. The terms will be 0, 2, 3, 5 and 6 and hence the
total number of terms is 5. 9. 1 + X = 1, where X is a variable or a Boolean func-
Ans. (5) tion, therefore, answer is 1.
Ans. (1)
1. The number of distinct Boolean expressions of four

variables is RS 00 01 11 10
PQ
(a) 16 (b) 256
(c) 1024 (d) 65536 00 1 1 1
(GATE 2003: 1 Mark)
01 1 1 1 1
Solution.
n 4
22 = 22 = 216 = 65536 11 1 1 1
Ans. (d)
10 1 1 1
2. If the functions W, X, Y and Z are as follows:
W = R + PQ + RS
The following figure shows the K-map for
X = PQRS + PQRS + PQRS X = PQRS + PQRS + PQRS :
Y = RS + PR + PQ + PQ
RS 00 01 11 10
Z = R + S + PQ + PQR + PQS PQ
Then 00 1
(a) W = Z , X = Z (b) W = Z, X = Y
01
(c) W = Y (d) W = Y = Z
11 1
Solution. The K-maps for all four Boolean func-
tions, namely, W, X, Y and Z are drawn as follows: 10 1
The following figure shows the K-map for
The following figure shows the K-map for Y:
W = R + PQ + RS :

3. The range of signed decimal numbers that can be

RS 00 01 11 10
PQ represented by six-bit 1s complement number is
(a) 31 to +31 (b) 63 to +63
00 1 (c) 64 to +63 (d) 32 to +31
(GATE 2004: 1 Mark)
01 1 1 1 1
Solution. The required range is given by
11 1 1 1
(2n1 1) to + (2n1 1) = (261 1) to
10 1 + (261 1)
= 31 to +31
Ans. (a)
Y = RS + PR + PQ + PQ
4. The Boolean expression AC + BC is equivalent to
= RS + (P + R)(P + Q)(P + Q)
= RS + (P + PQ + PR + QR)(P + Q) (a) AC + BC + AC
= RS + PQ + PQ + PQR + PQR + QR (b) BC + AC + BC + ACB
= RS + PQ + QR(P + P ) + QR (c) AC + BC + BC + ABC
= RS + PQ + QR
(d) ABC + ABC + ABC + ABC
The following figure shows the K-map for Z: (GATE 2004: 2 Marks)
Solution.
RS 00 01 11 10
PQ ABC + ABC + ABC + ABC
00 1 1 1 = AC(B + B) + BC(A + A) = AC + BC
Ans. (d)
01 1 1 1 1 5. 11001, 1001 and 111001 correspond to the 2s com-
plement representation of which one of the follow-
11 1 1 1 ing sets of number?
10 1 1 1 (a) 25, 9 and 57, respectively
(b) 7, 7, and 7, respectively
(c) 6, 6, and 6, respectively
Z = R + S + PQ + PQR + PQS (d) 25, 9 and 57, respectively
= R + S + PQ.PQR.PQS
Solution.
= R + S + (P + Q)(P + Q + R)(P + Q + S )
11001: The sign is negative. 2s complement of
= R + S + (PQ + PR + PQ + QR)(P + Q + S ) magnitude bits is 0111. The decimal equivalent
= R + S + PQ + PQ + PQS + PR + PQR + PRS + is -7.
1001: The sign is negative. 2s complement of mag-
nitude bits is 111. The decimal equivalent is -7.
PQS + PQR + QRS
= R + S + PQ + PR + PQS + PQR + PRS
S + PQS 111001: The sign is negative. 2s complement of
+ PQR + QRS magnitude bits is 00111. The decimal equivalent
is -7.
= R + S + PQ(1 + S ) + PR(1 + Q) + PRS + PQS Also note that 11001 and 111001 are extensions
+ PQR + QRS of 1001 where additional bit/s equal to MSB have
been added to the left.
= R + S + PQ + PR + PRS + PQS + PQR + QRS
Ans. (b)
= R + S + PQ + PR(1 + S + Q) + PQS + QRS
6. Decimal 43 in hexadecimal and BCD number
= R + S + PQ + PR + PQS + QRS system is, respectively,
From an examination of K-maps, it can be con- (a) B2, 01000011 (b) 2B, 01000011
cluded that W = Z and X = Z (c) 2B, 00110100 (d) B2, 01000100
Ans. (a) (GATE 2005: 1 Mark)

Solution. Hexadecimal equivalent can be deter- 9. The number of product terms in the minimized sum-
mined by successively dividing the decimal number of-product expression obtained through the follow-
by 16 and recording the remainders. Remainders ing K-map is (where d denotes `dont care states)
written in reverse order give the equivalent number.
BCD equivalent is found by replacing each decimal 1 0 0 1
digit by its four-bit binary equivalent.
Ans. (b)
0 d 0 0
7. The Boolean expression for the truth table shown
below is 0 0 d 1
A B C f
1 0 0 1
0 0 0 0
(a) 2 (b) 3
0 0 1 0 (c) 4 (d) 5
0 1 0 0 (GATE 2006: 1 Mark)
Solution. Four extreme entries of 1s form one
0 1 1 1
group and the other two 1s in the rightmost
1 0 0 0 column form the second term. Therefore, there are
two number of product terms in minimized sum-of-
1 0 1 0 product expression.
1 1 0 1 Ans. (a)
10. X = 01110 and Y = 11001 are two five-bit binary
1 1 1 0
numbers represented in twos complement format.
The sum of X and Y represented in twos comple-
(a) B(A + C )(A + C ) (b) B(A + C )(A + C ) ment format using 6 bits is
(a) 100111 (b) 001000
(c) B(A + C )(A + C ) (d) B(A + C )(A + C )
(c) 000111 (d) 101001
Solution. Solution. In binary addition using 2s complement
f = ABC + ABC format, CARRY is disregarded in the SUM. 01110
+ 11001 = 1000111. By disregarding the CARRY
= B(AC + AC ) (the leftmost bit), we get 000111.
= B(A + C )(A + C ) Ans. (c)
Ans. (a)
11. The Boolean function Y = AB + CD is to be real-
8. A new binary coded pentary (BCP) number system ized using only two-input NAND gates. The mini-
is proposed in which every digit of a base-5 number mum number of gates required is
is represented by its corresponding three-bit binary
(a) 2 (b) 3
code. For example, the base-5 number 24 will be
(c) 4 (d) 5
represented by its BCP code 010100. In this num-
bering system, the BCP code 100010011001 cor- (GATE 2007: 1 Mark)
responds of the following number in base-5 system
Solution. A B + C D = [(A B) (C D)] .
(a) 423 (b) 1324
The following figure shows the NAND implementa-
(c) 2201 (d) 4231
tion and it requires three NAND gates.
A
Solution. Given BCP number = 100010011001. B
This number can be rewritten as 100 010 011 001 Y
by splitting it in groups of three bits starting from
extreme right. Replacing each three-bit group by
its corresponding pentary equivalent, we get the C
answer as 4231. D
Ans. (d) Ans. (b)

Therefore, expression inside first bracket reduces to

12. The Boolean expression Y = ABCD + ABCD +
1 and expression in the second bracket reduces to
ABCD + ABCD can be minimized to
X + Z . This reduces the given Boolean equation to
(a) Y = ABCD + ABC + ACD Z = 1, which gives Z = 0.
(b) Y = ABCD + BCD + ABCD Ans. (d)
(c) Y = ABCD + BCD + ABCD 15. In the sum of products function f (X, Y, Z) =
(d) Y = ABCD + BCD + ABCD (2, 3, 4, 5), the prime implicates are
(GATE 2007: 2 Marks) (a) XY , XY (b) XY , XYZ , XYZ
Solution. The K-map corresponding to given
(c) XYZ , XYZ , XY (d) XYZ , XYZ , XYZ , XYZ
Boolean expression is shown in the following figure:
CD (GATE 2012: 1 Mark)
00 01 11 10
AB Solution. Substituting
f (X , Y , Z ) = S(2, 3, 4, 5)
00 1
01 1 Figure below shows the K-map for this Boolean

function.
11 1 YZ YZ YZ YZ
10 1 X 1 1
X 1 1
The simplified expression from the K-map is given by Therefore, the minimized Boolean function is given by
Y = ABCD + ABCD + BCD f (X , Y , Z ) = XY + XY
Ans. (d)
13. The two numbers represented in signed 2s comple- So, the prime implicants are XY and XY .
ment form are P = 11101101 and Q = 11100110. Ans. (a)
If Q is subtracted from P, the value obtained in
signed 2s complement form is 16. In the circuit shown in the figure, Q1 has negli-
gible collector-to-emitter saturation voltage and
(a) 100000111 (b) 00000111 the diode drops negligible voltage across it under
(c) 11111001 (d) 111111001 forward bias. If VCC is +5 V, X and Y are digital
(GATE 2008: 2 Marks) signals with 0 V as logic 0 and VCC as logic 1, the
Solution. The two numbers P and Q are repre- Boolean expression for Z is
sented in 2s complement form. (P-Q) can be found +VCC
out by adding 2s complement of Q to P and disre-
garding the CARRY. The answer will also be in 2s R1
complement notation.
P = 11101101 and Q = 11100110 Z
R2
The 2s complement of Q = 00011010
X Q1
P Q = P + (2s complement of Q). Diode
Addition of the two numbers gives 00000111.
Ans. (b)
{ }{
14. If X = 1 in the logic equation X + Z Y + (Z + XY ) X + Z(X + Y ) = 1
Y
}
{ }{
X + Z Y + (Z + XY ) X + Z(X + Y ) = 1 , then
} (a) XY (b) XY (c) XY (d) XY
(a) Y = Z (b) Y = Z (c) Z = 1 (d) Z = 0
(GATE 2009: 2 Marks) Solution. It is evident from the figure that output
Z is logic `1 only when X = 0 and Y = 1. In that
Solution. Substituting for X = 1 and X = 0, we
case, both transistor Q1 and diode will be in cut-off.
get the answer. We know that
The output will be equal to +VCC, that is, logic `1.
1 + Boolean expression = 1 Ans. (b)

CHAPTER 24
LOGIC GATES AND LOGIC FAMILIES
This chapter discusses different types of logic gates and some related devices such as buffers and drivers. The discussion
is mainly in terms of truth tables and Boolean expressions. Logic families are discussed later.
24.1 POSITIVE AND NEGATIVE 24.2 TRUTH TABLE

LOGIC
A truth table lists all possible combinations of input
The binary variables as we know can have either of binary variables and the corresponding outputs of a logic
the two states, that is, logic `0 state and logic `1 system. The logic system output can be found out from
state. These logic states in digital systems, such as com- the logic expression, often referred to as the Boolean
puters for instance, are represented by two different expression that relates the output with the inputs of
voltage levels or two different current levels. If the more that very logic system. If a logic circuit has n binary
positive of the two different voltage or current levels rep- inputs; its truth table will have 2n possible input combi-
resents a logic `1 and the less positive of the two levels nations or in other words 2n rows.
represents a logic `0, then the logic system is referred
to as the positive logic system. If the more positive of 24.3 LOGIC GATES
the two voltage or current levels represents a logic `0
and less positive of the two levels represents a logic `1,
then the logic system is referred to as the negative logic A logic gate is the most basic building block of any digi-
system. tal system including computers. Each one of the basic

542 Chapter 24: Logic Gates and Logic Families
logic gates is a piece of hardware or an electronic circuit circuit symbols of a three-input and four-input OR gate,
that can be used to implement some basic logic expres- respectively.
sion. While laws of Boolean algebra could be used to do
manipulation with binary variables and simplify logic
24.3.2 AND Gate
expressions, these are actually implemented in a digital
system with the help of electronic circuits called logic
An AND gate is a logic circuit having two or more
circuits. The three basic logic gates are as follows: (1)
inputs and one output. The output of an AND gate is
OR gate, (2) AND gate and (3) NOT gate.
HIGH only when all of its inputs are in HIGH state. In
all other cases, the output is LOW. When interpreted
24.3.1 OR Gate for a positive logic system, this means that the output
of the AND gate is a logic `1 only when all of its inputs
An OR gate performs ORing operation on two or more are in logic `1 state. In all other cases, the output is logic
than two logic variables. OR operation on two indepen- `0. Figures 24.2(a), (b) and (c) show the logic symbol
dent logic variables A and B is written as Y = A + B of two-input AND gate along with its truth table, logic
and read as `Y equals A OR B but not read as À plus symbol of three-input AND gate and logic symbol of
B. An OR gate is a logic circuit with two or more inputs four-input AND gate, respectively.
and one output. The output of an OR gate is LOW
only when all of its inputs are LOW. For all the other
possible input combinations, the output is HIGH. This A B Y
statement, when interpreted for a positive logic system, 0 0 0
means the following: The output of an OR gate is logic 0 1 0
A 1 0 0
`0 only when all of its inputs are at logic `0. For all Y=AB
B 1 1 1
other possible input combinations, the output is a logic
`1. Figure 24.1(a) shows the circuit symbol and the (a)
truth table of a two-input OR gate. The operation of a
two-input OR gate is explained by the logic expression
A
B Y=ABC
Y = A+B C
(b)
A B Y
A 0 0 0
Y=A+B A
B 0 1 1 B
1 0 1 C Y=ABCD
1 1 1 D
(a) (c)
Figure 24.2| (a) Circuit symbol and truth table
A
B Y=A+B+C
C of two-input AND gate. Circuit symbol
of (b) three-input AND gate and (c) four-
input AND gate.
(b)
A AND operation on the two independent logic variables A
B
C
Y=A+B+C+D and B is written as Y = A B (or Y = AB) which is read
D as Y equals A AND B and it is not read as A multiplied
(c) by B. Here, A and B are the input logic variables and Y
is the output. For example,
Figure 24.1| (a) Circuit symbol and truth table of
two-input OR gate. Circuit symbol of (b)
1. For a two-input AND gate, Y = A B
three-input OR gate and (c) four-input 2. For a three-input AND gate, Y = A B C
OR gate. 3. For a four-input AND gate, Y = A B C D
If we interpret the basic definition of OR and AND gates
As an illustration, if we have four logic variables and we for a negative logic system, we have an interesting obser-
want to know the logical output of A + B + C + D, it vation. We find that OR gate in positive logic system is
would be the output of a four-input OR gate with A, B, an AND gate in negative logic system. Also, a positive
C and D as its inputs. Figures 24.1(b) and (c) show the AND is a negative OR.

24.3 LOGIC GATES 543
24.3.3 NOT Gate

A B C D Y
A NOT gate is a one input one output logic circuit 0 0 0 0 0
whose output is always complement of the input. That 0 0 0 1 1
0 0 1 0 1
is, a LOW input produces a HIGH output and vice
0 0 1 1 0
versa. When interpreted for a positive logic system,
A 0 1 0 0 1
logic `0 at the input produces logic `1 at the output Y=A+B 0
and vice versa. It is also known as a complementing B 1 0 1 0
circuit or an inverting circuit. Figure 24.3 shows the 0 1 1 0 0
(a) 0 1 1 1 1
circuit symbol and the truth table of a NOT gate. NOT
operation on a logic variable X is denoted as X or 1 0 0 0 1
X . That is, if X is the input to a NOT circuit, then 1 0 0 1 0
its output Y is given by Y = X or X and read as Y 1 0 1 0 0
equals NOT X . A B Y 1 0 1 1 1
0 0 0 1 1 0 0 0
0 1 1 1 1 0 1 1
1 0 1 1 1 1 0 1
1 1 0 1 1 1 1 0
X Y=X
(b) (c)
or Figure 24.4| (a) Circuit symbol of a two-input EX-OR
gate. Truth table of a (b) two-input EX-OR
X Y gate and (c) a four-input EX-OR gate.
X Y=X 0 1
1 0
24.3.5 NAND Gate
(a) (b)
NAND stands for NOT-AND. An AND gate followed
Figure 24.3| (a) Circuit symbol and (b) the truth by a NOT circuit makes it a NAND gate as shown in
table of a NOT gate. Fig. 24.5(a). Figures 24.5(b) and (c) show the circuit
symbol and truth table of a two-input NAND gate. The
truth table of a NAND gate is obtained from the truth
24.3.4 Exclusive-OR Gate table of an AND gate by complementing the output
entries. The output of a NAND gate is logic `0 when all
The exclusive-OR gate, commonly written as EX-OR its inputs are logic `1. For all other input combinations,
gate is a two-input one-output gate. Figures 24.4(a) output is logic `1. Two-input NAND gate operation is
and (b), respectively, show the logic symbol and truth logically expressed as
table of a two-input EX-OR gate. As can be seen from Y = AB
the truth table, output of an EX-OR gate is logic `1
In general, Boolean expression for a NAND gate with
when the inputs are unlike inputs and logic `0 when
more than two inputs can be written as
the inputs are like inputs. Although EX-OR gates are
available in the integrated circuit form only as two-input Y = A B C D
gates unlike other gates which are available in multiple
inputs also, multiple input EX-OR logic functions can be A
implemented using more than one two-input gates. The
truth table of a multiple input EX-OR function can be B
expressed as follows. Output of a multiple input EX-OR
logic function is logic `1 when the number of 1s in the (a) A B Y
input sequence is odd and logic `0 when the number of 0 0 1
1s in the input sequence is even including zero. That is, A 0 1 1
Y=AB 1 0 1
an all 0s input sequence also produces logic `0 at the
output. Figure 24.4(c) shows the truth table of a four- B 1 1 0
input EX-OR function. Output of a two-input EX-OR (b) (c)
Figure 24.5| (a) Circuit symbol of a NAND gate. (b)
gate is expressed by
Circuit symbol and (c) truth table of a two-
Y = A B = AB + AB input NAND gate.

24.3.6 NOR Gate Y = AB = AB+AB

NOR stands for NOTOR. An OR gate followed by a The output of a two-input EX-NOR gate is logic `1 when
NOT circuit makes it a NOR gate as shown in Fig. 24.6(a). the inputs are like inputs and logic `0 when they are
Figures 24.6(b) and (c) show the logic symbol and truth unlike inputs. In general, the output of a multiple input
table of a NOR gate, respectively. The truth table of a EX-NOR logic function is logic `0 when the number of
NOR gate is obtained from the truth table of an OR gate 1s in the input sequence is odd and logic `1 when the
by complementing the output entries. The output of a number of 1s in the input sequence is even including
NOR gate is logic `1 when all its inputs are logic `0. For zero. That is, an all 0s input sequence also produces
all other input combinations, output is logic `0. NOR logic `1 at the output.
gate operation is logically expressed as
Y = A+B
24.3.8 INHIBIT Gate
In general, Boolean expression for a NOR gate with more
than two inputs can be written as In digital circuit design, there are many situations where
the passage of a logic signal needs to be either enabled
Y = A + B + C + D or inhibited depending upon certain other control inputs.
INHIBIT here means that the gate produces a certain
A A
Y=A+B fixed logic level at the output irrespective of changes
Y
B B in the input logic level. As an illustration, if one of the
inputs of a four-input NOR gate is permanently tied to
(a) (b) logic `1 level, then the output shall always be a logic
`0 level irrespective of the logic status of other inputs.
A B Y This gate shall behave as a NOR gate only when this
0 0 1 control input is at logic `0 level. This is an example of
0 1 0 INHIBIT function. INHIBIT function is available in the
1 0 0 integrated circuit form for an AND gate, which is basi-
1 1 0 cally an AND gate with one of its inputs negated by
(c) an inverter. Negated input acts to inhibit the gate. In
Figure 24.6| (a) Two-input NOR implementation

other words, the gate shall behave like an AND gate only
when the negated input is driven to logic `0. Figure 24.8
using an OR gate and a NOT circuit. (b) shows the circuit symbol and truth table of a four-input
Circuit symbol and (c) truth table of a
INHIBIT gate.
two-input NOR gate.
24.3.7 Exclusive-NOR Gate A B C D Y

0 0 0 0 0
Exclusive-NOR (commonly written as EX-NOR) means 0 0 0 1 0
NOT of EX-OR, that is, logic gate that we get by com- 0 0 1 0 0
plementing the output of an EX-OR gate. Figure 24.7 0 0 1 1 0
shows its circuit symbol of an EX-NOR gate along with 0 1 0 0 0
its truth table. 0 1 0 1 0
0 1 1 0 0
A B Y 0 1 1 1 0
0 0 1 1 0 0 0 0
A 0 1 0 1 0 0 1 0
Y=A+B 1 0 0 1 0 1 0 0
B 1 1 1 1 0 1 1 0
(a) (b) 1 1 0 0 0
Figure 24.7| (a) Circuit symbol and (b) truth table of

A 1 1 0 1 0
B 1 1 1 0 1
a two-input EX-NOR gate. C Y
1 1 1 1 0
D
The truth table of EX-NOR gate is obtained from the
(a) (b)
truth table of EX-OR gate by complementing the output
entries. Logically, Figure 24.8| INHIBIT gate.

24.3.9 Universal Gates A Y=A

OR, AND and NOT gates are the three basic logic gates
as they all together can be used to construct the logic cir- (a)
cuit for any given Boolean expression. NOR and NAND
gates have the property that they individually can be
used to hardware implement logic circuit corresponding
A Y=A+B
to any given Boolean expression. That is, it is possible to
use either only NAND gates or only NOR gates to imple- B
ment any Boolean expression. It is so because a combina-
tion of NAND gates or that of NOR gates can be used (b)
to perform functions of any of the basic logic gates. It is
because of this reason that NAND and NOR gates are A
A
called universal gates. As an illustration, Fig. 24.9 shows Y=AB
how two-input NAND gates can be used to construct
B
a NOT circuit [(Fig. 24.9(a)], a two-input AND gate B
[Fig. 24.9(b)] and a two-input OR gate [(Fig. 24.9(c)].
(c)
A Figure 24.10| Implementation of basic logic gates
Y=A using only NOR gates.
(a)
The advantage of using open collector/open drain gates
lies in their capability to provide ANDing operation
when outputs of several gates are tied together through a
A Y=AB common pull-up resistor without having to use an AND
B gate for the purpose. This connection is also referred to
as WIRE-AND connection. Figure 24.11(a) shows such a
(b) connection for open-collector NAND gates. In this case,
the output would be
Y = AB CD EF
A A
Y=A+B Figure 24.11(b) shows a similar arrangement for NOT
B gates. The disadvantage is that they are relatively slower
B
and noisier. Open collector/drain devices are therefore
(c) not recommended for applications where speed is an
important consideration.
Figure 24.9| Implementation of basic logic gates using
only NAND gates.
24.3.11 Tristate Logic Gate
Figure 24.10 demonstrates the implementation of diff-
erent logic gates using NOR gates. Tristate logic gates have three possible output states,
that is, logic `1 state, logic `0 state and a high imped-
24.3.10 Gate with Open Collector/Drain ance state. High impedance state is controlled by an
Outputs external ENABLE input. The ENABLE input decides
whether the gate is active or is in high impedance state.
These are the gates in which we need to connect an When active, output can be `0 or `1 depending upon
external resistor called the pull-up resistor between the input conditions. One of the main advantages of these
output and the DC power supply to make the logic gate gates is that their inputs and outputs can be connected
perform the intended logic function. Depending on the in parallel to a common bus line. Figure 24.12 shows
logic family used to construct the logic gate, they are the circuit symbol of a tristate NAND gate with active
referred to as gates with open collector output (in case of HIGH ENABLE input along with its truth table. The
TTL logic family) or open drain output (in case of MOS one shown in Figure 24.12(b) has active LOW ENABLE
logic family). Logic families are discussed in Section 24.5 input. When tristate devices are paralleled, only one of
of this chapter. them is enabled at a time.

+V 24.3.12 AND-OR-INVERT Gates
Pull-up AND-OR and OR-AND gates can be usefully employed

resistor to implement sum-of-products and product-of-sums
A Boolean expressions, respectively. Figures 24.13(a)
and (b), respectively, show the symbols of AND-OR-
B INVERT and OR-AND-INVERT gates.
C
AB CD EF
A
D
E B
(AB + CD)
C
F
(a) D
(a)
+V
A
Pull-up
B
resistor (A + B)(C + D)
C
A
D
(b)
Figure 24.13| (a) AND-OR-INVERT gate
B A B C
(b)OR-AND-INVERT gate.
C Another method of designating the gates shown in Fig.

(b) 24.13 is to call them two-wide, two-input AND-OR-
INVERT or OR-AND-INVERT gates as the case may
Figure 24.11| WIRE-AND connection with open be. The gate is two-wide as there are two gates at the
collector/drain devices. input, and two-input as each of the gates has two inputs.
24.3.13 Schmitt Gates
A A Logic gates discussed so far have a single input thresh-

Y Y
old voltage level. This threshold is same for both LOW-
B B to-HIGH as well as HIGH-to-LOW output transitions.
This threshold voltage is somewhere between the highest
E E LOW voltage level and the lowest HIGH voltage level
guaranteed by the manufacturer of the device. These
logic gates can produce an erratic output when fed with
A B E Y A B E Y
a slow varying input. A possible solution to this problem
0 0 0 Z 0 0 0 1
lies in having two different threshold voltage levels, one
0 0 1 1 0 0 1 Z
for LOW-to-HIGH transition and the other for HIGH-
0 1 0 Z 0 1 0 1
0 1 1 to-LOW transition by introducing some positive feed-
0 1 1 1 Z
1 0 0 1 back in the internal gate circuitry, a phenomenon called
1 0 0 Z
1 0 1 1 0 1 Z hysteresis.
1
1 1 0 Z 1 1 0 0 There are some logic gate varieties, mainly in NAND
1 1 1 0 1 1 1 Z gates and inverters that are available with built-in hys-
Z = High impedance Z = High impedance teresis. These are called Schmitt gates, which inter-
state state pret varying input voltages according to two threshold
(a) (b) voltages, one for LOW-to-HIGH and other for HIGH-
to-LOW output transition. Figures 24.14(a) and (b),
Figure 24.12| Tristate devices. respectively, show circuit symbols of Schmitt NAND and

Vo (volts)
Vin (volts)
(a) (c)
Voltage
Upper threshold
Lower threshold
Output
Input
Time
(b) (d)
Figure 24.14| Schmitt gate.
Schmitt inverter. Figure 24.14(c) shows typical transfer is limited by current sourcing capability of the output
characteristics for such a device. Figure 24.14(d) shows when the output of the logic gate is HIGH and current
the response of a Schmitt inverter to a slow varying sinking capability of output when it is LOW and also the
noisy input signal. requirements of logic gates inputs being fed in the two
states. To illustrate the point further, let us say the cur-
24.3.14 Fan-out of Logic Gates rent sourcing capability of a certain NAND gate is (IOH)
when its output is in logic HIGH state and that each of
It is not practical to drive unlimited number of logic the inputs of the logic gate that it is driving requires an
gates inputs from the output of a single logic gate. It input current of (IIH) as shown in Fig. 24.15(a). In that
IOH IIH IOL IIL
IIL
IIH
IIL
IIH
(a) (b)
Figure 24.15| Fan-out of logic gates.

case, the output of the logic gate shall be able to drive a load driving capability than a logic gate. It could be an
maximum of (IOH/IIH) inputs when it is in logic HIGH inverting or non-inverting buffer with a single input, a
state. When the output of the driving logic gate is in logic NAND buffer, a NOR buffer, an OR buffer or an AND
LOW state, let us say it has a maximum current sinking buffer. Driver is another name for a buffer. A driver
capability of (IOL) and that each of the inputs of driven is sometimes used to designate a circuit that has even
logic gates require a sinking current of (IIL) as shown in larger drive capability than a buffer. Buffers are usu-
Fig. 24.15(b). In that case, the output of the logic gate ally tristate devices to facilitate their use in bus oriented
shall be able to drive a maximum of (IOL/IIL) inputs when systems. Figure 24.16 shows the symbols and functional
it is in logic LOW state. Thus the number of logic gate tables of inverting and non-inverting buffers of the
inputs that can be driven from the output of a single logic tristate type.
gate shall be (IOH/IIH) in the logic HIGH state and (IOL/ A transceiver is a bidirectional buffer with additional
IIL) in the logic LOW state. Number of logic gate inputs direction control and Enable inputs. It allows flow of
that can be driven from the output of a single logic gate data in both directions depending upon the logic status
without causing any false output is called FAN-OUT. It is of control inputs. Transceivers too like buffers are
the characteristic of the logic family the device belongs to. tristate devices to make them compatible with bus ori-
If in a certain case, the two values (IOH/IIH) and (IOL/IIL) ented systems. Figures 24.17(a) and (b), respectively,
are different, FAN-OUT is taken as smaller of the two. show the circuit symbols of inverting and non-inverting
transceivers.
24.4 BUFFERS AND TRANSCEIVERS Figure 24.18(a) shows a typical logic circuit arrange-
ment of a tristate non-inverting transceiver with its
functional table shown in Fig. 24.18(b).
Logic gates discussed in the previous sections have a
limited load driving capability. A buffer has a larger
A Y A Y A Y A Y
E E E E
A E Y A E Y A E Y A E Y
X 0 Z X 1 Z X 0 Z X 1 Z
0 1 1 0 0 1 0 1 0 0 0 0
1 1 0 1 0 0 1 1 1 1 0 1
Z = High Impedance State

Figure 24.16| Inverting tristate buffers and non-inverting tristate buffers.
B B
A A
(a) (b)
Figure 24.17| (a) Inverting transceivers and (b) non-inverting transceivers.

24.5 LOGIC FAMILIES 549
E2 family (using P-channel MOSFETs), the NMOS-family

(using N-channel MOSFETs) and CMOS-family (using
both N and P channel devices). Bi-MOS logic family uses
both bipolar and MOS devices.
E1 Of all the logic families listed above, the first three,
A B that is, DL, RTL and DTL are of historical importance
only. Diode logic used diodes and resistors and in fact was
never implemented in integrated circuits. RTL family
used resistors and bipolar transistors, DTL family used
resistors, diodes and bipolar transistors. Both RTL and
DTL suffered from large propagation delay due to the
need for the transistor base charge to leak out if the tran-
(a) sistor were to switch from conducting to non-conducting
state. Figure 24.19 shows the simplified schematics of
E1 E2 Operation a two-input AND gate using DL [Fig. 24.19(a)], a two-
input NOR gate using RTL [Fig. 24.19(b)] and a two-
L L Data flow from B to A input NAND gate using DTL [Fig. 24.19(c)]. DL, RTL
L H Data flow A to B and DTL families however were rendered obsolete very
H X Isolation
shortly after their introduction in early 1960s due to
arrival on the scene of transistor-transistor logic (TTL).
(b)
Logic families that are still in widespread use include
Figure 24.18| Tristate non-inverting transceiver. TTL, CMOS, ECL, NMOS and Bi-CMOS. PMOS and
I2L logic families, which were mainly intended for use in
custom large scale integrated (LSI) circus devices, have
24.5 LOGIC FAMILIES also been rendered more or less obsolete with NMOS logic
family replacing them for LSI and VLSI applications.
There are a variety of circuit configurations used to pro- TTL family further has a number of subfamilies
duce different types of digital integrated circuits. Each include standard TTL, low power TTL, high power TTL,
such fundamental approach is called a logic family. The low power Schottky TTL, Schottky TTL, advanced low
idea is that different logic functions when fabricated in power Schottky TTL, advanced Schottky TTL, fast
the form of an integrated circuit (IC) with the same TTL. The popular CMOS subfamilies include 4000A
approach or in other words belonging to the same logic CMOS family, 4000B CMOS family, 4000UB CMOS
family shall have identical electrical characteristics. family, 54/74C family, 54/74HC family, 54/74HCT
These characteristics include supply voltage range, speed family, 54/74AC family and 54/74ACT family. 4000A
of response, power dissipation, input and output logic CMOS family has been replaced by its high voltage ver-
levels, current sourcing and sinking capability, fan-out, sions in 4000B and 4000UB CMOS families with the
noise margin, etc. In other words, the set of digital ICs former having buffered and latter having unbuffered
belonging to the same logic family are electrically com- outputs. 54/74C, 54/74HC, 54/74HCT, 54/74AC and
patible with each other. 54/74ACT are CMOS logic families with pin-compatible
54/74 TTL series logic functions.
First monolithic emitter coupled logic family was
24.5.1 Types of Logic Families
introduced by ON semiconductor, formerly a division of
Motorola, with MECL-I series of devices in 1962 follow-
The entire range of digital ICs is fabricated using either
ing it up with MECL-II in 1966. Both these logic families
the bipolar devices or the MOS devices or a combina-
have become obsolete. Currently, popular subfamilies
tion of the two. Different logic families falling in the first
of ECL logic include MECL-III (also called MC 1600
category are called bipolar families and some of these are
series), MECL-10K series, MECL-10H series and MECL-
the diode logic (DL), resistance transistor logic (RTL),
10E (ECLinPS and ECLinPSLite).
the diode transistor logic (DTL), transistor transistor
logic (TTL), emitter coupled logic (ECL) also known
as current mode logic (CML) and integrated injection 24.5.2 Characteristic Parameters
logic (I2L). The logic families that use MOS devices as
their basis are known as MOS families and the promi- The different parameters characterizing the logic families
nent members belonging to this category are the PMOS include the following:

+V
+V
Y=A+B
A Y = AB A
B
B
(a) (b)
+V
Y = AB
A
(c)
Figure 24.19| (a) Diode logic. (b) Resistor transistor logic. (c) Diode transistor logic
HIGH-level input current (IIH): It is the cur- ENABLE input so chosen as to establish high imped-
rent flowing into (taken as positive) or out of (taken ance state and a logic LOW voltage level applied at
as negative) an input when it is applied a HIGH- the output. The input conditions are so chosen as to
level input voltage equal to the minimum HIGH-level produce logic HIGH if the device were enabled.
output voltage specified for the family. HIGH-level input voltage (VIH): It is the mini-
LOW-level input current (IIL): LOW-level input mum voltage level that needs to be applied at the
current is the maximum current flowing into (taken input to be recognized as legal HIGH level for the
as positive) or out of (taken as negative) the input of specified family.
a logic function when the voltage applied at the input LOW-level input voltage (VIL): It is the maximum
equals the maximum LOW-level output voltage speci- voltage level that needs to be applied at the input to be
fied for the family. recognized as legal LOW level for the specified family.
HIGH-level output current (IOH): It is the maxi-
HIGH-level output voltage (VOH): It is the
mum current flowing out of an output when the input
minimum voltage on the output pin of a logic func-
conditions are such that the output is in logic HIGH state.
tion when the input conditions establish logic HIGH
LOW-level output current (IOL): It is the maxi- at the output for the specified family.
mum current flowing into the output pin of a logic
LOW-level output voltage (VOL): It is the max-
function when the input conditions are such that the
imum voltage on the output pin of a logic function
output is in logic LOW state. It tells about the cur-
when the input conditions establish logic LOW at the
rent sinking capability of the output.
output for the specified family.
HIGH-level off-state (high impedance state)
Supply current (ICC): Supply current when the
output current (IOZH): It is the current flowing
output is HIGH, LOW and in high impedance state is
into an output of a tristate logic function with the
respectively designated as ICCH, ICCL and ICCZ.
ENABLE input so chosen as to establish high imped-
ance state and a logic HIGH voltage level applied at Rise time (tr): It is the time that elapses between
the output. The input conditions are so chosen as to 10% and 90% of the final signal level when the signal
produce logic LOW if the device were enabled. is making a transition from logic LOW to logic HIGH.
LOW-level off-state (high impedance state) Fall time (tf): It is the time that elapses between
output current (IOZL): It is the current flowing 90% and 10% of the signal level when it is making
into an output of a tristate logic function with the HIGH to LOW transition.

24.5 LOGIC FAMILIES 551
Propagation delay (tp): Propagation delay is the without causing any false output. It is the character-
time delay between the occurrence of change in logi- istic of the logic family the device belongs to.
cal level at the input and before it is reflected at the Noise margin: It is a quantitative measure of noise
output. It is the time delay between the specified immunity offered by the logic family. When the
voltage points on the input and output waveforms. output of a logic device feeds the input of another
Propagation delays are separately defined for LOW-to- device of the same family, a legal HIGH logic state
HIGH and HIGH-to-LOW transitions at the output. at the output of the feeding device should be treated
Propagation delay (from LOW to HIGH) as a legal HIGH logic state by the input of the device
(tpLH): It is the time delay between specified voltage being fed. Similarly, a legal LOW logic state of the
points on the input and output waveforms with the feeding device should be treated as a legal LOW logic
output changing from LOW to HIGH. state by the device being fed. Legal HIGH and LOW
Propagation delay (from HIGH to LOW) voltage levels for a given logic family are different for
(tpHL): It is the time delay between specified voltage outputs and inputs. Figure 24.20 shows the general-
points on the input and output waveforms with the ized case of legal HIGH and LOW voltage levels for
output changing from HIGH to LOW. output [Fig. 24.20(a)] and input [Fig. 24.20(b)]. As
we can see from the two diagrams, there is a disal-
Maximum clock frequency (fmax): It is the lowed range of output voltage levels from VOL (max)
maximum frequency at which the clock input of a to VOH (min) and an indeterminate range of input
flip flop can be driven through its required sequence voltage levels from VIL (max) to VIH (min). Since VIL
while maintaining stable transitions of logic level at (max) is greater than VOL (max), the LOW output
the output in accordance with the input conditions state can therefore tolerate a positive voltage spike
and the product specification. It is also referred to as equal to [VIL (max) VOL (max)] and still be a legal
maximum toggle rate for a flip flop or counter device. LOW input. Similarly, VOH (min) is greater than VIH
Power dissipation: Power dissipation parameter (min), the HIGH output state can tolerate a negative
for a logic family is specified in terms of power con- voltage spike of [VOH (min) VIH (min)] and still be
sumption per gate and is the product of supply volt- legal HIGH input. [VIL (max) VOL (max)] and [VOH
age (VCC) and supply current (ICC). Supply current (min) VIH (min)] are respectively known as LOW-
is taken as the average of HIGH-level supply current level and HIGH-level noise margin.
(ICCH) and LOW-level supply current (ICCL).
Let us illustrate it further with the help of data for stan-
Speed-power product: A useful figure-of-merit dard TTL family. The minimum legal HIGH output
used to evaluate different logic families is the speed- voltage level in case of standard TTL is 2.4 V. Also, the
power product expressed in picojoules, which is the minimum legal HIGH input voltage level for this family
product of propagation delay (measured in nanosec- is 2 V. This implies that when the output of one device
onds) and power dissipation per gate (measured in feeds the input of another; there is an available margin of
milliwatts). 0.4 V. That is, any negative voltage spikes of amplitude
Fan-out: Fan-out is the number of inputs of a logic less than equal to 0.4 V on the signal line do not cause
function that can be driven from a single output any spurious transitions. Similarly, when the output is
Logic `1 Logic `1
VOH(min)
VNH
VIH(min)
Disallowed Indeterminate
Voltage output input voltage
voltage range range
VIL(max)
VNL
VOL(max)
Logic `0 Logic `0
(a) (b)
Figure 24.20| Noise margin.

in logic LOW state, maximum legal LOW output volt- VCC

age level in case of standard TTL is 0.4 V. Also, the R1 R2 R3
maximum legal LOW input voltage level for this family 4 kW 1.6 kW 130 W
is 0.8 V. This implies that when the output of one device
feeds the input of another; there is again an available
margin of 0.4 V. That is, any positive voltage spikes of
amplitude less than equal to 0.4 V on the signal line do Q1 Q3
not cause any spurious transitions. This leads to the fact D1
that standard TTL family offers a noise margin of 0.4 V. Input A Y
To generalize, noise margin offered by a logic family, as Input B Q2
outlined earlier, can be computed from the HIGH-state
noise margin, VNH = VOH (min) VIH (min) and LOW- R4 Q4
state noise margin, VNL = VIL (max) VOL (max). If D2 D3 1 kW
the two values are different, noise margin is taken as the
lower of the two. GND
Figure 24.21| Standard TTL NAND gate.
24.6 TRANSISTORTRANSISTOR
functions being driven by the output. When either of
LOGIC the two inputs or both inputs are in logic LOW state,
base-emitter region of Q1 conducts current driving Q2 to
cut-off in the process. When Q2 is in cut-off state, Q3 is
A transistortransistor logic (TTL) is a logic family
driven to conduction and Q4 to cut-off. This produces
implemented with bipolar process technology that com-
a logic HIGH output with VOH (min) = 2.4 V guar-
bines or integrates NPN transistors, PN junction diodes
anteed for minimum supply voltage, VCC, and source
current of 400 A. Transistors Q3, Q4 constitute what
and diffused resistors in a single monolithic structure
to get the desired logic function. NAND-gate is the
is known as totem-pole output arrangement. In such an
basic building block of this logic family. Different sub-
arrangement, either Q3 or Q4 conducts at a time depend-
families in this logic family include standard TTL, Low
ing upon logic status of inputs. The totem-pole arrange-
power TTL, high power TTL, low power Schottky TTL,
ment at the output has certain distinct advantages. The
Schottky TTL, advanced low power Schottky TTL,
major advantage of using totem-pole connection is that
advanced Schottky TTL and fast TTL. In the follow-
it offers low output impedance in both HIGH and LOW
ing sections, we shall briefly describe each of these sub-
output states. In HIGH state, Q3 acts as an emitter fol-
lower and has an output impedance of about 70 . In
families in terms of internal structure and characteristic
parameters.
LOW state, Q4 is saturated and the output impedance is
approximately 10 . Because of low output impedance,
24.6.1 Standard TTL any stray capacitance at the output can be charged or
discharged very rapidly through this low impedance thus
Figure 24.21 shows the internal schematic of a stan- allowing quick transitions at the output from one state
dard TTL NAND gate. It is one of the four circuits of to the other. Another advantage is that when the output
5400/7400, which is a quad two-input NAND gate. The is in logic LOW state, transistor Q4 would need to con-
circuit operates as follows:Q1 is a two-emitter NPN tran- duct a fairly large current if its collector were tied to VCC
sistor, which is equivalent to two NPN transistors with through R3 only. A non-conducting Q3 overcomes this
their base and emitter terminals tied together. The two problem. A disadvantage of totem-pole output configu-
emitters are the two inputs of the NAND gate. Diodes ration results from switch-off action of Q4 being slower
D2 and D3 are used limit negative input voltages. than the switch-on action of Q3. Due to this, there will
When both inputs are in logic HIGH state as speci- be a small fraction of time of the order of a few nano-
fied by the TTL family (VIH = 2 V minimum), current seconds when both the transistors are conducting thus
flows through the basecollector PN junction diode of drawing heavy current from the supply. The character-
transistor Q1 into the base of transistor Q2. Now, Q2 is istic parameters and features of standard TTL family of
turned ON to saturation with the result that transis- devices include the following:
tor Q3 is switched OFF and transistor Q4 is switched
Minimum HIGH-level input voltage, VIH = 2 V
ON. This produces a logic LOW at the output with VOL
being 0.4 V maximum when it is sinking a current of 16 Maximum HIGH-level input current, IIH = 40 mA
mA from external loads represented by inputs of logic Maximum LOW-level input voltage, VIL = 0.8 V

24.6 TRANSISTORTRANSISTOR LOGIC 553
Maximum LOW-level input current, IIL = 1.6 mA consumption. Figure 24.22 shows the internal schematic
Minimum HIGH-level output voltage, VOH = 2.4 V of Schottky TTL NAND gate. The circuit shown is that
of one of the four gates inside quad two-input NAND,
Maximum HIGH-level output current, IOH = 400 mA type 74S00 or 54S00. The transistors used in the circuit
Maximum LOW-level output voltage, VOL = 0.4 V are all Schottky transistors with the exception of Q5. A
Maximum LOW-level output current, IOL = 16 mA Schottky Q5 would serve no purpose with Q4 being a
Schottky transistor. A Schottky transistor is nothing but
Supply voltage, VCC = 4.75-5.25 V(74-series) and a conventional bipolar transistor with a Schottky diode
4.5-5.5 V(54-series) connected between its base and collector terminals.
Propagation delay (for load resistance of 400 and Schottky diode with its metalsemiconductor junction
load capacitance of 15 pF and an ambient temperature is not only faster but also offers a lower forward voltage
of 25C) = 22 ns (max) for LOW-to-HIGH transition drop of 0.4 V as against 0.7 V for a PN junction diode for
at the output and 15 ns (max) for HIGH-to-LOW the same value of forward current. Presence of Schottky
output transition. diode does not allow the transistor to go to deep satura-
Worst case noise margin = 0.4 V tion. While the power consumption of a Schottky TTL
gate is almost the same as that of a high power TTL
Fan-out = 10 gate due to nearly same values of resistors used in the
Maximum HIGH-level supply current, ICCH (for all circuit, Schottky TTL offers a higher speed due to use of
the four gates) = 8 mA Schottky transistors.
Maximum LOW-level supply current, ICCL (for all the
four gates) = 22 mA
Operating temperature range = 0 to 70C (74-series) +VCC
and 55 to +125C (54-series)
R1 R2 R3
Speed-power product = 100 pJ 2.8kW 900W 50W
Maximum flipflop toggle frequency = 35 MHz Q1
Q3
Input A
24.6.2 Low-Power TTL
Q2 R5 Q5
3.5kW Y
Low power TTL is low power variant of standard TTL
where lower power dissipation is achieved at the expense Input B R4
R6 Q4
of reduced speed of operation. The internal circuit of a D1 D2 500W 250W
low power TTL NAND gate is same as that of standard
TTL NAND gate except for increased resistance value Q6
of different resistors used in the circuit. Increased resis-
tance values lead to lower power dissipation. GND
Figure 24.22| NAND gate in the Schottky TTL.
24.6.3 High-Power TTL
High power TTL is high power, high speed variant of

24.6.5 Low-Power Schottky TTL
standard TTL where improved speed (reduced propa-
gation delay) is achieved at the expense of higher
Low power Schottky TTL is low power consumption
power dissipation. The internal circuit is nearly same
variant of Schottky TTL. Figure 24.23 shows the inter-
as that of standard TTL NAND-gate except for the
nal schematic of low power Schottky TTL NAND gate.
transistor Q3-diode D1 combination in the totem-pole
We can notice the significantly increased value of resis-
output stage having been replaced by a Darlington
tors R1 and R2 used to achieve lower power consumption.
arrangement and decreased resistance value of different
Another noticeable difference in the internal schematics
resistors.
of low power Schottky TTL NAND and Schottky TTL
NAND is the replacement of multi-emitter input transis-
24.6.4 Schottky TTL (74S/54S) tor of Schottky TTL by diodes D1 and D2, and resis-
tor R1. The junction diodes basically replace the two
Schottky TTL offers a speed that is about twice emitterbase junctions of the multi-emitter input tran-
that offered by high power TTL for the same power sistor Q1 of Schottky TTL NAND.

VCC
R1 R2 R3
20 kW 8 kW 120 W
D1
InputA
Q2
Input B D3
Q1
D2 R4 Q3
R5 Y
12 kW
4 kW
D4
D5 D6 Q5
R6 R7
1.5 kW 3 kW
Q4
GND
Figure 24.23| NAND gate in the low-power Schottky TTL.
24.6.6 Advanced Low-Power Schottky to reduced epitaxial layer-substrate capacitance,

and Advanced Schottky TTL which further reduces the switching times.
5. Both ALS-TTL and AS-TTL offer improved input
In the TTL subfamilies discussed so far, we have seen threshold voltage and reduced low-level input
that different subfamilies achieved improved speed at current.
the expense of increased power consumption or vice 6. Both ALS-TTL and AS-TTL feature active turn-
versa. For example, low power TTL offered lower off of the LOW-level output transistor producing a
power consumption over standard TTL at the cost of better HIGH-level output voltage and thus higher
reduced speed. High power TTL, on the other hand, HIGH-level noise immunity.
offered improved speed over standard TTL at the
expense of increased power consumption. Advanced 24.7 EMITTER-COUPLED LOGIC
low power Schottky TTL and advanced Schottky
TTL incorporate certain new circuit design features
and fabrication technologies to achieve improvement Emitter coupled logic (ECL) family is the fastest logic
of both parameters. Both ALS-TTL and AS-TTL family in the group of bipolar logic families. The charac-
offer an improvement in speedpower product, respec- teristic features that give this logic family its high speed
tively, over LS-TTL and S-TTL by a factor of four. or short propagation delay are outlined as under:
Salient features of ALS-TTL and AS-TTL include the 1. It is a non-saturating logic. That is, the transis-
following: tors in this logic are always operated in the active
1. All saturating transistors are clamped by using region of their output characteristics. They are
Schottky diodes. This virtually eliminates storage never driven to either cut-off or saturation, which
of excessive base charge thus significantly reducing means that logic LOW and HIGH states corre-
the turn-off time of the transistors. Elimination of spond to different states of conduction of various
transistor storage time also provides stable switch- bipolar transistors.
ing times over the entire operational temperature 2. The logic swing, that is, the difference in the
range. voltage levels corresponding to logic LOW and
2. Inputs and outputs are clamped by Schottky diodes HIGH states is kept small (typically 0.85 V) with
to limit the negative-going excursions. the result that the output capacitance needs to
3. Both ALS-TTL and AS-TTL use ion implantation be charged and discharged by a relatively much
rather than diffusion process, which allows use of smaller voltage differential.
small geometries leading to smaller parasitic capac- 3. The circuit currents are relatively high and the
itances and hence reduced switching times. output impedance is low with the result that the
4.Both ALS-TTL and AS-TTL use oxide isolation rather output capacitance can be charged and discharged
than junction isolation between transistors. This leads quickly.

24.7 EMITTER-COUPLED LOGIC 555
The different subfamilies of ECL logic include MECL- as their base-emitter junctions are not forward biased
I, MECL-II, MECL-III, MECL 10K, MECL 10H and by required voltage. This further leads us to say that
MECL 10E (ECLinPSTM and ECLinPS LiteTM). transistor Q7 is conducting, producing logic `0 output
and transistor Q8 is in cut-off producing logic `1 output.
In the next step, let us see what happens if any one or
24.7.1 Logic Gate Implementation in ECL
all of the inputs are driven to logic `1 status, that is, a
OR/NOR is the fundamental logic gate of ECL family. nominal voltage of 0.9 V is applied to the inputs. Base
Figure 24.24 shows the typical internal schematic of OR/ emitter voltage differential of transistors Q1 to Q4 exceeds
NOR gate in 10K-series MECL family. The circuit in the required forward biasing threshold with the result
essence comprises of a differential amplifier input circuit these transistors start conducting. This further leads to
with one side of the differential pair having multiple tran- rise in voltage at the common-emitter terminal, which
sistors depending upon the number of inputs to the gate, now becomes approximately 1.7 V as the common emit-
a voltage and temperature compensated bias network ter terminal is now 0.8 V more negative than the base
and emitter follower outputs. The internal schematic of terminal voltage. With rise in common-emitter termi-
10H-series gate is similar with the exceptions that bias nal voltage, the baseemitter differential voltage of Q5
network is replaced by a voltage regulator circuit and becomes 0.31 V driving Q5 to cut-off. Q7 and Q8 emitter
the source resistor (REE) of the differential amplifier is terminals, respectively, go to logic `1 and logic `0.
replaced by a constant current source. Typical values of This explains how this basic schematic functions as
power supply voltages are VCC = 0 and VEE = 5.2 V. OR/NOR gate. We shall note that differential action of
Nominal logic levels are logic LOW = logic `0 = 1.75 the switching transistors (where one section is ON while
V and logic HIGH = logic `1 = 0.9 V assuming a posi- other is OFF) leads to simultaneous availability of com-
tive logic system. plementary signals at the output. Figure 24.25 shows the
The circuit functions as follows: The bias network circuit symbol and switching characteristics of this basic
configured around transistor Q6 produces a voltage of ECL gate. It may be mentioned here that positive ECL
typically 1.29 V at its emitter terminal. This leads to (called PECL) devices operating at +5 V and ground are
a voltage of 2.09 V at the junction of all emitter ter- also available. ECL devices when used in PECL mode
minals of various transistors in the differential amplifier must have their input/output DC parameters adjusted
assuming 0.8 V as the required forward biased PN junc- for proper operation. PECL DC parameters can be com-
tion voltage. Now, let us assume that all inputs are in puted by adding ECL levels to the new VCC.
logic `0 state, that is, voltage at the base terminals of We shall also note that voltage changes in ECL are
various input transistors is 1.75 V. This means that small, largely governed by VBE of various conducting
the transistors Q1, Q2, Q3 and Q4 shall remain in cut-off transistors. In fact, the magnitude of currents flowing
VCC
NOR O/P Q Q7 OR O/P

8
Q6
Q2 Q3 Q4 Q5
Q1
REE
Bias
network
VEE
Inputs
Figure 24.24| OR/NOR in ECL.

0.8
HIGH
Output voltage (Volts)

(typ.0.9 V)
1.0
1.2
A OR
B 1.4
C
D NOR
1.6
1.8 LOW
(typ.1.75 V)
1.5 1.4 1.3 1.2 1.1 1.0
Input voltage (Volts)
Figure 24.25| ECL input/output characteristics.
through various conducting transistors is of greater rel- 24.8 CMOS LOGIC FAMILY
evance to the operation of the ECL circuits. It is because
of this reason that emitter coupled logic is also some-
times called current mode logic. CMOS (complementary metal oxide semiconductor)
logic family uses both N-type and P-type MOSFETs
(enhancement MOSFETs to be more precise) to realize
24.7.2 Salient Features of ECL
different logic functions. The two types of MOSFETs
There are many features possessed by MECL family are designed to have matching characteristics. That is,
devices other than their high speed characteristics, which they exhibit identical characteristics in switch-OFF and
make them attractive for many high performance appli- switch-ON conditions. The main advantage of CMOS
cations. The major ones include the following: logic families over bipolar logic families discussed so
far lies in its extremely low power dissipation, which is
1. ECL family devices produce the true and comple- nearly zero in static conditions. In fact, CMOS devices
mentary output of the intended function simul- draw power only when they are switching. This allows
taneously at the outputs without the use of any integration of much larger number of CMOS gates on
external inverters. This in turn reduces package a chip than would have been possible with bipolar or
count, reduces power requirements and also mini- NMOS (to be discussed later) technology. CMOS tech-
mizes problems arising out of time delays that nology today is the dominant semiconductor technology
would be caused by external inverters. used for making microprocessors, memory devices and
2.ECL gate structure inherently has high input imped- application specific integrated circuits (ASICs).
ance and low output impedance, which is very condu-
cive to achieving large fan-out and drive capability.
3. ECL devices with open emitter outputs allow them 24.8.1 Circuit Implementation of Logic
to have transmission line drive capability. The out- Functions
puts match any line impedance. Also, absence of
any pull-down resistors saves power. In the following subsections, we shall briefly describe
4. ECL devices produce a nearly constant current internal schematics of CMOS inverter, NAND and NOR
drain on the power supply, which simplifies power logic functions.
supply design.
5. Due to differential amplifier design, ECL devices 24.8.1.1 CMOS Inverter
offer a wide performance flexibility, which allows
ECL circuits to be used both as linear as well as Inverter is the most fundamental building block of CMOS
digital circuits. logic. It consists of a pair of N-channel and P-channel
6. Termination of unused inputs is easy. Resistors MOSFETs connected in cascade configuration as shown
of approximately 50 k allow unused inputs to in Fig. 24.26. The circuit functions as follows: When the
remain unconnected. input is in HIGH-state (logic `1), P-channel MOSFET,

24.8 CMOS LOGIC FAMILY 557
Q1, is in cut-off state while the N-channel MOSFET input combinations, either of the two N-channel devices
Q2 is conducting. The conducting N-channel MOSFET will be non-conducting and either of the two parallel
provides a path from ground to output and the output connected P-channel devices will be conducting. Either
is LOW (logic `0). When the input is in LOW-state we have Q3 OFF and Q2 ON or Q4 OFF and Q1 ON.
(logic `0), Q1 is in conduction while Q2 is in cut-off. The output in both cases is logic `1, which verifies the
Conducting P-channel device provides a path for VDD to remaining entries of the truth table. From the schematic
appear at the output so that the output is in HIGH or diagram of the circuit shown in Fig. 24.27, we can
logic `1 state. A floating input could lead to conduction visualize that under no possible input combination of
of both MOSFETs and a short circuit condition. It logic states is there a direct conduction path between
should therefore be avoided. It is also evident from VDD and ground. This further confirms that there is
Fig. 24.26 that there is no conduction path between near zero power dissipation in CMOS gates under static
VDD and ground in both input conditions, that is, when conditions.
input is in logic `1 and `0 states. That is why; there is
practically zero power dissipation in static conditions. VDD
There is only dynamic power dissipation, which occurs
during switching operations as the MOSFET gate
capacitance is charged and discharged. The power dis-
sipated is directly proportional to switching frequency. Q2 Q1
Y=A.B
VDD
A Q3
Q1
Q4
B
A Y=A
Figure 24.27| CMOS NAND.

Q2
24.8.1.3 NOR Gate
Figure 24.28 shows the basic circuit implementation of a

Figure 24.26| CMOS inverter. two-input NOR. As shown in the figure, two P-channel
MOSFETs, Q1 and Q2 are connected in series between
VDD and the output terminal and two N-channel
24.8.1.2 NAND Gate MOSFETs, Q3 and Q4 are connected in parallel between
ground and output terminal. The circuit operates as fol-
Figure 24.27 shows the basic circuit implementation of a lows. For the output to be in logic `1 state, it is essential
two-input NAND. As shown in the figure, two P-channel that both the series connected P-channel devices con-
MOSFETs, Q1 and Q2, are connected in parallel between duct and both the parallel connected N-channel devices
VDD and the output terminal and two N-channel remain in cut-off state. This is possible only when both
MOSFETs, Q3 and Q4, are connected in series between the inputs are in logic `0 state. This verifies one of the
ground and output terminal. The circuit operates as fol- entries of the truth table of NOR gate. When both the
lows. For the output to be in logic `0 state, it is essential inputs are in logic `1 state, both the N-channel devices
that both the series connected N-channel devices con- are conducting and both the P-channel devices are non-
duct and both the parallel connected P-channel devices conducting, which produces logic `0 at the output.
remain in cut-off state. This is possible only when both This verifies another entry of NOR truth table. For the
the inputs are in logic `1 state. This verifies one of remaining two input combinations, either of the two par-
entries of NAND-gate truth table. When both the inputs allel N-channel devices will be conducting and either of
are in logic `0 state, both the N-channel devices are non- the two series connected P-channel devices will be non-
conducting and both the P-channel devices are conduct- conducting. Either we have Q1 OFF and Q3 ON or Q2
ing, which produces logic `1 at the output. This verifies OFF and Q4 ON. The output in both cases is logic `0,
another entry of NAND truth table. For the remaining two which verifies the remaining entries of the truth table.

VDD the gates as shown in Fig. 24.29(b). The control inputs

to the gate terminals of two MOSFETs are complement
of each other. This is ensured by an inbuilt inverter.
A When control input is HIGH (logic `1), both devices
Q1 are conducting and the switch is closed. When control
input is LOW (logic `0), both devices are open and the
therefore the switch is open. It may be mentioned here
B that there is no discrimination between input and output
Q2 terminals. Either of the two can be treated as the input
terminal for the purpose of applying input. This is made
Y = (A + B) possible due to symmetry of the two MOSFETs.
24.8.2 CMOS with Open Drain Outputs

Q3 Q4
Outputs of conventional CMOS gates should never be
shorted together as is illustrated in case of two inverters
Figure 24.28| Two-input NOR in CMOS. shorted at the output terminals (Fig. 24.30). If the input
conditions are such that output of one inverter is HIGH
24.8.1.4 Transmission Gate and that of the other is LOW, the output circuit then is
like a voltage divider network with two identical resistors
Transmission gate, also called bilateral switch, is exclu- equal to ON-resistance of a conducting MOSFET. The
sive to CMOS logic and does not have a counterpart in output is then approximately equal to VDD/2, which lies
TTL and ECL families. It is essentially a single-pole sin- in the indeterminate range and therefore unacceptable.
gle-throw switch (SPST). The opening and closing opera- Also, an arrangement like this draws excessive current
tions can be controlled by externally applied logic levels. and could lead to device damage.
Figure 24.29(a) shows the circuit symbol. If logic `0 at
the control input corresponds to an open switch, then
logic `1 corresponds to a closed switch and vice versa. +VDD
Control Output
Input Output +VDD
(a)
Control
Figure 24.30| CMOS inverters with shorted outputs.
Input Output
This problem does not exist in CMOS gates with open
drain outputs. Such a device is counterpart of gates
with open collector outputs in TTL family. The output
stage of a CMOS gate with open drain output is a single
(b) N-channel MOSFET with an open drain terminal and
Figure 24.29| Transmission gate.
there is no P-channel MOSFET. The open drain termi-
nal needs to be connected to VDD through an external
pull-up resistor. Figure 24.31 shows the internal sche-
The internal schematic of a transmission gate is nothing matic of CMOS inverter with open drain output. The
but a parallel connection of an N-channel MOSFET and pull-up resistor shown in the circuit is external to the
a P-channel MOSFET with the control input applied to device.

24.8 CMOS LOGIC FAMILY 559
+VDD connected to ground or VDD or shorted to another input.

The same is applicable to the inputs of all those gates,
Output which are not in use. For example, we may be using
protection only two of the four gates available on an IC having four
diode gates. The inputs of remaining two gates should be tied
Y=A to either ground or VDD.
A 24.8.5 CMOS Subfamilies
In the following paragraphs, we shall briefly describe

Figure 24.31| CMOS inverter with an open drain
various subfamilies of CMOS logic including subfami-
output. lies of 4000-series and those of TTL pin-compatible 74C
series.
24.8.3 CMOS with Tristate Outputs 24.8.5.1 4000 Series
Like tristate TTL, CMOS devices are also available 4000A-series CMOS ICs, introduced by RCA, were the
with tristate outputs. Operation of tristate CMOS first to arrive the scene from the CMOS logic family.
devices is similar to that of tristate TTL. That is, when 4000A CMOS subfamily is obsolete now and has been
the device is enabled, it performs its intended logic replaced by 4000B and 4000UB subfamilies. 4000B series
function and when it is disabled; its output goes to is a high voltage version of 4000A series and also all
high impedance state. In high impedance state, both the outputs in this series are buffered. 4000UB series is
N-channel and P-channel MOSFETs are driven to also a high voltage version of 4000A series but here the
OFF-state. Figure 24.32 shows the internal schematic outputs are not buffered. A buffered CMOS device is one
of a tristate buffer with active LOW ENABLE input. that has constant output impedance irrespective of logic
Outputs of tristate CMOS devices can be connected status of inputs.
together in a bus arrangement like tristate TTL devices
with the same condition that only one device is enabled 24.8.5.2 74C Series
at a time.
74C CMOS subfamily offers pin to pin replacement of
74 series TTL logic functions. For instance, if 7400 is a
+VDD Quad two-input NAND in standard TTL, then 74C00 is
a Quad two-input NAND with same pin connections in
A CMOS. Characteristic parameters of 74C-series CMOS
are more or less same as those of 4000-series devices.
Y=A 24.8.5.3 74HC/HCT Series
74HC/HCT series is the high speed CMOS version of the

74C-series logic functions. This is achieved using silicon
gate CMOS technology rather than metal gate CMOS
Enable
technology used in earlier 4000-series CMOS subfamilies.
Figure 24.32| Tristate buffer in CMOS. 74HCT series is only a process variation of 74HC series.
74HC/HCT series devices have an order of magnitude
higher switching speed and also a much higher output
24.8.4 Floating or Unused Inputs drive capability than the 74C-series devices. This series
also offers pin-to-pin replacement of 74-series TTL logic
Unused inputs of CMOS devices should never be left functions. 74HCT-series devices in addition have TTL
floating or unconnected. A floating input is highly sus- compatible inputs.
ceptible to picking up noise and accumulating static
charge. This can often lead to simultaneous conduction 24.8.5.4 74AC/ACT Series
of P-channel and N-channel devices on the chip, which
further causes increased power dissipation and over- 74AC-series is presently the fastest CMOS logic family.
heating. Unused inputs of CMOS gates should either be This logic family has the best combination of high speed,

low power consumption and high output drive capabil- complex digital ICs belonging to the class of small
ity. Again, 74ACT is only a process variation of 74AC. scale integration (SSI) and medium scale integration
74ACT-series devices in addition has TTL compatible (MSI) level of inner circuit complexities. The TTL,
inputs. the CMOS and the ECL logic families are not suitable
for implementing digital ICs that have large scale
integration (LSI) and above level of inner circuit
24.8.6 BiCMOS LOGIC complexity. The competitors for LSI class digital
ICs are the PMOS, the NMOS and the integrated
BiCMOS logic family integrates bipolar and CMOS injection logic (I2L).
devices on a single chip with the objective of deriving the
advantages individually present in bipolar and CMOS
logic families. While bipolar logic families such as TTL
24.8.7.1 PMOS Logic
and ECL have the advantages of faster switching speed
PMOS logic family uses P-channel MOSFETs. Figure
and larger output drive current capability; CMOS logic
24.33(a) shows an inverter circuit using PMOS logic.
scores over bipolar counterparts where it comes to lower
MOSFET Q1 acts as an active load for the MOSFET
power dissipation, higher noise margin and larger pack-
switch Q2. For the circuit shown, GND and -VDD,
ing density. BiCMOS logic attempts to get the best of
respectively, represent logic `1 and logic `0 for a positive
both worlds.
logic system. When the input is grounded (i.e., logic `1),
Two major categories of BiCMOS logic devices have Q2 remains in cut-off and -VDD appears at the output
emerged over the years since its introduction in 1985. In through the conducting Q1. When the input is at -VDD
one type of devices, moderate speed bipolar circuits are or close to -VDD, Q2 conducts and the output goes to
combined with high performance CMOS circuits. Here, near zero potential (i.e., logic `1).
CMOS circuitry continues to provide low power dissipa-
Figure 24.33(b) shows the PMOS logic based two-input
tion and larger packing density. Selective use of bipolar
NOR gate. In the logic arrangement of Fig. 24.33(b), the
circuits gives improved performance. In the other cat-
output goes to logic `1 state (i.e., ground potential) only
egory, bipolar component is optimized to produce high
when both Q1 and Q2 are conducting. This is possible
performance circuitry.
only when both the inputs are in logic `0 state. For all
other possible input combinations, the output is in logic
24.8.7 NMOS AND PMOS LOGIC `0 state, because with either Q1 or Q2 non-conducting,
the output is nearly -VDD through the conducting Q3.
Logic families discussed so far are the ones that The circuit shown in Fig. 24.33(b) thus behaves like two-
are commonly used for implementing discrete logic input NOR gate in the positive logic. It may be men-
functions such as logic gates, flip flops, counters, tioned here that the MOSFET being used as load [Q1
multiplexers, demultiplexers etc. in relatively less in Fig. 24.33(a); Q3 in Fig. 24.33(b)] is so designed as to
VDD VDD
Q1 Q3
Y=A Y = (A + B)
A
A Q2
Q2
B
Q1
(a) (b)
Figure 24.33| (a) PMOS logic inverter and (b) PMOS logic two-input NOR.

24.9 COMPARISON OF DIFFERENT LOGIC FAMILIES 561
+VDD +VDD +VDD
Q3
Q1 Q3
Y=A Y = (A + B)
A
A Q2
Y=A B
Q2 A B
B
Q1 Q2 Q1
(a) (b) (c)

Figure 24.34| (a) NMOS logic inverter, (b) NMOS logic two-input NOR, and (c) NMOS logic two-input NAND.
have an ON-resistance that is much greater than the total further reducing the propagation delay. Figures 24.34(a),
ON- resistance of the MOSFETs being used as switches (b) and (c), respectively, show an inverter, a two-input
[Q2 in Fig. 24.33(a); Q1 and Q2 in Fig. 24.33(b)]. NOR and a two-input NAND using NMOS logic. The
logic circuits are self-explanatory.
24.8.7.2 NMOS Logic
NMOS logic family uses N-channel MOSFETs. N-channel 24.9 COMPARISON OF DIFFERENT
MOS devices require a smaller chip area per transistor LOGIC FAMILIES
as compared to P-channel devices with the result that
NMOS logic offers a higher density. Also due to greater
mobility of charge carriers in N-channel devices, NMOS Table 24.1 shows a comparison of various performance
logic family offers higher speed too. It is because of this characteristics of important logic families for quick ref-
reason that most of the MOS memory devices and micro- erence. The data given in case of CMOS families is for
processors employ NMOS logic or some variation of it VDD = 5 V. In case of ECL families, the data is for VEE
such as VMOS, DMOS and HMOS. VMOS, DMOS and = -5.2 V. The values of various parameters given in the
HMOS are only structural variations of NMOS aimed at table should be used only for rough comparison.
Table 24.1| Comparison of various performance characteristics of important logic families.
Maximum
Flip-flop
Typical Worst-case Toggle
Supply Propagation Noise Speed-power Frequency
Logic Family Voltage (V) Delay (ns) Margin (V) Product (pJ) (MHz)
TTL Standard 4.5 to 5.5 17 0.4 100 35
L 4.5 to 5.5 60 0.3 33 3
H 4.5 to 5.5 10 0.4 132 50
S 4.5 to 5.5 5 0.3 57 125
LS 4.5 to 5.5 15 0.3 18 45
ALS 4.5 to 5.5 10 0.3 4.8 70
AS 4.5 to 5.5 4.5 0.3 13.6 200
F 4.5 to 5.5 6 0.3 10 125
(Continued)

Table 24.1| Continued

Maximum
Flip-flop
Typical Worst-case Toggle
Supply Propagation Noise Speed-power Frequency
Logic Family Voltage (V) Delay (ns) Margin (V) Product (pJ) (MHz)
CMOS 4000 3 to 15 150 1.0 5 12
74C 3 to 13 50 1.4 5 12
74HC 2 to 6 8 0.9 1.4 40
74HCT 4.5 to 5.5 8 1.4 1.4 40
74AC 2 to 6 4.7 0.7 0.37 100
74ACT 4.5 to 5.5 4.7 0.729 0.37 100
ECL MECL III 5.1 to 5.3 1 0.2 60 500
MECL 10K 4.68 to 5.72 2.5 0.2 50 200
MECL 10H 4.94 to 5.46 1 0.15 25 250
ECLINPS TM
4.2 to 5.5 0.5 0.15 10 1000
ECLINPS 4.2 to 5.5 0.2 0.15 10 2800
TM
LITE
IMPORTANT FORMULAS
1. Fan-out of a logic family = IOH/IIH or IOL/IIL,

5. NOT gate: Y = A
whichever is lower.
6. NAND gate: Y = A B C D
2. Figure-of-merit of a logic family = tP PD, where
tP = propagation delay and PD = power dissipa- 7. NOR gate: Y = A + B + C + D
8. EX-OR gate: Y = A B = AB + AB
tion per gate.
3. AND gate: Y = A B C D
9. EX-NOR gate: Y = A B = A B + A B
4. OR gate: Y = A + B + C + + D
SOLVED EXAMPLES

1. A NOT gate can be implemented using only NAND 2. A NOT gate can be implemented using a two-input
gates by EX-OR gate by
(a) shorting all inputs to get a one-input, one-output (a) s horting all inputs to get a one-input, one-out-
logic device put logic device
(b) applying complement of the input to one of the (b) applying input to one of the inputs and tying
inputs and a logic `1 to the other input the other input permanently to logic `1
(c) applying input to one of the inputs and a logic (c) applying input to one of the inputs and tying
`0 to the other input the other input permanently to logic `0
(d) none of these (d) applying input to one of the inputs and con-
Solution. Referring to the truth table of a NAND necting the other input to output
gate, all `0 inputs would give logic `1 output and
all `1 inputs will give a logic `0 output and hence Solution. Referring to the truth table of EX-OR
the answer. gate, if one of the inputs were in logic `1 state,
Ans. (a) then a logic `1 at the other input would produce

SOLVED EXAMPLES 563
a logic `0 at the output and logic `0 at the other output of second AND gate along with fourth input
input would produce a logic `1 at the output and are applied to the third AND gate. Output of third
hence the answer. AND gate is then the final output.
Ans. (b) Ans. (a)
3. According to one of the theorems of Boolean alge- 7. The figure-of-merit of a logic family is often mea-
bra, a NAND gate is equivalent to a bubbled OR sured in the units of
gate and a NOR gate is equivalent to a bubbled (a) nanoseconds (b) microwatts
AND gate. Name the theorem. (c) picojoules (d) megahertz
(a) Involution theorem Solution. Figure-of-merit is measured as the prod-
(b) Absorption law uct of speed and power. Speed here is represented
(c) Complementation theorem as propagation delay which is generally measured
(d) De Morgans theorem in nanoseconds. Power is the power dissipation per
gate which is measured in milliwatts. The product
Solution. A bubbled gate is the gate where the of the two has units of picojoules.
inputs to the gate are inverted. A NAND gate is Ans. (c)
represented by
8. Of the various commonly used logic families, the
Y = AB one with highest speed and the one with least
According to De Morgans theorem, it equals power dissipation, respectively, are
(a) TTL and CMOS (b) CMOS and TTL
Y = A+B
(c) CMOS and ECL (d) ECL and CMOS
Here, A + B represents a bubbled OR gate, that Solution. ECL being a non-saturating bipolar
is, an OR gate whose inputs are A and B. It can logic family is the fastest and CMOS inherently
be similarly be explained for a NOR gate. dissipates least power due to use of MOS devices.
Ans. (d) Ans. (d)
4. In a certain logic gate, the output is always in logic 9. Logic gates with associated hysteresis are called
`1 state except for one input combination when all
(a) INHIBIT gates (b) Schmitt gates
inputs are in logic `1 state. Name the gate.
(c) Universal gates (d) None of these
(a) NAND (b) NOR (c) EX-OR (d) AND
Solution. Schmitt gates have different threshold
Solution. The answer is evident from the truth voltage levels for LOW-to-HIGH and HIGH-to-
table of a NAND gate [see the truth table of a two- LOW transitions at the output. This allows them
input NAND gate shown in Fig. 24.5(c)]. to prevent an erratic output in the presence of slow
Ans. (a) varying inputs.
Ans. (b)
5. One of the following logic gates can be called a
universal gate. 10. Arrange the following logic families in the order
of increasing speed: CMOS, low power Schottky
(a) AND (b) OR (c) NOR (d) EX-OR TTL, ECL, Schottky TTL, low power TTL.
Solution. NAND and NOR are called universal (a) C MOS, low power TTL, TTL, low power
gates as they can be used to implement all logic Schottky TTL, Schottky TTL and ECL
gate functions. (b) Low power TTL, CMOS, TTL, Schottky TTL,
Ans. (c) low power Schottky TTL and ECL
6. Minimum number of two-input AND gates required (c) ECL, Schottky TTL, low power Schottky TTL,
to implement a four-input AND gate would be TTL, low power TTL and CMOS
(d) TTL, low power TTL, ECL, CMOS, low power
(a) 3 (b) 2 (c) 4 (d) 5 Schottky TTL, Schottky TTL
Solution. The four inputs are applied to two two- Solution. Referring to Table 24.1, we get the
input AND gates. The two outputs from these AND answer as follows:
gates are then applied to the inputs of a third AND
gate whose output is the final output. Alternatively, CMOS < low power TTL < TTL < low power
the output of the first AND gate along with the Schottky TTL < Schottky TTL < ECL
third input are applied to the second AND gate and Ans. (a)


1. What is the minimum number of two-input EX-OR Therefore, the number of two-input EX-NOR gates
gates needed to implement a three-input EX-OR that can be used to implement one three-input
gate? EX-NOR gate function is 3.
Ans. (3)
Solution. Following figure shows the implementa-
tion of a three-input EX-OR logic function using 4. The logic gate shown in the following figure is an
two-input logic gates. X-wide, Y-input OR-AND-INVERT gate. What is
the value of Y?
A Y1
Y A
B
C B
For this figure, the output Y1 is given by C
(A B) D Y
Final output Y is given by E
Y = (Y1 C ) = (A B) C = A B C F
Therefore, the minimum number of two-input G
EX-OR gates needed to implement a three-input
EX-OR gate is 3. Ans. (3) H
2. What is the minimum number of two-input NAND Solution. There are four two-input OR gates
gates required to implement a three input NAND? at the input whose outputs have been fed to an
Solution. Figure below shows the arrangement, NAND gate. Therefore, Y = 2.
which is self-explanatory. First step is to get a two- Ans. (2)
input AND from a two-input NAND. Output of 5. In the logic arrangement shown in the following
two-input AND gate and the third input together figure, how many minterms will the logic expres-
feed the inputs of another two-input NAND to get sion for the output, Y, have?
the desired output.
+V
A AB
AB
B
C A
Y
Y = ABC B
Therefore, the minimum number of two-input C
NAND gates required to implement a three-input
NAND is 3. D
3. How many two-input EX-NOR gates can be used to
implement one three-input EX-NOR gate function? Solution. The NAND gates used in the circuit are
open collector gates. Paralleling of the two NAND
Solution. Figure below shows the arrangement. gates at the input lead to a wire-AND connection.
First two EX-NOR gates implement a two-input Therefore, the logic expression at the point where
EX-OR gate. Second EX-NOR gate here has the two outputs combine is given by AB CD.
been wired as a NOT circuit. The output of the Using De Morgans theorem,
second gate and the third input are fed to the
two inputs of the third EX-NOR gate. AB CD = AB + CD
A The third NAND is wired as an inverter. Therefore,

A+B
A+B the final output is given by the Boolean function
B
0
Y = AB + CD
C Therefore, the logic expression for the output, Y,
has the total number of minterms 2.
Y = A+B+C Ans. (2)

6. A Schottky TTL logic gate has following specifica- Solution. Average supply current is
tions: (1) Maximum output HIGH-state current =
ICCH + ICCL 1.6 + 4.4
1 mA, (2) Maximum output LOW-state current = = 3 mA
= 20 mA, (3) Maximum input HIGH-state current 2 2
= 50 A and (4). Maximum input LOW-state cur- The supply voltage is VCC = 5 V. Therefore, the
rent = 2 mA. Determine fan-out. power dissipation for all four gates in the IC is
5 3 = 15 mW
Solution. LOW state fan-out = 20 103/2 103
= 10 and HIGH-state fan-out = 1 103/50 106 Therefore, the average power dissipation per gate
= 20. Fan-out is the lower value of the two values; is given by
therefore, the required fan-out is 10. 15
= 3.75 mW
Ans. (10) 4
Ans. (3.75)
7. Of the following logic families, which serial number
9. Assuming the specifications of NAND gate of
logic family is a CMOS family? 1. 74LS, 2. 74S, 3.
Question 8, how many NAND gate inputs can be
54AS, and 4. 74HC.
driven from the output of a NAND gate?
Solution. 74HC is pin-to-pin TTL compatible Solution. These figures are given by worst case
CMOS logic family. All others are TTL subfami- fan-out specification of the device. Now, the HIGH-
lies. 54AS is MIL-qualified version of 74 AS. state fan-out is
Ans. (4) IOH 400
= = 20
8. Datasheet of a quad two-input NAND gate speci- I IH 20
fies the following parameters:
IOH (max) = 0.4 mA; VOH (min) = 2.7 V; VIH and the LOW state fan-out is
(min) = 2 V; VIL (max) = 0.8 V; VOL (max) = IOL 8
0.4 V; IOL (max) = 8 mA; IIL (max) = 0.4 mA; IIH = = 20
I IL 0.4
(max) = 20 A; ICCH (max) = 1.6 mA; ICCL (max)
= 4.4 mA; supply voltage range = 5 V. Therefore, the number of inputs that can be driven
Determine the average power dissipation of a single from a single output is 20.
NAND gate in mV. Ans. (20)
PRACTICE EXERCISE

1. What is the only input combination that will 4. It is proposed to construct an eight-input NAND
produce logic `0 at the output of a four-input gate using only two-input AND gates and two-
NAND gate? input NAND gates. What is the least number of
gates required to do it?
(a) 1111 (b) 1110 (c) 0000 (d) 1100
(1 Mark) (a) 2 (b) 4 (c) 3 (d) 7
(2 Marks)
2. What is minimum number of two-input NAND
5. An AND gate in positive logic system is a
gates required to implement two-input OR gate?
(a) NOR gate in negative logic system
(a) 2 (b) 3 (c) 4 (d) 5 (b) NAND gate in negative logic system
(2 Marks) (c) AND gate in negative logic system
3. The input to a four-input EX-OR logic function is (d) OR gate in negative logic system
1001. The output would be (1 Mark)
(a) logic `1 6. Refer to the data given below for 4000B-series

(b) logic `0 CMOS and 74LS-TTL. Determine the number of
(c) indeterminate from given data 74LS-TTL inputs that can be reliably driven from
(d) There cannot be a four-input EX-OR logic the output of a single 4000B output.
function 4000B: IOH = 0.4 mA, IIH = 1.0 A, IOL = 0.4 mA,
(1 Mark) IIL = 1.0 A

74LS-TTL: IOH = 0.4 mA, IIH = 20.0 A, IOL = (a) A-1, B-4, C-2, D-3
8.0 mA, IIL = 0.4 mA (b) A-1, B-4, C-3, D-2
(c) A-4, B-1, C-2, D-3
(a) 20 (b) 2 (c) 1 (d) 10
(d) A-4, B-1, C-3, D-2
(2 Marks)
(2 Marks)
7. A two-wide four-input and-or-invert gate uses
9. The basic CMOS two-input NAND gate requires
(a) two four-input AND gates at the input and
their outputs feed a two-input OR gate (a) two N-channel MOSFETs
(b) four two-input AND gates at the input and (b) two N-channel and two P-channel MOSFETs
their outputs feed a two-input NOR gate (c) two P-channel MOSFETs
(c) two four-input AND gates at the input and (d) one N-channel and one P-channel MOSFET
their outputs feed a two-input NOR gate (1 Mark)
(d) two four-input OR gates at the input and their 10.The unused inputs of CMOS logic family should
outputs feed a two-input AND gate never be left open. They should
(2 Marks)
(a) preferably be grounded
8. Match the entries of column I with those in col- (b) preferably be tied to +VDD
umn-II. Identify the correct matching sequence: (c) be tied to logic LOW or logic HIGH level or
another used input
Column I Column II (d) preferably be connected to one of the used
A. TTL 1. Maximum power consumption inputs
B. ECL 2. Highest packing density (2 Marks)
C. NMOS 3. Least power dissipation
D. CMOS 4. Saturated logic
1. The LOW level input and output currents of stan- 6. Two types of bipolar logic families, one saturated
dard TTL family devices are specified as 1.6 mA and and the other non-saturated, have propagation
16 mA, respectively. When the output of a NAND delays of 100 ns and 2 ns. What can possibly be
gate belonging to standard TTL family is in logic the propagation delay (in ns) of non-saturated logic
`0 state and is driving the two shorted inputs of a family?
NOR gate of the same family, what will be the cur-
7. Refer to the logic circuit shown in the following
rent drawn by the input of the driven gate in mA?
figure. What is the logic status of the output, 0 or 1,
(2 Marks)
for A = logic `0 and B = logic `1?
2. In the case discussed in Question 1, if the driven (1 Mark)
gate were a two-input NAND gate instead of a
two-input NOR gate, what would then be the cur-
rent drawn by the input of the driven gate in mA? A
(1 Mark) B
Y
3. Transmission gate, also called a bilateral switch,
is exclusive to CMOS logic family. How many
MOSFETs does a transmission gate comprise of?
(1 Mark)
4. How many possible input combinations can a four- 8. How many NAND gates the TTL IC 7400 have?
input logic gate have? (1 Mark)
(2 Marks)
9. A logic family has a HIGH state fan-out of 20 and
5. A certain logic family has propagation delay and
LOW state fan-out of 10. Which of the two values
power dissipation per gate specifications of 1.0 s
would be considered while deciding the driving
and 0.1 mW, respectively. What is its figure-of-
capability of a logic gate of this family?
merit in picojoules?
(2 Marks)
(1 Mark)


1. (a) A NAND gate gives a logic `0 output only LOW-state current specifications, we can drive
when all inputs are in logic `1 state. For all other only one input and hence the answer.
possible input combinations, output is logic `1.
7. (c) Two-wide means two gates and four input
2. (b) The two NAND gates at the input are wired as means each having four inputs. This gives it the
inverters and their outputs feed the third NAND name two-wide four-input AND. OR-INVERT is
gate. equivalent to NOR and hence the answer.
3. (b) For an EX-OR gate, when the number of logic 8. (c) ECL being a non-saturated logic family has the
1s in the input sequence is even, the output is logic highest power consumption. Of the four logic fami-
`0 and when it is odd; the output is logic `1. lies mentioned, TTL is the only saturated bipolar
4. (d) Four AND gates at the input handle eight logic family. CMOS family has least power dissipa-
inputs. The outputs of first two AND gates feed the tion because of use of MOS devices.
fifth AND gate. The output of the remaining two 9. (b)
AND gates feed the sixth AND gate. The outputs
of fifth and sixth AND gates feed the NAND gate. 10. (c) Unused inputs of CMOS devices should never
be left floating or unconnected. A floating input is
5. (a) If we replace `0 and `1 in the truth table of
highly susceptible to picking up noise and accumu-
AND gate by LOW and HIGH (positive logic
lating static charge. This can often lead to simul-
system) and `0 and `1 in the truth table of NOR
taneous conduction of P-channel and N-channel
gate by HIGH and LOW (negative logic system),
devices on the chip, which further causes increased
we get the same truth table in the two cases.
power dissipation and overheating. Unused inputs
Similarly, an NAND gate in positive logic system is
of CMOS gates should either be connected to
equivalent to an OR gate in negative logic system.
ground or VDD or shorted to another input. The
6. (c) Considering HIGH-state current specifications, same is applicable to the inputs of all those gates,
we can drive 20 inputs whereas considering which are not in use.
1. In the case of NOR gates of TTL logic, the input four-input logic gate has the possible input combi-
side uses multiple bipolar transistors depending upon nations that is equal to 16.
number of inputs to the logic gate. Here, each gate 5. Figure-of-merit in picojoules is given by product of
will therefore draw 1.6 mA and the total LOW level power dissipation in mW and propagation delay in
current drawn by shorted inputs will be 3.2 mA. ns; therefore, the figure of merit in the given case
2. In the case of NAND gates, the input side uses a is 100 picojoules.
multi-emitter single bipolar transistor. As a result 6. Saturated transistors have longer switch-off times.
of this, the LOW level input current drawn by the Therefore, the propagation delay of the given non-
gate will equal the current drawn by a single input, saturated logic family is 2 ns.
that is, 1.6 mA. 7. Logic `0.
3. The number of MOSFETS, a transmission gate 8. IC 7400 is a quad two-input NAND of standard
comprises of, is 2. TTL logic family. Therefore, the total number of
NAND gates the TTL IC 7400 can have is 4.
4. Number of possible input combinations is given by
2n, where n is the number of inputs. Therefore, a 9. Lower of the two values is considered; hence, 10.
1. The following figure shows the internal schematic (a) 0 (b) 1

of a TTL AND-OR-Invert (AOI) gate. For the (c) AB (d) AB
inputs shown in the flowing figure, the output Y is (GATE 2004: 1 Mark)

5V
A 1.4 kW I
Vo
B
Y
Inputs are
floating { IR 1 kW
Solution. For TTL logic, the floating input = 1. (a) 0.65 mA (b) 0.70 mA
Therefore, the output is given by (c) 0.75 mA (d) 1.00 mA
(1 + A B) = 1 = 0 Solution. From the given circuit:
Ans. (a) +5V
2. A Boolean function f of two variables x and y is
defined as follows: 1.4 kW
f(0, 0) = f(0, 1) = f(1, 1) = 1; f(1, 0) = 0 I = 1 mA

Assuming that the complements of x and y are not Q2 Vo
available, a minimum cost solution for realizing f Q1
using only two-input NOR gates and two-input OR Q3
gates (each having unit cost) would have a total +
VBE3

cost of
(a) 1 unit (b) 4 unit 1 kW
(c) 3 unit (d) 2 unit IR
When the output is at logic is zero, Vo = 0V. Also,
Solution. From the truth table, one can draw Vo = 0V, when transistor Q3 is in saturation. When
the Karnaugh map. The simplified Boolean func- transistor Q3 is in saturation, then VBE3 = 0.75V.
tion is Applying KVL in base-emitter loop of transistor
Q3, we get
x+y
IR 1 103 VBE3 = 0
IR = 0.75 103 A = 0.75 mA
The following figure shows that the logic imple-
mentation in the absence of availability of comple-
ments. Therefore, the number of units is 2. Ans. (c)
4. The point P in the following figure is stuck at 1.
y The output f will be
f A
f
x
x
B
Ans. (d)
P
3. The transistor used in a portion of the TTL gate
shown in the figure has a b = 100. The base-emitter
voltage of is 0.7 V for a transistor in active region C
and 0.75 V for a transistor in saturation. If the sink
current I = 1 mA and the output is at logic 0, then (a) ABC (b) A (c) ABC (d) A
current IR will be equal to (GATE 2006: 2 Marks)

Solution. With point P stuck in logic `1 state, 5 0.7 0.7

we have to look at only the last three NAND gates I1 = A = 0.72 m A
4 103 + 1 103
appearing on the right side. The last but one NAND
gate produces an output equal to (1A) = A. The Also,
last NAND gate inverts this to produce A. VB2 = 5 0.7 I1 4 103
Ans. (d) = 5 0.7 0.72 10 -3 4 103
5. Circuit diagram of a standard TTL NOT gate is = 1.42 V
shown in the figure. When Vi = 2.5 V, the modes Since VB2 > 0.7 V, it implies that the transistor Q2
of operation of the transistor will be operates in saturation region.
VCC = 5 V Since transistor Q2 is in saturation,
VCC 5 5
I2 = = = A = 2.03 mA
R2 + R3 1.4 10 + 1 10
3 3
2.4 103
4 kW 1.4 kW 100 W VCC 5 5
I2 = = = A = 2.03 mA
R2 + R3 1.4 10 + 1 10
Also,
3 3
2.4 103
Q4
VB3 = I3R3 = (2.03 10 -3 ) 1 103 = 2.03 V
+ Q2 D
Q1 Since VB3 > 0.7 V, it implies that Q3 also operates
+ in saturation region.
Q3 Q3 and Q4 together form a totem pole output. Only
Vi Vo one of the transistors will be ON. As Q3 is in satu-
1 kW ration, therefore Q4 will be in cut off.

Ans. (b)
6. Refer to the following figure. Which of the follow-
ing Boolean Expressions correctly represents the
(a) Q1 : reverse active; Q2 : normal active; Q3 : relation between P, Q, R and M1?
saturation; Q4 : cut-off
(b) Q1 : reverse active; Q2 : saturation; Q3 : satura- P
X
tion; Q4 : cut-off
Q
(c) Q1 : normal active; Q2 : cut-off; Q3 : cut-off; Z
Q4 : saturation
M1
(d) Q1 : saturation; Q2 : saturation; Q3 : saturation;
Q4 : normal active Y
Solution. From the given circuit, when Vin is at R
logic HIGH (2V - 5V), base-emitter junction of Q1 (a) M1 = (P OR Q) XOR R
becomes reverse biased and current flows through first (b) M1 = (P AND Q) XOR R
resistor and base-collector junction of Q1 into the base (c) M1 = (P NOR Q) XOR R
of Q2. Hence, Q1 operates in the reverse active region. (d) M1 = (P XOR Q) XOR R
Considering the following figure, we have (GATE 2008: 2 Marks)
+ VCC = 5 V Solution.
I1 (PQ) = (P + Q)
Therefore,
4 kW
M1 = [PQ(P + Q)] R = [(P + Q)(P + Q)] R
0.7 = (P Q) R
Q2 Ans. (d)
Q1 0.7 7. The full forms of the abbreviations TTL and CMOS
in reference to logic families are
VB2
(a) t riple transistor logic and chip metal oxide
1 kW semiconductor
(b) tristate transistor logic and chip metal oxide
semiconductor

(c) transistor transistor logic and complementary state. In the given logic circuit, other than C input,
metal oxide semiconductor the other two inputs cannot be simultaneously in
(d) tristate transistor logic and complementary logic `1 state. Only one of them can be `1 at a
metal oxide semiconductor time. Therefore, C must be in logic `1 state and
Ans. (c) hence the answer.
Ans. (d)
8. Match the logic gates in Column I with their
equivalents in Column II shown in the following table. 10. The output Y in the circuit shown in the follow-
ing figure is always 1 when
Column I Column II
P
P. 1.
Q. 2.
Y
R
R. 3.
(a) two or more of the inputs P, Q, R are 0
(b) two or more of the inputs P, Q, R are 1
S. 4. (c) any odd number of the inputs P, Q, R is 0
(d) any odd number of the inputs P, Q, R is 1
(GATE 2011: 1 Mark)
(a) P-2, Q-4, R-1, S-3 (b) P-4, Q-2, R-1, S-3 Solution. Look at the three NAND gates appearing
(c) P-2, Q-4, R-3, S-1 (d) P-4, Q-2, R-3, S-1 on the extreme left side. First NAND has P and Q
(GATE 2010: 1 Mark) as inputs. Second NAND has Q and R as inputs and
third NAND has R and P as inputs. Output of any
Solution. NOR gate is equivalent to a bubbled of these NAND gates produces logic `1 at the output
AND gate. NAND gate is equivalent to bub- provided that either P = Q = 1 or Q = R = 1 or R
bled OR gate. EX-OR gate is equivalent to a = P = 1 or P = Q = R = 1 and hence the answer.
EX-NOR gate with one input bubbled. EX-NOR Ans. (b)
gate is equivalent to EX-OR gate with one input
11. A bulb in a staircase has two switches, one switch
bubbled.
being at the ground floor and the other one at the
Ans. (d)
first floor. The bulb can be turned ON and also can
9. For the output F to be 1 in the logic circuit shown in be turned OFF by any one of the switches irrespec-
the following figure, the input combination should be tive of the state of the other switch. The logic of
switching of the bulb resembles
A
(a) an AND gate (b) an OR gate
B (c) an XOR gate (d) a NAND gate
(GATE 2013: 1 Mark)
Solution. It is clear from the truth table of an

F EX-OR gate [see Fig. 24.4(b)] that both switches
can be used to either turn ON or turn OFF the
switch. Let us assume that one is at the ground
floor. If the two switches are in different states,
C operating the ground floor switch will put them
(a) A = 1, B = 1, C = 0 (b) A = 1, B = 0, C = 0 in the same state thereby changing the status of
(c) A = 0, B = 1, C = 0 (d) A = 0, B = 0, C = 1 lamp. If the switches are in same state initially,
(GATE 2010: 1 Mark) then operating the switch puts them in different
states again changing the status of lamp. Similar
Solution. For F = 1, even number of inputs to the explanation holds for first floor switch.
EX-NOR gate at the output should be in logic `1 Ans. (c)

CHAPTER 25
COMBINATIONAL CIRCUITS
This chapter discusses various combinational logic circuits including arithmetic circuits, code converters, multiplexers,
demultiplexers, decoders, programmable read only memories (PROMs) and programmable logic arrays (PLAs).
25.1 ARITHMETIC CIRCUITS SUM, S = AB + AB
CARRY, C = AB
In this section, we shall discuss about the combinational
logic circuit devices used to perform arithmetic and Figure 25.1 shows truth table of a half-adder showing all
other related operations. These include adders, subtrac- possible input combinations and the corresponding outputs.
tors, magnitude comparators and look-ahead carry gen-
erators. Particular emphasis is given to the functioning A B S C
and design of these combinational circuits. 0 0 0 0
0 1 1 0
1 0 1 0
25.1.1 Half-Adder 1 1 0 1
A half-adder is an arithmetic circuit block that can be

used to add two bits. Such a circuit thus has two inputs A Half- S
that represent the two bits to be added and two outputs adder
with one producing the SUM output and the other pro- B C
Figure 25.1| Truth table of a half-adder.

ducing the CARRY. The SUM and CARRY outputs are
represented by the following Boolean functions:

572 Chapter 25: Combinational Circuits
A [A (A B)]
(A B)
S
A
S=A B+A B
B B [B (A B)]
C=A B C
(a) (b)
Figure 25.2| (a) Logic implementation of a half-adder. (b) Half-adder implementation using NAND gates.
The simplest way to implement in hardware a half-

A S
adder would be use a two-input EX-OR gate for the Full
SUM output and a two-input AND gate for the CARRY B
adder
output as shown in Fig. 25.2(a). It could also be imple- Cin Cout
mented by using appropriate arrangement of either
NAND or NOR gates. Figure 25.2(b) shows implementa-
tion of half-adder with NAND gates only. A B Cin SUM(S) Cout
0 0 0 0 0
0 0 1 1 0
25.1.2 Full-Adder 0 1 0 1 0
0 1 1 0 1
A full-adder circuit is an arithmetic circuit block that 1 0 0 1 0
can be used to add three bits to produce a SUM and a 1 0 1 0 1
CARRY output. Such a building block becomes a neces- 1 1 0 0 1
1 1 1 1 1
sity when it comes to adding binary numbers with large
number of bits. The full-adder circuit overcomes the limi- Figure 25.3| Truth table of a full-adder.
tation of the half-adder, which can be used to add two
bits only. Let us recall the procedure for adding larger Figure 25.4(a) and (b) show logic circuit diagrams of
binary numbers. We begin with addition of LSBs of the full-adder based on the Boolean expressions for the two
two numbers. We record the sum under the LSB column outputs. A full-adder can also be seen to be comprising
and take the carry, if any, forward to next higher column of two half-adders and an OR gate.
bits. As a result, when we add the bits of the next adja-
Figure 25.5 shows the circuit implementation.
cent higher column bits, we would be required to add
A cascade arrangement of the full-adders described
three bits if there were a carry from the previous addi-
above can be used to construct adders capable of
tion. We have a similar situation for the other higher
adding binary numbers with larger number of bits.
column bits also till we reach the MSB. A full-adder is
For example, a four-bit binary adder would require
therefore essential for the hardware implementation of
four full-adders of the type shown in Fig. 25.5 to be
an adder circuit capable of adding larger binary num-
connected in cascade.
bers. Half-adder can be used for addition of LSBs only.
Figure 25.6 shows such an arrangement. A3A2A1A0
Figure 25.3 shows truth table of a full-adder circuit
and B3B2B1B0 are the two binary numbers to be added
showing all possible input combinations and correspond-
with A0, B0 representing LSBs and A3, B3 representing
ing outputs. The Boolean expressions for the two output
MSBs of the two numbers.
variables are as follows:
SUM, S = ABCin + ABC in + ABC in + ABCin 25.1.3 Half-Subtractor

CARRY, Cout = ABCin + ABCin + ABC in + ABCin
A half-subtractor is a combinational circuit that can be
The expression for SUM (S) output cannot be simplified used to subtract one binary digit from another to produce
any further whereas simplified Boolean expression for C a DIFFERENCE output and a BORROW output. The
is given as follows: BORROW output here specifies whether a 1 has been
Cout = BCin + AB + ACin borrowed to perform the subtraction. The truth table

25.1 ARITHMETIC CIRCUITS 573
A
B
Cin
A A
B S
Cin B
A B
B Cin Cout
Cin
A A
B Cin
Cin
(a) (b)
Figure 25.4| Logic circuit diagram of a full-adder.
of half-subtractor is shown in Fig. 25.7. The Boolean Comparing half-subtractor with half-adder, we find that
expressions for the two outputs are given by following the expressions for SUM and DIFFERENCE outputs
equations. are just the same. The expression for BORROW in case
of half-subtractor is also similar to what we have for
DIFFERENCE, D = AB + AB CARRY in case of half-adder. If the input (A), that is
minuend, is complemented, an AND gate can be used to
BORROW, Bo = AB implement the BORROW output.
It is obvious that there is no further scope for any simpli-
fication of these Boolean expressions. While the expres- A D = A B
sion for the DIFFERENCE (D) output is that of an Half-
EX-OR gate, the expression for BORROW (Bo) output subtractor
B Bo
is that of an AND gate with input (A) complemented
before it is fed to the gate. Figure 25.8 shows the logic
implementation of a half-subtractor. A B D Bo
0 0 0 0
0 1 1 1
Cin Half- S 1 0 1 0
Sum 1 1 0 0
adder
Figure 25.7| Half-subtarctor.
Sum Carry
A Half-
adder Cout
B
Carry
Figure 25.5| Logic implementation of a full-adder with
A
D=AB
half-adder. B
Bo
A3 A2 A1 A0
B3 B2 B1 B0
Figure 25.8| Logic diagram of a half-subtractor.
FA FA FA FA Cin
25.1.4 Full-Subtractor
A full-subtractor performs subtraction operation on two

Cout S3 S2 S1 S0 bits, a minuend and a subtrahend and also takes into
Figure 25.6| Four-bit binary adder.

consideration the practical fact whether a `1 had already
been borrowed by the previous adjacent lower minuend

A Full- D Bin B D D
B subtractor HS
Bin Bo A A D A Bo
HS Bo
B B Bo
Minuend Subtrahend Borrow Difference Borrow Figure 25.10| Logic implementation of a full-subtractor
(A) (B) In (Bin) (D) Out (Bo) with half-subtractors.
0 0 0 0 0 Figure 25.11 shows a cascaded arrangement of four full-
0 0 1 1 1
0 1 0 1 1 subtractors to construct a four-bit binary subtractor.
0 1 1 0 1
1 0 0 1 0 25.1.5 Controlled Inverter
1 0 1 0 0
1 1 0 0 0 Controlled inverter is needed when an adder is to be used
1 1 1 1 1
as a subtractor. As outlined earlier, subtraction is noth-
Figure 25.9| Truth table of a full-subtractor. ing but addition of 2s complement of subtrahend to the
minuend. Thus the first step towards practical implemen-
bit or not. As a result, there are three bits to be handled tation of subtractor is to determine the 2s complement
at the input of a full-subtractor, namely, the two bits to of the subtrahend. And for this, one needs to first find
be subtracted and a borrow bit designated as Bin. There 1s complement. A controlled inverter is used to find 1s
are two outputs, namely, the DIFFERENCE output complement. A 1-bit controlled inverter is nothing but
and the BORROW output. BORROW output bit tells a two-input EX-OR gate with one of its inputs treated
whether the minuend bit needs to borrow a `1 from the as a control input as shown in Fig. 25.12(a). When the
next possible higher minuend bit. Figure 25.9 shows the control input is LOW, the input bit is passed as such to
truth table of full-subtractor. The Boolean expressions the output. (Recall the truth table of an EX-OR gate).
for the two output variables are given as follows. When the control input is HIGH, the input bit gets comple-
mented at the output. Figure 25.12(b) shows an eight-bit
DIFFERENCE, controlled inverter of this type. When the control input
D = ABBin + ABB in + ABB in + ABBin is LOW, the output Y7Y6Y5Y4Y3Y2Y1Y0 is same as the
input A7A6A5A4A3A2A1A0. When control input is HIGH,
BORROW OUT, the output is 1s complement of the input. As an exam-
Bo = ABBin + ABB in + ABBin + ABBin ple, 11010010 at the input would produce 00101101 at the
output when control input is in logic `1 state.
No simplification is possible for the DIFFERENCE
output. The simplified expression for Bo is given by 25.1.6 AdderSubtractor
Boolean function
Subtraction of two binary numbers can be accomplished
Bo = AB + ABin + BBin by adding 2s complement of the subtrahend to the min-
uend and disregarding the final carry, if any. If MSB bit
Figure 25.10 shows the logic implementation of a full- in the result of addition is a `0, then the result of addition
subtractor using half-subtractors. is the correct answer. If the MSB bit is a `1; this implies
A3 A2 A1 A0
B3 B2 B1 B0
FS FS FS FS Bin
D3 D2 D1 D0
Bout
Figure 25.11| Four-bit subtractor.

Control I/P
`1 Output Y = A
Input A
(a)
A7 A6 A5 A4 A3 A2 A1 A0
Control
I/P
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
(b)
Figure 25.12| (a) One-bit and (b) eight bit controlled inverter.
that the answer has a negative sign. The true magnitude four-bit binary representations, that is, 0000, 0001, 0010,
in this case is given by 2s complement of the result of 0011, 0100, 0101, 0110, 0111, 1000 and 1001, equivalent
addition. Full-adders can be used to perform subtraction of decimal numbers 0, 1, ..., 9. When we set ourselves out
provided we have the necessary additional hardware to to add two BCD digits and we assume that there is an
generate 2s complement of the subtrahend and disregard input carry too, the highest binary number that we can
the final carry or overflow. Figure 25.13 shows one such get is the equivalent of decimal number 19 (9 + 9 + 1).
hardware arrangement. Here, we are basically adding 2s This binary number is going to be (10011)2. On the other
complement of B3B2B1B0 to A3A2A1A0. Outputs of full- hand, if we do BCD addition, we would expect the answer
adders in this case give the result of subtraction of the to be (0001 1001)BCD. And if we restrict the output bits
two numbers. The arrangement shown achieves A B. to the minimum required, the answer in BCD would be
The final carry (carry out of MSB full-adder) is ignored (1 1001)BCD. As long as the sum of the two BCD digits
if it is not displayed. remains equal to or less than 9, the four-bit adder pro-
duces the correct BCD output.
The binary sum and the BCD sum in this case are
25.1.7 BCD Adder the same. It is only when the sum is greater than nine
that the two results are different. It can also be seen
A BCD adder is used to perform addition of BCD num- from the table that for decimal sum greater than nine
bers. A BCD digit can have any of the ten possible (or equivalent binary sum greater than 1001), if we add
A3 B3 A2 B2 A1 B1 A0 B0
SUB
A B A B A B A B
FA Cin Cout FA Cin Cout FACin Cout FACin
S S S S
D3 D2 D1 D0
Figure 25.13| Four-bit adder subtractor.

BCD Digit-1 BCD Digit-2
Carry
K Four-bit binary adder
in
Z3 Z2 Z1 Z0
Four-bit binary adder
C
S3 S2 S1 S0
Figure 25.14| Single-digit BCD adder.
0110 to the binary sum, we can get the correct BCD sum BCD adder hardware can be used to perform addition
and the desired carry output too. Figure 25.14 shows the of multiple digit BCD numbers. For example, an n-digit
logic arrangement of a BCD adder capable of adding two BCD adder would require `n such stages in cascade. As
BCD digits with the help of two four-bit binary adders an illustration, Fig. 25.15 shows the block diagram of a
and some additional combinational logic. circuit for the addition of two three-digit BCD numbers.
The first BCD adder labeled least significant digit (LSD)
The BCD adder described in the preceding para- handles the least significant BCD digits. It produces sum
graph can be used to add two single digit BCD num- outputs S3S2S1S0, which is the BCD code for the LSD of
bers only. However, cascade arrangement of single-digit the sum. It also produces an output carry that is fed as
B11B10B9 B8 A11A10A9 A8 B7 B6 B5 B4 A7 A6 A5 A4 B3 B2 B1 B0 A3 A2 A1 A0
Carry BCD BCD BCD

C adder Cin C adder Cin C adder Cin
(MSD) (LSD)
S11S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Figure 25.15| Three-digit BCD adder.

an input carry to the next higher adjacent BCD adder. by successively comparing the next adjacent lower pair
This BCD adder produces sum output S7S6S5S4, which of digits if the digits of the pair under examination are
is the BCD code for the second digit of the sum, and a equal. The comparison continues until a pair of unequal
carry output. This output carry serves an input carry for digits is reached. In the pair of unequal digits, if A = 1,
the BCD adder representing the most significant digits. B = 0, then A > B and if A = 0, B = 1 then A < B. If
The sum outputs S11S10S9S8 represent BCD code for the X, Y and Z are three variables, respectively, representing
MSD of the sum. A = B, A > B and A < B conditions, then the Boolean
expression representing these conditions are given by the
following Boolean functions.
25.1.8 Magnitude Comparator X = x3 x2 x1 x0
Y = A3 B3 + x3 A2 B2 + x3 x2 A1 B1 + x3 x2 x1 A0 B0
Magnitude comparator is a combinational circuit that
compares two given numbers and determines whether Z = A3 B3 + x3 A2 B2 + x3 x2 A1 B1 + x3 x2 x1 A0 B0
one is equal to, less than or greater than the other. The where xi = Ai Bi + Ai Bi
output is in the form of three binary variables represent-
ing the conditions A = B, A > B and A < B, if A and
Figure 25.16 shows logic diagram of four-bit magnitude
comparator.
B were the two numbers being compared. Depending
upon the relative magnitude of the two numbers, rel- Magnitude comparators are available in IC form. For
evant output changes state. If the two numbers, let us example, 7485 is a four-bit magnitude comparator of
say, are four-bit binary numbers and are designated as the TTL logic family. IC 4585 is a similar device in the
A3A2A1A0 and B3B2B1B0, the two numbers will be equal CMOS family. Both 7485 and 4585 have same pin con-
if all pairs of significant digits are equal, that is, A3 = B3, nection diagram and functional table. The logic circuit
A2 = B2, A1 = B1 and A0 = B0. In order to determine inside these devices determines whether one four-bit
whether A is greater than or less than B, we inspect the number, binary or BCD, is less than, equal to or greater
relative magnitude of pairs of significant digits starting than a second four-bit number. Magnitude comparators
from most significant position. The comparison is done available in IC form are designed in such a way that they
A3
B3
A2
B2
(A < B)
O/P
A1
B1
A0 (A > B)
O/P
B0
(A = B)
O/P
Figure 25.16| Four-bit magnitude comparator.

can be connected in a cascade arrangement to perform 25.2.1 Implementing Boolean Functions

comparison operations on numbers of longer lengths. In with Multiplexers
cascade arrangement, A = B, A > B and A < B outputs
of a stage handling less significant bits are connected to One of the most common applications of a multiplexer is
corresponding inputs of the next adjacent stage handling in implementation of combinational logic Boolean func-
more significant bits. Also, the stage handling least sig- tions. The simplest technique to do so is to employ a
nificant bits must have a HIGH level at A = B input. 2n-to-1 MUX to implement an n-variable Boolean func-
The other two cascading inputs (A > B and A < B) may tion. The input lines corresponding to each of the mint-
be connected to LOW level. erms present in the Boolean function are made equal to
logic `1 state. The remaining minterms that are absent
in the Boolean function are disabled by making their cor-
25.2 MULTIPLEXERS responding input lines equal to logic `0. As an example,
Fig. 25.18(a) shows the use of (8-to-1) MUX for imple-
menting the Boolean function given by
A multiplexer (MUX), also called data selector, is a com-
binational circuit with more than one input lines, one F (A, B, C ) = 2, 4, 7
output line and more than one selection lines. There are In terms of variables A, B and C, we have
some multiplexer ICs that provide complementary out-
puts. Also, multiplexers in the integrated circuit form F (A, B, C ) = ABC + ABC + ABC
almost invariably have an ENABLE or STROBE input,
which needs to be active for the multiplexer to be able As shown in Fig. 25.18(a), the input lines correspond-
to perform its intended function. A multiplexer selects ing to the three minterms present in the given Boolean
binary information present on any one of the input lines, function are tied to logic `1. Remaining five possible
depending upon the logic status of selection inputs, and minterms absent in the given in the Boolean function
routes it to the output line. If there are n selection lines, are tied to logic `0. However, there is a better technique
then the number of maximum possible input lines is 2n available to do the same. In this, a 2n-to-1 MUX can
and the multiplexer is referred to as 2n-to-1 multiplexer be used to implement a Boolean function with n + 1
or 2n 1 multiplexer. Figures 25.17(a) and (b), respec- variables. The procedure is as follows. Out of n + 1 vari-
tively, show the circuit representation and truth table of ables, n are connected to the n selection lines of 2n-to-1
the basic 4-to-1 multiplexer. multiplexer. The left over variable is used with the input
When the ENABLE input is active, that is, when it is lines. Various input lines are tied to one of the following,
in logic `1 or logic `0 state depending upon whether which includes `0, `1, left-over variable and complement
ENABLE input is active HIGH or active LOW, respec- of left-over variable. Logic status of different input lines
tively, the output is enabled. The multiplexer functions can be determined with the help of a simple procedure.
normally. When ENABLE input is inactive, the output The complete procedure is illustrated for the above men-
is disabled and permanently goes to either logic `0 or tioned Boolean function.
logic `1 state depending upon whether the output is It is a three-variable Boolean function. Conventionally,
uncomplemented or complemented. we shall need to use an 8-to-1 multiplexer to implement
I0 0
I1 1
4-to-1 O/P Y
I2 2 MUX X1 X0 Y
0 0 I0
I3 3 X1 X0 0 1 I1
1 0 I2
1 1 I3
(a) (b)
Figure 25.17| (a) Circuit representation and (b) truth table of a 4-to-1 multiplexer.

25.2 MULTIPLEXERS 579
`1
I0
I1
I2 I0
I3 8-to-1 F `0 I1 4-to-1
I4 MUX F
A I2 MUX
I5
I3
I6 S1 S0
I7 ABC
B C
(a) (b)
Figure 25.18| Hardware implementation of the Boolean function F(A, B, C) = 2, 4, 7.
Table 25.1| Truth table. Table 25.2| Implementation table for multiplexers.
Minterm A B C F(A, B, C) I0 I1 I2 I3
0 0 0 0 0 A 0 1 2 3
1 0 0 1 0
A 4 5 6 7
2 0 1 0 1
3 0 1 1 0 A 0 A A
4 1 0 0 1
5 1 0 1 0 highlighted, a `1 is written. If only one is highlighted,
the corresponding variable (complemented or uncomple-
6 1 1 0 0
mented) is written. The input lines are then given appro-
7 1 1 1 1 priate logic status. In the present case, I0, I1, I2 and I3
would be connected to A , 0, A and A, respectively.
Figure 25.18(b) shows the logic implementation.
this function. We shall now see how this can be imple-
mented with a 4-to-1 multiplexer. The chosen multi- It is not necessary to choose only the left most variable
plexer has two selection lines. The first step here is to in the sequence to be used as input to the multiplexer.
determine the truth table of the given Boolean function, Any of the variables can be used provided the implemen-
which is shown in Table 25.1. tation table is constructed accordingly. In the problem
illustrated above, À was chosen as the variable for the
In the next step, two of the three variables are connected input lines and accordingly, the first row of the imple-
to the two selection lines with higher order variable con- mentation table contained those entries where À was
nected to higher order selection line. For instance, in the complemented and second row contained entries where
present case, variable B and C are the chosen variables À was uncomplemented. If we consider `C as the left
for the selection lines and are, respectively, connected to out variable, the implementation table will be as shown
selection lines S1 and S0. In the third step, construct a in Table 25.3.
truth table of the type shown in Table 25.2. Under the
inputs to the multiplexer, minterms are listed in two Table 25.3| Implementation table for multiplexers.
rows as shown. The first row lists those terms where
remaining variable A is complemented and second row I0 I1 I2 I3
lists those terms where A is uncomplemented. This is
C 0 2 4 6
easily done with the help of truth table.
The required minterms are identified or marked in some C 1 3 5 7
manner in this table. In the given table, these entries
have been highlighted. Each column is inspected indi- 0 C C C
vidually. If both the minterms of a certain column are
not highlighted, a `0 is written below that. If both are Figure 25.19 shows hardware implementation.

to construct 16-to-1 or 32-to-1 or even larger multiplexer

`0 I0 circuits. The basic steps to be followed to carry out the
I1 4-to-1 design are as follows.
F
I2 MUX 1. If 2n is the number of input lines in the available
I3 multiplexer and 2N is the number of input lines in
S1 S0
C the desired multiplexer, then number of individual
multiplexers required to construct the desired mul-
A B
tiplexer circuit would be 2Nn.
Figure 25.19| Hardware implementation using a 4-to-1 2. From the knowledge of number of selection inputs
multiplexer. of the available multiplexer and that of the desired
multiplexer, connect the less significant bits of the
selection inputs of desired multiplexer to the selec-
25.2.2 Multiplexers for Parallel-to-Serial
tion inputs of the available multiplexer.
Data Conversion 3. The left-over bits of the selection inputs of desired
multiplexer circuit are used to enable or disable the
Though the data is processed in parallel in many digital
individual multiplexers so that their outputs when
systems to achieve faster processing speeds; but, when it
ORed produce the final output. The procedure is
comes to transmitting this data to relatively large dis-
illustrated with the help of an example explaining
tances, it is done so serially. The parallel arrangement in
how two 8-to-1 multiplexers can be used to con-
this case is highly undesirable as it would require a large
struct a 16-to-1 multiplexer.
number of transmission lines. Multiplexer can possibly
be used for parallel-to-serial conversion. Figure 25.20
shows one such arrangement where an 8-to-1 multiplexer D0 I0
is used to convert eight-bit parallel binary data to serial D1 I1
form. A three-bit counter controls the selection inputs. D2
As the counter goes through 000 to 111, the multiplexer D3 8-to-1
D4
output goes through X0 to X7. The conversion process D5 MUX
takes a total of eight clock cycles. The three-bit counter D6
has been constructed with the help of three toggle flip D7 I7 Y
flops (FFs) as shown in Fig. 25.20. A large variety of S3 E
counters is available in IC form. S2 S2
S1 S1
I0 S0
S0
I1
I2 D8 I0
I3 D9 I1
Parallel I4 D10
I5 8-to-1 Serial D11
inputs Y
I6 MUX output D12 8-to-1
I7 D13 MUX
D14
D15 I7 Y
S2 S1 S0
E
S2
C A Clock S1
FF2 T FF1 T FF0 T
input
C A S0
Figure 25.20| Multiplexer for parallel-to-serial Figure 25.21| Complete logic circuit diagram of
conversion. 16-to-1 multiplexer.
25.2.3 Cascading Multiplexer Circuits A 16-to-1 multiplexer can be constructed from two 8-to-1
multiplexers having an ENABLE input. The ENABLE
Multiple devices of a given size can be used to construct input is taken as the fourth selection variable occupying
multiplexers that can handle larger number of input the MSB position Figure 25.21 shows the complete logic
channels. For instance, 8-to-1 multiplexers can be used circuit diagram. The circuit functions as follows. When

25.2 MULTIPLEXERS 581
S3 is in logic `0 state, upper multiplexer is enabled and are in logic `0 state. This can be overcome by having an
the lower multiplexer is disabled. If we recall the truth additional line to indicate an all 0s input sequence.
table of a four-variable Boolean function, S3 would be
`0 for the first eight entries and `1 for the remaining Table 25.4| Truth table of an encoder.
eight entries. Therefore, when S3 = 0 the final output
will be any of the inputs from D0 to D7 depending upon D0 D1 D2 D3 D4 D5 D6 D7 A B C
the logic status of S2, S1 and S0. Similarly, when S3 = 1, 1 0 0 0 0 0 0 0 0 0 0
the final output will be any of the inputs from D8 to
D15 again depending upon the logic status of S2, S1 and 0 1 0 0 0 0 0 0 0 0 1
S0. The circuit therefore implements the truth table of a 0 0 1 0 0 0 0 0 0 1 0
16-to-1 multiplexer. 0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
25.2.4 Encoders 0 0 0 0 0 1 0 0 1 0 1
An encoder is a multiplexer without its single output 0 0 0 0 0 0 1 0 1 1 0
line. It is a combinational logic function that has 2n (or 0 0 0 0 0 0 0 1 1 1 1
less) input lines and n output lines, which correspond
to n selection lines in a multiplexer. The n-output lines
generate the binary code for the possible 2n-input lines. 25.2.5 Priority Encoder
Let us take the case of an octal-to-binary encoder. Such
an encoder would have eight input lines, each represent- A priority encoder is a practical form of an encoder. The
ing an octal digit and three output lines representing encoders available in the IC form are all priority encod-
the three-bit binary equivalent. The eight input lines ers. In this type of encoder, a priority is assigned to each
would have 28 = 256 possible combinations. However, input so that when more than one input is simultane-
in case of an octal-to-binary encoder, only eight of these ously active, the input with highest priority is encoded.
256 combinations would have any meaning. Remaining We shall illustrate the concept of priority encoding with
combinations of input variables are `dont care input the help of an example. Let us assume that the octal-to-
combinations. Also, only one of the input lines at a time binary encoder described in the previous paragraph has an
is in logic `1 state. Figure 25.22 shows hardware imple- input priority for higher order digits. Let us also assume
mentation of octal-to-binary encoder described by truth that input lines D2, D4 and D7 are all simultaneously
table (Table 25.4). This circuit has a shortcoming that it in logic `1 state. In that case, only D7 will be encoded
produces an all 0s output sequence when all input lines and the output will be 111. The truth table of such a
D0 D1 D2 D3 D4 D5 D6 D7
Figure 25.22| Octal-to-binary encoder.

priority encoder will then get modified to what is shown in A decoder, as mentioned earlier, is a combinational cir-
Table 25.5. Looking at the last row of the table, it implies cuit that decodes the information on n input lines to a
that if D7 = 1, then irrespective of the logic status of other maximum of 2n unique output lines. Figure 25.24 shows
inputs, output is 111 as D7 will only be encoded. circuit representation of 2-to-4, 3-to-8 and 4-to-16 line
Table 25.5| Priority encoder.

decoders. In case there are some unused or `dont care
combinations in the n-bit code, then there will be less
than 2n output lines. As an illustration, if there are
D0 D1 D2 D3 D4 D5 D6 D7 A B C three input lines, it can have a maximum of eight unique
1 0 0 0 0 0 0 0 0 0 0 output lines. In case, in the three-bit input code, the
1 0 0 0 0 0 0 0 0 1 only used three-bit combinations are 000, 001, 010, 100,
110 and 111 (011 and 101 being either unused or `dont
1 0 0 0 0 0 0 1 0
care combinations), then this decoder will have only
1 0 0 0 0 0 1 1 six output lines. In general, if n and m, respectively,
1 0 0 0 1 0 0 are numbers of input and output lines, then m 2n. A
decoder can generate a maximum of 2n possible mint-
1 0 0 1 0 1
erms with an n-bit binary code.
1 0 1 1 0
1 1 1 1 A 0 A 0
1
2-to-4 1 B 3-to-8
2
25.3 DEMULTIPLEXERS AND B 3 C 7
DECODERS
A 0
A demultiplexer is a combinational logic circuit with an B 1
4-to-16
input line, 2n output lines and n select lines. It routes C
the information present on the input line to any of the D 15
output lines. The output line that gets the information
Figure 25.24| Circuit representation of 2-to-4, 3-to-8
present on the input line is decided by the bit status of
the selection lines. A decoder is a special case of demul-
and 4-to-16 line decoders.
tiplexer without the input line. Figure 25.23(a) shows
the circuit representation of a 1-to-4 demultiplexer.
Figure 25.23(b) shows the truth table of the demulti- 25.3.1 Implementing Boolean Functions
plexer when the input line is held HIGH. with Decoders
D0 A decoder can be conveniently used to implement a

I/P line 1-to-4 D1 given Boolean function. The decoder generates the
DEMUX D2 required minterms and an external OR gate is used to
D3 produce sum of minterms. Figure 25.25 shows the logic
diagram where a 3-to-8 line decoder is used to generate
the Boolean function given by
A B Y = ABC + ABC + ABC + ABC
(a)
0
Select O/P 1
I/P
A 22 2
A B D0 D1 D2 D3 3-to-8 3
B 21 Decoder 4 Y
1 0 0 1 0 0 0
1 0 1 0 1 0 0 5
1 1 0 0 0 1 0
C 20 6
7
1 1 1 0 0 0 1
Figure 25.25| Implementing Boolean functions with
(b) decoders.
Figure 25.23| (a) Circuit representation and (b) truth In general, an n-to-2n decoder and m external OR gates
table of a 1-to-4 demultiplexer. can be used to implement any combinational circuit

25.4PROGRAMMABLE LOGIC DEVICES 583
with n inputs and m outputs. We can appreciate that eight combinations have D = 0 with CBA going through
a Boolean function with a large number of minterms, if 000 to 111. The higher order eight combinations have
implemented with a decoder and an external OR gate, all D = 1 with CBA going through 000 to 111. If we use
would require an OR gate also with equally large number D-bit as the ENABLE input for less significant 3-to-8
of inputs. Let us consider the case of implementing a line decoder and D -bit as the ENABLE input for more
four-variable Boolean function with 12 minterms using a significant 3-to-8 line decoder, less significant 3-to-8 line
4-to-16 line decoder and an external OR gate. The OR decoder shall be enabled for the less significant eight of
gate here needs to be a 12-input gate. In all such cases, the 16 input combinations and more significant 3-to-8
where number of minterms in a given Boolean function decoder shall be enabled for the more significant of the
with (n) variables is greater than 2n/2 (or 2n1), the 16 input combinations. Figure 25.26 shows the hardware
complement Boolean function will have fewer minterms. implementation. One of the output lines D0 to D15 is
In that case, it would be a better idea to do NOR opera- activated as the input bit sequence DCBA goes through
tion of minterms of complement Boolean function using 0000 to 1111.
a NOR gate rather than doing OR operation of given
function using an OR gate. The output will be nothing
but the given Boolean function. D0
D1
C 22
D2
25.3.2 Cascading Decoder Circuits B 21 3-to-8 D3
Decoder D4
There can possibly be a situation where the desired A 20 D5
number of input and output lines is not available in IC D E D6
decoders. More than one of these devices of a given size D7
may be used to construct decoder that can handle larger
number of input and output lines. For instance, 3-to-8
line decoders can be used to construct 4-to-16 or 5-to-32
or even larger decoder circuits. The basic steps to be fol-
lowed to carry out the design are as follows. D8
1. If n is the number of input lines in the available D9
22
decoder and N is the number of input lines in the D10
desired decoder, then number of individual decod- 21 3-to-8 D11
Decoder D12
ers required to construct the desired decoder circuit 20
would be 2Nn. D13
2. From the knowledge of number of selection inputs E D14
of the available decoder and that of the desired D15
Figure 25.26| Hardware implementation 4-to-16

decoder, connect the less significant bits of the
input lines of desired multiplexer to the input lines
decoder.
of the available multiplexer.
3. The left-over bits of the input lines of desired
decoder circuit are used to enable or disable the
25.4 PROGRAMMABLE LOGIC
individual decoders.
4. The output lines of individual decoders together DEVICES
constitute the output lines with outputs of less sig-
nificant decoder constituting less significant output
In the following paragraphs are discussed a new cate-
lines and those of higher order decoders consti-
gory of logic devices called programmable logic devices
tuting more significant output lines. The concept
(PLD). Function to be performed by a programmable
is further illustrated in the following example,
logic device is undefined at the time of its manufacture.
which gives design of 4-to-16 decoder using 3-to-8
These devices are programmed by the user to perform a
decoders.
range of functions depending upon the logic capacity and
Let us assume that A(LSB), B, C and D (MSB) are the other features offered by the device. We shall begin with
input variables for a 4-to-16 line decoder. Following the a comparison of fixed and programmable logic and then
steps outlined earlier, A(LSB), B and C (MSB) shall then follow it up with detailed description of different types of
be the input variables for the two 3-to-8 line decoders. If PLDs with particular emphasis on programmable logic
we recall the 16 possible input combinations from 0000 arrays (PLAs) and programmable read only memories
to 1111 in case of 4-to-16 line decoder, we find that first (PROMs).

25.4.1 Fixed Logic Versus Programmable Logic and B are the two bits to be added and C is the carry-in
bit. It is a fixed logic device as the circuit is unalterable
There are two broad categories of logic devices, namely, from outside due to fixed interconnections between vari-
fixed logic devices and programmable logic devices. ous building blocks.
While a fixed logic device such as logic gate or multi-
plexer or flipflop perform given logic function that is
known at the time of device manufacture; a program- A
B
mable logic device on the other hand can be configured C
by the user to perform a large variety of logic functions.
A
In terms of internal schematic arrangement of two types B
of devices, the circuits or building blocks and their inter- C
connections in a fixed logic device are permanent and Y
A
cannot be altered after the device is manufactured. B
Programmable logic device offers to the user a wide C
range of logic capacity in terms of digital building blocks, A
which can be configured by the user to perform the B
intended function or set of functions. This configuration C
can be modified or altered any number of times by the Figure 25.27| Fixed logic circuit.
user by reprogramming the device. Figure 25.27 shows a
simple logic circuit comprising of four three-input AND
gates and a four-input OR gate. This circuit produces an Figure 25.28 shows the logic diagram of a simple
output that is the sum output of a full-adder. Here, A programmable device. The device has an array of four
+V
A
B
C
+V
+V
Y
+V
Figure 25.28| Simple programmable logic circuit.

six-input AND gates at the input and a four-input interconnection is a `make connection where as in case
OR gate at the output. Each AND gate can handle of an anti-fuse; it is a `break connection.
three variables and thus can produce a product term Once a given pattern is formed, it remains as such
of three variables. The three variables (A, B and C in even if power is turned off and on. In case of PROMs,
this case) or their complements can be programmed user can erase the data already stored on the ROM
to appear at the inputs of any of the four AND gates chip and load it with fresh data. Memory related
through fusible links called anti-fuse. This means that issues of ROMs are discussed in detail in Chapter 28.
each AND gate can produce the desired three-vari- In this section, we shall discuss use of PROMs as
able product term. It may be mentioned here that an a programmable logic device for implementation of
anti-fuse performs a function that is opposite to that combinational logic functions, which is one of the most
performed by a conventional electrical fuse. A fuse widely exploited applications of PROMs. A PROM in
has a low initial resistance and permanently breaks general has n input lines and m output lines and is
an electrically conducting path when current through designated as 2n m ROM. Looking at the inter-
it exceeds a certain limiting value. In case of anti- nal architecture of a PROM device, it is a combina-
fuse, initial resistance is very high and it is designed tional circuit with the AND gates wired as a decoder
to create a low resistance electrically conducting path and having OR gates equal to number of outputs.
when voltage across it exceeds a certain level. As a A PROM with five input lines and four output lines, for
result, this circuit can be programmed to generate instance, would have an equivalent of 5 32 decoder
any three-variable sum-of-products Boolean function at the input that would generate 32 possible minterms
having four minterms by activating desired fusible or product terms. Each of these four OR gates would
links. For example, the circuit could be programmed be a 32-input gate fed from 32 outputs of the decoder
to produce the sum output resulting from addition of through fusible links.
three bits (sum output in case of a full-adder) or to
produce difference output resulting from subtraction Figure 25.30 shows the internal architecture of 32 4
of two bits with a borrow-in (difference output in case PROM. We can see that input side is hardwired to
of a full-subtractor). produce all possible 32 product terms corresponding
to five variables. All 32 product terms or minterms
We can visualize that the logic circuit of Fig. 25.28 are available at the inputs of each of the OR gates
has a programmable AND array at the input and a fixed through programmable interconnections. This allows
OR gate at the output. Incidentally, this is the architec- the user to have four different five-variable Boolean
ture of programmable logic devices called programmable functions of his choice. Very complex combinational
array logic (PAL). Practical PAL devices have much functions can be generated with PROMs by suitably
larger number of programmable AND gates and fixed making or breaking these links.
OR gates to have enhanced logic capacity and perfor-
mance capability. PAL devices are discussed in the latter To sum up, for implementing an n-input or variable,
part of this chapter. m-output combinational circuit, one would need a 2n m
PROM. As an illustration, let us see how PROM can be
used to implement the following Boolean function with
25.4.2 Programmable ROMs two outputs.
A read only memory (ROM) is essentially a memory F1 (A, B, C) = 0, 2

device that can be used to store a certain fixed set of
binary information. These devices have certain inher- F2 (A, B, C) = 1, 4, 7
ent links, which can be made or broken depending upon
type of fusible link to store any user specified binary Implementation of these Boolean functions would
information in the device. While in case of a conven- require an 8 2 PROM. The internal logic diagram
tional fusible link, relevant interconnections are broken of PROM in this case after it is programmed would be
to program the device; in case of anti-fuse, relevant as shown in Fig. 25.31. It may be mentioned here that
interconnections are made to do the same job. This is in practice, PROM would not be used to implement as
illustrated in Fig. 25.29. Figure 25.29(a) shows the inter- simple a Boolean function as illustrated above. The pur-
nal logic diagram of 4 2 PROM. The figure shows an pose here was to tell the readers how a PROM imple-
unprogrammed PROM. Figures 25.29(b) and (c), respec- ments a Boolean function. In actual practice, PROMs
tively, show use of fuse and anti-fuse to produce output would be used only in case of very complex Boolean
1 = AB. Note that in case of a fuse, an unprogrammed functions.

A B A B
Output-1 Output-2 Output-1 Output-2

(a) (b)
A B
Output-1 Output-2
(c)
Figure 25.29| Use of fuse and anti-fuse.
Another noteworthy point is that when it comes to However, unlike PROM, the PLA does not provide full
implementing Boolean functions with PROMs, it is not decoding of the input variables and does not generate
economical to use ROM for those Boolean functions which all possible minterms as is the case in a PROM. While
have a large number of `dont care conditions. In case of a PROM has a fixed AND gate array at the input and
a PROM, each `dont care condition would have either all a programmable OR gate array at the output; a PLA
0s or all 1s. In other words, the space on the chip is not device has a programmable AND gate array at the input
optimally utilized. Other programmable logic devices like and a programmable OR gate array at the output. In
PLA or PAL are more suitable in such situations. a PLA device, each of the product terms of the given
Boolean function is generated by an AND gate which
can be programmed to form the AND of any subset
25.4.3 Programmable Logic Array of inputs or their complements. The product terms so
produced can be summed up in an array of program-
A programmable logic array (PLA) enables logic func- mable OR gates. Thus, we have a programmable OR
tions expressed in sum-of-products form to be imple- gate array at the output. The input and output gates
mented directly. It is similar in concept to a PROM. are constructed in the form of arrays with input lines

A B C D E Programmable A B C
OR-array
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
F1 F2
22
23 Figure 25.31| 8 2 PROM internal logic diagram to
24 implement given Boolean functions.
25
26 gates at the output can generate four different Boolean
27 functions, each having a maximum of eight minterms
28 out of 16 minterms possible with four variables. The
29 logic diagram depicts the unprogrammed state of the
device. PLAs usually have inverters at the output of OR
30
gates to enable PLAs implement a given Boolean func-
31 tion in either AND-OR and AND-OR-INVERT form.
Figure 25.33 shows a generalized block schematic repre-
sentation of a PLA device having n inputs, m outputs
Y1 Y2 Y3 Y4 and k product terms with n, m and k, respectively, rep-
resenting number of input variables, number of OR gates
Figure 25.30|Internal architecture of a 32 4 PROM. and number of AND gates. The number of inputs to each
OR gate and each AND gate are k and 2n, respectively.
orthogonal to product lines and the product lines being A PLA is specified in terms of number of inputs,
orthogonal to output lines. number of product terms and number of outputs. As is
clear from the description given in the preceding para-
Figure 25.32 shows internal architecture of a PLA
graph, the PLA would have a total of 2Kn + Km pro-
device with four input lines, eight product lines and four
grammable interconnections. A ROM with same number
output lines. That is, programmable AND gate array has
of input and output lines would have 2n m program-
eight AND gates. Each of the AND gates here has eight
mable interconnections.
inputs, four corresponding to four-input variables and
their complements. Input to each of the AND gates can PLA could be either mask programmable or field pro-
be programmed to be any of the possible 16 combinations grammable. In case of a mask programmable PLA, the
of four-input variables and their complements. Four OR customer submits a program table to the manufacturer

A B C D
Programmable OR-array
Y1 Y2 Y3 Y4
Figure 25.32| Internal architecture of a PLA device.
(k) (m)
AND-Gates OR-Gates
(Product terms) (Sum terms)
Figure 25.33| Generalized representation of PLA architecture.
to produce a custom made PLA having desired inter- 25.4.4 Programmable Array Logic
nal paths between inputs and outputs. A field program-
mable logic array (FPLA) is programmed by the user Programmable array logic (PAL) device is a variant of
himself by using a hardware programmer unit available PLA device. It has a programmable AND gate array
commercially. at the input and a fixed OR gate array at the output.
While implementing a given Boolean function with a The idea to have a fixed OR-array at the output and
PLA, it is important that each expression is simplified make the device less complex originated from the fact
to a minimum number of product terms which would that there were many applications where product term
minimize number of AND gates required for the purpose. sharing capability of the PLA was not fully utilized and
Since all input variables are available to different AND thus wasted. PAL device is a trade mark of Advanced
gates, simplification of Boolean functions to reduce the Micro Devices, Inc. PAL devices are however less flex-
number of literals in various product terms is not impor- ible than PLA devices. The flexibility of a PAL device
tant. In fact, each of the Boolean functions and their can be enhanced by having different output logic con-
complements should be simplified. What is desirable is figurations including availability of both OR (also
to have fewer product terms and product terms that are called active HIGH) and NOR (also called active LOW)
common to other functions. We would recall that PLAs outputs, bidirectional pins that can act both as inputs
offer the flexibility of implementing Boolean functions in as well as outputs, having clocked flipflops at the
both AND-OR and AND-OR-INVERT forms. outputs to provide what is called registered outputs.

Inputs
Hard-wired
Product OR-array
terms
Programmable
AND-array
Figure 25.34| Generalized PAL device.
These features allow the device to be used in a wide Another number following the alphabet indicates number
range of applications than would be possible with a of outputs. In case of PAL devices offering a combina-
device with fixed input and output allocations. Mask tion of different types of logic outputs, the rightmost
programmed version of PAL is known as a hard number indicates the number of output type implied by
array logic (HAL) device. A HAL device is pin to pin the alphabet used in the designation. For example, a
compatible to its PAL counterpart. PAL device designated PAL-16L8 shall have 16 inputs
Figure 25.34 shows the block schematic representa- and eight active LOW outputs. Another PAL device
tion of generalized architecture of a PAL device. As we designated PAL-16R4 has 16 inputs and four registered
can see from the arrangement shown, the device has a outputs. Also, number of inputs as given by the number
programmable AND gate array that is fed with various designation includes dedicated inputs, user program-
input variables and their complements. Programmable mable inputs accessible from combinational I/O pins
input connections allow any of the input variables their and any feedback inputs from combinational and regis-
complements to appear at the inputs of any of the AND tered outputs. For example, PAL-16L8 has 10 dedicated
gates in the array. Each of the AND gates generates a inputs and six inputs accessible from I/O pins.
minterm of user defined combination of input variables In addition to the numbering system described above,
and their complements. As an illustration, Figure 25.35 an alphanumeric designation on the extreme left may
gives an example of generation of minterms. be used to indicate the technology used. `C stands for
Outputs from programmable AND array feed an CMOS, `10H for 10KH ECL and `100 for 100K ECL.
array of hard wired OR gates. Here, output of each of TTL is represented by a blank. An alphabet on the
the AND gates does not feed the input of each of the extreme right may be used to indicate power level with
OR gates. Each OR gate is fed from a subset of AND `L and `Q, respectively, indicating low and quarter
gates in the array. This implies that the sum-of-product power levels and blank representing full power.
Boolean functions generated by each of the OR gates
at the output shall have only a restricted number of B C D
minterms depending upon the number of AND gates it
is being fed from. Outputs from the PAL device, as is
clear from the generalized form of representation shown
in Fig. 25.34, are available both as OR outputs as well
as complemented (or NOR) outputs. Logic `0
Standard PAL numbering system uses an alphanu-
meric designation comprising of a two-digit number
indicating number of inputs followed by an alphabet
that tells about the architecture/type of logic output. Figure 25.35|Programmability of inputs in a PAL device.

IMPORTANT FORMULAS
1. Half-adder: SUM, S = AB + AB and CARRY, X = x3 x2 x1 x0

C=AB
Y = A3 B3 + x3 A2 B2 + x3 x2 A1 B1
2. Full-adder: SUM, S = ABCin + ABC in + ABC in +
ABCin and CARRY, Cout = BCin + AB + ACin + x3 x2 x1 A0 B0
3. Half-subtractor: DIFFERENCE, D = AB + AB
and BORROW, Bo = AB Z = A3 B3 + x3 A2 B2 + x3 x2 A1 B1
4. Full-subtractor: DIFFERENCE, D = ABBin + ABB in + + x3 x2 x1 A0 B0
D = ABBin + ABB in + ABB in + ABBin and BORROW, Bo = AB + ABin
B = AB + AB +BB where xi = Ai Bi + Ai Bi .
o in in
5. Four-bit magnitude comparator: If the two 6. Multiplexer with n data inputs, one output and m
four-bit numbers are represented by A3A2A1A0 and control inputs: n = 2m.
B3B2B1B0, then the conditions X(A = B), Y(A > B)
and Z(A < B) are given by the following Boolean
7. Demultiplexer with one input, n outputs and m
control inputs: n = 2m.
functions.
SOLVED EXAMPLES
1. The logic diagram shown in the following figure (a) SUM output
performs the function of a very common arithmetic (b) DIFFERENCE output

building block. Identify the logic function. (c) either SUM or DIFFERENCE output
A (d) CARRY output of a half-adder
B Solution. Both SUM and DIFFERENCE outputs
X are expressed by the Boolean function AB + AB.
Ans. (c)
3. Two binary digits are applied to the inputs of a two-
Y input AND gate. The output of the logic can generate
(a) Half-adder (b) Full-adder (a) BORROW OUT of a half-subtractor

(c) Half-subtractor (d) Multiplier (b) CARRY OUT of a half-adder

(c) SUM output of a half-adder
Solution. Writing Boolean expressions for X and (d) DIFFERENCE output of a half-adder
Y, we get
Solution. CARRY OUT of a half-adder is given
X = AB AB = AB + AB = AB + AB by A B, which is the Boolean function of an AND
gate.
Y = A + B = AB
Ans. (b)
The a ove Boolean functions, X and Y, are those of
a half-adder. X and Y represent SUM and CARRY 4. Identify the logic circuit shown in the following
outputs, respectively. figure. IC 7483 is a four-bit binary adder.
Ans. (a)
(a) Four-bit adder subtractor
2. Two binary digits are applied to the inputs of a (b) Four-bit adder
two-input Exclusive-OR gate. The output of the
(c) Four-bit subtractor
logic gate can generate (d) None of these

SOLVED EXAMPLES 591
A3 A2 A1 A0 B3 B2 B1 B0 Control A
Input B
`0 or `1 X
1 2 4 5 9 10 12 13
Y
7486
3 6 8 11 Solution. The circuit is half-subtractor if A and B
1 3 8 10 16 4 7 11 are the bits to be subtracted, X is the DIFFERENCE
output and Y is the BORROW OUT. This can be
proved by writing Boolean functions for X and Y.
Boolean functions for X and Y are determined to be
7483 13
Y = AB + AB and X = AB
Ans. (c)
15 2 6 9 7. A decoder is nothing but a demultiplexer without
(a) control inputs (b) data input
(c) enable input (d) None of these
Solution. In the case of a decoder, the n-bit data
at the control inputs is converted to a maximum of
S3 S2 S1 S0 2n unique output lines.
Ans. (b)
Solution. The logic circuit shown is that of a four-
8. Identify the product-of-sums Boolean function rep-
bit binary adder in combination with a four-bit
resented by logic diagram shown in the following
controlled inverter constituted by Exclusive-OR
figure.
gates of IC 7486. When the control input is logic
`0, the B-input is passed on to the 7483 input as `1
such. In that case, the logic circuit functions like a
four-bit adder. When the control input is logic `1, I0
the B-input is inverted before it gets to the input of `0 I1 4-to-1
7483. In that case, the output is A B, that is, the I2 MUX Y F
C
circuit behaves like a four-bit subtractor. I3
Ans. (a) S1 S0
5. Number of half- and full-adders required to con- B

struct a 64-bit binary adder would be A

(a) F (A, B, C ) = 1, 2, 5
(a) one half-adder and 63 full-adders
(b) 64 full-adders

(c) 64 half-adders (b) F (A, B, C ) = 0, 3, 4, 6, 7
(d) one full-adder and 63 half-adders (c) F (A, B, C ) = 0, 3, 4, 6

Solution. The least significant bit requires adding (d) F (A, B, C ) = 0, 3, 4, 6, 7

only two bits while the addition at more signifi-
cant positions has to deal with CARRY IN also. Solution. The implementation table can be drawn
Therefore, a half-adder would suffice at the least from the given logic diagram as shown in the fol-
significant bit position while full-adders would be lowing implementation table:
required at other bit positions.
Ans. (a) I0 I1 I2 I3
6. The following figure displays some arithmetic circuit C 0 1 2 3

building block. Identify the circuit. C 4 5 6 7
(a) Half-adder (b) Adder-subtractor 1 0 C 1
(c) Half-subtractor (d) Magnitude comparator


The sum-of-products Boolean function can be writ- (a) 1-to-16 demultiplexer
ten from an examination of implementation table as (b) 16-to-1 multiplexer

F (A, B, C ) = 0, 3, 4, 6, 7
(c) Dual 8-to-1 multiplexer
(d) Dual 1-to-8 demultiplexer
The equivalent product-of-sums Boolean function
can therefore be written as Solution. In the circuit shown in the figure, D0 to
D15 are the 16 input lines; S0 to S3 are the selection
F (A, B, C ) = 1, 2, 5 lines and F is the output. For inputs 0000 to 0111;
Ans. (a) S3 is LOW enabling the upper MUX and disabling
9. Identify the logic circuit shown in the following the lower MUX. As a result, D0 to D7 appear at
figure. the output as per the status of S0 to S3. For inputs
1000 to 1111; S3 is HIGH thereby enabling the
D0 I0
D1 I1 lower MUX and disabling the upper MUX. As a
D2 result, the output is D8 to D15 in accordance with
D3 logic status at S0 to S3.
D4 8-to-1
MUX Ans. (b)
D5
D6 10. The following figure shown below depicts the
D7 I7 Y1 logic diagram and truth table of a 10-line deci-
S3 E mal to 4-line BCD priority encoder. Which
S2 decimal digit or digits in this have priority
S2 encoding?
S1 S1
S0
S0 (a) 0 has priority encoding
F (b) has priority encoding
D8 I0
(c) 0 and 9 have priority encoding
D9 I1 (d) Higher order digits have priority encoding
D10
D11
D12 8-to-1 Solution. The encoder has active LOW inputs
D13 MUX and outputs. A close examination of truth table
D14 reveals that the highest decimal digit input line
D15 I7 Y2 that is active (LOW in this case) is encoded. For
E example, when input line 9 is active, then irrespec-
tive of logic status of other input lines, the output
S2 is BCD equivalent of 9.
S1 Ans. (d)
S0
Inputs Outputs
0 1 2 3 4 5 6 7 8 9 D C B A
0 0 1 1 0
0 1 0 1 1 1
0 0 1 1 1 0 0 0
1 0 1 1 1 1 0 0 1
2 10 - Line 0 1 1 1 1 0 1 0
A 1
3 Decimal
4 B 0 1 1 1 1 1 1 0 1 1
5 to BCD 0 1 1 1 1 1 1 1 1 0 0
C
6 Priority 0 1 1 1 1 1 1 1 1 1 0 1
Encoder D
7 1
8 0 1 1 1 1 1 1 1 1 1 1 0
9 0 1 1 1 1 1 1 1 1 1 1 1 1 1
11. In Question 10, what would be the output for an (a) 1101 (b) 0010
input bit sequence of 0001111111 corresponding to (c) 1111 (d) 0110
decimal digits 0 to 9?

SOLVED EXAMPLES 593
Solution. Three digits, namely, 0, 1 and 2 are Solution. The number of inputs is
active simultaneously. 2 will have priority encod-
ing. Since the outputs are active when LOW; the 8 + 8 + 3 = 19
BCD output will be 1101.
Here, the number of selection inputs is 3. The
Ans. (a)
number of outputs is 2. Therefore, the size of
12. The size of a PROM needed to implement a dual PROM is
8-to-1 multiplexer with common selection inputs
would be 219 2 = 512K 2
Ans. (b)
(a) 256K 2 (b) 512K 2
(c) 1024K 2 (d) None of these
1. How many logic gates are required to generate the for X and Y in terms of A, B and C inputs.
SUM output in a half-adder circuit? Therefore the value of X = 1.
Ans. (1)
Solution. Only one two-input EX-OR gate is
required to generate the SUM output in a half 6. A multiplexer has X data inputs, three control
adder circuit since 0 + 0 = 0, 0 + 1 = 1 + 0 = 1 inputs and one output. What is X?
and 1 + 1 = 0. The answer is 1.
Solution. Here X = 2m where `m is number of
Ans. (1)
control inputs. Therefore, X = 23 = 8.
2. How many inputs does a half-subtractor have? Ans. (8)
Solution. There are two inputs namely minuend 7. Identify the logic status of F output for I0 = I2 = 0,
and subtrahend. The answer is 2. I1 = I3 = 1, S0 = 1 and S1 = 0. Function performed
Ans. (2) by the logic diagram shown in the following figure.
3. How many inputs does a full-adder have?
Solution. The three inputs are the two bits to be I3 I1
added and the third input is the CARRY IN. The MUX Y
answer is 3.
Ans. (3) I2 I0
S
4. In the case of subtraction of two bits, what will
I1
be the DIFFERENCE output when minuend and
subtrahend bits respectively are 0 and 1? MUX Y F
I0
Solution. In this case, 0 1 = 1 with BORROW
S
IN of 1.
Ans. (1)
I1 I1
5. In the basic logic circuit shown in the following Y
figure, determine the status of X for A = 0, B = 1 MUX
and C = 0. I0 I0
S
A
X
B
C Y
S1 S0
Solution. The circuit is basically a one-bit adder
subtractor. Here, A and B are input bits; C is the Solution: F will be I1 of the output MUX, which
control input; X is the SUM or DIFFERENCE will further be equal to I2 of top input MUX. The
output and Y is the CARRY or BORROW output. answer is 0.
This can be verified by writing Boolean functions Ans. (0)

8. An 8-to-1 multiplexer is used to generate the Therefore, there are 1024 AND gates at the input.
CARRY output of a full-adder. If the three control There are four OR gate outputs. Each of the 1024
inputs are used as the two input bits to be added possible minterms available from AND gate array
and the CARRY IN bit; how many number of data can be programmed to appear at the output of each
bits would need to be tied to logic `1 status? of the four OR gates. Therefore, number of pro-
grammable interconnections is
Solution. The CARRY output of `1 would be pro-
duced for input bit sequences of 011, 101, 110 and 1024 4 = 4096
111, which correspond to I3, I5, I6 and I7. Therefore,
four data bits need to be tied to logic `1 status. Ans. (4096)
Hence, the answer is 4. 10. How many outputs will a PAL device designated as
Ans. (4) PAL16L8 have?
9. How many programmable interconnections does a
1K 4 PROM have? Solution. It will have 16 inputs and 8 active LOW
Solution. outputs. Therefore, the total outputs is 8.
1K = 210 = 1024 Ans. (8)
PRACTICE EXERCISE
1. An eight-bit magnitude comparator can be con- 5. Given that IC 7483 is four-bit parallel adder chip; how
structed by using would you construct a 16-bit parallel adder circuit?

(a) eight one-bit magnitude comparators (a) By a cascaded arrangement of four 7483s
(b) four two-bit magnitude comparators (b) By a cascaded arrangement of 16 7483s

(c) two four-bit magnitude comparators (c) 16-bit adder cannot be constructed from 7483s
(d) None of these (d) None of these
(1 Mark) (2 Marks)
2. A full-subtractor can be constructed from two half- 6. In a decoder, n is the number of input lines and m
subtractors and one is the number of output lines. One of the following
equations is valid.
(a) two-input OR gate
(b) two-input AND gate (a) m = 2n (b) n = 2m
(c) two-input EX-OR gate (c) m 2n (d) n 2m
(d) three-input OR gate (1 Mark)
(1 Mark) 7. The 10-input bits to a 10-line decimal to four-line
BCD priority encoder corresponding to 0, 1, 2, 3,
3. A full-adder can be constructed from two half- 4, 5, 6, 7, 8 and 9, respectively, are 1, 0, 0, 0, 1, 1,
adders and one 0, 1, 0 and 0. What will be the corresponding BCD
(a) two-input OR gate output if all inputs and outputs are active HIGH?
(b) two-input AND gate The encoder has priority for higher order bits.
(c) two-input Exclusive-OR gate (a) 0111 (b) 1000
(d) three input OR gate (c) 1001 (d) 0110
(1 Mark) (2 Marks)
4. A four-bit adder-subtractor can be constructed 8. In the encoder mentioned in question 7, what will
from four full-adders and be the corresponding BCD output if all inputs were
active HIGH and outputs were active LOW and
(a) four two-input OR gates
also the encoder had priority for lower order bits?
(b) two four-input OR gates
(c) two four-input Exclusive-OR gates (a) 1110 (b) 0000
(d) four two-input Exclusive-OR gates (c) 0001 (d) 1111
(1 Mark) (1 Mark)

9. Size of the PROM required to implement 16 1 11. A PROM is usually not preferred to implement
multiplexer would be
(a) very complex Boolean functions
(a) 512K 1 (b) 1M 2 (b) Boolean functions with large number of `dont
(c) 1M 1 (d) 512K 2 care conditions
(1 Mark) (c) Boolean functions with large number of outputs
(d) Boolean functions which can otherwise be
10. The architecture of a PLA differs from that of a implemented with PLAs
PROM in the sense that (1 Mark)
(a) former has a larger number of AND gates in 12. A PLA like architecture required to implement a
the AND array than the latter for a given full-adder should at least have
number of variables (a) seven six-input AND gates and two four-input
(b) former has hard wired AND array and program- OR gates
mable OR array while latter has a programmable (b) eight three-input AND gates and two four-
AND array and a hard wired OR array input OR gates
(c) former has a programmable AND array and a (c) seven six-input AND gates and two three-input
programmable OR array while latter has hard OR gates
wired AND array and programmable OR array (d) seven six-input AND gates and two three-input
(d) None of these OR gates
(1 Mark) (1 Mark)
1. Determine the minimum number of programmable 6. How many two-input EX-OR gates would be
interconnections required in the PLA architec- required to generate the SUM output of addition
ture used to implement a full-adder. of three bits?
(2 Marks) (1 Marks)
2. Determine the minimum number of AND gates 7. The minuend, the subtrahend and the
required in the architecture of a PROM used to BORROW IN inputs of a full-subtractor were
implement a full-adder. fed with certain bit status. The DIFFERENCE
(1 Marks) output was observed to be `1. If the minuend,
3. Determine the number of data outputs in a 1-to-32 subtrahend and BORROW IN bit status were
demultiplexer. applied to augend, addend and CARRY IN
(1 Marks) inputs of a full-adder; determine the bit status
of SUM output.
4. What is the least number of input lines in a mul- (2 Marks)
tiplexer capable of implementing the following
Boolean function: 1, 13? 8. The objective is to design a BCD adder that can add
two decimal numbers using four-bit binary adders
(2 Marks)
of the type IC 7483 and some combinational logic.
5. What is the least number of input lines in a If the decimal numbers to be added can be any-
multiplexer capable of implementing the following where between 0 and 999; determine the number of
Boolean function: 8, 9, 10, 11, 12, 13, 14, 15? four-bit binary adders required to do the job.
(2 Marks) (2 Marks)
1. (c) The less significant four bits of the two words A > B outputs of less significant comparator are
to be compared are applied to the less significant applied to A < B, A = B and A > B inputs of more
magnitude comparator and more significant bits significant comparator respectively. Also, A < B
of the two words are applied to the less signifi- and A > B inputs of less significant comparator are
cant magnitude comparator. A < B, A = B and grounded and A = B input is applied logic `1.

2. (a) The block diagram representation of a full sub- 8. (d) The inputs are active when HIGH and all out-
tractor using two half subtractors and a two-input puts are active when LOW. The priority is for lower
OR gate is shown in Fig. 25.10. order bits. The lowest input bit that is HIGH cor-
responds to decimal number `0. Since the output is
3. (a) The block diagram representation of a full active when LOW, encoded output would be 1111.
adder using two half adders and a two-input OR
gate is shown in Fig. 25.5. 9. (b) 16-to-1 multiplexer has 16 data inputs and four
control inputs. Total number of inputs is therefore
4. (d) An addersubtractor circuit is nothing but an 20. Also there is only one output. Therefore, size of
adder circuit with a controlled inverter. In the case multiplexer is 220 1 or 1M 1.
of a four-bit addersubtractor, one would require
a four-bit controlled inverter. A two-input EX-OR 10. (c) Block diagram representations of PROM and
gate is a single bit controlled inverter. PLA devices are shown in Figs. 25.30 and 25.32
respectively.
5. (a) The CARRY output of each 7483 is connected
to the CARRY input of the next higher order 7483. 11. (b) In the case of a PROM, each `dont care con-
The CARRY input of LSB 7483 constitutes the dition would have either all 0s or all 1s. In other
CARRY input of the 16-bit adder and CARRY words, space on the chip is not optimally utilized.
output of MSB 7483 constitutes the CARRY 12. (a) There are seven minterms to be generated, four
output of 16-bit adder. for SUM output and three for CARRY output and
6. (c) seven AND gates. There are three variables. Each
variable is to be generated in true and complement
7. (a) The inputs and outputs are active when HIGH. form and hence six-input AND gates. There are two
Priority is for higher order bits. The highest input outputs and hence two OR gates. Maximum number
bit that is HIGH corresponds to decimal number 7. of minterms in these outputs is four in the SUM
Therefore, the encoded output would be 0111. output. Therefore, OR gates are four-input gates.
1. The number of programmable interconnections in a 5. Equivalent sum-of-products Boolean function is

PLA architecture is given by 2kn + km, where n is 0, 1, 2, 3, 4, 5, 6, 7 and it is a three variable
number of input variables; k is the number of AND expression. Therefore, it can be implemented by a
gates and `m is the number of OR gates. Full- 2-to-1 multiplexer. Thus, the least number of input
adder has seven AND gates, two OR gates and lines is 2.
three-input variables. Hence, the minimum number Ans. (2)
of programmable interconnections required in the
6. We would need a three-input EX-OR function,
PLA architecture used to implement a full-adder
which can be implemented by using two two-input
comes out to be 56.
EX-OR gates. Thus, the answer is 2.
Ans. (56)
Ans. (2)
2. The number of AND gates is equal to 2n where n
7. Boolean functions describing DIFFERENCE
is number of input variables. Therefore, number of
and SUM outputs are the same if CARRY IN,
AND gates is 8.
Augend and Addend of full-adder are replaced
Ans. (8)
by BORROW IN, Minuend and Subtrahend of
3. Number of data outputs is 32. Number of control full-subtractor. Therefore, the bit status of SUM
inputs in this case will be 5 and number of data output is 1.
inputs will be 1. Ans. (1)
Ans. (1)
8.Addition of each decimal digit requires two four
4. The given sum-of-products Boolean function has four binary adders of the type 7483. Since there are a
variables. Conventionally, one would need a 16-to-1 maximum of three decimal digits in each decimal
multiplexer and number of input lines would be number in the addition; one would require six IC
16. The same can be implemented by 8-to-1 multi- 7483. Thus, the number of four-bit binary adders
plexer. (The procedure is explained in the chapter.) required to do the job is 6.
Therefore, the least number of input lines is 8. Ans. (6)
Ans. (8)

1. Without any additional circuitry, an 8:1 MUX can MSB

be used to obtain
(a) some but not all Boolean functions of three
variables
(b) all functions of three variables, but none of four
variables
(c) all functions of three variables and some but
not all of four variables
(d) all functions of 4 variables OUTPUTS
(GATE 2003: 1 Mark) MSB
Solution. By connecting all input lines to logic
Solution. The logic circuit is redrawn as shown in
`1 state; all eight possible three-variable minterms
the following figure:
can be generated. These represent eight out of six-
teen functions of four variables 1 0 1 0
Ans. (c) a b c d
1 1
2. The circuit shown in the following figure has four 1 1
boxes each described by inputs P, Q, R and outputs 0 1
Y, Z with Y = P Q R and Z = RQ + PR + QP . 0 1 1 1
1 0
The circuit acts as a
1
(a) four-bit adder giving P + Q 0
(b) four-bit subtractor giving P Q
(c) four-bit subtractor giving Q P 0
w x y z
(d) four-bit adder giving P + Q + R
1 1 0 0
Now,
w=a
Q
x =ab
y = c x(a + b)
z = d y(a + b + c)
P
These are Boolean functions for converting Gray
P Q P Q P Q P Q code number to Binary code number.
Z R Z R Z R Z R Ans. (d)
Y Y Y Y
4. The minimum number of 2-to-1 multiplexers required
to realize a 4-to-1 multiplexer is
(a) 1 (b) 2 (c) 3 (d) 4
Output (GATE 2004: 2 Marks)
Solution. Two 2-to-1 multiplexers are required at

Solution. Y = D = P Q R and
the input and one 2-to-1 multiplexer is required at
the output.
ZZ =
=Borrow
Borrow == RQ
RQ++PR
PR ++QP
QP Ans. (c)
Ans. (b)
5. The Boolean function f implemented in the follow-
3. The circuit shown in the following figure converts ing figure using two input multiplexers is
(a) BCD to binary code (a) ABC + ABC (b) ABC + ABC
(b) Binary to excess 3 code
(c) Excess 3 to Gray code (c) ABC + ABC (d) ABC + ABC
(d) Gray to Binary code (GATE 2005: 1 Mark)

C O
0 0 I3
f I2
C A
1 1 4-to-1 MUX Z
I1
B E I0

f = E A R S
where E = BC + BC. Therefore, output f is given by (GATE 2008: 2 Marks)
ABC + ABC
Ans. (a) Solution. The output can be written as
6. In the circuit shown in the following figure, X is Z = PRS + PQRS + PRS + (P + Q)RS
given by
(a) X = ABC + ABC + ABC + ABC The following figure shows the respective Karnaugh
(b) X = AB + BC + AC map.
(c) X = AB + BC + AC
(d) X = AB + BC + AC RS
PQ 00 01 11 10
0 I0 0 I0
00 1
1 I1 4-to-1 1 I1 4-to-1
Y X
1 I2 MUX 1 I2 MUX
01
0 I3 0 I3
S1 S0 S1 S0
11 1 1 1 1
A B C
(GATE 2007: 2 Marks) 10 1 1 1

Solution. Let the output of the first MUX be Y.
Therefore,
Therefore, the output is
Y = AB + AB = A B
X = YC + YC = Y C Z = PQ + PQS + QRS
Thus, Ans. (a)
X = A B C = ABC + ABC + ABC + ABC
Ans. (a) Statement for Linked Answer Questions 8 and 9:
Two products are sold from a vending machine, which
7. For the circuit shown in the following figure, I0 to has two push buttons P1 and P2. When a button is
I3 are the inputs to the 4:1 multiplexer R(MSB) pressed, the price of the corresponding product is
and S are control bits. The output Z can be repre- displayed in a seven-segment display. If no buttons
sented by are pressed, `0 is displayed, signifying `H0. If only P1
is pressed, `2 is displayed, signifying `H2. If only P2 is
(a) PQ + PQS + QRS pressed, `5 is displayed, signifying `H5. If both P1 and
(b) PQ + PQR + PQS P2 are pressed, È is displayed, signifying Èrror. The
names of the segments in the seven-segment display, and
(c) PQR + PQR + PQRS + QRS
the glow of the display for `0, `2, `5 and È are shown
(d) PQR + PQRS + PQRS + QRS in the following figure.

a 9. What are the minimum numbers of NOT gates and

two-input OR gates required designing the logic of
f b the driver for this seven-segment display?
g
(a) 3 NOT and 4 OR (b) 2 NOT and 4 OR
e c
(c) 1 NOT and 3 OR (d) 2 NOT and 3 OR
d (GATE 2009: 2 Marks)
0 2 5 E
Solution. The answer is obvious from the Boolean
functions of a to g. Implementation of b and c
require NOT gates. Implementation of e, f and g
require OR gates. Ans. (d)
10. What are the minimum number of 2-to-1 multi-
plexers required to generate a two-input AND gate
Consider and a two-input EX-OR gate?
i.Push button pressed/not pressed is equivalent (a) 1 and 2 (b) 1 and 3
to logic 1/0, respectively. (c) 1 and 1 (d) 2 and 2
ii.A segment glowing/not glowing in the display (GATE 2009: 2 Marks)
is equivalent to logic 1/0, respectively.
Solution. One 2-to-1 multiplexer is required to
8. If segments a to g are considered as functions of P1 implement AND gate. In the case of AND gate
and P2, then which of the following is correct? implementation, select line is tied to A input, I0
input line is tied to logic 0 and I1 input line is tied
(a) g = P1 + P2 , d = c + e to logic 1. Similarly, EX-OR gate also requires one
(b) g = P1 + P2 , d = c + e 2-to-1 multiplexer. Select line is connected to A.

(c) g = P1 + P2 , e = b + c Input lines I0 and I1, respectively, are connected
to B and B . Ans. (c)
(d) g = P1 + P2 , e = b + c
(GATE 2009: 2 Marks) 11. The Boolean function realized by the logic circuit
shown in the following figure is
Solution. The truth table can be drawn as follows:
C I0
P1 P2 a b c d e f g
0 0 1 1 1 1 1 1 0 D I1
0 1 1 0 1 1 0 1 1 4-to-1
1 0 1 1 0 1 1 0 1 I2 MUX F (A,B,C,D)
1 1 1 0 0 1 1 1 1
I3
From the truth table, we can write the simplified S1 S0
Boolean functions for a, b, c, d, e, f and g as follows:
A B
a =1 (a) F = m (0, 1, 3, 5, 9, 10, 14)
b = P2 (b) F = m (2, 3, 5, 7, 8, 12, 13)

(c) F = m (1, 2, 4, 5, 11, 14, 15)
c = P1
(d) F = m (2, 3, 5, 7, 8, 9, 12)
d =1 (GATE 2010: 2 Marks)
e = P1 + P2 Solution.
f = P1 + P2 F (A, B, C , D) = ABC + ABD + ABC + AB(CD)
g = P1 + P2
= ABC(D + D) + AB(C + C )D
From the above expressions, we get + ABC(D + D) + ABCD

c+e=1=d which gives
and hence the answer. F = m(2, 3, 5, 7, 8, 9, 12)
Ans. (b) Ans. (d)

12. The logic function implemented by the circuit

F = P Q + P Q = XOR (P, Q)
shown in the following figure is (ground implies a
logic `0) Ans. (d)
4-to-1 MUX 13. The output Y of a two-bit comparator is logic 1

whenever the two-bit input A is greater than the
I0
two-bit input B. The number of combinations for
which the output is logic 1, is
I1
(a) 4 (b) 6 (c) 8 (d) 10
Y F (GATE 2012: 1 Mark)
I2
Solution. Output will be 1 if A > B. Now, A can
I3 be greater than B for the following conditions:
S1 S0
i.If B = 00, there will be three combinations for
P Q which O/P will be 1, that is, when A = 01, 10, or 11.
ii.If B = 01, there will be two conditions, that is,
(a) F = AND (P, Q) (b) F = OR (P, Q) A = 10 and 11.
(c) F = XNOR (P, Q) (d) F = XOR (P, Q)
(GATE 2011: 1 Mark) iii.If B = 10, there will be one condition, that is,
A = 11.
Solution. I1 and I2 are tied to logic `1 state. I0 and Therefore, there are a total of six combinations for
I3 are tied to logic `0 state. Therefore, the output which output is in logic `1 state.
is logic `1 for P = 0, Q = 1 and P = 1, Q = 0. Ans. (b)
Therefore, the output is

CHAPTER 26
SEQUENTIAL CIRCUITS
This chapter discusses various sequential logic circuits including multivibrators, latches, flipflops, counters and
registers. The different sequential logic devices are discussed in terms of their types, operational principles, timing
diagrams and applications.
26.1 MULTIVIBRATOR subsequent pages, the operation of a Bistable multivibra-

tor is identical to that of a flipflop. Figure 26.1 shows
the basic bistable multivibrator circuit. This is the fixed
Multivibrators are circuits with regenerative feedback bias type of bistable multivibrator. Other configurations
with the difference that they produce pulsed output. are self-bias type and the emitter coupled type. However,
There are three basic types of multivibrators, namely, the operational principle of all these three types of multi-
(1) bistable multivibrator, (2) monostable multivibrator vibrators is the same.
and (3) astable multivibrator. These multivibrators are In the circuit arrangement shown in Fig. 26.1, it can
briefly described in the following sections. be proved that both the transistors Q1 and Q2 cannot be
simultaneously ON or OFF. If Q1 is ON, the regenera-
26.1.1 Bistable Multivibrator tive feedback ensures that Q2 is OFF and when Q1 is
OFF, the feedback drives transistor Q2 to the ON state.
A bistable multivibrator circuit is the one in which both Transition to the other state can be caused by applying
LOW and HIGH output states are stable. Irrespective a trigger pulse of appropriate amplitude and polarity to
of the logic status of the output, LOW or HIGH, it the base of one of the two transistors. Both states are
stays in that state unless a change is induced by apply- stable and a change of state takes place only when the
ing an appropriate trigger pulse. As we shall see in the multivibrator is suitably triggered.

602 Chapter 26: Sequential Circuits
+V VCC
IC1 IC2
C C
RC RC
VO1 = VC1 R1 R1 VO2 = VC2
Q1 Q2
R2 R2
VCE (sat) 0
V
Figure 26.1| Bistable multivibrator. VLT VUT

Vin
Figure 26.3| Transfer characteristics of a Schmitt trigger.
26.1.2 Schmitt Trigger
Figure 26.3 shows the transfer characteristics of the
Schmitt trigger circuit is a slight variation of the bistable
Schmitt trigger circuit. The lower trip point (VLT) and
multivibrator circuit shown in Fig. 26.1. Figure 26.2
upper trip point (VUT) of these characteristics is given
shows the basic Schmitt trigger circuit. If we compare
by the following equations:
the bistable multivibrator circuit shown in Fig. 26.1
with the Schmitt trigger circuit shown in Fig. 26.2, we V R
find that the coupling from Q2-collector to Q1-base in VLT = CC e + 0.7
case of bistable circuit is absent in case of Schmitt trig- Re + RC1
ger circuit. Instead, resistance Re provides the coupling. V R
V UT = CC e + 0.7
The circuit functions as follows: The output taken across Re + RC2
Q2-collector is normally LOW in the absence of an input
pulse. When the input increases beyond a certain thresh-
old voltage level VLT, the output goes to HIGH state. 26.1.3 Monostable Multivibrator
It stays in HIGH state as long as Vin remains greater
than VLT. When Vin falls below another threshold volt- A monostable multivibrator, also known as monoshot,
age level VUT, the output goes back to LOW state. is the one in which one of the states is stable and
the other is quasi-stable. The circuit is initially in the
stable state. It goes to the quasi-stable state when
VCC appropriately triggered. It stays in the quasi-stable
state for a certain time period depending upon values
C of R and C, after which it comes back to the stable
RC1 RC2
state. Figure 26.4 shows the basic monostable multi-
Vo vibrator circuit.
R2 In a conventional monostable multivibrator, once
the output is triggered to the quasi-stable state by
Vin
applying a suitable trigger pulse, the circuit does
Q1 Q2 not respond to subsequent trigger pulses as long as
the output is in quasi-stable stable. After the output
returns to its original state, it is ready to respond to
the next trigger pulse. There is another class of mono-
stable multivibrators called retriggerable monostable
Re R1 multivibrators, which responds to trigger pulses even
when the output is in quasi-stable state. In this class
of monostable multivibrators, if n trigger pulses with
a time period Tt are applied to the circuit, the output
pulse width, that is, the time period of the quasi-
Figure 26.2| Schmitt trigger circuit. stable state equals

26.1 MULTIVIBRATOR 603
+VCC VCC
RC1 R RC2 RC1 R1 R2 RC2

C1
C C1 C2
Vo
R1 Vo
Q1 Q2
R2 Q1 Q2
V Figure 26.6| Astable multivibrator.

Figure 26.4| Monostable vibrator.
26.1.5 IC Timer Based Multivibrators
(n 1)Tt + T
IC timer 555 is one of the most commonly used general
where (T) is the output pulse width for the single trigger purpose linear integrated circuits. The simplicity with
pulse and Tt < T. Figure 26.5 shows output pulse width which monostable and astable multivibrator circuits can be
in case of a retriggerable monostable multivibrator for configured around this IC is one of the main reasons for its
repetitive trigger pulses. wide use. Figure 26.7 shows the internal schematic of timer
IC 555. It comprises of two operational amplifier (opamp)
comparators, a flipflop, a discharge transistor, three iden-
tical resistors and an output stage. The resistors set the ref-
Trigger erence voltage levels at the non-inverting input of the lower
Pulses comparator and inverting input of the upper comparator
at +VCC/3 and +2VCC/3. Outputs of two comparators
feed SET and RESET inputs of the flipflop and thus
decide the logic status of its output and subsequently the
final output. The flipflops complementary outputs feed
Output the output stage and the base of the discharge transistor.
Pulse Tt T This ensures that when the output is HIGH, the discharge
Figure 26.5| Retriggerable monostable multivibrator
transistor is OFF and when the output is LOW, the dis-
charge transistor is ON. Different terminals of the timer
output for repetitive trigger pulses.
555 are designated as ground (terminal-1), trigger (ter-
minal-2), output (terminal-3), reset (terminal-4), control
26.1.4 Astable Multivibrator (terminal-5), threshold (terminal-6), discharge (terminal-7)
and +VCC (terminal-8). With this background, we shall
In case of an astable multivibrator, neither of the two now describe the astable and monostable circuits config-
output states is stable. Both output states are quasi- ured around timer 555.
stable. The output switches from one state to the other
and the circuit functions like a free running square wave 26.1.5.1 Astable Multivibrator Using Timer
oscillator. Figure 26.6 shows the basic astable multivibrator IC 555
circuit. It can be proved that in this type of circuit,
neither of the output states is stable. Both states, LOW Figure 26.8(a) shows the basic 555 timer based astable
as well as HIGH are quasi-stable. The time periods for multivibrator circuit. Initially, capacitor C is fully dis-
which the output remains LOW and HIGH depends upon charged, which forces output to go to HIGH state. An
R2C2 and R1C1 time constants, respectively. For R1C1 open discharge transistor allows the capacitor C to
= R2C2, the output is a symmetrical square waveform. charge from +VCC through R1 and R2. When the voltage

VCC(Pin-8)
Vref (int)
2 5kW
Reset (Pin-4)
Control 3 VCC

(Pin-5)
Threshold +
(Pin-6)
5kW FF
1 +
Trigger 3 VCC

(Pin-2)
Discharge
(Pin-7) Output
stage Output (Pin-3)
5kW Discharge
transistor
Ground (Pin-1)
Figure 26.7| Internal schematic of timer IC 555.
across C exceeds +2VCC/3, the output goes to LOW period is about 30% longer as the capacitor is initially
state and the discharge transistor is switched ON at the discharged and it charges from 0, rather than +VCC/3
same time. The capacitor C begins to discharge through to +2VCC/3. In case of the astable multivibrator circuit
R2 and the discharge transistor inside the IC. When the shown in Fig. 26.8(a), HIGH-state time period is always
voltage across C falls below +VCC/3, the output goes greater than the LOW-state time period. Figures 26.8(c)
back to HIGH state. The charge and discharge cycles and (d) show the two modified circuits where HIGH-
repeat and the circuit behaves like a free running multi- state and LOW-state time periods can be chosen inde-
vibrator. Terminal-4 of the IC is the RESET terminal. pendently. For the astable multivibrator circuits shown
Usually, it is connected to +VCC. If the voltage at this in Figs. 26.8(c) and (d), the two time periods are given
terminal is driven below 0.4 V, the output is forced to by following equations:
LOW state overriding the command pulses at terminal-2
of the IC. HIGH-state and LOW-state time periods are HIGH-state time period = 0.69R1C
governed by the charge +VCC/3 to +2VCC/3 and dis-
LOW-state time period = 0.69R2C
charge +2VCC/3 to +VCC/3 timings. These are given by
following equations: For R1 = R2 = R, we would have
HIGH-state time period, THIGH = 0.69(R1 + R2)C 1

T = 1.38RC and f =
1.38RC
LOW-state time period, TLOW = 0.69(R2C)
26.1.5.2Monostable Multivibrator Using
The relevant waveforms are shown in Fig. 26.8(b). The Timer IC 555
time period (T) and the frequency (f) of the output
waveform, respectively, are given by following equations: Figure 26.9(a) shows the basic monostable multivibra-
tor circuit configured around timer 555. Trigger pulse is
Time period, T = 0.69(R1 + 2R2)C applied to terminal-2 of the IC, which should initially be
1 kept at +VCC. A HIGH at terminal-2 forces the output
Frequency, f =
0.69(R1 + 2R2 )C to LOW state. A HIGH-to-LOW trigger pulse at termi-
nal-2 holds the output in the HIGH state and simultane-
It should be remembered that when the astable mul- ously allows the capacitor to charge from +VCC through
tivibrator is powered, the first cycle HIGH-state time R. It should be remembered that the LOW level of the

26.1 MULTIVIBRATOR 605
Vo
+VCC
R1
tON tOFF
7 8 4 3 Vo
R2 555 t
2,6 5 1 VC
2V
3 CC
C 0.01 F
1V
CC
3
t
(a) (b)
+VCC
+VCC
R1
4 8 3 Vo
7 8 4 3 Vo
D R2 555 7
555
2,6 5 R2 R1
1
5 1 2,6
C 0.01 F 0.01 F C
(c) (d)
Figure 26.8| (a) Astable multivibrator using timer IC 555; (b) Astable multivibrator relevant waveforms;
(c) and (d) Modified versions of the astable multivibrator using timer IC 555.
trigger pulse needs to go at least below +VCC/3. When leading edges (LOW-to-HIGH) of the trigger waveform.
the capacitor voltage exceeds +2VCC/3, the output goes In order to achieve that, we shall need an external cir-
back to the LOW state. We shall need to apply another cuit between the trigger waveform input and terminal-2
trigger pulse to terminal-2 to make the output go to of timer 555. The external circuit ensures that termi-
HIGH state again. Every time, the timer is appropriately nal-2 of the IC gets the required trigger pulse corre-
triggered, the output goes to HIGH state and stays there sponding to the desired edge of the trigger waveform.
for a time period taken by capacitor to charge from 0 to Figure 26.10(a) shows the Monoshot configuration that
+2VCC/3. This time period, which equals the monoshot can be triggered on the trailing edges of the trigger
output pulse width, is given by equation waveform. R1-C1 combination constitutes a differentia-
tor circuit. One of the terminals of resistor R1, is tied to
T = 1.1RC +VCC with the result that the amplitudes of differenti-
ated pulses are +VCC to +2VCC and +VCC to ground
Figure 26.9(b) shows relevant waveforms for the circuit corresponding to leading and trailing edges of the trig-
shown in Fig. 26.9(a). ger waveform, respectively. Diode (D) clamps the posi-
It is often desirable to trigger a Monostable mul- tive going differentiated pulses to about +0.7 V. The net
tivibrator either on the trailing (HIGH-to-LOW) or result is that the trigger terminal of timer 555 gets the

+VCC VCC
R1 D R
R 4, 8
8 4 2 3 Vo
6,7 Trigger
3 Vo I/p C1
C 555 555 6, 7
VC
Trigger 2
5 1 1 5
C
0.01 0.01 F
F
(a)
(a)
+VCC VCC
Trigger
Trigger I/P
input 0
t +0.7
Vo T At VCC
Pin-2
Output
0
t
VC (b)
Figure 26.10| 555 monoshot triggering on trailing
2V edges.
3 CC
the trigger waveform for proper differentiation. Second,

t
the differentiated pulse width should be less than the
(b)
expected HIGH-time of the monoshot output.
Figure 26.9| (a) Monostable multivibrator using timer
555 and (b) monostable multivibrator
relevant waveforms. 26.2 R-S (RESET AND SET) FLIP
FLOP
required trigger pulses corresponding to HIGH-to-LOW
edges of the trigger waveform. Figure 26.10(b) shows
relevant waveforms. A flipflop is a bistable multivibrator circuit. Both of
Figure 26.11(a) shows the monoshot configuration its output states are stable. The circuit remains in a
that can be triggered on the leading edges of the trigger particular output state indefinitely until something
waveform. R1-C1 combination constitutes the differentia- is done to change that output status. Referring to the
tor producing positive and negative pulses corresponding Bistable multivibrator circuit discussed earlier, these two
to LOW-to-HIGH and HIGH-to-LOW transitions of the states were those of the output transistor in saturation
trigger waveform. The negative pulses are clamped by (representing a LOW output) and cut-off (representing
the diode and the positive pulses are applied to the base a HIGH output). If the LOW and HIGH outputs,
of a transistor switch. Collector terminal of the tran- respectively, are regarded as `0 and `1, then the output
sistor feeds the required trigger pulses to terminal-2 of can either be a `0 or a `1. Since either a `0 or a `1
the IC. Figure 26.11(b) shows relevant waveforms. For can be held indefinitely till the circuit is appropriately
the circuits shown in Figs. 26.10 and 26.11 to function triggered to go to the other state, the circuit is said to
properly, the values of R and C for the differentiator have memory. It is capable of storing one binary digit or
should be chosen carefully. First, the differentiator time one bit of digital information. Also, if we recall the func-
constant should be much smaller than the HIGH-time of tioning of the Bistable multivibrator circuit, we find that

26.2 R-S (RESET AND SET) FLIPFLOP 607
VCC
S
R3 1 Q Q
S
8
C1 R2 2 4 R
Trigger
I/P RS
Q 555 6,7 FF
R1 D
3 Vo
1
5 R Q
0.01 F
C 2 Q
R
(a) (b)
(a)
Operation
VCC S R Qn+1
Mode
No change 1 1 Qn
Trigger
I/P 0 SET 0 1 1
VCC RESET 1 0 0
After Forbidden 0 0
differentiator
0
0.7 (c)
At Pin-2 VCC Figure 26.12| R-S flipflop with active-LOW inputs.
Figure 26.12(b) shows its logic symbol. It can be explained

0 that this configuration follows the function table of
Fig. 26.12(c). The operation of R-S flipflop shown in
(b) Fig. 26.12(a) can be briefly described as follows:
Figure 26.11|555 monoshot triggering on leading edges. 1. SET = RESET = 1 is the normal resting condition
of the flipflop. In this case, both SET and RESET
when one of the transistors was in saturation, the other inputs are inactive. It has no effect on the output
was in cut-off. This implies that if we had taken outputs state of flipflop. Both Q and Q outputs remain
from collectors of both transistors, then the two outputs in the logic state they were in prior to this input
would be complementary. In the flipflops of various condition.
types available in the IC form, we shall see that all these 2. SET = 0 and RESET = 1 sets the flipflop. Q and
devices offer complementary outputs usually designated Q go to `1 and `0 state, respectively.
as Q and Q . The R-S flipflop is the most basic of all 3. SET = 1 and RESET = 0 resets or clears the flip
flipflops. `R and `S stand for RESET and SET. When flop. Q and Q go to `0 and `1 state, respectively.
the flipflop is SET, its Q-output goes to `1 state and 4. SET = RESET = 0 is forbidden as such a condi-
when it is RESET, it goes to `0 state. Q -output is com- tion tries to set (i.e., Q = 1) and reset (that is, Q
plement of Q-output. = 1) the flipflop at the same time. To be more
precise, SET and RESET inputs in R-S flipflop
cannot be active at the same time.
26.2.1 R-S FlipFlops with Active LOW and
Active HIGH Inputs The R-S flipflop shown in Fig. 26.12(a) is also referred
to as an R-S latch. It is said so as any combination at
Figure 26.12(a) shows a NAND gate implementation of the inputs immediately manifests itself at the output as
an R-S flipflop with active LOW inputs. The two NAND per the truth table.
gates are cross coupled. That is, output of NAND-1 is Figure 26.13(a) shows another NAND gate implemen-
fed back to one of the inputs of NAND-2 and the output tation of R-S flipflop. Figures 26.13(b) and (c), respec-
of NAND-2 is fed back to one of the inputs of NAND-1. tively, show its circuit symbol and function table. It can
The remaining input of NAND-1 and NAND-2 are the be explained that such a circuit would have active HIGH
S and R inputs. The output of NAND-1 and NAND-2, inputs and the input combination R = S = 1 would be
respectively, are Q and Q outputs. forbidden. Again, as outlined earlier, SET and RESET

S
Q
S Q
Operation
RS Mode S R Qn+1
FF No change 0 0 Qn
SET 1 0 1
RESET 0 1 0
Q R Q
R Forbidden 1 1
(a) (b) (c)

Figure 26.13| R-S flipflop with active-HIGH inputs.
inputs in R-S flipflop cannot be active at the same expressed its output (immediately after it was clocked)
time. NOR gate implementation of R-S flipflops (or in terms of its present output and its inputs. The func-
latches) shown in Figs. 26.12(a) and 26.13(a) are shown tion tables shown in Figs. 26.12(c) and 26.13(c) may be
in Figs. 26.14 (a) and (b), respectively. redrawn as shown in Figs. 26.15(a) and (b), respectively.
This new form of representation is known as the char-
acteristic table. Having done this, we could even write
S simplified Boolean expressions called characteristic equa-
Q
tions using any of the minimization techniques such as
Karnaugh mapping. The K-maps for the characteristic
tables shown in Figs. 26.15(a) and (b) are, respectively,
shown in Figs. 26.15(c) and (d). Characteristic equations
for R-S flipflops with active LOW and active HIGH
inputs are given as follows:
Q Qn Qn+1 Qn S R Qn+1
R S R
0 0 0 Indeter 0 0 0 0
(a) 0 0 1 1 0 0 1 0
0 1 0 0 0 1 0 1
0 1 1 0 0 1 1 Indeter
S 1 0 0 Indeter 1 0 0 1
Q 1 0 1 0
1 0 1 1
1 1 0 0 1 1 0 1
1 1 1 1 1 1 1 Indeter
(a) (b)
SR SR
Q Qn 00 01 11 10 Qn 00 01 11 10
R
0 1 0 1
(b) 1 1 1 1 1 1
Figure 26.14| NOR implementation of an R-S (c) (d)

flipflop.
Figure 26.15| (a) Characteristic table of an R-S
So far, we have discussed the operation of an R-S flip flipflop with active-LOW inputs and
flop with the help of its logic diagram and the func- (b) with active-HIGH inputs. (c) The
tion table on the lines similar to what we did in case of K-map solution of an R-S flipflop
combinational circuits. We would, however, appreciate with active-LOW inputs, and (d) with
that a sequential circuit would be better explained if we active-HIGH inputs.

26.3 LEVEL-TRIGGERED AND EDGE-TRIGGERED FLIPFLOPS 609
their status complemented. The outputs can now change

Qn +1 = S + R Qn and S + R = 1 (Active LOW inputs)
states as per the status of R and S at the flipflop inputs.
Qn +1 = S + R Qn and S R = 0 (Active HIGH inputs) For instance, when S = 1, R = 0, it will be passed on
to flipflop as S = 0, R = 1 when the clock is HIGH.
S + R = 1 indicates that R = S = 0 is a prohibited When the clock is LOW, the two NAND gates produce a
entry. Similarly, SR = 0 only indicates that R = S = 1 `1 at their outputs irrespective of S and R status. This
is a prohibited entry. produces logic `1 at both inputs of the flipflop with
the result that there is no effect on the output states.
Figure 26.17(a) shows the clocked R-S flipflop with
26.2.2 Clocked R-S FlipFlop
active LOW (R) and (S) inputs. The logic implementa-
tion here is a modification of the basic R-S flipflop of
In case of a clocked R-S flipflop or for that matter
Fig. 26.13(a). The truth table of this flipflop is shown in
any clocked flipflop, the outputs change states as per
Fig. 26.17(b) is self-explanatory. Figure 26.17(c) shows
the inputs only on the occurrence of a clock pulse. The
the circuit symbol.
clocked flipflop could be a level-triggered one or an
edge-triggered one. These two types are discussed in the
next section. Figure 26.16(a) shows the logic implemen- 26.3 LEVEL-TRIGGERED AND EDGE-
tation of a clocked flipflop that has active HIGH inputs.
TRIGGERED FLIPFLOPS
The function table and the circuit symbol for the same,
respectively, are shown in Figs. 26.16(b) and (c).
The basic flipflop is same as that shown in In a level-triggered flipflop, output responds to the data
Fig. 26.12(a). The two NAND gates at the input have present at the inputs during the time the clock pulse
been used to couple the R and S inputs to the flip level is HIGH (or LOW). That is, any changes at the
flop inputs under the control of clock signal. When the input during the time the clock is active (HIGH or LOW)
clock signal is HIGH, the two NAND gates are enabled are reflected at the output as per its function table. The
and S, R inputs are passed on to flipflop inputs with clocked R-S flipflops of Figs. 26.16(a) and 26.17(a)
S 1 Q
Clk
R 2 Q
(a)
S R Clk Qn+1
0 0 0 Qn S Q
0 0 1 Qn
0 1 0 Qn
0 1 1 0 Clk FF
1 0 0 Qn
1 0 1 1
1 1 0 Qn R Q
1 1 1 Invalid
(b) (c)
Figure 26.16| Clocked R-S flipflop with active-HIGH inputs.

described in the preceding paragraphs are level-triggered few nanoseconds wide. This narrow pulse coincides with
flipflops with active HIGH and active LOW inputs either LOW-to-HIGH or HIGH-to-LOW transition of
respectively. the clock input depending upon whether it is a posi-
In an edge-triggered flipflop, output responds to the tive edge-triggered flipflop or a negative edge-triggered
data at the inputs only on LOW-to-HIGH or HIGH- flipflop. This pulse is so narrow that the operation of
to-LOW transition of the clock signal. The flipflop in the flipflop can be considered to have occurred on the
the two cases is referred to as positive edge-triggered edge itself.
and negative edge-triggered, respectively. Any changes
in the input during the time the clock pulse is HIGH (or
LOW) do not have any effect on the output. In case of S Q
edge-triggered flipflop, an edge detector circuit trans-
forms the clock input into a very narrow pulse that is a
Clk Edge
detector
S 1 Q
R Q
Figure 26.18| Edge-triggered R-S flipflop.

Clk
Figure 26.18 shows the clocked R-S flipflop shown in

R 2 Q Fig. 26.16 with the edge detector block incorporated in
the clock circuit. Figure 26.19 (a) and (b) respectively
show the positive edge and negative edge triggered edge
(a) detector circuits.
R Clk Qn+1 26.4 J-K FLIPFLOP

S
0 0 0 Qn
0 0 1 Invalid A J-K flipflop behaves in the same fashion as an R-S
0 1 0 Qn flipflop except for one of the entries in the function
0 1 1 1 table. In case of an R-S flipflop, the input combina-
1 0 0 Qn tion S = R = 1 (in case of flipflop with active HIGH
1 0 1 0 inputs) and the input combination S = R = 0 (in case
1 1 0 Q n of flipflop with active LOW inputs) are prohibited.
1 1 1 Qn In case of J-K flipflop with active HIGH inputs, the
output of the flipflop toggles, that is, it goes to the
(b) other state, for J = K = 1. The output toggles for
J = K = 0 in case of the flipflop having active LOW
inputs. Thus, a J-K flipflop overcomes the problem
of a forbidden input combination of the R-S flip
S Q flop. Figures 26.20(a) and (b), respectively, show the
circuit symbol of level-triggered J-K flipflops with
active HIGH and active LOW inputs along with their
Clk FF function tables. Figure 26.21 shows realization of a
J-K flipflop with an R-S flipflop.
The characteristic tables for a J-K flipflop with
R Q active High J and K inputs and a J-K flipflop with
active LOW J and K inputs are shown in Figs. 26.22(a)
and (b), respectively. The corresponding Karnaugh maps
(c)
are shown in Figs. 26.22(c) for the characteristics table
Figure 26.17| Clocked R-S flipflop with active-LOW shown in Figs. 26.22(a) and 26.22(d) for the character-
inputs. istic table shown in Fig. 26.22(b). The characteristic

26.4 J-K FLIPFLOP 611
Clk
Clk
Clk Clk
Clk
Clk
Clk
Clk
(a) (b)
Figure 26.19| (a) Positive edge-triggered and (b) negative edge-triggered edge detector circuits.
J Q Operation Mode J K Clk Qn+1

SET 1 0 1 1
Clk FF RESET 0 1 1 0
NO CHANGE 0 0 1 Qn
K Q TOGGLE 1 1 1 Qn
(a)
J Q Operation Mode J K Clk Qn+1

SET 0 1 1 1
Clk FF RESET 1 0 1 0
NO CHANGE 1 1 1 Qn
K Q TOGGLE 0 0 1 Qn
(b)
Figure 26.20| J-K flipflop (a) active-HIGH inputs and (b) active-LOW inputs.
equations for Karnaugh maps shown in Figs. 26.22 (c) 26.4.1 J-K FlipFlop with Preset and Clear
and (d) are given in equations below in the same order. Inputs
Qn +1 = J Qn + K Qn (Active HIGH J and K inputs) It is often necessary to clear a flipflop to a logic `0
Qn +1 = J Qn + K Qn (Active LOW J and K inputs) state (Qn = 0) or preset it to a logic `1 state (Qn = 1).

irrespective status of clock, J and K inputs. In a flipflop of

this type, both PRESET and CLEAR inputs should not be
J S Q made active at the same time.
FF
26.4.2 MasterSlave FlipFlop
Whenever the width of the pulse clocking the flipflop

K R Q is greater than the propagation delay of the flipflop,
the change of state at the output is not reliable. In case
of edge-triggered flipflops, this pulse width would be
Figure 26.21| Realization of a J-K flipflop using an the trigger pulse width generated by the edge detector
R-S flipflop. portion of the flipflop and not the pulse width of the
input clock signal. This phenomenon is referred to as
race problem. As the propagation delays are normally
very small, the likelihood of occurrence of race condition
Qn J K Qn+1 Qn J K Qn+1 is reasonably high. One way to get over this problem is
0 0 0 0 0 0 0 1 to use masterslave configuration. Figure 26.24(a) shows
0 0 1 0 0 0 1 1 a masterslave flipflop constructed with two J-K flip
0 1 0 1 0 1 0 0 flops. The first flipflop is called the master flipflop and
0 1 1 1 0 1 1 0 the second is called the slave. The clock to the slave
1 0 0 1 1 0 0 0 flipflop is complement of the clock to the master flip
1 0 1 0 1 0 1 1 flop. When the clock pulse is present, the master flip
1 1 0 1 1 1 0 0 flop is enabled while the slave flipflop is disabled. As a
1 1 1 0 1 1 1 1 result, master flipflop can change state while the slave
flipflop cannot. When the clock goes LOW, the master
(a) (b) flipflop gets disabled while the slave flipflop is enabled.
Therefore, the slave J-K flipflop changes state as per
JK JK the logic states at its J and K inputs. The contents of the
Qn 00 01 11 10 Qn 00 01 11 10
master flipflop are therefore transferred to the slave flip
0 1 1 0 1 1 flop, the master flipflop being disabled can acquire new
inputs without affecting the output. As would be clear
1 1 1 1 1 1 from the description above, a masterslave flipflop is a
pulse-triggered flipflop and not an edge-triggered one.
(c) (d) Figure 26.24(b) shows the truth table of a masterslave
Figure 26.22|(a) Characteristic table of a J-K flipflop
J-K flipflop with active LOW PRESET and CLEAR
inputs, active HIGH J and K inputs. The masterslave
with active-HIGH inputs and (b) with
active-LOW inputs. (c) The K-map solu- configuration has become obsolete. The newer IC tech-
tion of a J-K flipflop with active-HIGH nologies such as 74LS, 74AS, 74ALS, 74HC, 74HCT do
inputs and (d) with active-LOW inputs. not have masterslave flipflops in their series.
26.5 TOGGLE FLIPFLOP (T- FLIP

An example of how this is realized is shown in FLOP)
Fig. 26.23(a). The flipflop is cleared (that is, Qn = 0)
whenever CLEAR input is `0 and PRESET input is `1.
The flipflop is preset to logic `1 state whenever PRESET The output of toggle flipflop, also called T-flipflop,
input is `0 and CLEAR input is `1. Here, the CLEAR and changes state every time it is triggered at its T-input
PRESET inputs are active when LOW. Figure 26.23(b) called the toggle input. That is the output becomes `1 if
shows the circuit symbol of this presettable, clearable it were `0 and `0 if it were `1. Figures 26.25(a) and (b),
clocked J-K flipflop. Figure 26.23(c) shows the function respectively, show the circuit symbols of positive edge-
table of such a flipflop. It is evident from the function triggered and negative edge-triggered T-flipflops along
table that whenever the PRESET input is active, the with their function tables. If we consider the T-input
output goes to `1 state irrespective of status of clock, J as active when HIGH, the characteristic table of such
and K inputs. Similarly, when the flipflop is cleared, that a flipflop is shown in Fig. 26.25(c). If T-input were
is, CLEAR input is active, the output goes to `0 state active when LOW, the characteristic table is shown in

26.5 TOGGLE FLIPFLOP (T- FLIPFLOP) 613
PRESET
J
Q
J Pr Q
Clk
Clk FF
Q
K
K Cl Q
CLEAR
(a) (b)
PR Cl Clk J K Qn+1 Qn+1

0 1 1 0
1 0 0 1
0 0
1 1 1 0 0 Qn Qn
1 1 1 1 0 1 0
1 1 1 0 1 0 1
1 1 1 1 1 Toggle
1 1 0 Qn Qn
(c)
Figure 26.23| J-K flipflop with PRESET and CLEAR inputs.
PR Clr Clk J K Qn+1 Qn+1

0 1 1 0
1 0 0 1
0 0 Unstable
1 1 0 0 Qn Qn
J Q J Q
1 1 1 0 1 0
Master
Clk Clk Slave
FF FF 1 1 0 1 0 1
K Q K Q
1 1 1 1 Toggle
(a) (b)
Figure 26.24| Masterslave flipflop.

Q
T Qn Qn+1
T FF 0 1
1 0
(a)
Q
T Qn Qn+1
T FF 0 1
1 0
(b)
Qn T Qn+1 Qn T Qn+1
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1
(c) (d)
T T
Qn 0 1 Qn 0 1
0 1 0 1
1 1 1 1
(e) (f)
Figure 26.25| (a) Positive edge-triggered toggle flipflop. (b) A negative edge-triggered toggle flipflop.
(c) and (d) Characteristic tables of level-triggered toggle flipflop. (e) and (f) Karnaugh maps
for characteristic tables shown in (c) and (d) respectively.
Figure 26.25(d). The Karnaugh maps for the character- n T-flipflops, where output of one flipflop is connected
istic tables of Figs. 26.25(c) and (d), respectively, are to the T-input of the following flipflop, can be used
shown in Figs. 26.25(e) and (f). The characteristic equa- to divide the input signal frequency by a factor of 2n.
tions as written from Karnaugh maps are given in the Figure 26.26 shows a `divide-by-16 circuit built around
following equations: a cascaded arrangement of four T-flipflops.
Qn +1 = T Qn + T Qn (Active HIGH T-input) 26.5.1 J-K FlipFlop as Toggle FlipFlop

Qn +1 = T Qn + T Qn (Active LOW T-input)
If we recall the function table of a J-K flipflop, we shall
It is obvious from operational principle of T-flipflop that see that when both J and K inputs of the flipflop are
the frequency of signal at Q-output is half of frequency tied to their active level (`1 level if J and K are active
of signal applied at T-input. A cascaded arrangement of when HIGH and `0 level when J and K are active when

26.6 D-FLIPFLOP 615
Q Q Q Q
T FF T FF T FF T FF
Figure 26.26| Cascade arrangement of four T flipflops.
LOW), the flipflop behaves like a Toggle flipflop with symbol and function table of a negative edge-triggered
its clock input serving as the T-input. In fact, J-K flip D-flipflop. When the clock is active, the data bit (0 or
flop can be used to construct any other flipflop. Due to 1) present at the D-input is transferred to the output.
this reason, sometimes it is also referred to as a universal In the D-flipflop of Fig. 26.28(a), the data transfer
flipflop. Figure 26.27 shows use of a J-K flipflop as a from D-input to Q-output occurs on the negative going
T-flipflop. (HIGH-to-LOW) transition of clock input. D-input can
acquire new status when the clock is inactive, which is
`1 the time period between successive HIGH-to-LOW tran-
sitions. The D-flipflop can provide a maximum delay
of one clock period. The characteristic table and the
J Q corresponding Karnaugh map for the D-flipflop of Fig.
26.28(a) are shown in Figs. 26.28(c) and (d), respec-
tively. The characteristic equation is given by
T Clk FF
Qn+1 = D
K Q 26.6.1 J-K FlipFlop as D-FlipFlop
Figure 26.27| J-K flipflop as a T flipflop. Figure 26.29 shows how a J-K flipflop can be used as a
D-FlipFlop. When D-input is logic `1, J and K inputs,
respectively, are logic `1 and `0. According to the func-
26.6 D-FLIPFLOP tion table of J-K flipflop, under these input conditions,
Q-output shall go to logic `1 state when clocked. Also,
when D-input is logic `0, (J) and (K) inputs, respec-
D-flipflop, also called delay flipflop, can be used to tively, are logic `0 and `1. Again, according to func-
provide temporary storage of one bit of information. tion table of J-K flipflop, under these input conditions,
Figures 26.28(a) and (b), respectively, show the circuit Q-output shall go to logic `0 state when clocked. Thus,
D Q D Clk Q
Clk FF 0 0
1 1
(a) (b)
D
Qn D Qn+1 Qn
0 1
0 0 0
0 1
0 1 1
1 0 0 1 1
1 1 1 Qn+1 = D
(c) (d)
Figure 26.28| D-flipflop.

Q input becoming inactive during the entire time period

D J
the ENABLE input is inactive. A D-flipflop should not
be confused with a D-type latch. In a D-flipflop, the
data on D-input is transferred to the Q-output on the
Clk FF
positive or negative going transition of the clock signal
depending upon the flipflop and this logic state is held
at the output till we get next effective clock transition.
K The difference between the two is further illustrated in
Figure 26.29| J-K flipflop as a D-flipflop.
Figs. 26.30(a) and (b) which depict the functioning of a
D-latch and a D-flipflop, respectively.
in both cases, D-input is passed on to the output when
the flipflop is clocked. 26.7 SYNCHRONOUS AND
ASYNCHRONOUS INPUTS
26.6.2 D-Type Latch
In a D-type latch, output Q follows the D-input as long Most flipflops have both synchronous and asynchro-
as the clock input (also called ENABLE input) is HIGH nous inputs. Synchronous inputs are those whose
or LOW depending upon which clock level it responds to. effect on the flipflop output is synchronized with the
When clock goes to the inactive level, the output holds clock input. R, S, J, K and D inputs are synchronous
on to the logic state it was in just prior to ENABLE inputs. Asynchronous inputs are those which operate
Enable
D Q
Enable FF D-input
Q-output
(a)
Clk
D Q
FF D-input
Clk
Q-output
(b)
Figure 26.30| Comparison between a D-type latch and a D-flipflop.

26.8 COUNTERS 617
independently of the synchronous inputs and the input states that it goes through before it repeats the sequence,
clock signal. These are in fact override inputs as their a parameter known as modulus of the counter. In a ripple
status overrides the status of all synchronous inputs and counter, also called an asynchronous counter or a serial
also the clock input. They force the flipflop output to counter, the clock input is applied to only the first flip
go to a predefined state irrespective of the logic status flop, also called input flipflop, in the cascaded arrange-
of synchronous inputs. PRESET and CLEAR inputs ment. The clock input to any subsequent flipflop comes
are examples of asynchronous inputs. When active, from the output of its immediately preceding flipflop. In
the PRESET and CLEAR inputs place the flipflops general, in an arrangement of n flipflops, clock to nth
Q-output in `1 and `0 state, respectively. Usually, these flipflop comes from the output of (n 1)th flipflop for
are active LOW inputs. When it is desired that the flip n > 1. Figure 26.31 shows generalized block schematic
flop functions as per its synchronous inputs status, the arrangement of n-bit binary ripple counter. Also, nth
asynchronous inputs are kept in their inactive state. flipflop will change state only after a delay equal to n
Also, both the asynchronous inputs, if available on a times the propagation delay of one flipflop. The name
given flipflop, are not made active simultaneously. ripple counter comes from the mode in which the clock
information ripples through the counter. It is also called
an asynchronous counter as different flipflops compris-
26.8 COUNTERS ing the counter do not change state in synchronization
with the input clock. In a counter like this, after the
occurrence of each clock input pulse, the counter has
Counters and registers belong to the category of medium to wait for a time period equal to sum of propagation
scale integrated (MSI) sequential logic circuits. They have delays of all flipflops before the next clock pulse can
similar architecture as both counters as well as registers be applied. The propagation delay of each flipflop, of
comprise of a cascaded arrangement of more than one flip course, will depend upon the logic family to which it
flop with or without combinational logic devices. Both con- belongs. Increased propagation delay puts a limit on the
stitute very important building blocks of sequential logic maximum frequency used as clock input to the counter.
and different types of counters and registers available in The maximum clock frequency therefore corresponds to
the integrated circuit (IC) form are used in a wide range of a time period that equals the total propagation delay.
digital systems. While counters are mainly used in counting Often, the two propagation delay times are specified in
applications where these are used either for measuring time the case of flipflops, one for LOW-to-HIGH clock tran-
interval between two unknown time instants or for measur- sition (tpLH) and the other for HIGH-to-LOW clock tran-
ing the frequency of a given signal, registers are primarily sition (tpHL). In such a case, larger of the two should be
used for temporary storage of data present at the output considered for computing the maximum clock frequency.
of a digital circuit before it is fed to another digital circuit.
While counters are described in this section and registers
are discussed in the next section. 26.8.2 Synchronous Counter
In a synchronous counter also known as a parallel

26.8.1 Asynchronous (Ripple) Counter counter, all the flipflops in the counter change state
at the same time in synchronism with the input clock
A counter is a cascaded arrangement of flipflops where signal. The clock signal in this case is simultaneously
output of one flipflop drives the clock input of the fol- applied to the clock inputs of all the flipflops. The
lowing flipflop. The number of flipflops in the cascaded delay involved in this case is equal to the propagation
arrangement depends upon the number of different logic delay of one flipflop only irrespective of the number
J J J J Qn
Q1 Q2 Qn1
Clock
FF1 FF2 FF(n1) FF(n)
K K K K
Figure 26.31| Generalized block schematic of an n-bit ripple counter.

of flipflops used to construct the counter. In other 26.8.4 Binary Ripple Counter Operational Basics
words, the delay is independent of the size of the
counter. Operation of a binary ripple counter can be best
explained with the help of a typical counter of this type.
Figure 26.32(a) shows a four-bit ripple counter imple-
26.8.3 Modulus of a Counter
mented with negative edge-triggered J-K flipflops wired
as toggle flipflops. The outputs of the four flipflops are
The Modulus of a counter is the number of different logic
designated as Q0 (LSB flipflop), Q1, Q2 and Q3 (MSB
states it goes through before it comes back to the initial
flipflop). Figure 26.32(b) shows the waveforms appear-
state to repeat the count sequence. An n-bit counter that
ing at Q0, Q1, Q2 and Q3 outputs as the clock signal goes
counts through all its natural states and does not skip
through successive cycles of trigger pulses.
any of the states has a modulus of 2n. We can see that
such counters have a modulus that is an integral power The four-bit binary ripple counter functions as follows:
of 2, that is, 2, 4, 8 and 16 and so on. These can be modi- Let us assume that all the flipflops are initially cleared to
fied with the help of additional combinational logic to `0 state. On HIGH-to-LOW transition of the first clock
get a modulus less than 2n. In general, the arrangement pulse, Q0 goes from 0 to 1 due to the toggling action. As
of N flipflops can be used to construct any counter with the flipflops used are the negative edge-triggered ones,
a modulus given by 2N1 + 1 modulus 2N. the 0 to 1 transition of Q0 does not trigger flipflop FF1.
J J J J
Q0 Q1 Q2 Q3
Clock
FF0 FF1 FF2 FF3
K K K K
Q0 Q1 Q2 Q3
(a)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Clock-input
Q0 -output
Q1 -output
Q2 -output
Q3 -output
(b)
Figure 26.32| Four-bit binary ripple counter.

26.8 COUNTERS 619
FF1 along with FF2 and FF3 remain in their `0 states. f/2N2, f/2N3, ..., f/2 at the outputs of Nth, (N1)th,
So, on the occurrence of first negative going clock transi- (N2)th, (N3)th, ..., first flipflops.
tion, Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0. On the HIGH-
to-LOW transition of the second clock pulse, Q0 toggles 26.8.5 Binary Ripple Counters with Modulus
again. That is, it goes from `1 to `0. This `1 to `0 tran- Less than 2N
sition at Q0 output triggers FF1 whose output Q1 goes
from `0 to `1. Q2 and Q3 outputs remain unaffected. An N-flipflop binary ripple counter can be modified to
Therefore, immediately after occurrence of second HIGH- have any other modulus less than 2N with the help of simple
to-LOW transition of clock signal, Q0 = 0, Q1 = 1, Q2 = externally connected combinational logic. The steps to be
0, Q3 = 0. On similar lines, we can explain that the logic followed to design any binary ripple counter that starts
status of Q0, Q1, Q2 and Q3 outputs immediately after from 0000 and has a modulus of X are given as follows:
subsequent clock transitions. Logic status of outputs for 1. Determine the minimum number of flipflops N so
the first 16 relevant (HIGH-to-LOW in the present case) that 2N X. Connect these flipflops as a binary
clock signal transitions is summarized in Table 26.1. ripple counter. If 2N = X, then do not go to steps
Thus, we see that the counter goes through sixteen two and three.
distinct states from 0000 to 1111 and then on the occur- 2. Identify the flipflops that will be in logic HIGH
rence of the desired transition of the sixteenth clock state at the count whose decimal equivalent is
pulse, it resets to the original state of 0000 from where it X. Choose a NAND gate with number of inputs
had started. In general, if we had N flipflops, we could equal to number of flipflops that would be in logic
count up to 2N pulses before the counter resets to the HIGH state. As an example, if the objective were
initial state. We can also notice from the Q0, Q1, Q2 to design a MOD-12 counter, then in the corre-
and Q3 waveforms, [as shown in Fig. 26.32(b)] that the sponding count, that is, 1100, two flipflops will
frequencies of Q0, Q1, Q2 and Q3 waveforms are f/2, f/4, be in logic HIGH state. The desired NAND-gate
f/8 and f/16, respectively, where f is the frequency of therefore shall be a two-input gate.
clock input. This implies that a counter of this type can 3. Connect the Q-outputs of the identified flipflops
be used as a divide-by-2N circuit where N is the number to the inputs of the NAND gate and the NAND-
of flipflops in the counter chain. In fact, such a coun- gate output to asynchronous clear inputs of all
ter provides frequency divided outputs of f/2N, f/2N1, flipflops.
Table 26.1| Output logic states for different clock signal transitions for a four-bit binary ripple counter.
Clock Signal Transition Number Q0 Q1 Q2 Q3

After first clock transition 1 0 0 0
After second clock transition 0 1 0 0
After third clock transition 1 1 0 0
After fourth clock transition 0 0 1 0
After fifth clock transition 1 0 1 0
After sixth clock transition 0 1 1 0
After seventh clock transition 1 1 1 0
After eighth clock transition 0 0 0 1
After ninth clock transition 1 0 0 1
After tenth clock transition 0 1 0 1
After eleventh clock transition 1 1 0 1
After twelfth clock transition 0 0 1 1
After thirteenth clock transition 1 0 1 1
After fourteenth clock transition 0 1 1 1
After fifteenth clock transition 1 1 1 1
After sixteenth clock transition 0 0 0 0

26.8.6 Synchronous or Parallel Counters FF3 toggles only with those clock pulses when Q0, Q1
and Q2 are all in logic `1 state. Such logic can be easily
In a synchronous counter, all flipflops in the counter are implemented with AND gates. Figure 26.33(a) shows the
clocked simultaneously in synchronism with clock and schematic arrangement of a four-bit synchronous coun-
as a consequence, all flipflops change state at the same ter. The timing waveforms are shown in Fig. 26.33(b).
time. The propagation delay in this case is independent The diagram is self-explanatory.
of number of flipflops used. A synchronous counter that counts in the reverse
Since different flipflops in a synchronous counter are or downward sequence can be constructed in a similar
clocked at the same time, there needs to be additional manner by using complementary outputs of the flip
logic circuitry to ensure that various flipflops toggle flops to drive J and K inputs of the following flipflops.
at the right time. For instance, if we look at the count
sequence of a four-bit binary counter, we find that flip 26.8.7 UP/DOWN Counters
flop FF0 toggles with every clock pulse, flipflop FF1 tog-
gles only when output of FF0 is in `1 state, flipflop FF2 An UP-counter is the one that counts upwards or in the
toggles only with those clock pulses when the outputs forward direction by one LSB every time it is clocked.
of FF0 and FF1 are both in logic `1 state and flipflop A four-bit binary UP-counter will count as 0000, 0001,
J Q0 J Q1 J Q2 J Q3
FF0 FF1 FF2 FF3
Clk Clk Clk Clk
K Q0 K Q1 K Q2 K Q3
Clock
(a)
Clock
Q0
Q1
Q2
Q3
(b)
Figure 26.33| Four-bit synchronous counter.

26.8 COUNTERS 621
0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, (down mode) output, also called borrow out (Bo), fed
1011, 1100, 1101, 1110, 1111, 0000, 0001, .... A DOWN- back to the PL input, it works like a MOD-X counter.
counter counts in the reverse direction or downwards
by one LSB every time it is clocked. The four-bit
26.8.10 Decoding a Counter
binary DOWN-counter will count as 0000, 1111, 1110,
1101, 1100, 1011, 1010, 1001, 1000, 0111, 0110, 0101,
The output state of a counter at any time instant, as it
0100, 0011, 0010, 0001, 0000, 1111, .... Some counter
is being clocked, is in the form of a sequence of binary
ICs having separate clock inputs for UP and DOWN
digits. For a large number of applications, it is impor-
count while others have a single clock input and an UP/
tant to detect or decode different states of the counter
DOWN control pin. The logic status of this control pin
whose number equals the modulus of the counter. One
decides the counting mode.
typical application could be a need to initiate or trigger
some action after the counter reaches a specific state.
26.8.8 Decade and BCD Counters The decoding network therefore is going to be a logic
circuit that takes its inputs from the outputs of different
A decade counter is the one that goes through ten flipflops constituting the counter and then makes use
unique combinations of outputs and then resets as the of that data to generate outputs equal to modulus or
clock proceeds further. Since it is a MOD-10 counter, it MOD-number of the counter.
can be constructed with a minimum of four flipflops. Depending upon the logic status of decoded output,
A four-bit counter would have 16 states. By skipping there are two basic types of decoding, namely, active-
any of the six states by using some kind of feedback or HIGH decoding and active-LOW decoding. In case of the
some kind of additional logic, we can convert a normal former, the decoder outputs are normally LOW and for
four-bit binary counter into a decade counter. A decade a given counter state, the corresponding decoder output
counter does not necessarily count from 0000 to 1001. It goes to logic HIGH state. In case of active-LOW decod-
could even count as 0000, 0001, 0010, 0101, 0110, 1001, ing, the decoder outputs are normally HIGH and the
1010, 1100, 1101, 1111, 0000, .... In this count sequence, decoded output representing the counter state goes to
we have skipped 0011, 0100, 0111, 1000, 1011 and 1110. logic LOW state.
A BCD-counter is a special case of a decade counter in
which the counter counts from (0000) to (1001) and then
resets. The output weights of flipflops in these counters 26.8.11 Cascading Counters
are in accordance with 8421-code.
A cascade arrangement allows us to build counters with
higher modulus than is possible with a single stage. The
26.8.9 Presettable Counters terminal count outputs allow more than one counters
to be connected in a cascade arrangement. In the fol-
Presettable counters are those that can be preset to any lowing paragraphs, we shall examine some such cascade
starting count either asynchronously (independent of the arrangements in case of binary and BCD counters.
clock signal) or synchronously (with the active transition
of the clock signal). The presetting operation is achieved 26.8.11.1 Cascading Binary Counters
with the help of PRESET and CLEAR (or MASTER
RESET) inputs available on the flipflops. Presetting In order to construct a multistage UP-counter, all coun-
operation is also known as preloading or simply load- ter stages are connected in the count-UP mode. The
ing operation. Presettable counters can be UP-counters, clock is applied to the clock input of lower order counter,
DOWN-counters or UP/DOWN counters. Additional the terminal count up (TCU) also called carry out (Co)
inputs/outputs available on Presettable UP/DOWN of this counter is applied to clock input of next higher
counter usually include PRESET inputs from where any counter stage and the process continues. In case it is
desired count can be loaded, parallel load (PL) input, desired to build a multistage DOWN counter, all coun-
which when active allows the PRESET inputs to be ters are wired as DOWN counters, the clock is applied
loaded onto the counter outputs and terminal count to clock input of lower order counter, the terminal count
(TC) outputs which become active when the counter down (TCD) also called borrow out (Bo) of the lower
reaches the terminal count. Presettable counters can be order counter is applied to clock input of next-higher
wired as counters with modulus less than 2N without counter stage. The process continues in the same fashion
the need for any additional logic circuitry. When a pre- with TCD output of second stage feeding clock input of
settable counter is preset with a binary number whose third stage and so on. The modulus of multistage coun-
decimal equivalent is some number X and if this counter ter arrangement equals product of modulus of individual
is wired as a DOWN counter with its terminal count stages.

26.8.11.2 Cascading BCD Counters 26.9 SHIFT REGISTER

BCD counters are used when the application involves
counting of pulses and the result of counting is to be A shift register is a digital device used for storage
displayed in decimal. A single stage BCD counter counts and transfer of data. The data to be stored could
from 0000 (decimal equivalent `0) to 1001 (decimal be the data appearing at the output of an encoding
equivalent `9) and thus is capable of counting up to a matrix before it is fed to the main digital system for
maximum of nine pulses. Output in a BCD counter is in processing or it might be the data present at the
binary coded decimal (BCD) form. BCD output needs output of a microprocessor before it is fed to the driver
to be decoded appropriately before it can be displayed. circuitry of the output devices. The shift register thus
Decoding a counter has been discussed in the previous forms an important link between the main digital
section. Coming back to the question of counting pulses, system and the input/output channels. The shift
more than one BCD counter stages need to be used in a registers can also be configured to construct some
cascade arrangement in order to be able to count up to special types of counters that can be used to perform
a larger number of pulses. The number of BCD counter a number of arithmetic operations like subtraction,
stages to be used equals the number of decimal digits in multiplication, division, complementation etc. The
the maximum number of pulses we want to count up to. basic building block in all shift registers is the flip
A maximum count of 9999 or 3843, both would require flop, mainly a D-type flipflop.
a four-stage BCD counter arrangement with each stage The storage capacity of a shift register equals the total
representing one decimal digit. number of bits of digital data it can store, which in turn
Figure 26.34 shows a cascade arrangement of four depends upon the number of flipflops used to construct
BCD counter stages. The arrangement works as follows. the shift register. Since each flipflop can store one bit of
Initially, all four counters are in all 0s state. The counter data, the storage capacity of the shift register equals the
representing the decimal digit of ones place is clocked number of flipflops used. As an example, internal archi-
by the pulsed signal that needs to be counted. The suc- tecture of an eight-bit shift register shall have a cascade
cessive flipflops are clocked by the MSB of the immedi- arrangement of eight flipflops.
ately previous counter stage. The first nine pulses take Based on the method used to load data onto and read
the ones place counter to 1001. The tenth pulse resets data from shift registers, they are classified as follows:
it to 0000 and 1-to-0 transition at MSB of ones place
counter clocks tens place counter. Tens place counter 1. Serial-in serial-out (SISO) shift registers
gets clocked on every tenth input clock pulse. On the 2. Serial-in parallel-out (SIPO) shift registers
hundredth clock pulse, the MSB of tens counter makes 3. Parallel-in serial-out (PISO) shift registers
a 1-to-0 transition which clocks the 100s place counter. 4. Parallel-in parallel-out (PIPO) shift registers
This counter gets clocked on every successive hundredth Figure 26.35 shows circuit representation of these four
input clock pulse. On thousandth input clock pulse, the types of shift registers.
MSB of 100s counter makes 1-to-0 transition for the
first time and clocks the 1000s place counter. This coun-
ter is clocked thereafter on every successive thousandth 26.9.1 Serial-In Serial-Out (SISO) Shift Register
input clock pulse. With this background, we can always
tell the output state of the cascade arrangement. For Figure 26.36 shows the basic four-bit SISO shift register
example, immediately after 7364th input clock pulse, the implemented using D-type flipflops. The circuit func-
state of 1000s, 100s, 10s and 1s BCD counters would, tions as follows: A reset applied to the CLEAR input of
respectively, be 0111, 0011, 0110 and 0100. all the flipflops resets their Q-outputs to 0s.
1000s Counter 100s Counter 10s Counter 1s Counter
BCD Clk BCD Clk BCD Clk BCD Clk Input

Counter Counter Counter Counter
D C B A D C B A D C B A D C B A
Figure 26.34| Cascading BCD counters.

26.9 SHIFT REGISTER 623
In In
Serial-in Out Serial-in
Clock Clock
Serial-out Parallel-out
Out
In In
Parallel-in Out Parallel-in

Clock Clock
Serial-out Parallel-out
Out
Figure 26.35| Circuit representation of shift registers.
Data in
D QA D QB D QC D QD
Data out
Clock
Clk Clk Clk Clk
CL CL CL CL
CLEAR
Figure 26.36| Serial-in serial-out shift register.
Clock
Clear
1 0 0 1
Data input
QA-output
QB-output
QC-output
QD-output
Figure 26.37| Timing waveforms for the shift register shown in Fig. 26.36.
Refer to the timing waveforms shown in Fig. 26.37. The flipflops shown respond to the LOW-to-HIGH
The waveforms shown include the clock pulse train, the transition of the clock pulses as indicated by their logic
waveform representing the data to be loaded onto the symbols. During the first clock transition, QA output
shift register and the Q-outputs of different flipflops. goes from logic `0 to logic `1. The outputs of other three

flipflops remain in logic `0 states as their D-inputs were IC 74166, an eight-bit parallel/serial-in, serial out shift
in logic `0 state at the time of clock transition. During register belonging to TTL family of devices.
the second clock transition, QA-output goes from logic The parallel-in or serial-in modes are controlled by
`1 to logic `0 and QB-output goes from logic `0 to logic SHIFT/LOAD input. When the SHIFT/LOAD input is
`1 again in accordance with logic status of D-inputs at held in logic HIGH state, the serial data input AND
the time of relevant clock transition. gates are enabled and the circuit behaves like a SISO
Thus, we have seen that a logic `1 that was present at shift register. When the SHIFT/LOAD input is held
the data input prior to the occurrence of first clock transi- in logic LOW state, parallel data input AND gates are
tion has reached the QB-output at the end of two clock enabled and data is loaded parallel in synchronism with
transitions. This bit will reach QD-output at the end of the next clock pulse. Clocking is accomplished on the
four clock transitions. In general, in a four-bit shift register LOW-to-HIGH transition of the clock pulse via a two-
of the type shown in Fig. 26.36, a data bit present at the input NOR gate. Holding one of the inputs of the NOR
data input terminal at the time of nth clock transition gate in logic HIGH state inhibits the clock applied to
reaches the QD-output at the end of (n + 4)th clock the other input. Holding an input in logic LOW state
transition. During the fifth and subsequent clock transi- enables the clock applied to the other input. An active
tions, data bits continue to shift to the right and at the LOW CLEAR input overrides all the inputs including
end of eighth clock transition, the shift register is again the clock and resets all flipflops to logic `0 state.
reset to all 0s. Thus, in a four-bit SISO shift register, it
takes four clock cycles to load the data bits and another
26.9.4 Parallel-In Parallel-Out (PIPO) Shift
four cycles to read the data bits out of the register.
Register
26.9.2 Serial-In Parallel-Out Shift (SIPO) The hardware of a PIPO shift register is similar to that
Register of a parallel-in, serial-out shift register. If in a parallel-
in, serial-out shift register, outputs of different flipflops
An SIPO shift register is architecturally identical to a are brought out, it becomes a parallel-in, parallel-out
SISO shift register except that in case of former, all flip shift register. In fact, the logic diagram of a PIPO shift
flop outputs are also brought out on the IC terminals. registers is similar to that of a PISO shift register. As
Figure 26.38 shows the logic diagram of a typical serial- an example, IC 74199 is an eight-bit parallel-in, parallel
in parallel out shift register. In fact, the logic diagram out shift register. Figure 26.40 shows its logic diagram.
shown in Fig. 26.38 is that of IC 74164, a popular eight- We can see that the logic diagram of IC 74199 is similar
bit SIPO shift register. to that of IC 74166 mentioned in the previous section
except that in case of former, the flipflop outputs have
been brought out on the IC terminals.
26.9.3 Parallel-In Serial-Out (PISO) Shift
Register
26.9.5 Bidirectional Shift Register
We shall explain the operation of a PISO shift register
with the help of logic diagram of a practical device avail- A bidirectional shift register allows shifting of data
able in IC form. Figure 26.39 shows the logic diagram either to the left or to the right. This is made possible
of one such shift register. The logic diagram is that of with inclusion of some gating logic having a control
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
A
B D Q0 D Q1 D Q2 D Q3 D Q4 D Q5 D Q6 D Q7
CP CP CP CP CP CP CP CP
CD CD CD CD CD CD CD CD
Clock
MR
Figure 26.38| Logic diagram of IC 74164.

26.9 SHIFT REGISTER 625
(9)
CLEAR
Serial Input
(1)
SHIFT/LOAD (15)
A
(2) R S
Cl CK
QA
(3)
B
R S
CK
Cl
QB
(4)
C
R S
CK
Cl
QC
(5)
D
R S
CK
Cl
QD
(10)
E
R S
CK
Cl
QE
(11)
F
R S
CK
Cl
QF
(12)
G
R S
CK
Cl
QG
(14)
H
(7) R S
CK
Clock Cl
(13)
Clock INHIBIT (6) QH
Figure 26.39| Logic diagram of 74166.
input. The control input allows shifting of data either sections. That is, it has serial/parallel data input and
to the left or to the right depending upon its logic output capability, which means that it can function as
status. SISO, SIPO, PISO and PIPO shift registers.
IC 74194 is a common four-bit bidirectional universal
26.9.6 Universal Shift Register shift register. Figure 26.41 shows the logic diagram of IC
74194. The device offers four modes of operation, namely,
A universal shift register can be made to function as (1) Inhibit clock, (2) shift right, (3) shift left and (4) par-
any of the four types of registers discussed in previous allel load. The clocking of the device is inhibited when

(13)
Clock (11)
Clock INHIBIT
Serial inputs JK (2)
(1)
SHIFT/LOAD (23)
A (3)
R S
Cl CK
(4)
QA
(5)
B
R S
Cl CK
(6)
QB
(7)
C
R S
Cl CK
(8)
QC
(9)
D
R S
Cl CK
(10)
QD
(16)
E
R S
CK
Cl
(15)
QE
(18)
F
R S
Cl CK
(17)
QF
(20)
G
R S
CK
Cl
(19)
QG
(22)
H
(14) R S (21)
CLEAR Cl CK
QH
Figure 26.40| Logic diagram of IC74199.
both the mode control inputs S1 and S0 are in logic LOW is also accomplished synchronously with LOW-to-HIGH
state. Shift right and shift left operations are accom- clock transitions by applying four bits of data and
plished synchronously with LOW-to-HIGH transition of then driving the mode control inputs S1 and S0 to logic
the clock with S1 LOW, S0 HIGH (for shift right) and S1 HIGH state. Data is loaded into corresponding flipflops
HIGH and S0 LOW (for shift left) respectively. Serial data and appears at the outputs with LOW-to-HIGH clock
is entered in case of shift right and shift left operations at transition. Serial data flow is inhibited during parallel
the corresponding data input terminals. Parallel loading loading.

26.10 SHIFT REGISTER COUNTERS 627
Shift
right Parallel inputs Shift
serial A B C D left
input (2) (3) (4) (5) (6) (7) serial
(9) input
S0
Mode
control (10)
S1
(11)
Clock
CLEAR
(1)
R R R R R R R R
Clk Clk Clk Clk
S Q S Q S Q S Q
(15) (14) (13) (12)

QA QB QC QD
Parallel outputs
Figure 26.41| Logic diagram of IC 74194.
26.10 SHIFT REGISTER COUNTERS are being used to construct the shift register, the ring
counter can be constructed by feeding back Q-output
of the output flipflop back to the D-input of the input
We have seen that both counters and shift registers are flipflop. In case J-K flipflops are being used, Q-output
some kinds of cascade arrangements of flipflops. A shift and Q outputs of the output flipflop, respectively, are
register unlike a counter has no specified sequence of fed back to the J and K inputs of the input flipflop.
states. However, if the serial output of the shift reg- Figure 26.42 shows logic diagram of the four-bit ring
ister is fed back to the serial input, we do get a cir- counter.
cuit that exhibits a specified sequence of states. The Ring counters of this type find wide application in the
resulting circuits are known as shift register counters. control section of microprocessor based systems where
Depending upon nature of feedback, we have two types one event should follow the other. The timing waveforms
of shift register counters, namely, ring counter and for the circulating register shown in Fig. 26.42 is depicted
shift counter also called Johnson counter. These shift in Fig. 26.43 which further illustrate their utility as a
register counters are briefly described in the following control element in a digital system to generate control
sections. pulses that must occur one after the other sequentially.
26.10.1 Ring Counter 26.10.2 Shift Counter
A ring counter also rferred to as a circulating register is A shift counter on the other hand is constructed by
obtained from a shift register by directly feeding back having an inverse feedback in a shift register. For
the true output of the output flipflop to the data input instance, if we connect Q-output of the output flipflop
terminal of the input flipflop. In case, D-type flipflops back to the K-input of the input flipflop and Q output

D Q0 D Q1 D Q2 D Q3
FF0 FF1 FF2 FF3

CK CK CK CK
Q0 Q1 Q2 Q3
Figure 26.42| Four-bit ring counter.
Clock
Q0-output
Q1-output
Q2-output
Q3-output
Figure 26.43| Timing waveforms of the four-bit ring counter.
J Q0 J Q1 J Q2 J Q3
Clock FF0 FF1 FF2 FF3

CK CK CK CK
K Q0 K Q1 K Q2 K Q3
Figure 26.44| Four-bit shift counter.
of the output flipflop to the J-input of the input flip Let us assume that the counter is initially reset to all
flop in a serial shift register, the result is a shift coun- 0s. With the first clock cycle, the outputs will become
ter also called a Johnson counter. If the shift register 0001. With the second, third and fourth clock cycles, the
employs D-flipflops, Q output of output flipflop is fed outputs will, respectively, be 0011, 0111 and 1111. The
back to D-input of input flipflop. If R-S flipflops are fifth clock cycle will change the counter output to 1110.
used, Q-output goes to the R input and the Q output is The sixth, seventh and eighth clock pulses successively
connected to the S-input. Figure 26.44 shows the logic change the outputs to 1100, 1000 and 0000. Thus, one
diagram of basic four-bit shift counter. count cycle is completed in eight cycles. Figure 26.45

SOLVED EXAMPLES 629
Clock-input
Q -output
0
Q -output
1
Q -output
2
Q -output
3
Figure 26.45| Timing waveform of the shift counter.
shows the timing waveforms. Different output waveforms shift counter behaves as a divide-by-8 circuit. In general,
are identical except for the fact that they are shifted shift counter comprising of n flipflops acts as divide by
from the immediately preceding one by one clock cycle. 2n circuit. Shift counters can be used very conveniently
Also, the time period of each of these waveforms is eight to construct counters having a modulus other than inte-
times the period of the clock waveform. That is, this gral power of two.
IMPORTANT FORMULAS
1. Retriggerable monoshot: Output pulse width of is 4. Characteristic equation (R-S flipflop): Qn +1 = S + RQn
(n 1)Tt + T where n is the number of trigger Qn +1 = S + RQn and S + R = 1 (active LOW inputs)
pulses Tt is the time period of trigger pulses, T is and Qn +1 = S + R Qn and SR = 0 (active HIGH
the output pulse width for a single trigger pulse. inputs).
2. IC timer 555 based astable multivibrator: Time 5. Characteristic equation (J-K flipflop): Qn +1 = J Qn + K Qn
period is Qn +1 = J Qn + K Qn (active HIGH J and K inputs) and
T = 0.69(R1 + 2R2)C Qn +1 = J Qn + K Qn (active LOW J and K inputs)
where R1 is the charging path resistance, R2 is 6. Characteristic equation (T flipflop): Qn +1 = T Qn + T Qn

the discharge path resistance and C is the n +1 = T Qn + T Qn (active HIGH T-input) and Qn +1 = T Qn + T Qn
Q
capacitance. Qn +1 = T Qn + T Qn (active LOW T-input).
3. IC timer 555 based monostable multivibrator Time
period is T = 1.1RC, where R is the charging path 7. Characteristic equation (D flipflop): Qn+1 = D.
resistance, C is the capacitance. 8. Modulus of a shift counter: 2n where `n is number
of flipflops.
SOLVED EXAMPLES

1. In a 555 timer based astable multivibrator, the (a) 6.66 kHz (b) 13.33 kHz
charging resistance is twice the discharge path (c) 10 kHz (d) None of these
resistance. If the LOW-time of the output pulse
waveform is 50 s; the frequency of the output Solution. LOW-time is proportional to prod-
waveform would be uct of discharge path resistance and capacitance.

HIGH-time is proportional to product of charg- Solution. An R-S flipflop wired in this fashion
ing resistance and capacitance. Therefore, HIGH- behaves like a toggle flipflop and hence the answer.
time of the output waveform will also be twice Ans. (b)
the LOW-time. Therefore, the time period of the
output waveform is 150 s. Frequency is
6. Identify the flipflop whose function table is given
1
f= = 6.66 kHz
150 106 PR Clr Clk J K Qn+1 Qn+1
Ans. (a)
1 0 1 0
2. In a 555 timer based monostable multivibrator, the
trigger terminal is driven by a symmetrical 10 kHz 0 1 0 1

pulsed waveform. The expected output pulse width
as per chosen values of R and C is 150 s. The fre-
1 1 Unstable
quency of output waveform would be 0 0 0 1 1 0
(a) 20 kHz (b) 10 KHz 0 0 1 0 0 1
(c) 5 kHz (d) None of these
0 0 1 1 Qn Qn
Solution. The IC timer 555 is triggered on HIGH- 0 0 0 0 Toggle
to-LOW edges of the trigger waveform. Successive
HIGH-to-LOW edges in this case are separated by 100 (a) P
ositive edge-triggered J-K flipflop with
s. As a result of this, the IC timer will be triggered active-HIGH J and K inputs and active-LOW
only on alternate edges as the expected output pulse PRESET and CLEAR inputs
width is 150 s. The frequency of the output wave- (b) Positive edge-triggered J-K flipflop with
form will therefore be half of the trigger frequency. active-HIGH J and K inputs and active-HIGH
Ans. (c) PRESET and CLEAR inputs
3. J and K inputs of a negative edge-triggered flip (c) Positive edge-triggered J-K flipflop with
flop are tied to logic `1 state. If the flipflop were active-LOW J and K inputs and active-HIGH
clocked by a 100 kHz waveform, the Q-output will PRESET and CLEAR inputs
(d) Positive edge-triggered J-K flipflop with
(a)always be in logic `1 state active-LOW J and K inputs and active-LOW
(b)be a 50 kHz waveform PRESET and CLEAR inputs
(c) be a 100 kHz waveform
(d) be a 200 kHz waveform Solution. The first three entries of the function
table indicate that the J-K flipflop has active
Solution. The flipflop in this case works like a HIGH PRESET and CLEAR inputs. Referring to
toggle flipflop, which is basically a divide-by-2 cir- fourth and fifth entries of the function table, it has
cuit. Therefore, frequency of Q-output will be 50 kHz. active LOW J and K inputs. The seventh row of the
Ans. (b) function table confirms this. The output responds
4.There is a negative edge-triggered R-S flipflop to positive LOW-to-HIGH edges of the clock input.
having active-LOW R and S inputs and active- Thus, the flipflop represented by the given func-
HIGH outputs. Identify the forbidden input entry. tion table is a presettable, clearable, positive edge-
triggered flipflop with active HIGH PRESET,
(a) R = 0, S = 0 (b) R = 1, S = 1 CLEAR and active-LOW J and K inputs.
(c) R = 0, S = 1 (d) R = 1, S = 0 Ans. (c)
Solution. The forbidden input is the one when 7. A negative edge-triggered presettable clearable J-K
both R and S inputs are active simultaneously. flipflop with active LOW J and K inputs, active
Since the flipflop has active LOW inputs, the LOW PRESET and CLEAR inputs and active
input R = 0, S = 0 will be forbidden. HIGH outputs has the following inputs at a cer-
Ans. (a) tain time instant: J = 1, K = 0, PRESET = 0,
5. In a positive edge-triggered clocked R-S flipflop, CLEAR = 1. What would be the logic status of
Q-output is tied to R-input and Q -output is tied output when clocked?
to S-input. If the clock frequency is f, the Q-output
(a) 0
frequency will be
(b) 1
(a) f (b) f/2 (c) Indeterminate from given data
(c) 2f (d) None of these (d) Can be either `0 or `1

SOLVED EXAMPLES 631
Solution. Since the PRESET input is active and 11. A shift counter comprising of a cascaded arrange-
CLEAR input is inactive, Q-output will always ment of five flipflops with inverse feedback from
be active irrespective of logic status of J and K output of MSB flipflop to input of LSB flipflop
inputs. The output in this case will be preset to is a
logic `1.
(a) Divide-by-32 counter
Ans. (b)
(b) Divide-by-10 counter
8. One of the following is not a synchronous input (c) Divide-by-5 counter
with reference to flipflops. (d) Five-bit shift register
(a) J-input in a J-K flipflop
Solution. A shift counter comprising of n flipflops
(b) R-input in an R-S flipflop
has a modulus of 2n.
(c) PRESET input in a J-K flipflop
Ans. (b)
(d) D-input in a D-flipflop
12. A binary ripple counter is to be constructed
Solution. J, K, R, S and D are synchronous using J-K flipflops with each flip having a
inputs since their effect on the output is synchro- propagation delay of 12 ns. The largest modulus
nized with clock input. PRESET and CLEAR are counter that can be constructed using these flip
asynchronous inputs as they operate independently flops and still operate up to a clock frequency of
of the synchronous inputs and clock. 10 MHz is
Ans. (c)
(a) MOD-16 (b) MOD-64
9. For one of the following conditions, clocked J-K (c) MOD-256 (d) MOD-8
flipflop can be used as a divide-by-2 circuit when
the input is applied at clock input. Solution. If the counter were to work up to
a clock frequency of 10 MHz; maximum accept-
(a) J = K = 1 and flipflop has active HIGH inputs
able propagation delay should be less than 100 ns.
(b) J = K = 0 and flipflop has active HIGH inputs
Propagation delay of each flipflop is 12 ns. Since
(c) J = K = 1 and flipflop has active LOW inputs
it is a ripple counter; total propagation delay is
(d) J = K = 1 and flipflop should be a negative
sum of propagation delays of individual flipflops.
edge-triggered one
Therefore, the maximum number of acceptable
flipflops is 8. Therefore, the largest modulus pos-
Solution. A toggle flipflop is a divide-by-2 cir-
sible with this configuration is 28 = 256.
cuit. A J-K flipflop functions like a toggle flipflop
when both J and K inputs are made active. Ans. (c)
Ans. (a) 13. A 10 kHz clock signal having a duty cycle of 25%
10. We have two negative edge-triggered J-K flipflops is used to clock a three-bit binary ripple counter.
with active LOW inputs. J and K inputs of both What will be the frequency and duty cycle of true
the flipflops are tied to logic `0. The Q-output of output of the MSB flipflop?
first flipflop feeds the clock input of second flip (a) 1.25 kHz, 25% (c) 3.33 kHz, 25%
flop. What will be the logic status of Q1 and Q2 (d) 3.33 kHz, 50% (d) 1.25 kHz, 50%
at the end of five cycles if the two flipflops were
cleared to logic `0 before start? Solution. A three-bit binary ripple counter
(a) Q1 = 0, Q2 = 0 (b) Q1 = 0, Q2 = 1 is a divide-by-8 circuit. The duty cycle of the
(c) Q1 = 1, Q2 = 0 (d) Q1 = 1, Q2 = 1 waveforms at the true outputs of various flip
flops is 50% irrespective of the duty cycle of the
Solution. Both flipflops are wired as toggle flip input clock signal. The flipflops toggle on the
flops. The output of the first feeds the clock input edge transitions of the clock signal with LSB
of the second. Status of Q1-output and Q2-output flipflop toggling on every relevant edge of the
at the end of successive cycles will be as follows: clock signal, second MSB flipflop toggling on
1. First clock cycle: Q1 = 1, Q2 = 0 every relevant edge of the waveform appearing
2. Second clock cycle: Q1 = 0, Q2 = 1 at true output of LSB flipflop and MSB flip
3. Third clock cycle: Q1 = 1, Q2 = 1 flop toggling on every relevant edge of wave-
4. Fourth clock cycle: Q1 = 0, Q2 = 0 form appearing at true output of second MSB
5. Fifth clock cycle: Q1 = 1, Q2 = 0 flipflop.
Ans. (c) Ans. (d)

14. A counter that has a modulus of 64 should use a (a) 3(b) 19

minimum of (c) 35 (d) Indeterminate from given information
(a) Six flipflops (b) Six J-K flipflops
1
(c) Six D-flipflops (d) 64 flipflops
J J J J
Solution. If n was the number of flipflops, then Q0 Q1 Q2 Q3
Clock
the maximum modulus can be 2n. Also, the flip FF0 FF1 FF2 FF3
flops need not necessarily be a J-K or D-flipflop. K K K K
Ans. (a)
15. A four-bit binary ripple counter of the type shown Q0 Q1 Q2 Q3
in the following figure is initially in (0000) state
before the clock input is applied to the counter. Solution. It is not possible to determine the
The clock pulses are applied to the counter at some number of clock edges as it could have been 3, 19,
time instant t1 and then again removed sometimes 35, 51, 67, 83, ... since there is no means of finding
later at another time instant t2. The counter is out whether the counter has recycled or not from
observed to read 0011. How many negative going the given data. Remember that this counter would
clock transitions have occurred during the time the come back to 0000 state after every 16 clock pulses.
clock was active at the counter input? Ans. (d)
1. How many stable states does a flipflop have? 3. A Schmitt NAND gate is used as an inverter and
the two trip points are 1.5 V and 2.7 V. If the
Solution. A flipflop is nothing but a bistable output is initially HIGH, it will go to LOW state
multivibrator, which has two stable states. Hence, for input voltage greater than X (in volts). Find X
the answer is 2. in this case.
Ans. (2)
Solution. If the output is initially HIGH, the input
2. An inverter is wired between J and K inputs of
would be initially LOW. The output will go to LOW
the J-K flipflop and J-input is treated as the
state only when input exceeds the upper point, that
input to the flipflop. In that case, what will be
is, 2.7 V. The output will go to HIGH state again
the logic status of the true output when clocked
when the input voltage falls below the lower trip
for J = 1?
point, that is, 1.5 V. Hence, the answer is 2.7 V.
Ans. (2.7)
Solution. In this case, the flipflop becomes a
D-flipflop and in the case of D-flipflop, D-input 4. The following figures (a) and (b), respectively,
is passed onto the true output true output when show the circuit symbol and incomplete function
clocked. Therefore output = `1'. table of a D-flipflop. Fill in the missing places
Ans. (1) marked as (i), (ii), (iii), and (iv).
D Pr Q
PR Cl Clk D Q Q
(i) 1 1 0
Clk FF
1 0 0 1
0 (ii) Unstable
Cl Q 1 (iii) 1 1 0
1 1 0 0 (iv)
(a) (b)

SOLVED EXAMPLES 633
Solution. Referring to the first row of function The time period of output waveform is
table, the Q-output is logic `1 irrespective D and
s = 200 ms
1
5 103
clock inputs. This is possible only when CLEAR
input is inactive and PRESET input is active.
Therefore, the duty cycle of output waveform is
Now PRESET and CLEAR inputs are active
when LOW. Therefore, (i) should be a logic `0. 110 106
= 0.55 Ans. (0.55)
Referring to the third row of the function table, the 200 106
output is shown as unstable irrespective of D and 6. Refer to the circuit symbol of the flipflop shown in
clock inputs. This is the case when both PRESET the following figure. What will be the logic status
and CLEAR inputs are active. Therefore, (ii) is of the Q-output on the rising edge of the clock
logic `0. Referring to fourth row, D-input is being pulse for Pr = Cl = 0, J = 0 and K = 1.
passed on to Q-output when clock goes HIGH.
Therefore both PRESET and CLEAR inputs
should be inactive. As a result, (iii) is a logic `1.
Referring to the fifth row, (iv) should be a logic `1
J Pr Q
for obvious reasons.
Ans. (0, 0, 1, 1)
5. Refer to the monostable multivibrator circuit Clk FF
shown in the following figure. Trigger terminal
(pin-2 of the IC) is driven by a symmetrical pulsed
waveform of 10 kHz. Determine the duty cycle of K Cl Q
the output waveform.
VCC
10 kW
Solution. Refer to the figure showing the circuit
symbol of the flipflop. As is evident from the
4,8 figure, the symbol represents a LOW-to-HIGH edge
6,7 Output
3 triggered J-K flipflop with active HIGH PRESET
Trigger and CLEAR inputs, active LOW J and K inputs
input 2 555 and active HIGH outputs. Thus, the answer is 1.
Ans. (1)
0.01 5 1 7. What is least modulus a four-bit binary counter
F 0.01 can be configured for?
F
Solution. In general, the arrangement of N flip
flops can be used to construct any counter with a
modulus given by
Solution
The time period between two successive leading or (2N1 + 1) Modulus 2N
trailing edges = 100s. Here, N = 4. Therefore, the least modulus is
The expected pulse width of monoshot output = 23 + 1 = 9
1.1RC = 1.1 104 108 = 110s. Ans. (9)
The trigger waveform is a symmetrical one; it has
HIGH and LOW time periods of 50 s each. Since 8. Determine the maximum usable clock frequency in
the LOW-state time period of the trigger waveform MHz of a Modulo-7 binary ripple counter if the
is less than the expected output pulse width, it propagation delay specifications of the flipflops
can successfully trigger the monoshot on its trail- used are tpLH = 20 ns, tpHL = 25 ns.
ing edges. Solution. The number of flipflops = 3 as 23 =
However, since the time period between two succes- 8 and 8 is the smallest integer that is equal to or
sive trailing edges is 100 s and the expected output greater than 7 and is also an integer power of 2.
pulse width is 110 s, only alternate trailing edges
of trigger waveform shall trigger the monoshot. The total propagation delay = 3 25 = 75 ns (higher
The frequency of output waveform is of the two propagation delays is taken).
10 103 The maximum usable clock frequency = 13.33 MHz.
Hz = 5 kHz Ans. (13.33)
2

9. It is desired to design a binary ripple counter capable 10. Refer to binary ripple counter shown in the fol-
of counting the number of items passing on a con- lowing figure. Determine the frequency in kHz of
veyor belt. Each time an item passes a given point, a flipflop Q3-output.
pulse is generated that can be used as a clock input. If
the maximum number of items to be counted is 6000, Solution. The counter counts in the natural
determine the number of flipflops required. sequence from 0000 to 1011. The moment the coun-
Solution. The counter is to be able to count a max- ter goes to 1100, NAND-output goes to logic `0
imum of 6000 items. An N-flipflop would be able to state and immediately clears the counter to 0000
count up to a maximum of 2N 1 counts. On (2N) state. Thus, the counter is not able to stay in 1100
th clock pulse, it will get reset to all 0s. Now, 2N state. It has only 12 stable states from 0000 to
1 should be greater than or equal to 6000. That is, 1011.
2N 1 6000 or 2N 6001 Therefore, the modulus of counter = 12.

This gives Now, Q3-output is the input clock frequency divided
by 12. Therefore, the frequency of Q3-output wave-
log 6001 3.778
N 12.55 form is
log 2 0.3010
The smallest integer that satisfies this condition 1.2 106
is 13. Therefore, minimum number of flipflops = 100 kHz
12
required = 13.
Ans. (13) Ans. (100)
1.2MHz
J Q0 J Q1 J Q2 J Q3
FF0 FF1 FF2 FF3
Clk Clk Clk Clk
K Cl K Cl K Cl K Cl
PRACTICE EXERCISE
1. A logic circuit that may give a pulsed waveform at 2. A decade counter is also referred to as
the output for a sinusoidal input is the (a) BCD counter (b) BCD-Decade counter
(a) Schmitt trigger circuit (c) Modulo-10 counter (d) None of these
(1 Mark)
(b) Bistable multivibrator 3. PRESET and CLEAR inputs are referred to as
(c) Monostable multivibrator (a) synchronous inputs (b) serial inputs
(d) Astable multivibrator (c) load inputs (d) asynchronous inputs
(1 Mark) (1 Mark)

4. In a negative edge-triggered D-type flipflop, the data 7. A MOD-32 synchronous counter would require
at D-input is transferred to the Q-output during
(a) six flipflops and three AND gates
(a) LOW-to-HIGH transition of the clock pulse (b) five flipflops
(b) HIGH-to-LOW edge of the clock pulse (c) five flipflops and three AND gates
(c) HIGH time of the clock pulse (d) None of these (1 Mark)
(d) LOW time of the clock pulse 8. Mark the false statement:
(1 Mark)
(a) Ring counter is a synchronous counter.
(b) Johnson counter is a synchronous counter.
5. Two of the four synchronous modes of operation in
(c) The output of a ring counter is always a square
a clocked J-K flipflop are SET and HOLD. The
wave.
other two are
(d) The decoding circuitry of a Johnson counter is
(a) PRESET and CLEAR always simpler than that of a ring counter.
(b) PRESET and RESET (1 Mark)
(c) RESET and TOGGLE
9. A four-bit presettable DOWN counter initially
(d) PRESET and TOGGLE (1 Mark)
loaded with 0101 will divide the input clock fre-
quency by
6. Mark the incorrect statement.
(a) 16 (b) 5
(a) D-flipflop is same as D-type latch. (c) 11 (d) 10
(b) When the PRESET input of a certain flipflop (1 Mark)
is active, it sets the flipflop to logic `1 state 10. A cascade arrangement of four stages of BCD coun-
irrespective of status of synchronous inputs. ters can be used to count a maximum of
(c) PRESET and CLEAR inputs should not be (a) 1111 pulses
active simultaneously. (b) 1111111111111111 pulses
(d) A J-K flipflop with active LOW J and K (c) 1001100110011001 pulses
inputs will function like a toggle flipflop for (d) 9999 pulses
J= K = 0. (1 Mark) (2 Marks)
1. Of what modulus, Johnson counters can be con- propagation delay of 25 ns and 10 ns, respectively.
structed from an octal D-type flipflop IC? Determine the maximum usable clock frequency in
(1 Mark) MHz of this counter. (1 Mark)
2. A five-bit Johnson counter is in cascade with a 7. A four-bit shift counter is clocked by a 10 MHz
five-bit ring counter. What will be the modulus of clock signal. Determine duty cycle of the waveform
resultant counter circuit? (1 Mark) appearing at the output of the output flipflop.
(1 Mark)
3. Of what modulus ring counters can be constructed
from an octal D-type flipflop IC? (1 Mark) 8. A 100 kHz clock signal is applied to a J-K flipflop.
J = K = 1. If the J and K are active-LOW inputs,
4. What can be the possible range of modulus of a what would be the frequency of true output in kHz
five-bit binary counter? (2 Marks) assuming true output is initially in logic `0 state?
(1 Mark)
5. An eight-bit binary ripple UP counter with a
modulus of 256 is holding a count 01111111. 9. In Question 8, what would be the frequency of true
What will be the count after 135 clock cycles? output if J and K are active-HIGH inputs, other
(2 Marks) data remaining same. (1 Mark)
6. The flipflops used in a four-bit binary ripple coun- 10. In Question 9, what will be the frequency in kHz of
ter have a HIGH-to-LOW and LOW-to-HIGH the complementary output? (1 Mark)

1. (a) A Schmitt trigger is a bistable multivibrator gate fed from true outputs of LSB and fourth MSB
with an external input. It has two trip points, one flipflops. Its output feeds tied J and K inputs of
for LOW-to-HIGH transition and the other for third MSB flipflop. Second AND gate is a three-
HIGH-to-LOW transition thereby providing an input gate fed from true outputs of LSB, fourth
inherent hysteresis. MSB and third MSB flipflops. Its output feeds
tied J and K inputs of second MSB flipflop. Third
2. (c) A decade counter is always a modulo-10 coun-
AND gate is four-input gate fed from true outputs
ter. It may not necessarily be a BCD counter. BCD
of LSB, fourth MSB, third MSB and second MSB
counter is a special case of a decade counter.
flipflops. Its output feeds tied J and K inputs of
3. (d) They are called asynchronous inputs as they MSB flipflop. Fourth MSB flipflops J and K
operate independent of synchronous inputs and inputs are fed from true and complementary out-
input clock signal. puts of LSB flipflop.
4. (b) Negative edge-triggered implies HIGH-to- 8. (c) In the case of ring counter, duty cycle of output
LOW edge of the clock pulse and positive edge waveform is 0.25. The output is a square waveform
triggered means LOW-to-HIGH edge of the clock in case of shift counter.
pulse.
9. (b) The down counter will count as 0101, 0100,
5. (c) PRESET and CLEAR are asynchronous inputs. 0011, 0010 and 0001. On the occurrence of sixth
clock pulse, the output tends to go to 0000 and gets
6. (a) In the case of D-latch, output follows D-input
loaded with 0101 again. The down count sequence
as long as ENABLE input is active. In D-flipflop,
repeats again. Therefore, it becomes a modulo-5
output attains the status of D-input only on the
counter.
relevant clock signal transition. In between two
clock transitions, D-input can change without 10. (d) All BCD counters can count from decimal 0 to
affecting the output. 9. Four BCD counters in the cascade arrangement
are in 1s, 10s, 100s and 1000s places and hence
7. (c) The requirement of five flipflops is obvious for
the answer.
a modulo-32 counter. First AND gate is two-input
1. Johnson counters can be constructed of modulus 16. The next six clock cycles will produce 00000110
Ans. (16) (binary equivalent of decimal number 6). Thus, the
2. A five-bit Johnson counter has a modulus of 10 count after 135 clock cycles is 00000110.
while a five-bit ring counter is a modulo-5 counter. Ans. (00000110)
The modulus of resultant counter circuit is 50. 6. The total propagation delay is
Ans. (50)
25 4 = 100 ns
3. Ring counters can be constructed of modulus 8.
Ans. (8) Therefore, the maximum usable frequency = 10 MHz.
Ans. (10)
4. A four-bit counter can have a maximum modulus of 16
(i.e., 24). The minimum modulus for a five-bit counter 7. The shift counter produces a symmetrical output.
is therefore 17. The maximum modulus of a five-bit Therefore, the duty cycle of the output waveform
counter is 32 (i.e., 25). Hence, the possible modulus or = 50%.
range of modulus of a five-bit binary counter is 1732. Ans. (50)
Ans. (1732) 8. Both J and K inputs are inactive in this case.
5. The current count is 01111111 whose decimal Therefore, true output will remain in the existing
equivalent is 127. After 135 cycles, it will become state, that is, 0. Therefore, the frequency of this
262. The counter comes back to 00000000 after output waveform is also zero.
256 cycles (since it is an eight-bit counter). Ans. (0)

9. The flipflop will function as a toggle flipflop and 10. Complementary output is just the complement
hence a divide-by-two circuit. Hence, the answer is 50. of true output. The frequency remains the same.
Ans. (50) Hence, the answer is 50. Ans. (50)
1. A 0 to 6 counter consists of three flipflops and a When the clock goes HIGH, master flipflop that is
combination circuit of two-input gate(s). The com- enabled and slave flipflop is disabled. Data input
bination circuit consists of affects operation of master flipflop only. When the
(a) one AND gate clock goes LOW, master gets disabled and slave
(b) one OR gate gets enabled and the slave output gets affected
(c) one AND gate and one OR gate according to data input.
(d) two AND gates (GATE 2003: 1 Mark) Ans. (c)
4. Choose the correct one from among the alternatives
Solution. It is a modulo-7 counter and the count A, B, C and D after matching an item from Group
sequence is 000, 001, 010, 011, 100, 101, 110 and 1 with the most appropriate item in Group 2.
000 and so on. The counter is reset the moment
it goes to 111. Since there is no three-input gate Group 1 Group 2
here; two two-input AND gates will be required to
simulate a three-input AND gate that in turn will P. Shift register 1. Frequency division
generate the LOW-to-HIGH CLEAR signal. Q. Counter 2.Addressing in
Ans. (d) memory chips
2. A four-bit ripple counter and a four-bit synchro- R. Decoder 3.Serial-to-parallel
nous counter are made using flipflops having a data conversion
propagation delay of 10 ns each. If the worst case
delay in the ripple counter and the synchronous (a) P 3, Q 2, R 1 (b) P 3, Q 1, R 2
counter be R and S, respectively, then (c) P 2, Q 1, R 3 (d) P 1, Q 2, R 2
(a)R = 10 ns, S = 40 ns (b) R = 40 ns, S = 10 ns (GATE 2004: 1 Mark)
Solution. Counter is used for frequency division,

(c) R = 10 ns, S = 30 ns (d) R = 30 ns, S = 40 ns
decoder is used for addressing in memory chips and
(GATE 2003: 2 Marks) shift register can be used for serial-to-parallel data
conversion.
Solution. Each flipflop has a propagation delay Ans. (b)
of 10 ns. Total propagation delay in a ripple coun- 5. In the modulo-6 ripple counter shown in the follow-
ter is sum of propagation delays of all flipflops. ing figure, the output of the two-input gate is used to
In the case of synchronous counters, it is equal to clear the J-K flipflops. The two-input gate is a/an
propagation delay of each flipflop. Therefore, R =
1
40 ns and S = 10 ns.
Ans. (b) C J B J A J Clock
input
3. A masterslave flipflop has the characteristic that
C K B K A K
(a) change in the input is immediately reflected in
the output
(b) change in the output occurs when the state of 2-input
the master is affected gate
(c) change in the output occurs when the state of
the slave is affected (a) NAND gate (b) NOR gate
(d) both the master and the slave states are affected (c) OR gate (d) AND gate
at the same time (GATE 2004: 2 Marks)
(GATE 2004: 1 Mark)
Solution. This counter counts as 000, 001, 010,
Solution. The output of the master-slave flip 011, 100, 101, 000, .... Thus, the logic gate should
flop is basically the output of the slave flipflop. be such that it produces a `0 output for B = 1,

C = 1 (B = 0, C = 0 ) and a `1 output for every other (a) S = 0 Co = 0 (b) S = 0 Co = 1

input. Note that inputs to the logic gate are from B (c) S = 1 Co = 0 (d) S = 1 Co = 1
and C . Therefore, the logic gate is an OR gate.
Ans. (c)
Solution. After the first clock pulse, A = 1, B =
6. The present output Qn of an edge-triggered J-K
1, Ci = 0, S = 0, Co = 1. After the second clock
flipflop is at logic 0. If J = 1, then Qn+1
pulse, A = 1, B = 1, Ci = 1, S = 1, Co = 1.
(a) cannot be determined (b) will be logic 0 Ans. (d)
(c) will be logic 1 (d) will race around 9. Two D-flipflops, as shown in the following figure,
(GATE 2005: 2 Marks) are to be connected as a synchronous counter
that goes through the following Q1Q0 sequence
Solution. It is given that Qn = 0 and J = 1. K is
00 01 11 10 00 . The inputs D0
either `0 or `1. If K = 0, the output will go to logic
and D1 , respectively, should be connected as
`1 once triggered. If K = 1, the flipflop will toggle
and again go to logic `1 state.
Ans. (c) D0 Q0 D1 Q1
7. The following figure shows a ripple counter using LSB MSB
positive edge-triggered flipflops. If the present
Clk Q0 Clk Q1
state of the counter is Q2 Q1 Q0 = 011, then its next
state (Q2 Q1 Q0 ) will be
1 1 Clock
1 (a) Q1 and Q0 (b) Q0 and Q1

T0 Q0 T1 Q1 T2 Q2
(c) Q1Q0 and Q1Q0 (d) Q1Q0 and Q1Q0
Clk (GATE 2006: 2 Marks)
Q0 Q1 Q2
Solution.
(a) 010 (b) 100 Q1 Q0 D1( Q0) D0( Q1)

(c) 111 (d) 101 0 0 0 1
(GATE 2005: 2 Marks) 0 1 1 1
Solution. Initially, Q2Q1Q0 = 011. Therefore,Q2 1 1 1 0
= 0, Q1 = 0 and Q0 = 0. With the first clock 1 0 0 0
pulse, all flipflops change state. Therefore, the
Ans. (a)
counter goes to 100.
Ans. (b) 10. The following binary values were applied to the X
and Y inputs of the NAND latch as shown in the
8. For the circuit shown in the following figure, two
following figure in the sequence indicated below:
four-bit parallel-in serial-out shift registers loaded
with the data shown are used to feed the data to a X = 0, Y = 0; X = 1, Y = 1.
full adder. Initially, all the flipflops are in CLEAR
state. After applying two clock pulses, the outputs The corresponding stable P, Q outputs will be
of the full adder should be
X
P
1 0 1 1 D Q A S
MSB LSB Clk Full-
Shift registers adder
0 0 1 1 D Q B
MSB LSB Ci Co
Clk
Q
Q D Y
Clk
(a) P = 1, Q = 0; P = 1, Q = 0; P = 1, Q = 0 or P = 0, Q = 1
Clock (b) P = 1, Q = 0; P = 0, Q = 1 or P = 0, Q = 1; P = 0, Q = 1

(c) P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 0 or P = 0, Q = 1
(d) P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 1
(GATE 2007: 2 Marks) Clk 1
Solution. The circuit shown is that of an R-S 0
latch (X = S, Y = R) with active LOW inputs. T
The input entry X = 0, Y = 0 is a forbidden t
combination. Therefore, none of the answers is t1
correct.
Which of the following waveforms correctly repre-
11. For the circuit shown in the following figure, the sents the output atQ1?
counter state Q1 Q0 follows the sequence
(a) 00, 01, 10, 11, 00, ... (b) 00, 01, 10, 00, 01, ... 1
(a)
(c) 00, 01, 11, 00, 01, ... (d) 00, 10, 11, 00, 10, ... 0
(GATE 2007: 2 Marks) 2T
t1 + T
1
(b)
0
4T
t1 + 2T
D0 Q0 D1 Q1 1
(c)
0
2T
t1 + 2T
1
Clk (d)
0
Solution. Initially Q1Q0 are 00. NOR gate output 4T
is 1 and therefore D0 is 1 and D1 is 0. With first t1 + T
clock edge, Q0 becomes 1 and Q1 remains 0.
This drives NOR gate output to 0 making D0 as 0 (GATE 2008: 2 Marks)
and D1 as 1. With second clock edge, Q0 becomes 0
and Q1 becomes 1. This does not change status of Solution. The arrangement is a divide-by-4 cir-
NOR gate output. Therefore with third clock edge, cuit. Therefore, the output waveform will have
both Q0 remains 0 and Q1 becomes 0. The process a time period of 4T. Also, the total propagation
repeats afterwards Ans. (b) delay is 2T.
Ans. (b)
12. For each of the positive edge-triggered J-K flipflop
used in the following figure, the propagation delay 13. For the circuit shown in the following figure, D has
is T . a transition from 0 to 1 after Clk changes from 1
to 0. Assume gate delays to be negligible. Which of
the following statements is true?
Q0 Q1
1 J0 1 J1 (a) Q goes to 1 at the Clk transition and stays at 1.
(b) Q goes to 0 at the Clk transition and stays at 0.
(c) Q goes to 1 at the Clk transition and goes to 0
Clk when D goes to 1.
(d) Q goes to 0 at the Clk transition and goes to 1
when D goes to 1.
1 K0 1 K1 (GATE 2008: 2 Marks)

1 (P1, P2) = (0, 1), the output (Q1, Q2) will be

0 Clk 10. For (P1, P2) = 11; both inputs are inactive.
Therefore, the previous output will be retained.
Q That is, (Q1, Q2) = (1, 0).
1 D Ans. (b)
0
15. What are the counting states (Q1 , Q2 ) for the
counter shown in the following figure?
Q1 Q2
Q
J1 Q1 J2 Q2
Clock
Solution. At high to low clock transition, the J-K Flip-flop J-K Flip-flop
input to the top cross-coupled NOR gate is 1,
while the input to the botton cross-coupled NOR K1 Q1 1 K2 Q2
gate is 0. Therefore output Q = 1. When D = 1,
the input to the top cross-coupled NOR gate is 0
and to the bottom cross-coupled NOR gate is 1.
Therefore Q = 0.
(a) 11, 10, 00, 11, 10 ... (b) 01, 10, 11, 00, 01 ...
Ans. (c)
(c) 00, 11, 01, 10, 00 ... (d) 01, 10, 00, 01, 10 ...
14. Refer to the NAND and NOR latches shown in the (GATE 2009: 2 Marks)
following figure.
Solution. Initially the count is 00. J and K
P1
Q1 inputs of both flipflops are in logic `1 state.
With first clock pulse, count sequence becomes
11. Now, J and K inputs of the first flipflop are
both in logic `0 state. J and K inputs of second
flipflop, respectively, are in logic `0 and logic
Q2 `1 states. Therefore, with the second clock pulse,
P2
the count sequence becomes 10. With the third
clock pulse, the firstflop toggles and the count
P1 sequence is 00. So, the counting sequence is 11,
Q1
10, 00, 11, 10, 00 ... Ans. (a)
16. Assuming that all flipflops are in reset conditions
initially, the count sequence observed at QA in the
circuit shown in the following figure is
Q2
P2 (a) 0010111 ... (b) 0001011 ...
(c) 0101111 ... (d) 0110100 ...
The inputs (P1 , P2 ) for both the latches are first (GATE 2010: 2 Marks)
made (0, 1) and then, after a few seconds, made (1,
1). The corresponding stable outputs (Q1 , Q2 ) are Output
(a) N
AND: first (0, 1) then (0, 1) NOR: first (1, 0)
then (0, 0)
(b) NAND: first (1, 0) then (1, 0) NOR: first (1, 0)
DA QA DB QB DC QC
then (1, 0)
(c) NAND: first (1, 0) then (1, 0) NOR: first (1, 0)
QA QB QC
then (0, 0)
(d) NAND: first (1, 0) then (1, 1) NOR: first (0, 1) Clock
then (0, 1)
(GATE 2009: 2 Marks) Solution. Initially, QA, QB, QC are `0. This makes
DA = `1.With the first clock pulse, QA becomes `1.
Solution. Both circuits are R-S latches with QB and QC remain in logic `0 state. DA is still `1.With
active LOW inputs. Therefore, in both cases, for the second clock pulse, QA remains in logic `1 state.

(a)
Vo
QB becomes `1. QC remains `0. DA becomes `0. With

the third clock pulse, QA becomes `0. The first four (b)
Vo
entries of QA therefore are 0110. This matches with
only the answer given in option (d).
Ans. (d)
17. When the output Y in the circuit shown in the
following figure is `1, it implies that data has
(c)
Vo
Y
Data D Q D Q
Clock Q Q
(d)
Vo
(a) Changed from `0 to `1
(b) Changed from `1 to `0
(c) Changed in either direction
(d) Not changed (GATE 2011: 1 Mark)
Solution. Presently, Y = 1. This implies that
prior to clock pulse; both the D-inputs were in logic
`1 state. This further implies that Q-output of the (GATE 2011: 2 Marks)
first flipflop was in logic `0 state. This can result
from its D-input being previously in logic `0 state. Solution. Sequence of Johnson counter in one
Hence, the data input has changed from 0 to 1. complete cycle is 000, 100, 110, 111, 011, 001 and
Ans. (a) 000. The corresponding analog outputs will be
18. The output of a three-stage Johnson (twisted-ring) 0 V, 4 V, 6 V, 7 V, 3 V, 1 V and 0 V if LSB = 1 V
counter is fed to a digital-to-analog (D/A) con- and hence the answer.
verter as shown in the following figure: Ans. (a)
19. Two D-flipflops are connected as a synchronous
Vref counter that goes through the following QBQA
D/A
Vo sequence 00 11 01 10 00 . The
Converter connections to the inputs DA and DB are
D2 D1 D0
(a) DA = QB , DB = QA
(b) DA = QA , DB = QB
Q2 Q1 Q0
(c) DA = (QB QB + QA QB ), DB = QA
Johnson
counter (d) DA = (QA QB + QA QB ), DB = QB
Clock
Assume all states of the counter to be unset ini- Solution.

tially. The waveform which represents the D/A
Present State Next State
converter output Vo is
QB QA QB QA
(a) 0 0 1 1
Vo
1 1 0 1
0 1 1 0
1 0 0 0
0 0 1 1
(b)
Vo

Now, using the excitation table of D-flip-flop A=1 A=0

DA = QA QB + QA QB A=1
DB = QB Ans. (d) (a)

Q=0 Q=1
A=0
20. Consider the circuit shown in the following figure.
A A=0 A=0
A=1
Clk (b)
Q=0 Q=1
A=1
A=0 A=1
B
A=0
In this circuit, the race around (c)

Q=0 Q=1
A=1
(a) does not occur
(b) occurs when Clk = 0
(c) occurs when Clk = 1 and A = B = 1 A=1 A=1
(d) occurs when Clk = 1 and A = B = 0 A=0
(GATE 2012: 1 Mark)
(d)
Q=0 Q=1
Solution. The circuit shown is that of an active- A=0
HIGH clocked R-S flipflop with S = A and R
= B. The race condition does not occur in these
flipflops. (GATE 2012: 2 Marks)
Ans. (a)
21. The state transition diagram for the logic circuit Solution. When A = 1, X1 = Q will be selected
shown in the following figure is as feedback to D-input. Therefore, Q-state (0 or
1) will be retained. When A = 0, X0 = Q will
be selected as feedback to D-input. Therefore,
Q-output will toggle.
2-1 MUX Ans. (d)
D Q X1
Y
X0
Clk Q Select

CHAPTER 27
D/A AND A/D CONVERTERS
This chapter discusses digital-to-analog (D/A) and analog-to-digital (A/D) converters. The discussion is mainly in terms
of operational fundamentals, major performance specifications, types and applications of D/A and A/D converters.
27.1 D/A CONVERTERS the help of simple network theorems that the output
analog voltage is given by
V1 20 + V2 21 + V3 22
A D/A converter takes digital data at its input and VA = (27.1)
converts it into an analog voltage or current that is 23 1
proportional to weighted sum of digital inputs. V V V
27.1.1 Simple Resistive Divider Network for

D/A Conversion R/4 R/2 R
Simple resistive networks can be used to convert a VA

digital input into an equivalent analog output. Figure
27.1 shows one such resistive network that can convert RL
a three-bit digital input into an analog output. This
network can be extended further to enable it perform
digital-to-analog conversion of digital data with larger
number of bits. In the network shown in Fig. 27.1, Figure 27.1| Simple resistive divider network for D/A
if RL is much larger than R, it can be proved with conversion.

644 Chapter 27: D/A and A/D Converters
Eq. (27.1) can be extended further to an n-bit D/A

V1 20 + V2 21 + V3 22 + V4 23
converter to get the following expression: VA = (27.4)
24
V1 20 + V2 21 + V3 22 + + Vn 2n 1 In general, for an n-bit D/A converter using binary
VA = (27.2)
2n 1 ladder network, VA is given by Eq. (27.5).
In Eq. (27.2), if V1 20 + V2 21 + V3 22 + ... Vn 2n 1
VA = (27.5)
2n
V1 = V2 = = Vn = V
Using Eq. (27.5), for V1 = V2 = V3= =Vn = V, we get
then a logic `1 at the LSB position would contribute
2n 1
V/(2n 1) to the analog output, a logic `1 in the next VA = n V
adjacent higher bit position would contribute 2V/(2n 1) 2
to the output. The contributions of successive higher bit
positions in case of a logic `1 would be and for V1 = V2 = V3= = Vn = V = 0, we get VA = 0.
4V 8V 16V V V V V
, , 20 21 22 23
2n 1 2n 1 2n 1 (LSB) (MSB)
That is, contribution of any given bit position due to 2R 2R 2R 2R
the presence of a logic `1 is twice the contribution of
the adjacent lower bit position and half of the adjacent 2R R R R
higher bit position. When all input bit positions have VA
logic `1, the analog output is given by
V (20 + 21 + 22 + + 2n 1 )
VA = =V (27.3) Figure 27.2| Binary ladder network for D/A
2n 1 conversion.
In the case of all inputs being in logic `0 state, VA = 0.
Therefore, analog output varies from 0 to V volts as the Analog output voltage in this case varies from 0 V (for an
digital input varies from an all 0s to an all 1s input. all 0s input) to
2n 1
VA = n V
27.1.2 Binary Ladder Network for D/A 2
Conversion for an all 1s input.
Also, in case of resistive divider network, the LSB
The simple resistive divider network shown in Fig. 27.1 contribution to the analog output is
has two serious drawbacks: (1) Each resistor in the net-
work is of a different value. Since these networks use pre- 1
n V
cision resistors, the added expense becomes unattractive; 2 1
(2) Two, the resistor used for the most significant bit This is also the minimum possible incremental change
(MSB) is required to handle a much larger current than in the analog output voltage. The same in the case of
the LSB resistor. For example, in a 10-bit network, cur- binary ladder network would be
rent through MSB resistor will be about 500 times the
current through LSB resistor. 1
n V
To overcome these drawbacks, a second type of resis- 2
tive network called binary ladder (or R/2R ladder) is Binary ladder network is the most widely used net-
used in practice. The binary ladder too is a resistive work for digital-to-analog conversion for obvious reasons.
network which produces an analog output that equals Though actual D/A conversion takes place in this net-
weighted sum of digital inputs. Figure 27.2 shows the work, a practical D/A converter device has additional
binary ladder network for a four-bit D/A converter. As circuitry such as a register for temporary storage of
is clear from the figure, the ladder is made up of only input digital data and level amplifiers to ensure that
two different values of resistors. This overcomes one of the digital signals presented to the resistive network are
the drawbacks of the resistive divider network. It can all of the same level. Figure 27.3 shows block schematic
be proved with the help of simple mathematics that the representation of a complete n-bit D/A converter. D/A
analog output voltage (VA) in the case of binary ladder converters of different sizes (8-bit, 12-bit, 16-bit etc.) are
network is given by available in the form of integrated circuits.

27.2 D/A CONVERTOR SPECIFICATIONS 645
n-bit In general, for an n-bit D/A converter, percentage

Digital resolution is given by
input
100 %
1
Input 2 1
n
gates The resolution in millivolts for the two cases for a

n-Lines full-scale output of 5 V is approximately 20 mV (for an
eight-bit converter) and 1.2 mV (for a 12-bit converter).
n-bit
register 27.2.2 Accuracy
n-Lines
The accuracy of a D/A converter is the difference between
the actual analog output and the ideal expected output
Level when a given digital input is applied. Sources of error
amplifiers include the gain error (or full-scale error), offset error
n-Lines (or zero scale error), non-linearity errors and a drift of
all these factors. Gain error [Fig. 27.4(a)] is the difference
Binary between the actual and ideal output voltage expressed in
VA percent of full-scale output. It is also expressed in terms
ladder
of LSB. As an example, accuracy of 0.1% implies that
Figure 27.3| Block schematic representation of a D/A the analog output voltage may be off by as much as
converter 5 mV for a full-scale output of 5 volts throughout the
analog output voltage range. The offset error is the error
at analog zero [Fig. 27.4 (b)].
27.2 D/A CONVERTOR
SPECIFICATIONS
27.2.3 Conversion Speed or Settling Time
The major performance specifications of a D/A converter The conversion speed of a D/A converter is expressed in
include the following: terms of its settling time. Settling time is the time period
that has elapsed for the analog output to reach its final
1. Resolution
value within a specified error band after a digital input
2. Accuracy
code change has been affected. The general purpose D/A
3. Conversion speed
converters have a settling time of several microseconds
4. Dynamic range
while some of the high speed D/A converters have a set-
5. Non-linearity (NL) and differential non-linearity
tling time of a few nanoseconds.
(DNL)
6. Monotonocity
27.2.4 Dynamic Range
27.2.1 Resolution
Dynamic range is the ratio of the largest output to the
The resolution of a D/A converter is the number of smallest output excluding zero expressed in dB. For the
states 2n that the full-scale range is divided or resolved linear D/A converters, it is (20 log2n) dBs which is
into. Here, n is the number of bits in the input digital approximately equal to 6n dBs.
word. Higher the number of bits better is the resolution.
An eight-bit D/A converter has 255 resolvable levels. It
is said to have a percentage resolution of 27.2.5 Non-linearity and Differential
Non-linearity
1
100 = 0.39%
255 Non-linearity (NL) is the maximum deviation of analog
output voltage from a straight line drawn between the
or simply eight-bit resolution. A 12-bit D/A converter
end points expressed in percent of the full-scale range or
would have a percentage resolution of
in terms of LSBs. The differential non-linearity (DNL) is
1 the worst-case deviation of any adjacent analog outputs
100 = 0.0244%
4095 from the ideal 1 LSB step size.

Ideal Actual
Actual
Ideal
Analog output
Analog output Gain
error
Offset error
Digital input Digital input
(a) (b)
Figure 27.4| (a) Gain error and (b) offset error.
27.2.6 Monotonocity 1. Multiplying-type D/A converters

2. Bipolar output D/A converters
In an ideal D/A converter, the analog output should 3. Companding D/A converters
increase by an identical step size for every 1 LSB incre-
ment in the digital input word. When the input of such 27.3.1 Multiplying-type D/A Converters
a converter is fed from the output of a counter, the con-
verter output would be a perfect staircase waveform as In a multiplying-type D/A converter, the converter mul-
shown in Fig. 27.5. In such cases, the converter is said tiplies an analog reference by the digital input. Figure
to be exhibiting perfect monotonocity. A D/A converter 27.6 shows the circuit representation. Some D/A con-
is considered as monotonic if its analog output either verters can multiply only positive digital words by a
increases or remains same but does not decrease as the positive reference. This is known as single quadrant
digital input code advances in 1 LSB steps. If the dif- (QUAD-I) operation. Two quadrant operation (QUAD-I
ferential non-linearity (DNL) error of a D/A converter and QUAD-III) can be achieved in a D/A converter
is less than or equal to twice its worst-case non-linearity by configuring the output for bipolar operation. This
error, it guarantees monotonocity. is accomplished by off-setting the output by a negative
MSB (equal to analog output of 1/2 of full-scale range)
so that MSB becomes the sign bit. Some D/A convert-
ers provide even four-quadrant operation by allowing
D/A the use of both positive as well as negative reference.
Converter Multiplying D/A converters are particularly useful when
Analog
we are looking for digitally programmable attenuation of
O/P
Digital I/P an analog input signal.
Digital input
Counter
Figure 27.5| Monotonocity in a D/A converter. Analog Analog

reference D/A output
27.3 TYPES OF D/A CONVERTERS Converter
Figure 27.6| Multiplying-type D/A converter.

The D/A converters discussed in this section include the
following:

27.4 MODES OF OPERATION 647
27.3.2 Bipolar Output D/A Converters 27.4 MODES OF OPERATION

In bipolar output D/A converters, the analog output
signal range includes both positive and negative values. D/A converters are usually operated in either of the
The transfer characteristics of an ideal two-quadrant following two modes of operation.
bipolar output D/A converter are shown in Fig. 27.7. 1. Current steering mode
2. Voltage switching mode
+FS Analog
O/ P 27.4.1 Current Steering Mode of Operation
In the current steering mode of operation of a D/A con-

verter, the analog output is a current equal to the prod-
-FS +FS uct of a reference voltage and a fractional binary value D
Digital of the input digital word. Here, D is the sum of fractional
I/P binary values of different bits in the digital word. Also,
the fractional binary values of different bits in an n-bit
digital word starting from LSB are
-FS 20 21 22 2 n 1
n
, n
, n
,,
2n
Figure 27.7| Bipolar-output D/A converter transfer
2 2 2
characteristics. The output current is often converted into a corre-

sponding voltage using an external opamp wired as a
current-to-voltage converter. Figure 27.8 shows the cir-
cuit arrangement. The majority of D/A converters in
27.3.3 Companding D/A Converters
integrated circuit form has an in-built opamp that can
Companding-type D/A converters are so constructed be used for current-to-voltage conversion. For the circuit
that the more significant bits of the digital input have arrangement shown in Fig. 27.8, if the feedback resistor
a larger than binary relationship to the less significant RF equals the ladder resistance R, the analog output
bits. This decreases the resolution of more significant voltage at opamp output is DVref.
bits, which in turn increases the analog signal range. The arrangement of a four-bit D/A converter shown
The effect of this is to compress more data into more in Fig. 27.8 can be conveniently used to explain the oper-
significant bits. ation of a D/A converter in the current steering mode.
I R R R 2R I/16
Vref
I/2 I/4 I/8 I/16
(Analog ground) RF = R
2R 2R 2R 2R
Out-1
Out-2 +
(Digital ground)
MSB LSB
Figure 27.8| Current steering mode of operation of a D/A converter.

The R/2R ladder network divides the input current I (1 2n ) Vref

due to a reference voltage Vref applied at the reference
voltage input of the D/A converter into binary weighted where n is number of bits in the input digital word.
currents as shown. These currents are then steered to
either the output designated Òut-1 or Òut-2 by the 27.4.2 Voltage Switching Mode of Operation
current steering switches. The positions of these current
steering switches are controlled by digital input word. In the voltage switching mode of operation of R/2R
A logic `1 steers the corresponding current to Out-1 ladder-type D/A converter, the reference voltage is
whereas a logic `0 steers it to Out-2. For instance, a applied to Out-1 terminal and the output is taken from
logic `1 in MSB position will steer the current I/2 to reference voltage terminal. Out-2 is joined to analog
Out-1. Logic `0 steers it to Out-2, which is the ground ground. Figure 27.9 shows the four-bit D/A converter
terminal. In the four-bit converter shown in Fig. 27.8, of R/2R ladder-type in voltage switching mode of opera-
the analog output current (or voltage) will be maximum tion. The output voltage is product of fractional binary
for a digital input of 1111. The analog output current in value of the digital input word and the reference voltage
this case will be applied at Out-1 terminal, that is, DVref. Since the posi-
15
I I I I tive reference voltage produces a positive analog output
+ + + = I
2 4 8 16 16
voltage, the voltage switching mode of operation is pos-
sible with a single supply. Since the circuit produces
The analog output voltage will be analog output voltage, it obviates the need for an opamp
and the feedback resistor. However, the reference voltage
15 15
IRF = IR applied to Out-1 terminal in this case will see different
16 16 input impedances for different digital inputs. For this
Also, I = Vref/R since the equivalent resistance of the reason, the source of input is buffered.
ladder network across Vref is also R. The analog output
voltage is then 27.5 BCD INPUT D/A CONVERTER
( 15/16)Vref 15
R = 16 Vref
R A BCD input D/A converter accepts BCD equivalent
Here, 15/16 is the fractional binary value of digital input of decimal digits at its input. A two-digit BCD D/A
1111. In general, the maximum analog output voltage is converter for instance is an eight-bit D/A converter.
given by Figure 27.10 shows circuit representation of an eight-bit
(Analog O/P) R R R 2R
2R 2R 2R 2R
Vref
Out-1
Out-2 +
(Digital ground)
MSB LSB
Figure 27.9| Voltage switching mode of operation of a D/A converter.

27.6 A/D CONVERTERS 649
BCD-input D/A converter. Such a converter has 99 4. Gain and offset drifts
steps and accepts decimal digits 00 to 99 at its input. 5. Sampling frequency and aliasing phenomenon
A 12-bit converter will have 999 steps. The weight of 6. Quantization error
different bits in the least significant digit (LSD) will be 7. Non-linearity
1 (for A0), 2 (for B0), 4 (for C0) and 8 (for D0). The 8. Differential non-linearity
weights of the corresponding bits in the next higher digit 9. Conversion time
will be 10 times the weights of corresponding bits in the 10. Aperture and acquisition times
lower adjacent digit. For the D/A converter shown in 11. Code width
Fig. 27.10, the weight of different bits in the most signifi-
cant digit (MSD) will be 10 (for A1), 20 (for B1), 40 (for
27.6.1.1Resolution
C1) and 80 (for D1). In general, an n-bit D/A converter
of BCD input type will have (10n/4 1) steps. The per-
The resolution of an A/D converter is the quantum of
centage resolution of such a converter is given as follows:
input analog voltage change required to increment its

100 %
1 digital output between one code change and the next
Percentage resolution = n/ 4
10 1 code change. An n-bit A/D converter can resolve 1 part
in 2n. It may be expressed in percent of full-scale or in
bits. The resolution of an eight-bit A/D converter, for
Most D1 example, can be expressed as 1 part in 256 or as 0.4%
significant C1 of full scale or simply as eight-bit resolution. If such a
digit B1 converter has a full-scale analog input range of 10 V, it
(MSD) A1 can resolve a 40 mV change in input.
BCD
Leat D0 D/A
Converter Analog O/P
significant C0 27.6.1.2Accuracy
digit B0
(LSD) A0 The accuracy specification describes the maximum sum
of all the errors, both from analog sources (mainly the
comparator and the ladder resistors) as well as the digital
Figure 27.10| BCD-input D/A converter. sources (quantization error) of the A/D converter. These
errors mainly include the gain error, the offset error
and the quantization error. The accuracy describes the
difference between the actual analog input and full-scale
27.6 A/D CONVERTERS weighted equivalent of the output code corresponding to
actual analog input.
An A/D converter takes at its input an analog voltage
and after a certain amount of time, produces a digital 27.6.1.3Gain and Offset Errors
output code representing the analog input. A/D conver-
sion process is generally more complex than the D/A The gain error is the difference between the actual full-
conversion process. There are various techniques devel- scale transition voltage and the ideal full-scale transi-
oped for the purpose of A/D conversion and these tech- tion voltage. It is expressed either as percent of full-scale
niques have different advantages and disadvantages with range (% of FSR) or in LSBs. Offset error is the error at
respect to one another, which have been utilized in the analog zero for an A/D converter operating in the bipo-
fabrication of different categories of A/D converter ICs. lar mode. It is measured in % of FSR or in LSBs.
A D/A converter circuit, as we shall see in the follow-
ing sections, forms a part of some of the A/D converter
types. 27.6.1.4Gain and Offset Drifts
The gain drift is the change in the full-scale transition

27.6.1 A/D Converter Specifications voltage measured over the entire operating temperature
range. It is expressed in full scale per degree Celsius or
The major performance specifications of an A/D con- ppm of full scale per degree Celsius or LSBs. The offset
verter include the following: drift is the change with temperature of the analog zero
1. Resolution for an A/D converter operating in the bipolar mode. It
2. Accuracy is generally expressed in ppm of full scale per degree
3. Gain and offset errors Celsius or LSBs.

27.6.1.5Sampling Frequency and Aliasing 27.6.1.8Differential Non-linearity

Phenomenon
It indicates the worst-case difference between the actual
If the rate at which the analog signal to be digitized is analog voltage change and the ideal 1 LSB voltage
sampled is at least twice the highest frequency in the change. DNL specification is as important as the INL
analog signal, which is what is embodied in the Shannon specification as an A/D converter having a good INL
Nyquist sampling theorem, then the analog signal can specification may have a poor quality transfer curve if
be faithfully reproduced from its quantized values by DNL specification is poor. DNL is also expressed in per-
using a suitable interpolation algorithm. The accuracy cent of full scale or in LSBs. DNL in fact explains the
of the reproduced signal is however limited by quantiza- smoothness of the transfer characteristics and is thus
tion error. If the sampling rate is inadequate, that is, it of great importance to the user. Figure 27.11 shows the
is less than the Nyquist rate, in that case the reproduced transfer curve for three-bit A/D converter with 7 V full-
signal is not a faithful reproduction of original signal scale range, (1/4)-LSB INL and 1-LSB DNL.
and these spurious signals called aliases are produced.
The frequency of aliased signal is difference between the
signal frequency and the sampling frequency. For exam- 111
ple, a 2 kHz sine wave if sampled at 1.5 kHz rate would
be reconstructed as a 500 Hz sine wave. This problem is 110
Digital output
called aliasing and in order to avoid aliasing, the analog 101
input signal is low pass filtered to remove all frequency
100
components above half of the sampling rate. This filter,
called anti-aliasing filter, is used in all practical A/D 011
converters.
010
001
27.6.1.6Quantization Error
000
0 1 2 3 4 5 6 7 8
The quantization error is inherent to digitizing process. Analog input(V)
For a given analog input voltage range, it can be reduced
by increasing the number of digitized levels. An A/D Figure 27.11| Transfer characteristics of a three-bit
converter having an n-bit output can only identify (2n) A/D converter [INL = (1/4)-LSB,
output codes while there exist an infinite number of DNL = 1LSB].
analog input values which are assigned the same output
code. For instance, if we are digitizing an analog signal Figure 27.12 shows the same for 7 V full-scale range,
with a peak value of 7 V using 3 bits, then in that case 1-LSB NL and (1/4)-LSB DNL. Although the former has
all analog voltages equal to or more than 5.5 V and much better INL specification, the latter with better DNL
less than or equal to 6.5 V will be represented by same specification, has a much better and smoother curve and
output code, that is, 110 (if the output coding is in may thus be preferred. Too high a value of DNL may
straight binary form). The error is 0.5V or (1/2)- even grossly degrade the converter resolution. In a four-bit
LSB as 1-LSB change in the output corresponds to an converter with 2-LSB DNL, the 16-step transfer curve
analog change of 1 V in this case. The (1/2)-LSB limit may be reduced to a six-step curve. DNL specification
to resolution is known as the fundamental quantization should in no case be ignored unless the INL specification is
error. Expressed in percentage, the quantization error in tight enough to guarantee the desirable DNL.
an eight-bit converter is 1 part in 256 or 0.4%.
27.6.1.9Conversion Time
27.6.1.7Non-linearity
It is the time that elapses from the time instant of the
The non-linearity specification [also referred to as the start of conversion signal until the conversion complete
integral non-linearity (INL) by some manufacturers] of signal occurs. It ranges from a few nanoseconds for flash-
an A/D converter describes its departure from a linear type A/D converters to a few microseconds for succes-
transfer curve. Non-linearity error does not include gain, sive approximation type A/D converters and may be as
offset and quantization errors. It is expressed in percent large as tens of milliseconds for dual-slope integrating
of full scale or in LSBs. A/D converters.

27.8 TYPES OF A/D CONVERTERS 651
digitize the signal. Based on various conversion meth-

111 odologies, common types of A/D converters include the
following:
110
Digital output
1. Flash or simultaneous or direct conversion A/D

101 converter
100 2. Half-flash A/D converter
3. Counter-type A/D converter
011 4. Tracking-type A/D converter
010 5. Successive approximation type A/D converter
6. Single-slope, dual-slope and multi-slope A/D
001
converters
000 7. Sigmadelta A/D converter
0 1 2 3 4 5 6 7
Analog input(V)
Figure 27.12| Transfer characteristics of a three-bit
27.8.1 Simultaneous or Flash A/D Converter
A/D converter [INL = 1 LSB,
The simultaneous method of A/D conversion is based
DNL = (1/4)-LSB].
on using a number of comparators. The number of com-
parators needed for n-bit A/D conversion is 2n 1. One
27.6.1.10Aperture and Acquisition Times such system capable of converting an analog input signal
into a two-bit digital output is shown in Fig. 27.13. The
When a rapidly changing signal is digitized, the input analog signal to be digitized serves as one of the inputs
signal amplitude would have changed even before the to each of the comparators. The second input for each of
conversion is complete with the result that output of the the comparators is a reference input, different for each
A/D converter does not represent the signal amplitude at comparator. The reference voltages to be used for com-
the start. A sample and hold circuit with a buffer ampli- parators are, in general, given as follows:
fier is used at the input of the A/D converter to over-
come this problem. Aperture and acquisition times are V 2V 3V 4V
the parameters of the sample and hold circuit. The signal n
, n
, , ,
to be digitized is sampled with an electronic switch that 2 2 2n 2n
can be rapidly turned on and off. The sampled amplitude Here, V is the maximum amplitude of the analog signal
is then stored on the hold capacitor. The A/D converter that the A/D converter can digitize and n is the number
digitizes the stored voltage and after the conversion is of bits in the digitized output. In the present case of two-
complete, a new sample is taken and held for the next bit A/D converter, the reference voltages for the three
conversion. The acquisition time is the time required by comparators will be V/4, V/2 and 3V/4. If we wanted a
the electronic switch to close and the hold capacitor to three-bit output, the reference voltages would have been
charge while aperture time is the time needed for the V/8, V/4, 3V/8, V/2, 5V/8, 3V/4 and 7V/8. Referring
switch to completely open after the occurrence of hold to Fig. 27.13, the output status of various comparators
signal. Ideally, both times should be zero. The maximum depends upon the input analog signal VA. For instance,
sampling frequency is thus determined by the aperture when the input VA lies between V/4 and V/2, output C1
and acquisition times in addition to the conversion time. is HIGH whereas both C2 and C3 outputs are LOW. The
three comparator outputs can then be fed to a coding
27.6.1.11Code Width network (comprising of logic gates, etc.) to provide two
bits which are digital equivalent of input analog voltage.
The quantum of input voltage change that occurs The bits at the output of the coding network can then be
between the output code transitions expressed in LSBs entered into a flipflop register for storage.
of full-scale is the code width. Code width uncertainty is The construction of a simultaneous A/D converter is
the dynamic variation or jitter in the code width due to quite straightforward and relatively easy to understand.
noise. However, as the number of bits in the desired digital
signal increases, the number of comparators required
27.8 TYPES OF A/D CONVERTERS performing A/D conversion increases very rapidly and it
may not be feasible to use this approach once the number
of bits exceeds 6 or so. The greatest advantage of this
A/D converters are often classified according to the technique lies in its capability to execute extremely fast
conversion process or the conversion technique used to A/D conversion.

+
Comp.
C3

3V/4
S 1
Coding network
Q 2
Read gates
VA R
+
V/2 C2
S 0
Q 2
R
+
Comp.
C1

V/4
Figure 27.13| Two-bit simultaneous A/D converter.
27.8.2 Half-Flash A/D Converter In case of an eight-bit converter, the number is 32 (for
half-flash) against 256 (for full-flash). How it is achieved
Half-flash A/D converter, also known as pipeline A/D is explained in the following sections considering the
converter, is a variant of flash-type A/D converter that example of an eight-bit half-flash A/D converter.
overcomes to a large extent the primary disadvantage of
A half-flash A/D converter uses two full-flash converters
requirement of a prohibitively large number of compara-
with each full-flash A/D converter having a resolution equal
tors in high-resolution full-flash A/D converters without
to half the number of bits of the half-flash A/D converter.
significantly degrading its high speed conversion perfor-
That is, an eight-bit half-flash A/D converter uses two
mance. When compared to a full-flash A/D converter of
four-bit flash A/D converters. In addition, it uses a four-bit
certain resolution, while the number of comparators and
D/A converter and an eight-bit latch. Figure 27.14 shows
associated resistors reduce drastically in a half-flash A/D
the basic architecture of such an A/D converter.
converter; conversion time increases approximately by a
factor of 2. For an n-bit-flash A/D converter, number The most significant four-bit A/D converter con-
of comparators required is 2n (2n 1 for encoding of verts the input analog signal into a corresponding four-
amplitude and one comparator for polarity), the same bit digital code, which is stored in the most significant
for an equivalent half-flash converter would be 2 2n/2. four bits of the output latch. This four-bit digital code
Vref (+)
4-Bit
Vref () flash
Analogue Vin ADC
Output Digital
4-Bit DAC latch output
Vref (+)
16 4-Bit
flash
ADC
Figure 27.14| Eight-bit half-flash A/D converter.

however represents the low-resolution sample of the The counter-type A/D converter provides a very good
input. Simultaneously, it is converted back into an method for digitizing to a high resolution. The drawback
equivalent analog signal with a four-bit D/A converter. with this A/D converter is that the required conversion
The approximate value of the analog signal so produced time is longer. Since the counter always begins from
is then subtracted from the sampled value and the differ- all 0s position and counts through its normal binary
ence is converted into digital code using least significant sequence, it may require as many as 2n counts before
four-bit A/D converter. Least significant A/D converter conversion is complete. The average conversion time can
is referenced to (1/16)th (i.e., 1/24) of the reference volt- be taken to be 2n/2 = 2n1 counts.
age used by most significant A/D converter. The new
four-bit digital output is stored in least significant four
bits of the output latch. The latch now contains the 27.8.4 Tracking-Type A/D Converter
bit digital equivalent of the analog input. The digitized
output is the same as would be produced by an eight- Tracking-type A/D converter, also called delta-encoded
bit full-flash converter. The only difference is that the A/D converter, is a modified form of counter-type A/D
conversion process takes a little longer. It may also be converter that overcomes to some extent the shortcoming
mentioned here that eight-bit half-flash A/D converter of the latter. In the modified arrangement, the counter,
can be either used as a four-bit full-flash A/D converter which is primarily an UP-counter, is replaced by an UP/
or eight-bit half-flash A/D converter. DOWN counter. It counts in upward sequence when-
ever D/A converter output analog voltage is less than
the analog input voltage to be digitized and it counts in
27.8.3 Counter-Type A/D Converter the downward sequence whenever D/A converter output
analog voltage is greater than analog input voltage. In this
It is possible to construct higher resolution A/D convert- type of converter, whenever a new conversion is to begin,
ers with a single comparator by using a variable refer- the counter is not reset to zero; in fact it begins counting
ence voltage. One such A/D converter is the counter-type either up or down from its last value depending upon the
A/D converter represented by the block schematic shown comparator output. The D/A converter output staircase
in Fig. 27.15. The circuit functions as follows. To begin waveform contains both positive going and negative going
with, the counter is reset to all 0s. When a convert signal staircase signals that track the input analogsignal.
appears on the start-line, the input gate is enabled and
the clock pulses are allowed to the counters clock-input.
The counter advances through its normal binary count 27.8.5 Successive Approximation
sequence. Counter output feeds a D/A converter and Type A/D Converter
the staircase waveform generated at the output of D/A
converter forms one of the inputs of the comparator. The Successive approximation type A/D converter aims at
other input to the comparator is the analog input signal. approximating the analog signal to be digitized by trying
Whenever the D/A converter output exceeds the analog only one bit at a time. The process of A/D conversion
input voltage, the comparator changes state. The gate is by this technique can be illustrated with the help of an
disabled and the counter stops. The counter output at example. Let us take a four-bit successive approximation
that instant of time is then the required digital output type A/D converter. Initially, the counter is reset to all
corresponding to analog input signal. 0s. The conversion process begins with MSB being set
by the start pulse. That is, the flipflop representing
the MSB is set. The counter output is converted into
an equivalent analog signal and then compared with the
Start
analog signal to be digitized. A decision is then taken
whether the MSB is to be left-in (i.e., flipflop represent-
Clock Gate Counter ing MSB remains set) or it is to be taken out (i.e., flip
flop is reset) when the first clock pulse sets the second
MSB. Once the second MSB is set, again a comparison is
Digital made and a decision taken whether the second MSB is to
output remain set or not when the subsequent clock pulse sets
+ the third MSB. The process continues till we go down
to LSB. We will notice that every time we make a com-
D/A parison, we tend to narrow down the difference between
Analog converter the analog signal to be digitized and the analog signal
input, VA
representing the counter count. Refer to the operational
Figure 27.15| Counter-type A/D converter. diagram shown in Fig. 27.16. It is clear from the diagram

1111 is, an eight-bit A/D converter of this type operating on 1

1111
1110 1110 MHz clock has a conversion time of 8 s.
1101
1101 1100
1100 1011
1011 1010 Ring
1010 1001 counter
1001 1000
0000 1000 0111 Control
0111 0110 logic
0110 0101
0101 Analog and
0100 0100 clock
0011 input Counter
0011 0010
0010 VA
0001
0001 0000 Digital
Figure 27.16| Conversion process in a successive
output
approximation type A/D converter.
D/A
Converter
that to reach any count from 0000 to 1111, the converter
requires 4 clock cycles. In general, the number of clock
cycles required for each conversion will be n for n-bit Figure 27.17|Block schematic representation of a successive-
A/D converter of this type. approximation A/D converter.
Figure 27.17 shows the block-schematic representation
of a successive approximation type of A/D converter. Since 27.8.6 Single-Slope, Dual-Slope and Multi-Slope
only one flipflop (in the counter) is operated upon at one A/D Converters
time, a ring counter which is nothing but a circulating

register (serial shift register with outputs Q and Q of the Figure 27.18 shows the block schematic representation
last flipflop connected to J and K inputs, respectively, of a single-slope A/D converter. In this type of A/D
of the first flipflop) is used to do the task. Referring to converter, one of the inputs to the comparator is a ramp
Fig. 27.16, the dark lines show the sequence in which the of fixed slope while the other input is the analog input
counter arrives at the desired count, assuming that 1001 to be digitized. The counter and the ramp generator are
is the desired count. This type of A/D converter is much initially reset to 0s. The counter starts counting with
faster than the counter-type A/D converter previously the first clock cycle input. The ramp is also synchro-
discussed. In an n-bit A/D converter, the counter-type nized to start with the first clock input. The counter
A/D converter on an average would require 2n1 clock stops when the ramp amplitude equals the analog input.
cycles for each conversion whereas successive approxima- In this case, the counter count is directly proportional
tion type A/D converter requires only n clock cycles. That to the analog signal. It is a low cost, reasonably high
Clk
Analog input
+ Timing Binary
input
Comp. and or
VA
control BCD counter
Reset
Ramp generator Latches
Digital output
Figure 27.18| Block schematic representation of a single-slope A/D converter.

Analog input
VA R C

S Comparator
VR
vo vcomp
+
Integrator + Clock
input
Q
FF N-Bit
CK
binary counter
CK
Qn1 Qn2 Qn3 Q1 Q0

Figure 27.19| Block schematic representation of a dual-slope A/D converter.
accuracy converter but it suffers from the disadvantage converter is very popular in digital voltmeters due
of loss of accuracy due to changes in the characteristics to its good conversion accuracy and low cost. Also,
of the ramp generator. This shortcoming is overcome in accuracy is independent of both the integrator
dual-slope integrating-type A/D converter. capacitance and the clock frequency as they affect
Figure 27.19 shows the block schematic arrangement the negative and positive slope in the same manner.
of a dual-slope A/D converter. The converter works as Yet another advantage of the dual-slope integrator
follows. Initially, switch S is connected to the analog A/D converter is that the fixed analog input integra-
input voltage VA to be digitized. The output of the inte- tion period results in rejection of noise frequencies
grator is mathematically given by Eq. 27.5: present in the analog input and having time periods
that are equal to or sub-multiple of the integration
V
VA dt = RCA t
1
vo = (27.5) time. Proper choice of integration time can therefore
RC achieve excellent rejection of (50/60) Hz line ripple.
The moment vo tends to go below zero, clock pulses

reach the clock input terminal of the counter which is
initially cleared to all 0s. The counter begins counting vo
from 0000 ... 0. At the (2n)th clock pulse, the counter is
again cleared; the 1-to-0 transition of MSB of the coun- T1 T2
ter sets a flipflop which controls the state of switch S 0 t
which now connects the integrator input to a reference
(V
VR
(T2 T1)
voltage of polarity opposite to that of analog input. The A
T
RC )
+
integrator output moves in the positive direction; the VA 1
RC
counter has again started counting after it got reset (say, vcomp t
RC
at t = T1). The moment, the integrator output tends 1
to exceed zero, the counter stops as the clock pulses
no longer reach the counters clock input. The counter
output at this stage (say, at t = T2) is proportional to
the analog input. 0 T1 T2 t
Figure 27.20 illustrates the concept further with Figure 27.20| Relevant waveforms in a dual-slope
the help of relevant waveforms. This type of A/D A/D converter.

fs
Quantization
Analog A/D noise
input converter
fs/2
(a)
Kfs
Digital filter
Analog A/D Digital Removed noise

input converter filter
fs /2 Kfs /2
(b)
Figure 27.21| (a) Quantization noise spectrum with sampling at the Nyquist rate and (b) the quantization noise
spectrum with oversampling.
27.8.7 SigmaDelta A/D Converter S

= (6.02n + 1.76) dB
N
Sigmadelta A/D converter employs a different concept
from what has been discussed so far in the case of vari- where n is the number of bits. The only way to increase
ous types of A/D converters. While the A/D converters the signal-to-noise ratio is by increasing number of bits.
covered so far rely on sampling of analog signal at the On the other hand, a sigmadelta converter attempts to
Nyquist frequency and encode the absolute value of the enhance signal to noise ratio by over sampling the analog
sample, in the case of sigmadelta A/D converter, the signal, which has the effect of spreading the noise spec-
analog signal is over sampled by a large factor (i.e., sam- trum over a much larger bandwidth, and then filtering
pling frequency is much larger than the Nyquist value) out the desired band.
and also it is not the absolute value of the sample but If the analog signal were sampled at a rate of Kfs,
the difference between the analog values of two succes- the quantization noise gets spread over DC to Kfs/2 as
sive samples that is encoded by the A/D converter. shown in Fig. 27.21(b). Here, K is a constant referred
In the case of A/D converters discussed prior to this to as oversampling ratio. Enhanced S/N ratio means
and sampled at Nyquist rate (fs), the root mean square higher resolution, which is achieved by other types of
(RMS) value of the quantization noise is uniformly dis- A/D converters by way of increasing number of bits.
tributed over the Nyquist band of DC to (fs/2) as shown Sigma-delta A/D converters use over sampling as well
in Fig. 27.21(a). The signal-to-noise ratio for a full-scale as they shape the quantization noise such that it falls
sine wave input in this case is given by outside the passband.
IMPORTANT FORMULAS
1. Resistive divider type n-bit D/A converter: The 4. Percentage resolution in an n-bit BCD-input D/A
analog output voltage is converter:
V1 20 + V2 21 + V3 22 + + Vn 2n 1 1
Percentage resolution = n/ 4
10 100 %
1
VA =
2n 1
2. Binary ladder type n-bit D/A converter: 5. The analog voltage at opamp output for current
V1 20 + V2 21 + V3 22 + + Vn 2n 1 steering mode of operation for RF = R is
VA =
2n DVref
3. Percentage resolution in an n-bit D/A converter:
where D is the fractional binary value of input digi-
100 %
1
Percentage resolution = tal word and Vref is the reference voltage.
2n 1

SOLVED EXAMPLES 657
6. Flash-type A/D converters: The number of com- 8. Counter-type A/D converter: The average conver-
parators required in an n-bit A/D converter is sion time in an n-bit counter-type A/D converter
is 2n1 clock cycles.
2n 1.(2n including one for polarity.)
9. Successive approximation A/D converter: The con-
7. Half-flash A/D converter: The number of compara- version time in an n-bit successive approximation
tors required in n-bit A/D converter is type A/D converter equates n clock cycles.
2 (2n/2) 10. S/N ratio of a n-bit Nyquist frequency A/D con-
verter is (6.02n + 1.76)dB
SOLVED EXAMPLES
1. An eight-bit D/A converter has a step size of 20 mV. 4. An eight-bit D/A converter produces an analog output
The full-scale output voltage in this case would be voltage of 50 mV for a digital input of 00000010.
Analog output for a digital input of 10000000 will be
(a) 5.1 V (b) 5.12 V
(c) 0.16 V (d) None of these (a) 1.6 V (b) 3.2 V
(c) 1.28 V (d) None of these
Solution. The step size is same as the resolution.
Therefore, Solution. It is given that logic `1 in bit position
1 3
next to LSB position produces an output of 50 mV.
8 V = 20 10 This implies that logic `1 in the LSB position,
(2 1) second-, third-, fourth-, fifth-, sixth-, seventh- and
where V is the full-scale voltage. This gives eighth-bit positions shall produce the outputs of
25 mV, 50 mV, 100 mV, 200 mV, 400 mV, 800 mV,
V = 20 103 255 = 5.1 V 1.6 V and 3.2 V, respectively. Therefore, the analog
Ans. (a) output for a digital input of 10000000 will be 3.2 V.
2. In the D/A converter discussed in Question 1, the Ans. (b)
percentage resolution is 5. The resolution of a 12-bit A/D converter having a
(a) 0.196% (b) 0.392% full-scale analog input voltage of 5 V is
(c) 0.125% (d) 0.250% (a) 1.22 mV (b) 2.44 mV
Solution. The percentage resolution for the D/A (c) 4.88 mV (d) 0.4 V
converter discussed in Question 1 is obtained as Solution. A 12-bit A/D converter resolves analog
follows: input voltage into 212 1 levels. The resolution is
nothing but the step size. Therefore, the resolution is
1 100
n 100% = 255 % = 0.392%
2 1
5
=
5000
=
5000
= 1.22 mV
Ans. (b) 2 12
1 4096 1 4095
Ans. (a)
3. The percentage resolution in case of a D/A con-
verter having a step size of 10 mV and full-scale 6. The average conversion time of an eight-bit
output of 5 V is counter-type A/D converter run by a 10 MHz clock
would be
(a) 0.1% (b) 0.4%
(c) 0.2% (d) 0.3% (a) 12.8 s (b) 25.5 s
(c) 80 ns (d) 800 ns
Solution.
Solution. The average conversion time of an n-bit
Step size
Percentage resolution = 100% counter-type A/D converter is given by 2n1 clock
Full-scale output
%
cycles. Therefore, the average conversion time is
10 103 27 clock cycles = 128 clock cycles = 128 0.1 s
=
100% = 12.8 s Ans. (a)
5
= 0.2% 7. A counter does not constitute a building block in
Ans. (c) one of the following A/D converter types.

(a) Successive approximation type A/D converter 9. The number of comparators required to build an
(b) Counter-type A/D converter eight-bit half-flash A/D converter is
(c) Tracking-type A/D converter
(a) 256 (b) 255 (c) 64 (d) 32
(d) Simultaneous A/D converter
Solution. The number of comparators required in
Solution. Simultaneous A/D converter does not n-bit half-flash A/D converter is
have a counter as a building block. All the other
three types of A/D converters employ a counter. 2 2n/2 = 2 24 = 32
Ans. (d) Ans. (d)
8. The maximum conversion time in one of the fol- 10. A 12-bit D/A convetrter has a resolution of 2.44
lowing types of A/D converter almost doubles for mV. Determine its analog output for a digital input
every bit added to the device. of 111111111111.
(a) Counter-type A/D converter (a) Indeterminate from given data (b) 10 V
(b) Tracking-type A/D converter (c) 5 V (d) 2.44 V
(c) Single-slope integrating-type A/D converter Solution. The resolution is
(d) Successive approximation type A/D converter Full-scale output voltage
Solution. The maximum conversion time in counter- 2n 1

type A/D converter is given by 2n. Every additional Therefore, the full-scale output voltage is
bit increases the conversion time by a factor of 2. 2.44 (2n 1) mV = 2.44 4095 mV = 10 V
Ans. (a) Ans. (b)
1. The conversion time of a certain A/D converter of logic `1 in the second and third bit positions shall
the successive approximation type for digitizing an produce outputs of 50 mV and 100 mV respectively.
analog signal equal to one-fourth of full-scale value The analog output for a digital input of 00000110
is 2.5 s. What would be the conversion time in s will be 150 mV.
for this converter for digitizing analog signal equal Ans. (150)
to one-half of full-scale output?
4. The speed of a motor is controlled using a computer.
Solution. The conversion time in the case of n-bit The computer output is interfaced to the motor input
successive approximation type A/D converter is equal through an n-bit D/A converter. If the motor speed
to n clock cycles. It is independent of the magnitude is to be controlled from 0 to 1000 rpm and if the
of analog input to be digitized and hence 2.5 s. motor speed is to be within 1.5 rpm of the desired
Ans. (2.5) speed, determine the size (in bits) of D/A converter.
2. A 12-bit binary input D/A converter and a 12-bit Solution. For an n-bit D/A converter, the number
BCD input D/A converter have the same full-scale of steps are 2n 1. This gives
1000
output voltage. What would be the resolution of
2n 1 666.67 or 2n 667.67
1.5
12-bit binary D/A converter in mV if the resolu-
tion of BCD input converter were 10 mV?
or
log 667.67
Solution. Full-scale output in case of BCD input
D/A converter = 10 999 mV = 9.99 V n
log 2
= 9.382
Therefore, the step size or resolution in case of
binary input D/A converter is Since n is an integer, n must at least be 10. Therefore,
the D/A converter should be a 10-bit D/A converter.
9.99 9.99 Thus, the size (in bits) of D/A converter is 10.
n mV = mV = 2.44 mV
2 1 4095 Ans. (10)
Ans. (2.44) 5. The data sheet of a certain eight-bit A/D converter
3. An eight-bit D/A converter produces an analog lists the following specifications: Resolution: Eight
output voltage of 25 mV for a digital input of bits; Full-scale error: 0.02% of full-scale; Full-scale
00000001. What will be the analog output (in mV) analog input: +5 V. Determine the total possible
for a digital input of 00000110? error (in millivolts).
Solution. It is given that logic `1 in LSB position Solution. An eight-bit A/D converter has the
produces an output of 25 mV. This implies that following number of steps:

28 1 = 255 steps 0.02 5000

Therefore, the quantization error is mV = 1 mV
100
5 5000
V = mV = 19.607 mV Therefore, the total possible error is
255 255
(19.607 + 1)mV = 20.607 mV
The full-scale error, which is 0.02% of full scale, is Ans. (20.607)
PRACTICE EXERCISE
1. The resolution of an eight-bit BCD-input D/A con- 7. A 10-bit successive approximation type A/D con-
verter with a full-scale output of 9.9 V will be verter has quantization error of 10 mV. The digital
output corresponding to analog input of 4.365 V
(a) 9.9 mV(b) 99 mV
would be
(c) 100 mV(d) None of these
(1 Mark) (a) 0110110110 (b) 0100100100
(c) 0110110100 (d) 1101101100
2. The conversion time in the case of an n-bit successive
approximation-type A/D converter is 0.8 s when
(2 Marks)
run by a 10 MHz clock. The number of bits n is 8. A successive approximation type A/D converter
when run by 1 MHz clock offered a conversion
time of 8 s. What would be the conversion time
(a) 8 (b) 10
(c) 12 (d) Indeterminate from given data
if the same converter were run by a clock of 5
(1 Mark)
MHz?
(a) 40 s (b) 1.6 s
3. The percentage resolution of an n-bit D/A con-
(c) 8 s
verter can be computed from
(d) None of these
100 n (1 Mark)
(a) n (b)
2 100
9. Arrange the following A/D converter types in the
(d) 1 100
2n1
(c) ascending order of conversion speed (i.e, A/D con-
100 2n 1 verter with highest conversion time or lowest speed
(1 Mark) to come first and all have the same number of bits):
4. An analog output from a certain six-bit D/A con- Simultaneous A/D converter; Counter-type A/D
verter for a digital input of 000100 is 400 mV.
converter; Successive approximation A/D con-
Determine the analog output for a digital input of verter; Half-flash A/D converter.
010101.
(a) C ounter-type A/D converter; Successive
(a) Indeterminate from given data (b) 2.1V approximation A/D converter; Half-flash A/D
(c) 2.65 V (d) 10.6 V converter; Simultaneous A/D converter
(1 Mark) (b) Simultaneous A/D converter; Half-flash A/D
5. Among the following types of A/D converters, converter; Counter-type A/D converter;
name the one in which the analog signal is sampled Successive approximation A/D converter
at a frequency much higher than the Nyquist rate. (c) Successive approximation A/D converter;
Counter-type A/D converter; Half-flash A/D
(a) Tracking-type A/D converter
converter; Simultaneous A/D converter
(b) Dual-slope integrating-type A/D converter
(d) Counter-type A/D converter; Successive
(c) Half-flash A/D converter
approximation A/D converter; Simultaneous
(d) Sigmadelta A/D converter
A/D converter; Half-flash A/D converter
(1 Mark)
(2 Marks)
6. Architecture of a 16-bit half-flash converter com-
prises of 10. A 0001 input to a four-bit D/A converter produces
a 1 V output. The analog output corresponding to
(a) two eight-bit-flash converters 1000 input would be
(b) four four-bit-flash converter
(c) modified form of 16-bit-flash converter (a) 4 V (b) 8 V
(d) None of these (c) 15 V (d) Indeterminate from given data
(1 Mark) (1 Mark)

1. What is the minimum resolvable analog signal in 4. What will be conversion time in s of an eight-
mV in the case of a 12-bit A/D converter for a full- bit successive approximation type A/D converter
scale analog input of 5 V? for an analog input of 2.0 V and operating at
(1 Mark) 1.0 MHz?
2. A four-bit D/A converter produces a full-scale (1 Mark)
output current of 1.5 mA. If the error is 0.1% of 5. What will be the conversion time (in s) in the
full scale, what would be the analog output current case of A/D converter discussed in Question 4 if
range for a digital input of 1100? the analog input were 4.0 V?
(2 Marks) (1 Mark)
3. What will be the resolution of an eight-bit A/D
converter in percent?
(1 Mark)
1. (c) The resolution of the given converter is The step number 436 will produce the D/A con-
9.9 verter output as follows:
99
V = 0.1 V = 100 mV 436 10 = 4360 mV = 4.36 V
2. (a) Conversion time in this case equals n clock Also, the step number 437 will produce a D/A
cycles. For 10 MHz clock, each cycle is for 0.1s. converter output of 4.37 V. The A/D converter will
Since the conversion time is given to be 0.8 s; the settle at step 436. The digital output will be the
A/D converter has eight bits. binary equivalent of (436)10, that is, 0110110100.
3. (d) This is the standard formula for calculating 8. (b) Conversion time is equal to n clock cycles where
percentage resolution of an n-bit D/A converter. n is number of bits. It is an eight-bit converter as
the clock period is 1.0 s and conversion time is
given to be 8.0 s. Multiplying the clock frequency
4. (b) The resolution is 100 mV. Therefore, the output
is obtained as follows:
by 5 will reduce clock period by a factor of 5, which
(1600 + 400 + 100)mV = 2100 mV = 2.1 V
reduces the conversion time by a factor of 5. Hence,
5. (d) Sigma-delta A/D converters are sampled at the answer is 8/5 s = 1.6 s.
a frequency much higher than Nyquist rate to 9. (a) Of the types mentioned in this case, the counter
increase the S/N ratio. It does so by spreading the type A/D converter is the slowest (average conver-
noise over a much larger bandwidth. sion time for n-bit converter = 2n1 clock cycles)
6. (a) It is inherent to internal architecture of a half- and simultaneous type A/D converter (conversion
flash A/D converter. time depending upon only the propagation delay)
is the fastest.
7. (c) The analog input voltage is 4.365 V; the resolu-
tion is 10 mV. Therefore, the number of steps is 10. (b) LSB corresponds to 1 V. The other higher order
bits therefore correspond to 2 V, 4 V and 8 V.
4.365
= 436.5 Thus, the analog output corresponding to 1000
10 103 input would be 8 V.
1. The resolution is Error is

5 1.5
0.1 = 1. 5 A
mV = 1.22 mV
4095 100
Ans. (1.22) The output current for digital input of 1100 is
1.2 mA. Considering the error, the output current
2. The resolution is range is therefore obtained as
1.5
mA = 0.1 mA 1198.51201.5 A
15 Ans. (1198.51201.5)

3. The resolution of eight-bit D/A converter (in per- 5. In successive approximation type A/D converter,
cent) is given by the conversion time is independent of magnitude
of analog input voltage. Therefore the conversion
% = 0.4 %
100 100
%= time is 8 s.
2 1
8 255
Ans. (8)
Ans. (0.4)
4. An eight-bit A/D converter of successive approxi-
mation type requires eight clock cycles. For 1 MHz
clock, the conversion time becomes 8 s.
1. The minimum number of comparators required to 3. A digital system is required to amplify a binary-
build an eight-bit-flash ADC is encoded audio signal. The user should be able to
control the gain of the amplifier from a minimum
(a) 8 (b) 63
to a maximum in 100 increments. The minimum
(c) 255 (d) 256
number of bits required to encode, in straight
(GATE 2003: 1 Mark)
binary, is
Solution. The number of comparators needed
for an n-bit flash A/D converter is given by 2n1.
(a) 8 (b) 6
(c) 5 (d) 7
This, of course, excludes one comparator required
(GATE 2004: 1 Mark)
for polarity.
Ans. (c)
Solution. From the given data, we have 2n 100,
2. The circuit shown in the following figure is a four-bit which gives n =7.
DAC. The input bits 0 and 1 are represented by 0 Ans. (d)
and 5V, respectively. The opamp is ideal, but all
the resistances and the 5V inputs have a tolerance 4. A four-bit D/A converter is connected to a free-
of 10% . The specification (rounded to the nearest running three-bit UP counter, as shown in the fol-
multiple of 5%) for the tolerance of the DAC is lowing figure.
R
R 1 k
Q2 D3
2R
D2
4R Vo
+ Q1 D1 +
1 k
R Q0 D0
8R
Clock 3-Bit 4-Bit
(a) 35%
counter DAC
(b) 20%
(c) 10% (d) 5%
Which of the waveforms shown in the following
four options will be observed at Vo?
Solution.
R R R R
Vo = VR d3 + d2 + d1 + d0
R 2R 4R 8R
R
Therefore, Vo = VR [constant] (a) (b)
R
The worst-case tolerance in Vo is

(c) (d)
1.1 1.1
1 100% = 35%
0.9
Ans. (a) (GATE 2006: 2 Marks)

Solution. Therefore,
5
Vo = 103 10 103 = 3.125 V
C /P 1 2 3 4 5 6 7 8
16
Counter 001 010 011 100 101 110 111 000 Ans. (c)
Input Statement for Linked Answer Questions 7
ofD/A 0001 0010 0011 1000 1001 1010 1011 0000 and 8: In the circuit shown in the following figure,
converter 1 2 3 8 9 10 11 0 the comparator output is logic `1 if V1 > V2 and is
logic `0 otherwise. The D/A conversion is done as
Therefore, the waveform given in (b) is the correct
per the relation:
answer.
3
Ans. (b) VDAC = 2n 1 bn V
n=0
and 6: In the D/A converter circuit shown in the where b3 (MSB), b2 ,b1 and b0 (LSB) are the coun-
following figure, VR = 10 V and R = 10 k . ter outputs. The counter starts from the clear state.
R R R i 2R VDAC 4-Bit D/A

VR converter
+5V Binary 2 Digit
2R 2R 2R to LED
2R R BCD
Clr display
4-Bit

Clk
+
up counter
Vin =
+ Vo 6.2V
Clock
7. The stable reading of the LED display is
5. The current i is
(a) 06 (b) 07
(a) 31.25 A (b) 62.5 A (c) 12 (d) 13
(c) 125 A (d) 250 A (GATE 2008: 2 Marks)
(GATE 2007: 2 Marks) Solution.
VDAC = 21 b0 + 20 b1 + 21 b2 + +22 b3
Solution. The negative terminal of the opamp
shown in the circuit can be considered to be at vir- = 0.5b0 + b1 + 2b2 + 4b3
tual earth as the non-inverting input is connected The counter output will start from 0000 and will
to ground. The resistive network can be simpli- increase by 1 LSB at every clock pulse as it moves
fied to prove VR is connected across a resistance from 0000 to 1111. The corresponding D/A converter
equal to R. Therefore, the current drawn from output voltage levels would be 0 V, 0.5 V, 1.0V, 1.5
VR = 10/(10 103) = 1 mA. This current is suc- V, 2.0 V, 2.5 V, 3.0 V, 3.5 V, 4.0 V, 4.5 V, 5.0 V, 5.5
cessively divided between two equal resistance V, 6.0 V, 6.5 V, 7.0 V and 7.5 V. The moment D/A
paths of 2R each. It can be proved that current converter output goes from 6.0 V to 6.5 V, the com-
parator output goes to LOW state thereby disabling
1
i = mA = 62.5 A
the clock signal. The corresponding counter output is
16 1101, which gives the reading of `13 in LED display.
Ans. (b) Ans. (d)
6. The voltage Vo is 8. The magnitude of the error between VDAC and
Vin at steady state in volts is
(a) 0.781 V (b) 1.562 V
(c) 3.125 V (d) 6.250 V (a) 0.2 (b) 0.3
(c) 0.5 (d) 1.0
Solution. The net current in the inverting termi- Solution. The magnitude of the error between
nal of the opamp is equal to D/A converter output and Vin is
1 1 5 6.5 6.2 = 0.3 V
+ mA = mA
4 16 16 Ans. (b)

CHAPTER 28
MICROPROCESSORS AND MEMORY DEVICES
This chapter discusses microprocessors and memory devices. The discussion is mainly in terms of operational funda-
mentals, architecture, programming and interfacing aspects of microprocessors with particular reference to 8085 micro-
processor. This is followed up by discussion on memory devices.
28.1 INTRODUCTION TO The memory stores the binary instructions and data
MICROPROCESSORS for the microprocessor. Memory can be classified as pri-
mary or main memory and secondary memory. Read/
write memory (R/WM) and read only memory (ROM)
A microprocessor is a programmable device that accepts are examples of primary memory and are used for exe-
binary data from an input device, processes the data cuting and storing programs. Magnetic disks and tapes
according to the instructions stored in the memory and are examples of secondary memory. They are used to
provides results as output. In other words, micropro- store programs and results after the completion of pro-
cessor executes the program stored in the memory and gram execution. Microprocessors do not execute pro-
transfers data to and from the outside world through grams stored in the secondary memory directly. Instead,
I/O ports. Any microprocessor based system essen- they are first copied on to the R/W primary memory.
tially comprises of three parts, namely, microprocessor, The input/output devices are means through which
memory and peripheral I/O devices. The microprocessor microprocessor interacts with the outside world. The com-
is generally referred to as the heart of the system as it monly used input devices include keyboards, A/D con-
performs all the operations and also controls the rest of verters, cameras, scanners, microphones and so on. LEDs,
the system. The three are interconnected by the data seven-segment displays, LCD displays, printers and moni-
bus, the address bus and the control bus. tors are some of the commonly used output devices.

664 Chapter 28: Microprocessors and Memory Devices
A bus is basically a communication link between the largest number processed for instance by a 16-bit inter-
processing unit and the peripheral devices. It is a group nal data bus is 65535. The data bus is labeled as D0, ...,
of wires that carry information in the form of bits. The Dn-1 where n is the data bus width in bits.
address bus is unidirectional and is used by the centre The control bus contains a number of individual lines
process unit (CPU) to send out address of the memory carrying synchronizing signals. `Bus here would nor-
location to be accessed. It is also used by the CPU to mally imply a group of lines working in unison. The con-
select a particular input or output port. It may control bus (if we call it a bus) sends out control signals
sist of 8, 16, 20 or even more number of parallel lines. to memory, I/O ports and other peripheral devices to
Number of bits in the address bus determines the maxi- ensure proper operation. It carries control signals such
mum number of data locations in the memory that can as memory read, memory write, read input port, write
be accessed. A 16-bit address bus for instance can access output port, hold, interrupt, etc. For instance, if it is
216 data locations. It is labeled as A0, ..., An-1 where n is desired to read the contents of a particular memory
width in bits of the address bus. location, the CPU first sends out address of that very
The data bus is bidirectional, that is, data flow occurs location on the address bus and a `memory read con-
both to as well as from microprocessor and peripherals. trol signal on the control bus. The memory responds by
The data bus size has a considerable influence on the outputting data stored in the addressed memory loca-
computer architecture as the parameters like the word tion onto the data bus. Ìnterrupt tells the CPU that
length and the quantum of data that can be manipulated an external device needs to be read or serviced. `Hold
at a time are determined by size of the data bus. There allows a device such as direct memory access (DMA)
is an internal data bus, which may not be of the same controller to take over the address and data busses.
width as the external data bus that connects the micro- Figure 28.1 shows the bus interface between the micro-
processor to I/O and memory. The size of the internal processor and its peripheral devices. The microproces-
data bus determines the largest number that can be pro- sor in this figure is an eight-bit microprocessor such as
cessed by the microprocessor in a single operation. The Intel 8085.
A15 Address bus

A0
8085
Micro-
processor RAM ROM
D7 Data bus
D0
Clk
RD
WR
RES
INTR
IO/M
Output Input
interface interface
Output Input
devices devices
Figure 28.1| Bus interface between the microprocessor and its peripheral devices.

28.2 MICROPROCESSOR ARCHITECTURE 665
28.2 MICROPROCESSOR found registers in most of the microprocessors include

ARCHITECTURE program counter (PC), instruction registers, buffer reg-
isters, status register, stack pointer, general purpose reg-
isters and temporary registers.
Figure 28.2 shows a simplified typical schematic arrange-
ment of a microprocessor. The figure shown is a gen- 28.2.2.1Program Counter (PC)
eralized one and is not the actual structure of any of
the commercially available microprocessors. The impor- The program counter is a register that stores address of
tant functional blocks of a microprocessor include the the next instruction to be executed and hence plays a cen-
following: tral role in controlling the sequence of machine instruc-
1. Arithmetic logic unit (ALU) tions that the processor executes. After the instruction
2. Register file is read into the memory, the PC is automatically incre-
3. Control unit mented by `1. This is of course with the assumption that
the instructions are executed sequentially. Its contents
Control are affected by JUMP and CALL instructions. In the case
Control unit bus of JUMP instruction, the PC is first loaded with the new
address and then incremented thereafter until another
Register file JUMP instruction is encountered. When the micropro-
ALU cessor receives an instruction to begin a subroutine, the
contents of the program counter are incremented by `1
Internal and are saved in the stack. The PC is loaded with the
bus address of the first instruction of the subroutine. Its con-
tents are incremented by `1 until a return instruction is
Data bus encountered. The saved stack contents are then loaded
Figure 28.2| Typical schematic arrangement of a into the PC and the program continues, executing each
microprocessor. instruction sequentially until another JUMP instruction
or a subroutine call is encountered. The interrupt pro-
cess also alters the contents of program counter.
28.2.1 Arithmetic Logic Unit (ALU)
28.2.2.2 Instruction Register
ALU is the core component of all microprocessors. It
performs the entire integer arithmetic and bit-wise logi-
An instruction register stores the code of the instruc-
cal operations of the microprocessor. ALU is a combina-
tion currently being executed. Control unit extracts
tional logic circuit and has two data input lines, a data
the operation code from the instruction register, which
output line and a status line. It gets data from the reg-
determines the sequence of signals necessary to perform
isters of the microprocessor, processes the data accord-
the processing required by the instruction.
ing to the instructions from the control unit and stores
the results in its output registers. All modern ALUs use
binary data in twos complement format. The integer
28.2.2.3 Buffer Register
arithmetic operations performed by the ALU include the
Buffer registers interface the microprocessor with its
addition and subtraction. It performs AND, OR, NOT
memory system. The two standard buffer registers are
and EX-OR logical operations. Some 16-bit, 32-bit and
memory address register (MAR) and memory buffer
64-bit microprocessors also perform the multiplication
register (MBR). MAR is connected to the address pins
and division operations. In other microprocessors, the
of the microprocessor and holds the absolute memory
multiplication and division operations are performed by
address of the data or instruction to be accessed. MBR,
writing algorithms using addition and subtraction opera-
also known as memory data register, is connected to the
tions. ALU also performs the bit shifting operations and
data pins of the microprocessor. It stores all data written
the comparison of data operations.
to and read from memory.
28.2.2 Register File 28.2.2.4 Status Register
Register file comprises of various registers used primarily The status register stores the status outputs of the
to store data, addresses and status information during result of an operation and gives additional information
the execution of a program. Registers are sequential about the result of an ALU operation. The status of bits
logic devices built using flip-flops. Some of the commonly stored in the status register tells about occurrence or

non-occurrence of different conditions and one or more 28.2.2.7 Temporary Registers

bits may be updated at the end of an operation. Each
bit is a Boolean flag representing a particular condition. They are used when data has to be stored during the
The most common conditions are the carry, overflow, execution of a machine instruction. They are completely
zero and negative. For instance, a `1 in the carry status hidden from the user of the microprocessor.
bit position shows that the result of the operation gener-
ates a carry. The significance of status register lies in the
fact that the condition code set by the status of differ- 28.2.3 Control Unit
ent bits in the status register form the basis of decision
making by the microprocessor during the execution of a A control unit governs and coordinates the activities of
program. different sections of the microprocessor and I/O devices.
It is responsible for controlling the cycle of fetching
machine instructions from memory and executing them.
28.2.2.5 Stack Pointer It also coordinates the activities of the input and output
devices. It is undoubtedly the most complex of all func-
A stack pointer is a register used to store the address of tional blocks of the microprocessor and occupies most of
a memory location belonging to the most recent entry in the chip area. Control unit is a sequential logic circuit,
the stack. A stack in fact is a block of memory locations which steps the processor through a sequence of syn-
designated for temporary storage of data. It is used to chronized operations. It sends a stream of control signals
save data of another general purpose register during and timed pulses to the components and external pins
execution of a subroutine or when an interrupt is serviced. of the microprocessor. As an illustration, to execute an
The data is moved from a general purpose register to instruction from the memory, the control unit sends out
the stack by a PUSH instruction at the beginning of a a Read command to the memory and reads the instruc-
subroutine call and back to the general purpose register tion (or data) that comes back on the data bus. The
by a POP instruction at the end of the subroutine call. control unit then decodes the instruction and sends
Microprocessors use a stack because it is faster to move appropriate signals to the ALU, the general purpose
data using PUSH and POP instructions than moving registers, the multiplexers, the de-multiplexers, the pro-
data to/from memory using MOVE instruction. gram counter and so on. If the instruction was to store
data in the memory, the control unit sends out address
of the memory location on the address bus, the data to
28.2.2.6 General Purpose Registers
be stored on the data bus and a `write command on a
control line.
There is a set of registers for general purpose use desig-
nated as general purpose registers. They are used explic- Control units are categorized into two types depending
itly to store data and address information. Data registers upon the way they are built. These include hard-wired
are used for arithmetic operations while the address and microcoded control units. Hard-wired controllers are
registers are used for indexing and indirect addressing. sequential logic circuits, the states of which correspond
These enhance processing speed of the microprocessor to the phases of the instruction execution cycle. In the
by avoiding large number of external memory read/ case of hard-wired controllers, there is an electronic cir-
write operations while an ALU operation is being per- cuitry in the control unit to generate control signals for
formed as it is much easier and faster to read from or each instruction. They are very compact and fast, but are
write into an internal register than to read from or write difficult to design. This design is also known as reduced
into an external memory location. Earlier microproces- instruction set computer (RISC) design. Microcoded
sors had only one register called accumulator for ALU control units are easy to design and execution of an
operations. It needed at least four assembly language instruction in this case involves executing a micropro-
instructions to perform a simple addition including car- gram consisting of a sequence of microinstructions. This
rying data from an external memory location to the design is also known as complex instruction set computer
accumulator, adding contents of accumulator to those (CISC) design. Microcoded control units offer more flex-
of another memory location, storing the result in the ibility as compared to hardwired control unit but they
accumulator and transferring the contents of the accu- are comparatively slower than hard-wired control units.
mulator back to the external memory location. With Figure 28.3 shows a more descriptive block diagram of a
the availability of more number of general purpose microprocessor. Multiplexers and de-multiplexers do not
registers, it would be possible to perform many ALU represent primary functions and are there to facilitate
operations without even a need to store data in external flow of data between different blocks and also between
memory. different blocks and the outside world.

28.3 BASIC MICROPROCESSOR INSTRUCTIONS 667
location to a register or from a register to a memory

location and so on. In fact, they are more correctly
referred to as data movement operations as the contents
Demultiplexer of the source are not transferred, but are copied into the
destination register without modifying the contents of
the source. It may be mentioned here that these opera-
General purpose tions do not affect the flags. Data transfer operations of
registers 8085 microprocessor are of three types, namely MOVE,
LOAD and STORE.
MOV destination, Copy data from the source

Multiplexer Multiplexer source to the destination location
LDA address Copy the data byte at
memory location specified
Function by 16-bit address into the
Arithmetic logic unit (ALU) accumulator
select
Status STA address Copy the data from the
accumulator to the memory
Status Result location specified by 16-bit
register address
Data bus
Stack pointer 28.3.2 Arithmetic Instructions
Arithmetic instructions performed by microprocessors

include addition, subtraction, multiplication, division,
Program Address bus comparison, negation, increment and decrement. It may
counter be mentioned here that most of the eight-bit micropro-
cessors do not support the multiplication and the divi-
sion operations. These operations are supported by the
Control Control bus 16-bit and 32-bit microprocessors. The arithmetic opera-
unit tions supported by the 8085 microprocessor are addi-
tion, subtraction, increment and decrement operations.
Figure 28.3| Descriptive block diagram of a Examples are given as follows:
microprocessor.
ADD R Adds the contents of the register
28.3 BASIC MICROPROCESSOR to accumulator
INSTRUCTIONS ADI eight- Adds the eight-bit data to
bit data accumulator
SUB R Subtracts the contents of register
Microprocessors perform the following basic operations:
from accumulator
1. Data transfer instructions
SUI eight-bit Subtracts eight-bit data from the
2. Arithmetic instructions
data contents of accumulator
3. Logic instructions
4. Control transfer instructions INR R Increments the contents of the
5. Machine control instructions register
DCR R Decrements the contents of the
28.3.1 Data Transfer Instructions register
Data transfer instructions transfer data from one

location designated as the source to another location 28.3.3 Logic Instructions
designated as destination. The data transfer could take
place from one register to another, from one memory Microprocessors can perform all the logic functions of hard-
location to another memory location, from a memory wired logic. The basic logic operations performed by all

microprocessors are AND, OR, NOT and EX-OR. The 28.3.4 Control Transfer Instructions
other logic operations include `shift and `rotate operations.
All these operations are performed on a bit-for-bit basis Microprocessors execute machine codes from one memory
on bytes or words. For instance, 11111111 AND 10111010 location to the next, that is, they execute instructions
equals 10111010 and 11111111 OR 10111010 equals in a sequential manner. Branch instructions change the
11111111. Some microprocessors also perform bit-level flow of the program either unconditionally or under
instructions such as `set bit, `clear bit and `complement certain test conditions. Branch instructions include
bit operations. It may be mentioned that logic operations JUMP, CALL, RETURN, and INTERRUPT.
always clear the carry and overflow flags, while the other JUMP instructions are of two types, namely, (1)
flags change to reflect the condition of the result. UNCONDITIONAL JUMP instructions and (2)
The basic shift operations are the `shift left and `shift CONDITIONAL JUMP instructions. If the micropro-
right operations. In the shift left operation also known cessor is so instructed as to load a new address in the
as arithmetic shift left, all bits are shifted one position program counter and start executing instructions at
to the left with the rightmost bit set to `0 and the left- that address, it is termed as an UNCONDITIONAL
most bit-transferred to the carry position in the status JUMP. In the case of a CONDITIONAL JUMP,
register. In the shift right operation also known as logic the program counter is loaded with a new instruc-
shift right, all bits are shifted one bit position to the tion address only if and when certain conditions are
right with the leftmost bit set to `0 and the rightmost established by the microprocessor after reading the
bit transferred to the carry position in the status reg- appropriate status register bits. CALL instructions
ister. If in the shift right operation, leftmost bit is left transfer the flow of the program to a sub-routine. The
unchanged, it is called arithmetic shift right. In a `rotate CALL instruction differs from JUMP instruction as
operation, the bits are circulated back into the register. CALL saves a return address (address of program
Carry may or may not be included. As an illustration, counter plus one) on the stack. The RETURN instruc-
in a `rotate left operation without carry, the leftmost tion returns control to the instruction whose address
bit goes to the rightmost bit position and in a `rotate was stored in the stack when CALL instruction was
right with carry included, the rightmost bit goes to the encountered. INTERRUPT is a hardware-generated
carry position and the carry bit takes the position of left CALL (externally driven from a hardware signal) or
most bit. Examples of logic instructions performed by a software-generated CALL (internally derived from
the 8085 microprocessor include the following: the execution of an instruction or by some internal
event). Examples of control transfer instructions of
8085 microprocessor are the following.
ANA R/M Logically AND the contents of
Register/memory with the contents
of accumulator
JMP 16-bit Change program sequence to
ANI eight- Logically AND the eight-bit data address location specified by 16-bit
bit data with the contents of the accumulator address
ORA R/M Logically OR the contents of JZ 16-bit Change program sequence to
Register/memory with the contents address location specified by 16-bit address
of accumulator if zero flag is set
ORI eight- Logically OR the eight-bit data with JC 16-bit Change the program sequence to
bit data the contents of the accumulator address the location specified by 16-bit
XRA R/M Logically EX-OR the contents of address if carry flag is set
Register/memory with the contents JNZ 16-bit Change the program sequence to
of accumulator address the location specified by 16-bit
XRI eight- Logically EX-OR the eight-bit data address if zero flag is reset
bit data with the contents of the accumulator JNC 16-bit Change the program sequence to
CMA Complement the contents of the address the location specified by 16-bit
accumulator address if carry flag is reset
RLC Rotate each bit in the accumulator CALL 16-bit Change the program sequence
to the left position address to the location of the subroutine
RRC Rotate each bit in the accumulator specified by the 16-bit address
to the right position RET Return to the calling program

28.4 ADDRESSING MODES 669
28.3.5 Machine Control Instructions

Operation Address Memory
Machine control instructions include HALT and NOP Data
instructions. Machine control instructions performed by
8085 microprocessor include the following:
(a)
HLT Stop processing and wait
NOP No operation 09H 31H
MOV A, 30H 07H 30H
22H 29H
28.4 ADDRESSING MODES (b)
Figure 28.4| Absolute addressing mode.
Microprocessors perform operations on data stored in
register or memory. This data is specified in the operand
Operation Data
field of the instruction. The data can be specified in vari-
Figure 28.5| Immediate addressing mode.
ous ways as direct data value or stored in some register
or memory location and so on. These are referred to
as the addressing modes of the microprocessor. In other
words, addressing mode as expressed in the instruction 28.4.3 Register Direct Addressing Mode
tells us as to how and from where the microprocessor
can get the data to act on. Addressing modes are of In register direct addressing mode, the data is accessed
direct relevance to compiler writers and to programmers by specifying the register name in which it is stored
writing the code in assembly language. Different micro- [Fig. 28.6(a)]. Operations on registers are very fast and
processor architectures provide a variety of addressing hence instructions in this mode require less time than
modes. RISC microprocessors have far less addressing absolute addressing mode instructions. As an example,
modes than CISC microprocessors. The most commonly the instruction MOV A, R1 in 8051 microprocessor
used addressing modes are absolute, immediate, register moves the contents of register R1 into accumulator [Fig.
direct, register indirect, indexed, implicit and relative 28.6(b)]. The contents of accumulator after the instruc-
addressing modes. They account for more than 90% of tion are 06H.
the total addressing modes.
Operation Register name Register
28.4.1 Absolute or Memory Direct Data
Addressing Mode
(a)
In absolute addressing mode, the data is accessed by
specifying its address in the memory [Fig. 28.4(a)]. This 09H R0
mode is useful for accessing fixed memory locations,
MOV A, R1 06H R1
such as memory mapped I/O devices. For example,
the instruction MOV A, 30H in 8085 microprocessor 22H R2
moves the contents of memory location 30H into accu- (b)
Figure 28.6| Register direct addressing mode.
mulator [Fig. 28.4(b)]. In this case accumulator has the
value 07H.
28.4.2 Immediate Addressing Mode 28.4.4 Register Indirect Addressing Mode
In immediate addressing mode, value of the operand is In all modes discussed so far, either the value of the data
held within the instruction itself (Fig. 28.5). This mode or its location is directly specified. Indirect addressing
is useful for accessing constant values in a program. It mode uses a register to hold the actual address where the
is faster than the absolute addressing mode and requires data is stored. That is, in this case the memory location
less memory space. For example, the instruction MVI A, of the data is stored in a register [Fig. 28.7(a)]. In other
#30H moves the data value 30H into the accumulator. words, in indirect addressing mode, the address is speci-
The sign `# in the instruction tells the assembler that fied indirectly and has to be looked up. This addressing
the addressing mode used is immediate. mode is useful when implementing the pointer data type

of high-level language. In 8085 microprocessor, R0 and 28.4.6 Implicit Addressing Mode and Relative
R1 registers are used as eight-bit index and DPTR as Addressing Mode
16-bit index. The mnemonic symbol used for indirect
addressing is @. As an example the instruction MOV In implicit addressing mode, no operand is used in the
A, @R0 moves the contents of memory location whose instruction and the location of the operand is obvious
address is stored in R0 into accumulator. The value of from the instruction itself. Examples include `Clear carry
accumulator in this example is 07H [Fig. 28.7(b)]. This flag, `Return from sub-routine and so on. The rela-
addressing mode can also be enhanced with an offset for tive addressing mode is used for JUMP and BRANCH
accessing data structures in data space memory. This is instructions only. In this, a displacement is added to the
referred to as register indirect with displacement. As an address in the program counter and the next instruction
example, the instruction MOVC A,@A+DPTR copies is fetched from the new address in the program counter.
the code byte at the memory address formed by adding This mode is particularly useful in connection with con-
the contents of A and DPTR to A. ditional JUMPs.
28.5 PROGRAMMING
Operation Register number Register Memory MICROPROCESSORS
Memory Data
Microprocessors execute programs stored in the memory

(a)
in the form of sequence of binary digits. Programmers do
not write the program in binary form but write it either
R0 09 31H in the form of a text file containing assembly-language
MOV A, @R0 30H 07 30H source code or using a high-level language. Programs
22 29H such as editor, assembler, linker and debugger enable the
user to write the program in assembly language, covert it
(b) into binary code and debug the binary code. Editor is a
Figure 28.7| Register indirect addressing mode.

program that allows the user to enter, modify and store
a group of instructions or text under a file name. The
assembly language source code is translated into object
code by a program called assembler. Linker converts the
28.4.5 Indexed Addressing Mode output of the assembler into a format that can be exe-
cuted by the microprocessor. The debugger is a program
In an indexed addressing mode, the address is obtained by that allows the user to test and debug the object file.
adding the contents of a register to a constant (Fig. 28.8). Programming in assembly language produces code
The instruction `Move the contents of Accumulator A which is fast and takes up little memory. However, it
to the memory location whose address is given by the is difficult to write large programs using assembly lan-
contents of register 1 plus 5 is an example of indexed guage. Another disadvantage of assembly language
addressing. Indexed addressing mode is useful whenever programming is that it is specific to a particular micro-
the absolute location of the data is not known till the processor. High-level language programming overcomes
program is running. This addressing mode is used to these problems. Some of the popular high-level languages
access a continuous table or array of data items stored in used include C, C++, Pascal, etc. Compiler programs
memory. The content of the constant gives the starting are primarily used to translate source code from a high-
address while the contents of the register determine the level language to a lower level language (e.g., assembly
element of the array or table to be accessed. If program language or machine language). Figures 28.9(a) and (b)
counter is used in the indexed addressing mode, it is show the various steps involved in executing assembly
known as PC relative addressing mode. language programs and programs written in high-level
languages, respectively.
Operation Register Constant Memory 28.6 RISC VERSUS CISC PROCESSORS

+ Data
Address
The primary goal of complex instruction set computer
Register (CISC) architecture is to complete a task in as few lines
Figure 28.8| Indexed addressing mode. of assembly as possible. This is achieved by building

28.7 8085 MICROPROCESSOR 671
Assembly source file MOV in hardware and MUL in software then there will
*.asm be considerable gain in speed, which is the basic fea-
ture of RISC technology. Examples of RISC processors
Assembler include Suns SPARC, IBM and Motorolas PowerPC,
Library
and ARM-based processors. The salient features of a
Linker/Locator RISC processor are as follows:
Object file List file
1. The microprocessor is designed using hardwired
control. For example, one bit can be dedicated for
Hex file one instruction. Generally, variable length instruc-
(a) tion formats require microcode design. All RISC
instructions have fixed formats, so no microcode
High level language is required.
source file *.c 2. RISC microprocessor executes most of the instruc-
tions in a single clock cycle. This is due to the fact
Compiler that they are implemented in hardware.
Assembly file 3. The instruction set typically includes only register-
Assembler to-register load and store.
Library
4. The instructions have simple format with few
Linker/Locator addressing modes.
Object file List file 5. RISC microprocessor has several general-purpose
registers and large cache memories, which support
very fast access of data.
Hex file 6. RISC microprocessor processes several instructions
(b) simultaneously and so includes pipelining.
Figure 28.9| Various steps involved in (a) executing
7. Software can take advantage of more concurrency.
assembly language programs and (b)
executing programs written in high-level
languages. 28.7 8085 MICROPROCESSOR
processor hardware that is capable of understanding and
executing a series of complex operations. In this case, Figure 28.10 gives the pin out configuration and Fig.
each instruction can execute several low-level instruc- 28.11 shows the block diagram of 8085 microprocessor.
tions. One of the primary advantages of this system is Table 28.1 lists the pin details.
that the compiler has to do very little work to translate
a high-level language statement into assembly language.
X1 1 40 VCC
Because the length of the code is relatively short, very 1 24
X2 2 39 HOLD
little RAM is required to store instructions. In nutshell,
RESET OUT 3 38 HLDA
the emphasis is to build complex instructions directly
SOD 4 37 Clk(OUT)
into the hardware. Examples of CISC processors include
SID 5 36 RESET IN
the following: CDC 6600, System/360, VAX, PDP-11,
6 35
Motorola 68000 family, and Intel and AMD 86 CPUs.
TRAP READY
RST 7.5 7 34 IO/M
Reduced instruction set computer (RISC) is a micropro- RST 6.5 8 33 S1
cessor that emphasizes on simplicity and efficiency. RISC RST 5.5 9 32 RD
designs start with a necessary and sufficient instruction INTR 10 31 WR
set. The objective of any RISC architecture is to maxi- INTA 11 30 ALE
mize speed by reducing the number of clock cycles per AD0 12 29 S0
AD1 13 28 A15
instruction. Almost all computations can be done from a
AD2 14 27 A14
few simple operations. The goal of RISC architecture is
AD3 15 26 A13
to maximize the effective speed of a design by performing
AD4 16 25 A12
infrequent operations in software and frequent functions in A11
AD5 17 24
hardware, thus obtaining net performance gain. AD6 18 23 A10
To understand this phenomenon, let us consider any AD7 19 22 A9
assembly-level language program. It has been observed VSS 20 21 A8
that it uses MOV instruction much frequently as com-
pared to MUL. So if the architectural design implements Figure 28.10| Pin-out configuration of 8085.

INTR INTA RST 6.5 TRAP SID SOD

RST 5.5 RST 7.5
Serial I/O
Interrupt control
control
8-Bit internal data bus
(8) (8) Flag (5) Instruction(8) B (8) C (8)

Accumulator Temp.reg. flip-flops register Reg Reg
D (8) E (8)
Register array
Reg Reg
(8) Instruction H (8) L (8)
Reg Reg
Arithmetic decoder Stack (16)
logic and pointer
unit machine Program (16)
(ALU) cycle counter
encoding Incrementer/ (16)
Decrementer address latch
Power { +5V
supply GND
(8) Address/(8)
X1 Timing and Control Address buffer data buffer
Clk
X2 GEN CONTROL STATUS DMA RESET
A15-A8
ADDRESS BUS AD7 -AD0
Clk OUT RD HOLD
WR ALE S0 S1 IO/M HLDA RESET OUT ADDRESS/DATA BUS
READY RESET IN
Figure 28.11| Block diagram of 8085.
Table 28.1| Pin details of 8085.
Signals Description
Address bus (12-19, A 16-bit address bus. The lower eight bits are multiplexed with the data bus. The
21-28) most significant eight bits of the memory address (or I/O address) are denoted by
A8-A15. The lower eight bits of the memory address (or I/O address) appear on the
multiplexed address/data bus (AD0-AD7) for the first clock cycle of the machine
cycle. It then becomes the data bus during the second and third clock cycles
Data bus (12-19) Eight-bit data bus is multiplexed with lower eight bits of the address bus (AD0-AD7)
Control and Status Signals
ALE (Address latch It is a positive-going pulse during the first clock state of the machine cycle that
enable) (30) indicates that the bits on AD0-AD7 are address bits. It is used to latch the low-order
address on the on-chip latch from the multiplexed bus
READ RD (32)( ) ( )
A LOW on RD indicates that the selected memory or I/O device is ready to be read
and the data bus is available for data transfer
WRITE WR (31) ( ) A LOW on WR indicates that data on the data bus are to be written into a selected
memory or I/O location. Data is set up at the trailing edge of the WR signal
IO/ M (34) This is a status signal that is used to differentiate between I/O and memory
operations
S1 and S0 (33, 29) These are status signals and can identify various operations
(Continued)

28.7 8085 MICROPROCESSOR 673

Signals Description
Power Supply and Clock Frequency
VCC (40) + 5V
VSS (20) Ground
X1, X2 (1,2) A crystal, LC or RC network is connected at these two pins to drive the internal clock
generator. X1 can also be an external clock input from a logic gate. The frequency is
internally divided by 2 to give the internal operating frequency of the processor. The
crystal frequency must be at least 1 MHz and must be twice the desired internal clock
frequency
CLK (OUT) - clock This output signal can be used as a system clock for devices on the board. The period
output (37) of CLK (OUT) is twice the X1, X2 input period
Interrupts and Other Operations: 8085 has Five Interrupt Signals
INTR (10), INTA (11) This is a general-purpose interrupt signal, The microprocessor issues an interrupt
acknowledge signal (INTA) when the interrupt is requested
RST 7.5 (7) These are restart interrupts. These are vectored interrupts and transfer the program
RST 6.5 (8) control to specific memory locations
RST 5.5 (9)

TRAP (6) It is a non-maskable interrupt and has the highest priority
In addition to these interrupts RESET, HOLD and READY pins accept externally initiated
signals as inputs
HOLD (39) A HOLD signal indicates that another master device is requesting the use of data and address
HLDA (38) buses. The microprocessor, upon receiving the HOLD request, will relinquish the use of the
bus after completion of the current bus transfer. It sends the HOLD ACKNOWLEDGE
(HLDA) signal, indicating that it will relinquish the bus in the next clock cycle
READY (35) A READY signal is used to delay the microprocessor READ or WRITE cycles until a
slow-responding peripheral is ready to send or accept data. If READY is HIGH during
the READ or WRITE cycle, it indicates that the memory or peripheral is ready
to send or receive data. If READY is LOW, the processor will wait for an integral
number of clock cycles for READY to go to HIGH
RESET IN (36) A LOW on the RESET IN pin causes the program counter to be set to zero, the buses
RESET OUT (3) are tristated and the microprocessor is reset. RESET OUT indicates microprocessor is
being reset
Serial I/O Ports
SID (5) Serial input data
SOD (4) Serial output data
28.7.1 8085 Registers 3.B and C registers: 8085 has eight-bit B and C regis-
ters which can be used as one 16-bit BC register pair.
The 8085 microprocessor has the following registers: 4.D and E registers: 8085 has eight-bit D and E regis-
1. Accumulator: 8085 microprocessor has an eight-bit ters which can be used as one 16-bit DE register pair.
accumulator. 5.H and L registers: 8085 has eight-bit H and L regis-
2. Flag register: 8085 has an eight-bit flag register ters which can be used as one 16-bit HL register pair.
containing five one-bit flags, namely, sign, zero, 6. Stack pointer: 8085 has a 16-bit stack pointer.
auxiliary carry, parity and carry. 7.Program counter: 8085 has a 16-bit program counter.

28.7.2 Addressing Modes
An 8085 microprocessor has four addressing modes: (1) CPU Volatile

register addressing mode, (2) register indirect address- registers memories
ing mode, (3) direct addressing mode and (4) immediate Cache
addressing mode. memory
Random access memory
(RAM)
28.7.3 8085 Instructions
Read only memory
(ROM) Non-volatile
An instruction is a binary pattern designed inside a memories
microprocessor to perform a specific function. The entire Hard drives/Removable discs
group of instructions a microprocessor can perform is
Figure 28.12| Various types of memories present in a
referred to as its instruction set. Instruction cycle is
defined as the time required for completing the execution
typical computer system.
of an instruction. The 8085 instruction cycle consists of
one to six machine cycles. Machine cycle is defined as the instructions are written over them. So, same data can be
time required for completing one operation of accessing accessed repeatedly if so desired and same instructions
memory, I/O and so on. This will comprise of three to can be executed repeatedly if so required. This is what
six T-states, which is defined as one sub-division of the is called stored program concept. The primary memory
operation performed in one clock period. of a computer further comprises of process registers,
random access memory (RAM), cache memory and read
only memory (ROM). Process registers are memory cells
28.8 MEMORY DEVICES built into the CPU that contain the specific data needed
by the CPU. Cache memory is basically a type of RAM
memory.
A computer memory refers to components, devices, chips RAM is a `read/write memory where the data
and recording media that are used for temporary, semi- can be read from or written into any of the memory
permanent and permanent storage of data. As mentioned locations regardless of the order in which they are
in the previous section, there are several types of memory arranged. Therefore, all the memory locations in a
devices used in a computer. These include RAM, ROM, RAM can be accessed at the same speed. RAM is used
cache, flash memory, hard disk, floppy disk, CDs, etc. to store data, program instructions and the results of
The memory devices can be broadly classified into two any intermediate calculations during the execution of
types, namely, the primary memory and the secondary a program. Also, same data can be read any number
storage. Figure 28.12 shows the various types of memory of times and different data written into same memory
devices present in a typical computer system. It may be location with every fresh data item over-writing the
mentioned here that in computer terminology memory existing one. It is typically used for short-term data
usually refers to RAM and ROM and the term `stor- storage as it cannot retain data when the power is
age refers to hard disk, floppy disk and CDs. Primary turned off. RAM is available in the form of ICs as
memory devices such as ROM and RAM are discussed in well as in form of plug-in modules. The plug-in mod-
detail in the following sections. ules are small circuit boards containing memory ICs
and having input and output lines connected to an
edge connector. They are available as single in-line
28.9 PRIMARY MEMORY memory modules (SIMMs) and dual in-line memory
modules (DIMMs). More than one memory ICs (or
chips) can be used to build the RAM for larger sys-
The primary memory holds the program instructions tems. The capacity or size of a RAM is measured in
for the program to be executed, the input data to be bytes. RAM chips are available in the memory capac-
processed and the intermediate results of any calcula- ities ranging from 2 kB to as much as 16 GB. One kB
tions when processing is being done. Primary memory of memory equals 210 = 1024 bytes, one MB memory
is also used for storing BIOS and start-up programs. equals 220 bytes and one GB memory equals 2 30 bytes.
When a program and data are entered into a computer, The words kilo (k), mega (M) and giga (G) have been
the control unit directs them to the primary memory. used as 2 10, 220 and 2 30 are approximately equal to
Each program instruction and each data item is stored 1000, 1000000 and 10 9 respectively. As an illustra-
in a memory location that has a unique address. These tion, a microcomputer with a 64 kB of RAM has
data and instructions are held till new data items and 64 2 10 = 2 6 2 10 = 2 16 = 65536 bytes of memory.

28.10 RANDOM ACCESS MEMORY (RAM) 675
The two categories of RAM are static RAM (SRAM) Select

and the dynamic RAM (DRAM).
Data in Data out
In the case of ROM, instructions can be written
into the memory only once at the manufacturers
premises. These instructions can however be read from
a ROM as many times as desired. Once it is written, a
ROM cannot be written into again. The contents of
a ROM can thus be accessed by a CPU but cannot be Figure 28.13| Basic SRAM memory cell.
changed by it. The instructions stored on a ROM vary
with the type of application it is made for. The ROM
for a general purpose microcomputer for instance, SRAMs can be broadly classified as asynchronous
would contain system programs such as those designed SRAM and synchronous SRAM. Asynchronous
to handle operating system instructions. In the case of SRAMs are those, whose operations are not synchro-
some special types of ROMs, it is possible for the user nized with the system clock, that is, they operate
to have his own instructions stored on the ROM as per independent of the clock frequency. In these RAMs,
his requirements. Such ROM chips are called program- `Data in and `Data out are controlled by address
mable read only memories (PROMs). PROM contents transition. Synchronous RAMs are those whose tim-
once programmed cannot be changed. However, there ings are initiated by clock edges. Also Àddress, `Data
are some special types of PROMs whose contents in, `Data out and all other control signals are syn-
can be erased and then reprogrammed. These are chronized with the clock signal. Synchronous RAMs
known as erasable programmable read only memories normally have an address burst feature, which allows
(EPROMs). the memory to read and write at more than one loca-
tion using a single address. Both synchronous and
asynchronous SRAMs are available in bipolar, MOS
28.10 RANDOM ACCESS MEMORY and BiCMOS technologies. While bipolar SRAM offers
(RAM) relatively higher speed of operation, MOS technology
offers higher capacity and reduced power consump-
tion. Figures 28.14(a) and (b), respectively, show the
In this section, we shall discuss at length types of RAM basic bipolar memory cell and the MOS (NMOS more
and their basic construction, properties, applications and specifically) memory cell.
so on. RAM has three basic building blocks, namely,(1)
an array of memory cells arranged in rows and columns
with each memory cell capable of storing either a `0 or
a `1, (2) an address decoder and (3) a read/write con- +VDD
trol logic. Depending upon the nature of memory cell +VCC
used, there are two types of RAM, namely, static RAM
(SRAM) and dynamic RAM (DRAM). In SRAM the
memory cell is essentially a latch and can store data
indefinitely as long as the DC power is supplied. DRAM
on the other hand, has a memory cell that stores data
in the form of charge on a capacitor. Therefore, DRAM
cannot retain data for long and hence needs to be
refreshed periodically. SRAM has higher speed of opera-
tion than DRAM but has lesser storage capacity.
28.10.1 Static RAM (SRAM)
As mentioned before, the basic element of SRAM is a

latch memory cell. Figure 28.13 shows a basic SRAM
memory cell. The memory cell is selected by setting the (a) (b)
`Select line active. The data bit is written in to the cell
by placing it on the `Data in line and is read from the Figure 28.14| (a) Basic bipolar memory cell; (b) Basic
`Data out line. MOS memory cell.

28.10.1.1Asynchronous SRAM are `1 and `0, respectively, while during the `write
operation it is `0 and `0, respectively. During the `read
Figure 28.15 shows the typical architecture of 64 8 operation, the input buffers are disabled and the contents
asynchronous SRAM. It is capable of storing 64 words of the selected register appear at the output. During the
of eight bits each. The main blocks include six-line to `write operation, the input buffers are enabled and the
64-line address decoder, I/O buffers, 64 memory cells output buffers are disabled. The contents of the input
and control logic for read/write operations. The memory buffers are loaded into the selected register whose previ-
cells in a row are represented as a register. Each register ous data is overwritten by the new data. The output
is an eight-bit register and can be read from as well as buffers being tri-state are in high impedance state during
written into. As can be seen from the figure, all the cells the `write operation. CS = 1 deselects the chip and
inside the same register share the same decoder output both the input and output data buffers get disabled
line, also referred to as `row line. The control functions and go to the high impedance state. The contents of
are provided by R/W (read/write) and the CS (chip memory in this case remain unaffected. The `chip select
select) inputs. R/W and CS inputs are also referred inputs are particularly important when more than one
to as WE (write enable) and CE (chip enable) inputs, RAM memory chips are combined to get larger memory
respectively. The `Data input and `Data output lines capacity.
are usually combined by using common ìnput/output In the case of larger SRAM memories, there are two
lines in order to conserve the number of pins on the IC address decoders, one for rows and one for columns. They
package. are referred to as row decoders and column decoders,
The memory is selected by making CS = 0. During respectively. A part of the address lines are fed to the row
the `Read operation, the status of R / W and CS pins decoder and the rest of the address lines are fed to the
Data input
Input R/W
buffers
0 Register `0
A5
1 Register `1
A4
A3 6-Line
Address to
inputs 64-Line CS
A2 decoder
A1
A0
63 Register `63
Output
buffers
Data output
Figure 28.15| Typical architecture of 64 8 asynchronous SRAM.

Data input

R/W
CS
Input buffers
0 1 0
Memory array
Address Row (128 rows Output Data
lines decoder 128 columns buffers output
8 bits)
128
1 128
Column decoder
Address
lines
Figure 28.16| Typical architecture of 16K 8 asynchronous SRAM.
column decoder. Figure 28.16 shows the architecture of a Complete It is defined as the time interval for
typical 16K 8 asynchronous SRAM. The memory cells write cycle which a valid address code is applied
are arranged in eight arrays of 128 rows and 128 columns time (tWC) to the address lines during `write
each. Memories with a single address decoder are referred operation.
to as two-dimensional memories and those with two decod-
ers are referred to as three-dimensional memories. Write Pulse It is the time for which R/W is held
Width (tW) `LOW during `write operation.
Figures 28.17(a) and (b) show the timing diagrams
during `read and `write operations, respectively. The dia- Address It is the time interval between
grams are self-explanatory. Read and write cycle time inter- set-up time appearance of a new address and
vals of few nano-seconds to a few tens of nanoseconds are (tAS) R/W going `LOW.
common in the case of asynchronous SRAMs. The different
Data set-up It is defined as the time interval for
timing intervals shown in the diagram are defined as follows:
time (tDS) which R/W must remain `LOW
Complete It is defined as the time interval for after valid data is applied to the data
read cycle which a valid address code is applied inputs.
time (tRC) to the address lines during the `read
Data hold It is defined as the time interval for
operation.
time (tDH) which valid input data must remain
RAM It is defined as time lapse between on the data lines after the R/W
access time application of new address input input goes `HIGH.
(tACC) andappearance of valid output
data. Address It is defined as the time interval for
hold time which the valid address must remain
Chip enable It is defined as the time taken by interval on the address lines after the R/W
access time RAM output to go from Hi-Z state (tAH) input goes `HIGH.
(tCO) to a valid data level once CS is
activated. Address It is defined as the required time
hold time interval after which R/W can go
Chip disable It is defined as the time taken by
interval `LOW after a valid address appears
access time RAM to return to Hi-Z state after
(tAS) on the address lines.
(tOD) CS is inactivated.

tRC
1
Address New address valid
inputs
0
tACC
R/W 1
CS 1
tCO tOD
Data Hi-Z state Data Hi-Z state

output vaild
to bus
t0 t1 t2 t3 t4
(a)
tWC
1
Address
New address valid
inputs
0
tAS tAH
R/W 1
tW
CS 1
tDS
Data Hi-Z state Data Hi-Z state

input valid
tDH
(b)
Figure 28.17| Timing diagram during (a) read operation and (b) write operation.

28.10.1.2Synchronous SRAM decoder block and R / W and CS are the same as in the
case of asynchronous SRAM. As mentioned before, most
Synchronous RAM as mentioned before is synchro- synchronous RAMs have address burst feature. In this case
nized with the system clock. In the case of a computer when an external address is latched to the address register,
system, it operates at the same clock frequency at which a certain number of lowest address bits are applied to the
the microprocessor operates. This synchronization of the burst logic. Burst logic comprises of a binary counter and
microprocessor and memory ensures faster execution EX-OR gates. The output of the burst logic which basi-
speeds. The basic difference between the architecture of cally produces a sequence of internal addresses is fed to the
synchronous and asynchronous RAMs is that synchro- address bus decoder. In the case of a two-bit burst logic,
nous RAM makes use of clocked registers to synchronize the internal address sequence generated is given by A1A0,
Àddress, R / W , CS and `Data in lines to the system A1 A0 , A1A0, A1 A0 where A0 and A1 are the address
clock. Figure 28.18 shows the basic architecture of a bits applied to the burst logic. The burst logic shown in
16K 8 synchronous SRAM with burst feature. As we can Fig. 28.18 is also a two-bit logic.
see from the figure the memory array block, the address
2-Bit burst logic
Burst
control Binary
counter
Q1 Q0
A0 A1
CLK A0 Address
decoder
(14 line- Memory array
to-16K (16K 8)
Address decoder)
register
A13
A0-A13
Address lines
Data Data
input output
WE Write register register
register
Data
I/O Output
control
buffers
CS Enable
register
{
OE
Data
I/O
lines
(I/O0 - I/O7)
Figure 28.18| Architecture of a 16K 8 synchronous RAM.

28.10.2 Dynamic RAM (DRAM) There are two basic modes of refreshing the memory,
namely, the burst refresh and distributed refresh mode.
The memory cell in the case of a DRAM comprises of a In burst refresh mode, all rows in the memory array
capacitor and a MOSFET. The cell holds a value of `1 are refreshed consecutively during the refresh burst
when the capacitor is charged and `0 when discharged. cycle. In distributed refresh mode, each row is refreshed
The main advantage of this type of memory is its higher at intervals interspaced between `read and `write
density or more bits per package as compared to SRAM. operations.
This is because the memory cell is very simple as com-
pared to that of SRAM. Also the cost per bit is less in the
case of DRAM. The disadvantage of this type of memory 28.10.2.1DRAM Architecture
is the leakage of charge stored on the capacitors of vari-
ous memory cells when they are storing a `1. To prevent The architecture of DRAM memory is somewhat dif-
this from happening, each memory cell in a DRAM needs ferent from that of SRAM memory. Row and column
to be periodically read, its charge (or voltage) compared address lines are usually multiplexed in a DRAM. This is
with a reference value and then charge restored to the done to reduce the number of pins on the package. Row
capacitor. This process is known as `memory refresh and address select (RAS) and column address select (CAS)
is done approximately in every 5-10 ms. inputs are used to indicate whether a row or a column
Figure 28.19 shows the basic memory cell of DRAM and is to be addressed. Address multiplexing is particularly
its basic principle of operation. The MOSFET acts like a attractive for higher capacity DRAMs. A 4M RAM,
switch. When in the `write mode (R / W = 0) the input for instance, would require to have 22 address inputs
buffers are enabled while the output buffers are disabled. (222 = 4M).
When `1 is to be stored in the memory, `Data in line Figure 28.20 shows the architecture of a 16K 1
must be in `HIGH state and the corresponding `Row line DRAM. The heart of a DRAM is an array of single
should also be in `HIGH state so that the MOSFET is bit memory cells. Each cell has a unique position vis-
switched ON. This connects the MOSFET to the `Data -vis row and column. Other important blocks include
in line and it charges to a positive voltage level. When address decoders (row decoder and column decoder),
`0 needs to be stored, `Data in line is `LOW and the refresh control, address latches (row address latch and
capacitor also acquires the same level. When the `Row column address latch). As can be seen from the figure,
line is taken to `LOW state, the MOSFET is switched seven address lines are time multiplexed at the begin-
OFF and disconnects the `MOSFET from the bit line. ning of the memory cycle by the RAS and CAS lines.
This traps the charge on the capacitor. When in `read First, the seven bit address (A0-A6) is latched into
mode (R / W = 1) the output buffers are enabled while the row address latch and then the seven-bit address
the input buffers are disabled. When the `Row line is is latched to the column address latch (A7-A13). They
taken to `HIGH logic, the MOSFET is switched ON and are then decoded to select the particular memory loca-
connects the capacitor to the `Data out line through tion. Larger word sizes can be achieved by combin-
the output buffer. Refresh operation is performed by ing more than one chip. This is discussed in the next
setting R / W = 1 and by enabling the refresh buffer. section.
Column
Refresh
Refresh
buffer
Column
Row
Row
Data out
MOSFET Output buffer
R/W sense amplfier
Capacitor
Data in
Input buffer
Figure 28.19| Basic memory cell of DRAM.

Refresh
Refresh control and
circuitry timing signals
1
2
Multiplexed Memory array
address bus Data Row 128 Rows
A0 selector decoder 128 Columns
Row 127
address 128
A6 latch 1 2 127 128
1
2
A7 I/OBuffer
Column Column and
address decoder sense Data out
A13 latch amplifiers Data in
127
128
CAS
RAS R/W CS
Figure 28.20| Architecture of 16K 1 DRAM.
Figures 28.21(a) and (b), respectively, show the timing output (EDO) DRAM, (3) burst extended data output
diagrams for read and write operations. The diagrams (BEDO) DRAM and (4) synchronous (S) DRAM. In
are self-explanatory. DRAMs are relatively slower than FPM DRAM, the row address is specified only once for
SRAMs. Typical access time is in the range of 100-250 ns. access to several successive column addresses. Hence, the
read and write times are reduced. EDO DRAM is simi-
28.10.2.2Types of DRAM lar to FPM DRAM with the additional feature that a
new access cycle can be started while keeping the data
DRAM memories can be further classified as follows: output of the previous cycle active. BEDO DRAM is
(1) Fast page mode (FPM) DRAM, (2) extended data an EDO DRAM with address burst capability. All the
1
MUX
0
1
RAS
0
1
CAS
0
1
Row
Address address Column address
R/W 1
Data Data Hi-Z

output valid state
(a)
1
MUX
0
28-Chapter-28-Gate-ECE.indd 681 1 6/4/2015 2:46:22 PM
R/W 1
Data Data Hi-Z

output valid state
(a)
1
MUX
0
1
RAS
0
1
CAS
0
1
Address Row Column
0
R/W 1
Hi-Z
Data
state
(b)
Figure 28.21| Timing diagrams of (a) read operation and (b) write operation.
DRAM discussed till now are asynchronous DRAMs and normally require that all of systems main memory has
their operation are not synchronized with the system speed comparable to that of the CPU. It may not be eco-
clock. SDRAM as the name suggest, is a synchronous nomical to have all of main memory as a high speed one in
DRAM whose operation is synchronized with the system many systems. It is where cache memory comes in.
clock. Cache memory is a block of high speed memory
located between main memory and the CPU. The cache
28.10.3 RAM Applications memory block is the one that communicates directly with
the CPU at high speed. It stores the most recently used
One of the major applications of RAM is its use in cache instructions or data. When the processor needs data, it
memories. It is also used as main memory to store tem- checks in high speed cache to see if the data is there. If
porary data and instructions in a computer. it is there, called a `Cache hit, the CPU accesses the
data from the cache. If not there, called a `Cache Miss,
28.10.3.1Cache Memory then the CPU retrieves it from relatively slower main
memory. Cache memory mostly uses SRAM chips but it
Advances in microprocessor technology and also the soft- can also use DRAM.
ware have enhanced manifold the application potential of There are two levels of cache memory. First is Level-1
present day computers. These enhanced performance fea- cache (L1 or primary or internal cache). It is physically a
tures and increased speed can be optimally utilized to the part of the microprocessor chip. Second is Level-2 cache
maximum only if the computer has the required capacity of (L2 or secondary or external cache). It is in the form of
main (or internal) memory. The computers main memory, memory chips mounted external to the microprocessor.
as we know, stores program instructions and data that It is larger than L1 cache. L1 and L2 cache memories are
the CPU needs during normal operation. In order to get of the sizes in the range of 2 KB to 64 KB and 256 KB
the maximum performance from the system, this would to 2 MB, respectively. Some systems have higher level

28.11 READ ONLY MEMORY (ROM) 683
Clk
Central Cache
processing controller
unit
Main Hard
(CPU) memory disk
L1Cache L2 Cache
Address
bus
Data
bus
Figure 28.22| Cache memory in a computer system.
caches L3, L4 etc. but L1 and L2 are most common. a binary address is applied at its input lines. Five-bit
Figure 28.22 shows the use of L1 and L2 cache memories address code (A4A3A2A1A0) is needed to address 32
in a computer system. memory cells. As an illustration, an address code of
10011 will identify 19th row. The output is read from the
column lines. The data placed on the internal data bus
28.11 READ ONLY MEMORY (ROM) by the memory cells is fed to output buffers. CS is an
active low input used to select the memory device. In the
case of larger memories, the address decoder comprises
ROM is a non-volatile memory that is used for perma- of row as well as column decoders. Let us consider a 2K
nent or semi-permanent storage of data. The contents of bit ROM device with 256 8 organization. The memory
ROM are retained even after the power is turned off. In is arranged in the format of 32 64 matrix instead of
this section, we shall be discussing at length the ROM 256 8 matrix. Five of the address lines are connected
architecture, types of ROM and typical applications. to the row decoder and rest three of the lines are con-
nected to the column decoder. Row decoder is a 1-of-32
28.11.1 ROM Architecture decoder and it selects one of the 32 rows. The column
decoder comprises of eight 1-of-8 decoders. It selects eight
The internal structure or architecture of a ROM comprises of the total 64 columns. Thus, eight-bit word appears
of three basic parts, namely, the array of memory cells, on the data output when the address is applied and
address decoder and the output buffers. The address decoder the CS = 0.
comprises of a single decoder in the case of small memories. Figure 28.24 shows the typical diagram of a ROM
In the case of large memories, it comprises of two decoders read operation. It shows that there is a time delay that
referred to as row and column decoders. The operation of a occurs between the application of an address input and
ROM can be best explained with the help of the simplified the availability of corresponding data at the output. It is
representation of a 32 8 ROM as shown in Fig. 28.23. this time delay that determines ROMs operating speed.
The array of memory cells stores the data to be pro- This time delay is known as access time, tACC. Another
grammed into the ROM. The number of memory cells in useful timing parameter is the output enable time, tOE
a row equals the word size and the number of memory which is the time delay between application of CS input
cells in a column equals the number of such words to and appearance of valid data output.
be stored. In the memory shown in Fig. 28.23, the word The typical bipolar ROMs have access times in the
size is eight bits and the number of words is 32. The range of 30-90 ns. In the case of NMOS devices, they
data outputs of each of the memory cells in the array have access times in the range of 35-500 ns. The output
are connected to an internal data bus that runs through enable time (tOE) in the case of bipolar ROMs is in the
the entire circuit. The address decoder, 1-of-32 decoder range of 10-20 ns. For MOS based ROMs, the same is
in this case sets the corresponding `row line HIGH when in the range of 25-100 ns.

0 MC MC MC MC MC
1 MC MC MC MC MC
A0
A1
A2 Address
decoder
A3
A4
30 MC MC MC MC MC
31 MC MC MC MC MC
1 6
0 2 7
MC = Memory Cell
Output buffers
D0 D1 D2 D3 D4 D5 D6 D7
Figure 28.23| Architecture of 32 8 ROM.
1 1
Address
input Old New
address address
0 0
CS 1
0
0
1
Data
Data
output
output
Hi-Z valid
state 0
tOE
tACC t
Figure 28.24| Typical timing of a ROM read operation.

28.11.2 Types of ROM a MOSFET in common drain configuration. Figures

28.25(a) and (b) show a MOSFET based basic cell con-
Depending upon the methodology of programming, eras- nection when storing a `1 and `0, respectively. As is
ing and reprogramming information into ROMs, they clear from the figure, connection of the `row line to the
are classified as follows: gate of the MOSFET stores `1 at the location when the
1. Mask-programmed ROMs `row line is set to level `1. A floating gate connection is
2. Programmable ROMs (PROM) used to store `0. Figures 28.25(c) and (d) show the basic
3. Erasable programmable ROMs (EPROM) bipolar transistor based memory cell connection when
i.Ultraviolet erasable programmable ROMs storing a `1 and `0, respectively.
(UV-EPROM) Figure 28.26 shows the internal structure of a 4 4
ii.Electrically erasable programmable ROMs bipolar mask-programmed ROM. The data programmed
(EEPROM) into the ROM is given in the adjoining truth table. The
transistors with an open base store a `0 where as those
28.11.2.1Mask-Programmed ROM with their bases connected to the corresponding decoder
output store a `1. As an illustration, transistors Q30,
In the case of a mask-programmed ROM, the ROM is Q20, Q10 and Q00 in Row-0 store 1, 0, 1 and 0, respec-
programmed at the manufacturers site according to the tively. The stored information in a given row is available
specifications of the customer. A photographic negative at the output when the corresponding decoder is enabled
called a mask is used to store the required data on the and that `row line is set to level `1. The output of the
ROM chip. A different mask would be needed for stor- memory cells appear at the column lines. For example,
ing each different set of information. As preparation of when the address input is `11, Row-3 is enabled and the
a mask is an expensive proposition, mask-programmed data at the output is 0110.
ROM is economical only when manufactured in large
In the ROM architecture shown in Fig. 28.26, number
quantities. The limitation of such a ROM is that once
of memory cells in a row represents the word size. The
programmed, it cannot be reprogrammed.
four memory cells in a row here constitute a four-bit
The basic storage element is a NPN bipolar tran- register. There are four such registers in this ROM. In a
sistor connected in common-collector configuration or 16 8 ROM of this type, there will be 16 rows of such
Column Column
Row Row
+VDD +VDD
(a) (b)
Column Column
Row Row
+VCC +VCC
(c) (d)
Figure 28.25| Basic cell connection of mask-programmed ROM.

Row-0
+VCC
Q30 Q20 Q10 Q00

Row-1
+VCC
Q31 Q21 Q11 Q01

A1 A0 EN Row-2
+VCC
0
1 Q32 Q22 Q12 Q02

1-of-4 Row-3
Decoder
2 +VCC
3 Q33 Q23 Q13 Q03
D3 D2 D1 D0
Truth Table
Address Data
A1 A0 D3 D2 D1 D0
0 0 1 0 1 0
0 1 1 0 0 0
1 0 0 1 1 1
1 1 0 1 1 0
Figure 28.26| Internal structure of a 4 4 bipolar mask-programmed ROM.
transistor cells with each row having eight memory cells. used in PROMs are metal links, silicon links and PN
The decoder in that case would be a 1-of-16 decoder. junctions. These fusible links can be selectively blown off
to store the desired data. A sufficient current is injected
28.11.2.2Programmable ROM (PROM) through the fusible link to burn it open to store `0.
The programming operation, as said earlier, is done with
In the case of PROMs, the programming instead of being PROM programmer. The PROM chip is plugged into the
done at the manufacturers premises during the manu- socket meant for the purpose. The programmer circuitry
facturing process, is done by the customer with the help
Column Column
of a special gadget called PROM programmer. Since the
data once programmed, cannot be erased and repro- Row Row
+VDD +VCC
grammed, these devices are also referred to as one time Fusible
programmable ROMs. link
The basic memory cell of PROM is similar to that of a
mask programmed ROM. Figures 28.27(a) and (b) show Fusible
MOSFET based memory cell and bipolar transistor based link
memory cell, respectively. In the case of a PROM, each
of the connections that were left either intact or open in
(a) (b)
the case of mask programmed ROM are made with a thin
fusible link as shown in Fig. 28.27. Basic fuse technologies Figure 28.27| Basic memory cell of PROM.

selects each address of the PROM one by one, burns in cell. Application of a high voltage programming pulse
the required data and then verifies the correctness of the between gate and drain induces the charge in the float-
data before proceeding to the next address. The data is ing gate region which can be erased by reversing the
fed to the programmer from a keyboard or a disk drive polarity of the pulse. Since the charge transport mecha-
or from a computer. nism requires very low current, erasing and programming
PROM chips are available in various word sizes and operations can be carried out without removing the chip
capacities. 27LS19, 27S21, 28L22, 27S15, 24S41, 27S35, from the circuit. EEPROMs also have another advan-
24S81, 27S45, 27S43 and 27S49, respectively, are 32 8, tage that it is possible to erase and rewrite data in the
256 4, 256 8, 512 8, 1K 4, 1K 8, 2K 4, 2K individual bytes in the memory array. The EEPROMs,
8, 4K 8 and 8K 8 PROMS. Typical access time in however, have lower density (bit capacity per square mm
the case of these devices is in the range of 50 to 70 ns. MOS of silicon) and higher cost as compared UV-EPROMs.
based PROMs are available with much greater capacities
than bipolar transistor based PROMs. Also, the power 28.11.2.4Flash Memory
dissipation is much lower in MOS PROMs than it is in the
case of bipolar PROMs with similar capacities. Flash memories are high density non-volatile read/
write memories with higher density. Flash memory
combines the low cost and high density features of an
28.11.2.3Erasable PROM (EPROM) UV-EPROM and in-circuit electrical erasability feature of
EEPROM without compromising on the high speed access
EPROM can be erased and reprogrammed as many of both. Structurally, the memory cell of a flash memory
times as desired. Once programmed, it is non-volatile, is like that of an EPROM. The basic memory cell of a
that is, it holds the stored data indefinitely. There are flash memory is shown in Fig. 28.28. It is a stacked gate
two types of EPROM, namely, the ultraviolet erasable MOSFET with a control gate and floating gate in addi-
PROM (UV-EPROM) and electrically erasable PROM tion to drain and source. The floating gate stores charge
(EEPROM). when sufficient voltage is applied to the control gate. `0 is
The memory cell in a UV-EPROM is MOS transistor stored when there is more charge and `1 when there is less
with a floating gate. In the normal condition, the MOS charge. The amount of charge stored on the floating gate
transistor is OFF. It can be turned ON by applying a determines if the MOSFET is turned ON or not.
programming pulse (in the range of 10-25V) that injects It is called a flash memory because of its rapid erase
electrons in the floating gate region. These electrons and write times. Most of the flash memory devices use a
remain trapped in the gate region even after removal of `bulk erase operation in which all the memory cells on
programming pulse. This keeps the transistor ON once the chip are erased simultaneously. Some flash memory
it is programmed to be in that state even after removal devices offer a `Sector Erase mode in which specific sec-
of power. The stored information can however be erased tors of the memory device can be erased at a time. This
by exposing the chip to ultra-violet radiation through a mode comes handy when only a portion of the memory
transparent window on the top of the chip meant for the needs to be updated.
Figure 28.29 shows the basic array of 4 4 flash
purpose. The photo current thus produced removes the
stored charge in the floating gate region and brings the memory. Similar to the case of earlier memories, there
transistor back to OFF state. The erasing operation takes is an address decoder which selects the row. During the
about 15-20 min and the process erases information on read operation, for a cell containing `1 there is current
all the cells of the chip. It is not possible to carry out any through the bit line which produces a voltage drop across
selective erasure of memory cells. Intels 2732 is a (4K the active load. This is compared with the reference volt-
8) UV-EPROM hardware implemented with NMOS age and the output bit is `1. In case the memory cell has
devices. Type numbers 2764, 27128, 27256 and 27512 `0, there is very little current in the bit line. Memory
have capacities of (8K 8), (16K 8), (32K 8) and sticks are flash memories. They are available in 4MB,
(64K 8), respectively. The access time is in the range
of 150-250 ns. UV-EPROMs suffer from disadvantages Floating
such as need for removing the chip from the circuit if it gate Drain
is to be reprogrammed, non-feasibility of carrying out Control
selective erasure and reprogramming process takes sev- gate
eral tens of minutes. These are overcome in EEPROMs
and flash memories discussed in the following sections.
The memory cell of an EEPROM is also a floating
Source
gate MOS structure with a slight modification that there
is a thin oxide layer above the drain of the MOS memory Figure 28.28| Basic cell of a flash memory.

+VDD +VDD
Load
`Data out 0
Bit line Bit Ref Comp 3
Ref Comp 0 `Data out 3
line 0 line 3
line
2-Bit Row
address decoder
Column decoder
2 Bit address
Figure 28.29| Basic array of a 4 4 flash memory.
8MB, 16MB, 32MB, 64MB, 128MB, 256MB, 512MB, 4. Function generators

1GB, 2GB, 4GB, 8GB and 16GB sizes. 5. Auxiliary memory
To sum up, while PROMs are least complex and low cost, The most common application of ROM chips is in the
they cannot be erased and reprogrammed. UV-EPROMs storage of data and program codes that must be made
are little more complex and costly, but then they can be available to a microprocessor based systems such as
erased and reprogrammed by taking them out of the cir- microcomputers on power-up. This component of the soft-
cuit. Flash memories are in-circuit electrically erasable ware is referred to as firmware as it comes embedded in
either in sector wise or bulk mode. The most complex and the hardware with the machine. Even consumer products
most expensive are the EEPROMs, but then they offer such as CD players, microwave ovens, washing machines,
byte-by-byte electrical erasability in-circuit. etc., have embedded microcontrollers which have a micro-
processor to control and monitor the operation according
to the information stored on the ROM. ROMs are also
28.11.3 Applications of ROMs
used to store the `bootstrap program in computers. It is a
relatively small program containing instructions that will
Majority of ROM applications originate from the need
cause the CPU to initialize the system hardware after it is
for non-volatile storage of data or program codes. Some
powered on. The bootstrap program then loads the oper-
of the common application areas include:
ating system programs stored in the secondary memory
1. Firmware into its main internal memory. The computer then begins
2. Bootstrap memory to execute operating system program. This start-up oper-
3. Look-up tables ation is also called `booting operation.

28.12 EXPANDING MEMORY CAPACITY 689
ROMs are frequently used as `look-up tables. There 28.12 EXPANDING MEMORY
are two sets of data, one constituting the address and CAPACITY
the other corresponding to the data stored in various
memory locations of the ROM. Corresponding to each
address input, there is a unique data ouput. One typical When a given application requires a RAM or ROM with
application is that of code conversion. As an illustration, a capacity that is larger than what is available on a
a ROM can be used to build a binary-to-BCD converter single chip, more than one such chip can be used to
where each memory location stores BCD equivalent of achieve the objective. Now, the enhancement in capacity
corresponding address code expressed in binary. required could be either in terms of increasing the word
A ROM can be an important building block in a wave- size or increasing the number of memory locations. How
form generator. In a typical waveform generation set-up, this can be achieved is illustrated in the following sec-
ROM is used as a look-up table with each of its memory tions with the help of examples.
location storing a unique digital code corresponding to
a different amplitude of the waveform to be generated. 28.12.1 Word Size Expansion
The address inputs of the ROM are fed from the output
of a counter. The data outputs of ROM feed a D/A Let us take up the task of expanding the word size of an
converter whose output constitutes the desired analogue available 16 4 RAM chip from 4 bits to 8 bits. Figure
waveform. This concept is also utilized in speech synthe- 28.30 shows the diagram where two such RAM chips
sizers, where the digital equivalent of speech waveform have been used to achieve the desired. The arrangement
values is stored in the ROM.
{
AB3
AB2
Address
bus
AB1
AB0
A3 A2 A1 A0 A3 A2 A1 A0
R/W R/W R/W

RAM-1 RAM-2
(16 4) (16 4)
CS CS CS
I/O3 I/O2 I/O1 I/O0 I/O3 I/O2 I/O1 I/O0
DB7
DB6
DB5
DB4
Data bus
DB3
DB2
DB1
DB0
Figure 28.30| Word size expansion.

is straightforward. Both chips are selected or deselected Let us consider use of two 16 8 chips to get a
together. Also, input that determines whether it is a 32 8 chip. A 32 8 chip would need 5 address input
`read or `write operation is common to both chips. That lines. Four of the five address inputs other than the
is, both chips are selected for `read or `write opera- MSB address bit are common to both 16 8 chips. The
tion together. The address inputs to the two chips are MSB bit feeds input of one chip directly and input of
also common. The memory locations corresponding to the other chip after inversion. Input to the two chips is
various address inputs store higher order four bits in the common.
case of RAM-1 and lower order four bits in the case of
Now, for first half of the memory locations correspond-
RAM-2. In essence, each of the RAM chips stores half
ing to address inputs 00000 to 01111 (a total of 16 loca-
of the word. Since the address inputs are common, same
tions), the MSB bit of the address is `0 with the result
location in each chip is accessed at the same time.
that RAM-1 is selected and RAM-2 is deselected. For
the remaining address inputs of 10000 to 11111 (again a
28.12.2 Memory Locations Expansion total of 16 locations), RAM-1 is deselected while RAM-2
is selected. Thus, the overall arrangement offers a total
Figure 28.31 shows how more than one memory chips of 32 locations, 16 provided by RAM-1 and 16 provide
can be used to expand the number of memory locations. by RAM-2. The overall capacity is thus 32 8.
AB4
AB3
Address
input AB2
AB1
AB0
R/W
A3 A2 A1 A0 A3 A2 A1 A0
CS CS
RAM-1 RAM-1
(16 8) (16 8)
R/W R/W
I/O7 I/O0 I/O7 I/O0
DB7
DB6
DB5
Data DB4
bus
DB3
DB2
DB1
DB0
Figure 28.31| Memory locations expansion.

28.13 PERIPHERAL DEVICES 691
28.13 PERIPHERAL DEVICES 28.13.3 Programmable Interrupt

Controller (PIC)
Microprocessors and peripheral devices provide a com- A PIC is a device that allows priority levels to be assigned
plete solution in increasingly complex application envi- to its interrupt outputs. It functions as an overall man-
ronments. A peripheral device typically belongs to the ager in an interrupt driven system environment. When
category of MSI logic devices. This section gives an the device has multiple interrupt outputs, it will assert
introduction to the popular peripheral devices which are them in the order of their relative priority. Common
used along with the microprocessor in a microcomputer modes of a PIC include hard priorities, rotating priorities
system. The different peripheral devices used in a micro- and cascading priorities. PICs often allow the cascading
computer system include programmable timer/counter, of their outputs to inputs between each other. Intel 8259
Programmable peripheral interface (PPI), EPROM, is a family of PICs designed and developed for use with
RAM, programmable interrupt controller (PIC), DMA the Intel 8085 and Intel 8086 microprocessors.
controller, programmable communication interface-uni-
versal synchronous asynchronous receiver transmitter
28.13.4 DMA Controller
(USART), math co-processor, programmable keyboard/
display interface, CRT controller, floppy disk controller, In direct memory access (DMA) data transfer scheme,
clock generators and transceivers. data is transferred directly from a I/O device to memory
or vice versa without going through the CPU. DMA con-
28.13.1 Programmable Timer/Counter troller is used to control the process of data transfer.
Its primary function is to generate, upon a peripheral
Programmable timer/counter is used for generation of request, sequential memory address which will allow
accurate time delay for event counting, rate genera- the peripheral to read or write data directly to or from
tion, complex waveform generation applications and so memory. One of the popular known programmable DMA
on. Examples of programmable timer/counter devices controller is Intels 8257.
include Intels 8254 and 8253 family of devices. Intel
8254 contains three 16-bit counters which can be pro- 28.13.5 Programmable Communication
grammed to operate in several different modes. Some Interface
of the functions common to microcomputers and imple-
mentable with 8254 are real time clock, event counter Programmable communication interface (PCI) is an
digital one shot, programmable rate generator, square interface device that is used for data communication
wave generator, binary rate multiplier, complex wave applications with microprocessors. They basically con-
form generator and complex motor controller. vert the data from the microprocessor into a format
acceptable for communication and also convert the
28.13.2 Programmable Peripheral incoming data into a format understood by the micro-
Interface (PPI) processor. 8251 is a PCI device designed for Intels 8085,
8086 and 8088 microprocessors and is used in serial com-
PPI devices are used to interface the peripheral munication applications.
devices with the microprocessors. 8255 PPI is a widely
used programmable parallel I/O device. 8255 can be 28.13.6 Math Co-processor
programmed to transfer data under various conditions,
from simple I/O to interrupt I/O. It can function in bit Math co-processors are special purpose processing units
reset (BSR) mode or I/O mode. In I/O mode, it has that assist the microprocessor in performing certain
three ports, namely, port A, port B and port C. The mathematical operations. The arithmetic operations per-
I/O mode is further divided into three different modes, formed by the coprocessor are floating-point operations,
namely, mode 0, mode 1, mode 2. In mode 0, all ports trigonometric, logarithmic and exponential functions
function as simple I/O ports. Mode 1 is a handshake and so on. The examples include Intels 8087, 80287, etc.
mode whereby port A and/or B use bits from port C as The 8087 Numeric coprocessor provides the instructions
handshake signals. In mode 2, port A can be set up for and data types needed for high performance numeric
bidirectional data transfer using handshake signals from application, providing up to 100 times the performance
port C and port B can be set up either in mode 0 or in of a CPU alone. Another widely used math coprocessor
mode 1. In BSR mode, individual bits in port C can be is 80287. The 80287 Numeric processor extension (NPX)
set or reset. provides arithmetic instructions for a variety of numeric

data types in 80286 systems. It also executes numerous 8275H. It allows simple interface to almost any raster
built-in transcendental functions (e.g., tangent and log scan CRT display with a minimum of external hardware
functions). and software overhead. The number of display charac-
ters per row and the number of character rows per frame
are software programmable.
28.13.7 Programmable Keyboard/Display
Interface
28.13.9 Floppy Disk Controller
Programmable keyboard/display interfaces are the
devices used for interfacing the keyboard and the dis- A floppy disk controller is used for disk drive selection,
play to the microprocessor. The keyboard section of the head loading, issue of read/write commands, data sepa-
device debounces the keyboard entries and provides the ration, and serial-to-parallel and parallel-to-serial con-
data to the microprocessor in the desired format. The version of data. Some examples of floppy disk controllers
display section converts the data output of the micro- include Intel 82078, Intel 82077 and Intel 8272.
processor into the form desired by the display device
in use. 8279 is general purpose programmable keyboard 28.13.10 Clock Generator
and display I/O interface device designed for use with
Intel microprocessors. The keyboard portion can pro- A clock generator is a circuit that produces timing signal
vide a scanned interface to a 64-contact key matrix. for synchronization of circuits operation. Examples of
The keyboard entries are debounced and strobbed in an clock generators used in microprocessor systems include
eight-character FIFO. If more than eight characters are 8284 and 82284. 8284 generates the system clock for
entered, overrun status is set. Key entries set the inter- the 8086 and 8088 processors. It requires a crystal or
rupt output line to the CPU. The display portion pro- a TTL signal source for producing clock waveforms.
vides a scanned display interface for LED, incandescent, It provides local READY and MULTIBUS READY
and other popular display technologies. Both numeric synchronization.
and alpha-numeric segment displays may be used. The
8279 has 16 8 display RAM.
28.13.11 Octal Bus Transceiver
28.13.8 Programmable CRT Controller Bus transceivers are devices with high output drive
capability for interconnection with data buses. In a
Programmable CRT controller is a device to inter- microprocessor based system they provide interface
face CRT raster scan displays with the microprocessor between the microprocessor bus and the system data
system. Its primary function is to refresh display by buff- bus. 8286 is eight-bit bipolar transceiver with three-
ering the information from main memory and keeping state output used in a wide variety buffering applica-
track of the display position of the screen. One of the tions in microcomputer systems. It is packaged in 20-pin
commonly used programmable CRT controller is Intels DIP package.
SOLVED EXAMPLES
1. Two operands can be checked for equality using 2. A microprocessor is called an n-bit microprocessor
depending upon
(a) OR operation (b) AND operation
(c) EX-OR operation (d) None of these (a) registers length
(b) size of internal data bus
Solution. An EX-OR gate produces the same (c) size of external data bus
output for identical inputs. (d) None of these
Ans. (c)

SOLVED EXAMPLES 693
Solution. The size of the internal data bus decides (c) store the status of the microprocessor
the largest number that can be processed in a single (d) None of these
operation. Hence, the microprocessor is known by Ans. (a)
its internal data bus size. Ans. (b)
8. The set of commands which give directions to the
3. 8085 microprocessor is a assembler during the assembly process but are not
translated into machine instructions are called
(a) zero address microprocessor
(b) one address microprocessor (a) mnemonics (b) identifiers
(c) two address microprocessor (c) directives (d) operands
(d) None of these
Solution. This is also a function and therefore no
Solution. It is a zero address microprocessor as all explanation is needed.
arithmetic operations take place using the top one Ans. (c)
or two positions on the stack.
9. With reference to 8085 microprocessor, ANA
Ans. (a)
R/Mis
4. Setting contents of a microprocessor to zero can be
(a) a logic instruction
efficiently done by
(b) an arithmetic instruction
(a) MOV Immediate instruction using zero as (c) data transfer instruction
immediate data (d) control instruction
(b) AND Immediate instruction using zero as
immediate data Solution. ANA R/M is an instruction that
(c) XORing register with itself instructs to `logically AND the contents of reg-
(d) None of these ister/memory with the contents of accumulator.
Therefore, it is a logic instruction.
Solution. XOR operation will set the contents of Ans. (a)
register to zero as like inputs in an EX-OR gate
produce a `0 output. 10. The following signal is used when a peripheral
Ans. (c) device requests the microprocessor to have a DMA
operation.
5. Stack memory is used to
(a) provide additional memory to the base memory (a) INTR and INTA (b) READY
(b) save return addresses of a subroutine
(c) save the status of a microprocessor (c) HOLD and HLDA (d) RD and WR
(d) None of these Ans. (d)
Ans. (b) 11. Identify the primary memory device(s).
6. `Shift left instruction causes all bits shifted one (a) Registers built into CPU
position to the left with rightmost bit set to zero. (b) RAM and ROM
The effect is to (c) Cache memory
(a) multiply by 2 (b) divide by 2 (d) All of these
(c) SET the most significant bit (d) None of these
Solution. Primary memory is directly accessed by
Solution. Let us take an example. `shift left instruc- the processor or the CPU for storage or retrieval of
tion when applied to a 4-bit number 0110 (decimal 6) information. Secondary memory on the other hand
changes it to 1100 (decimal 12). Therefore, its effect is not directly accessed by CPU. It is through an
is the same as multiplying by 2. external storage device. Primary memory devices
Ans. (a) are the registers built into CPU, RAM, ROM and
cache memory.
7. Program counter is used to Ans. (d)
(a) store address of the next instruction to be
12. SRAM devices are made using
executed
(b) store temporary data to be used in arithmetic (a) Bipolar, MOS or BiMOS technologies
operations (b) MOS technology

(c) Bipolar technology (a) Capacitor

(d) BiMOS technology (b) MOS switch and a capacitor
(c) MOSFET
Solution. The basic element of SRAM is a latch. (d) Flip flop
It can be implemented using bipolar, MOS or
Solution. The basic DRAM cell consists of a MOS
BiMOS technologies.
switch and capacitor. The cell holds a value of `1
Ans. (a)
when capacitor is charged and `0 when discharged.
13. Two 1K 8 ROM chips can be used to configure Ans. (b)
(a) One 2K 8 ROM (b) One 1K 16 ROM 15. Which one of the following types of RAM needs
(c) Both (a) and (b) (d) None of these periodic refreshing?
(a) Asynchronous SRAM
Solution. In the case discussed in option (a), we (b) DRAM
are doing memory location expansion and in the (c) Synchronous SRAM
case discussed in option (b) we are doing word size (d) All types of RAM need periodic refreshing
expansion. Both are possible.
Solution. Refreshing is needed in a DRAM cell to
Ans. (c)
prevent leakage of charge when it is holding a `1.
14. The basic memory cell in a DRAM is a Ans. (b)
1. What is the largest number that can be processed 3. How many 16K 4 RAMs will be needed to build
in a single operation by a 16-bit microprocessor? a 16K 8 ROM?
Solution. The largest number that can be pro- Solution. This is a case of word length expansion.
cessed by a 16-bit microprocessor in a single opera- Both chips are selected and deselected together.
tion is given by Address lines are common. Memory locations corre-
sponding to various address inputs store higher order
216 1 = 65535 four bits in one chip and lower order four bits in
Ans. (65535) the other chip. The number of RAMS required is 2.
Ans. (2)
2. How many 8K 8 RAM chips are needed to build
a 16K 8 ROM? 4. How many bytes of data a 64K RAM can store?
Solution. This is a case of expansion of memory Solution. 64K RAM can store
locations. 16K 8 has 14 address lines and 8K8 216 = 65536 bytes of data
has 13 address lines. In the case of 16K 8 RAM, Ans. (65536)
13 out of 14 address lines will be common to both
5. Identify the maximum number of output lines in
8K 8 RAMs. The MSB address line will be
the address decoder used with 64 8 SRAM.
applied directly to one RAM chip and after inver-
sion to the other RAM chip. Hence, the number of Solution. 64 8 SRAM will use a 6-line to 64-line
chips required to build a 16K 8 ROM is 2. address decoder. Hence, the answer is 64.
Ans. (2) Ans. (64)
PRACTICE EXERCISE
1. The synchronization between microprocessor and 2. RISC processor is characterized by

memory is done by
(a) h
ardwired control design with no microcodes
(a) ALE signal (b) HOLD signal and fixed instruction format
(c) READY signal (d) None of these (b) executing most of the instructions in a single
(1 Mark) clock cycle

(c) several general purpose registers and large cache (c) There will be 1, 31, 072 memory cells
memories that support very fast access to data (d) Both (b) and (c) are true
(d) All of the above (2 Marks)
(1 Mark)
7. The memory device that communicates with the
3. It is a type of microprocessor instruction in which CPU and has relatively much higher speed than
the contents of the source are copied into destination the main memory is
register without modifying the contents of the source.
(a) DVD ROM (b) cache memory
(a) Arithmetic instructions (c) primary memory (d) hard disk
(b) Data transfer instructions (1 Mark)
(c) Control transfer instructions
(d) Machine control instructions 8. With reference to level-1 and level-2 cache memory,
(1 Mark) one of the following statements is true.
4. Identify the true statement with reference to imme- (a) L

evel-1 cache has relatively higher storage
diate addressing mode. capacity.
(b) Level-2 cache is part of microprocessor itself.
(a) In this mode, data is accessed by specifying the (c) Level-2 cache has relatively lower stor-
register name in which it is stored. age capacity and is mounted external to the
(b) In this mode, value of operand is held within microprocessor.
the instruction itself. (d) Level-1 cache has relatively lower storage
(c) In this mode, memory location of data is stored capacity and is part of microprocessor itself.
in a register (1 Mark)
(d) This mode is useful for accessing fixed memory
locations such as memory mapped I/O devices 9. A type of memory device in which data is stored in
(1 Mark) the form of charge on a capacitor is
5. With reference to a 2K bit ROM organized as 256 (a) Asynchronous SRAM
8 array of memory cells, which one of the follow- (b) Synchronous SRAM
ing statements is true? (c) DRAM
(d) All of these
(a) It uses 256 rows of eight cells each.
(1 Mark)
(b) It uses 2048 memory cells and 8-line to 256-line
address decoder. 10. Identify the characteristic feature or features of a
(c) Both (a) and (b) are correct. random access memory.
(d) None of these
(2 Marks) (a) It is a serial access memory
(b) Data can be read from or written into any of
6. With reference to 16K 8 asynchronous SRAM the memory locations regardless of the order in
with memory cells arranged in array of 128 rows which they are arranged
and 128 columns, (c) All memory locations can be accessed with
(a) There will be 8-line to 128-line row and column same speed
address decoders (d) Both (b) and (c) are correct
(b) There will be 7-line to 128-line row and column (1 Mark)
address decoders
1. What is the size of internal data bus in bits of 8085 4. How many RAM chips specified as 16K 8 will be
microprocessor? needed to construct a 64K 16 RAM?
(1 Mark) (2 Marks)
2. How many address input lines does a 16K 8 5. A certain memory is specified as 32K 8.
RAM chip have? Determine number of data input lines.
(1 Mark) (1 Mark)
3. What is the size (in bits) of stack pointer in 8085?
(1 Mark)

1. (c) A READY signal is used to delay the micro- 6. (d) 7-line to 128 row and column address decoders
processor READ or WRITE cycles until a slow are required as 128 = 27 and number of rows =
responding peripheral is ready to send or accept number of columns = 128. Number of memory cells =
data thereby achieving synchronization. 214 8 = 1,31,072.
2. (d) Statements given in options (a), (b) and (c) are 7. (b)
the characteristic features of RISC processors.
8. (d)
3. (b) In the data transfer instructions, the data
is not transferred but copied to the destination 9. (c) A DRAM cell consists of a capacitor and a
register without modifying the contents of the MOS switch. Charged capacitor represents `1 and
source. discharged capacitor represents `0.
4. (b) 10. (d)
5. (c) Option (a) is obvious. Number of memory cells =

256 8 = 2048. Address decoder has eight lines
as 256 = 28.
1. 8085 is an eight-bit microprocessor and number of 4. To convert 16K 8 RAM into 64K 8 RAM
bits specifies the size of internal data bus. Hence, (Memory locations expansion), we would need
the answer is 8. four chips as 16K = 214 and 64K = 216. Further,
Ans. (8) another four 16K 8 RAM chips will be required
2. Since 16K = 214, Therefore the number of address to convert 64K 8 RAM into 64K 16 RAM
lines is 14. (word length expansion). Hence, the answer is 8.
Ans. (14) Ans. (8)
3. The size (in bits) of stack pointer in 8085 is 16. 5. Word length is eight bits. Hence, the answer is 8.
Ans. (16) Ans. (8)
1. In the circuit shown in the following figure, A is W

parallel-in, parallel-out four-bit register, which MSB
loads at the rising edge of the clock C.
The input lines are connected to a four-bit bus,
W. Its output acts as the input to a 16 4 ROM
whose output is floating when the enable input E
is 0. A partial table of the contents of the ROM is Clk A
as follows:
1
Address 0 2 4 6 8 10 12 14
Data 0011 1111 0100 1010 1011 1000 0010 1000
ROM
E
The clock to the register is shown, and the data on

the W bus at time t1 is 0110. The data on the bus
at time t2 is
Clk
t1 t2 time
ROM
E
Solution. The given instructions perform the fol-

lowing functions:
Clk
LXI H, 9258 Memory location 9258
MOV A, M Data moved from memory to
t1 t2 time accumulator
(a) 1111 (b) 1011 CMA Data complemented in
(c) 1000 (d) 0010 accumulator
(GATE 2003: 2 Marks) MOV M, A Complemented data moved
to memory from accumulator
Solution. When W has the data 0110 (i.e., 6 in
decimal), its data value at that address is 1010. Hence, as a result of the given sequence of instruc-
Now, 1010, that is, 10 is acting as address at time tions, contents of location 9258 are complimented
t2 and data at that moment is 1000. and stored in location 9258.
Ans. (c) Ans. (c)
2. In an 8085 microprocessor, the instruction CMP B 5. It is desired to multiply the numbers 0AH by 0BH
has been executed while the content of the accu- and store the result in the accumulator. The num-
mulator is less than that of register B. As a result bers are available in registers B and C respectively.
A part of the 8085 program for this purpose is
(a) Carry flag will be set but Zero flag will be reset given below:
(b) Carry flag will be reset but Zero flag will be set
(c) both Carry flag and Zero flag will be reset MVI A, 00H
(d) both Carry flag and Zero flag will be set Loop; .
(GATE 2003: 2 Marks) .
..
Solution. CMP B subtracts the contents of regis- HLT END
ter B from the accumulator A. Since accumulator
The sequence of instruction to the complete the
has content less than that of register B, therefore
program would be
CY = 1 as it shows negative result. Also, the result
being non-zero, the zero flag will be reset. (a) JNZ LOOP, ADD B, DCR C
Ans.(a) (b) ADD B, JNZ LOOP, DCR C
(c) DCR C, JNZ LOOP, ADD B
3. The number of memory cycles required to execute
(d) ADD B, DCR C, JNZ LOOP
the following 8085 instructions
I. LDA 3000 H
II. LXI D, FOF 1H Solution.
would be
Comments
(a) 2 for (I) and 2 for (II) MVI A, 00H A 00H
(b) 4 for (I) and 3 for (II)
(c) 3 for (I) and 3 for (II) Loop; ADD B A 0AH
(d) 3 for (I) and 4 for (II) DCR C Decreases the contents
(GATE 2004: 2 Marks) of register C OBH times,
therefore adding
Ans. (b)
OAH and OBH eleven times
4. Consider the sequence of 8085 instructions given JNZ Loop Thus instruction causes the
below. functioning of loop 11 times.
LXI H, 8258, MOV A, M, CMA, MOV M, A
Thus multiplication
Which one of the following is performed by this
accomplished.
sequence?
HLT
(a) Contents of location 9258 are moved to the END
accumulator Ans. (d)
(b) Contents of location 9258 are compared with
6. The 8255 programmable peripheral interface is
the contents of the accumulator
used as described below.
(c) Contents of location 9258 are complemented
and stored in location 9258 I. A
n A/D converter is interfaced to a microproces-
(d) Contents of location 5892 are complemented sor through an 8255. The conversion is initiated
and stored in location 5892 by a signal from the 8255 on Port C. A signal
(GATE 2004: 2 Marks) on Port C causes data to be stored into Port A.

II. T
wo computers exchange data using a pair of 9. What memory address range is NOT represented
8255s. Port A works as a bidirectional data port by chip#1 and chip#2 in the following figure.
supported by appropriate handshaking signals. A0 to A15 in this figure are the address lines and
The appropriate modes of operation of the 8255 CS means chip select.
for (I) and (II) would be
(a) Mode 0 for (I) and Mode 1 for (II) 256 bytes
(b) Mode 1 for (I) and Mode 0 for (II) A0A7 Chip #1
(c) Mode 2 for (I) and Mode 0 for (II)
(d) Mode 2 for (I) and Mode 1 for (II)
A8
Ans. (d) A9
A9
and 8: Consider an 8085 microprocessor system. A8
7. The following program starts at location 0100 H.

A0A7 256 bytes
LXI SP, 00FF
Chip #2
LXI H, 0107
MVI A, 20H
SUB M
A10A15 not used
The content of accumulator when the program
counter reaches 0109H is
(a) 0100-02FF (b) 1500-16FF
(a) 20H (b) 02H (c) 00H (d) FFH (c) F900-FAFF (d) F800-F9FF
Solution. Solution.
Location Muemonics Operation Chip #1
0100H LXI SP, 00FF SP 00FF H A15 A12 A11 A10 A9 A8 A7 A0
0103H LXI H, 0107 H-L 0107 H
0106H MVI A, 20H A 20H 0 1 0 0 0 0
0108H SUB M A 00 H 0 1 1 1 1 1
0109H Chip #2
Address of M specified by contents of H-L memory A15 A12 A11 A10 A9 A8 A7 A0
and H-L 0107 H, and 0107H 20H When PC
1 0 0 0 0 0
reaches 0109 H, contents of accumulator reduces to
zero after having operation of instruction SUB M. 1 0 1 1 1 1
Ans. (c) Therefore, F800 - F9FF cannot be the memory
8. If in addition following code exists from 0109 onwards, range for chip#1 and chip#2.
ORI 40H Ans. (d)
ADD M 10. Following is the segment of a 8085 assembly lan-
What will be the result in the accumulator after guage program
the last instruction is executed? LXI SP, EFFFH
(a) 40H (b) 20H (c) 60H (d) 42H CALL 3000H
(GATE 2005: 2 Marks) :
:
Solution. 3000 H : LXI H, 3CF4 H
0109H ORI 40H A 40H PUSH PSW
010BH ADD M A 40H + 20H = 60H SPHL
A 0000 0000H = 00H POP PSW
M 0107H 0100 0000H = 40H RET
ORI 0100 0000H = 40H On completion of RET execution, the contents of SP is
0107H 20H 0010 0000H = 20H (a) 3CFO H (b) 3CF8 H
ADD M 0110 0000H = 60H (c) EFFD H (d) EFFF H

Solution. Solution.
Location Instruction Operation
LXI SP, EFFFH SP EFFF H A7 A6 A5 A4 A3 A2 A1 A0
CALL 3000H program transfers to 1 1 0 1 0 1 0 0 D4
memory location 3000H
3000H : LXI IH, 3CF4H HL 3CF4 1 1 0 1 0 1 0 1 D5
PUSH PSW SP EFFF ////////
1 1 0 1 0 1 1 0 D6
SP-1 EFFE X
SP-2 EFFD Y 1 1 0 1 0 1 1 1 D7
(X and Y are accumulators con- I/P lines to
tents and flag register contents decoder
loaded into memory location
EFFE and EFFD, respectively.) From the table we can see that the line A5 is low
SPHL SP 3CF4 contents of H-L for all the address values.
register loaded into SP. Therefore, the output is taken from the fifth line.
POP PSW SP 3CF4 Flag register Z Ans. (b)
SP 3CF5 Accumulator W 12. An 8255 chip is interfaced to an 8085 microproces-
SP 3CF6 sor system as an I/O mapped I/O as shown in the
(Z and W are contents of memory figure. The address lines A0 and A1 of the 8085 are
locate 3CF4 and 3CF5 respec- used by the 8255 chip to decode internally its three
tively.) ports and the control register. The address lines
RET A3 to A7 as well as the IO/M signal are used for
address decoding. The range of addresses for which
3CF6 SP initial address the 8255 chip would get selected is
3CF7 A7 8255
A6
A5
3CF8 CS
SP address after RET execute A4
A3 A1 A1
Hence SP 3CF8 H. A0
IO/M A0
Ans. (b)
11. An I/O peripheral device shown in figure (b) below (a) F8HFBH (b) F8HFCH
is to be interfaced to an 8085 microprocessor. To (c) F8HFFH (d) F0HF7H
select the I/O device in the I/O address range D4H (GATE 2007: 2 Marks)
D7H, its chipselect (CS ) should be connected to Solution. 8255 chip will select in I/O mapped
the output of the decoder shown in figure (a) below. when
A7 A6 A5 A5 A3
A2 LSB 0 Data
1 1 1 1 1 1
2 IORD
A3 38 A0, A1 and A2 are in dont care conditions.
3 I/O
decoder 4 A7 A6 A5 A4 A3 A2 A1 A0
IOWR peripheral
5 1 1 1 1 1 0 0 0 = F8H
6 A1 1 1 1 1 1 1 1 1 = FFH
A4 MSB
7 A0 So, range of chip selection is F8H FFH
A7 Ans. (c)
A6
A5 CS and 14: An 8085 assembly language program is
(a) (b) given below
Line 1: MVI A, B5H
(a) output 7 (b) output 5 Line 2: MVI B, 0EH
(c) output 2 (d) output 0 Line 3: XRI 69H
(GATE 2006: 2 Marks) Line 4: ADD B

Line 5: ANI 9BH (c) PC = 6140H (d) PC = 6140H

Line 6: CPI 9FH HL = 6140H HL = 2715H
Line 7: STA 30101H (GATE 2008: 2 Marks)
Line 8: HLT Ans. (c)
13. The contents of the accumulator just after execu- 16. In a microprocessor, the service routine for a certain
tion of the ADD instruction in line 4 will be interrupt starts from a fixed location of memory
which cannot be externally set, but the interrupt
(a) C3H (b) EAH (c) DCH (d) 69H can be delayed or rejected. Such an interrupt is
(a) non-maskable and non-vectored
Solution. (b) maskable and non-vectored
After line (1) A contains B5H (c) non-maskable and vectored
After line (2) B contains 0EH (d) maskable and vectored
After line (3) (GATE 2009: 1 Mark)
A is XOR with 69 H
A 10 11 01 01 Solution. If an interrupt has an address, then
69 01 10 10 01 it is vectored interrupt, and if a interrupt can be
DC 11 01 11 00 rejected, then it is maskable interrupt.
After this contents of registor B are added to accu- Ans. (d)
mulator A. 17. In the circuit shown, the device connected to Y5
11 01 11 00 can have address in the range
00 00 11 10
11 10 10 10
So after line 4, A = EAH A8 A
Ans. (b) A9 B Y5
A10 C To device
14. After execution of line 7 of the program, the status chip select
of the CY and Z flags will be
748138
(a) CY = 0, Z = 0 (b) CY = 0, Z = 1 38 decoder
(c) CY = 1, Z = 0 (d) CY = 1, Z = 1
(GATE 2007: 2 Marks) A11 G2A
A12
Solution. Line 5: ANI 9BH. This line ANDs the A13 G2B
A14
contents of accumulator A with 9B. Accumulator A15
with 9BH G1
IO/M
A 11 10 10 10
9BH 10 01 10 11
10 00 10 10 (a) 2000 20FF (b) 2D00 2DFF
Accumulator stores 8AH in line 6 and compares (c) 2E00 2EFF (d) FD00 FDFF
its contents with 9FH. Since 9FH is greater than (GATE 2010: 1 Mark)
8AH, so carry flag will be generated while zero flag
remains unaffected. Solution. From the given circuit:
Ans. (c) A15 A14 A13 A12 A11 A10 A9 A8
15. An 8085 executes the following instructions .
00 1
0 1 1 0
1
2710 LXI H, 30A 0H To enable chip for Y5
5
2713 DAD H
2714 PCHL A7 A6 A5 A4 A3 A2 A1 A0
All addresses and constants are in Hex. Let PC be 0 0 0 0 0 0 0 0
the contents of the program counter and HL be the
contents of the HL register pair just after execut-
ing PCHL. 1 1 1 1 1 1 1 1

Which of the following statement is correct?
Hence range of the address is 2D00 2DFF
(a) PC = 2715H (b) PC = 30A0H Ans. (b)
HL = 30A0H HL = 2715H

18. For the 8085 assembly language program given B 0000 1110
below, the content of the accumulator after the +
execution of the program is A 0011 1000
0100 0110
3000 MVI A, 45H RRC 0010 0011 Contents of A
3002 MOV B, A Therefore, content of A = 23H
3003 STC Ans. (c)
3004 CMC 20. For 8085 microporcessor, the following program is
3005 RAR executed.
3006 XRA B
MVI A, 05H;
(a) 00H (b) 45H (c) 67H (d) E7H MVI B, 05H;
(GATE 2010: 2 Marks) PTR: ADD B;
DCR B;
Solution. JNZ PTR;
MVI A, 45H A = 45H ADI 03H;
MOV B, A B = 45H HLT;
STC set carry carry flag = 1 At the end of program, accumulator contains
CMC compliment carry carry Flag = 0
RAR .. Rotate right with carry (a) 17H (b) 20H (c) 23H (d) 05H
(GATE 2013: 1 Mark)
0 1 0 0 0 1 0 1 Solution. Accumulator changes as follows (05 +

0 05 + 04 + 03 + 02 + 01)H
Therefore, carry flag = 1 At the end of Loop accumulator contains = 14H
ADI 03H A = (14 + 03) = 17H
0010 0010 Ans. (a)
A= = 22H
2 2 21. There are four chips each of 1024 bytes connected
to a 16 bit address bus as shown in the follow-
XRA B XOR with 45H ing figure. RAMs 1, 2, 3 and 4, respectively, are
22H = 00100010 mapped to address
45H = 01000101
Output = 01100111
Therefore, A = 67H RAM
#4
1024B
19. An 8085 assembly language program is given below. E
Assume that the carry flag is initially unset. The
content of the accumulator after the execution of RAM
8 Bit data bus

the program is #3
1024B
MVI A, 07H E
RLC
MOV B, A RAM
A0A9 #2
RLC 1024B
E
RLC
ADD B
RAM
RRC #1
A10 1024B
(a) 8CH (b) 64H (c) 23H (d) 15H A11
A12 11 E
(GATE 2011: 2 Marks) A13 Input 10
A14 01
Solution. A15 S1 S0 00
MVI A, 07 H 0000 0111 content of A
RLC 0000 1110 content of A
MOV B, A 0000 1110 content of B (a) 0 C00H-0FFFH, 1C00H-1FFFH, 2C00H-2FFFH,
RLC 0001 1100 content of A 3C00H-3FFFH
RLC 011 1000 content of A (b) 1800H-1FFFH, 2800H-2FFFH, 3800H-3FFFH,
ADD B 4800H-4FFFH

(c) 0500H-08FFH, 1500H-18FFH, 3500H-38FFH, A10 = 0 , A11 = 1, A14 = 0 and A15 = 0

5500H-58FFH
(d) 0800H-0BFFH, 1800H-1BFFH, 2800H-2BFFH, In view of the above description, START ADDRESS
3800H-3BFFH A15-A0 for RAM-1 will be 0000100000000000. The
(GATE 2013: 2 Marks) LAST ADDRESS for the same can be determined
Solution. Since the range of RAM-1 is different in by adding 0000001111111111 to the above number
all four options, we will first check for RAM-1 only as size of RAM is 1024 bytes = 210 bytes. The
and then the same procedure can be followed for LAST ADDRESS is therefore 0000101111111111.
RAM-2, RAM-3 and RAM-4 if needed. RAM-1 will Hence, the range of RAM1-1 is 0800H to 0BFFH.
be selected when S0 = 0 and S1 = 0 , (S0 = A12 = 0, Ans. (d)
S1 = A13 = 0 ). Now, RAM-1 will be enabled when
the input of MUX is 1, or the output of AND gate
is 1. So,

PART V: SIGNALS AND SYSTEMS
12
10
Numbers of Questions
8
Marks 1
6
Marks 2
4
0
2015 2014 2013 2012 2011 2010 2009

704 Part V: SIGNALS AND SYSTEMS
Year Topic
2015 Parallel and cascade structure
Continuous-time Fourier transform
Definitions and properties of Laplace transform
Convolution
Sampling theorem
Quantisation
Discrete-time Fourier series
Linear Time-Invariant (LTI) systems impulse response
Linear Time-Invariant (LTI) systems frequency response
z-transform
Linear Time-Invariant (LTI) systems: definitions and properties
Discrete-time Fourier series and Fourier transform
2014 Linear Time-Invariant (LTI) systems: definitions and properties
z-transform
Sampling theorem
Continuous-time and discrete-time Fourier transform
Impulse response
Continuous-time Fourier series
Convolution-discrete
Definitions and properties of Laplace transform
Group delay, phase delay
RMS of a signal
Discrete-time Fourier series
2013 Definitions and properties of Laplace transform
DFT
Sampling theorem
Linear Time-Invariant (LTI) systems
Causality
Impulse response
Convolution
2012 Continuous-time and discrete-time Fourier transform
z-Transform
Causality
Continuous-time and discrete-time Fourier series
Continuous-time and discrete-time Fourier Transform
z-Transform
Stability
Impulse response
Continuous-time and discrete-time Fourier series
z-Transform
Frequency response
Convolution
Continuous-time and discrete-time Fourier Series
z-Transform
Frequency response
Signal transmission through LTI Systems

CHAPTER 29
LAPLACE TRANSFORM
This chapter discusses the Laplace transform, and its properties. Analysis and characterization of linear time invariant
(LTI) systems using Laplace transform is also discussed.
29.1 INTRODUCTION Whenever x(t) is linear combination of real and complex

exponentials, the Laplace transform X(s) is rational and
is given by
Laplace transform X(s) of a signal x(t) is given by
N (s)
X(s) = (29.3)
D(s)

st
X(s) = x(t)e dt (29.1)
where N(s) and D(s) are the numerator and the denomi-
nator polynomials, respectively.
where s is an independent complex variable given by
+ jw ( and w are the real and imaginary parts, respec-
The roots of the numerator polynomial are referred to
as zeros of X(s) and for those values of s, X(s) = 0. The
tively). The range of values of s for which the integral
roots of the denominator polynomial are referred to as
in Eq. (29.1) converges is referred to as the region of
poles of X(s) and for those values of s, X(s) is infinite. If
convergence (ROC) of the Laplace transform. Definition
the order of the denominator polynomial is greater than
given by Eq. (29.1) is referred to as the bilateral Laplace
the numerator polynomial, then X(s) is a proper rational
transform or two-sided Laplace transform. The unilat-
function and it becomes zero as s approaches infinity.
eral Laplace transform is given as follows:
Similarly, if the order of the numerator polynomial is
greater than that of the denominator, then X(s) is an
x(t)e
st
XU (s) = dt (29.2) improper rational function and it becomes unbounded as
0 s approaches infinity.

706 Chapter 29: Laplace Transform
29.1.1 Properties for ROC of Laplace It may be mentioned here that signals whose ROC do
Transforms not include the jw-axis do not have Fourier transform.
Table 29.1 lists some of the common Laplace transform
1. The ROC of X(s) consists of strips parallel to the pairs along with their region of convergence.
jw-axis in the s-plane.
2. For rational Laplace transforms, the ROC does not
contain any poles. 29.2 PROPERTIES OF LAPLACE
3. If x(t) is of finite duration and is absolutely inte- TRANSFORM
grable, then the ROC is in the entire s-plane.
4.If x(t) is right sided [Fig.29.1(a)] and if line Re{s =
0 is in the ROC, then all values of s for which Re{s Laplace transform has the following properties:
> 0 will also be in ROC. The ROC for such signals 1. Linearity: If
is referred to as right-half plane as if a point s is in
x1(t) X1(s) ROC R1 and
LT
the ROC, then all the points to the right of s, that is,
all points with larger real parts are also in the ROC. x2 (t) X2 (s) ROC R2
LT
5. If x(t) is left sided [Fig.29.1(b)] and if line Re{s
= 0 is in the ROC, then all values of s for which then we have
Re{s < 0 will also be in ROC. ROC for such
ax1(t) + bx2 (t) aX1(s) + bX2 (s)
LT
signals is referred to as left-half plane.
6. If x(t) is two sided and if line Re{s = 0 is in ROC containing R1 R2
the ROC, then ROC will consist of a strip in the
2. Time shifting: If
s-plane that includes the line Re{s = 0.
x(t) X(s) ROC R
7. If the Laplace transform X(s) of x(t) is rational, LT
then the ROC is bounded by poles or extends to
infinity. In addition, no poles of X(s) are contained then we have
x(t t0 ) est0 X(s) ROC R
in the ROC. LT
8. If the Laplace transform X(s) of x(t) is rational,
then if x(t) is right sided, the ROC is in the region 3. Shifting in s-domain: If
in the s-plane to the right of the rightmost pole. If
x(t) X(s) ROC R
LT
x(t) is left-sided, the ROC is in the region in the
s-plane to the left of the leftmost pole.
then we have
es0 t x(t) X(s s0 ) ROC R + Re{s0 }
LT
x(t)
4. Time scaling: If
x(t) X(s) ROC R
LT
then we have
1 s R
x(at) ROC
LT
X
a a
T0 t
a
(a) 5. Conjugation: If
x(t) X(s) ROC R
LT
x(t)
then we have
x*(t) X *(s*) ROC R
LT
When x(t) is real, then

X(s) = X*(s*)
t T0
6. Convolution: If
(b)
x1(t) X1(s) ROC R1 and
LT
Figure 29.1| (a) Right-sided signal; (b) Left-sided
x2 (t) X2 (s) ROC R2
signal. LT

29.2 PROPERTIES OF LAPLACE TRANSFORM 707
Table 29.1| Common Laplace transform pairs along with their region of convergence.
S. No. Signal Transform ROC
1 (t) 1 All s
1
2 u(t) Re{s > 0
s
1
3 u(t) Re{s < 0
s
tn1 1
4 u(t) Re{s > 0
(n 1)! sn
tn 1
5 u( t) 1
Re{s < 0
(n 1)! sn
ea tu(t)
1
6 Re{s > a
s+a
eat u( t)
1
7 Re{s < a
s+a
tn 1 at 1
8 e u(t) Re{s > a
(n 1)! (s + a )n
tn 1 at 1
9 e u( t) Re{s > a
(n 1)! (s + a )n
10 d(t T ) esT All s
[cos w0t]u(t)
1
11 Re{s > 0
s2 + w 02
w0
12 [sin w0t]u(t) Re{s > 0
s + w 02
2
[ eat cos w0t]u(t) s+a Re{s > a

13
(s + a )2 + w 02
w0
14 [eat sin w0t]u(t) Re{s > a
(s + a )2 + w 02
d nd (t)
15 un (t)= sn All s
n
dt
un (t) = u(t) * * u(t)

16 1
Re{s > 0
n times sn
then we have 7. Differentiation in time domain: If

x(t) X(s) ROC R
LT
x1(t) * x2 (t) X1(s)X2 (s)

LT
Then we have
ROC containing R1 R2
dx(t)
sX(s)
LT
ROC containing R
dt

8. Differentiation in s-domain: If 11. Final value theorem: The value of x(t) as t

tends to infinity is given by
x(t) X(s) ROC R
LT
lim x(t) lim sX(s)
Then t s 0
dX(s) Table 29.2 enlists these properties for easy reference.

tx(t) ROC R
LT
ds
9. Integration in the time domain: If 29.3 ANALYSIS AND
CHARACTERIZATION OF LTI SYSTEMS
x(t) X(s) ROC R
LT
USING LAPLACE TRANSFORM
then
t

X(s)
x(t )dt
LT
s 29.3.1 Causality

ROC containing R {Re(s) > 0} For a causal LTI system, the impulse response is zero for
10. Initial value theorem: If x(t) = 0 for t < 0 and t < 0 and is thus right sided. The ROC associated with a
x(t) contains no impulses or higher order singulari- system function for a causal system is a right-half plane.
ties at the origin, then Causality of an LTI system is equivalent to its impulse
response being absolutely integrable, that is, Fourier
x(0+ ) lim sX(s) transform of the impulse response converges.
s
Table 29.2| Properties of Laplace transform.
Property Signal** Laplace Transform ROC

Linearity ax1(t) + bx2(t) aX1(s) + bX2(s) At least R1 \ R2
Time shifting x(t t0) est0 X(s) R

Shifting in the s-domain es0 t x(t) X(s s0) Shifted version of R (i.e.,
s is in the ROC if s s0
is in R)
1 s
Time scaling x(at) X Scaled ROC (i.e., s is in
a a the ROC if s/a is in R)
Conjugation x * (t) X *(s*) R
Convolution x1(t) * x2 (t) X1(s)X2 (s) At least R1 \ R2
d
Differentiation in the time x(t) sX(s) At least R
domain dt
d
Differentiation in s-domain tx(t) X(s) R
ds
x(t )dt At least R1 \ {Re(s) > 0

1
Integration in the time X(s)
domain
s
Initial value theorem x(0+) = lim sX(s)

s
Final value theorem lim x(t)= lim sX(s)

t s 0
**Let x1(t), x2(t) and x(t) be with Laplace transforms and let X1(s), X2(s) and X(s) with ROC R1,
R2 and R, respectively.

29.4 INVERSE LAPLACE TRANSFORM 709
For a system with a rational system function, the cau-

sality of the system is equivalent to the ROC being the x(t) h1(t) h2(t) y(t)
right-half plane to the right of the rightmost pole. H1(s) H2(s)
Figure 29.3| Series interconnection of two systems.

29.3.2 Stability
An LTI system is stable if and only if the ROC of its h(t) = h1(t)*h2(t) (29.6)
system function H(s) includes the jw-axis, that is, Re{s
H(s) = H1(s)H2(s) (29.7)
= 0. A causal system with rational system function H(s) is
stable if and only if all the poles of H(s) lie in the left-half 29.3.3.3Feedback Interconnection of Two
of the s-plane, that is, all the poles have negative real parts. Systems
29.3.3 System Functions for Interconnections of Figure 29.4 shows the feedback interconnection of two
LTI Systems systems. Here, h1(t)[H1(s)] and h2(t)[H2(s)] are the
impulse responses of the systems in the forward and the
29.3.3.1Parallel Interconnection of Two feedback path, respectively, and h(t)[H(s)] is the impulse
Systems response of the combined system.
Figure 29.2 shows the parallel interconnection of two x(t) + e(t) h1(t) y(t)
+ H1(s)

systems having impulse responses h1(t)[H1(s)] and h2(t)
[H2(s)]. Here, h(t)[H(s)] is the impulse response of the
combined system.
h(t) = h1(t) + h2(t) (29.4)
H(s) = H1(s) + H2(s) (29.5) z(t) h2(t)
H2(s)
29.3.3.2Series Interconnection of Two
Systems Figure 29.4| Feedback interconnection of two systems.
Figure 29.3 shows the series interconnection of two sys- H1(s)

H(s) = (29.8)
tems having impulse responses h1(t)[H1(s)] and h2(t) 1 + H1(s)H2 (s)
[H2(s)]. Here, h(t)[H(s)] is the impulse response of the
combined system.
29.4 INVERSE LAPLACE TRANSFORM
h1(t)
H1(s)
Inverse Laplace transform of X(s) is given by
+ s + jw
x(t)
2pj s jw
y (t) 1
x(t) = X(s)est ds (29.9)
h2(t)
H2(s)
From Eq. (29.9), we can infer that x(t) can be repre-
Figure 29.2| Parallel interconnection of two systems. sented as a weighted integral of complex exponentials.
IMPORTANT FORMULAS
1. Laplace transform X(s) of a signal x(t) is 4. For the feedback interconnection of two systems,
H1(s)
X(s) = x(t)est dt H(s) =
1 + H1(s)H2 (s)

5. The inverse Laplace transform of X(s) is
2. For the parallel interconnection of two systems,
s + jw
h(t) = h1(t) + h2(t) and H(s) = H1(s) + H2(s) 1
X(s)est ds
2pj s jw
x(t) =
3. For the series interconnection of two systems,
h(t) = h1(t)*h2(t) and H(s) = H1(s)H2(s) 6. Formulas given in Tables 29.1 and 29.2.

SOLVED EXAMPLES
1. Laplace transforms of the function tu(t) and For the first term, the inverse Laplace transform
u(t)sin(t), respectively, are and ROC is
1 s 1 1 5e3tu(t) and Re{s >3

(a) , 2 (b) ,
2
s s +1 s s2 + 1
For the second term, the inverse Laplace transform
1 1 s and ROC is
(c) , (d) s,
3e2tu(t) and Re{s > 2
2 2 2
s s +1 s +1
Combining the two terms, we get

Solution. We have
, Re{s} > 2
1 2s + 4
tu(t)
LT X(s) =
2 2
s s + 5s + 6
Ans. (a)
u(t) sin at
LT a
s2 + a2 3. The Laplace transform of a function f(t)u(t), where
f(t) is periodic with period T, is A(s) times the
Therefore, Laplace transform of its first period. Then
u(t) sin t
LT 1 1
= 1
s2 + 12 s2 + 1 (a) A(s) = s (b) A(s) =
1 eTs
Ans. (c)
1
(c) A(s) = (d) A(s) = eTs
2. The Laplace transform and ROC for the signal 1 + eTs
x(t) = 5e3t u(t) 3e2t u(t) is
Solution. The given function represents a causal
(a)
2s + 4
, Re{s} > 2 periodic signal since f(t)u(t) = 0 (t < 0). Let us
s2 + 5s + 6 consider the following:
2s + 4 f (t)u(t) 0tT
(b) , Re{s} > 3 f1(t) =
s + 5s + 6
2
0 otherwise
, Re{s} > 2
s+2 Now,
(c) 2
f1(t nT )
s + 5s + 6
f (t)u(t) =
, Re{s} > 3
s+2 n =0
(d)
s2 + 5s + 6 Let f1(t) F1(s). Therefore,
Solution. The Laplace transform of the given f1(t nT ) enTs F1(s)

signal is
enTsF1(s) = 1 1eTs
F (s)
f (t)u(t) F (s) =
+
5e3t u(t) 3e2t u(t) est dt

n =0

X(s) =
1
f (t)u(t) Ts
Therefore, 1 e
[Transformofthefirstperiodoff (t)u(t)]
+ +
3t st
X(s) = 5 e e u(t)dt 3 e2t est u(t)dt Therefore,
1
A(s) =
=
5

3 1 eTs
s+3 s+2 Ans. (b)

SOLVED EXAMPLES 711
4. When a unit impulse is applied at t = 0 to an ini- The Laplace transform of a unit step function
tially relaxed linear constant parameter network, starting at t = a is
its response is 7e3tu(t). The response of this net-
1 eas
u(t a) eas =
work to a unit step function will be LT
s s
(a) [1 e3t ]u(t) (b) [et e3t ]u(t)
7 7
3 3 The Laplace transform of a unit ramp function is
(c) cos 3t (d) [sin3t 7e3t]u(t) LT 1
r(t)
Solution. Given that h(t) = 7e3t and x(t) = u(t). s2
Therefore, The Laplace transform of a unit ramp function
1 starting at t = a is
eas
H(s) = 7
(s + 3)
r(t a) eas 2 = 2
LT 1
1 s s
and X(s) = Ans. (c)
s
6. Given that Laplace transforms of x1(t) and x2(t) are
We know that
Y (s) X1(s) = 1 / (s + 4) and X2 (s) = 1 / [(s + 4)(s + 5)],,
H(s) = respectively. What is the Laplace transform of the
signal x1(t) x2(t)?
X(s)
Therefore,
1 1
Y(s) = H(s)X(s) (a) (b)
s+4 (s + 4)(s + 5)
Substituting the values of H(s) and X(s) in the
above equation, we get 1
(c) (d) None of these
7 1 s+5
Y (s) =
(s + 3) s
Solution. Let x(t) = x1(t) x2(t). We can write
7 1 1
=
3 s s + 3 L[x(t)] = X(s) = X1(s) X2(s)
Taking inverse Laplace transform on both sides, Hence,
we get
1 1 1
=
y(t) = [1 e3t ]u(t)
7 X(s) =
s + 4 (s + 4)(s + 5) s + 5
3
Ans. (a) Ans. (c)
5. The Laplace transforms of unit step and unit ramp 7. What is the ROC for the Laplace transform formu-
functions starting at t = a, respectively, are lated in Question 6?
1 1 eas eas (a) Re{s > 4 (b) 5 < Re{s < 4
(a) , (b) ,
(s + a) (s + a)2 (s + a) (s + a)2 (c) Re{s > 5 (d) None of these
eas eas a a
(c) , 2 (d) , 2 Solution. The pole at s = 4 is cancelled with a
s s s s zero at 4. The ROC hence is governed by the pole
at s = 5. Therefore, the ROC is
Solution. The Laplace transform of a unit step
function is Re{s > 5
1
u(t)
LT
s Ans. (c)
1. The Laplace transform of a function f(t) is

f (0+ ) = lim
4s(s + 1)
4(s + 1) s s2
2 . Find the value of f(0+). + 3s + 7
s + 3s + 7
4s2 + 4s
Solution. = lim
s s2 + 3s + 7
s2 [4 + (4 s)]
= lim
s s2 [1 + (3 s) + (7 s2 )]
4 + (4/s)
= lim
s [1 + (3 s) + (7 s2 )]
f (0+ ) = lim
4s(s + 1)
s s2 + 3s + 7
2
4s + 4s
= lim
s s2 + 3s + 7
Solution. The signal x(t) is a two-sided signal and
s2 [4 + (4 s)]
= lim it can be divided into sum of a right-sided and left-
s s2 [1 + (3 s) + (7 s2 )] sided signal.
= lim
4 + (4/s) x(t) = ebt u(t) + e+bt u(t)
s [1 + (3 2
s) + (7 s )]
Now,
=4
ebt u(t)
1
, Re{s > b
LT
Ans. (4) s+b
2. For the Laplace transform of the function f(t) given 1
e+bt u(t) , Re{s < +b
LT
in Question 1, find the value of f(). and
sb
Solution. There is no ROC if b 0 and thus for those values
f () = lim sF (s) of b, there is no Laplace transform. For b > 0, the
s 0
Laplace transform of x(t) is
4(s + 1)
= lim s 2 1 1

LT
s 0 s + 3s + 7 x(t)
s+b sb
=0
2b
Ans. (0) = , b < Re{s < b
b t s2 b2
3. For the signal x(t) = e , the ROC for Laplace
transform exists if the value of b > x. What is the Therefore, the value of x = 0.
value of x? Ans. (0)
PRACTICE EXERCISE
1. The pole-zero pattern of a certain filter is shown in 1 3 t

the following figure. (a) y(t) = t e + 4et + 6tet
2
(b) y(t) = t3et + 4et + 6tet
j
+j2 1 3 t t
(c) y(t) = t e + 4e
2
(d) y(t) = t3et + et
+j1
(2 Marks)

1 +1 3. The voltage across an impedance in a network
j1
is V(s) = Z(s)I(s), where V(s), Z(s) and I(s) are
the Laplace transform of the corresponding time
functions v(t), z(t) and i(t). The voltage v(t) is
j2 t
(a) v(t) = z(t) i(t) (b) v(t) = i(t )z(t t )dt
0
The filter must be of the type t
(a) low-pass (b) high-pass (c) v(t) = i(t )z(t + t )dt (d) v(t) = z(t) + i(t)
(c) all-pass (d) band-pass 0 (1 Mark)
(2 Marks) 2
4. The Laplace transform of cosh t is
2
d2y dy ts s2
2. The solution of the differential equation + 2 + y =(a)
3te (b)
2 dt2 dt s 4
2
s(s 4)
2
+ y = 3tet with initial conditions y(0) = 4

d y dy
2
+2
dt s2 2 s2 2
dt (c) (d)
dy(0) s(s2 4) s2 4
and =2 is (2 Marks)
dt

5. The Laplace transform of the periodic function (c) 0 and 1, respectively

which is given by (d) 1 and 0, respectively
(1 Mark)
sin t if (2n 1)p t 2np (n = 1, 2, 3,)
f (t) = 8. The transfer function of a linear system is the
0 otherwise
is (a) ratio of the output, v0(t), and input, v1(t)
ps
e (b)ratio of the derivatives of the output and the
(a) F (s) =
(s + 1)(1 eps )
2 input
(c)ratio of the Laplace transform of the output
1 and that of the input with all initial conditions
(b) F (s) =
(s + 1)(1 eps )
2 as zero
(d) None of these
1 + eps (1 Mark)
(c) F (s) =
(s2 + 1)(1 eps ) 9. The Laplace transform of eatsin(at)u(t) is equal to
(s a ) a
(d) None of these
(2 Marks) (a) (b)
(s + a )2 + a 2 (s a )2 + a 2
6. Which among the following two statements is true?
S1: If G(s) is a stable transfer function, then 1
(c) (d) None of these
F (s) =
1
is always a stable transfer function. (s a )2
G(s) (2 Marks)
S2: If G1(s) and G2(s) are stable transfer functions, s+4 s2 1
then F (s) = G1(s) G2 (s) is always a stable trans- 10. Given that L[f (t)] = , L[ g(t)] = ,
s2 1 (s + 4)(s + 2)
fer function. t
(a) S1 (b) S2 and h(t) = f (t )g(t t ) dt . Then the value of
(c) Both S1 and S2 (d) Neither S1 nor S2 0
(2 Marks) L[h(t)] is
s2 1 1
2(s + 1) - (a) (b)
7. If L[f (t)] = , then f(0 ) and f() are s+4 s+2
2s2 + 4s + 5
given by s2 1 s+4
(c) + (d) None of these
(a) 0 and 2, respectively (s + 4)(s + 2) s2 1
(b) 2 and 0, respectively (1 Mark)
1. The value of the pole for causal system with impulse 2. For the signal x(t) = 4d (t) + e2t u(t) + 7e3t u(t),
response h(t) = e2tu(t) is s = x. What is the value of x? the ROC is given by Re{s >x. Find the value of x.
(1 Mark) (2 Marks)
1. (c) In the given pole-zero pattern, poles and zeros Substituting the values of y(0) and y(0) in the
are symmetrical about imaginary axis. Therefore, above equation, we get
the filter is an all-pass filter.
3
2. (a) Taking Laplace transform on both sides, we get s2 Y (s) 4s 2 + 2(sY (s) 4) + Y (s) =
(s + 1)2
s2 Y (s) sy(0) y (0) + 2(sY (s) y(0)) + Y (s)
3 Solving the above equation and rearranging the
= terms, we get
(s + 1)2

3 10 + 4s 6. (b) If G(s) is stable, then all its poles must lie

Y (s) = 4
+ 2 on the left half of s-plane and there is no restric-
(s + 1)
(s + 1)
tion on its zeros, which can lie also in the right
3 4 6 half of s-plane. The inverse function F (s) = 1/G(s)
= + +
(s + 1)4 (s + 1) (s + 1)2 may or may not be stable as the zeros of G(s) are
Taking inverse Laplace transform, we get the poles of F(s). So, F (s) = 1/G(s) is not always
a stable transfer function. If G1(s) and G2(s) are
y(t) = t3et + 4et + 6tet
1
stable functions, then all the poles must lie on the
2
left half of the s-plane. Therefore, all the poles of
3. (b) Multiplication of two functions in frequency G1(s) G2(s) will also lie on the left half of the
domain is equivalent to the convolution in time s-plane. Therefore, [G1(s) G2(s)] is always a
domain. Therefore, stable function.
t
v(t) = i (t )z(t t )dt 7. (d) From the initial value theorem, we have
0
f (0+ ) = lim s 2
2(s + 1)
4. (c) The Laplace transform of cosh2t is
s 2s + 4s + 5
1 2

L[cosh2 t] = L et et ( ) 2s2 + 2s
2 = lim
s 2s2 + 4s + 5
e 2t 2 t
1 e
= L + + That is,
4 2 4
2+2 s
1 1 1 1 1 1
= f (0+ ) = lim
+ + 2 + (4 s) + (5 s2 )
4 s2 2 s 4 s+2 s
s2 2 =
2+0
= 2+0+0
s(s2 4)
=1
5. (a) The given signal f(t) is a causal periodic signal
with period, T0 = 2. Let us consider the following: From the final value theorem, we have
f (t) 0 < t < 2p f () = lim sF (s)
f1(t) = s 0
0 otherwise
Therefore, 2(s + 1)
= lim s 2
f1(t) = [sin(t p )u(t p ) + sin(t 2p )u(t 2p )] s 0 2s + 4s + 5
We know that Therefore,

, sin(t p ) u(t p )
1
sin(t) u(t) f () = 0
s2 + 1
eps e2ps
8. (c)
, sin(t 2p ) u(t 2p ) ,
s2 + 1 s2 + 1 9. (b) We have
and so on. Therefore, a
sin(a t) u(t)
LT
eps e2ps ps 1 + e
ps
s + a2
2
F1(s) = 2 + 2 = e 2
s + 1 s + 1 s + 1 That is,
Thus, a
eat sin(a t) u(t)
LT
(s a )2 + a 2
F1(s) F1(s)
F (s) = =
1e T0 s
1 e2ps
Therefore, 10. (b) Convolution in time domain is multiplication in
1 + e ps s-domain. Therefore,
F (s) = eps 2
1
2p s
s + 1 (1 e ) L[h(t)] = L[f (t)] L[ g(t)]
s
= es 2
(1 + e ) s + 4 s2 1
(s + 1)(1 + e s )(1 es ) (s + 4)(s + 2)

= 2
s 1
es 1
= s =
(s + 1)(1 e
2
) s+2

1 7
X(s) = 4 + +
s + 2 s 3
4(s + 2)(s 3) + (s 3) + 7(s + 2)

Numerical Answer Questions =
(s + 2)(s 3)
1. The Laplace transform of the impulse response is
4s2 + 4s 13
1 =
H(s) = (s + 2)(s 3)
s2
Therefore, the pole is at the location s = 2. Thus, Since the degree of the numerator and the denomina-
the value of x is 2. tor of X(s) are equal, X(s) has neither poles nor zeros
Ans. (2) at infinity. ROC is the set of values of s for which
2. The Laplace transform X(s) of x(t) is the Laplace transforms of all the three terms in x(t)
converge. The ROC of the first term is the entire
X(s) = 4 +
1
+
7 s-plane, ROC of the second term is Re{s > 2 and
s+2 s3 the ROC of the third term is Re{s > 3. Therefore,
the ROC of the given signal is Re{s > 3. Thus, the
4(s + 2)(s 3) + (s 3) + 7(s + 2)
= value of x is 3.
(s + 2)(s 3) Ans. (3)
4s2 + 4s 13
=
SOLVED GATE 2)(s 3)
PREVIOUS
(s + YEARS QUESTIONS
1. The Laplace transform of i(t) is given by 3. Consider the function f(t) having Laplace transform
2
I (s) = . As t , the value of i(t) tends to w0
s(1 + s) F (s) = Re{s} > 0
s + w 02
2
(a) 0 (b) 1 (c) 2 (d)
(GATE 2003: 1 Mark) The final value of f(t) would be
Solution. From the final value theorem, we get (a) 0 (b) 1
(c) 1 f() 1 (d)
lim i(t) = lim sI (s)
t s 0 (GATE 2006: 2 Marks)
2
= lim s =2 Solution. Inverse Laplace transform of the given
s 0 s(1 + s)
Ans. (c) equation is
2. In what range should Re{s} remain so that the L1[F (s)] = sin w 0 t
Laplace transform of the function e(a + 2)t + 5 exists?
(a) Re{s}>a + 2 (b) Re{s}>a + 7 Therefore, f(t) = sin w0t. Since the value of a sine
function varies between 1 and +1, we get
(c) Re{s}<2 (d) Re{s}>a + 5
1 f () 1
Ans. (c)
Solution.
4. If the Laplace transform of a signal y(t) is
st
X(s) = x(t)e dt
Y (s) =
1
, then its final value is
0 s(s 1)

= e5 e(a + 2)t est dt (a) 1 (b) 0
0
(c) 1 (d) Unbounded
(GATE 2007: 1 Mark)
= e5 e(sa 2)t dt
0
Solution. The final value theorem is applicable
5 only when all the poles of system lie on the left half
=
e et(sa 2) of the s-plane. Since s = 1 is a right s-plane pole.
a+2+s 0 Therefore, the system is unbounded.
e5 e(sa 2) 1
Ans. (d)
=
a+2+s 5. Given that F(s) is the one-sided Laplace transform
(sa2)
to be zero, Re{s a 2} > 0
t
f(t )dt
For e
of f(t), the Laplace transform of is
Therefore, Re{s} >(a + 2)
Ans. (a) 0

(a) sF(s) f(0)

1
7. Given f (t) = L1 3
(b) F (s) 3s + 1
s
s + 4s + (K 3)s
2
s
(c) F (t ) dt
1
(d) [F (s) f (0)]
s If lim f (t) = 1, then the value of K is
0 t
(GATE 2009: 2 Marks) (a) 1 (b) 2 (c) 3 (d) 4
Solution. The Laplace transform of f (t ) dt is

t
0 Solution. Given that:
1
F (s) f +
(0 ) F (s)
f (t) = L1 3
(3s + 1)
+ =
s + 4s + (K 3)s
s s s 2
with zero initial condition.

F (s) = L {f (t)} =
3s + 1
Ans. (b) or,
s + 4s2 + (K 3)s
3
6. A continuous time LTI system is described by
From the final value theorem
d 2 y(t) dy(t) dx(t)
+4 + 3y(t) = 2 + 4x(t) lim f (t) = lim sF (s)
dt2 dt dt t s 0
Assuming zero initial conditions, the response y(t)
of the above system for the input x(t) = e2tu(t)
Therefore,
(3s + 1)
is given by lim s =1
t 3t
s 0 s + 4s2 + (K 3)s
3
(a) (e e )u(t)
t 3t
(b) (e e )u(t) Hence,
(c) (et + e3t)u(t) (d) (et + e3t)u(t) 3s + 1
lim =1
(GATE 2010: 2 Marks) + 4s + K 3
s 0 s2
Solving the above equation, we get K = 4
Solution. It is given that Ans. (d)
8. If the unit step response of a network is (1 e-at),

2
d y(t) 4dy(t) 2dx(t)
2
+ + 3y(t) = + 4x(t)
dt dt dt then its unit impulse response is
Taking Laplace transform on both sides (assuming (a) aeat (b) a1eat
zero initial conditions), we get (c) (1 a1)eat (d) (1 a)eat
s2 Y (s) + 4sY (s) + 3Y (s) = 2sX(s) + 4X(s) (GATE 2011: 1 Mark)
Therefore,
Solution. The unit step response of the given net-
Y (s) 2s + 4 2(s + 2) work is
= =
X(s) s2 + 4s + 3 (s + 1)(s + 3) s(t) = (1 eat)
It is also given that Therefore, the unit impulse response is
x(t) = e2t u(t) s(t) = (1 ea t )= aea t

d d
h(t) =
dt dt
Ans. (a)
Therefore,
X(s) =
1 9. An input x(t) = exp(2t) u(t) + d (t 6) is applied
s+2 to an LTI system with impulse response h(t) =
Hence, u(t). The output is
2(s + 2) (a) [1 exp(2t)]u(t) + u(t + 6)
Y (s) =
(s + 1)(s + 3)(s + 2) (b) [1 exp(2t)]u(t) + u(t 6)
=
2
=
1

1 (c) 0.5[1 exp(2t)]u(t) + u(t + 6)
(d) 0.5[1 exp(2t)]u(t) + u(t 6)
(s + 1)(s + 3) (s + 1) (s + 3)
Taking inverse Laplace transform on both sides, (GATE 2011: 2 Marks)
we get
y(t) = (et e3t )u(t) Solution. It is given that
Ans. (b) x(t) = e2t u(t) + d (t 6)

Therefore, Solution. If L[f (t)] = F (s), then

+ e6s
1
X(s) =
s+2 dn
L[tn f (t)] = (1)n F (s)
It is also given that dsn
1 It is given that
H(s) =
s 1
Therefore, L[f (t)] = 2
= F (s)
s + s+1
Y (s) = X(s) H(s) Therefore,
+ e6s d1
1 1
= L[tf (t)] = (1)1 F (s)
s(s + 2) s ds1
1 1 1 1 6s

d
= + e = F (s)
2s s+2 s ds
d 1
= 2
Taking inverse Laplace transform, we have
y(t) = 0.5(1 e2t )u(t) + u(t 6) ds s + s + 1
Ans. (d) 1
= 2 2
(2s + 1)
2(s + 1) (s + s + 1)
10. If F (s) = L[f (t)] = 2 then the initial
s + 4s + 7
2s + 1
and final values of f(t), respectively, are = 2 2
(s + s + 1)
(a) 0, 2 (b) 2, 0 (c) 0, 2/7 (d) 2/7, 0
(GATE 2011: 2 Marks) Ans. (d)
Solution. 12. The impulse response of a system is h(t) = tu(t).
2(s + 1) For an input u(t 1), the output is
t(t 1)
F (s) = L[f (t)] = 2 t2
s + 4s + 7 (a) u(t) (b) u(t 1)
From the initial value theorem, 2 2
(t 1)2 t2 1
lim f (t) = lim sF (s)
t0 s (c) u(t 1) (d) u(t 1)
2 2
2(s + 1) (GATE 2013: 1 Mark)
= lim s 2
s s + 4s + 7
Solution. It is given that
2s2 [1 + (1 s)]
= lim h(t) = tu(t)
s s2 [1 + (4 s) + (7 s2 )]
Taking Laplace transform, we get
2(1 + 0) 1
= =2 H(s) = 2
(1 + 0 + 0)
s
From the final value theorem, It is also given that
2(s + 1)
lim f (t) = lim sF (s) = lim s =0 x(t) = u(t 1)
t s 0 s 0 s2 + 4s + 7
Ans. (b) Taking Laplace transform, we get
11. The unilateral Laplace transform of f(t) is es
1 X(s) =
2
. The unilateral Laplace transform of tf(t) s
s + s+1
is Y (s)
s 2s + 1 Since = H(s) , therefore
(a) 2 2 (b)
2 X(s)
(s + s + 1) (s + s + 1)2
2s + 1 Y(s) = H(s)X(s)
s
(c) (d) 2
(s + s + 1)2 1 es es
2 2
(s + s + 1)
Hence, Y (s) = . =
(GATE 2012: 1 Mark) s2 s s3

Taking the inverse Laplace transform, we get 1 0 < t < 2

x(t) =
(t 1) 2 0 otherwise
y(t) = u(t 1)
2 dy(t )
Ans. (c) Assuming that y(0) = 0 and = 0 at t = 0,
dt
13. Assuming zero initial condition, the response y(t) the Laplace transform of y(t) is
of the system (shown in the following figure) to a
unit step input u(t) is e2s 1 e2s
(a) (b)
s(s + 2)(s + 3) s(s + 2)(s + 3)
U(s) Y(s) e2s 1 e2s

1/s (c) (d)
(s + 2)(s + 3) (s + 2)(s + 3)
(a) u(t) (b) tu(t) Solution. It is given that
t2 x(t) = u(t) u(t 2)

(c) u(t) (d) etu(t)
2 Therefore,
(GATE 2013: 1 Mark)
1 e2s 1 e2s
X(s) = =
Solution. It is given that x(t) = u(t) and s s s
1 It is also given that
H(s) =
s
d 2 y(t) dy(t)
+5 + 6y(t) = x(t)
Taking Laplace transform, we get dt 2 dt
1 Taking Laplace transform on both the sides and
X(s) =
s assuming
1 1 1 dy(t)
Y(s) = H(s)X(s) = = 2 y(0) = 0 and =0
s s s dt t=0
Taking inverse Laplace transform, we get we get
y(t) = tu(t) s2 Y (s) + 5sY (s) + 6Y (s) = X(s)

Ans. (b)
Therefore,
1 e2s 1 e2s
14. A system is described by the differential equation
d 2 y(t ) dy(t ) Y (s) = =
2
+5 + 6y(t) = x(t). Let x(t) be a rect- s(s2 + 5s + 6) s(s + 2)(s + 3)
dt dt
angular pulse given by Ans. (b)

CHAPTER 30
CONTINUOUS-TIME AND DISCRETE-TIME FOURIER SERIES
30.1 FOURIER SERIES

REPRESENTATION OF CONTINUOUS- x(t) = a0 + (ak cos kwt + bk sin kwt) (30.2)
k =1
TIME PERIODIC SIGNALS
where
T
1
For continuous-time periodic signal x(t) which is having a0 =
T x(t)dt
time period T and fundamental frequency w 0, the Fourier 0
T
x(t) cos kw t dt
series representation is given by Eq. (30.1): 2
ak =
T
ck e jkw 0 t = ck e jk(2p/T )t (30.1)
0
x(t) = T
k = k =
x(t) sin kw t dt
2
bk =
where ck are the Fourier series coefficients or spectral T 0
components of x(t) and are given by For even functions x(t) = x(t), the Fourier series does
not contain the sine terms and for odd functions x(t) =
1 jkw 0 t 1 jk(2p / T )t
ck = T x(t)e dt = T x(t)e dt x(t), the Fourier series contains only the sine terms.
T T For the half-wave symmetric functions x(t) = x(t T/2),
In terms of sine and cosine functions, the Fourier series where T is the time period, the odd harmonics of both
representation is given by sine and cosine terms are present. For the Fourier series

720 Chapter 30: Continuous-Time and Discrete-Time Fourier Series
representation given in Eq. (30.2), the effective or the 3. Time reversal: If

rms power of the signal x(t) is given by FS
x(t) ak
1
x(t)rms = a02 + (a12 + a22 + a32 + + b12 + b22 + b32 + ) then we have
2
x(t) ak
FS
(30.3)
The rms value of a signal x(t) over an interval (a, b) is The time reversal applied to a continuous-time
also given as signal results in a time reversal of the correspond-
ing sequence of the Fourier series coefficients. For
b
x(t)
2 even signals,
dt
a x(t) = x(t)
x(t)rms = (30.4)
(b a)
Therefore,
30.1.1 Convergence of Fourier Series ak = ak
For a signal to have a Fourier series representation, it For odd signals,

should satisfy the following conditions: x(t) = x(t)
1. Over any period, x(t) must be absolutely integra-
Therefore
ble, that is, T x(t)dt < .
ak = ak
2. In any finite interval of time, x(t) is of bounded
variation, that is, there are no more than finite 4. Time scaling: If
number of maxima and minima during any single

period of the signal. x(t) = ak e jkw 0 t
3. In any finite interval of time, there are only a finite k =
number of discontinuities and each of these discon-
tinuities is finite. then

x(a t) = ak e jkw 0a t
30.1.2 Properties of Continuous-Time Fourier
k =
Series
The Fourier series coefficients do not change due
1. Linearity: Let x(t) and y(t) denote two periodic to time scaling, but the Fourier series representa-
signals with period T having Fourier series coeffi- tion has changed due to change in the fundamental
cients denoted by ak and bk, respectively: frequency.
FS FS 5. Multiplication: Let x(t) and y(t) denote two
x(t) ak and y(t) bk
periodic signals with period T having Fourier series
The Fourier series coefficients ck of the linear com- coefficients denoted by ak and bk, respectively. If
bination of x(t) and y(t) and [z(t) = Ax(t) + By(t)]
FS FS
are given by the same linear combination of the x(t) ak and y(t) bk
Fourier series coefficients for x(t) and y(t).
FS then we have
z(t) = Ax(t) + By(t) ck = Aak + Bbk

x(t)y(t)
FS
2. Time shifting: If al bk l
l =
FS
x(t) ak
The Fourier series coefficients for a signal, which is
Then we have the time domain product of two signals, are given
x(t t0 ) ejkw 0 t0 ak = ejk(2p / T )t0 ak

FS by discrete-time convolution of the Fourier series
coefficients of the two signals.
That is, when a periodic signal is shifted in time, 6. Conjugation and conjugate symmetry: If
the magnitudes of its Fourier series coefficients FS
x(t) ak
remains unaltered.

30.2 FOURIER SERIES REPRESENTATION OF DISCRETE-TIME PERIODIC SIGNALS 721
then we have relation states that the total average power in a

periodic signal is equal to the sum of the average
x * (t) a *k
FS
powers in all of its harmonic components.
Taking the complex conjugate of a periodic signal Properties mentioned in the above list are enumerated in
x(t) has the effect of complex conjugation and time Table 30.1 for easy reference.
reversal on the corresponding Fourier series coef-
ficients. When x(t) is real,
30.2 FOURIER SERIES
x(t) = x*(t)
REPRESENTATION OF DISCRETE-
then the Fourier series coefficients are conjugate TIME PERIODIC SIGNALS
symmetric. That is,
ak = a *k
For discrete-time periodic signal x[n], having fundamen-
7.Parsevals relation for continuous-time signals: tal period N, Fourier series representation is given by
Eq.(30.5):

1 2 2
T x(t) dt = ak
ak e jkw 0 n = ak e jk(2p / N )n (30.5)
T k = x[n ] =
k= N k= N
The LHS of this equation represents the average
where
power (energy per unit time) in one period of the

2
x[n ]ejkw 0 n = x[n ]ejk(2p / N )n
periodic signal. ak is the average power of the kth 1 1
ak =
harmonic component of x(t). Therefore, Parsevals N n= N N k= N
Table 30.1| Properties of continuous-time Fourier series.
Property Periodic Signal Fourier Series Coefficients

ak
x(t) Periodic with period T and

y(t) fundamental frequency w 0 = 2p /T
bk
Linearity Ax(t) + By(t) Aak + Bbk
Time shifting x(t t0 ) ak ejkw 0 t0 = ak ejk(2p / T )t 0
Frequency shifting e jMw 0 t x(t) = e jM (2p / T )t x(t) akM
Conjugation x*(t) a*k
Time reversal x( t) ak
Time scaling x(a t), a > 0 (periodic with period T /a ) ak
Periodic convolution x(t )y(t t )dt Takbk

T

Multiplication x(t)y(t) al bk l
l =
d 2p
Differentiation x(t) jkw 0 ak = jk ak
dt T
(Continued)

t 1 1
Integration x(t)dt (finite valued and periodic only if jkw ak = jk(2p /T ) ak
0

a0 = 0)
Conjugate symmetry x(t) real ak = a*k

for real signals Re{a } = Re{a }
k
k
Im{ak } = Im{ak }
ak = ak

ak = ak
Real and even signals x(t) real and even ak real and even
Real and odd signals x(t) real and odd ak purely imaginary and odd
Evenodd xe (t) = Ev{x(t)} [x(t) real] Re {ak }

x (t) = Od{x(t)}
decomposition of real o [x(t) real] j Im {ak }
signals
Parsevals relation for
1 2 2
periodic signals
T T x(t) dt = ak
k =
It may be noted that for discrete-time periodic signals, then we have

x[n ] ak
ak = ak N FS
30.2.1 Properties of Fourier Series of Discrete- For even signals, x[n] = x[n]. Therefore, ak = ak
Time Periodic Signals For odd signals, x[n] = x[n]. Therefore, ak =
ak
1. Linearity: Let x[n] and y[n] denote two periodic
4. Time scaling: If
signals with fundamental period N having the
Fourier series coefficients denoted by ak and bk,
x[n/m] if n is a multiple of m
respectively, that is, x m [n ] =
0 if n is not a multiple of m
x[n ] ak and y[n ] bk
FS FS
and
The Fourier series coefficients ck, of the linear com- FS
x[n ] ak
bination of x[n] and y[n] and [z[n] = Ax[n] + By[n]],
are given by the same linear combination of the then we have
Fourier series coefficients for x[n] and y[n].
FS 1
FS x m [n ] a
z[n ] = Ax[n ] + By[n ] ck = Aak + Bbk m k
2. Time shifting: If 5.Multiplication: Let x[n] and y[n] denote two peri-
FS odic signals with fundamental period N having Fourier
x[n ] ak series coefficients denoted by ak and bk, respectively. If
then we have
FS FS
x[n ] ak and y[n ] bk
x[n n0 ] ejk(2p /N )n0 ak
FS
Then we have
3. Time reversal: If
x[n ] ak
FS
FS
x[n ]y[n ] al bk l
l= N

30.2 FOURIER SERIES REPRESENTATION OF DISCRETE-TIME PERIODIC SIGNALS 723
6. Conjugation and conjugate symmetry: If 7. Parsevals relation for discrete-time signals:

FS 1 2 2
x[n ] ak
N
x[n ] = ak
n= N k= N
then we have
FS The properties mentioned in the list above are enumer-
x * [n ] a *k ated in Table 30.2 for easy reference.
Table 30.2| Properties of discrete-time Fourier series.
x[n ] Periodic with period N and ak

y[n ] fundamental frequency w0 = 2 p/N
Periodic with period N
bk
Linearity Ax[n ] + By[n ] Aak + Bbk
jk(2p / N )n0
Time shifting x[n n0 ] ak e
Frequency shifting e jM (2p /N )n x[n ] akM

Conjugation x*[n ] a*k
Time reversal x[ n ] ak
x[n/m] if n is a multiple of m 1
Time scaling x m [n ] = a
0 if n is not a multip
ple of m m k
(periodic with period mN) (viewed as periodic with period mN)
Periodic convolution x[r ]y[n r ] Nakbk

r= N
Multiplication x[n ]y[n ] al bk l

l= N
First difference x[n ]y x[n 1] (1 ejk(2p /N ))ak

n
1
Running sum x[k ] a
jk(2p / N ) k
k = 1e
(finite valued and periodic only if a0 = 0)
Conjugate symmetry for x[n] real ak = a*k

{ k } = Re{ak }
real signals Re a
Im{ak } = Im{ak }
ak = ak

ak = ak
Real and even signals x[n] real and even ak real and even
Real and odd signals x[n] real and odd ak purely imaginary and odd
Evenodd xe [n ] = Ev{x[n ]} [x[n ] real] Re {ak }
x [n ] = Od{x[n ]}
o
decomposition of real [x[n ] real] j Im {ak }
signals
Parsevals relation for
1 2 2
periodic signals
N
x[n ] = ak
n= N k= N

IMPORTANT FORMULAS
1. The Fourier series representation of a continuous- 3. The Fourier series representation of a discrete-time
time signal x(t) is periodic signal x[n], having fundamental period,
N, is
x(t) = ck e jkw 0 t = ck e jk(2p / T )t
k = k =
x[n ] = ak e jkw 0 n = ak e jk(2p / N )n
2. The rms value of a signal x(t) in terms of Fourier k= N k= N
series coefficients is
4. Formulas listed in Tables 30.1 and 30.2.
1
x(t)rms = a02 + (a12 + a22 + a32 + + b12 + b22 + b32 + )
2
SOLVED EXAMPLES
1. Waveform 5coswt is applied to a half-wave recti- Vm

= [1 (1)]
2p
fier. The average value and the peak value of the
fundamental component of the output waveform,
V
respectively, are given by = m 2
2p
10 5 10 10 Vm
(a) V, V (b) V, V
p 2 p 2 =
p
5 5 10 5
(c) V, V (d) V, V
p 2 p 2 In this case, Vm = 5 V. Therefore, DC value =
5
V
p
Solution. Let vi (t) = Vm cos(w o t) be the input The peak value of the fundamental component is
waveform, with time period To and the fundamen- given by
tal frequency wo, where To = 2p/wo. The output
To T o
2
waveform is given by a1 = v (t) cos(wo t) dt
o
To
vo (t) = Vm cos(w o t) t Therefore,
4 To /4

2
The Fourier series of vo(t) is given by a1 = Vm cos(w o t) cos(w o t) dt
To To /4
vo (t) = a0 + a1 cos(w o t) + a2 cos(2w o t) + To /4
Vm cos
2
= 2
(wo t) dt
where a0 is the DC value or the average value To To / 4
which is given by
(1 + cos 2wo t)
To / 4
To T o
1

a0 = v (t) dt 2V
= m dt
o
To To /4
2
To /4

1
Vm cos(w o t) dt
That is,
=
2Vm o
To T /4 To /4
To /4
dt + cos 2w o t dt
a1 =
2To T /4 T /4
1 Vm [sin w o t ]To /4
T /4
o
o
o
=
To wo V T T
= m o o
Vm p p To 4 4
= sin sin
2p 2 2 Vm To V
= = m
To 2 2

SOLVED EXAMPLES 725
5 Solution. The trigonometric Fourier series of a peri-

In this case, V m = 5 V. Therefore, peak value = V odic time function has both cosine and sine terms.
2
Ans. (c)
Ans. (c)
4. A periodic signal x(t) of period T0 is given by
2. Which of the following signal is non-periodic?
1, t < T1
(a) s(t) = cost + cos3t + cos7t
x(t) = T0
0, T1 < t < 2
(b) s(t) = exp(j9pt)
(c) s(t) = exp(7t)sin10pt
(d) s(t) = cos2t cos4t The DC component of x(t) is
Solution. T1 T1
(a) (b)
(a) s(t) is periodic as the ratio of any two frequen- T0 (2T0 )
cies of the waveform is given by p/q, where
p and q are integers. 2T1 T0
(c) (d)
(b) s(t) is periodic with w = 9p. T0 T1
(c) exp (7t) is an exponentially decaying function
and therefore exp(7t) sin10pt is not a periodic Solution. The given periodic signal x(t) has the
signal. time period T0. Therefore,
T0 / 2
(d) s(t) is non-periodic.
x(t) dt
1
xDC =
We know that T0 T0 / 2
2cosA cosB = cos(A B) + cos(A + B). Therefore,
T1
Therefore,

1
xDC = 1 dt
1 T0
s(t) = [cos 2t + cos 6t] T1
2
1 T1
= [t ]
T0 T1
Hence, s(t) given in option (d) is periodic with fun-
damental frequency 2 rad/s.
1
Ans. (c) = [ T (T1 )]
3. The trigonometric Fourier series of a periodic time T0 1
function can have only 2T1
=
(a) cosine terms (b) sine terms T0
(c) cosine and sine terms (d) DC and cosine terms Ans. (c)
1. The rms value of a rectangular wave of period 10s, 2. One period (0, T) each of two periodic waveforms
having a value of +10 V for a duration of 4 s and W1 and W2 are shown in the following figure. The
10 V for the duration of 6 s equals . magnitude of the fifth Fourier series coefficient of
W1 is proportional to .
Solution. The rms value of any signal x(t) having
time period T is given by 1 1
T
1 2
RMS = x (t) dt W1 W2
T 0
Therefore, the rms value of the given signal is T/2 T T
4 10 0 0 T/2
1
102 dt + (10)2 dt
10 0 4
1
1
= [102 [4 0 ] + (10)2 (10 4)] 1
10
= 102
Solution. For the continuous-time periodic signal
= 10
x(t), having time period T and the fundamental
Ans. (10)

frequency w0, the Fourier series representation is 3. Refer to the data and figures of Question 2. The
given by magnitude of the fifth Fourier series coefficient of
W2 is proportional to .
x(t) = ak e jkw 0 t = ak e jk(2p / T )t
k = k =
Solution. Refer to the Solution of Question 2.
For the rectangular pulses,
A triangular waveform is obtained after integrating
At sin kw 0t /2 t
sin kw 0
2A the rectangular waveform. Therefore,
ak = =
T kw 0t /2 Tkw 0 2
1
Therefore, ak
1 k2
ak
k Hence, for k = 5,
Hence, for k = 5
ak 0.2 ak 0.04
Ans. (0.2) Ans. (0.04)
PRACTICE EXERCISE

1 1 1
1. The Fourier series representation of an impulse Then the sum of the series 1 + 2
+ 2
+ is
3 5 72
train s(t) = d (t nT ) is given by
n = p2 p2

j2pnt jpnt
(a) (b)
exp T (b) T exp T
1 1 2 8
(a)
T n = n = (c) p (d) p2

1
jpnt 1
j2pnt (2 Marks)
(c)
T
exp
T
(d)
T
exp
T 4. A function f(x) satisfies the following two condi-
n = n =
(2 Marks) tions: f(x) = f(x) and f(x + p) = f(x). Which
of the following statements are true?
2. The waveform shown in the following figure con-
tains (a) a0 = a1 = a2 = a3... = 0 and b2 = b4 = b6 = ... = 0
(b) a0 = a1 = a2 = a3... = 0 and b1 = b3 = b5 = ... = 0
f(t) (c) a0 = a1 = a2 = a3... = p and b2 = b4 = b6 = ... = 0
(d) a0 = a1 = a2 = a3... = p and b1 = b3 = b5 = ... = 0
1
(1 Mark)
3T/4 T/4 0 T/4 3T/4 t 5. Given that the Fourier series of the function
px 0 x 1
p (2 x)
f (x) =
1 1x2
p 4 cos p x cos 3p x cos 5p x

(a) odd cosine terms (b) even cosine terms is + + + .... . Then
(c) odd sine terms (d) even sine terms 2 p 12 32
52

(1 Mark) 1 1 1
the value of 2 + 2 + 2 + .... is
3. The Fourier series of the periodic function (with 1 3 5
period 2p) defined by
p2
0, p < x < 0 (a) p2 (b)
16
x, 0 < x < p
f (x) =
is p2 p2
(c) (d)
8
p 1
4
+ 2 [cos(np ) 1]cos(nx) cos(np ) sin(nx) .
1
(2 Marks)
4 1 pn n

1. A function f(x) with period 2T is given by 2. Given that f (x) = x2 in the interval p < x <
if T < x < 0 cp a
2 p. The value of 4 + 4 + 4 + 4 + + =
1 1 1 1
.
f (x) =
4 if 0 < x < T 1 2 3 4 b
Then, find the value of a. (2 Marks)
What does the Fourier series of the function con-
3. What is the value of b for the data given in Question 2.
verge to when x = 0?
(1 Mark)
(1 Mark) 4. Find the value of c for the data given in Question 2.
(1 Mark)
1. (d) The Fourier series expansion of any periodic 3. (b) Time period is given by
signal x(t) is given by T = p (p)= 2p

jnw 0 t At the point of discontinuity x = p, f(x) expressed
x(t) = an e
in Fourier series converge to the middle value p /2.
n =
where From the given trigonometric form of Fourier
series, at x = p, we get
1 jnw 0 t
an = T x(t)e dt
p 2
f(p ) =
T 1 1 1
+ 1 + 2 + 2 + 2 .....
Therefore, for an impulse train, 4 p 3 5 7
Therefore,
s(t) = (t nT )
n =
p p 2 1 1 1
= + 1 + 2 + 2 + 2 .....
T /2 2 4 p 3 5 7
(t)ejnw 0 t dt =
1 1
an = Hence,
p2
T T / 2
T
1 1 1
1 + 2 + 2 + 2 ..... = 8
Therefore, 3 5 7
4. (a) The function is an odd function, so all cosine
e jnw 0 t = e j2pnt / T
1 1
s(t) = terms a1, a2, a3, ... are zero. The function has zero
T n = T n = DC value; therefore, a0 = 0. The function is half-
wave symmetric; therefore, it contains only odd
2. (a) The waveform is an even function[x(t) = x(t)],
terms. Hence, b2 = b4 = b6 = .... = 0.
therefore, the Fourier series contains the cosine
terms. The average power of the waveform over 5. (d) It is given that value of f(x) at x = 2 is 0. It
one period is zero; therefore, a0= 0. The waveform is also given that Fourier series representation of
is a half-wave symmetric function [x(t) = x(t f(x) is
T/2), where T is the time period. Therefore, the p 4 cos p x cos 3p x cos 5p x
f (x) = + + + ....
Fourier series representation contains odd harmon- 2 p 12 32 52
ics of both sine and cosine terms.
Substituting x = 2 and solving, we get
Combining all information, the Fourier series rep-
resentation of the waveform contains odd harmon- 1 1 1 p2
2 + + + .... = 8
ics of cosine terms. 1 32 52
1. The series converges to the average value of f(x) 2. Using the Fourier series expansion
around x = 0. Therefore, the series converges to

2+4
2
=3 x(t) = a0 + (an cos nw t + bn sin nw t)
Ans. (3) n =1

The values of a0, an and bn can be calculated to be Equating the two and taking square on both sides,
p2
we get
a0 =
p4 p4
3
1
4 + 8 4 =
an = 2 ( 1)n
n
9 1 n 5
bn = 0
Therefore,
The rms value of f(x) in the interval (p, p) is
p4
given as
1 1 1 1 1
( ) n4
1 = + + + + .... =
f (x)rms = a02 + a12 + a22 + a32 + + b12 + b22 + b32 + .... 1 14 24 34 44 90
2

p4 Therefore, a = 4. Ans. (4)
+ 8 4
1
=
9 1 n 3.Referring to Solution of Problem 2, we get the
The value of rms value of f (x) in the interval (p, p) value of b = 90. Ans. (90)
is also given as
p 4.Referring to Solution of Problem 2, we get the
1 2 p4
f (x)rms = f (x) dx = value of c = 1. Ans. (1)
2p p
5
1. The Fourier series expansion of a real periodic that fourier series cannot be defined for functions
signal with fundamental frequency f0 is given by that are not periodic or constant. Therefore, (c) is
the correct answer.
g p (t) = cn e j2pnf0 t Ans. (c)
n = 3. The Fourier series of a real periodic function has only
It is given that c3 = 3 + j5. Then c3 is
P: cosine terms if it is even
(a) 5 + j3 (b) 3 j5 Q: sine terms if it is even
(c) 5 + j3 (d) 3 j5 R: cosine terms if it is odd
(GATE 2003: 1 Mark) S: sine terms if it is odd
Solution. For a real periodic signal, Which of the above statements are correct?
(a) P and S (b) P and R
ck = c*k (c) Q and S (d) Q and R
(GATE 2009: 1 Mark)
Given that c3 = 3 + j5. Therefore,
Solution. The Fourier series of a real periodic
c3 = c*k = 3 j5 function has only cosine terms if it is even and only
Ans. (d) sine terms if it is odd.
Ans. (a)
2. Choose the function f(t), < t < , for which a
Fourier series cannot be defined. 4. The trigonometric Fourier series of an even func-
tion does not have the
(a) 3 sin (25t)
(a) DC term (b) cosine terms
(b) 4cos (20t + 3) + 2 sin(710t)
(c) sine terms (d) odd harmonic terms
(c) exp( t ) sin(25t) (GATE 2011: 1 Mark)
(d) 1
(GATE 2005: 1 Mark) Solution. Trigonometric Fourier series of an even
function has DC and cosine terms only and does
Solution. Excluding option (c), all other functions not have the sine terms
are either periodic or constant functions. We know Ans. (c)

CHAPTER 31
CONTINUOUS-TIME AND DISCRETE-TIME

FOURIER TRANSFORM
This chapter discusses the continuous-time and discrete-time Fourier transforms, their properties and analysis and
characterization of linear time invariant (LTI) systems using them. In addition, the discrete Fourier transform (DFT)
and fast Fourier transform (FFT) are also covered in the chapter.
31.1 CONTINUOUS-TIME FOURIER

TRANSFORM X(jw ) = x(t)e jw tdt (31.2)

The inverse Fourier transform of X(jw) is given by
The continuous-time Fourier Transform X(jw) of a

X( jw )e jw t dw
signal x(t) is given by 1
x(t) = (31.3)
2p
X( jw ) = x(t)ejw t dt (31.1) For a periodic signal x(t) with Fourier series coefficients

ak, the Fourier transform is a train of impulses occurring
Here, X(jw) is a complex variable and can be expressed at the harmonically related frequencies and for which
as the area of the impulse at the kth harmonic frequency
kw0 is 2p times the kth Fourier series coefficient ak. That
X( jw ) = X( jw ) e jq (w ) is, if
where Xj(w ) is the magnitude of X(jw), q(w) is the +
angle (or phase) of X(jw). Substituting w by -w in x(t) = ak e jkw 0 t
k =
Eq. (31.1), we get

730 Chapter 31: Continuous-Time and Discrete-Time Fourier Transform

then the Fourier transform is given by
+
X( jw ) =
2p akd (w kw 0) (31.4) Signal Fourier Transform
k =
eat u(t), Re{a} > 0 1
a + jw
Table 31.1 lists some of the common Fourier transform
pairs.
teat u(t), Re{a} > 0
1
Table 31.1| Common Fourier transform pairs. (a + jw )2
Signal Fourier Transform tn 1 at

e u(t)
(n 1)! 1
+ +
Re{a} > 0 (a + jw )n
ak e jkw 0t 2p akd (w kw 0 )
k = k =
e jw 0 t 2pd (w w 0 ) 31.1.1 Convergence of Fourier Transform

cos w 0 t p [d (w w 0 ) + d (w + w 0 )] The sufficient conditions for convergence of Fourier
transform are the following. These conditions are referred
p to as the Dirichlet conditions. +
sin w 0 t [d (w w 0 ) d (w + w 0 )]
j 1. x(t) is absolutely integrable, that is, x(t) dt < .

x(t) = 1 2pd (w ) 2. x(t) has finite number of maxima and minima in
any finite interval of time.
Periodic square wave 3. x(t) has finite number of discontinuities in any
1, t < T1
finite interval of time and these discontinuities are
+
2sinkw 0 T1

finite.
x(t) = T d (w kw 0 )
0, T1 < t k = k
2
and 31.2 PROPERTIES OF CONTINUOUS-
x(t + T ) = x(t) TIME FOURIER TRANSFORM
+ +
2p 2p k Continuous-time Fourier transform has the following
d(t nT ) dw
T
properties:
n = T k =
1. Linearity: If
1, t < T1 x1(t) X1( jw ) and x2 (t) X2 ( jw )

FT FT
2sinw T1
x(t)
0, t < T1 w
then we have
ax1(t) + bx2 (t) aX1( jw ) + bX2 ( jw )

FT
sin WT 1, w < W
X(jw ) =
pt 0, w > W 2. Time and Frequency shifting: If
d(t) x(t) X( jw )
FT
1
then we have
x(t t0 ) ejw t0 X( jw )
1
u(t) + pd (w ) FT
(time shifting)
jw
Also
d(t t0 ) e jw t0
x(t)e jw 0 t X( j(w w 0)) (frequency shifting)
FT
(Continued)

31.3 FREQUENCY RESPONSE OF CONTINUOUS-TIME LTI SYSTEMS 731
3. Time and frequency scaling: If 9. Convolution: If
x(t) X( jw ) x1(t) X1( jw ), x2 (t) X2 ( jw )

FT FT FT
and
y(t) Y ( jw )
FT
Then we have
1 jw
x(at) X
FT
then we have
a a
y(t) = x1(t) x2 (t) Y ( jw ) = X1( jw )X2 ( jw )
FT
4. Conjugation and conjugate symmetry: If
x(t) X( jw )
FT 10. Multiplication in time-domain: If
x1(t) X1( jw ), x2 (t) X2 ( jw ) and

FT FT
then we have
y(t) Y ( jw )
FT
x*(t) X *(jw )
FT
then we have
When x(t) is real, then we get the following:
y(t) = x1(t)x2 (t) Y ( jw )
FT
i. X(-jw) = X*(jw)
ii. Even part of x(t) Re{X( jw )}
FT
1
X ( jw ) X2 ( jw )
2p 1
=
iii. Odd part of x(t) j Im{X( jw )}
FT
5. Differentiation in time-domain: If 11. Parsevals relation:

+ +
x(t) X( jw )
FT

1
X( jw ) dw
2 2
x(t) dt =

2p
then we have
dx(t) The total energy in the signal x(t) can be determined
jwX( jw )
FT 2
dt by computing the energy per unit time x(t) and
integrating over all time or by combining energy per
d n x(t)
( jw )n X( jw ) unit frequency X( jw ) 2p and integrating over all
FT 2
n
frequencies. The term X( jw ) is also referred to as
dt 2
6. Differentiation in frequency-domain: If the energy-density spectrum of the signal x(t).
x(t) X( jw )
FT Table 31.2 enlists the properties discussed above for easy
reference.
then we have
dX( jw )
(jt)x(t) 31.3 FREQUENCY RESPONSE OF
FT
and
dw CONTINUOUS-TIME LTI SYSTEMS
d n X( jw )
(jt)n x(t)
FT
dw n
Let x(t) be the input to the LTI system, h(t) be its
7. Integration in time-domain: If impulse response and y(t) be the output. Then
y(t) = x(t) h(t)
x(t) X( jw )
FT (31.5)
Let X(jw), Y(jw) and H(jw) be the Fourier transform of
then we have x(t), y(t) and h(t), respectively. Then
Y ( jw ) = X( jw )H( jw )
t

1 (31.6)
x(t )dt X( jw ) + pX(0)d (w )
FT

jw H(jw) can be expressed as
8. Duality: If H( jw ) = H( jw ) e jq H (w ) (31.7)
x(t) X( jw )
FT where, H( jw ) is the magnitude response of the system,
qH(w) is the phase response of the system. The magni-
then we have tude of the output signal is given by
X( jt) 2p x( w )
FT
Y ( jw ) = X( jw ) H( jw ) (31.8)

Table 31.2| Properties of continuous-time Fourier transform.
Property Aperiodic Signal Fourier Transform
x(t) X(jw )
y(t) Y (jw )
Linearity ax(t) + by(t) aX(jw ) + bY (jw )
Time shifting x(t t0 ) ejw t0 X(jw )
Frequency shifting e jw 0 tx(t) X(j(w w 0 )
Conjugation x*(t) X *(jw )
Time reversal x(t) X(jw )
1 jw
Time and frequency x(at) X
scaling a a
Convolution x(t)*y(t) X(jw)Y(jw)
1
Multiplication x(t)y(t) X(jw ) * Y (jw )
2p
d
Differentiation in x(t) jwX(jw )
time dt
1
t
Integration x(t)dt jw X(jw ) + pX(0)d (w )

d
j X(jw )
dw
Differentiation in tx(t)
frequency
X(jw ) = X *(jw )
Re{X(jw )} = Re{X(jw )}
Conjugate
symmetry for real x(t) real Im{X(jw )} = Im{X(jw )}
signals X(jw ) = X( jw )

X(jw ) = X(jw )
Symmetry for real x(t) real and even X(jw ) real and even
and even signals
Symmetry for real x(t) real and odd X(jw ) purely imaginary and odd
and odd signals
Even-odd xe (t) = Ev{x(t)} [x(t) real] Re {X(jw )}

x (t) = Od{x(t)}
decomposition for o [x(t) real] j Im {X(jw )}
real signals
+ +

1
X( jw ) dw
2 2
Parsevals relation x(t) dt =
for aperiodic signals
2

31.4 DISCRETE-TIME FOURIER TRANSFORM 733
The phase of the output signal is given by where w = 2p/N. The inverse of discrete-time Fourier
transform is given by
q y (w ) = q x (w ) + q H (w ) (31.9)
jw
X(e )e jwn dw
1
x[n ] = (31.16)
For a non-periodic signal x(t), we have 2p 2p
+
H( jw )X( jw )e jwt dw
1 It may be mentioned here that the discrete-time Fourier
y(t) = (31.10) transform of signal x[-n]is given by
2p
x[n ] X(ejw )
FT
For a distortionless transmission through an LTI system, (31.17)
the output should have the shape of the input signal.
However, the output can have different amplitude and Table 31.3 enlists the discrete-time Fourier transform of
may be delayed in time with respect to the input signal. the commonly used signals.
Therefore, for a distortionless LTI system, we have
Table 31.3| Discrete-time Fourier transform pairs.
y(t) = Kx(t td ) (31.11)
Signal Fourier Transform
where K is the gain of the LTI system and td is the time
+
2p k
delay. Also, +
ak e jk(2n/N )n 2p akd w
N

H( jw ) = k and q H (w ) = jw td k= N k =
31.3.1 LTI Systems Characterized in Differential e jw 0 n 2p d (w w 0 2p l)

l=
Equations
+
cos w 0 n p {d (w w 0 2p l)
Continuous-time LTI systems can be expressed by linear
constant-coefficient differential equation of the form l=
+ d (w + w 0 2p l)}
dy(t) d 2 y(t) d N y(t)
a0 y(t) + a1 + a2 + + aN
dt2 dtN +
p
dt
dx(t) 2
d x(t) d x(t) M sin w 0 n {d (w w 0 2p l)
= b0 x(t) + b1 + b2 2
+ + bM (31.12) j l =
dt dt dtM d (w + w 0 2p l)}
N
dk y(t) M
dk x(t) +
or ak
dt k
= bk
dtk
(31.13) x[n] - 1 2p d (w 2p l)
k =0 k =0 l=
where M N . The transfer function H(jw) in this case +

2p k
is expressed as Periodic square wave 2p akd w
N

k =
1, n N1

M
bk (jw ) k
x[n ] = N
H( jw ) = 0, N1 < n

k =0
N
(31.14) 2
ak (jw ) k
and
k =0 x[n + N ] = x[n ]
+ +
2p 2p k
31.4 DISCRETE-TIME FOURIER d(n kN ) d w
N

TRANSFORM k = N k =
a n u [n ] , a <1
1
Discrete-time Fourier transform X(ejw) of a signal x[n] 1 aejw
is given by
1, n < N1 sin[w (N1 + (1/2))]
+ + x[n ] =
0, n < N1 sin(w /2)
X(e jw ) = x[n ]ejw n = x[n ]ej2p n / N (31.15)
n = n =
(Continued)

Table 31.3| Continued 3. Time shifting: If

x[n ] X(e jw )
FT
Signal Fourier Transform
Wn 1, 0 w W then we have
X(e jw ) =
sin Wn W
sinc
p
=
pn p 0, W < w p x[n n0 ] ejw n0 X(e jw )
FT
0<W <p
X(ejw) periodic with 4. Frequency shifting: If
period 2p
x[n ] X(e jw )
FT
[n ] 1
then we have
+
e jw 0 n x[n ] X(e j(w w 0 ) )
1
pd (w 2p k)
FT
u[n] jw
+
1 e k =
5. Conjugation and conjugate symmetry: If
d(n n0 ) ejwn0
x[n ] X(e jw )
FT
1
(n + 1)an u[n ], a <1 then we have
(1 aejw )2
x*[n ] X *(ejw )
FT
(n + r 1)! n 1 When x[n] is real, then we get the following:

a u[n ],
n !(r 1)! (1 aejw )r
i. X(ejw) = X*(ejw)
a <1
ii. Even part of x[n ] Re{X(e jw )}
FT
iii. Odd part of x[n ] j Im{X(e jw )}

FT
For a periodic signal x[n] with Fourier series representation
jkn (2p N )
6. Differencing: If
x[n ] = ak e
x[n ] X(e jw )
FT
k= N
the Fourier transform is given by then we have

+
2p k x[n ] x[n 1] (1 ejw )X(e jw )
X(e jw ) =
FT
2p akd w (31.18)
k =
N
7. Accumulation: If
x[n ] X(e jw )
FT
31.5 PROPERTIES OF DISCRETE-
TIME FOURIER TRANSFORM then we have
n
X(e jw )
1
x[m]
FT
jw
Discrete-time Fourier transform has the following
m = (1 e )
+
properties:
1. Periodicity: The discrete-time Fourier transform + p X(e j 0 ) d (w 2pk)
is periodic in w with period of 2w whereas the con- k =
tinuous-time Fourier transform is non-periodic.
8. Time expansion or time scaling: If
X(e j(w + 2p ) ) = X(e jw )
x[n ] X(e jw )
FT
and
x[n/k ]
2. Linearity: If
if n is a multiple of k
jw jw
x k [n ] =
x1[n ] X1(e ) and x2 [n ] X2 (e 0
FT FT if n is not a multiple of k
)
then we have then we have
jw jw
ax1[n ] + bx2 [n ] aX1(e x k [n ] X(e jkw )
FT FT
) + bX2 (e )

31.5PROPERTIES OF DISCRETE-TIME FOURIER TRANSFORM 735
9. Convolution: If 11. Differentiation in frequency domain: If

jw jw
x1[n ] X1(e ), x2 [n ] X2 (e x[n ] X(e jw )
FT FT FT
)
and y[n ] Y (e jw )
FT then we have
dX(e jw )
nx[n ] j
FT
then we have
dw
y[n ] = x1[n ] * x2 [n ] Y (e jw )
FT
12. Parsevals relation:
= X1(e jw )X2 (e jw ) +
X(e jw ) dw
2 1 2
x[n ] =
10. Multiplication in time-domain: If n = 2p 2p
x1[n ] X1(e jw ), x2 [n ] X2 (e jw )
FT FT The total energy in the signal x[n] can be deter-
mined by integrating the energy per unit frequency
and y[n ] Y (e jw )
FT
[|X(e jw )|2/2p ] over a full 2p interval of distinct dis-
jw 2
then we have crete-time frequencies. The term |X(e )| is also
y[n ] = x1[n ]x2 [n ] Y (e jw )
FT referred to as the energy-density spectrum of the
signal x[n].
jq
X1(e )X2 (e j(w q ) )dq
1
= Table 31.4 lists the properties discussed in the list
2p 2p above for easy reference.
Table 31.4| Properties of discrete-time Fourier transform.
x[n ] X(e jw ) Periodic with

y[n ] Y (e jw ) period 2p
Linearity ax[n ] + by[n ] aX(e jw ) + bY (e jw )
Time shifting x[n n0 ] ejwn0 X(e jw )
Frequency shifting e jw 0 n x[n ] X(e j(w w 0 ) )
Conjugation x*[n ] X *(ejw )
Time reversal x[ n ] X(ejw )
x[n/k ], if n = multiple of k
Time expansion x k [n ] = X(e jkw )
0, if n multiple of k
Convolution x[n ]*y[n ] X(e jw )Y(e jw )
jw
X (e )Y (e j(w q ) )dq
1
Multiplication x[n ] y[n ]
2p 2p
Differencing in time x[n ] x[n 1] (1 ejw )X(e jw )
(Continued)


n +
X(e jw ) + pX(e jq )
1
Accumulation x[k ] d (w 2pk)
k = 1 ejw k =
Differentiation in nx[n] dX(e jw )

j
frequency dw
Conjugate x[n] real X(e jw ) = X * (ejw )

jw jw
symmetry for real Re{X(e )} = Re{X(e )}
jw jw
{ } { )}
signals
Im X ( e ) = Im X ( e
jw jw

X (e ) = X (e )
X(e ) = X(e jw )
w

j
Symmetry for real x[n] real and even X(e jw ) real and even
and even signals
Symmetry for real x[n] real and odd X(e jw ) purely imaginary and odd
and odd signals
Even-odd xe [n ] = Ev{x[n ]} [x[n ] real ] { }

Re X(e jw )
j Im {X(e )}
decomposition of jw
real signals xo [n ] = Od{x[n ]} [x[n ] real ]
+
X(e jw ) dw
2 1 2
Parsevals relation x[n ] =
for aperiodic signals n = 2p 2p
31.6 FREQUENCY RESPONSE OF

DISCRETE-TIME LTI SYSTEMS
y[n ] = ck H(e jw 0 )e jkw 0 n (31.21)
k= N
If x[n] is non-periodic, then

Let x[n], h[n] and y[n] be the input, impulse response and
H(e jw )X(e jw )e jwn dw
1
the output of the discrete-time LTI system. y[n ] = (31.22)
2p
Then y[n ] = x[n ] h[n ] (31.19)
31.6.1 LTI Systems Characterized in Difference
Also Equations
Y (e jw ) = X(e jw )H(e jw ) (31.20) Discrete-time LTI systems are characterized by linear

constant-coefficient difference equations given by
If x[n] is a periodic signal with the Fourier series a0 y[n ] + a1y[n 1] + a2 y[n 2] + + aN y[n N ]
= b0 x[n ] + b1x[n 1] + b2 x[n 2] + + bM x[n M ]
representation
x[n ] = ck e jkw 0 n
N M
(31.23)
k= N
or ak y[n k ] = bk y[n k]
where w 0 = 2p /N, then the output y[n] of the discrete-
k =0 k =0
time LTI system is given by where M N . The transfer function is given by

31.7 DISCRETE FOURIER TRANSFORM (DFT) AND FAST FOURIER TRANSFORM (FFT) 737
M Equation (31.28) can be expressed as

bk ejkw X = Wx (31.29)
H(e jw ) = k =0
N
(31.24) where
ak ejkw X[ 0 ]
X[1]
k =0

X = X[ 2 ]
31.7 DISCRETE FOURIER

TRANSFORM (DFT) AND FAST X[n 1]
FOURIER TRANSFORM (FFT)
1 1 1 1 1
1 W 1 2
WN3
WNN 1
N WN
2(N 1)
Discrete Fourier transforms (DFTs) are defined for finite W = 1 WN2 WN4 WN6 WN

length sequences. For the finite duration causal signal

1 W N 1 W 2(N 1) W 3(N 1) (N 1)(N 1)
x[n], the DFT is given by
N N N WN
N 1
X(k) = X(e jw ) = x[n]e(j2pk/N )n (31.25) x[0 ]
x[1]

n =0
where k = 0, 1, 2, ..., N -1 and x[n] is a finite length x = x[2]

sequence of length N. Substituting WN = ej2p /N in Eq. x[N 1]
(31.25), we get
N 1 From the matrix representation of Eq. (31.29), the com-
X(k) = x[n ]WN kn (31.26) putation complexity of the DFT is of the order of O(N2)
n=0 as it involves N2 complex multiplications and N(N - 1)
complex additions.
Here, WN for n = 0, 1, 2 ..., N - 1 are referred to as Nth
k
k Fast Fourier transform (FFT) is an efficient method
roots of unity as in complex arithmetic (WN )N = 1
for all k. The DFT coefficient X(k) represents both the for computing the DFT. The FFT algorithms reduce the
sample of Fourier transform at w = 2pk/N and sample time involved in finding a DFT from several minutes to
of z-transform on the unit circle. The inverse discrete less than a second. Using FFT algorithms the complex-
Fourier transform (IDFT) is given by ity of calculating the transform reduces to O(Nlog2N)
operations. The FFT can be calculated using the follow-
N 1
X[k] WN kn
1 ing steps (Cooley-Tukey FFT algorithm).
x[n ] = (31.27)
N k =0 1. Divide the N-point DFT into two N/2-point DFTs
operating on the even and odd samples:
where n = 0, 1, 2, ..., N-1. The DFT and IDFT pairs
N 1
x[n]WN kn
can be represented in matrix form as
X(k) = (N-point DFT)
X[ 0 ]
n =0
(N /2)1 (N /2)1
X[1]
X[ 2 ] X(k) = x1[n ] WN kn + WN k x2 [n ] WN kn
n =0 n =0

2 2

X[n 1]
k
= Y (k) + WN Z(k)
1 1 1 1 1 (Two N/2-point DFTs)

1 W 1 WN2 WN3 WNN 1
N where x1[n] and x2[n] are even and odd samples of
2(N 1)
= 1 WN2 WN4 WN6 WN x[n], respectively, and Y(k) and Z(k) are two N/2-

point DFTs operating on even and odd samples,

1 W N 1 W 2(N 1) W 3(N 1) (N 1)(N 1) respectively.
N N N WN 2. The transform can be simplified further using
x[0 ] k+ N
x[1] the periodicity WN 2 = WN k and symmetry

x[2] 2 2
k+ N
x[N 1] WN 2 = WN properties.
k
(31.28)

y[0]
x[0] X[0] = y[0]+W0z[0]
y[1]
x[2] X[1] = y[1]+W1z[1]
N/2 point y[2]
x[4]
DFT
y[N/22]
x[N2]
z[0]
x[1] X[N/2] = y[0]W0z[0]
z[1] W0 1
x[3] X[N/2+1] = y[1]W1z[1]
N/2 point z[2] W1 1
x[5]
DFT
z[N/21]
x[N1]
Figure 31.1| First decimation in time FFT.
3. Using these properties, we get In Fig. 31.2, y0 = x0 + x1 and y1 = x0 - x1.

A butterfly is a portion of the computation that
N
X k + combines the results of
2
(N /2)1 (N /2)1
= x1[n ] WN kn WN
k
x2 [n ] WN kn x0 y0
n =0 2 n =0 2
= Y (k) WN Z(k)
k
x1 y1
Therefore, one needs to calculate Y(k) and Z(k) 1
only and they can be used to calculate both X(k) Figure 31.2| Butterfly structure for computing
and X(k + (N/2)). Subsequently, the number of FFT.
calculations reduced from 0 to (N - 1) to 0 to
[(N/2) - 1]. smaller DFTs into a larger DFT or vice versa (breaking
4. Y(k) and Z(k) can be further divided into N/4- a larger DFT up into sub-transforms). A decimation-in-
point DFTs using the process mentioned above. time FFT algorithm on n = 2p inputs with respect
to a primitive nth root of unity W = e2pi/n relies on
5. The process continues till two-point DFTs are O(nlogn) butterflies as given below.
obtained.
y0 = x0 + x1W k
6. Figure 31.1 illustrates the first decimation in time
FFT. y1 = x0 x1W k
7. Figure 31.2 shows the inputs and outputs of a but- where k is an integer depending on the part of the
terfly structure used for calculating FFT. transform being computed.
IMPORTANT FORMULAS
1. The continuous-time Fourier transform X(jw) of a 3. The transfer function H(jw) of a continuous-time
signal x(t) is LTI system
M
X( jw ) = x(t)ejwt dt bk (jw )k

H( jw ) = k =0
N
2. The inverse Fourier transform of X(jw) is

ak (jw )k
X( jw )e jwt dw
1 k =0
x(t) =
2p 4. Formulas given in Tables 31.1 and 31.2.

SOLVED EXAMPLES 739
5. Discrete-time Fourier transform X(ejw) of a signal M

x[n] is
+
bk ejkw
X(e jw ) = x[n ]ejwn H(e jw ) = k =0
N
n =
ak ejkw
k =0
6. The inverse of discrete-time Fourier transform
8. Formulas given in Tables 31.3 and 31.4.
jw
X(e )e jwn dw
1
x[n ] =
2p 2p
9. DFT of a sequence x[n]
N 1
x[n] WN kn
7. The transfer function of a discrete-time LTI system
X(k) =
is given by n =0
SOLVED EXAMPLES
1. If X(jf) represents the Fourier transform of a real 3. Consider an LTI system with impulse response
and odd symmetric signal x(t), then h(t) = e-tu(t). An input signal e-tu(t) is applied to
the system. The output y(t) is given by
(a) X(jf) is complex
(b) X(jf) is imaginary (a) e-tu(t) (b) te-tu(t)
(c) X(jf) is real (c) u(t) (d) e-2tu(t)
(d) X(jf) is real and non-negative
Solution. The Fourier transform of the given
impulse response h(t) = e-tu(t) is
Solution. Fourier transform of real and odd symmet-
ric signal is imaginary and odd function of frequency.
1
H( jw ) =
Ans. (b)
2. The Fourier transform of a signal x(t) = e , m t 1 + jw
m > 0 is
The Fourier transform of the given input signal
x(t) = e-tu(t) is
2m m
(a) 2 (b) 2
w +m 2
w + m2
2w w X( jw ) =
1
(c) 2 (d) 2 1 + jw
w +m 2
w + m2
Solution. The continuous-time Fourier transform If y(t) is the output signal and Y(jw) is its Fourier
X(jw) of a signal x(t) is transform, then

1
2
jw t
X( jw ) = x(t)e dt Y ( jw ) = H( jw ) X( jw ) =
1 + jw

Therefore, the Fourier transform of the given func- Taking inverse Fourier transform, we get
tion is
y(t) = te-tu(t)
m t jw t
X( jw ) = e e dt Ans. (b)

4. The 3-dB bandwidth of a typical second-order
0
mt jw t mt jw t
dt + e
system with the transfer function
= e e e dt
0 w n2
H(s) =
0 s2 + 2z w n s + w n2
= e(m jw )t dt + e(m+ jw )t dt
0 is given by
1 1 2m
= + = 2 (a) w n 1 2z 2
m jw m + jw m + w2
Ans. (a) (b) w n (1 z 2 ) + z 4 z 2 + 1

Therefore,
(c) w n (1 2z 2 ) + 4z 4 4z 2 + 2
D = (1 2z 2 ) 4z 4 4z 2 + 2
(d) w n (1 z ) 4z 4z + 2
2 2 2
The value of D at the 3 dB frequency wc is given by

Solution. The given transfer function is
wc
w n2 D=
H(s) = wn
s2 + 2zw n s + w n2
wc
Substituting s = jw in the above equation, we get Therefore, = (1 2z 2 ) 4z 4 4z 2 + 2
wn
w n2
H( jw ) = or w c = w n (1 2z 2 ) 4z 4 4z 2 + 2
( jw )2 + 2zw n ( jw ) + w n2
w n2 Since w c cannot be negative, we get
=
w n2 2
w + 2 jzw nw
w c = w n (1 2z 2 ) + 4z 4 4z 2 + 2
1 Ans. (c)
=
1 (w 2 /w n2 ) + j (2zw /w n )
5. A rectangular pulse of duration T is applied to
a filter matched to this input. The output of the
Let us consider that filter is a
w (a) rectangular pulse of duration T
D=
wn (b) rectangular pulse of duration 2T
Therefore, (c) triangular pulse of duration 2T
(d) triangular pulse of duration T
1
H( jw ) = and
(1 D ) + j2zD
2 Solution. Following figure shows the input signal
x(t):
1
H( jw ) =
(1 D ) + (2zD)2
2 2 x(t)
We know that at 3 dB frequency wc,

1
1
H( jw c ) =
2 t
Therefore, 0 T
1 1 For the matched filter,
=
2 (1 D ) + (2zD)
2 2 2
h(t) = x(T t)
Therefore,
The following figure shows the impulse response:
(1 D2 )2 + (2z D)2 = 2
Hence, h(t) = x(T t)
1 + D 2D + 4z D = 2
4 2 2 2
or
D 4 + D2 (4z 2 2) 1 = 0
1
Therefore, t
0 T
(4z 2) (4z 2) 4(1)(1)
2 2 2
D2 =
2 Also
= (1 2z ) 4z 4z + 2
2 4 2
y(t) = x(t) * h(t)

The following figure shows the waveform of output

Solution. If x(t) X(f )
FT
y(t).
then x(t 2) ej2p 2f X(f ) = X(f )ej(4pf )
FT
y(t)
Ans. (a)
7. Based on the data given in Question 6 the Fourier
transform of x(t/2) is
(a) X(f )ei (4pf )
t
0 T 2T (b) X(2f )
y(t) is a triangular pulse of duration 2T. (c) 2X(2f ) (d) X(f 2)
Ans. (c)
6. If the Fourier transform of a deterministic signal
Solution. If x(t) X(f )
FT
x(t) is X(f), then the Fourier transform of x(t 2) is
(a) X(f )ei (4pf ) f
then x
(b) X(2f ) t 1

FT
1/2 1/2
X = 2X(2f )
(c) 2X(2f ) (d) X(f 2) 2
Ans. (c)
1. What is the value of the Fourier transform of a 2. Find the fundamental period of the discrete-time
unit impulse function? signal x[n] = (-1)n.
Solution. Continuous-time Fourier transform Solution. The signal x[n] is shown in the follow-
X(jw) of a signal x(t) is ing figure. From the figure, we can infer that the
fundamental period of the signal is 2.
X( jw ) = x(t)ejwt dt
x[n]
The unit impulse function is given by
t = 0 + 1 1 1 1 1
d (t) =
0 t0 d (t)dt = 1

4 1
Therefore, the Fourier transform of a unit impulse n
3 2 0 1 2 3 4
function is

X( jw ) = d (t)ejwt dt = 1 1 1 1 1

Ans. (1) Ans. (2)
PRACTICE EXERCISE
1. The Fourier transform of the exponential signal ejw0t is 3. Let X(jw) be the Fourier transform of a signal x(t).
The plot of X( jw ) as a function of w reveals
2
(a) a constant (b) a rectangular gate
(c) an impulse (d) exponential signal (a) h
ow the power of the signal is distributed as a
(1 Mark) function of frequency
2. The inverse Fourier transform of u(w) is (b) how the energy of the signal is distributed as a
1 j function of frequency
(a) d(t) (b) d (t) +
pt
(c) how the amplitude of the signal is distributed
2
as a function of frequency
1 j (d) None of these
(c) u(t) (d) u(t) +
2 pt (1 Mark)
(2 Marks)

4. Select the best option for the following statement: sin 2Wt cos Wt
Given that x(t) is a periodic signal whose average (a) 2W (b) W
2Wt Wt
value over one period is zero.
cos 2Wt sin Wt
(a) In frequency domain, the energy is concentrated (c) 2W (d) W
Wt Wt
at discrete frequencies equal to the fundamen-
(2 Marks)
tal frequency and all of its harmonics.
(b) In frequency domain, the energy is distributed 8. The following figure shows the amplitude and
uniformly across all frequencies. phase spectrum of a signal g(t) in the frequency
(c) In frequency domain, the energy is concen- domain. Then g(t) is
trated at w = 0.
(d) In frequency domain, the energy is concen- G(w)
trated at the fundamental frequency.
(1 Mark)
p
5. Given a Fourier transform pair
w
p t t 4p cos w W 0 W
x(t)= cos rect X(=) = 2
FT
.
2 2 p 4w 2
4p cos t qg(w)
The Fourier transform of y(t) = 2 is
p 4t 2
p/2
pw w w
(a) cos rect
2 2 p/2
pw w
(b) p cos rect
2 2
(2 sin 2Wt) (1 cos Wt)
pw w (a) 2W (b) W
(c) 2p cos rect
2
2Wt Wt
2
(2 cos 2Wt) (1 sin Wt)
pw w
(c) 2W (d) W
(d) 4 cos rect
4
2Wt Wt
4 (2 Marks)
(2 Marks)
9. The Fourier transform of a voltage signal x(t) is
6. The amplitude spectrum of a Gaussian pulse is X(jf). The unit of X( jf ) is
(a) uniform (b) a sine function
(c) Gaussian (d) an impulse function (a) Volt (b) Volt-s
(1 Mark) (c) Volt/s (d) Volt2
(2 Marks)
7. The following figure shows the amplitude and
phase spectrum of a signal f(t) in the frequency 10. A signal x(t) has a Fourier transform X( jw ). If x(t)
domain. Then, f(t) is is a real and odd function of t, then X( jw ) is
(a) a real and even function of w
F(w) (b) an imaginary and odd function of w
(c) an imaginary and even function of w
(d) a real and odd function of w
p (1 Mark)
w 11. A seven-point sequence x[n] is given as x [3] = 1,

W 0 W x [2] = 0, x [1] = 3, x [0 ] = 5, x [1] = 1, x[2] = 7,
x[3] = 4. The DFT of x[n] is
qf(w)
(a) 4e3 jw + 7 e2 jw + e jw + 5 + 3ejw e3 jw
(b) e3 jw + 3e jw + 5 + ejw + 7 e2 jw + 4e3 jw

w
(c) Cannot be determined from the given data
(d) None of these
(2 Marks)

12. The FT of the signal is (u[n - 3] - u[n - 7]) is 14. An LTI system has an impulse response h[n] and
frequency response H(ejw). When the system is fed
(a) e3 jw + e4 jw + e5 jw + e6 jw with an input cos w0n (-w w0 w), its output
(b) e3 jw e7 jw isw0cosw0n. What is the frequency response of the
(c) 0 system?
(d) None of these (a) 1 (b) cosw0n
(2 Marks) (c) w (d) w
13. DFT of a signal is cos2w + sin22w. The signal (2 Marks)
corresponding to the DFT is 15. For the data given for the LTI system in Question
(a) u[n] 14, what is the impulse response of the system?
(b) d[n ]
1 cos np 1 1 sin np 1
p p
(a) (b)

1 1 1
(c) d [n ] + d [n 2] + d [n + 2] d [n 4] n2 n2
4 4 4
1
d [n + 4] (c) 1 (d)
1
4 p
1 1 1
(d) 4d [n ] + d [n 2] + d [n + 2] d [n 4] (2 Marks)
4 4 4
1
d [n + 4]
4
(2 Marks)

1
n
1. Let x[n ] = u[n ], y[n ] = x3 [n ] and Y (e jw ) be 3. The Fourier transform of the signal x(t) = e3t is
2
3
of the form AeBf , where A and B are constants.
m
the Fourier transform of y[n]. Y (e j 0 ) is given by

Find the value of m.
a/b. Find the value of a.
(1 Mark)
(2 Marks)
4. For a linear phase channel, with phase delay tp of
2. For the data given in Question 1, find the value
5, what is the group delay tg ?
of b.
(1 Mark) (2 Marks)
ince the signal contains only one frequency w0,

1. (c) S 5. (c) From duality property, we get
its Fourier transform is an impulse at w0. Y (w ) = 2pX(w )
p (w ) w
2. (b) If x(t) = u(t) and x(t) X(w ) then = 2p cos rect
2 2
FT
X(w ) =
1
+ pd (w ). From duality property, pw w
= 2p cos
2
rect
jw 2
X(t) 2p x(w ) 6. (c) A normalized Gaussian pulse is defined as

x(t) = ept
2
Therefore,
The Fourier transform of a Gaussian pulse is given by
1 j
u(w ) = d (t) + x(t) = ep t X(f ) = epf
2
FT 2
2 pt
Therefore, the amplitude spectrum of a Gaussian
pulse is also Gaussian, that is, X(f ) = epf is also
3. (b) 2
4. (a) a Gaussian pulse in frequency domain.

7. (d) We have 12. (a) We have

u[n 3] u[n 7 ]
f (t) = F 1[F ( jw )]
+
= d [ n 3] + d [ n 4] + d [ n 5] + d [ n 6 ]
F ( jw )e jw t dw = e3 jw + e4 jw + e5 jw + e6 jw
1
=
2p
+W 13. (c) It is given that
p e jw t dw
1
X(e jw ) = cos2 w + sin2 2w
=
2p W
=W
sin Wt (1 + cos 2w ) (1 cos 4w )
Wt = +
2 2
8. (b) We have
1
= 1 + e2 jw + e2 jw e4 jw + e4 jw
1 1 1
f (t) = F 1[F ( jw )] 4 4 4 4
+
F ( jw )e jw t dw
1
=
2p
Therefore,
1 1
0 W x[n ] = d [n ] + d [n 2] + d [n + 2]
jp /2 jw t jp / 2 jw t
pe e dw + 2p pe
1 1
= e dw 4 4
2p 1 1
W 0 d [n 4] d [n + 4]
(1 cos Wt) 4 4
=W
Wt 14. (c) Whenever the system is fed with a complex
exponential of frequency w0, its output is the same
9. (b) By definition, the Fourier transform is complex exponential scaled by the same frequency

w0. Therefore, the frequency response of the system is
X( jw ) = x(t)ejwt dt
H(e jw ) = w , p w p
The unit of Fourier transform of any signal is the
unit of the signal multiplied by unit of time, that is, 15. (a) The impulse response h[n] is obtained by taking
seconds(s). We know that unit of voltage is volts; the inverse Fourier transform of the frequency
therefore, the unit of Fourier transform of voltage response. Therefore,
signal is volt-s.
p
H(e jw )e jwn dw
10. (b) 1
h[n ] =
2p p
11. (b) The DFT of x[n] is given by
+ 0 p
x[n ]ejw n w e jw n dw +
2p 0
w e jw n dw
1 1
X( jw ) = =
n =
2p p
Substituting the different values of n in the above

equation, we get the DFT of x[n] as
e3 jw + 3e jw + 5 + ejw + 7 e2 jw + 4e3 jw 1 cos np 1
p
h[n ] =
n2
1
3n
y[n ] = u3 [n ]
Numerical Answer Questions 3
1 3
n
1
1. Given that n
= u[n ] = u[n ]
1 3 27
n
x[n ] = u[n ] and y[n ] = x3 [n ].
3
Therefore, Taking z-transform, we get
1 Y (z ) =
3n 1
y[n ] = u3 [n ]
3 1 (1/27)z1
1 3
n
1
n
= u[n ] = u[n ]
3 27

Substituting z = e jw in the above equation, we get The phase delay tp is given by
Y (e jw ) =
1 q (w )
1 (1/27)ejw
tp =
w
Substituting w = 0 in the above equation, we get Therefore,
1 27 tp = t0
Y (e j 0 ) = =
1 (1/27) 26
The group delay tg is given by
Therefore, a = 27
Ans. (27)
dq (w )
tg =
2. Referring to the Solution of Question 1, we get dw
b = 26.
Ans. (26) Therefore,
3. The signal x(t) is a normalized Gaussian function. tg = t0
As we know, the normalized Gaussian functions
have Gaussian Fourier transform. Therefore, the Hence,
Fourier transform of the given signal is of the form tp = tg = t0 = constant
-Bf2
Ae . Therefore, m = 2
Ans. (2)
Given thattg = 5,
4. For a linear phase channel, the phase q(w) is given by
therefore tp = 5
q (w ) = w t0 Ans. (5)
1. Let x(t) be the input to a linear, time-invariant 2. Let H(f) denote the frequency response of the
system. The required output is 4x(t 2). The RC-LPF. Let f1 be the highest frequency such that
transfer function of the system should be H (f1 )
j 4pf j 8pf 0 f f1 ; 0.95. Then f1 (in Hz) is
(a) 4 e (b) 2 e H (0 )
(a) 327.8 (b) 163.9
(c) 4 ej 4pf (d) 2 e j 8pf (c) 52.2 (d) 104.4
(GATE 2003: 1 Mark) (GATE 2003: 2 Marks)
Solution. It is given that Solution. The circuit of an RC-LPF is shown in

y(t) = 4x(t 2) the following figure.
R
Therefore,
Y (s) = 4e2s X(s)
C
Hence,
= 4e2s
Y (s)
H(s) =
X(s) The transfer function of the filter is
H( jf ) = 4e2 j2pf = 4ej 4pf H(f ) =
1
Ans. (c) 1 + j2pfRC
Data for Questions 2 and 3: The system under Also, for a RC-LPF,
consideration is an RC low-pass filter (RC-LPF) with
R = 1.0 k and C = 1.0 F. H(0) = 1.

We need to find maximum value of f1 such that 5. A rectangular pulse train s(t) as shown in the
following figure is convolved with the signal
H(f1 )
=
1
0.95 cos2 (4p 103 t). The convolved signal will be a
H(0) 1 + 4p 2f12R 2C 2
s(t)
Therefore,
1
1.108 1 + 4p 2f12 (RC )2
Substituting the value of R and C, we get

0.329
f1 52.2 Hz t
2p 103 0
0.1ms
Therefore, (a) DC (b) 12 kHz sinusoid
f1max = 52.2 Hz (c) 8 kHz sinusoid (d) 14 kHz sinusoid
3. Let tg (f ) be the group delay function of the given Solution. The time period T0 of the given wave-
RC-LPF and f2 = 100 Hz. Then tg (f2 ), in ms, is form is
(a) 0.717 (b) 7.17 T0 = 0.1 103 = 104 s
(c) 71.7 (d) 4.505
(GATE 2003: 2 Marks) Therefore, the fundamental frequency is
Solution. The transfer function of a RC-LPF is 1
f0 = = 104 = 10 kHz
T0
1
H(w ) =
1 + jwRC Its Fourier transform comprises of only the odd
harmonics of the fundamental frequency as shown
and the phase response is in the following figure.
q (w ) = tan1 RCw
Group delay tg of an RC-LPF is given by

RC
tg =
1 + (2pRCf )2
0 10 kHz 30 kHz
Therefore,
The signal cos2 (4p 103 t) has frequency 4 kHz. Its
103 Fourier transform representation is shown in the
tg = = 0.717 ms
1 + 106 4p 2 104 following figure.
Ans. (a)
4. The Fourier transform of a conjugate symmetric
function is always
(a) imaginary (b) conjugate antisymmetric
(c) real (d) conjugate symmetric
(GATE 2004: 1 Mark) 4 kHz 0 4 kHz
Solution. The Fourier transform of a conjugate Therefore, after convolution, we have a signal at
symmetric function is real. f = 0 with constant amplitude in the time-domain.
Ans. (c) Ans. (a)

6. Let x(t) and y(t) [with Fourier transforms X(f) 8. For a signal x(t) the Fourier transform is X(f). Then
and Y(f), respectively] be related as shown in the the inverse Fourier transform of X(3f + 2) is given by
following figure. Then Y(f) is 1 t j3pt 1 t j 4p t /3
(a) x e (b) x e
x(t) 2 2 3 3
1 y(t) (c) 3x(3t)ej 4p t(d) x(3t + 2)
2 1 0 Solution. Applying frequency scaling and fre-
t t
2
quency shifting properties, we get
0 2
2
X[3f + 2] = X 3 f +
1 3
1 t
x ej 4p t /3
FT
1 f 1 f 3 3
(a) X ej2pf (b) X e j2pf
2 2 2 2
Ans. (b)
f f
(c) X e j2pf (d) X ej2pf 9. The output y(t) of a linear time invariant system is
2 2 related to its input x(t) by the following equation:
y(t) = 0.5x(t td + T ) + x(t td ) + 0.5x(t td T ).
The filter transfer function H(w ) of such a system

Solution. From the given figures, we can write as
y(t) = x [2(t + 1)] is given by
Using the time shifting and time scaling properties (a) (1 + cos w T )ejwtd (b) (1 + 0.5 cos w T )ejw td
x(t t0 ) X(f )ej2pft0 (c) (1 cos w T )ejw td (d) (1 0.5 cos w T )ejw td
1 f (GATE 2005: 2 Marks)
and x(at) = X
a a Solution. Given that
where t0 = -1 and a = -2, we get
y(t) = 0.5x(t td + T ) + 0.5x(t td T ) + x(t td )
1 f
Y (f ) = X e j2pf
2 2
Taking the Fourier transform, we get
Ans. (b) Y ( jw ) = 0.5e jw (td + T ) + 0.5e jw (td T ) + ejwtd X( jw )

7. Match the items in Group 1 with those in Group 2
and choose the correct combination. The filter transfer function is
Y ( jw )
H( jw ) =
Group 1 Group 2 X( jw )
= ejw td 0.5e jw T + 0.5ejw T + 1
E.Continuous and 1.Fourier representation is
aperiodic signal continuous and aperiodic
F.Continuous and 2.Fourier representation is = (1 + cos w T )ejw td
periodic signal discrete and aperiodic Ans. (a)
G.Discrete and 3.Fourier representation is
aperiodic signal continuous and periodic 10. Let x(t) X( jw ) be Fourier transform pair. The
Fourier transform of the signal x(5t 3) in terms of
X( jw ) is given as
H.Discrete and 4.Fourier representation is
periodic signal discrete and periodic
1 ( j3w /5) jw jw
(b) e( j3w /5)X
1
X 5
(a) e
(a) E-3, F-2, G-4, H-1 (b) E-1, F-3, G-2, H-4 5 5 5
(c) E-1, F-2, G-3, H-4 (d) E-2, F-1, G-4, H-3
1 j3w jw jw
(d) e j3w X
(GATE 2005: 2 Marks) 1
X
5 5
(c) e
5 5
Solution. E-1, F-2, G-3, H-4
Ans. (c) (GATE 2006: 1 Mark)

Solution. Using time shifting and time scaling 13. The signal x(t) is described by
properties
x(t t0 ) X( jw )ejwt0 1 for 1 t +1
x(t) =
0 otherwise
1 jw
and x (at ) = X (here t0 = 3/5 and a = 5),
a a Two of the angular frequencies at which its Fourier
we get transform becomes zero are
j 3w
3 1 jw (a) p , 2p (b) 0.5p , 1.5p
x 5 t X e 5
5 5 5 (c) 0, p (d) 2p , 2.5p
Ans. (a) (GATE 2008: 2 Marks)
11. The 3-dB bandwidth of the low-pass signal et u(t),
where u(t) is the unit step function, is given by Solution. The Fourier transform of a signal x(t)
is given by
1 1
(a) Hz (b) 2 1 Hz
2p x(t)ejw t dt
2p
(c)
X( jw ) =
(d) 1 Hz
Therefore, the Fourier transform of the given signal
Solution. The Laplace transform of is
et u(t) = ejw t
1 1 1
ejwt dt =
1 jw
s+1 = (e ejw )
1
jw jw
The magnitude at 3-dB frequency is
1
; therefore, 1
2
X( jw ) = 0, when e jw ejw = 0. Therefore,
1 1 1
= =
2 s+1 1 + w2
Solving the above equation, we get w=1 rad.
e jw
1
Therefore, jw
=0
e
1
f= Hz 2 jw
2p Solving the above equation, we get e = 1.
Therefore, e = 1. Hence, w = p , 2p .
Ans. (a)
jw
12. A five-point sequence x[n] is given as x [3] = 1, x [2] = 1, x [1] = 0, x [0 ] = 5, x [1] = 1. Ans. (a)
x [3] = 1, x [2] = 1, x [1] = 0, x [0 ] = 5, x [1] = 1.
Let X(e jw ) denote the discrete-time Fourier trans- Linked Answer Questions 14 and 15: The
p impulse response h(t) of a linear time-invariant con-
form of x[n]. The value of X(e jw )dw is tinuous-time system is given by h(t) = exp(2t)u(t),
p where u(t) denotes the unit step function.
(a) 5 (b) 10p
(c) 16p (d) 5 + j10p 14. The frequency response H(w ) of this system in
(GATE 2007: 2 Marks) terms of angular frequency w, is given by H(w ) =
Solution. 1 sin (w )
(a) (b)
X(e jw
)=e 3 jw
+e 2 jw
+ 0+ 5+ e jw 1 + j2w w
Therefore, 1 jw
(c) (d)
p jw p 2 + jw
e3 jw e2 jw
2 + jw
X(e jw )dw =
e
+ + 5w +
p
3j 2j j (GATE 2008: 2 Marks)
p
= 5p + 5p Solution. It is given that the impulse response is
= 10p
Ans. (b) h(t) = exp(2t)u(t)

Y ( jw ) = 2p [ d (w 2) + d (w + 2)]
2 + jw
2p 2p
= d (w 2) + d (w + 2)
2 + j2 2 j2
2p
= [ (2 GATE
SOLVED
8
d (w 2)YEARS
j2)PREVIOUS + (2 +QUESTIONS ]
j2)d (w + 2)749
p
[ d (w 2) + d (w + 2)]
Therefore,
=
2
H( jw ) = h(t)ejwt dt
p
j
2
[ d (w 2) d (w + 2)]

= e2t ejwt dt cos 2t sin 2t
0
= +
2 2

= e(2 + jw )t dt 2 1 1
2 2
= cos 2t + sin 2t
0 2

e(2 + jw )t
1
cos (2t 0.25p )
1
= =
2 + jw 0
2
1 = 20.5 cos (2t 0.25p )

=
2 + jw Ans. (d)
Ans. (c) 16. [x(n)] is a real-valued periodic sequence with a
period N. x(n) and X(k) form N-point discrete
15. The output of this system, to the sinusoidal input Fourier transform (DFT) pairs. The DFT Y(k) of
1 N 1
x(t) = 2 cos (2t) for all time t, is
(a) 0 (b) 20.25 cos (2t 0.125p ) the sequence y(n) = x(r)x(n + r) is
N r =0
(c) 20.5 cos (2t 0.125p ) (d) 20.5 cos (2t 0.25p ) N 1
X(r)X * (k + r)
2 1
(GATE 2008: 2 Marks) (a) X(k) (b)
N r =0
N 1
X(r)X(k + r)
Solution. The given input signal is 1
(c) (d) 0
x(t) = 2 cos (2t) N r =0
whose Fourier transform is given by 2
Solution. X(k)
X( jw ) = 2p [d (w 2) + d (w + 2)] Ans. (a)
17. The four-point discrete Fourier transform (DFT) of
It is given that the transfer function is a discrete-time sequence {1, 0, 2, 3 is
1 (a) [0, 2 + 2 j, 2, 2 2]
H( jw ) =
2 + jw (b) [2, 2 + 2 j, 6, 2 2 j ]
The Fourier transform of the output signal is given by (c) [6, 1 3 j, 2, 1 + 3 j ]
Y ( jw ) = H( jw )X( jw ) (d) [6, 1 + 3 j, 0, 1 3 j ]

Therefore, Solution. The four-point DFT of sequence {1, 0,
2, 3 is given as
2p [ d (w 2) + d (w + 2)] 1 1 1 1 +2 +3 6
1
Y ( jw ) = 1 1
2 + jw 1 j 1 j 0 1 2 3j 1 + 3 j
1 1 1 1 2 = 1 +2 3
= 0
2p 2p
= d (w 2) + d (w + 2) 1 j 1 j 3 1 2 3 j 1 3 j
2 + j2 2 j2
Therefore, DFT of the given sequence is
=
2p
[ (2 j2)d (w 2) + (2 + j2)d (w + 2)] [6, 1 + 3 j, 0, 1 3 j] .
8 Ans. (d)
p
=
2
[ d (w 2) + d (w + 2)]
p
j
2
[ d (w 2) d (w + 2)]
cos 2t sin 2t
= +
31-Chapter-31-Gate-ECE.indd 749 2 2 5/29/2015 7:42:09 PM
18. A function is given by f (t) = sin2 t + cos 2t. Which 20. For an N-point FFT algorithm with N = 2m , which
of the following is true? one of the following statements is TRUE?
(a)f has frequency components at 0 and (1/2p ) Hz. (a)It is not possible to construct a signal flow
(b)f has frequency components at 0 and (1/p ) Hz. graph with both input and output in normal
(c)f has frequency components at (1/2p ) Hz and order.
(1/p ) Hz. (b)The number of butterflies in the mth state is
(d)f has frequency components at 0, (1/2p ) and N/m.
(1/p ) Hz. (c)In-place computation requires storage of only
2N node data.
(GATE 2009: 1 Mark) (d)Computation of a butterfly requires only one
Solution. Given that the function complex multiplication.
(GATE 2010: 1 Mark)
f (t) = sin2 t + cos 2t
Therefore, Solution. For an N-point FFT algorithm with

N = 2m , the computation of a butterfly requires
1
f (t) = (1 cos 2t) + cos 2t only one complex multiplication and two complex
2 additions.
Hence, the frequency components are 0, 1/p Hz. Ans. (d)
Ans. (b)
21. The first five points of the eight-point DFT of a real
valued sequence are 5, 1 j3, 0, 3 j4 and 3 + j4.
19. Consider a system whose input x(t) and output y(t)

are related by the equation y(t) = x(t t )h(2t )dt The last two points of the DFT are, respectively,
(a) 0, 1 j3 (b) 0, 1 + j3
where h(t) is depicted in the graph shown in the
following figure. (c) 1 + j3, 5 (d) 1 j3, 5
h(t)
Solution. If a sequence x[n] is real then its DFT
X[k] is conjugate symmetric, that is,
t
0
X [k ] = X * [N k ]
Which of the following four properties are pos- In our case, N = 8; therefore,
sessed by the system?
BIBO: Bounded input gives a bounded output. X [k ] = X * [8 k ]
Causal: The system is causal.
Therefore,
LP: The system is low pass.
X [6 ] = X * [ 8 6 ] = X * [ 2 ] = 0
LTI: The system is linear and time-invariant.
(a) Causal, LP (b) BIBO, LTI
X [7 ] = X * [8 7 ] = X * [1] = 1 + j3
(c) BIBO, Causal, LTI (d) LP, LTI
(GATE 2009: 2 Marks) and
Ans. (b)
Solution. It is given that y(t) = x(t t )h(2t )dt
22. The Fourier transform of a signal h(t) is
H( jw ) = (2 cos w )(sin 2w )/w . The value of h(0) is
and h(t). We know that h(t) is not the impulse
response of a low-pass filter. Therefore, the system
is not a low-pass system. However, the system is (a) 1/4 (b) 1/2
both LTI and BIBO. (c) 1 (d) 2
Ans. (b) (GATE 2012: 2 Marks)

is given that g(t) = ep t . Therefore,

2
Solution. It is given that Solution. It
pf 2
2 sin 2w
H( jw ) = 2 cos w
g(f ) = e . As h(t) is a filter matched to g(t).
2w Therefore,
h(f ) = epf
2
It can be expressed as
H( jw ) = H1( jw ) H2 ( jw )
When g(t) is applied as input to h(t), output in
where H1( jw ) = 2 cos w and
frequency domain is represented as
2 sin 2w
H2 ( jw ) = = 2Sa(2w ) y(f ) = g(f )h(f )
2w
H1( jw ) = 2 cos w = (e jw + ejw )
Therefore,
y(f ) = epf epf = e2pf

2 2 2
h2(t) is shown in the following figure.

Ans. (d)
h2(t)
24. The DFT of a vector [a b c d] is the vector
1/2
[a , b , g , d ] . Consider the product
2 Sa[2w] a b c d
d c
[ p q r s] = [a b c d ] c
a b
b
2
d a
2 t
b c d a
Therefore, The DFT of the vector [p q r s] is a scaled version of

jw jw
H( jw ) = (e )H2 ( jw )
(a) a 2 g 2 d 2
+e
b2
= e H2 ( jw ) + ejw H2 ( jw )
jw
(b) a b g d
Therefore,
h(t) = h2 (t + 1) + h2 (t 1) (c) [a + b b +d d +g g + a]
The following figure shows the waveform of h(t). (d) [a b g d]

1 Solution. The DFT of the vector [a b c d]
is [a b g d ] , that is,
1/2
h(t) = a 1 1 1 1 a a + b + c + d
3 1 b 1 j 1 j b a jb c + jd
g = 1 1 1 1 c = a b + c d
1 3

d 1 j 1 j d a + jb c jd
Therefore, the value of h(0) = 1.
Ans. (c)
Now, it is given that
23. Let g(t) = ep t , and h(t) is a filter matched to g(t).
2
If g(t) is applied as input to h(t), then the Fourier a b c d

d c
[ p q r s] = [a b c d ] c
transform of the output is a b
d a b
(a) epf (b) epf
2 2
/2
b c d a
(c) ep f (d) e2pf
2
(GATE 2013: 1 Mark) = a2 + 2bd + c 2 2ab + 2cd 2ac + b2 + d 2 2ad + 2bc

The DFT of [ p q r s] is given as Now,

p + q + r + s = (a2 + c 2 + 2bd) + (2ab + 2cd)
1 1 1 1 + (b2 + d 2 + 2ac) + (2ad + 2bc)
1 j 1 j
[ p q r s] 1 1 1 1 = (a + b + c + d)2 = a 2

1 j 1 j Similarly, p jq r + js = b 2, p q + r s = g 2 and
p+ jq r js = d 2. Therefore, DFT of [p q r s] is
= [( p + q + r + s)( p jq r + js)
a 2 b2 g 2 d 2

( p q + r s)( p + jq r js)] Ans. (a)

CHAPTER 32
z-TRANSFORM
This chapter discusses about z-transforms, properties for ROC of z-transforms, properties of z-transform, LTI systems
and z-transform and unilateral z-transform.
32.1 z-TRANSFORM AND INVERSE The term of integration in Eq. (32.2) is an around a
z-TRANSFORM counterclockwise closed circular contour centered around
the origin, with radius r (r has any value for which X(z)
converges).
z-transform is a discrete-time counterpart of Laplace
transform. The z-transform of a discrete-time signal x[n] 32.1.1 Properties for ROC of z-Transforms
is given by
+
x[n ]zn
1. The ROC of X(z) consists of a ring in the z-plane
X(z) = (32.1)
centered about the origin.
n =
2. The ROC does not contain any poles.
For the convergence of z-transform of signal x[n], the 3. If x[n] is of finite duration, then the ROC is in the
Fourier transform of the signal x[n ]rn should converge. entire z-plane, except possibly z = 0 or/and z = .
The relation between z and r is given by 4. If x[n] is a right-sided sequence and if the circle
z = re jw
z = r0 is in the ROC, then all finite values of z for
which z > r0 will also be in ROC.
The inverse z-transform of X(z) is given by 5. If x[n] is a left-sided sequence and if the circle
z = r0 is in the ROC, then all finite values of z for
X(z)z dz
n 1 which 0 < z < r0 will also be in ROC.
2pj
1
x[n ] = (32.2)

754 CHAPTER 32: z-TRANSFORM

6. If x[n] is a two sided sequence and if the circle
z = r0 is in the ROC, then the ROC consists of a
ring in the z-plane that includes the circle z = r0 .
7. If the z-transform X(z) of x[n] is rational, then the Signal Transform ROC
1 [r cos w 0 ]z1 z >r

ROC is bounded by poles or extends to infinity.
[r n cos w 0 n ]u[n ]
8. If the z-transform X(z) of x[n] is rational, then if
1 2 2
x[n] is right sided, the ROC is in the region in the 1 [2r cos w 0 ]z +r z
z-plane outside the outermost pole. If x[n] is causal,
then the ROC also includes z = . [r n sin w 0 n ]u[n ] [r sin w 0 ]z1 z >r
1 [2r cos w 0 ]z1 + r2z2
9. If the z-transform X(z) of x[n] is rational, then if
x[n] is left sided, the ROC is in the region in the
z-plane inside the innermost pole. If x[n] is anti-
causal, then the ROC also includes z = 0.
32.2 PROPERTIES OF z-TRANSFORM
Table 32.1 lists some of the common z-transform pairs
along with their region of convergence.
z-transform has the following properties:
Table 32.1| Common z-transform pairs along with 1. Linearity: If
x1[n ]
X1(z) ROC R1
their region of convergence. z
Signal Transform ROC

and x2 [n ]
X2 (z) ROC R2
z
d[n] 1 All z
then we have
ax1[n ] + bx2 [n ]
aX1(z) + bX2 (z)
z
z >1
1
u[n]
1
1z ROC containing R1 R2
1
u[n1] z <1 2. Time shifting: If
1 z 1
x[n ]
X(z) ROC R
z
m
d[nm] z All z, expect then we have
zn0 X(z) ROC R
x[n n0 ]
z
0 (if m > 0)
or with possible addition/deletion of origin/infinity
(if m < 0)
3. Shifting in z-domain: If
a u[n] z >a
n 1
x[n ]
X(z) ROC R
z
1 az1
then we have
1
a u[n 1]
n
z <a e j0 n x[n ]
X(e j 0 z)
z
ROC R
1 a z 1
4. Time reversal: If
a z 1
z >a x[n ]
X(z) ROC R
n z
na u[n] 1 2
(1 az )
then we have
1
az 1 1
nanu[n 1] z < a x[ n ] X ROC
z
(1 az 1 2
) z R
5. Convolution: If
1 [cos w 0 ]z1
[cos w 0 n ]u[n ] z >1 x1[n ]
X1(z)
z
ROC R1
1 [2 cos w 0 ]z1 + z2
and x2 [n ]
X2 (z) ROC R2
z
[sin w 0 ]z1
[sin w 0 n ]u[n ] z >1
1 [2 cos w 0 ]z1 + z2
then we have
x1[n ] x2 [n ]
X1(z)X2 (z)
z
ROC containing R1 R 2
(Continued)

32.3 LTI SYSTEMS AND z-TRANSFORM 755
6. Differentiation in z-domain: If 32.3 LTI SYSTEMS AND

x[n ]
X(z) ROC R
z z-TRANSFORM
then we have
dX(z)
nx[n ]
z ROC R
z 32.3.1 LTI Systems Characterized by Difference
dz Equations
7. Initial value theorem: If x[n] = 0 for n < 0,
then x[0 ] lim X(z). Discrete-time LTI systems are characterized by linear
z constant-coefficient difference equations given by
8.Final value theorem: lim x [n ] = lim (1z1 )X(z)
n z 1 N M
Table 32.2 lists the properties discussed in the list above
for easy reference.
ak y[n k ] = bk x[n k]
k =0 k =0
Table 32.2| Properties of z-transform.
Property Signal z-Transform

Linearity ax1[n] + bx2[n] aX1(z) + bX2(z) At least the intersection of
R1 and R2
Time shifting x[n n0] zn0 X(z) R, except for the possible
addition or deletion of the
origin
Scaling in the e jw 0 n x[n ] X(ejw 0 z) R
z-domain z z0R
z0n x[n ] X
z0
X(a1z)
Scaled version of R (i.e.,
an x[n ]
a R = the set of points
{ a z} for z in R)
Time reversal x[n] X(z1) Inverted R (i.e., R1 = the set

of points z1, where z is in R)
x[r ], n = rk
Time expansion x(k)[n ] = for some integer r X(zk) R1/k (i.e., the set of points
0, n rk z1/k, where z is in R)
Conjugation x* [n ] X*(z*) R
Convolution x1[n ] * x2 [n ] X1(z)X2(z) At least the intersection of

R1 and R2
First difference x[n] x[n1] (1 z1 )X(z) At least the intersection of
R and z > 0
k = x[k]
n 1
Accumulation X(z) At least the intersection of
1 z 1 R and z > 1
dX(z)
Differentiation nx[n] z R
in the z-domain dz
Initial value If x[n] = 0 for n < 0,

theorem then x[0 ] lim X(z)
z
Final value lim x [n ] = lim (1z1 )X(z)

n z 1
theorem

The transfer function is given by (z-transform of the impulse response) of the combined
M system. Then
bk zk H(z) = H1(z)H2(z) (32.5)
k =0
H(z) = N
(32.3)
ak zk
32.3.2.3Feedback Interconnection of Two
k =0
Systems
32.3.2 Interconnections of LTI Systems Let h1(t)[H1(z)] be the impulse response (z-transform of
the impulse response) of the system connected in forward
32.3.2.1Parallel Interconnection of Two path, h2(t)[H2(z)] be the impulse response (z-transform of
Systems the impulse response) of the system connected in the
feedback path. Let h(t)[H(z)] be the impulse response
Let h1(t) [H1(z)] and h2(t) [H2(z)] be the impulse responses [z-transform of the impulse response] of the combined
(z-transforms of the impulse responses) of the individ- system. Then,
ual systems and let h(t) [H(z)] be the impulse response H1(z)
H(z) = (32.6)
(z-transform of the impulse response) of the combined 1 + H1(z)H2 (z)
system. Then
H(z) = H1(z) + H2(z) (32.4)
32.4 UNILATERAL z-TRANSFORM
32.3.2.2Series Interconnection of Two
Systems
The unilateral z-transform of a discrete-time signal x[n]
is given by
Let h1(t) [H1(z)] and h2(t) [H2(z)] be the impulse responses +
(z-transforms of the impulse responses) of the individ- X(z) = x[n]zn (32.7)
ual systems and let h(t) [H(z)] be the impulse response n =0
IMPORTANT FORMULAS
1. The z-transform of a discrete-time signal x[n] is 5. For the feedback interconnection of two systems,
+
X(z) = x[n ]z n
. H(z) =
H1(z)
.
n = 1 + H1(z)H2 (z)
2. The inverse z-transform of X(z) is given by 6. The unilateral z-transform of a discrete-time signal
+
X(z)z dz.
n 1
2pj x[n]zn .
1
x[n ] = x[n] is X(z) =
n =0
3. For the parallel interconnection of two systems, 7. Formulas given in Tables 32.1 and 32.2.
H(z) = H1(z) + H2(z).
4. For series interconnection of two systems, H(z) =
H1(z)H2(z).
SOLVED EXAMPLES

1
n
1
1. For the given a signal x[n ] = u[n 2], the (a) X(z) =
7 1 (1/7)z1
z-transform of the signal x[n] is

SOLVED EXAMPLES 757
z 2 1 Solution. Let X(z) and Y(z) be the z-transform of

(b) X(z) = x(k) and y(k), respectively. Let Y1(z) be the output
49 1 (1/7)z 1
of the first adder. The following figure shows the
block diagram of the system.
1
(c) X(z) =
1 (1/2)z1 + Y1(z) +
X(z) Y(z)
z 7 1 + +
(d) X(z) =
49 1 (1/2)z 1
z1
Solution.

b a
1
n
X(z) = u[n 2] zn

n = 7 Now,

1
n
= 7 zn Y1(z) = X(z) bz1Y1(z)
n =2
Rearranging the terms, we get
Therefore, X(z)
Y1(z) =
z 2
1 1 + bz1
X(z) =
49 1 (1/7)z1 From the figure, we have
Ans. (b) Y (z) = Y1(z) + az1Y1(z)
2. For signal given in Question 1, the ROC of the Therefore,
Y (z ) = Y1 (z ) 1 + az1
z-transform of x[n] is
1
(b) z <
1
(a) z >
7 7 Substituting the value of Y1(z) in the above equa-
tion, we get
1 1
(c) z > (d) z <
(1 + az1 )
2 2 X(z)
Y (z) = 1
(1 + bz )
1
Solution. X(z) converges for z > . Therefore, The transfer function is
7
the ROC of X(z) is z > .
1 Y (z) 1 + az1
H(z) = =
7 Ans. (a) X(z) 1 + bz1
Ans. (a)
3. The following figure shows the block diagram of
1
a system. The transfer function Y (z)/X(z) of the n
4. The z-transform of the signal x[n ] = 5 u[n ]
system is 2
1
n
4 u[n ] is
x(k) y(k) 3
z(3z + 1) z
(a) (b)
z1 (2z 1)(3z 1) (2z 1)(3z 1)
z(6z + 2) 1
(c) (d)
(2z 1)(3z 1) (2z 1)(3z 1)
b a
Solution. The z-transform of x[n] is
1 + az1 1 + bz1
1 n 1
n n
(a) 1
(b) X(z) = 5 u[n ] 4 u[n ]z
3
1 + bz 1 + az1 n =
2
1 + az1 1 bz1
1
n
1
n
(c) 1
(d) = 5 u[n ]zn 4 u[n ]zn
1 bz 1 + az1 n =

2 n =

3

Therefore, Solution. It is given that

1 1
1 1 y[n ] y[n 1] + y[n 2] = x[n ].
4
1 1
X(z) = 5
1 1 3 6
1 z 1 z Taking z-transform on both sides, we get
2 3
10z 12z
= Y (z) z1Y (z) + z2 Y (z) = X(z)
1 1
2z 1 3z 1 3 6
30z 2 10z 24z 2 + 12z
(2z 1)(3z 1)
= Solving the above equation, we get
z(6z + 2) Y (z) 1
=
=
(2z 1)(3z 1) X(z) 1 (1/3)z1 + (1 / 6)z2
Ans. (c)
The poles of H(z) are (1/6) j( 5 36 ). Since,
5. An LTI system has the following properties: the system is causal, the ROC is given by
P1: h[n] is real and right sided. z > (1/6) j( 5 36 ) > 1 6 .
P2: H(z) has two poles and one of the non-real Ans. (a)
poles is on the location z = 4/5. 7. For the data given in Question 6, the output Y(z)
P3: lim H(z) = 1. for the given input is
z
The system is 1
(a) Y (z) =
(a) Both causal and stable 1 (1/3)z1 + (1 / 6)z2
(b) Causal but not stable
(c) Stable but not causal 1
1
, z <1/3
(d) Not causal and not stable 1 (1/3)z
Solution. Since lim H(z) = 1, H(z) has no poles 1

z (b) Y (z) = 1 2
at infinity. Since h[n] is right sided and H(z) has 1 (1/3)z + (1/6)z
no poles at infinity, the system is causal. Since the
1
system is causal, the numerator and denominator
1
, z > 1/3
polynomials of H(z) are of the same order. Since 1 (1/3)z
H(z) has two poles, it has two zeros. Since h[n] is
real, the poles occur in conjugate pairs. Therefore, 1
(c) Y (z) = 1 2
both poles lie on the circle z = 4/5. The ROC of 1 (1/3)z + (1/6)z
H(z) is therefore z > 4/5 which includes the unit
circle. Therefore, the system is stable. 1
1
,1 6 < z < 1/3
Ans. (a) 1 (1/3)z
6. A causal LTI system is defined by the difference (d) None of these
1 1
equation y[n ] y[n 1] + y[n 2] = x[n ].
3 6 Solution. It is given that
1
n
Input x[n ] = u[n ] is applied to the above
1
n
3 x[n ] = u[n ]
system. The system function of the system is 3
1
, ROC of z > 1 6
Therefore,
(a)
1 (1/3)z + (1/6)z2
1
1 1
X(z) = 1
,z >
(b)
1
, ROC of z < 1 6 1 (1/3)z 3
1 2
1 (1/3)z + (1/6)z Now,
z 1 Y(z)=H(z)X(z)
(c) 1 2
, ROC of z > 1 6
1 (1/3)z + (1/3)z Therefore,
1
z
, ROC of z < 1 6
1 1
(d) 1 2 Y (z) = 1 2 1
1 (1/3)z + (1/6)z 1 (1/3)z + (1/6)z 1 (1/3)z

SOLVED EXAMPLES 759
The ROC is given by intersection of ROC of H(z) The z-transform of x[n] is given by
and X(z). Therefore,
+
z >
1 X (z) = x[n ]zn
3 n =
Ans. (b) +
8. For an even sequence, x[n] = x[n], the relation = x[n ]z n

n =
between X(z) and X(1/z) is given by
1 1
(a) X(z) = X (b) X(z) = X(z) =X
z z
1
(c) X(z) = X(z) (d) X(z) = X
z
It is given that x[n] = x[n]; therefore,
1
X(z) = X
z
Solution. The z-transform of x[n] is given by
+
X(z) = x[n ]zn Ans. (d)
n =
1. The z-transform of a signal is given by X(z) = Solution. From initial value theorem, if x[n] = 0
1 4
1 z (1 z ) for n < 0, then
. Find its final value.
4 (1 z1 )2 x[0 ] lim X(z)
z
Solution. From the final value theorem, we know It is given that

(1 2z1 )
that
X(z) = 4
lim x [n ] = lim (1 z1 )X(z) (1 z1 )2
n z 1
Therefore,
(1 2z1 )
Now,
z1(1 z4 )
x[0 ] = lim 4 =4
lim (1 z1 )X(z) = lim (1 z1 )
1 z (1 z1 )2
z 1 z 1 4 (1 z1 )2 Ans. (4)
1 4
1 z (1 z ) 3. The ROC of the z-transform of a unit step function
= lim
z 1 4 (1 z1 ) is the magnitude of z is greater than a value. What
is that value?
1 1 (z 4 1)/z 4
= lim
z 1 4 z (z 1)/z
Solution. It is given that h(n) = u(n). Therefore,

= lim
1 (z 2 1)(z 2 + 1) H(z) = 1zn
z 1 4 z 4 (z 1)
n =0
For the convergence of H(z),
1 (z + 1)(z 1)(z 2 + 1)
( z 1 )
n
<
= lim
z 1 4 z 4 (z 1)
n =0
1
= 4 = 1 Therefore, the ROC is the range of values of z for
4 which
Ans. (1)
z1 < 1 or z > 1
2. The z-transform of a signal x[n](x[n] = 0 for n < 0) is
(1 2z1 )
Hence, the required value is 1.
given by X(z) = 4 . Find its initial value. Ans. (1)
(1 z1 )2

PRACTICE EXERCISE

2 1
n
2
1. If the real exponential sequence x(n) is given as (a) h[n ] = u[n ] + (2)n u[n 1]

3 2 3
x(n) = an , n 0, a > 0
2 1
n
2
= 0, n < 0, a > 0 (b) h[n ] = + u[n ] (2)n u[n 1]

3 2 3
then its z-transform is 2 1
n
2 n
1 1 (c) h[n ] = u[n ] + (2) u[n 1]
(a) ; z > 1 (b) ; z >a 3 2 3
1 z 1 1 az1
2 1
n
2
(d) h[n ] = u[n ] (2)n u[n 1]
(c) 1 for all z (d)
1
; z <a
3 2 3
1 az1 (2 Marks)
(1 Mark)
6. Which of the following statements is/are true?
2. A linear discrete-time system has the characteris-
S1: If x1[n ] X1(z) ROC R1 and
z
tics equation, z 3 0.64z = 0. The system
x2 [n ] X2 (z) ROC R2 then
z
(a)
is stable
ax1[n ] + bx2 [n ] aX1(z) + bX2 (z) ROC containing R1 R2
z
(b)
is marginally stable
aX1(z) + bX2 (z) ROC containing R1 R2
z
(c)
is unstable
(d)
cannot be determined from given data
S2: If x[n ] X(z) ROC R then
z
(1 Mark)
x[n n0 ] zn0 X(z) ROC R withpossible addition/d
z
1
(1 z(1/3)zn0 )
3. The inverse z-transform of Xx([n n0 ]
z)= z X(z,) z >ROC2 R withpossible addition/deletionof oriigin/infinity
1 1
1
(1 (1/3)z ) (1 z )(1 + 2z )
1 1
, z > 2 is (a) S1 (b) S2
(1 z )(1 + 2z ) (c) both S1 and S2 (d) Neither S1 nor S2
(a) x[n ] = u[n ] + (2) u[n ]
2 7 n (2 Marks)
9 9
7. The following figure shows the block diagram of an
(b) x[n ] = u[n ] + (2)n u[n ]
7 2 LTI system.
9 9
x[n] y[n]
(c) x[n ] = u[n ] (2)n u[n ]
2 7 + +
9 9
z1 z1
(d) x[n ] = u[n ] (2)n u[n ]
7 2
9 9
+ 1 x1[n] y1[n] 5 +
(2 Marks) 3 3
4. The z-transform of the signal x[n ] = 3n u[n 1] z1 z1

+2n u[n ] is

1 1
6 3
1 1

x2[n] y2[n]
(a) ,2 < z < 3
1 2z1 1 3z1 What is the transfer function of the system?
(b)
1
+
1
,2 < z < 3 1
1 2z1 1 3z1 (a)
1 2

1 + (1/3)z (1/6)z
1 1
(c) 1
,2 < z < 3
1 (1/2)z 1 (1/3)z1
1
1 2
1 (5/3)z (1/3)z
1 1
(d) 1
+ ,2 < z < 3
1 (1/2)z 1 (1/3)z1 1
(b)
2
1
+
1 + (1/3)z (1/6)z
(2 Marks)

5. The unit sample response of a discrete-time stable
1
LTI system with input x[n]output y[n] relation 1 2
y[n 1] 5/2y[n] + y[n + 1] = x[n] is 1 (5/3)z (1/3)z

(c) 1 4z 1 4z

2 (z + 2) z 4
(a) ,
1
1 (1/3)z = (1/6)z (z + 2)
4z 1 4z

(z 2) z 4 (z 2)
1 (b) ,
1 2
1 + (5/3)z + (1/3)z
4 4z
1

(z 2) z 3
(c) ,
(d) 1 (z 2)
1 2
+
1 (1/3)z + (1/6)z 4 1 4z
(d) , 3
(z + 2) z (z + 2)
1

1 + (5/3)z1 + (1/3)z2
(2 Marks)
(2 Marks)
2z 2 + 2z
11. The inverse z-transform of X(z) = is
8. For the block diagram of an LTI system shown in z 2 + 2z 3
Question 7, the relationship between y1[n] and x1[n] is
(b) (3) [n ] + [n ]
n
(a) [n ]
(a) x1[n] = y1[n]
(c) (2) [n ] + [n ]
(b) x1[n] = y1[n] n
(d) None of these
(c) x1[n]y1[n] = 1 (2 Marks)
(d) depends upon the value of x[n]
1
(1 Mark) n +1
12. Given that the signal x[n ] = u[n + 3]. Which
9. For the block diagram of an LTI system shown in 2
Question 7, the relationship between y2[n] and x2[n] is of the following statements is true?
(a) x2[n]y2[n] = 1 S1: Fourier transform of x[n] exists as the ROC of
(b) x2[n] = y2[n] z-transform includes the unit circle.
(c) x2[n] = y2[n] S2: Fourier transform of x[n] does not exist as the
(d) depends upon the value of x[n] ROC of z-transform does not be include the
unit circle.
(1 Mark) 4z 3 1
S3: z-transform of x[n] is ,z > .
10. Given two sequences x1[n] = [4, 8, 16, 64, ...] and 1 (1/2)z1 2
x2[n] = [0, 0, 0, 0, 4, 8, 16, 64, ...]. The z-transforms
(a) S1 only (b) S2 only
Z(x1) and Z(x2) of the sequences x1[n] and x2[n],
(c) S2 and S3 (d) S1 and S3
respectively, are
(2 Marks)
1. Given that the z-transform of a sequence [a, b, c, d, 2. If the region of convergence (ROC) of x1 [n ] x2 [n ]
is 1 < z < 3 and ROC of x1 [n ] x2 [n ] includes
2 5
0, 0, ...] is 1 + 2 3 . Find the value of d.
z z
(2 Marks) a < z < b, then find the value of b.
(1 Mark)
1. (b) It is given that 2. (a) It is given that the characteristic equation of

x(n) = an n 0, a > 0 the system is z 3 0.64z = 0. Therefore,
Therefore, z(z 2 0.64) = 0 or z(z 0.8)(z + 0.8) = 0
x(n) = an u(n) a>0 Therefore, the poles of the system are z = 0, 0.8
and 0.8. Since all three poles are inside the unit
z 1
x(n) X(z) = ; z>a= ; z >a
z circle, the system is stable.
z a 1 az1

3. (a) It is given that 7. (a) The block diagram given in the problem
is a cascade connection of two systems as shown in
(1 (1/3)z1 ) the following figure.
X(z) = ,z >2
(1 z1 )(1 + 2z1 )
H1[z] H2[z]
Using partial fraction expansion, we get
x[n] y[n]
2/9 7/9 + +
X(z) = + ,z >2
(1 z1 ) (1 + 2z1 )
z1 z1
Taking inverse z-transform, we get
2 7 1 5
x[n ] = u[n ] + (2)n u[n ] + 3 x1[n] y1[n] 3
+
9 9
4. (a) The z-transform of 3n u[n 1] is z1 z1
1
,z <3 1 1
1 3z1
6 3
x2[n] y2[n]
The z-transform of 2n u[n ] is From this figure, we have

1
,z >2 1
1 2z1 H1(z) = 1 2
1 + (1/3)z (1/6)z
The z-transform of x[n ] is 1
and H2 (z) = 1 2
1 1 1 (5/3)z (1/3)z
1
,2 < z < 3
1 2z 1 3z1
The overall transfer function H(z) is
5. (d) The given inputoutput relationship is
H(z) = H1(z)H2 (z)
y[n 1] 5/2y[n] + y[n+1] = x[n]
1 1
=
Taking the z-transform and rearranging the terms, 1 + (1/3)z1 (1/6)z2 1 (5/3)z1 (1/3)z2
we get
Y (z) 8. (b) From the figure shown in the solution of
H(z) = Question 7, it is clear that x1[n] = y1[n].
X(z)
1 9. (c) From the figure shown in the solution of
=
z1 (5/2) + z
Question 7, it is clear that x2[n] = y2[n].
z 1
10. (b) It is given that he sequence x1[n] = [4, 8. 16,
= 64, ...]. It is a geometrical sequence of the form
z2 (5/2)z1 + 1 4 2 n.
Z(x1 ) = Z(4 2n )
The partial fraction expansion of the above expres-
sion is
= 4Z(2n )
Y (z) 2/3 2/3
H(z) = =

1 (1/2)z1
4z
X(z) 1 2z 1 =
(z 2)
Since the system is stable, the ROC includes the
unit circle. Therefore, (1/2) < z < 2. Therefore, x2[n] is a delayed version of x1[n] by four
steps. The z-transform of a delayed sequence is
2 1
n
2 givenby
h[n ] = u[n ] (2)n u[n 1]
3 2 3 1
Z(x[n n0 ]) = Z(x[n ])
6. (c) z n0

Here, n0 = 4. Therefore, or
z z
1 4z X(z) = + ,z >3
z 1 z + 3
Z(x2 ) = 4
z
(z 2) The inverse z-transform of X(z) is (3)n d [n ] + d [n ].
11. (b) It is given that 12. (d) It is given that
2
2z + 2z
1
n +1
X(z) =
z + 2z 3
2 x[n ] = u[n + 3]
2
Therefore,
X(z) 2z + 2 Therefore,
= 2
z z + 2z 3
1
n +1
A B X(z) = u[n + 3]zn
= + n = 2
z 1 z + 3

1
n +1
2 zn
Multiplying throughout by z + 3 and substituting
=
z = 3, we get
n = 3
2z + 2 4 n 2
1
2
A= = =1
z 1 z = 3 4 = zn + 3
Multiplying throughput by z 1 and substituting n =0
z = 1, we get Hence,
2z + 2 4 4z 3 1
B= = =1 X(z) = 1
,z >
z +3 z =1 4 1 (1/2)z 2
Therefore,
X(z) 1 1 Since the ROC contains the unit circle, the Fourier
= + ,z >3
z z 1 z + 3 transform of x[n] exists.
1. The z-transform of a sequence x[n] is Therefore, a = 1, b = 0, c = 2 and d = 5. Hence,

+ + the answer is d = 5.
x[n]zn =
x[n ]
X(z) =
zn Ans. (5)
n =0 n =0
It is given that the z-transform of sequence [a, b, c, 2. The ROC remains the same after addition and sub-
d, 0, 0, ...] is traction in z-domain. Therefore, the value of b is 3.
2 5
1+ 2 3 Ans. (3)
z z
1.A sequence x(n) with the z-transform X(z) = Solution. It is given that input x[n] has z-transform
z 4 + z 2 2z + 2 3z4 is applied as an input to X(z) = z 4 + z 2 2z + 2 3z4 and impulse response
a linear, time-invariant system with the impulse of the LTI system is h(n) = 2d (n 3). Therefore,
response h(n) = 2d (n 3) where
H(z) = 2z3
1, n = 0
a(n) = Now,
0, otherwise
Y (z) = H(z)X(z)
The output at n = 4 is
(a) 6 (b) zero = 2z3 (z 4 + z 2 2z + 2 3z4 )
(c) 2 (d) 4 = 2(z + z1 2z2 + 2z3 3z7 )
(GATE 2003: 1 Mark)

Taking the inverse of z-transform, we get Since b does not appear in the denominator of the
transfer function, b can be of any value. For system
d (n + 1) + d (n 1) 2d (n 2)
y(n) = 2 to be stable all poles should be inside unity circle,
+ 2d (n 3) 3d (n 7 ) that is, z <1. Setting the denominator term to zero,
we get
From the above expression, it is clear that at
n = 4, we have y(4) = 0. a
z=
Ans. (b) 2
z Therefore, a < 2.
2. The z-transform of a system is H(z) = . If
z 0. 2 Ans. (c)
the ROC is z < 0.2, then the impulse response of 4. The region of convergence of z-transform of the
the system is
5 6
n n
(a) (0.2)n u [n ] (b) (0.2)n u [n 1] sequence u(n) u(n 1) is
6 5
(c) (0.2)n u [n ] (d) (0.2)n u [n 1] 5 5
(a) z < (b) z >
(GATE 2004: 1 Mark) 6 6
z 5 6 6
Solution. Given that H(z) = , ROC is (c) < z < < z <
(d)
z < 0.2 . Therefore, z 0. 2 6 5 5
z 1 (GATE 2005: 1 Mark)
H(z) = 1
= , ROC is z < 0.2
z(1 0.2z ) 1 0.2z1 5 6
n n
Solution. The z-transform of u(n)
1 6 5
Comparing with an u[n 1] , z < a, u(n 1) is
we get 1 az1
h(n) = (0.2)n u[n 1] 1 1

+ 1
Ans. (d) 1 (5/6)z1 1 (6/5)1 z
3. A causal LTI system is described by the difference Therefore, the ROC of the given sequence is
equation
5 6
< z <
2y [n ] = a y [n 2] 2x [n ] + b x [n 1] 6 5
The system is stable only if Ans. (c)
(a) a = 2, b < 2 1
n
5. Let x(n) = u(n), y(n) = x2 (n) and Y (e jw ) be
2
(b) a > 2, b > 2
the Fourier transform of y(n). Then Y (e j 0 ) is
(c) a < 2, any value of b 1
(a) (b) 2
(d) b < 2 any value of a 4
4
(GATE 2004: 2 Marks) (c) 4 (d)
3
(GATE 2005: 1 Mark)
2y[n ] = a y[n 2] 2x[n ] + b x[n 1] Solution. It is given that
1
n
x (n ) = u (n )
Taking z-transform, we get 2
2Y (z) = aY (z)z2 2X(z) + bX(z)z1
and y(n) = x2 (n)
Rearranging the terms, we get Therefore,
Y (z) bz1 2 1 1
2n n
y(n) = u2 (n) = u (n )
X(z) 2 az2 2
=
4

The z-transform Y(z) of y(n) is 2

1
Y (z) =
1 (1/4)z1
1 1
Substituting z = e jw in the above equation, we get
1/2 1/2
jw 1
Y (e )=
1 (1/4)ejw (c)
Therefore, 6 4 2 0 2 n
1 4
Y (e j 0 ) = =
1 (1/4) 3
2
Ans. (d)
Linked Answer Questions 6 and 7: A sequence

x(n) has non-zero values as shown in the following 1 1
figure. 1/2 1/2
2 x(n) (d)
5 3 1 1 3 n
1 1 (GATE 2005: 2 Marks)

1/2 1/2
n
y(n) = x 1 , n even
2
2 1 0 1 2 n = 0 for n odd
Therefore, for
6. The sequence
n = 0, y(n) = x(1) = 1
n
x 1
y(n) = 2
for n even n = 2, y(n) = x(0) = 2

0 for n odd
n = 4, y(n) = x(1) = 1
will be n = 6, y(n) = x(2) = 1/2
Hence, y(n) given in option (a) is the correct answer.
2 Ans. (a)
7. The Fourier transform of y(2n) will be
1 1 (a) ej2w [cos 4w + 2 cos 2w + 2]
1/2 1/2 (b) [cos 2w + 2 cos w + 2]
(a) (c) ej w [cos 2w + 2 cos w + 2]

2 0 2 4 6 n (d) ej w /2 [cos 2w + 2 cos w + 2]
2
Solution.
y(2n) = x(n 1)
1 1
Therefore,
1
d (n + 1) + d (n) + 2 d (n 1)
1/2 1/2
y(2n) =
2
(b) 1
+ d (n 2) + d (n 3)
3 1 1 3 5 n 2

which is from the figure shown in the given data. 10 F

Let f(n) = y(2n). Taking z-transform, we get S X[z]
x(n)
F (z) = z + 1 + 2z1 + z2 + z3
1 1
2 2 + Sampler
200 k z -Transform
jw (fs=10 Hz)
Substituting z = e in the above equation, we get 5V
F (e j w ) =
1 jw
e + 1 + 2ej w + e2 j w + e3 jw
1
2 2
1 10. The samples x(n) (n = 0, 1, 2, ) are given by
= ej w e2 j w + e j w + 2 + ej w + e2 j w
1
2
2 (a) 5(1 e0.05n ) (b) 5e0.05n
e +2 j w 2 j w
= ej w + e j w + ej w + 2 (c) 5(1 e5n ) (d) 5e5n
+e
2
Therefore,
Solution. After closing the switch, the voltage
f(n) = y(2n) = ej w [cos 2w + 2 cos w + 2] across the resistor is given by
5
Ans. (c)
200 103
VR (s) =
8. If the ROC of x1 [n ] + x2 [n ] is < z < , then 200 103 + [1/(10 + 106 s)] s
1 2
3 3
the ROC of x1 [n ] x2 [n ] includes 5 2 105 10 10 66
=
1 2 2 105 105 s + 1
(a) < z < 3 (b) < z < 3 5
3 3 =
3 1 2 s + 0.5
(c) < z < 3 (d) < z <
2 3 3 The voltage across the resistor in time-domain is
(GATE 2006: 1 Mark) given by
VR (t) = 5e0.5t
Solution. The ROC remains the same after addi-
tion and subtraction in z-domain. Hence, the It is given that the samples are taken at 10Hz.
1 2
answer is < z < . Therefore, the sampling time instants are n/10.
3 3 Ans. (d) Therefore, the samples are
9. The z-transform X[z] of a sequence x[n] is given by x(n) = 5e0.5n /10
= 5e0.05n
0.5
X[ z ] = . It is given that the ROC of X[z]
1 2z1 Ans. (b)
includes the unit circle. The value of x[0] is
11. The expression and the ROC of the z-transform of
(a) 0.5 (b) 0 the sampled signal are
(c) 0.25 (d) 0.5
, z < e5(b) , z < e0.05
5z 5z
(GATE 2007: 2 Marks) (a)
z e5 z e0.05
, z > e0.05 (d) , z > e5

Solution. It is given that 5z 5z
(c) 0.05
0.5 z e z e5
X [z ] =
1 2z1 (GATE 2008: 2 Marks)
and the ROC includes a unit circle. Therefore, the Solution. Taking z-transform of signal x(n), we get
signal is a left-handed signal. Hence,

x[n ] = (0.5)(2)n u(n 1) X[ z ] = 5e0.05n zn
n =0
From the above equation, x[0] = 0.
Ans. (b) = 5 (e0.05z1 )n
n =0
Linked Answer Questions 10 and 11: In the
and ROC is z > e0.05
network shown in the following figure, the switch is 5z
closed at t = 0 and the sampling starts from t = 0.
Therefore, X[z ] =
z e0.05
The sampling frequency is 10 Hz. Ans. (c)

12. The ROC of z-transform of the discrete time 14. Consider the z-transform X(z) = 5z 2 + 4z1 + 3; 0 < z <
sequence x(n) = (1/3) u(n) (1/2) (X 1
z)1)= is5z + 4z + 3; 0 < z < . The inverse z-transform x[n] is
n (
n n 2
(a) 5d [n + 2] + 3d [n ] + 4d [n 1]
1 1 1
< z < (b) z >
(b) 5d [n 2] + 3d [n ] + 4d [n + 1]
(a)
3 2 2
1 (c) 5u [n + 2] + 3u [n ] + 4u [n 1]
(c) z < (d) 2 < z < 3
3 (d) 5u [n 2] + 3u [n ] + 4u [n + 1]
(GATE 2009: 1 Mark)
(GATE 2010: 1 Mark)
Solution. It is given that Solution. It is given that
1 1 X(z) = 5z 2 + 4z1 + 3; 0 < z <
n n
x(n) = u(n) u(n 1)
3 2
We know that
d n + n0
z n0
z
Here, (1/3)n u(n) is right-sided signal; so the ROC
Therefore,
will be 1/3 < z . Also (1/2)n u(n 1) is left-sided
x [n ] = 5d [n + 2] + 4d [n 1] + 3d [n ]
1
signal so ROC will be z < . Combining this Ans. (a)
2
information, the ROC of the given function will be 15. Two discrete time systems with impulse responses
given as h1 [n ] = d [n 1] and h2 [n ] = d [n 2] are con-
1 1 nected in cascade. The overall impulse response of
< z < the cascaded system is
3 2
Ans. (a) (a) d [n 1] + d [n 2] (b) d [n 4]
13. A system with transfer function H(z) has (c) d [n 3] (d) d [n 1] d [n 2]
the impulse response h() defined as h(2) = 1,
h(3) = 1 and h(k) = 0 otherwise. Consider the fol-
(GATE 2010: 1 Mark)
lowing statements. Solution. It is given that h1 [n ] = d [n 1] and
h2 [n ] = d [n 2].Therefore,
S1 : H(z) is a low-pass filter
h1 [n ] = d [n 1]
H1(z) = z1
S2 : H(z) is an FIR filter. z
and h2 [n ] = d [n 2]
H2 (z) = z2
Which of the following is correct? z
(a) Only S2 is true.
(b) Both S1 and S2 are false. The overall impulse response in z-domain is
(c) Both S1 and S2 are true, and S2 is a reason for S1 .
H(z) = H1(z)H2 (z) = z1z2 = z3
(d) Both S1 and S2 are true, but S2 is not a reason
for S1 . The overall impulse response in discrete-time
(GATE 2009: 2 Marks) domain is
h [n ] = d [n 3 ]
Solution. It is given that h(2) = 1, h (3) = 1 and h(k) = 0 otherwise
h(2) = 1, h (3) = 1 and h(k) = 0 otherwise. h(t) is shown in the following
Ans. (c)
figure. 16. The transfer function of a discrete time LTI system
is given by
2 (3/4)z1
1 H(z) =
1 (3/4)z1 + (1/8)z2
1

2 3 Consider the following statements:
1
S1 :The system is stable and causal for
1
From the given figure, we can see that it is finite ROC : z > .
2
impulse response (FIR) filter and not a low-pass
filter. S2 :The system is stable but not causal for
1
Ans. (a) ROC : z < .
4

S3 :The system is neither stable nor causal for Solution. It is given that y[n ] = x[n 1] .
1 1
ROC : < z < .
Therefore, Y (z) = z1X(z) or = z1.
Y (z)
4 2
X(z)
Which one of the following statements is valid? For the cascaded system,
(a) Both S1 and S2 are true
(b) Both S2 and S3 true H(z) = H1(z)H2 (z)

(c) Both S1 and S3 are true Therefore,
(1 0.4z1 )
(d) S1 , S2 and S3 are all true z 1 = H2 (z)
(GATE 2010: 2 Marks) (1 0.6z1 )
Solution. A discrete-time LTI system is causal if z1(1 0.6z1 )

or, H2 (z) =
and only if the ROC of its system function is the (1 0.4z1 )
exterior of a circle, including infinity. A discrete-
time LTI system is stable if and only if the ROC of Ans. (b)
1 1
its system function includes the unit circle, z = 1. n n
18. If x [n ] = u [n ] , then the ROC of its
3 2
It is given that
2 (3/4)z1 z-transform in the two-plane will be

H (z ) =
1 (3/4)z1 + (1/8)z2 1 1 1
(a) < z < 3 (b) < z <
Therefore, 3 3 2
1
(c) < z < 3
1
(d) < z
(1 (1/4)z1 ) + (1 (1/2)z1 ) 2 3
H(z) =
(1 (1/4)z1 )(1 (1/2)z1 ) (GATE 2012: 1 Mark)
1 1
= 1
+
1 (1/4)z 1 (1/2)z1 Solution. It is given that
1 1
n n
x [n ] = u [n ]
1
For the ROC : z > , the system is stable and
causal. 2 3 2
1 1 1
For the ROC : z < and the ROC : < z < , Therefore,
4 4 2 n
1 1 1
n n
the ROC does not include the unit circle. So, the x [n ] = u [n ] + u [n 1] u [n ]
system is not stable. Also the ROC is not the exte- 3 3 2
1
rior of z = , so it is not causal. The z-transform of
2 Ans. (c)
1
n
u [n ]
1 1
17. Two systems H1(z) and H2 (z) are connected in cas- ROC z >
cade as shown in the following figure. The overall 3 1 (1/3)z1 3
output y[n] is the same as the input x[n] with a The z-transform of
one unit delay. The transfer function of the second n
1
u [n 1]
1
system H2 (z) is
ROC z < 3
3 1 3z1
(10.4z 1) The z-transform of
x[n] H1(z)= H2(z) y[n]
(10.6z 1)
1
n
u [n ]
1 1
ROC z >
2 1 (1/2)z1 2
(1 0.6 z1 ) z1(1 0.6 z1 )
(a) (b)
z1(1 0.4 z1 ) (1 0.4 z1 )
So the overall ROC will be intersection of three
ROCs, that is,
z1(1 0.4 z1 ) (1 0.4 z1 ) 1
(c) (d) < z <3
(1 0.6 z1 ) z1(1 0.6 z1 ) 2

CHAPTER 33
SAMPLING THEOREM
Sampling is the process in which a continuous time signal is sampled at discrete instants of time and its amplitudes at
those discrete instants of time are measured.
33.1 SAMPLING THEOREM For sampling band-pass signals, lower sampling rates
can sometimes be used. The sampling theorem for band-
pass signals states that if a band-pass message signal has
The sampling theorem states that a band-limited signal a bandwidth of fB and an upper frequency limit of fu,
with the highest frequency component, as fM Hz can be then the signal can be recovered from the sampled signal
recovered completely from a set of samples taken at a by band-pass filtering if
rate of fS samples per second, provided that
2fu
fS (33.2)
fS 2fM (33.1) k
This theorem is also known as the uniform sampling where fS is the sampling rate and k is the largest integer
theorem for base band or low-pass signals. The mini- not exceeding fu/fB.
mum sampling rate of 2fM samples per second is called
the Nyquist rate and its reciprocal the Nyquist interval. 33.2 SAMPLING WITH ZERO-ORDER
This process of sampling is referred to as an impulse- HOLD
train sampling. The original signal is recovered from the
sampled signal by passing it through an ideal low pass
filter with a cut-off frequency greater than fM and less In a zero-order hold system, the sample of the signal at
than fS - fM. Figure 33.1 shows the process of impulse- any instant is held, until the next sample is taken. Figure
train sampling and recovery of the original signal using 33.2(a) shows any arbitrary signal and Fig. 33.2(b) shows
ideal low pass filter. the sampled signal through a zero-order hold system.

770 Chapter 33: Sampling Theorem
+
s(t) = (tnT )
n=
Input Sampled Sampled Recovered

signal signal signal H(jw) signal
x(t) xs(t) xs(t) xr(t)
(a) (b)
X(jw) Xp(jw)
1 ws>2wM
1 T
wM wM w ws wM wM ws w
(c) (d)
H(jw) Xr(jw)
wM <wc <(wswM) 1
T
wc wc w wM wM w
(e) (f)
Figure 33.1|Impulse-train sampling: (a) Sampling process; (b) Signal recovery process; (c) Signal x(t) to be sampled in
frequency domain; (d) Sampled signal; (e) Characteristics of an ideal filter; (f) Recovered signal after filtering.
33.3 ALIASING PROBLEM
(a) When the sampling frequency is less than the Nyquist

frequency, the original signal is not recoverable by low-
passing filtering. The sampled signals overlap in the fre-
quency domain and this process is referred to as aliasing.
x(t) Zero-order x0(t) Figure 33.3 shows the aliasing phenomenon.
hold
X(jw)
(b)
1
Figure 33.2| Zero-order hold system: (a) Arbitary
signal x(t); (b) Sampled signal utilizing
zero-order hold. wM wM w
(a)
The transfer function of a zero-order hold system is Xs(jw)
given by
1
2 sin(wT /2)
H( jw ) = e-jwT /2
T
w (33.3)
The original signal can be recovered by passing the sam- 0 ws w

pled signal through a system with transfer function (wswM)
e jwT /2 H( jw ) (b)
H ( jw ) = (33.4) Figure 33.3| Aliasing phenomenon: (a) Original signal;
2 sin(wT 2)/w
(b) Sampled signal.
IMPORTANT FORMULAS
1. For band-limited signals, fS 2fM . 2fu

2. For band-pass signals, fS , where k is the
k
fu
largest integer not exceeding .
fB

SOLVED EXAMPLES 771
SOLVED EXAMPLES

1. A signal containing only two frequency compo- generate xs (t) = x(10-4 n)d (t - 10-4 n). Which
nents (3 kHz and 6 kHz) is sampled at the rate of n =-
8 kHz, and then passed through a low pass filter of the following statements is true?
with a cut-off frequency of 8 kHz. The filter output S1: Sampling period = 10-4s.
(a) is an undistorted version of the original signal. S2: x(t) can be recovered exactly from xs(t).
(b) contains only the 3 kHz component. S3: x(t) cannot be recovered exactly from xs(t).
(c) contains the 3 kHz component and a spurious (a) only S2 (b) Only S3
component of 2 kHz. (c) S1 and S2 (d) S1 and S3
(d) contains both the components of the original
signal and two spurious components of 2 kHz Solution. It is given that sampled signal is
and 5 kHz.
Solution. It is given that fS = 8000 samples/s,

xs (t) = x(10-4 n)d (t - 10-4 n)
n =-
fM1 = 3 kHz and fM 2 = 6 kHz. The spectrum of
the sampled signal would have frequency compo- Therefore, the sampling period is 10-4s. The
nents given by nfS fM . So, the frequency compo- Nyquist rate for the given signal is
nents present are
2 5000p = 10000p
3 kHz, (8 3) kHz, , 6 kHz, (8 6) kHz
= 3 kHz, 5 kHz, 11 kHz 6 kHz, 2 kHz, 14 kHz Therefore, the signal x(t) is recovered is from
xs(t) if the sampling period is 2p/10000p =
It is given that the cut-off frequency of 2 10-4 s. Since the sampling period used is less
LPF = 8 kHz. Therefore, the filter output would that than 2 10-4s, x(t) can be recovered exactly
have frequency components 2 kHz, 3 kHz, 5 kHz from xs(t).
and 6 kHz. Ans. (c)
Ans. (d)
4. Given that the signal x(t) is a band-limited signal
2. The transfer function of a zero-order hold is such that X( jw ) = 0, w > w M. The Nyquist rate
1 - e-Ts 1 for the signal x(t) + x(t - 1) is
(a) (b)
s s (a) wM
1 (b) wM/2
(c) 1 (d)
-e-Ts (c) 2wM
(d) cannot be computed from the given data
Solution. The impulse response, h(t), of zero-
order hold system is h(t) = u(t) - u(t - T ), where Solution. The Nyquist rate for signal x(t) = 2wM.
T is the sampling period. Therefore, The Fourier transform of x(t) + x(t - 1) is [X(jw)
+ e-jwtX(jw)]. Now,
1 e Ts 1 - e-Ts
H(s) = - = [X(jw) + e-jwtX(jw)] = 0 for w > wM
s s s
Ans. (a) Therefore, the Nyquist rate of signal x(t) + x(t - 1)
3. A signal with Fourier transform X(jw) [X(jw) = 0 is also 2wM.
for w > 5000p] undergoes impulse-train sampling to Ans. (c)

1. A 1.0 kHz signal is flat-top sampled at the rate Solution. It is given that fS = 1800 samples/ s
of 1800 samples/s and the samples are applied to and fM = 1000 Hz. The spectrum of the sampled
an ideal rectangular LPF with cut-off frequency signal would have frequency components nfS fM
of 1100 Hz, then what is the value of the other Therefore, the frequency components include the
frequency component (in Hz) at the output of the following:
filter apart from the signal frequency? 1000 Hz, 1800 1000 Hz, 3600 1000 Hz

or 1000 Hz, 800 Hz, 2800 Hz, 2600 Hz, 4600 Hz, components 800 Hz and 1000 Hz. Therefore, apart
from fM, the value of the other frequency compo-
The cut-off frequency of LPF is 1100 Hz. So, nent of the output of the filter is fM = 800 Hz.
the output of filter will contain the frequency Ans. (800)
PRACTICE EXERCISE

1. Consider the following two statements. Which of S2: The signal y(t) can be recovered from ys(t), if the
the statements is/are true? sampling time is less than or equal to 500 s.
S1: The signal x(t) = u(t + T0 ) - u(T - T0 ), when (a) Only S1 (b) Only S2
sampled using impulse train with sampling (c) Both S1 and S2 (d) Neither S1 nor S2
period less than 2T0, produces an output signal (2 Marks)
without aliasing. 5. A band-limited signal x(t) is sampled using impulse
S2: The signal x(t) with frequency domain repre- train with period T such that there is no aliasing.
sentation of X( jw ) = u(w + w 0 ) - u(w - w 0 ), The sampled signal is represented as xs(t), which is
when sampled using impulse train with sam- then converted to a sequence x[n] such that x[n] =
pling frequency greater than 2w0, produces an x(nT). If E is the energy of signal x(t) and EP is the
output signal without aliasing. energy of sequence x[n], then the relation between
(a) S1 only (b) S2 only E and EP is
E
(c) Both S1 and S2 (d) Neither S1 nor S2 (a) E = EP (b) E = P
(2 Marks) T
EP
2. Increased pulse-width in the flat-top sampling, (c) E = (d) E = TEP
2 (2 Marks)
leads to
6. Refer to the following figure. Signal x(t) is sampled
(a) attenuation of high frequencies in reproduction.
using an impulse train with period T = 1 ms and the
(b) attenuation of low frequencies in reproduction.
sampled signal is passed through a low pass filter.
(c) greater aliasing errors in reproduction.
(d) no harmful effects in reproduction. T
(1 Mark) x(t) xp(t) xr(t)
3. The transfer function of a zero-order-hold system is
2 sin(wT 2) p p
H( jw ) = e-jwT /2 . The transfer func-
T T
w + H(jw)
tion of the system for recovering the signal p(t) = d(t nT )
n=
e-jwT /2 H( jw )
(a) is If x(t) = cos(2p 250t + p/4), the reconstructed
2 sin(wT 2)/w signal is xr(t) is given by
e jwT /2 H( jw ) p
(b) is (a) 0 (b) cos 2p 250t +
4
2 sin(wT 2)/w
p
(c) depends upon the value of input signal (c) cos 2p 250t - (d) cos (2p 250t )
(d) None of these 4
(1 Mark) (2 Marks)
7. Referring to the data given in Question 6, if x(t)
= cos(2p 500t + p/4), the reconstructed signal
4. The two signals x1(t) and x2(t) are band-limited
signals with X1( jw ) = 0 for w > 2000p and
xr(t) is given by
X2 ( jw ) = 0 for w > 3000p . The signal y(t) is gen- p
(a) 0 (b) cos 2p 500t +
erated by convolving x1(t) and x2(t). Impulse-train 4
sampling is done on y(t) to generate ys(t). Which of 2p
(c) cos p 500t - (d) cos (2p 500t)

the following statements is true?
4
S1: The signal y(t) is bandlimited to 1000Hz. (1 Mark)

8. The following figure shows a sampling system. X(jw)
1
x(t) xr(t)
(d) w
w -2W -W W 2W
-W
Figure I| Different spectrums for the input signal x(t).
W
+
W = p/2T
d(t-nT ) Xr(jw)
n=-
The set of graphs shown in the following Figs. I

and II show the different spectrums for the input (a) w
signal x(t) and the recovered signal xr(t), respec- -W W
tively. Match the spectrums of input signal with Xr(jw)
the recovered signal.
X(jw)
(b) w
-W W
Xr(jw)
(a) w
-W W
(c) w
X(jw) -2W 2W
Xr(jw)
(b) w (d) w
-2W 2W -W W
X(jw) Figure II| Different spectrums for the recovered
signal xr(t).
(a) Fig.I(a) - Fig.II(a), Fig.I(c) - Fig.II(b)

(b) Fig.I(b) - Fig.II(a), Fig.I(d) - Fig.II(b)
(c) w (c) Fig.I(a) - Fig.II(b), Fig.I(c) - Fig.II(d)
-W W (d) Fig.I(b) - Fig.II(c), Fig.I(b) - Fig. II(d)
(2 Marks)
1. Given that the signal x(t) is a band-limited signal 2. A band-pass message signal has a bandwidth of
such that X( jw ) = 0, w > 500 Hz. Find the 1000 Hz and an upper frequency limit of 2500 Hz,
Nyquist rate for the signal x2(t) in kHz. then the signal can be recovered from the sampled
(2 Marks) signal by band-pass filtering if sampling rate in Hz
is equal or greater than x. Find the value of x.
(2 Marks)
1. (b) The signal x(t) in statement S1 is not a band- statement S2 is bandlimited to w0. Therefore, it
limited signal. Therefore, it cannot undergo impulse- can undergo impulse-train sampling without alias-
train sampling without aliasing. The signal x(t) in ing provided that the sampling frequency is 2w0.

2. (a) The following figure shows the Fourier trans- p/T

X( jw ) dw
form of a pulsed signal. 1 2
EP =
2pT
x(t) X(jf)= [t sinc(ft)] -p/T
Since, 2p/T 2w0,

FT
1 +w 0

1
X( jw ) dw
2
EP =
t f 2pT -w 0
Since the pulse-width t is increased, the width =

E
1/t of the first lobe of the spectrum is decreased. T
Hence, the increased pulse-width in the flat-top
6. (b) Let us denote the signal x(t) in generalized form
as x(t) = cos (w 0 t + q ), where w0 = 2pf0. Therefore,
sampling leads to attenuation of high frequencies
in reproduction.
1 j(w 0 t + q ) 1 -j(w 0 t +q )
3. (b) x(t) = e + e
2 2
4. (c) In the frequency domain, Y ( jw ) = X1( jw )X2 ( jw ). 1 jq jw 0 t 1 -jq -jw 0 t
Therefore, = e e + e e
2 2
Y ( jw ) = 0 for w > 2000p In frequency domain, x(t) is given by
Hence, the signal y(t) is band-limited to 1000Hz. X( jw ) = pe jq d (w - w 0 ) + pe-jq d (w + w 0 )
The Nyquist rate for y(t) is
2 2000p = 4000p
It is given that the sampling pulse train is
+
The maximum sampling period is p(t) = d (t - nT )
n =-
2 1
T= = In frequency domain, p(t) is given by
4000p 2000
= 5 10-4 s = 500 s 2p +
2pk
P ( jw ) = d w -
T k =- T
5. (d) The energy of a continuous-time signal x(t) is
given by The frequency spectrum of sampled signal xp(t) is

given by

2
E= x(t) dt + jq 2pk
- e d w -

- w 0 +

p 1 2p 2 k =- T
X p ( jw ) =

1
X( jw ) dw 2p T + -jq
2
=
2pk

2p -p d w - w 0
e +
k =- T
The energy of a discrete-time sequence x[n] is given
by The spectrum of the recovered signal xr(t) is given
by
x [n ]
2
EP = Xr(jw) = Xp(jw)H(jw)
n =-
p
It is given that T = 10-3 s. Therefore, the cut-off
j 2

1
= X(e ) d frequency of the filter is
2p -p p 10-3 = 1000p
where = wT represents the discrete-time fre- For the data given in Question 6, w0= 500p and
quency. We know that q = p/4. Therefore,
1 j + jq
X(e j ) =

X for - p p e d (w - 2p 10 k - 500p )
3
T T p k =-
X p ( jw ) =
Therefore, T +
p + e-jq d (w - 2p 103 k + 500p)
j
2 k =-

1
X d
T
EP =
2pT 2 -p Only k = 0 term is passed through the filter as the
Subtituting /T = w in the above equation, we get cut-off frequency of the filter wc = 1000p. Therefore,

Xr ( jw ) = p e jq d (w - 500p ) + e-jq d (w + 500p )

Passband
Therefore,
xr (t) = cos (2p 250t + q )
w
p
= cos 2p 250t + . 2p p 0 p 2p
4 T 2T 2T T
7. (a) Refer to the Solution of Question 6. Also, it is
given in Question 7 that w0 = 1000p and q = p/4. Therefore, it matches the spectrum shown in Fig.
Therefore, II(a). For the signal shown in Fig. I(b), the sam-
pling process is shown in the following figure.
+ jq
e d (w - 2p 10 k - 1000p )
3
p k =-
X p ( jw ) = Passband
T +
+ e-jq d (w - 2p 103 k + 1000p)
k =-
w
As the cut-off frequency of the filter wc = 1000p, 2p p p 0 p p 2p
the output xp(t) = 0. T T 2T 2T T T
8. (a) For the signal shown in Fig. I(a), the graph Therefore, it matches none of the graphs shown
that displays the sampling process is shown in the in Fig. II. Similar analysis can be done for signals
following figure. shown in Figs. I(c) and I(d).

1. The Nyquist rate for signal x(t) is 2. It is given that message signal bandwidth fB =
1000 Hz and upper frequency limit fu = 2500 Hz.
2wM = 2 500 Hz = 1 kHz Therefore,
fu 2500
The Fourier transform of x2(t) is = = 2.5
fB 1000
1

2p
[X(jw ) X(jw )] The Nyquist sampling rate is
Now, 2fu
fS =
1 k
[X( jw ) X( jw )] = 0 for w > 2w M
2p where k is the largest integer not exceeding
2 fu/fB. Therefore, k = 2. Hence,
Therefore, the Nyquist rate of signal x (t) is
2 2500
4wM = 4 500 Hz = 2 kHz x = fS =
2
= 2500 Hz
Ans. (2) Ans. (2500)
1. A 1 kHz sinusoidal signal is ideally sampled at 1500 sampled signal has output frequency components
samples/s and the sampled signal is passed through 1500-1000 Hz and 1500 + 1000 Hz, that is, 2.5
an ideal low-pass filter with cut-off frequency kHz and 0.5 kHz. Also, it is given that the LPF has
800Hz. The output signal has the frequency cut-off frequency of 0.8 kHz. Therefore, the output
signal has the frequency component 0.5 kHz.
(a) zero Hz (b) 0.75 kHz Ans. (c)
(c) 0.5 kHz (d) 0.25 kHz
(GATE 2004: 2 Marks) 2. A signal m(t) with bandwidth 500 Hz is first mul-
tiplied by a signal g(t) where

(-1)k d (t - 0.5 10-4 k)
Solution. It is given a 1 kHz sinusoidal signal is
g(t) =
ideally sampled at 1500 samples/s. Therefore, the
k =-

The resulting signal is then passed through an ideal state. The output is sampled at a rate ws rad/s to
low pass filter with bandwidth 1 kHz. The output obtain the final output {y(k)}. Which of the follow-
of the low-pass filter would be ing is true?
(a) d(t) (b) m(t) (a) y() is zero for all sampling frequencies ws
(c) 0 (d) m(t)d (t) (b) y() is nonzero for all sampling frequencies ws
(GATE 2006: 2 Marks) (c) y() is nonzero for ws > 2 but zero for ws < 2
(d) y() is zero for ws > 2 but nonzero for ws < 2
Solution. It is given that the signal m(t) with a
bandwidth of 500 Hz is multiplied by a signal (GATE 2009: 2 Marks)

g(t) = (1)k d (t 0.5 104 k) Solution. The given that transfer function
k =
s2 + 1
H(s) =
The following figure shows the frequency domain s2 + 2s + 1
representation of m(t)[M(jf)].
and x(t) = sin (t + 1)
M(jf)
The Laplace transform of x(t) is
es
X(s) =
f s2 + 1
-500 500 Therefore, the Laplace transform of output signal is
-4
Given that impulse train time period = 0.5 10 s. s2 + 1 es es
Therefore, sampling frequency Y (s) = =
s2 + 2s + 1 s2 + 1 s2 + 2s + 1
1
= Hz = 20 kHz
0.5 104 Therefore,
es
The following Figure (a) shows the frequency Y (s) =
(s + 1)2
domain representation of g(t) [G(jf)]. The resultant
signal is given by Taking inverse Laplace transform, we get
m(t)g(t) M ( jf ) * G( jf ) y(t) = (t + 1)e(t +1)
The following Figure (b) shows the resultant signal.
Therefore,
G(jf)
ses
y() = lim sY (s) = lim
s 0 s 0 (s + 1)2
=0
f Thus, in steady state y() remains zero for all sam-
20 kHz 20 kHz pling frequencies, ws.
(a) Ans. (a)
4. A band-limited signal with a maximum frequency of
M(jf)G(jf) 5 kHz is to be sampled. According to the sampling
theorem, the sampling frequency which is not valid is
(a) 5 kHz (b) 12 kHz
(c) 15 kHz (d) 20 kHz
20 kHz 20 kHz (GATE 2013: 1 Mark)
(b)
This signal is passed through a low-pass filter with Solution. The minimum sampling frequency is
cut-off frequency of 1 kHz. After the low-pass filter- (fS)min = 2fM
ing with fc = 1 kHz, the output is zero. Therefore,
Ans. (c) (fS )min = 2 5 103 Hz = 10 kHz
So fS 10 kHz.
3. An LTI system having transfer function
s2 + 1
and input x(t) = sin (t + 1) is in steady Hence, option (a) is not valid
s2 + 2s + 1 Ans. (a)

CHAPTER 34
LINEAR TIME-INVARIANT (LTI) SYSTEMS
This chapter discusses in detail the linear time-invariant (LTI) systems, their properties and time and frequency
response. In addition, an introduction to different types of signals and systems are discussed for better understanding
of the topic.
34.1 INTRODUCTION variable is inherently discrete. It is generally denoted

as x[n], where n can take integer values. Discrete-time
signals are obtained by sampling the continuous-time
34.1.1 Signals and Their Classification signals. Figure 34.1(b) shows the discrete-time signal
obtained by sampling the continuous-time signal of
Signal is a function representing a variable or a physical Fig. 34.1(a).
quantity that conveys some information.
x(t) x[n]
34.1.1.1Continuous-Time and Discrete-
Time Signals
Continuous-time signals: A continuous-time

signal represents a phenomenon for which the indepen-
dent variable is continuous [Fig. 34.1(a)]. Therefore, (t) n
these signals are defined for a continuum of values of
the independent variable. (a) (b)
Discrete-time signals: A discrete-time signal rep- Figure 34.1| (a) Continuous-time signal; (b) Discrete-
resents a phenomenon for which the independent time signal.

778 Chapter 34: Linear Time-Invariant (LTI) Systems
34.1.1.2Analog and Digital Signals A discrete-time signal x[n] is even if

x[n] = x[n] (34.6)
Analog signals are those signals that are continuously
variable, that is, they can take any value. A continuous-time signal x(t) is odd if
Digital signals are discrete-time signals that can take x(t) = x(t) (34.7)
only a finite number of values.
A discrete-time signal x[n] is odd if
34.1.1.3Periodic and Non-Periodic Signals x[n] = x[n] (34.8)
A continuous-time signal x(t) is said to be periodic if 34.1.1.5Energy and Power Signals

there is a positive value of T for which Eq. (34.1) holds
true for all values of t For a continuous-time signal x(t), the normalized energy
content E is defined as
x(t) = x(t +T) (34.1)

2
E= x(t) dt (34.9)
The smallest value of T is referred to as the fundamental
period of signal x(t). Now,
For a discrete-time signal x[n], the normalized energy
x(t) = x(t +mT) (34.2) content E is defined as
+

2
where m is an integer. A discrete time signal x[n] is peri- E= x[n ] (34.10)
odic with period N if there is a positive integer N for n =
which Eq. (34.3) holds true for all values of n:
For a continuous-time signal x(t), the normalized aver-
x[n] = x[n + N] (34.3) age power content P is defined as
T /2
1 2
The smallest positive value of N for which the Eq. (34.3) P = lim
T T
x(t) dt (34.11)
holds true is referred to as the fundamental period. Also, T /2
x[n] = x[n + mN] (34.4) For a discrete-time signal x[n], the normalized average
power content P is defined as
where m is an integer. +

1 2
P = lim x[n ] (34.12)
Non-periodic signals are those signals that donot repeat N 2N + 1
n =
themselves in a finite period of time
A continuous-time signal x(t) or a discrete-time signal
x[n] is said to be energy signal if its normalized energy
34.1.1.4Deterministic and Random Signals
content E is between zero and infinity, that is, 0 < E < .
Therefore, its normalized average power P is equal
Deterministic signal is a signal whose values are com-
to zero.
pletely specified for any given time.
A continuous-time signal x(t) or a discrete-time signal
Random signal is a signal that takes random
x[n] is said to be power signal if its average power con-
values at a given time and must be characterized
tent P is between zero and infinity, that is, 0 < P < .
statistically.
Therefore, its normalized energy content E is infinite.
Periodic signals are power signals if their energy content
34.1.1.5Even and Odd Signals per period is finite.
A signal is referred to as an even signal if it is identical

to its time-reversed counterpart around the origin. A
34.1.2 Basic Continuous-Time and
continuous-time signal x(t) is even if Discrete-Time Signals
Table 34.1 enumerates the basic continuous-time and

x(t) = x(t) (34.5) discrete-time signals.

34.1 INTRODUCTION 779
Table 34.1|

Anil Kumar Maini, Varsha Agrawal, Nakul Maini-Wiley Acing The GATE Examination For Electronics and Communication Engineering-Wiley

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Anil Kumar Maini, Varsha Agrawal, Nakul Maini-Wiley Acing The GATE Examination For Electronics and Communication Engineering-Wiley

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WILEY ACING THE GATE

ELECTRONICS AND COMMUNICATION ENGINEERING

Dr Anil Kumar Maini

Other Wiley Editorial Offices:

First Edition: 2015

Dedicated to my loving mom, Mrs Kussum Agrawal

In the memory of my grandparents for their countless blessings

FM.indd 5 6/30/2015 1:23:52 PM

FM.indd 7 6/30/2015 1:23:52 PM

FM.indd 8 6/30/2015 1:23:52 PM

FM.indd 9 6/30/2015 1:23:52 PM

ABOUT GATE EXAMINATION

Admission to Higher Learning Courses

FM.indd 11 6/30/2015 1:23:52 PM

Jobs in Public Sector Undertakings

APPLYING FOR THE EXAMINATION

FM.indd 12 6/30/2015 1:23:52 PM

STRUCTURE OF THE EXAMINATION

UNDERSTANDING GATE RELATED INFORMATION

FM.indd 13 6/30/2015 1:23:53 PM

Post-Examination (Normalization of GATE score)

ATTRIBUTES FOR SUCCESS IN GATE EXAMINATION

Preparing for the Examination

Knowing Your Subject

FM.indd 14 6/30/2015 1:23:53 PM

Preparation of a Study Plan

Refining Problem-Solving Skills

FM.indd 15 6/30/2015 1:23:53 PM

Taking the Examination

Effective Approach to Attempting Questions and Time Management

Maximize your Exam-taking Efficiency

FM.indd 16 6/30/2015 1:23:53 PM

Transform Theory: Fourier transform, Laplace transform, z-transform.

ELECTRONICS AND COMMUNICATION ENGINEERING

FM.indd 17 6/30/2015 1:23:53 PM

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2 Nodal and Mesh Analysis 13

2.1 Kirchhoffs Circuit Laws 13

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2.2.1 Resistors in Series 13

3.1 Superposition Theorem 35

4 Steady-State Sinusoidal Analysis 63

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5.1 Time Domain Analysis of RLC Circuits 83

6 Two-Port Networks 107

6.1 Introduction 107

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7 State Equations for Networks 131

7.1 Network Functions 131

PART II: ELECTRONIC DEVICES 145

8 Semiconductor Physics 147

9 Semiconductor Diodes 169

9.1 PN Junction 169

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9.5 Diode Junction Capacitance 175

10 BJTs and FETs 201

10.1 Transistor Construction and Types 201

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10.9 Dual-Gate MOSFET 220

11 Laser Basics 241

11.1 Introduction 241

12 Device Technology 253

12.1 Integrated Circuits 253

2 Nodal and Mesh Analysis 13

2.1 Kirchhoffs Circuit Laws 13

2.2.1 Resistors in Series 13

3.1 Superposition Theorem 35

4 Steady-State Sinusoidal Analysis 63

5.1 Time Domain Analysis of RLC Circuits 83

6 Two-Port Networks 107

6.1 Introduction 107

7 State Equations for Networks 131

7.1 Network Functions 131

PART II: ELECTRONIC DEVICES 145

8 Semiconductor Physics 147

9 Semiconductor Diodes 169

9.1 PN Junction 169

9.5 Diode Junction Capacitance 175

10 BJTs and FETs 201

10.1 Transistor Construction and Types 201

10.9 Dual-Gate MOSFET 220

11 Laser Basics 241

11.1 Introduction 241

12 Device Technology 253

12.1 Integrated Circuits 253

12.3.2 P-Well CMOS Process 256

PART III: ANALOG CIRCUITS 259

13 Small Signal Equivalent Circuits 261

13.1 Diodes 261

14 Simple Diode Circuits 273

14.1 Connecting Diodes in Series 273

15 Biasing and Bias Stability 297

15.1 BJT Amplifiers 297

15.1.2 Common Base Configuration 300

16.1 Amplifiers An Introduction 327

16.8 Feedback in Amplifiers 341

17 Frequency Response of Amplifiers 375

17.1 Low-Frequency Response of BJT Amplifiers 375

18 Simple Opamp Circuits 403

18.1 Inverting Amplifier 403

18.7 Integrator 406

19.1 Passive Low-Pass Filters 447

20 Sinusoidal Oscillators 453

20.1 Conditions for Oscillations Barkhausen Criterion 453

20.3 LC Oscillators 457

21 Function Generators and Wave-Shaping Circuits 469

21.1 Multivibrators 469

22 Power Supplies 485

22.1 Constituents of a Linear Power Supply 485

22.5.3 Forward Converter 494

PART IV: DIGITAL ELECTRONICS 511

23 Boolean algebra 513

23.1 Number Systems 513

23.9.3 Canonical Form of Boolean Expressions 525

24 Logic Gates and Logic Families 541

24.1 Positive and Negative Logic 541

24.8.6 BiCMOS Logic 560

25 Combinational Circuits 571

25.1 Arithmetic Circuits 571

26 Sequential Circuits 601

26.1 Multivibrator 601

26.2 R-S (Reset and Set) FlipFlop 606

27 D/A and A/D Converters 643

27.1 D/A Converters 643

27.2.2 Accuracy 645

28 Microprocessors and Memory Devices 663

28.1 Introduction to Microprocessors 663

28.4.5 Indexed Addressing Mode 670

PART V: SIGNALS AND SYSTEMS 703

29 Laplace Transform 705

29.1 Introduction 705

29.3.3 System Functions for Interconnections of LTI Systems 709

30 Continuous-Time and Discrete-Time Fourier Series 719

30.1 Fourier Series Representation of Continuous-Time Periodic Signals 719

31 Continuous-Time and Discrete-Time Fourier Transform 729

31.1 Continuous-Time Fourier Transform 729

32.1 z-Transform and Inverse z-Transform 753

32.4 Unilateral z-Transform 756

33 Sampling Theorem 769

33.1 Sampling Theorem 769

34 Linear Time-Invariant (LTI) Systems 777

34.1 Introduction 777