What is JTAG

 Joint Test Action Group

 Boundary-Scan formally known as IEEE/ANSI 1149.1 or 1149.4 standard with set of rules to transform
extremely difficult PCB testing problems that could only be dealt with Ad-Hoc testing methods to well-
structured problems that software can easily & swiftly deal with.
 This testing is done using ATE (Automatic tester Equipment)
 It is important that the rules of this standard be strictly obeyed, and that the details of how a given IC has
Boundary-Scan implemented be described with complete accuracy.
 The suffix on the name of the standard indicates the year of issue or re-issue.

Faults
 Faults are an abstraction. Most popular is single Stuck-At fault model, considering multiple Stuck-At is
explosively combinatorial. Thus “all faults” means all faults that are practical to consider.

IEEE 1149.1 is a testing standard that is a collection of design rules, that are applied at IC level. The standard is
intended to have impact at several points in the life cycle of a product.
 At IC level, it facilitates IC testing & direct support for Built-In-Self-Test (Self Testing).
 At PCB level, it facilitates board testing that includes bench testing of prototype boards, production testing,
and support emulation functions.
 At module or system level, it supports testing of higher level assemblies from modules and boxes to full
systems. This standard may also co-operate with other standards like 1149.5.

The dedicated four (optionally five) non-sharable boundary scan pins of TAP (Test Access Port) that use a simple
protocol to communicate with the on-chip boundary scan logic are:
 TCK – Test Clock
 TMS – Test Mode Select (the TAP controller is driven by TCK & TMS)
 TDI – Test Data In
 TDO – Test Data Out
 TRST – Test Reset (optional pin)
The standard requires TMS, TDI, TRST to float high if unconnected to enhance system reliability & permit fail safe
operation.
This is done using internal pull-ups. The quiescent current consumption of CMOS ICs impacts IDDQ testing if not
done.

Two boundary scan data registers that are required to be present on an 1149.1 component are Bypass Register &
the Boundary Register.

TAP is a FSM with 16 states, whose transition occurs only on the rising edge of TCK or asynchronously with the
assertion of TRST if it exists.
An assertion of TRST will always send the state machine to reset state asynchronously.
Five continuous cycles of TCK with TMS held high will send the state machine to reset synchronously, regardless of
its current position in the diagram.
All the state transitions happen on the rising edge of TCK (validated by the state of TMS). The falling edge of TCK
does not cause state transitions, but cause other actions within the architecture.
TEST-LOGIC-RESET – This is the reset state of the FSM, where the test logic is disabled & normal operation of the
IC can proceed unhindered. In this state, the Instruction Register is initialized to contain IDCODE instruction if the
component contains a Device ID or Bypass instruction if it does not contain Device ID.
Regardless of the controllers state, it enters Test-Logic-Reset state with TMS held high for five continuous
cycles of TCK ( or asynchronous assertion of TRST).
RUN-TEST-IDLE – The controller remains in this state as long as TMS is held low. In this state, activity in selected
test logic occurs only when certain instructions are present. RUNBIST or Self-tests selected by other instructions can
be designed to execute in this state.
SELECT-DR-STATE –This is a temporary controller state that will be exited on the next rising edge of TCK. If TMS is
held low, it enters Capture-DR state & a scan sequence is initiated for the select test data registers. If TMS is held
high, it moves to Select-IR-Scan state.
SELECT-IR-STATE –This is a temporary controller state that will be exited on the next rising edge of TCK. If TMS is
held low, it enters Capture-IR state & a scan sequence is initiated for the Instruction registers. If TMS is held high, it
returns to Test-Logic-Reset state.
CAPTURE-IR – In this controller state, the Instruction Register parallel loads instruction on the rising edge of TCK,
whose least significant bits are “01”, while higher-order bits are design specific. The controller enters Shift-IR state if
TMS is low & Exit1-IR state if TMS is high.
SHIFT-IR – In this controller state, the Instruction Register is connected between TDI & TDO and shifts on each
rising edge of TCK. The captured pattern is shifted out via TDO & new pattern is shifted in via TDI. The controller
enters Exit1-IR if TMS is high & remains in Shift-IR if TMS is low.
 It is possible to return to Shift-IR by passing to Exit1-IR, Pause-IR, & Exit2-IR states. If an external
controller is loading instruction bits with insufficient memory depth to complete entire shift sequence in one burst, it
can be broken to manageable pieces by passing to Pause-IR while next portion of shift is prepared.
EXIT1-IR – This is a temporary controller state & enters Pause-IR if TMS is held low & Update-IR if TMS is held high.
PAUSE-IR – This controller state allows shifting of Instruction Register to be temporarily halted. The controller
remains in this state if TMS is held low or enters Exit2-IR if TMS is held high.
EXIT2-IR – This is a temporary controller state & enters Update-IR if TMS is held high or Shift-IR if TMS is held low.
UPDATE-IR – In this state, the instruction previously shifted into the Instruction Register is latched on the falling edge
of TCK, by the hold portion the IR, thus setting a new operational mode. The controller enters Run-Test-Idle if TMS is
held low & Select-DR-Scan if TMS is held high.
CAPTURE-DR – In this controller state, data can be parallel loaded into the shift portion of the test data register
selected by the current instruction on the rising edge of TCK. It enters Exit1-DR if TMS is held high & Shift-DR if TMS
is held low.
SHIFT-DR – In this controller state, the test data register is connected between TDI & TDO and shifts on each rising
edge of TCK. The captured data is shifted out via TDO & new data is shifted in via TDI. The controller enters Exit1-
DR if TMS is high & remains in Shift-DR if TMS is low.
It is possible to return to Shift-DR by passing to Exit1-DR, Pause-DR, & Exit2-DR states. If an external
controller is loading data bits with insufficient memory depth to complete entire shift sequence in one burst, it can be
broken to manageable pieces by passing to Pause-DR while next portion of shift is prepared.
EXIT1-DR – This is a temporary controller state & enters Pause-DR if TMS is held low & Update-DR if TMS is held
high.
PAUSE-DR – This controller state allows shifting of data between TDI & TDO to be temporarily halted. The controller
remains in this state if TMS is held low or enters Exit2-DR if TMS is held high.
EXIT2-DR – This is a temporary controller state & enters Update-DR if TMS is held high or Shift-DR if TMS is held
low.
UPDATE-DR – In this state, data is latched on the falling edge of TCK, onto the parallel outputs of these test data
registers from shift register path. The controller enters Run-Test-Idle if TMS is held low & Select-DR-Scan if TMS is
held high.

Registers are constructed with dual ranks, a shiftable part & a hold part to prevent rippling during shift, from being
visible to the downstream logic. Register is selected or shifted means shift portion of it which is connected between
TDI & TDO.

Two shift states SHIFT-IR & SHIFT-DR activates the output driver for TDO & remains active until the falling edge of
EXIT1-IR or EXIT1-DR respectively. All other times the TDO driver is turned off (high impedance state)

The write operation using UPDATE-IR or UPDATE-DR happens only on the falling edge of TCK.
The read operation using CAPTURE-IR or CAPTURE-DR happens only on the rising edge of TCK. Paired with the
write operation of updating, these two operations allow Boundary-scan circuit to write data & later read it in no fewer
than 2.5 cycles.
No data is shifted by the rising edge of TCK that first brings the TAP controller into shift state from either Capture-
DR/IR.

The Instruction Register defines the mode in which Boundary-Scan data registers will operate. It is composed of a
shift rank & a parallel hold rank. The shift rank can be loaded in parallel at Capture-IR, shifted between TDI & TDO at
Shift-IR, and the contents of the shift rank are transferred to hold rank at Update-IR
#shift rank – edge triggered flip flop
#parallel hold rank – output latch
The minimum size of the Instruction Register is two cells. The size of the register dictates the size of the instruction
codes that can be used: code size must match the length of the register.

The Instruction Register operation during each TAP controller state

A sample Instruction Register cell

The pins labeled Clock-IR are derived from TCK and clock shift-register flip flop for capturing and shifting data. The
pins labeled Update-IR are derived from negated TCK and clocks the update latch for updating the hold rank of the
Instruction Register.

BYPASS-REGISTER – The Bypass Register is a simple register that does not require a parallel hold rank. This
register consists of only one scan cell. When selected by the BYPASS instruction, it shortens the shift path within an
IC to a single cell, thus reducing the shift time.
When TAP passes thru Capture-DR, it captures a fixed binary “0” which is subsequently shifted out.

A typical Boundary-Register cell

Boundary Register has a boundary scan cell adjacent to each digital system input & output pins (except the TAP
pins). This register is used to control & observe activities on the IC’s input & output pins.
A Bi-directional pin served by a reversible Boundary register cell
In this cell you will notice that it can monitor the output pin when the driver is enabled. This allows the state of the pin
to be sensed while driver is driving it. This important function is missing in BC_6 cell (flawed cell, which is improved in
BC_7)

Two logical symbols for typical boundary cells, one with Update latch (UPD) & the other without UPD.
First one is a regular Boundary scan cell, while the second one is an observe only cell that does not have an UPD
latch.
A paper by Lee Whetsel (Whet95) shows how designing by rules rather than the figures can lead to some
fundamental optimizations.
This design is essentially the same regular Boundary-Register for the CAP portion of the cell, but differs quite a bit for
the UPD portion of the cell. Here the insertion delay of the output multiplexer is fixed by replacing with two FET
switches S1 & S2. These switches are controlled by new signals DC & UC from TAP controller, replacing Update-DR
& Mode. You can notice that adding a weak feedback buffer FB on the output buffer converts it into a latch that
serves the purpose of UPD latch.

Block diagram of a Boundary Scan IC

There are four major pieces of Boundary Scan Architecture.
1. TAP controller consisting of 16-state state machine, which is actually a cascade of three simple
state machines.
2. Instruction register & its decode logic.
3. Data registers.
3.1. Boundary Register surrounding the system logic.
From the figure, you can observe that the TDO is synchronized by an additional register stage clocked by falling edge
of TCK. This ensures that all transitions on TDO occur ½ TCK cycle after TDI bits are read in.

Boundary scan ICs are designed to link together into simple chains with common TCK & TMS, and with their shift
paths linked together by connecting a TDO pin of one IC to the TDI pin of the following IC.
In some cases Boundary scan ICs are connected to conventional ICs. In such cases boundary scan registers can be
used to setup logic values necessary for testing conventional ICs.
An important property of simple chains is that, because of the commonality of TCK & TMS, every TAP of every IC in
the chain is always in the same state ensuring to keep track of the state of the entire chain.
Multiple simple chains could exist on a board (or in a system) where no TAP signals are shared between them. Any
parallel system signals shared between ICs of separate chains can be tested, but we now have to coordinate the
operation of multiple chains.
JTAG has two major modes of operation
 Non-Invasive – The TAP controller & four (optionally five) TAP pins may be operated asynchronously &
independently of the system logic. This allows the Boundary-Scan TAP to be used without disturbing the
normal operation of a chip, board or system. These activities are invisible to the normal behavior of IC.
Wake-up  Non-Invasive mode
 Pin-Permission – The standard specifies instruction modes of operation that can usurp the control of
input/output (I/O) pins of the IC, effectively disconnecting the ICs system logic from the outside world. These
modes allow the testing of ICs system logic or its isolation from testing activities taking place at its pins.
It is important that the system logic not be harmed by this radical change of configuration.

NON INVASIVE OPERATIONAL MODES

 BYPASS – This instruction places the single bit BYPASS data register between TDI & TDO to produce a
short 1-bit shift path through a component, and for the component to be operating normally.
The bypass register is parallel loaded with “0” upon passing to Capture-DR & initializes the register with a
known, predictable data.
 IDCODE – This instruction places the 32-bit Device Identification Register between TDI &TDO that contains
the identification code.

 USERCODE – This instruction places 32-bit user defined Device Identification Register between TDI & TDO
similar to IDCODE in cases where IDCODE alone is insufficient for identifying the IC & its programming.
 SAMPLE – This is the first instruction to target Boundary Register between TDI & TDO. SAMPLE
functionality occurs upon passing thru the Capture-DR TAP state. All the capture flops (CAP) loads the state
of the signals they are attached to; IC inputs or System logic signals destined for IC outputs.
The Boundary register takes the snapshot of the activity of the ICs I/O pins during SAMPLE
instruction.
SAMPLE – Capture-DR state
  PRELOAD – This instruction targets Boundary Register between TDI & TDO, while it does not disconnect
the system logic from the IC pins. The PRELOAD function initializes the CAP flops of the Boundary
Register. The data received at the CAP flops is then transferred to the UPD flops upon passing thru the
Update-DR TAP state.
The PRELOAD function allows us to have proper data setup before this switching takes place.
PRELOAD – Update-DR state

The bit pattern of all 1’s in the instruction register must decode to BYPASS instruction. The standard also states that
all unused instruction codes not declared to be private must also decode to BYPASS.

The LSB of any IDCODE needs to be 1 to be identified as IDCODE.

In TEST-LOGIC-RESET state, the instruction register is jammed with either BYPASS or IDCODE. In this state, the
data shifting via Capture-DR shifts out “0” for BYPASS or “1” for IDCODE in the first shift.

The PRELOAD instruction has no requirement for what is captured in the CAP flops when TAP passes thru Capture-
DR state. This allows the functionality of PRELOAD to be merged with the functionality of SAMPLE such that the two
instructions consume only one instruction bit pattern.

PIN-PERMISSION OPERATIONAL MODES

 EXTEST – During this instruction, we can sample the inputs & control the outputs of the IC pins. Shifting the
Boundary Register during Shift-DR allows us to read out the captured input states & to setup new output &
output enable states that will become effective upon passing thru Update-DR.
 INTEST – This is an inward looking instruction putting the system logic inputs under the control of the UPD
flops of the Boundary Register input cells. The Boundary Register cells connected to system logic outputs &
output enables sample the states produced by the system logic at Capture-DR.
Thus at Update-DR, a test pattern can be applied to system logic inputs and at Capture-DR, the
results of that pattern can be captured.
 RUNBIST – This instruction is to provide users of an IC access to internal built-in self-tests with a
standardized access protocol.
 HIGHZ – This instruction targets the Bypass Register between TDI & TDO, to shorten the shift path. It also
causes all the output & bi-directional pins to go to high-Z state.
 CLAMP – This instruction targets the Bypass Register between TDI & TDO to shorten the shift path & place
all the output & bi-directional pins under the control of the Boundary Registers, which should be setup
before hand with a PRELOAD sequence. This becomes effective at Update-DR.

In INTEST mode, the states driven to the component output pins are driven in one of the two ways, which should be
applied uniformly to all the IC pins.
1. They may be under the control of the Boundary Register so that they can be held at deterministic values
while the system logic is tested.
2. Place all the outputs in a disabled, non-driving state .

One major problem with the INTEST IC testing is that it is serialized & delivered via the TAP port. It is possible for the
apparent testing rate to be greatly reduced, by factors of hundreds, which is proportional to the length of Boundary
Registers & any other bits contributed by other ICs in a chain.

The RUNBIST runs when the TAP is placed in the RUN-TEST-IDLE state.

The CLAMP function can be accomplished by putting the IC in EXTEST, but boundary register would then be in shift
path (lengthening it) & it would have to have its clamp values reinstated on every new shifting cycle.
CLAMP is intended for digital guarding while testing a board.

For extremely performance sensitive component inputs, “observe-only” Boundary Register cells are used.

The Bypass-Register relation with each known instruction.

Instruction Register Selected
EXTEST Boundary Scan Register
SAMPLE/PRELOAD Boundary Scan Register
IDCODE ID Register
CLAMP Bypass Register
HIGHZ Bypass Register
BYPASS Bypass Register
Not Assigned Bypass Register

EXTENSIBILITY – A powerful feature of the 1149.1 standard is its extensibility. The architecture can be extended two
ways; by adding user-defined instructions & user-defined registers.

BSDL – Boundary Scan Description Language

VHDL is the foundation language specification for BSDL.
BSDL is not a general purpose hardware description language. It is not a model & does not provide architectural,
structural or detailed design information about an 1149.1 implementation.
BSDL allows the description of testability features in components that comply with IEEE 1149.1 standard. BSDL will
match the implementation of 1149.1 circuitry.
The process of writing BSDL can uncover errors in the implementation of 1149.1 circuitry. For example, if
System Logic is illegally placed between the Boundary Register Cells & the IO pins, it will not be possible to describe
this configuration within BSDL.
After a BSDL description is written, it may be checked by a program that looks for specific requirements to
be met for component to be in compliance. For example, it might check that the TAP Instruction Register captures a
valid pattern at Capture-IR as laid out by the standard.
Boundary Register cell that does not support INTEST when INTEST was listed as one of the
instruction the TAP will decode.

A process for checking the compliance of an IC with the standard

The entire body of BSDL contains a set of mandatory & some optional statements (optional statements are shown
between { })
entity <component name> is
<generic parameter>
<logical port description>
<standard use statement>
{<use statements>}
<component conformance statement>
<device package pin mappings>
{<grouped port identification>}
<scan port identification>
{<compliance enable description>}
<instruction register description>
{<optional register description>}
{<register access description>}
<boundary-scan register description>
{<RUNBIST description>}
{<INTEST description>}
{<BSDL extensions>}
{<design warning>}
end <component name>;
ENTITY DESCRIPTIONS – The entity statement starts with an entity statement & terminates with an end statement.
Typically the name of the component/chip is placed here.
entity ttl74bct8374 is
{BSDL statements to describe the entity}
end ttl74bct8374;
Generic Parameter – The generic parameter is a parameter that may be filled by a call from the outside world, or it
may be defaulted. In BSDL, the generic is a string with the name PHYSICAL_PIN_MAP, whose value must be
assigned for future reference.
generic (PHYSICAL_PIN_MAP : string := "DEFAULT_PACKAGE_NAME");
Logical Port Description – The logical port description gives logical names to the IO pins and denotes their nature
such as input, output, bidirectional and so on. Non digital signals such as Power, Ground, no-connects or analog are
labeled as linkage.
port (CLK:in bit;
Q:out bit_vector(1 to 8);
D:in bit_vector(1 to 8);
GND, VCC:linkage bit;
OC_NEG:in bit;
TDO:out bit;
TMS, TDI, TCK:in bit);
Standard Use Statement – The standard use statement refers to external definitions found in packages & package
bodies. This must appear in any BSDL before other use statement.
use STD_1149_1_2001.all; -- Get Std 1149.1-2001 definitions
Use Statement – Use statements are optional and more than one may be added. If a designer were to invent new
cell definitions, these could be placed in a new package and referenced with a use statement.
use MY_NEW_CELLS.all; -- Get new Boundary Register Cell info
Component Conformance Statement – The component conformance statement identifies the release of the standard
that was used to design the 1149.1 circuitry within an IC. This allows the end users to identify what features may be
present in the implementation.
attribute COMPONENT_CONFORMANCE of kincardine: entity is "STD_1149_1_2001";
Device Package Pin Mappings – As mentioned in the discussion on generic parameters, we can describe the
mapping of package pins to logical names from port descriptions. Further BSDL can describe the multiplicity of
mappings with VHDL attribute “constant”.
attribute PIN_MAP of ttl74bct8374:entity is PHYSICAL_PIN_MAP;
constant DW:PIN_MAP_STRING: =
"CLK:1, Q:(2,3,4,5,7,8,9,10), " &
"D:(23,22,21,20,19,17,16,15), " &
"GND:6, VCC:18, OC_NEG:24," &
"TDO:11, TMS:12, TCK:13, TDI:14";
constant FK:PIN_MAP_STRING:=
"CLK:9, Q:(10,11,12,13,16,17,18,19)," &
"D: (6,5,4,3,2,27,26,25) ," &
"GND:14, VCC:28, OC_NEG:7," &
"TDO:20, TMS:21, TCK:23, TDI:24";
Grouped Port Identification – The grouped port identification is optional & used to identify the system pins that have
the special property of using more than one pin to carry a bit of data. Differential signaling is the most common
example.
attribute PORT_GROUPING of Diff_IC:entity is
"Differential_Voltage((Q_Pos(1), Q_Neg(1)), " &
"(Q_Pos(2), Q_Neg(2)), " &
"(Q_Pos(3), Q_Neg(3)), " &
"(Q_Pos(4), Q_Neg(4))), " &
"Differential_Current ((D_Pos(1), D_Neg(1)), " &
"(D_Pos(2), D_Neg(2)), " &
"(D_Pos(3), D_Neg(3)), " &
"(D_Pos(4), D_Neg(4))) ";
TAP Port Identification – The TAP port identification section assigns special meaning to the four (optionally five) TAP
pins.
 attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TMS : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6, BOTH);
attribute TAP_SCAN_RESET of TRST : signal is true; -- optional TRST pin
Compliance Enable Description – This optional section contains compliance enable pins that must be held at static
logic states before any 1149.1 activities are attempted on an IC, and maintained until the completion of these
activities..
attribute COMPLIANCE_PATTERNS of Annex_A_Chip : entity is
"(LSSD_A, LSSD_B, LSSD_P, LSSD_C1, LSSD_C2) (00011)";
Instruction Register Description – The next major piece of information required in a BSDL description covers the
mandatory, optional and user-defined (both public & private) TAP instructions & their associate registers
implemented by the IC’s 1149.1 circuitry.
attribute INSTRUCTION_LENGTH of ttl74bct8374 : entity is 8;

attribute INSTRUCTION_OPCODE of ttl74bct8374 : entity is

"BYPASS (11111111, 10001000, 00000101, 00000001)," &
"EXTEST (00000000, 10000000)," &
"SAMPLE (00000010, 10000010), " &
"PRELOAD (00000010, 10000010), " &
"INTEST (00000011, 10000011) ," &
"TRIBYP (00000110, 10000110) ," & -- Boundary Hi-Z
"SETBYP (00000111, 10000111) ," & -- Boundary 1/0
"RUNT (00001001, 10001001), " & -- Boundary run test
"READBN (00001010, 10001010) ," & -- Boundary read normal
"READBT (00001011, 10001011) ," & -- Boundary read test
"CELLTST (00001100, 10001100) ," & -- Boundary self test
"TOPHIP (00001101, 10001101), " & -- Boundary toggle test
"SCANCN (00001110, 10001110) ," & -- Boundary Scan normal
"SCANCT (00001111, 10001111) "; -- Boundary Scan test
attribute INSTRUCTION_CAPTURE of ttl74bct8374 : entity is
"10000001";

attribute INSTRUCTION_PRIVATE of ttl74bct8374: entity is

"CELLTST";
Optional Register Description – They identify the content of the Device Identification Register after passing thru
Capture-DR when the IDCODE or USERCODE instructions are loaded, if they exist for the component.

Register Access Description – The optional attribute REGISTER_ACCESS is used to show how user defined
instructions interact with data registers. These data registers will be placed between TDI & TDO when the instruction
becomes effective at Update-IR.

Boundary-Scan Register Description – The description of Boundary Register contains data description of every cell in
the register. Two attributes makeup the description.
First attribute is BOUNDARY_LENGTH. The length of this register is greater than zero.
 The second attribute is BOUNDARY_REGISTER which is an array of data records. The array
contains four or seven fields. The first four remains the same. The rest three fields give information for cells devoted
to IC outputs, regarding how those are disabled.

RUNBIST Execution Description – An optional RUNBIST instruction must run for some length of time in the RUN-
TEST/IDLE state, governed by the passage of time or some number of clock cycles. The outputs & bidirectional pins
takes on states defined by Boundary Register, which should be initialized by a PRELOAD, before RUNBIST is
executed. The test results of RUNBIST will be found in the target register of RUNBIST, listed in
REGISTER_ACCESS attribute appearing in the BSDL description.
attribute RUNBIST_EXECUTION of BIST_IC : entity is
"ait_Duration (1. 0e-4) ," -- Duration of test
"Observing HIGHZ At_Pins," -- Condition of Output pins
"Expect_Data 0011001"; -- Result of passing test
INTEST Execution Description – This is optional. The actual patterns that would apply via INTEST must come from
an external source such as design verification tests for an IC. BSDL does not provide a means of describing these
patterns. The INTEST_EXECUTION attribute documents the details on how such patterns should be applied.
attribute INTEST_EXECUTION of INTEST_IC : entity is
"Wait_Duration (1. 0e-4) ," -- Duration of test
"Observing HIGHZ At_Pins"; -- Condition of Output pins
User Extensions to BSDL – Optional. Can be defined here if any.
Design Warnings – All the illegal or dangerous conditions to be avoided can be communicated to the user by the IC
designer thru this optional attribute DESIGN_WARNING

Normally all system signals are required to appear somewhere in the Boundary Register description. An exception is
that the “minus or negative” ports shown in a grouped port description are not required, indeed they should not
appear. Only one Boundary Register cell is associated with each differential pair.

The signals listed in compliance enable attribute cannot be scan port signals nor can they appear in subsequent
Boundary Register description.

The minimum length of Instruction Register “INSTRUCTION_LENGTH” is 2.

Boundary scan cell BC_0 serves as a minimum cell description that satisfies all rules for cell architecture but has no
additional capabilities.

The Boundary Scan Cell BC_1 is a basic cell that can be used as an input cell, an output cell, a control cell, an
internal cell & as a building block for handling bidirectional pins. This supports INTEST.

The Boundary Scan Cell BC_2 has the multiplexer placed in the signal path at the entrance of the cell from parallel
input. Thus the CAP flop can capture the contents of the UPD latch when the mode is set to 1.
This can also be used similar to BC_1, excepting that this is self testable without requiring the data to be propagated
thru system circuitry. This self testability feature makes it widely accepted Boundary Scan Cell.
The Boundary Scan Cell BC_3 is used only for inputs (or internal cells), that does not possess update latch but does
support INTEST.
One of the principal reasons for providing an update latch is to prevent the shift ripple that occurs on the output of the
capture flop while shifting data.

The Boundary Scan Cell BC_4 also does not have update latch & eliminates multiplexer from the system signal path
as well. Thus not supporting INTEST on general input pins.
This cell cannot be used on any input pin except clock pin.

The Boundary Scan Cell BC_5 is virtually identical to BC_2 except that this is used for controlling output driver
enables. The difference is due to the AND function that inserts another control variable into the signal used to turn
the driver on or off.
This is used to implement the HIGHZ instruction & the HIGHZ-type Boundary Register control feature that INTEST &
RUNBIST may exhibit as well.
The Boundary Scan Cell BC_6 is a flawed bi-directional cell discouraged by the 1149 working group.

The Boundary Scan Cell BC_7 is a single data cell that supports bidirectional system pins.
Basic Test Algorithm
Step 1: Initialize the TAP to TEST-LOGIC-RESET.
Step 2: Load the Instruction Register with the PRELOAD instruction. This puts the Boundary Register
between TDI and TDO, but does not grant pin permission.
Step 3: Shift the first stimulus pattern into the Boundary Register. This is the “preload” phase of the
algorithm.
Step 4: Load the Instruction Register with EXTEST. This puts the Boundary Register between TDI and TDO
and grants pin-permission upon passing UPDATE-IR. This applies (writes) the first stimulus pattern (PTV).
Step 5: Capture (read) the response pattern into the shift portion of the Boundary Register.
Step 6: Shift the captured response pattern out while shifting in the next stimulus pattern.
Step 7: Update (write) the next stimulus pattern.
Step 8: Have we written the last stimulus pattern? If so, go to step 9; otherwise go to step 5.
Step 9: Capture (read) the last response pattern.
Step 10: Shift in a “safe” stimulus pattern4 while shifting out the last captured response pattern.
Step 11: Update (write) the safe pattern.
Step 12: Go to TEST-LOGIC-RESET and halt the test.