EEE / INSTR F244

Microelectronic
Ci it
Circuits
BITS Pilani
Pilani Campus
p
 BITS Pilani
Pilani Campus

MOSFET AMPLIFIER
Aim
• Design an amplifier of gain 30 v/v
• Ch
Choose th
the device
d i (MOS , BJT)
• Set DC bias
• Choose a circuit topology
• Design
• Analyse
• R d i
Re-design

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MOSFET

• TRANSCONDUCTANCE
• ----defines
defines gain
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SYMBOLS

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CHOICE OF INPUT AND OUTPUT

• 3 parameters
parameters---V VGS, VDS, ID, (Vsb= for advanced course)
• ID α (VGS, VDS)
• ID---captures variation----output
• either VGS / VDS can be input
• but if VDS is input, no other terminal is
available for output
• so only VGS can be the input
• Now what should be Vds?
Where to bias ?
• Max gain-------MAX IDRD------------MAX ID
• Min distortion

• ID= f (VGS)------
) SATURATION REGION
• Max current, ID captures variations of VGS
f ithf ll
faithfully
• ID= f (VGS, VDS)-----------LINEAR REGION
• Min current, ID varies with VGS , VDS ---
(extra variation)

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MOS equations
Transfer charac.

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Output charac.—load line

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MOS AMPLIFIER

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DC BIAS

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Understanding MOS

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MODEL

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SECONDARY EFFECTS

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CHANNEL LENGTH MODULATION

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ID increases with VDS
MODIFIED MODEL & equ

I D  K ' VGS  VT 0  1  VDS 

W 2

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BODY BIAS EFFECT

• VT= VTO +γ [(2ΦF + VSB) ½ – (2ΦF)½ ]

2qN A s
 
C ox
I D  K ' VGS  VT  1  VDS 
W 2

ID reduces
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Impact of body bias
Id Vsb1 Vsb2 Vsb3

Vt1 Vt2 Vt3

Vgs

Vsb1< Vsb2 < Vsb3

Temperature effects
• Vt, K’ , µ  are temperature sensitive
• Vt reduces
d att a rate
t off 2mv
2 per degree
d rise
i
in temp.

• Breakdown---
• Oxide breakdown, punch through

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CIRCUIT SYMBOLS AND CONVENTIONS
SUMMARY OF BJT-CURRENT VOLTAGE
RELATIONSHIPS
O S S IN ACTIVE
C MODE
O
ic – vBE CHARACTERISTICS FOR NPN

As in silicon diodes, the voltage across the EBJ

decreases by about 2mV for each degree rise of
t
temperature.
t
Fig. 4.14 The iC-vCB characteristics for an npn transistor in
the active mode.
Ic--Vcb
Fig. 4.15 (a) Conceptual circuit for measuring the iC-vCE characteristics of the
BJT. (b) The iC-vCE characteristics of a practical BJT.
EARLY VOLTAGE
• At a given value of vBE, increasing vCE increases
reverse bias voltage on the CBJ
CBJ.
• This increases the width of the depletion of the
junction hence decreasing the effective base width
width.
• Is is inversely proportional to W. Hence Is increases
and ic increases.
increases This is the Early effect.
effect
• The finite slope in the ic-vCE curve in the active
region can be modeled as a finite output resistance
r0 = (δiC / vCE)-1 with vBE constant.
= VA / iC
Fig. 4.23 (a) Conceptual circuit to illustrate the operation of the transistor of an amplifier. (b) The circuit of (a)
with the signal source vbe eliminated for dc (bias) analysis.

DC CONDITIONS

IC = IS e(VBE/VT) IE=IC/α
IB=IC/β VC=VCE=VCC-ICRC
Vo=VCE=VCC    ‐ IS e(VBE/VT) RC

) IS e((VBE//VT))   RC
Av = (‐1/VT )    I
Av.=   (‐1/V

Av=    (‐IcRc/VT )   =    ‐VRC/VT
SMALL SIG. OPERATION

• iC= IS e (vBE/VT)

• =IS e (VBE+v be/VT)

• =IC e (vbe/VT)

• If Vbe <<V
T small sig. Approx.

• iC=IC (`1+vbe/VT)= IC+ IC vbe / VT

• = gm vbe
HYBRID - ∏ MODEL

Fig. 4.26 Two slightly different versions of the simplified hybrid- model for the small-signal
operation of the BJT. The equivalent circuit in (a) represents the BJT as a voltage-controlled
current source ( a transconductance amplifier) and that in (b) represents the BJT as a current-
controlled current source (a current amplifier).
BITS Pilani, Pilani Campus
 BITS Pilani
Pilani Campus

BIPOLAR JUNCTION TRANSISTORS

 NPN TRANSISTOR

Fig. 4.1 A simplified structure of the npn transistor.

 PNP TRANSISTOR

Fig. 4.2 A simplified structure of the pnp transistor.

 BJT MODES OF OPERATION

Different modes of operation based on bias condition

of the two p-n junctions.

Mode EBJ CBJ

Cut Off Reverse Reverse

Active
A ti Forward
F d Reverse
R
Reverse active Reverse Forward
Saturation Forward Forward
 CURRENT FLOW IN NPN

Fig. 4.3 Current flow in an npn transistor biased to operate in the active mode, (Reverse current components due to drift of thermally
generated minority carriers are not shown.)
Techniques to set DC bias--DISCRETE CKT.

• Using two supply voltages or generate VGS

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STABILITY OF Q POINT– FIX VGS

Vt reduces at high temperature

Vt
• Fix VG, but VS can adjust. ID rolls back
• Using degeneration resistance

VG  VGS  I D RS
Id

Q’
Id2
Q
Id1

-1/Rs

Vt1 Vgs1
Vt2 Vgs
Using single DC supply

• POTENTIAL DIVIDER BIAS

VG  VGS  I D RS
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Q point stability
• Case-1------Vg increases due to power
supply fluctuation
Vg↑ Vgs↑ Id↑ (Id Rs) ↑ Vgs↓

• Case-2----- VT decreases due to

temperature fluctuation
VT ↓ ( Vgs – VT )↑ Id↑ (Id Rs) ↑ Vgs↓ ( Vgs – VT ) ↓

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Setting DC BIAS

• DRAIN TO GATE FEEDBACK BIAS

VDD  VGS  I D RD

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Sensitivity
Potential divide bias–
without Rs

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With Rs

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IC BIASING—current bias

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PMOS Current Mirror

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Matched transistors— keep fab. conditions
same

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Why current biasing for ICs?

• To do away with coupling capacitors

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Why do we need coupling capacitors?

• To isolate the d
d.c
c bias voltges of two adjacent
amplifiers biased using voltage biasing technique

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GAIN EXPRESSION

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Amplifier equ.

y, x voltage or current

For a narrow range of x

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Current expression in sat. region

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Output voltage/ gain expression

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Distortion

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SMALL SIGNAL APPROX

• HOW MUCH SMALL?

• Vgs << 2Vov

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GAIN IN SATURATION REGION, IN LINEAR

• AV= - RD KN’(W/L)
(W/L) (VOV) (more)

• AV= - VDD RD KN’(W/L) / [1+ RD KN’(W/L) VOV]2

(
(less)
)

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Gain in saturation

• Av= - gm RD (effect of ro not taken into account))

• AV= - RD KN’(W/L) (VOV)

• gm = KN’ (W/L) (VOV))---trans-conductance

trans conductance

• = 2 ID/ Vov
V

• =√ [2 KN’(W/L) ID]
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gm

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SMALL SIGNAL PARAMETERS
• gm --transconductance
• ro—drain
d i resistance
i t
• gmb---body transconductance
• iD= f (vDS, vGS. VSB)

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iD= f (vDS, vGS, VSB)—Taylor approx.

iD iD iD

iD |Q  vGS  vDS  vSB
vGS vDS vSB
iD iD iD
I D  id  I D  v gs  vds  vsb
vGS vDS vSB
iD iD iD
id  [ v gs  vds  vsb ]Q
vGS vDS vSB
id  g m v gs  g d vds  g mb vsb
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Plot the graphs---do yourself
• gm vs. w/L for Id constant
• gm vs. w/L
/L ffor Vov. Constant
C t t
• gm vs. Id for Vov. Constant

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 With λ

Correction in book is required

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Model parameters

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Complete AC model

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NMOS

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PMOS

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 Converting to T model

Figure 4.39 Development of the T equivalent-circuit model for the MOSFET. For simplicity, ro has been omitted but can
be added between D and S in the T model of (d).

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How to draw AC model of amplifier?

• For amplification
amplification,
only AC behaviour
needs to be
considered

• Replace MOS by its

model in the circuit

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2 Sources in ckt.—1 ac, 1dc

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Using superposition

• Source Vdd/or
Source Ibias
voutDC  Vdd  I bias  RD
 ro 
voutDC  Vdd
 RD  ro 

• Source i voutAC  i  [ro || RD ]

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Considering only AC

voutAC  i  [ro || RD ]

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 Sensitivity of Id to Vdd fluctuation

V G  V GS  I R1=1M
R2=1M
D Rs=100
Rs ID=100umA
If Vgs constant
Vdd=3v
 R2  Kn’=140uA/v
Kn =140uA/v2

R  R   I D 
 1 2 I D 0.1 
Vdd
S
 ID

 Vdd 
Rs Vdd
If Vggs not constant

2I D
VGS  Vt 
' W  
Kn
 L 

ID
• Substitute Vgs and recalculate S VDD
Sensitivity of Id to Temp. change

 VG VGS  I D Rs

 T  T   Rs T  I D T
 

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