2.

1 LPC2103 Microcontroller
The ARM7TDMI-S is a 32-bit microcontroller based on RISC architecture. It offers
high performance for low power consumption. It uses 3 stage pipeline to increase the speed
of the flow of instruction. The 3 stages are fetch, decode and execute. During normal
operation, while one instruction is being executed, its successor is being decoded, and a third
instruction is being fetched from memory. Program Counter (PC) points to the instruction
being fetched rather than to the instruction being executed.

The ARM7TDMI-S has Von-Neumann architecture, with a single 32-bit data bus
carrying both instructions and data. Data can be 8, 16 and 32 bits length. It also supports for
16-bit THUMB architecture.

2.1.1 Features

 16/32-bit ARM7TDMI-S microcontroller in a 48 pin package.

 8kB on-chip Static RAM.
 32 kB on-chip Flash Program Memory.
 In-System Programming (ISP).
 Eight channel 10-bit A/D converter.
 Two 32-bit timers.
 Two 16-bit timers
 Serial interfaces including two UARTs, two Fast I2C,SPI and SSP.
 70 MHz maximum CPU clock available from programmable on-chip Phase-Locked
Loop.
 Two low power modes, Idle Dual power supply.
 Up to thirty two 5V tolerant general purpose I/O pins.
 CPU operating voltage range of 1.65V to 1.95V (1.8V +/- 8.3%). I/O power supply
range of 3.0V to 3.6V (3.3V +/- 10%).
 JTAG (Joint Test Action Group) support.

2.1.2 Block Diagram

2.1.3 Pin Configuration
2.1.4 Memory Organization
 The LPC2103 incorporate a 32 kB Flash memory system. This memory may be used
for both code and data storage. Programming of the Flash memory may be accomplished in
several ways - over the serial built-in JTAG interface, using In System Programming (ISP)
and UART0, or by means of In Application Programming (IAP) capabilities. The application
program, using the In Application Programming (IAP) functions, may also erase and/or
program the Flash while the application is running, allowing a great degree of flexibility for
data storage field firmware upgrades, etc.
 The LPC2103 provide a 8 kB static RAM memory that may be used for code and/or
data storage. The SRAM supports 8-bit, 16-bit, and 32-bit accesses. The SRAM controller
incorporates a write-back buffer in order to prevent CPU stalls during back-to-back writes.
The write-back buffer always holds the last data sent by software to the SRAM.

Both the AHB and VPB peripheral areas are 2 megabyte spaces which are divided up
into 128 peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying
the address decoding for each peripheral. All peripheral register addresses are word aligned
(to 32-bit boundaries) regardless of their size. This eliminates the need for byte lane mapping
hardware that would be required to allow byte (8-bit) or half-word (16-bit) accesses to occur
at smaller boundaries.

2.1.5 GPIO
 The pin connect block allows selected pins of the microcontroller to have more than
one function. Configuration registers control the multiplexers to allow connection between
the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins
prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any
enabled peripheral function that is not mapped to a related pin should be considered
undefined.

LPC2129 has two 32-bit General Purpose I/O ports. Total of 30 out of 32 pins are
available on PORT0. PORT0 and PORT1 are controlled via two groups of 4 registers as
shown.

2.1.6 UART
 LPC2103 microcontroller contains 2 UART’s. UART0 has a 16 byte receiver and
transmitter buffer FIFO’s and a built in baud rate generator.

The U0RBR is the top byte of the UART0 Rx FIFO. The top byte of the Rx FIFO
contains the oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the “oldest” received data bit. If the character received is less than 8 bits, the
unused MSBs are padded with zeroes.

The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the
U0RBR. The U0RBR is always Read Only. The UART0 Divisor Latch is part of the UART0
Baud Rate Generator and holds the value used to divide the VPB clock (pclk) in order to

produce the baud rate clock, which must be 16x the desired baud rate. The U0DLL and
U0DLM registers together form a 16 bit divisor where U0DLL contains the lower 8 bits of
the divisor and U0DLM contains the higher 8 bits of the divisor. A ‘h0000 value is treated
like a ‘h0001 value as division by zero is not allowed. The Divisor Latch Access Bit (DLAB)
in U0LCR must be one in order to access the UART0 Divisor Latches.
UART0 Receiver Buffer register (U0RBR - 0xE000 C000, when
DLAB = 0, Read Only)
The U0RBR is the top byte of the UART0 Rx FIFO. The top byte of the Rx FIFO contains
the oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the “oldest” received data bit. If the character received is less than 8 bits, the
unused MSBs are padded with zeroes.

3.2 UART0 Transmit Holding Register (U0THR - 0xE000 C000, when

DLAB = 0, Write Only)
The U0THR is the top byte of the UART0 TX FIFO. The top byte is the newest character in
the TX FIFO and can be written via the bus interface. The LSB represents the first bit to
transmit.
The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the
U0THR. The U0THR is always Write Only.

9.3.4 UART0 Fractional Divider Register (U0FDR - 0xE000 C028)

The UART0 Fractional Divider Register (U0FDR) controls the clock pre-scaler for the baud
rate generation and can be read and written at user’s discretion. This pre-scaler takes the
VPB clock and generates an output clock per specified fractional requirements.

This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of UART0 disabled making sure that UART0 is
fully software and hardware compatible with UARTs not equipped with this feature.
UART0 baudrate can be calculated as:

Where PCLK is the peripheral clock, U0DLM and U0DLL are the standard UART0 baud
rate divider registers, and DIVADDVAL and MULVAL are UART0 fractional baudrate
generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
1. 0 < MULVAL ≤ 15
2. 0 ≤ DIVADDVAL ≤ 15

4.1 Pin function Select register 0 (PINSEL0 - 0xE002 C000)

The PINSEL0 register controls the functions of the pins as per the settings listed
The direction control bit in the IO0DIR register is effective only when the
GPIO function is selected for a pin. For other functions, direction is controlled
automatically.

2.1.7 I2C
A typical I2C bus configuration is shown. Depending on the state of the direction bit
(R/W), two types of data transfers are possible on the I2C bus:
 Data transfer from a master transmitter to a slave receiver. The first byte transmitted
by the master is the slave address. Next follows a number of data bytes. The slave
returns an acknowledge bit after each received byte.
  Data transfer from a slave transmitter to a master receiver. The first byte (the slave
address) is transmitted by the master. The slave then returns an acknowledge bit. Next
follows the data bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than the last byte. At the end of the last
received byte, a “not acknowledge” is returned. The master device generates all of the serial
clock pulses and the START and STOP conditions. A transfer is ended with a STOP
condition or with a repeated START condition. Since a repeated START condition is also the
beginning of the next serial transfer, the I2C bus will not be released.

This device provides a byte oriented I2C interface. It has four operating modes:
master transmitter mode, master receiver mode, slave transmitter mode and slave receiver
mode.

2.1.7.1 Master Transmitter mode

In this mode data is transmitted from master to slave. Before the master transmitter
mode can be entered, I2CONSET must be initialized as shown in Figure 25. I2EN must be set
to 1 to enable the I2C function. If the AA bit is 0, the I2C interface will not acknowledge any
address when another device is master of the bus, so it can not enter slave mode. The STA,
STO and SI bits must be 0. The SI Bit is cleared by writing 1 to the SIC bit in the
I2CONCLR register.
 The first byte transmitted contains the slave address of the receiving device (7 bits)
and the data direction bit. In this mode the data direction bit (R/W) should be 0 which means
Write. The first byte transmitted contains the slave address and Write bit. Data is transmitted
8 bits at a time. After each byte is transmitted, an acknowledge bit is received. START and
STOP conditions are output to indicate the beginning and the end of a serial transfer. The I2C
interface will enter master transmitter mode when software sets the STA bit. The I2C logic
will send the START condition as soon as the bus is free. After the START condition is
transmitted, the SI bit is set, and the status code in I2STAT should be 08h.This status code
must be used to vector to an interrupt service routine which should load the slave address and
Write bit to I2DAT (Data Register), and then clear the SI bit. SI is cleared by writing a 1 to
the SIC bit in the I2CONCLR register.

When the slave address and R/W bit have been transmitted and an acknowledgment
bit has been received, the SI bit is set again, and the possible status codes now are 18h, 20h,
or 38h for the master mode, or 68h, 78h, or 0B0h if the slave mode was enabled (by setting
AA=1).

2.1.7.2 Master Receiver mode

In the master receiver mode, data is received from a slave transmitter. The transfer is
initiated in the same way as in the master transmitter mode. When the START condition has
been transmitted, the interrupt service routine must load the slave address and the data
direction bit to I2C Data Register (I2DAT) and then clear the SI bit. When the slave address
and data direction bit have been transmitted and an acknowledge bit has been received, the SI
bit is set, and the Status Register will show the status code. For master mode, the possible
status codes are 40H, 48H, or 38H. For slave mode, the possible status codes are 68H, 78H,
or B0H.
Slave Receiver mode
In the slave receiver mode, data bytes are received from a master transmitter. To initialize
the slave receiver mode, user write the Slave Address register (I2ADR) and write the I2C
Control Set register (I2CONSET) as shown in

I2EN must be set to 1 to enable the I2C function. AA bit must be set to 1 to acknowledge
its own slave address or the general call address. The STA, STO and SI bits are set to 0.
After I2ADR and I2CONSET are initialized, the I2C interface waits until it is addressed by
its own address or general address followed by the data direction bit. If the direction bit is
0 (W), it enters slave receiver mode. If the direction bit is 1 (R), it enters slave transmitter
mode. After the address and direction bit have been received, the SI bit is set and a valid
status code can be read from the Status register (I2STAT).

5.4 Slave Transmitter mode

The first byte is received and handled as in the slave receiver mode. However, in this
mode, the direction bit will be 1, indicating a read operation. Serial data is transmitted via
SDA while the serial clock is input through SCL. START and STOP conditions are
recognized as the beginning and end of a serial transfer. In a given application, I2C may
operate as a master and as a slave. In the slave mode, the I2C hardware looks for its own
slave address and the general call address. If one of these addresses is detected, an
interrupt is requested. When the microcontrollers wishes to become the bus master, the
hardware waits until the bus is free before the master mode is entered so that a possible
slave action is not interrupted. If bus arbitration is lost in the master mode, the I2C
interface switches to the slave mode immediately and can detect its own slave address in
the same serial transfer.

2.1.7 Real Time Clock

The Real Time Clock (RTC) is designed to provide a set of counters to measure time
during system power on and off operation. The RTC has been designed to use little power,
making it suitable for battery powered systems where the CPU is not running continuously
(Idle mode).

The RTC includes a number of registers. The address space is split into four sections
by functionality. The first eight addresses are the Miscellaneous Register Group. The second
sets of eight locations are the Time Counter Group. The third sets of eight locations contain
the Alarm Register Group. The remaining registers control the Reference Clock Divider.

Ultra Low Power design supports battery powered systems .Provides Seconds,
Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. Can be used
with dedicated 32 kHz oscillator or programmable prescaler from APB clock. Dedicated
power supply pin can be connected to a battery or to the main 3.3 V.

The Real-Time Clock (RTC) is a set of counters for measuring time when system
power is on and optionally when it is off. It uses little power in Power-down mode. RTC can
be clocked by a separate 32.768 KHz oscillator or by a Programmable prescale divider based
on the APB clock.

The RTC does a simple bit comparison to see if the two lowest order bits of the year
counter are zero. If true, then the RTC considers that year a leap year. The RTC considers all
years evenly divisible by 4 as leap years. This algorithm is accurate from the year 1901
through the year 2099, but fails for the year 2100, which is not a leap year. The only effect of
leap year on the RTC is to alter the length of the month of February for the month, day of
month, and year counters.
 Since the RTC operates from the VPB clock (pclk), any interruption of that clock will
cause the time to drift away from the time value it would have provided otherwise. The
variance could be to actual clock time if the RTC was initialized to that, or simply an error in
elapsed time since the RTC was activated.

PREINT = int (pclk / 32768) - 1. The value of PREINT must be greater than or equal to 1.
PREFRAC = pclk - ((PREINT +1) x 32768).

RTC external 32 kHz oscillator component selection

2.1.8 ADC
10 bit successive approximation analog to digital converter. Input multiplexing among
8 pins. It has a power down mode with measurement range 0 to 3V. Basic clocking for the
A/D converter is provided by the VPB clock. A programmable divider is included to scale
this clock to the 4.5 MHz (max) clock needed by the successive approximation process. A
fully accurate conversion requires 11 of these clocks. 10 bit conversion time ≥ 2.44 μs.