Documente Academic
Documente Profesional
Documente Cultură
Electronic Systems
By
Dr. Doug Hopkins & Dr. Ron Wunderlich
DCHopkins & Associates
Denal Way, m/s 408
Vestal, New York 13850-3035
dch@dchopkins-associates.com
Types of Loads
Motor drives
• Linear Lighting
• Fluorescent Pulsed power
• Rotational
• HID • Ignition
• Halogen • Flash lamp
• Pulsed propulsion
POWER CONVERSION
Clean AC
Noisy AC Utility
Power Electronic
Utility Processor Circuit
Voltage
Voltage
Time Time
Source Load
Power
Processor
SOURCE
Five Taxonomies
and
Three Characteristics
Technical Characteristics
– Energy Forms
– Conditions
• Start-up
• Shut-down
• Normal operation
• Fault operation
Electrical Spec
• Specified as peak-to-peak.
• Occurs at usually < 10Mhz
• Typically, < 10% of max Iin
Iin Irip
• E.g., if Iin max is 10A, Irip p-p
should < 1A
Time
Iin
>10Mhz.
• The noise is due to the
internal capacitive coupling Time
parasitics
• Typically, the peak-to-peak Iin Vin
noise is less than 1% of max
Iin
Time
• AC sources are:
Vpk
– Single Phase
– Three Phase (>5kW, not covered)
Voltage
• Vin is understood to be Vin-rms;
– Vin-rms = Vpk / 1.4142 *
• RMS makes calculations easier Time
Load Step
VOUT
Ripple & HF
Noise
Long Term
Stability
© 2006 DCHopkins www.DCHopkins-Associates.Com
Static Regulation
• Line Regulation
– % change in output voltage versus input voltage at a given load
– Typically 1-2%
• Load Regulation
– % change in output voltage versus load at a given input voltage
– Typically 0.1-3%
• Vout Temperature Effect
– % change in output voltage versus temperature for given input
and load
– Typically 0.2-1%
• Ripple
– Triangular-shaped current at
Vout
the switch frequency Vrip
– Due to inductor current x
ESR of output cap
Time
• High Frequency Noise
– Noise > 10 x fSW
– Either random or the
excitation of high-frequency
parasitics.
Voltage
• Typically 0.2-3%
Time
• Drift is due to
– Aging
– Soldering
– Package compression
• Typically < 0.2%
I step
Minimum
current
Time
Safety Corporate
Standards
Vin
Iin
Time
EMC Features
Robustness
Class A Class B
typically for industrial typically for commercial / home
equipment equipment
Class B is 10dB more stringent
• Answer
The speed of light, c, is 300 x 106m/s
At f = 30Mhz (30 x 106/s), the wavelength (=c/f) is 10m
• These standards help the user design a product that will last a
reasonable time in every day environments.
• There are no requirements to meet any of these standards.
However, they contain a wealth of experience.
• For example
– For connectors, FR4 cards and sheet metal
– Spacing between primary to secondary wring on a FR4 card is
well defined in safety guidelines
– IPC defines the spacing between primary-to-primary and
secondary-to-secondary wiring
– If the primary-to-primary spacing is reduced below the IPC
guidelines, arcing can occur
• There is no facility to test against the IPC spec.
• This is left up to the designer
dc source Load
(VIN) (VOUT)
Duality
Current is voltage; Voltage is current
L is C; C is L
R is R is R
Series is parallel; Parallel is series
Transistor is diode; Diode is Transistor
Open is closed; Closed is open
dc dc load
source load source
VOUT -D
= TON TON
VIN 1-D D=
TPERIOD TPERIOD
• •
Buck/Boost load
Isolated dc
source
Flyback
• •
Buck load
Isolated dc
source
Forward
dc
source LOAD
Full Bridge
dc
source LOAD
dc
source LOAD
Parallel Loaded
Series Resonant
dc
source
LOAD
Lower the
Mosfet rating,
the faster the
All parameters
device
work against
you Thank you,
Mother Nature
IF tn IF tn
ta tb ta tb
IRR IRR
Abrupt Recovery
Soft Recovery
Buck Load
© 2006 DCHopkins www.DCHopkins-Associates.Com
Safe Operating Area - the holy grail
SOA combines transient and thermal limits
ID Transient
Steady state (DC) limit thermal limit
Fusing current
Thermal path limit
Breakdown
MAXIMUM limit
POWER AREA
VDS
Rp Xp Xs
Xl Cs
Approx.: Xl = 10 *Xp
© 2006 DCHopkins www.DCHopkins-Associates.Com
The Dual Faces of
Power MOSFETS
Getting the heat out with
Synchronous Rectification
dc load
source
Boost
© 2006 DCHopkins www.DCHopkins-Associates.Com
Synchronous Rectification - Efficiency
• The best Schottky diode voltage is 0.25V and high current Schottky
diodes are as high as 1V
• For example, 1V@100A converter with 0.5V for Vd, can have an
efficiency of 67% best case
• For every 100W out, 50W is wasted as heat!
• Other advantages for increasing efficiency
– Greater utilization of AC feeder capacity
– Reduced electrical bill for the customer
– Increased reliability with less thermal issues
– More “green” friendly
• I x Rds-on < Vd I
– If the current reverses and the Fet is on, you have a short-circuit
condition across, usually, a transformer
– Timing is critical
– The MOSFET body diode may come on
– Placing a Schottky diode in parallel with the body diode will not,
in all cases, reduce power loss – Ramp down effect
– Very low Rds-on Fets require a large amount of gate drive energy
• For example, a 1V@100A converter, 2% efficiency loss to
gate drives is not uncommon
Electric
Magnetic
Electromagnetic
+
Thermal
Mechanical
Chemical
Photonic
We do not do ONLY electrical designs
© 2006 DCHopkins www.DCHopkins-Associates.Com
Typical Electrical Structure
Lead Inductance
Finite resistance
Skin Effect
Inter-Conductor Capacitance
Coupled Capacitance
© 2006 DCHopkins www.DCHopkins-Associates.Com
Conductor Resistance -Sheet Resistance
l
R= r l / (t × w)
t l
w
let l / w = 1 = “one square”
Rsheet = r / t [ W / sq. ]
A corner is 0.559 squares
Vleads =
=
Pleads =
? Terminal
• Substrate Coupling
Example:
Conductor #1: 100mils x 1 inch
Conductor #2: 400mils x 1 inch
Substrate: ceramic loaded polymer, 3 mils thick, er = 6.4
Find Capacitance:
C=
© 2006 DCHopkins www.DCHopkins-Associates.Com
Coupled Capacitance
• Substrate Coupling
Example:
Conductor #1: 100mils x 1 inch
Conductor #2: 400mils x 1 inch
Substrate: ceramic loaded polymer, 3 mils thick, er = 6.4
Find Capacitance:
C1 = 47.9 pF, C2 = 192 pF
C = C1 series with C2 = 38.3 pF
© 2006 DCHopkins www.DCHopkins-Associates.Com
Ground Coupling
Example: Switching current
coupled into header from FET drain. Vd
FET: 400mils2, tf = 20 ns
(+20 mil conductor periphery)
(+100 mils2 drain bond pad)
(+200 mils x 400 mils drain lead)
Substrate: Al2O3
25 mils thick, er = 9.4
Voltage source: 425 Vdc
continued
Bond Pad
Find Capacitance: 100mils2
20mils
?
Find switching current:
400mils2
i = C (dV/dt )
Drain Lead
100x200mils
i=
Bond Pad
100mils2
20mils
• Find Capacitance:
A = 0.284 in2 = 183 mm2 400mils2
d = 25 mils = 0.635 mm
Then: C = 24 pF (d-s Cap)
• Find switching current: Drain Lead
i = C (dV/dt )
100x200mils
= 24 pF (425/20ns)
i = 0.51 A
For ceramic loaded polymer
C = 136 pF and i = 2.9 A
Non-ferrous headers
Aluminum
Copper
Si C
Al Si C
Ferrous headers / substrates
Invar ( 64% iron, 36% nickel )
Kovar ( 54% iron, 29% nickel, 16% cobalt)
Ferrite (substrates)
Porcelainized steel (substrate)
Dust
Temperat 6% 100, 0.05
ure
55% 50, 0.005
Humidity
19%
Junction Temp (C)
Factors affecting DT
Convection/conduction in medium
Chip size
Chip attach
Heat spreader
Conductor type and thickness
Substrate type and thickness
Substrate attach
Heatsink
Power Supply
P0 / P i , Pl = P0 ( 1 - )
Load
P0, zero % efficient electrically
heat heat
For first-level type packaging
(e.g.. chip and wire) the thermal
area densities are equal:
P0
Pi , Pl PL
Pl / Aps = PL / AL
0.4
0.2
Then TDr ( Pl / Aps ) = PL / AL
0
Aps / AL = TDr ( 1 1 ) 0.5 0.6 0.7 0.8 0.9 1
Rq = 1 t Chip
k A Solder
1 l Spreader
R =
s A Conductor
Substrate
i q
Attach
R [W] = v[V] / i [A]
Dv DT Baseplate
R [oC/W] = T [oC] / q [W]
Attach
R Rq
Heatsink
© 2006 DCHopkins www.DCHopkins-Associates.Com
Comparative Thermal Resistances (°C/kW cm2)
Thermal Typical Thickness DT(°C)
Material Conductivity Rq/cm2 (mils) IGBT
(W/m °C) (°C/kW cm2) @0.2kW/cm2
Si
width depth thick k
Material (mm) (mm) (m) (W/m °C) DBC
Rq = (t / A) / k
Si
t = thickness, A= width x depth
DBC
*in mm
Rq, total = 0.198 °C/W
© 2006 DCHopkins www.DCHopkins-Associates.Com
- ” 45° ” Spreading Angle -
Assumption : For an isotropic material, heat flows laterally at the same
rate it flows vertically.
Hence: A = (Wu + t)(Du + t)
Rq = (t / A) / k
Rq = 0.290° C/W
AlSiC
Review of packaging
paraphernalia
The Good
the Bad and
the Ugly
© 2006 DCHopkins www.DCHopkins-Associates.Com
Presentation Goes Off-Line
Cost $$$
for Power Supplies SwitcherCAD
Ease of Use
SPICE based
or State- Pspice, AWB, SIMetrix, Simplis
Space
Simulator
FEM
Pisces, Fielday, Based
Ansoft Simulators
Physical Level
© 2006 DCHopkins www.DCHopkins-Associates.Com
FEM Design Tools
Expensive and require significant learning
• Pisces and Fielday,
IBM tools, simulate
semiconductor
devices at the
electron level
• Ansoft simulator
models electro-
magnetic devices
with FEM
– On the right is a
gapped ferrite core
showing the flux
lines
See additional Ansoft foils
© 2006 DCHopkins www.DCHopkins-Associates.Com
SPICE Design Tools
Easy to use but requires circuit
design experience and $$$
1=Transim Corp
© 2006 DCHopkins www.DCHopkins-Associates.Com
Webench Design Tool - www.webench.com
• Webench is a design
tool from National
Semi. in conjunction
with Transim Corp.
• Webench helps you
pick the IC, simulate
and build.
• Within Webench is
Websim which uses
Simplis as the
simulation engine
• Webench is a Web
based tool
• Very easy to use and
free but not flexible
Overhead
Other OH
Packaging Materials
& Production Costs
(controllable)
Production
Depreciation Cost
Standard unit cost
Wages
Packaging materials
Comp. packaging
Materials
Cost Minimum packaged
components
• Materials cost*
• Production cost*
– *Full Cost
• Partitioning cost
• Product business cost (return on investment for
development of one product)
• Company business cost (return on investment for cross
products)
yr - 2000
700%
600%
500%
Production Cost
300%
200% Depreciation
100%
Wages
0%
10k 32k 100k 320k 1000k
Products/Year
0.8
TF module
& leadframe 110 SMDs
Relative Cost
14 leadet
0.6
FR4
0.4
Functional
integration within 0.2
70 SMDs
7 leadet technology
0
0 5 10 15 20 25 30
Surface Density
Hot 0.2
Embossing
0
0 5 10 15 20 25 30
Surface Density
© 2006 DCHopkins www.DCHopkins-Associates.Com
Relative Packaging & Production Cost
10 b
8
b Substr/in2
6 c c Power chip&
wire/10 comp
4
2 d SMD/10 comp
d d
0 Integrated res/10 comp
TTF
FR4 Cu( 2x35um)
TF multilayer
Substrate Technology
120%
100%
Cost/component
80%
60%
40%
20%
0%
Leaded-manual Leaded-auto Power chip & wire SMD-auto
Assembly Technology