US20020181614A1 - Subsampling RF Receiver Architecture - Google Patents

11/13/2018 US20020181614A1 - Subsampling RF receiver architecture - Google Patents
Patents
Subsampling RF receiver architecture
Abstract
US20020181614A1
A subsampling receiver (50, 50′, 50″) for converting an RF signal to baseband is disclosed. The
US Application
subsampling receiver (50, 50′, 50″) may be implemented into a wireless communications device
(40), such as a wireless telephone handset. In one disclosed embodiment, the receiver (50) includes
a sample and hold circuit (80) that samples a bandpass ltered input modulated signal at the Download PDF Find Prior Art Similar
subsampling frequency (fs) that is well below the RF carrier frequency but twice the bandwidth (BW)
of the payload; the sampled signal is digitized, and applied to two digital mixers (85I, 85Q) to Inventor: Mohamed Mostafa, Sherif Embabi, Moderage
produce in-phase and quadrature components (I,Q) of the payload. In another embodiment, the Fernando, Wing Chan, Charles Gore
receiver (50′) includes two sample and hold circuits (96I, 96Q) to sample the ltered signal at Current Assignee : Texas Instruments Inc
different phases of the sampling frequency, to produce the in-phase and quadrature digital
Original Assignee: Texas Instruments Inc
components. In a third embodiment, the receiver (50″) includes an analog mixer (116) to
downconvert the RF input to an intermediate frequency, prior to digitization and digital mixing at Priority date : 2001-04-09
quadrature phase.
Family: US (1) EP (1) JP (1)

Images (7)
Date App/Pub Number Status
2002-03-19 US10102428 Active
2002-12-05 US20020181614A1 Application
2006-09-19 US7110732B2 Grant
Info: Patent citations (10), Cited by (66), Legal events, Similar

documents, Priority and Related Applications
Classi cations External links: USPTO, USPTO Assignment, Espacenet, Global
Dossier, Discuss
H04B1/0025 Software-de ned radio [SDR] systems, i.e. systems wherein components typically
implemented in hardware, e.g. lters or modulators/demodulators, are implented using
software, e.g. by involving an AD or DA conversion stage such that at least part of the signal
processing is performed in the digital domain wherein the AD/DA conversion occurs at
radiofrequency or intermediate frequency stage using a sampling rate lower than twice the
highest frequency component of the sampled signal
View 3 more classi cations
Claims (35)
We claim:
1. 1. A subsampling receiver, comprising:
a rst bandpass lter coupled to receive a modulated signal, the modulated signal including at least one carrier signal at radio frequencies, modulated by a payload
signal having frequencies signi cantly lower than the carrier signal and within a rst bandwidth, the rst bandpass lter passing frequencies within a frequency band
at least as wide as the rst bandwidth in a range including the at least one carrier signal;
a rst sample and hold circuit, having an input coupled to the rst bandpass lter, for sampling the modulated signal at a sampling frequency substantially lower than
the frequency of the at least one carrier signal; and
a rst analog to digital converter, coupled to the rst sample and hold circuit, for digitizing the sampled modulated signal to produce a digital signal at a baseband
frequency and corresponding to the payload signal.
2. 2. The receiver of claim 1, wherein the sampling frequency is at least twice the rst bandwidth.
3. 3. The receiver of claim 1, further comprising:
rst and second digital mixers, each coupled to the output of the rst analog to digital converter, for applying a sequence of varying amplitude values to the
digitized sampled modulated signal at a frequency lower than the sampling frequency;
wherein the sequence applied by the second digital mixer is phase-shifted from the sequence applied by the rst digital mixer;
and wherein the rst and second digital mixers present digital sequences corresponding to rst and second components of the payload signal.
4. 4. The receiver of claim 3, wherein the rst and second digital mixers are for applying the sequences of varying amplitude values at a frequency that is one-fourth
of the sampling frequency;
and wherein the sequence applied by the second digital mixer is phase-shifted by 90° from the sequence applied by the rst digital mixer so that the rst and
second components correspond to in-phase and quadrature components of the payload signal.
rst and second digital low pass lters coupled to the outputs of the rst and second digital mixers, respectively.
https://patents.google.com/patent/US20020181614 1/13
6. 6. The receiver of claim 3, wherein the sampled modulated signal includes a plurality of aliases of the modulated signal, the plurality of aliases including a near
baseband alias.
7. 7. The receiver of claim 6, wherein the output of the rst and second digital mixers correspond to rst and second components of the modulated signal at the
baseband frequency.
a rst low noise ampli er, coupled to the output of the rst bandpass lter; and
a second bandpass lter, coupled to the output of the rst low noise ampli er.
a second sample and hold circuit, having an input coupled to the rst bandpass lter, for sampling the modulated signal at the sampling frequency and phase-
shifted from the sampling by the rst sample and hold circuit; and
a second analog to digital converter, coupled to the second sample and hold circuit, for digitizing the sampled modulated signal to produce a digital signal at a
baseband frequency and corresponding to the payload signal;
wherein the digital signals produced by the rst and second analog to digital converters correspond to rst and second components of the payload signal.
10. 10. The receiver of claim 9, wherein the sampling by the rst and second sample and hold circuits are phase-shifted from one another by 90°;
and wherein the rst and second components of the payload signal correspond to in-phase and quadrature components of the payload signal.
rst and second digital low pass lters, coupled to the output of the rst and second sample and hold circuits, respectively.
a rst low noise ampli er, coupled to the input of the rst bandpass lter; and
a second low noise ampli er, coupled to the output of the rst bandpass lter.
13. 13. The receiver of claim 12, wherein the second low noise ampli er is integrated into the same integrated circuit as the rst and second sample and hold circuits
and the rst and second analog to digital converters.
an analog mixer, coupled to the output of the rst bandpass lter, for downconverting the modulated signal to an intermediate frequency;
digitized sampled modulated signal at a frequency lower than the sampling frequency;
wherein the sequence applied by the second digital mixer is phase-shifted from the sequence applied by the rst digital mixer;
and wherein the rst and second digital mixers present digital sequences corresponding to rst and second components of the payload signal.
15. 15. The receiver of claim 14, wherein the rst and second digital mixers are for applying the sequences of varying amplitude values at a frequency that is one-
fourth of the sampling frequency;
and wherein the sequence applied by the second digital mixer is phase-shifted by 90° from the sequence applied by the rst digital mixer so that the rst and
second components correspond to in-phase and quadrature components of the payload signal.
16. 16. The receiver of claim 14, wherein the analog-to-digital converter comprises:
a comparator, for generating an error signal corresponding to a difference between the sampled modulated signal and a feedback signal;
a bandpass lter coupled to the comparator, for ltering the error signal;
a quantizer, for quantizing the ltered error signal; and
a digital low pass lter, for ltering the quantized error signal;
wherein the feedback signal corresponds to the quantized error signal.
17. 17. A wireless communications unit, comprising:
an antenna;
a speaker;
a digital signal processor, for performing digital signal processing on signals received at the antenna;
an audio interface, for communicating processed received signals from the digital signal processor to the speaker; and
a subsampling receiver, comprising:
a rst bandpass lter coupled to receive a modulated signal from the antenna, the modulated signal including at least one carrier signal at radio frequencies,
modulated by a payload signal having frequencies signi cantly lower than the carrier signal and within a rst bandwidth, the rst bandpass lter passing
frequencies within a frequency band at least as wide as the rst bandwidth in a range including the at least one carrier signal;
a rst sample and hold circuit, having an input coupled to the rst bandpass lter, for sampling the modulated signal at a sampling frequency substantially lower
than the frequency of the at least one carrier signal; and
a rst analog to digital converter, coupled to the rst sample and hold circuit, for digitizing the sampled modulated signal to produce, at an output coupled to the
digital signal processor, a digital signal at a baseband frequency and corresponding to the payload signal.
18. 18. The communications unit of claim 17, wherein the sampling frequency is at least twice the rst bandwidth.
19. 19. The communications unit of claim 17, wherein the subsampling receiver further comprises:
digitized sampled modulated signal at a frequency that is one-fourth of the sampling frequency;
wherein the sequence applied by the second digital mixer is phase-shifted by 90° from the sequence applied by the rst digital mixer;
and wherein the rst and second digital mixers present digital sequences corresponding to in-phase and quadrature components of the payload signal.
20. 20. The communications unit of claim 19, wherein the sampled modulated signal includes a plurality of aliases of the modulated signal, the plurality of aliases
including a near baseband alias;
and wherein the output of the rst and second digital mixers correspond to rst and second components of the modulated signal at the baseband frequency.
a second sample and hold circuit, having an input coupled to the rst bandpass lter, for sampling the modulated signal at the sampling frequency and phase-
shifted by 90° from the sampling by the rst sample and hold circuit; and
a second analog to digital converter, coupled to the second sample and hold circuit, for digitizing the sampled modulated signal to produce a digital signal at a
baseband frequency and corresponding to the payload signal;
wherein the digital signals produced by the rst and second analog to digital converters correspond to in-phase and quadrature components of the payload
signal.
22. 22. The communications unit of claim 21, further comprising:
a rst low noise ampli er, coupled to the input of the rst bandpass lter; and
a second low noise ampli er, coupled to the output of the rst bandpass lter;
wherein the second low noise ampli er is integrated into the same integrated circuit as the rst and second sample and hold circuits and the rst and second
analog to digital converters.
an analog mixer, coupled to the output of the rst bandpass lter, for downconverting the modulated signal to an intermediate frequency;
digitized sampled modulated signal at a frequency values at a frequency that is one-fourth of the sampling frequency;
wherein the sequence applied by the second digital mixer is phase- shifted by 90° from the sequence applied by the rst digital mixer;
and wherein the rst and second digital mixers present digital sequences corresponding to in-phase and quadrature components of the payload of the payload
signal.
24. 24. The communications unit of claim 17, wherein the analog-to-digital converter comprises:
a comparator, for generating an error signal corresponding to a difference between the sampled modulated signal and a feedback signal;
a bandpass lter coupled to the comparator, for ltering the error signal;
a quantizer, for quantizing the ltered error signal; and
a digital low pass lter, for ltering the quantized error signal;
25. 25. A method of converting a received modulated signal to a baseband payload signal, the modulated signal including at least one carrier signal at radio frequencies,
modulated by a payload signal having frequencies signi cantly lower than the carrier signal and within a rst bandwidth:, the method comprising the steps of:
bandpass ltering the modulated signal, to pass frequencies within a frequency band at least as wide as the rst bandwidth in a range including the at least one
carrier signal;
sampling the modulated signal at a sampling frequency substantially lower than the frequency of the at least one carrier signal; and
digitizing the sampled modulated signal to produce a digital signal at a baseband frequency and corresponding to the payload signal.
26. 26. The method of claim 25, wherein the sampling frequency is at least twice the rst bandwidth.
27. 27. The method of claim 25, further comprising:
applying rst and second sequences of varying amplitude values to the digitized sampled modulated signal at a frequency lower than the sampling frequency;
wherein the second sequence is phase-shifted from the rst sequence, to produce rst and second digital sequences corresponding to rst and second
components of the payload signal.
28. 28. The method of claim 27, wherein the applying step applies the rst and second sequences of varying amplitude values at a frequency that is one-fourth of the
sampling frequency;
and wherein the second sequence is phase-shifted by 90° from the rst sequence so that the rst and second components correspond to in-phase and
quadrature components of the payload signal.
29. 29. The method of claim 27, wherein the sampled modulated signal includes a plurality of aliases of the modulated signal, the plurality of aliases including a near
baseband alias.
30. 30. The method of claim 29, wherein the rst and second components of the modulated signal are at the baseband frequency.
31. 31. The method of claim 25, wherein the sampling step comprises:
sampling the modulated signal at the sampling frequency to produce a rst sampled sequence of the modulated signal; and
also sampling the modulated signal at a phase-shifted version of the sampling frequency to produce a second sampled sequence of the modulated signal,
phase-shifted from the rst sampled sequence;
and wherein the digitizing step digitizes the rst and second sampled sequences corresponding to rst and second components of the payload signal.
32. 32. The method of claim 31, wherein rst and second components of the payload signal correspond to in-phase and quadrature components of the payload signal.
33. 33. The method of claim 25, further comprising:
downconverting the modulated signal to an intermediate frequency; and
after the digitizing step, applying rst and second sequences of varying amplitude values to the digitized sampled modulated signal at a frequency lower than
the sampling frequency, the second sequence phase-shifted from the rst sequence, to produce rst and second components of the payload signal.
34. 34. The method of claim 33, wherein the applying step is applies the rst and second sequences at a frequency that is one-fourth of the sampling frequency;
and wherein the second sequence is phase-shifted by 90° from the rst sequence, so that the rst and second components correspond to in-phase and
quadrature components of the payload signal.
35. 35. The method of claim 33, wherein the digitizing step comprises:
comparing the sampled modulated signal to a feedback signal to produce an error signal;
bandpass ltering the error signal;
quantizing the ltered error signal; and
low pass ltering the quantized error signal;
Description
CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority, under 35 U.S.C. §119(e), of Provisional Application No. 60 /282,582, led Apr. 9, 2001.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
[0002] Not applicable.
BACKGROUND OF THE INVENTION
[0003] This invention is in the eld of wireless communications, and is more speci cally directed to receiver circuitry used in such communications.
[0004] The popularity of mobile wireless communications has increased dramatically over recent years. It is expected that this technology will become even more
popular in the foreseeable future, both in modern urban settings, and also in rural or developing regions that are not well served by line-based telephone systems.
This increasing wireless tra c strains the available communications bandwidth for a given level of system infrastructure. As a result, there is substantial interest
in increasing bandwidth utilization of wireless communications system to handle this growth in tra c.
[0005] This trend toward heavier usage of wireless technologies for communications, in combination with the advent of so-called third-generation, or “3G”, wireless
communications that also carry data, video, and other high data rate payloads, will require continuing improvements in the processing capabilities of the
communications equipment. In particular, the higher required data rates will require corresponding increases in the digital processing of the communications
payloads.
[0006] Modern digital communications technology utilizes multiple-access techniques to increase bandwidth utilization, and thus to carry more wireless tra c. Under
current approaches, both time division multiple access (TDMA) and code division multiple access (CDMA) techniques are used in the art to enable the
simultaneous operation of multiple communication sessions, or wireless “connections”, each involving voice communications, data communications, or any type
of digital payload. As evident from the name, TDMA communications are performed by the assignment of time slots to each of multiple communications, with
each conversation transmitted alternately over short time periods. CDMA technology, on the other hand, permits multiple communication sessions to be
transmitted simultaneously in both time and frequency, by modulating the signal with a speci ed code. On receipt, application of the code will recover the
corresponding conversation, to the exclusion of the other simultaneously received conversations.
[0007] Wideband CDMA (WCDMA) is an extension of CDMA communications, and is contemplated to be useful for enhanced services such as contemplated in 3G
wireless. WCDMA involves a higher chip rate than in conventional CDMA, and thereby supports higher bit rates, increases spectrum e ciency by way of better
statistical averaging, and provides better coverage by improving frequency diversity.
[0008] In the receipt of wireless communications devices, digital receiver circuitry in general performs the function of converting the received high frequency signal to a
“baseband” signal output. As known in the art, the term “baseband” refers to the signal at its original band of frequencies. The baseband signal is typically in its
multiplexed form, for example corresponding to multiple communications that are carried out on multiple time or code channels, depending upon whether the
communications are TDMA, CDMA, or WCDMA.
[0009] Modern wireless systems place stringent demands on the analog ltering and digital processing of received signals. These demands arise from the high
frequencies involved in conventional wireless communications, such frequencies typically in the radio frequency (RF) bands, and also from the relatively low
received signal power levels. As a result, relatively costly and complex techniques are commonplace in these systems.
[0010] For example, surface acoustic wave (SAW) lters are often used in conventional wireless receivers, for example in implementing band pass lters. As known in
the art, conventional SAW lters include a piezoelectric substrate, on the surface of which input and output sets of interdigitated metal ngers are formed. The
bandpass ltering is effected by the received signal being applied to the input set of interdigitated metal ngers, with surface acoustic waves excited by the
piezoelectric substrate in response to the electric eld generated between the electrodes. These acoustic waves propagate along the surface of the substrate
and are received at the output set of interdigitated ngers, at which the piezoelectric substrate produces electrical signals in response to the surface acoustic
waves. The wavelength of the output signals are determined by the lengths of the output ngers. Conventional SAW devices readily attain high frequency
performance (with Q values up to on the order of 1000) while remaining relatively compact, in comparison with an equivalent electrical lter. However, because
of the piezoelectric substrate, SAW lters are not integratable with conventional semiconductor integrated circuits. Accordingly, the use of SAW lters adds
signi cantly to system cost.
[0011] Various conventional receiver architectures are now used in modern wireless systems, such as base stations and wireless handsets. These classes of
architectures include heterodyne receivers, direct conversion receivers, and digital mixer architectures. FIG. 1 illustrates a rst example of conventional
heterodyne receiver 10. Receiver 10 includes SAW bandpass lter 2, which receives input RF signal RFI, and passes its ltered output to low noise ampli er
(LNA) 4. The ampli ed signal is then downconverted by rst mixer 6, which is typically an active mixer (gain>unity) that generates an output signal at an
intermediate frequency that is the difference between the ampli ed RF input signal RFI and local oscillator signal LO1. This downconverted signal is then ltered
by second SAW bandpass lter 8, and applied to automatic gain control (AGC) 12. The ltered downconverted signal at the intermediate frequency is then
downconverted to baseband by I-Q mixers 14, which again are greater-than-unity gain analog mixers applying a periodic signal from a second local oscillator (not
shown). The downconverted baseband signal is ltered by analog low-pass lter 16. Analog-to-digital converter (ADC) 18 samples and converts the baseband
signal, at a sampling frequency that satis es the Nyquist criterion of twice the bandwidth of the communicated signal. The digital signal is then decimated by
decimating lter 19 to reduce the data rate, following which the signal is ready for demodulation and decoding.
[0012] However, this conventional heterodyne architecture is quite costly to implement, and also consumes a great deal of power, which is problematic for battery-
powered devices such as wireless telephone handsets. A primary reason for this high power consumption and high cost derives from the use of SAW lters 2, 8,
which necessarily consume signi cant power and must be realized off-chip, as described above. Because analog mixers 6, 8 operate at relatively low chopping
frequencies, with greater than unity gain, high-Q lters such as SAW lters are required for reasonable delity. The multiple downconversions necessary to bring
the input signal to baseband exacerbate these issues.
[0013] Another type of conventional receiver reduces these noise issues by using only a single mixer to directly downconvert the RF signal to baseband. FIG. 2
illustrates an example of this type of architecture, in the form of conventional direct conversion receiver 20. In this example, SAW lter 22 receives input signal
RFI, and applies the bandpass ltered signal to LNA 24. I-Q stage mixer 26 downconverts this ltered ampli ed input signal to baseband. Low pass lter 28 and
AGC 29 clean up this downconverted signal, prior to digitization by ADC 31 and decimating by decimating lter 33, similarly as described above. While this
architecture reduces the cost of manufacture relative to the heterodyne architecture of FIG. 1, the use of only one level mixer for downconversion causes this
architecture to suffer from DC offset problems, signi cant even-order distortion, and icker noise.
[0014] FIG. 3 illustrates a conventional receiver architecture of the low-IF digital mixer type, which is effectively a compromise between the heterodyne and direct
conversion receivers of FIGS. 1 and 2. As shown in FIG. 3, receiver 30 receives the RF input signal RFI with SAW bandpass lter 32, and applies the ltered output
to LNA 34 as before. A single mixer 36 downconverts the ltered input signal to an intermediate frequency, which is again ltered by second SAW lter 38, and
adjusted by AGC 39. ADC 41 converts the signal to digital, at a sampling frequency that is four times the intermediate frequency to which mixer 36
downconverted the input signal. I-Q mixer 45 then downconverts the digital signal, by applying a pattern of {−1, 0, +1, 0, 1, . . . }, at the sampling frequency, to the
digital samples from ADC 43. This digital mixing by mixer 45 effectively applies a sinusoid of one-fourth of the sampling frequency to the digital output.
Decimating lter 47 reduces the output data rate.
[0015] Digital mixer receiver 30 of FIG. 3 is a compromise of the heterodyne and direct conversion receivers, in that it still uses two stage mixers, but only one mixer is
an analog mixer. The second, digital, mixer is not as sensitive to noise and distortion as an analog mixer, and thus receiver 30 is contemplated to provide good
performance. In addition, the I & Q signals are generated in the digital domain, thus the matching between the I & Q branches is optimized. However, two SAW
lters are still required in digital mixer receiver 30, maintaining relatively high cost for this approach.
BRIEF SUMMARY OF THE INVENTION
[0016] It is therefore an object of this invention to provide a radio frequency (RF) receiver that provides high performance at a reduced manufacturing cost and power
dissipation.
[0017] It is a further object of this invention to provide such a receiver in which off-chip surface acoustic wave (SAW) lters are minimized.
[0018] It is a further object of this invention to provide such a receiver in which analog mixers need not be used or reduced in complexity.
[0019] It is a further object of this invention to provide such a receiver in which power consumption is also minimized.
[0020] It is a further object of this invention to provide such a receiver in which the matching between the I & Q branches is optimized.
[0021] Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following speci cation together
with its drawings.
[0022] The present invention may be implemented into a radio frequency (RF) receiver in which the received signal is sampled at a frequency that is signi cantly lower
than its carrier frequency, but at least twice the bandwidth of the modulating signal. This subsampling results in aliasing of the signal, including a near-baseband
alias of the communicated signal. Analog-to-digital conversion of the sampled baseband alias, and digital mixing can then be readily applied, producing a digital
baseband signal for demodulation.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0023] FIG. 1 is an electrical diagram, in block and schematic form, illustrating the architecture of a rst conventional RF receiver.
[0024] FIG. 2 is an electrical diagram, in block and schematic form, illustrating the architecture of a second conventional RF receiver.
[0025] FIG. 3 is an electrical diagram, in block and schematic form, illustrating the architecture of a third conventional RF receiver.
[0026] FIG. 4 is an electrical diagram, in block form, of a wireless communications device constructed according to the rst preferred embodiment of the invention.
[0027] FIGS. 5 a and 5 b are frequency plots illustrating the spectra resulting from subsampling, including the effects of noise in conventional subsampling.
[0028] FIGS. 5 c through 5 f are frequency plots illustrating the operation of the subsampling receiver according to a rst preferred embodiment of the invention.
[0029] FIG. 6 is an electrical diagram, in block and schematic form, of a subsampling receiver constructed according to a rst preferred embodiment of the invention.
[0030] FIG. 7 is an electrical diagram, in block and schematic form, of a subsampling receiver constructed according to a second preferred embodiment of the
invention.
[0031] FIG. 8 is an electrical diagram, in block and schematic form, of a subsampling receiver constructed according to a third preferred embodiment of the invention.
[0032] FIGS. 9 a through 9 c are frequency spectra illustrating the operation of the subsampling receiver of a third preferred embodiment of the invention.
[0033] FIG. 10 is an electrical diagram, in block form, illustrating a band-pass analog-to-digital converter as used in the subsampling receiver of the third preferred
embodiment of the invention.
DETAILED DESCRIPTION OF THE INVENTION
[0034] This invention will now be described in connection with its preferred embodiment. More speci cally, this invention is contemplated to be especially bene cial
when used in a wireless telephone. Therefore, the preferred embodiment of this invention will be described in connection with an exemplary architecture for a
wireless telephone. However, it is contemplated that this invention may be used in connection with wireless telephones of other architectures, and with devices
and systems other than wireless telephones. It is therefore to be understood that those alternative implementations, and other alternative applications of this
invention that will become apparent to those skilled in the art having reference to this speci cation, are within the true scope of this invention as claimed.
[0035] Referring now to FIG. 4, wireless unit 40 constructed according to the preferred embodiment of the invention will now be described in detail. Wireless unit 40 of
FIG. 4 corresponds to a wireless handset, having at least the so-called “second generation”, or “2G” capability, such as is typically used to carry out TDMA and
CDMA broadband communication; it is further contemplated that wireless unit 40 may also be constructed to provide the so-called “third generation” or “3G”
communications, which include data and video services. Of course, it is contemplated that the present invention may also be implemented in wireless base
stations and other digital radio applications, for similar bene ts from this invention. The architecture of the construction of wireless handset 40 shown in FIG. 4
is provided by way of example only, it being understood that such other alternative architectures may also be used in connection with the present invention.
[0036] The bulk of the digital signal processing performed on both signals to be transmitted and those received, is executed by digital signal processor (DSP) 53. In this
architecture of wireless handset 40, DSP 53 is coupled on one side to audio interface 58, which in turn couples wireless unit 40 to speaker S and microphone M;
on the other side, DSP 53 is coupled through RF interface circuitry 52 to radio subsystem 42 and antenna A. DSP 53 preferably has a signi cant amount of
processing capacity to handle the digital processing necessary for both the transmit and receive operations. An example of a suitable digital signal processor for
use as DSP 53 is the TMS320c6x family of digital signal processors available from Texas Instruments Incorporated, a preferred example of which is the
TMS320C6416 DSP. The particular digital functions performed by DSP 53 will depend, of course, upon the communications protocol used by wireless unit 40.
[0037] On the transmit side, incoming voice communications from microphone M are forwarded to DSP 53 by audio interface 58. Within DSP 53, encode and modulate
function 54 performs the appropriate digital processing functions for the particular protocol. For example, encode and modulate function 54 may rst encode
the received digital data into symbols, for example by way of a DFT operation. These symbols are then spread, by way of a spreading code, into a sequence of
chips according to a selected chip rate; the spreading may also include the spreading of the symbols into multiple subchannels. According to the preferred
embodiment of the invention, which will be described in further detail below, a cell-speci c scrambling code is then applied to the spread symbols, and the
scrambled spread symbols are modulated. In general, this modulation splits the subchannels into in-phase (I) and quadrature (Q) groups, so that the eventual
modulated signal includes both components. Typically, RF interface circuitry 52 performs the appropriate ltering and phase modulation appropriate for the
particular transmission protocol, on digital signals from DSP 53. For example, multiple channels of encoded digital bitstreams, corresponding to the combination
of both in-phase (I) and quadrature (Q) components, may be forwarded to RF interface circuitry 52 by DSP 53. RF interface circuitry 52 converts these digital
data into analog signals, phase-shifts the selected converted bitstreams to provide both in-phase (I) and quadrature (Q) analog signal components, and applies
analog ltering as appropriate to the signals to be handed off to modulator 48 in radio subsystem 42. The spread spectrum sequence is converted into an
analog signal by RF interface 32, with the desired ltering and pre-equalization to compensate for channel distortion, and is then transmitted over antenna A by
radio subsystem 42. Modulator 48 in radio subsystem 42 receives these signals to be transmitted from RF interface circuitry 52, and generates a broadband
modulated analog signal, under the control of synthesizer 46. Power ampli er 44 ampli es the output of modulator 48 for transmission via antenna A.
[0038] According to the preferred embodiments of the invention, on the receive side, incoming signals from antenna A are received by subsampling receiver 50 within
radio subsystem 42 and forwarded to DSP 53 for digital processing via RF interface circuitry 52. In this embodiment of the invention, as will be described in
detail below, subsampling receiver 50 in radio subsystem 42 converts the received analog signal into the appropriate digital format for processing by DSP 53. In
this example, as will become apparent from the following description, in-phase (I) and quadrature (Q) components of the received signal are separated and
ltered by subsampling receiver 50, including the necessary analog to digital conversion so that digital bitstreams corresponding to the separated and ltered
components of the received signal are forwarded to DSP 53 by RF interface circuitry 52.
[0039] On the receive side, DSP 53 will digitally perform such functions as channel decoding of the data from subsampling receiver 50 to retrieve a data signal from the
received digitally spread signal, followed by the decoding of the speech symbols from the channel decoded data using techniques such as inverse discrete
Fourier transforms (IDFT) and the like, as illustrated in FIG. 4 by decode and demodulate circuitry 55. Equalization, error correction, and decryption processes are
also performed upon the received signal as appropriate. The resulting signal processed by DSP 53 on the receive side is then forwarded to audio interface 58, for
output via speaker S.
[0040] Other support circuitry is also provided within wireless handset 40 as shown in FIG. 4. In this example, controller 56 handles the control of wireless handset 40
other than the data path. Such control functions include resource management, operating system control, and control of the human interface; in this regard,
controller 56 operates with such functions as memory 33 (for storage of the operating system and user preferences), keypad 57, and user display 58.
[0041] Referring now to the frequency spectrum of FIG. 5 a, the theory of operation of subsampling receiver 50 according to the preferred embodiments of the invention
will now be described. FIG. 5a illustrates signal RFI received by subsampling receiver 50. As shown in FIG. 5a, signal RFI is a relatively high frequency signal, and
has a bandwidth BW that extends to the highest frequency HIRFI within signal RFI. In conventional wireless communications, the payload of signal RFI is a
relatively low frequency modulation of a high frequency carrier or set of subcarriers. It is the carrier frequencies that position the spectrum of transmitted signal
RFI at this high frequency, with the payload of transmitted signal RFI contained within bandwidth BW.
[0042] According to the well-known Nyquist criterion, an analog signal must be sampled at a sampling frequency that is twice the bandwidth of the signal of interest in
order to faithfully reproduce the signal, without the presence of so-called destructive “aliases”. If one were to attempt to satisfy the Nyquist criterion relative to
signal RFI, one would sample at twice the highest frequency HI RFI. Considering that the frequencies of conventional wireless telephony are well into the GHz
range, such sampling requires extremely high performance integrated circuits.
[0043] According to the present invention, however, subsampling receiver 50 samples the received signal RFI at a frequency fs that is much lower than the theoretical
Nyquist frequency 2HIRFI. As a result of this subsampling, many aliases are generated, as shown in the frequency spectrum of FIG. 5a. These aliases include
mirror images of signal RFI about each multiple of sampling frequency fs, because of the “folding” effect of the subsampling. Of particular interest, however, is
the lowest frequency alias RFIBB. This alias corresponds to the actual signal RFI, but is near-baseband in absolute frequency. According to this invention, this low
frequency alias is retrieved by subsampling receiver 50, in effect downconverting signal RFI to a near-baseband version RFIBB.
[0044] The generation of aliases as shown in FIG. 5 a, as noted above, results from the “folding” of the sampled signal about the multiples of the sampling frequency fs.
Because the sampling frequency fs is at least twice the bandwidth BW of signal RFI, the spectra of the aliases do not overlap onto one another. However, any
broadband noise will be folded and summed together at each alias frequency across the spectrum. FIG. 5b illustrates, for example, the presence of broadband
noise NRFI across all frequencies. The power of broadband noise NRFI is low enough to not signi cantly affect signal RFI. However, because this noise NRFI is
additively folded M times with each alias resulting from the subsampling, the noise level becomes M*NRFI at the low frequencies of near-baseband alias RFINBB,
as shown in FIG. 5b. This additive noise level M*NRFI may approach or exceed the power of near-baseband alias RFINBB, rendering this alias useless as a
downconversion of the signal RFI. According to the present invention, however, the effects of this accumulated noise is avoided in subsampling receiver 50.
[0045] Referring now to FIG. 6, the construction and operation of subsampling receiver 50 according to a rst embodiment of this invention will now be described in
detail. As will be apparent from the following description, subsampling receiver 50 is constructed so as to be e ciently buildable into a single integrated circuit,
along with other analog functions contained within wireless handset 30, if desired. As shown in FIG. 6, the signal from antenna A is received by subsampling
receiver 50. FIG. 5c illustrates the frequency spectrum of this signal, including both the RF input signal RFI, which is centered at a high, RF, frequency, and also
broadband noise NRFI. This signal is applied to rst RF bandpass lter 70, which lters the received signal to the frequency range around its carrier frequencies.
According to this embodiment of the invention, after bandpass lter 70, the ltered signal is applied to low-noise ampli er (LNA) 72, which ampli es the signal
by on the order of 20 dB with a noise gure of 2 dB or less; the ampli ed signal is again ltered by bandpass lter 74, about the same frequency band as
bandpass lter 70. However, bandpass lter 74 need not have the ultra-high Q value provided by a SAW lter, as conventionally used as discussed above. Rather,
an integrated on-chip lter may be used to realize bandpass lter 74. The preferred realization of bandpass lter 74 is a conventional LC lter, in which the
capacitor is embodied in the integrated circuit on-chip with subsampling receiver 50, and in which the parasitic induction of the integrated circuit bond wires
serves as the inductor element of lter 74.
[0046] Second LNA 76 ampli es the signal again, for example with a gain of on the order of 22 dB with a noise gure of 4 dB or less, followed by another instance of RF
bandpass ltering by lter 78. Filters 70, 74, 78 not only remove the broadband noise described above relative to FIG. 5b, but also remove any noise added or
ampli ed by LNAs 72, 76. As a result of the operation of lters 70, 74, 78, and LNAs 72, 76, an ampli ed band-limited RF signal is produced. FIG. 5d illustrates
the frequency spectrum of this signal, illustrating that the broadband noise originally received (FIG. 5c) is also band-limited (NRFI′). The ampli ed band-limited RF
signal presented by lter 78 is then sampled by sample-and-hold circuit 80 realized by switch 81 and capacitor 83. Switch 81 samples the output of bandpass
lter 78 by closing at sampling frequency fs. As described above, the Nyquist criterion requires that this sampling frequency fs be at least twice the information
bandwidth BW in the input signal RFI. According to this rst embodiment of the invention, as will be described in further detail below, simple digital mixers (85)
are used to generate the output baseband signal. This further constrains the sampling frequency fs to: f S = RF M + 0.25
[0047] where RF is the nominal carrier frequency of input signal RFI, and where M is an integer, and which will correspond to the multiple of the sampling frequency f s
nearest the frequency of input signal RFI. For example, for an input signal frequency of 1575 MHz, as is typical in wireless communications, an integer M value of
19 and a sampling frequency fs of 81.84 MHz are suitable values. This sampling frequency well exceeds the requirement of twice the bandwidth (e.g., on the
order of 2 MHz) For these frequencies, it is contemplated that capacitor 83 may have a size that is on the order of 4 pF, assuming that the resistance of switch
81 is on the order of 25 Ω. These component values are reasonable for integrated circuit implementation.
[0048] The effect of sample and hold circuit 80 is to provide a signal that includes the original RF signal and also a near baseband alias to the input of ampli er 82.
Referring back to FIGS. 5a and 5 b, the signal applied to ampli er 82 by sample and hold circuit 80 includes the near baseband alias RFINBB, as shown in FIG. 5e.
However, because of bandpass lters 70, 74, 78, the noise level NRFI is not additively present within this near baseband frequency range, because these
bandpass lters eliminate noise from frequencies outside of the passband, so that the signal-to-noise ratio of the near-baseband alias RFINBB does not degrade
due to the sampling process, as shown in FIG. 5e.
[0049] The sampled analog values are applied to the input of ampli er 82. According to this preferred embodiment of the invention, ampli er 82 is realized as a
switched capacitor ampli er, to reduce the dynamic range over which digitization is to be performed (for example to a range of on the order of 40 dB). However,
ampli er 82 need not operate at RF, because of the down-converting performed by sample and hold circuit 80. In addition, ampli er 82 need not be particularly
large, given the relatively low frequencies of the near-baseband alias. The noise gure of ampli er 82 ought to be lower than 20 dB, however, so that the signal-
to-noise ratio of the received transmission is not degraded; the gain of ampli er 82 is preferably about 45 dB.
[0050] Analog-to-digital converter (ADC) 84 receives the ampli ed output form ampli er 82, which corresponds to a sequence of analog samples of the near-baseband
alias of the input signal RFI. ADC 84 also can be relatively simple, such as a seven-bit ADC, considering that its operation is con ned to the near-baseband
frequencies and that the dynamic range at its input is only about on the order of 40 dB. The output of ADC 84 is a sequence of digital words, corresponding to
the sampled analog signal.
[0051] Digital mixers 85 then perform the nal downconversion of the digital signal from near-baseband to baseband. According to this embodiment of the invention, in-
phase I and quadrature Q components are produced, which together correspond to the in-phase and quadrature components of the quadrature amplitude
modulation (QAM) input signal. Quadrature digital mixer 85Q downconverts the near-baseband signal to baseband by multiplying the digital values with a
sequence of values {−1, 0, +1, 0, −1, . . . } applied at a frequency that is one-fourth the sampling frequency fs at which sample and hold circuit 80 closes switch
81. Similarly, in-phase digital mixer 85I downconverts the same near-baseband digital signal to baseband by applying a sequence of values {0, +1, 0, −1, . . . },
also at one-fourth the sampling frequency fs, but phase-shifted by 90° from the sequence used by quadrature digital mixer 85Q. The outputs of digital mixers 85I,
85Q are low-pass ltered by digital lters 86I, 86Q, respectively, to produce the baseband in-phase and quadrature components I, Q, respectively. The effective
frequency spectrum of the output of digital mixers 85I, 85Q, after ltering by respective digital lters 86I, 86Q, is illustrated in FIG. 5f, as baseband signal RFIBB.
Again, the noise NRFRFI″ is not cumulative, but instead is within a reasonable signal-to-noise ratio.
[0052] Another concern in connection with this embodiment of the invention is in connection with the jitter on the sampling frequency f s clock. As known in the art, the
maximum tolerable jitter is inversely proportional to the RF center frequency of the input signal RFI. It has been discovered, however, that the jitter requirement is
somewhat less constrained according to this embodiment of the invention, for example relative to a stand-along analog-to-digital conversion, primarily because
the jitter noise level is proportional to the signal level, permitting a constant signal-to-jitter-noise ratio that can be incorporated into the design. This constant
ratio effectively reduces the dynamic range for the jitter time calculation, relaxing the jitter constraint. More speci cally, one can use the relationship of jitter time
tj: t j = 10 ( SNR j - 10 log OSR 20 ) 2 2 π f in
[0053] where SNR j is the dynamic range of the jitter, where OSR is the ratio of the sampling frequency fs to bandwidth BW, and where fin is the maximum input
frequency to sample and hold circuit 80. For example, an SNRj of 45 dB, at a sampling frequency fs of 81.82 MHz, bandwidth of 2 MHz, and an input frequency fin
of 1575 MHz, yields a jitter time tj of 2.5 psec, which is readily attainable from conventional clock circuits.
[0054] According to this rst preferred embodiment of the invention, therefore, an RF receiver suitable for use as a CDMA or WCDMA receiver is provided, in which the
lters and ampli ers may be realized by way of conventional integrated circuits. Speci cally, high-Q RF lters such as SAW lters are not required, and DC offset
is avoided. Furthermore, analog mixers are not necessary in this receiver, which further simpli es the design, as well as the chip area and manufacturing cost,
along with reduced power consumption. In addition, the critical components of the analog-to-digital converter, and also some ampli ers, need not be designed
for RF performance, but rather can be optimized for relatively low frequencies, such as the near base-band. In addition, the ease of producing a sub-sampling
receiver, in which the sample-and-hold function can operate at relatively low frequencies, is attained without the usual problem of additive folded broadband
noise that conventionally accumulates in subsampling applications.
[0055] Referring now to FIG. 7, the construction and operation of subsampling receiver 50′ according to a second preferred embodiment of the invention will now be
described in detail. According to this second embodiment of the invention, each of the in-phase and quadrature components I, Q have their own sample-and-hold
circuits, and as such avoids the necessity for digital mixers. In addition, as will become apparent from this description, subsampling receiver 50′ is particularly
well-suited for use in a multi-mode WCDMA receiver.
[0056] Antenna A is connected to duplexer 88, as shown in FIG. 7; as known in the art, duplexer 88 is a conventional circuit that combines both the transmit and receive
signals over antenna A. Duplexer 88 attenuates the received signal from antenna A by on the order of 3 dB, as is typical. In this embodiment of the invention,
signals received from antenna A via duplexer 88 are ampli ed by LNA 90, having a gain of on the order of 20 dB and a noise gure of 2 dB, and are ltered by RF
bandpass lter 92. The ltered ampli ed signals are then applied to an input of LNA 94. As suggested by the dashed line in FIG. 7 corresponding to a chip
boundary, it is contemplated that duplexer 88, LNA 90, and RF bandpass lter 92 may be realized off-chip, relative to LNA 94 and the remainder of the functions
of subsampling receiver 50′, which are preferably implemented on a single integrated circuit.
[0057] LNA 94 is a second low-noise ampli er, applying a gain of on the order of 22 dB and having a noise gure of 4 dB. At this point, noise on the received signal is
band-limited to frequencies in the RF range of the payload bandwidth, for example as illustrated in FIG. 5d discussed above. According to this embodiment of the
invention, the output of LNA 94 is separately sampled by sample and hold circuits 96I, 96Q to produce each of the in-phase and quadrature component outputs I,
Q, respectively. Each of sample and hold circuits 96I, 96Q include a respective switch 97I, 97Q and capacitor 98I, 98Q, for effecting the sample and hold
operations. Switch 97I in sample and hold circuit 96I is closed at sampling frequency fs, while switch 97Q in sample and hold circuit 96Q is also closed at
sampling frequency fs but at a 90° phase shift relative to switch 97I in sample and hold circuit 96I. As in the previously described example, sampling frequency fs
is much lower than the RF center frequency, but is at least twice the bandwidth BW of the incoming signal, to satisfy the Nyquist criterion relative to the
modulating signal of interest. According to this embodiment of the invention, sampling frequency fs is selected so that the center frequency of the input RF
signal is an integer multiple of sampling frequency fs. For example, a preferred sampling frequency fs of 40.37 MHz is a good choice for an RF center frequency
of 2140 MHz. The analog values sampled by each of sample and hold circuits 96I, 96Q have spectra including not only the RF signal and its band-limited noise,
but also aliases of the signal and noise at each integer multiple of sampling frequency fs, as shown in FIG. 5e discussed above.
[0058] Each of the in-phase and quadrature legs of subsampling receiver 50′ process their sampled signals to produce the respective baseband in-phase and
quadrature output signal components I, Q. Referring to the in-phase leg, sample and hold circuit 96I is coupled to low pass lter 100I, which is preferably an
analog low-pass lter having a cutoff frequency su cient to isolate the baseband alias (FIG. 5f). The ltered analog signal is then applied to switched-capacitor
ampli er 102I, having a gain of about 54 dB and a noise gure of about 20 dB, which ampli es the analog signal to present a usable dynamic range of on the
order of 40 dB to analog-to-digital converter (ADC) 104I. ADC 104I, which may be on the order of a seven-bit ADC, converts the ltered analog baseband alias to
a stream of digital words corresponding to the in-phase component I of the modulated received signal. Similarly, in the quadrature leg, analog low pass lter
100Q lters the aliased sampled analog signal to baseband; this ltered signal is ampli ed by switched-capacitor ampli er 102Q, and digitized by ADC 104Q to
produce quadrature component Q of the modulating incoming signal.
[0059] In-phase and quadrature components I, Q are therefore related to one another by a relative phase shift of 90° relative to one another, considering the phase
difference in the switching of their respective sample-and-hold circuits 96I, 96Q. These components thus correspond to the quadrature phase signals in the
modulating QAM signal, and thus correspond to the payload of the communication. The effect of LNAs 90, 94 raise the power level of the incoming RF signal
su ciently to overcome the thermal noise of sample and hold circuits 96I, 96Q. In addition, no lter is included between LNA 94 and sample and hold circuits 96,
because it is contemplated that the broadband noise added by LNA 94 will be much less than the total input noise prior to sample and hold circuits 96, and thus
is not a signi cant problem in this embodiment of the invention.
[0060] As evident from this description, sample and hold circuits 96 must be operable so as to not attenuate signals at up to the maximum RF bandwidth, while
sampling at the relatively low sampling frequency fs. At RF frequencies of up to on the order of 2140 MHz for WCDMA communications having bandwidths of 4
MHz, an example of sample and hold circuits 96 would include capacitor 98 of about 3.5 pF and switch 97 with an on resistance of about 20 Ω; this construction
would result in sample and hold noise power of about −70 dBm, which is suitable at these frequencies.
[0061] Similarly as discussed above relative to the rst preferred embodiment of the invention, the clock jitter t j of sample and hold circuits 96 is also of concern. As
before, the jitter requirement for subsampling receiver 50′ corresponds to: t j = 10 ( SNR j - 10 log OSR 20 ) 2 2 π f in
frequency to sample and hold circuit 80. For example, an SNRj of 35 dB, at a sampling frequency fs of 40.37 MHz, bandwidth of 4 MHz, and an input frequency fin
of 2140 MHz, yields a jitter time tj of 3 psec, which is readily attainable from conventional clock circuits.
[0063] According to this second preferred embodiment of the invention, numerous advantages are enabled in the receiving of RF signals, such as used in WCDMA
communications. In addition to the bene ts of not requiring the use of SAW lters or analog mixers, and avoiding DC offset, this second embodiment of the
invention also does not require the use of digital mixers. This further simpli es the design of the subsampling receiver, reduces the power consumption of the
circuit, and also reduces the chip area required for the receiver and thus reducing its manufacturing cost. These bene ts are attained without the usual problem
of additive folded broadband noise that conventionally accumulates in subsampling applications.
[0064] According to a third preferred embodiment of the invention, subsampling receiver 50″ illustrated in FIG. 8 will now be described in detail. This particular
architecture uses a SAW lter at RF frequencies, as will become apparent, but still achieves notable performance and cost advantages over conventional
WCDMA receivers.
[0065] As illustrated in FIG. 8, signals received at antenna A are received at duplexer 110. As conventional in the art, duplexer 110 combines both signals to be
transmitted and signals received at antenna A. As such, the frequency spectrum of signals received by duplexer 110 include both relatively strong signals in the
transmit band as well as signals in the receive band, and noise over all frequencies. Duplexer 110 serves to eliminate much of the unwanted spectrum from the
signals at antenna A. FIG. 9a illustrates the frequency spectrum of signals at antenna A, while FIG. 9b illustrates the spectrum at the output of duplexer 110 as
coupled to the input of rst low noise ampli er (LNA) 112. As evident from a comparison of these spectra, duplexer 110 performs signi cant ltering of these
signals, while retaining signi cant power in both of the RF transmit and receive bands.
[0066] LNA 112 is a low noise ampli er, providing low noise ampli cation of the signal from duplexer 110. This ampli ed signal is applied to SAW lter 114, which
effects a band pass ltering of the ampli ed signal, effectively removing much of the power from the transmit band while retaining the received signal in the
received RF band, as shown in FIG. 9c. This bandpass ltered signal is applied to one input of analog RF mixer 116, which downconverts the bandpass RF signal
from its RF frequency (e.g., on the order of 2140 MHz for WCDMA) to an intermediate frequency, for example on the order of 90 MHz, based upon the mixing of
the ltered received signal with a local oscillator signal LO, in the conventional manner. It is contemplated that the output of mixer 116 will be over a relatively
wide frequency range, a portion of which will contain the bandwidth of the RF received signal of interest. The output of mixer 116 is then applied to automatic
gain control circuit (AGC) 118, to equalize the amplitude over the various frequencies. Sample and hold circuit 120 then receives the ampli ed signal, and
samples this analog signal at a sampling frequency fs, in the manner described above. The determination of this sampling frequency fs will now be described in
detail, based on the bandwidth of the signal and the bandwidth of the received RX band, and also the selection of the intermediate frequency.
[0067] For example, consider a signal bandwidth BW S of 5 MHz and a receive bandwidth BWR of 60 MHz, within which the signal bandwidth BWS can reside. At one
extreme, if the signal bandwidth BWS resides in the upper end of the 60 MHz receive bandwidth BWR, the channel can be moved in frequency to as low as 30
MHz before frequencies from the lower frequency end of the receive bandwidth BWR wrap around 0 Hz and distort the signal at the upper end of the receive
bandwidth BWS. This sets the minimum center frequency for the signal bandwidth BWS at 30 MHz. At the other extreme, the signal bandwidth BWS may
alternatively reside in the lower 5 MHz of the receive bandwidth BWR. Centering the signal bandwidth BWS at 30 MHz, as required from the rst extreme case, the
non-signal portion of the receive bandwidth BWR (which is 55 MHz) will extend from 32.5 MHz to 87.5 MHz. In order for sampling to occur without destructive
aliasing into the signal bandwidth BWS centered at 30 MHz, the minimum sampling frequency fs must therefore be 120 MHz, because this sampling rate will fold
the frequencies from 60 MHz to 87.5 MHz into the frequencies from 32.5 MHz to 60 MHz, which does not disturb the signal bandwidth BWS that extends over
the 5 MHz from 27.5 MHz to 32.5 MHz. Finally, assuming a sampling frequency fs of 120 MHz, the intermediate frequencies of 90 MHz and 120 MHz become
available to downconvert the 5 MHz signal bandwidth BWS to 30 MHz (i.e., the difference between the sampling and intermediate frequencies). Between these
two frequencies, 90 MHz is the preferred intermediate frequency, to reduce the jitter requirements (as will be noted below).
[0068] It is contemplated that those skilled in the art having reference to this speci cation will be readily able to adopt similar analysis for selecting the sampling and
intermediate frequencies used according to this third preferred embodiment, for implementations using other signal and receive bandwidths.
[0069] At these frequencies, it is of course important that sample and hold circuit 120 must be operable up to the intermediate frequency bandwidth. Assuming an on-
resistance of 50 Ω for the switch, a capacitance of 8 pF will be suitable in this application. It is contemplated that the sample and hold thermal noise will be on
the order of −81 dBm, for a WCDMA bandwidth of 4 MHz and a sampling frequency fs of 120 MHz.
[0070] In this example, as described above, the output of sample-and-hold circuit 120 thus presents the received input channel of interest at frequencies centered at 30
MHz. Because the sampling frequency fs (120 MHz) is not twice the intermediate frequency (90 MHz) in this example, aliases will be present in the spectrum at
this point. The frequency planning described above, however, ensures that the channel of interest is not distorted. It is contemplated, however, that some noise
from mixer 116 and AGC 118 will also fold from the aliases into the channel of interest. According to this embodiment of the invention, however, no band pass
ltering is needed within subsampling receiver 50″ in the intermediate frequency band (i.e., after mixer 116). Because of the band-limiting of noise performed by
RF SAW lter 114, however, it is contemplated that the noise folded into the channel of interest, due primarily to mixer 116 and AGC 118, will be relatively small
(e.g., on the order of 0.3 dB).
[0071] Analog FIR lter 122 receives the sampled analog signals from sample-and-hold circuit 120. According to this embodiment of the invention, analog FIR 122
reduces the level of adjacent channel interference, and applies its output to switched capacitor ampli er (SCA) 124. The combination of FIR 122 and SCA 124 is
to reduce the dynamic range of the sampled analog signals to a range that can be readily digitized by ADC 130, of reasonable complexity. For example, it is
contemplated that the dynamic range of the signal at the output of SCA 124 is on the order of 55 dB.
[0072] ADC 130 according to this embodiment of the invention is a band-pass Σ-Δ analog-to-digital converter, digitizing at sampling frequency fs (e.g., 120 MHz), which
is of course the same frequency at which sample-and-hold circuit 120 samples the intermediate frequency signal. Referring now to FIG. 10, the construction of
ADC 130 according to this embodiment of the invention will now be described.
[0073] ADC 130 receives an input signal at the non-inverting input of comparator 140; a feedback signal is applied to the inverting input of comparator 140, as will be
noted below. The output of comparator 140, presenting a signal corresponding to the difference between the input signal and the feedback signal, is band-pass
ltered by bandpass lter 142, and then applied to 1-bit quantizer 144. Quantizer 144 is a conventional 1-bit quantizer, for issuing a decision signal
corresponding to the level of the bandpass ltered difference signal from comparator 140, with the decisions clocked at sampling frequency fs. The quantized
output is the feedback signal applied to comparator 140, and is also forwarded to digital low-pass lter and decimator 146. Considering that the quantization
frequency (at fs) is signi cantly higher than the frequency of the channel of interest (e.g., centered at about 30 MHz), the output of the quantizer will be an
oversampled bitstream. Filter and decimator 146 will therefore reduce adjacent channel interference, and present a digital output corresponding to the channel
of interest. It is contemplated that the digital words output by ADC 130 will have ten bits of resolution, considering an input dynamic range of on the order of 55
dB.
[0074] According to this preferred embodiment of the invention, bandpass lter 142 in ADC 130 replaces the conventional lowpass lter that is typically used in sigma-
delta ADCs when the band of interest is from DC to an upper frequency limit. However, because the signal being digitized is near-baseband, rather than at
baseband, bandpass lter 142 enhances the signal-to-noise ratio over the channel of interest, e.g., the 5 MHZ frequency band centered at about 30 MHz.
[0075] Referring back to FIG. 8, the digital signal from ADC 130 is applied to a pair of digital mixers 132, for generating the digital baseband output in the form of in-
phase and quadrature components I, Q. Digital mixer 132I multiplies the digital output from ADC 130 with a sequence {−1, 0, +1, 0, . . . }, presented at a frequency
of one-fourth the sampling frequency fs. Similarly, digital mixer 132Q multiplies the digital output from ADC 130 with a sequence {0, +1, 0, −1 . . . } that is also at
fs/4, but which is shifted in phase 90° from the sequence applied by digital mixer 132I. The effect of digital mixers 132 is to downconvert the digital signal to
baseband. The sequences are ltered by respective digital low-pass lters 134I, 134Q, to generate the output digital components I, Q, respectively, with reduced
adjacent channel interference.
[0076] As before, jitter time t j for subsampling receiver 50″ may be de ned as: t j = 10 ( SNR j - 10 log OSR 20 ) 2 2 π f in
frequency to sample and hold circuit 1210. For example, an SNRj of 50 dB, at a sampling frequency fs of 120 MHz, bandwidth of 4 MHz, and an input frequency
fin of 90 MHz, a jitter time tj of 21 psec. This jitter time is very relaxed relative to the other embodiments of this invention, due primarily to the downconversion to
the intermediate frequency. Of course, the jitter time of 21 psec is easily attainable in conventional clock circuits.
[0078] Subsampling receiver 50″ provides similar advantages as the embodiments of this invention described above. In summary, this implementation eliminates the
need to have an expensive, off-ship, SAW lter for the intermediate frequencies; indeed, it is apparent that no ltering in the intermediate frequencies is required
at all. This signi cantly simpli es the design of the subsampling receiver, reduces the power consumption of the circuit, and also reduces the chip area required
for the receiver and thus reducing its manufacturing cost. These bene ts are attained without the usual problem of additive folded broadband noise that
conventionally accumulates in subsampling applications, and in avoiding DC offset as conventionally occurs in direct conversion receivers. Subsampling
receiver 50″ according to this embodiment of the invention is well-suited for WCDMA communications.
[0079] While the present invention has been described according to its preferred embodiments, it is of course contemplated that modi cations of, and alternatives to,
these embodiments, such modi cations and alternatives obtaining the advantages and bene ts of this invention, will be apparent to those of ordinary skill in the
art having reference to this speci cation and its drawings. It is contemplated that such modi cations and alternatives are within the scope of this invention as
subsequently claimed herein.
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11/13/2018 US20020181614A1 - Subsampling RF receiver architecture - Google Patents

Subsampling RF receiver architecture

Family: US (1) EP (1) JP (1)

2002-03-19 US10102428 Active

2002-12-05 US20020181614A1 Application

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1. 1. A subsampling receiver, comprising:

3. 3. The receiver of claim 1, further comprising:

5. 5. The receiver of claim 3, further comprising:

8. 8. The receiver of claim 3, further comprising:

9. 9. The receiver of claim 1, further comprising:

11. 11. The receiver of claim 9, further comprising:

12. 12. The receiver of claim 9, further comprising:

14. 14. The receiver of claim 1, further comprising:

a quantizer, for quantizing the ltered error signal; and

wherein the feedback signal corresponds to the quantized error signal.

17. 17. A wireless communications unit, comprising:

a subsampling receiver, comprising:

22. 22. The communications unit of claim 21, further comprising:

a quantizer, for quantizing the ltered error signal; and

wherein the feedback signal corresponds to the quantized error signal.

27. 27. The method of claim 25, further comprising:

33. 33. The method of claim 25, further comprising:

downconverting the modulated signal to an intermediate frequency; and

bandpass ltering the error signal;

quantizing the ltered error signal; and

low pass ltering the quantized error signal;

wherein the feedback signal corresponds to the quantized error signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

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