Nama : Bayu Abi Pamungkas

NIM : 165060300111007
LAB 3
3.1 Comparator dan ROM
Program Utama
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity comparator is
Port ( A : in STD_LOGIC_VECTOR (1 downto 0);
B : in STD_LOGIC_VECTOR (1 downto 0);
less : out STD_LOGIC;
equal : out STD_LOGIC;
greater : out STD_LOGIC);
end comparator;

architecture comparator_op of comparator is

begin
less <= ((not A(1)) and (not A(0)) and b(0)) or ((not A(0))
and B(1) and B(0)) or ((not A(1)) and B(1));
equal <= (A(0) xnor B(0)) and (A(1) xnor B(1));
greater <= (A(0) and (not B(1)) and (not B(0))) or (A(1) and
(not B(1))) or (A(1) and A(0) and (not B(0)));
end comparator_op;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ROM_3x2 is
Port(ROM_addr : in STD_LOGIC_VECTOR(2 downto 0);
ROM_data : out STD_LOGIC_VECTOR( 1 downto 0)
);
end ROM_3x2;

architecture behavioral of ROM_3x2 is

type rom is array (0 to 3) of STD_LOGIC_VECTOR (1 downto 0);

constant MY_ROM : rom :=(

0 => "00",
1 => "01",
2 => "10",
3 => "11"
);
begin
process(ROM_addr)
begin
case ROM_addr is
when "000" => ROM_data <= MY_ROM(0);
 when "001" => ROM_data <= MY_ROM(1);
when "010" => ROM_data <= MY_ROM(2);
when "100" => ROM_data <= MY_ROM(3);
when others => ROM_data <= "00";
end case;
end process;
end behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity compRom is
Port (A : in STD_LOGIC_VECTOR(1 downto 0);
B : in STD_LOGIC_VECTOR(1 downto 0);
O : out STD_LOGIC_VECTOR(1 downto 0));
end compRom;

architecture compRom_op of compRom is

component comparator is
Port ( A : in STD_LOGIC_VECTOR (1 downto 0);
B : in STD_LOGIC_VECTOR (1 downto 0);
less : out STD_LOGIC;
equal : out STD_LOGIC;
greater : out STD_LOGIC);
end component;
component ROM_3x2 is
Port(ROM_addr : in STD_LOGIC_VECTOR(2 downto 0);
ROM_data : out STD_LOGIC_VECTOR( 1 downto 0)
);
end component;
signal less, equal, greater : STD_LOGIC;
begin
comp : comparator port map(
A => A,
B => B,
less => less,
equal => equal,
greater => greater
);
rom : ROM_3x2 port map(
ROM_addr(0) => less,
ROM_addr(1) => equal,
ROM_addr(2) => greater,
ROM_data => O
);
end compRom_op;

Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 ENTITY compRom_tb IS
END compRom_tb;

ARCHITECTURE behavior OF compRom_tb IS

COMPONENT compRom
PORT(
A : IN std_logic_vector(1 downto 0);
B : IN std_logic_vector(1 downto 0);
O : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;

signal A_sig : std_logic_vector(1 downto 0) := (others => '0');

signal B_sig : std_logic_vector(1 downto 0) := (others => '0');
signal O_sig : std_logic_vector(1 downto 0);

BEGIN

uut: compRom PORT MAP (

A => A_sig,
B => B_sig,
O => O_sig
);
stim_proc: process
begin
wait for 10 ns;
wait for 10 ns; A_sig <= "00"; B_sig <= "00";
wait for 10 ns; A_sig <= "01"; B_sig <= "00";
wait for 10 ns; A_sig <= "00"; B_sig <= "01";
wait for 10 ns; A_sig <= "10"; B_sig <= "01";
end process;

END;

Hasil Simulasi

Pada program ini dibuat perbandingan antara a dan b, apabila a=b maka
o=10, apabila a>b maka o=11, apabila a<b mama o=01, dan selain
persyaratan tersebut o=00. Dari hasil simulasi menunjukkan program
sudah berhasil melakukan hal tersebut.

3.1 Multiplier 2 bit dengan ROM

Program Utama
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplierRomImplement is
 Port (
a, b : in STD_LOGIC_VECTOR (1 downto 0);
ROM_data : out STD_LOGIC_VECTOR (3 downto 0)
);
end entity;

architecture Behavioral of multiplierRomImplement is

type rom is array (0 to 6) of STD_LOGIC_VECTOR (3 downto 0);
signal ROM_addr : STD_LOGIC_VECTOR (2 downto 0);
constant MY_ROM : rom :=(
0 => x"0",
1 => x"1",
2 => x"2",
3 => x"3",
4 => x"4",
5 => x"6",
6 => x"9"
);
begin
process (a,b)
begin
if (a = "00") and (b = "00") then
ROM_addr <= "000";
elsif (a = "00") and (b = "01") then
ROM_addr <= "000";
elsif (a = "00") and (b = "10") then
ROM_addr <= "000";
elsif (a = "00") and (b = "11") then
ROM_addr <= "000";
elsif (a = "01") and (b = "00") then
ROM_addr <= "000";
elsif (a = "01") and (b = "01") then
ROM_addr <= "001";
elsif (a = "01") and (b = "10") then
ROM_addr <= "010";
elsif (a = "01") and (b = "11") then
ROM_addr <= "011";
elsif (a = "10") and (b = "00") then
ROM_addr <= "000";
elsif (a = "10") and (b = "01") then
ROM_addr <= "010";
elsif (a = "10") and (b = "10") then
ROM_addr <= "100";
elsif (a = "10") and (b = "11") then
ROM_addr <= "101";
elsif (a = "11") and (b = "00") then
ROM_addr <= "000";
elsif (a = "11") and (b = "01") then
ROM_addr <= "011";
elsif (a = "11") and (b = "10") then
ROM_addr <= "101";
 elsif (a = "11") and (b = "11") then
ROM_addr <= "110";

end if;
end process;
process (ROM_addr)
begin
case ROM_addr is
when "000" => ROM_data <= MY_ROM(0);
when "001" => ROM_data <= MY_ROM(1);
when "010" => ROM_data <= MY_ROM(2);
when "011" => ROM_data <= MY_ROM(3);
when "100" => ROM_data <= MY_ROM(4);
when "101" => ROM_data <= MY_ROM(5);
when "110" => ROM_data <= MY_ROM(6);
when others =>
end case;
end process;
end Behavioral;

Test Bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY multiplierRom_tb IS
END multiplierRom_tb;

ARCHITECTURE behavior OF multiplierRom_tb IS

COMPONENT multiplierRomImplement
PORT(
a : IN std_logic_vector(1 downto 0);
b : IN std_logic_vector(1 downto 0);
ROM_data : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

signal a_sig : std_logic_vector(1 downto 0) := (others => '0');

signal b_sig : std_logic_vector(1 downto 0) := (others => '0');
signal ROM_data : std_logic_vector(3 downto 0);

BEGIN
uut: multiplierRomImplement PORT MAP (
a => a_sig,
b => b_sig,
ROM_data => ROM_data
);
stim_proc: process
begin
wait for 10 ns; a_sig <= "00"; b_sig <= "00";
wait for 10 ns; a_sig <= "01"; b_sig <= "01";
wait for 10 ns; a_sig <= "10"; b_sig <= "11";
 wait for 10 ns; a_sig <= "11"; b_sig <= "11";
end process;

END;
Hasil Simulasi

Simulasi menunjukkan hasil perkalian antara a dan b yang masing-masing

2 bit dan hasilnya pada rom_data. Dari hasil simulasi menunjukkan
program sudah berhasil melakukan perkalian.

Implementasi pada FPGA

File UCF
net "a(0)" loc = "k17";
net "a(1)" loc = "k18";
net "b(0)" loc = "h18";
net "b(1)" loc = "g18";
net "ROM_data(0)" loc = "k14";
net "ROM_data(1)" loc = "k15";
net "ROM_data(2)" loc = "j15";
net "ROM_data(3)" loc = "j14";

Hasil Implementasi

Hasil

a b

Implementasi pada board FPGA menggunakan sw0 dan sw1 sebagai input a
dan sw2 dan sw3 sebagai input b. Hasil perkalian a dan b ditampilkan
pada LED0 – LED3