462 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-7, NO.

6, DECEMBER 1972

A Precision Monolithic Time-Delay Generator for Use

in Automotive Electronic Fuel Injection Systems
WILLIAM l?. DAVIS ANDTHOMAS .&l. FREDERIKSEN

tu
Abstract—A high-performance low-cost IC time-delay generator
has been developed to be used as a building block for automotive
electronic fuel injection systems. Time-delay accuracies are achieved
by employing the IC to precisely control both the reset time and ‘K V02
the initial ramp voltage of an external RC voltage sweep circuit Ic o~
“+ TIME DELAY ..-
by means of a gated voltage regulator. Reference information, GENERATOR L
tz t
derived from the rotating distributor shaft, triggers an input flip-flop REFERENCE V03
POINT /
that controls a reset generator to produce the required gating pulses. OS
-..
The resulting exponential voltage sweep is sensed at the input of L
three externally programmable voltage comparators that provide *3 ‘

three separate time-delayed output signals within a *l-percent INPUT OUTPUTS

accuracy from —40° to + 125°C. This technique is contrasted to a Fig. 1. Basic function of the IC time-delay generator.
linear voltage sweep approach which offers less desensitivity to IC
parameter variations.
shaft has passed a point of reference and then to provide
I. INTRODUCTION three separate time-delayed output signals that can be
LECTRONIC fuel injection is presently being used to trigger events in the associated fuel-injection
considered as an important aid in reducing the system. Since there are two points of reference per shaft
E
detrimental exhaust emissions of the automobile. rotation, there will also be two corresponding sets of
The complex functional requirements and the accuracy time delays; one for each 180° of rotation. For optimum
to which the system must perform, both initially and system performance, these two sets of time delays should
over a given temperature range, place stringent demands be matched to within +1 percent over the temperature
on the performance specifications that would be difficult range from – 40 to + 125°C. The initial tolerance of
to achieve economically with the use of discrete circuitry. the IC parameters should be minimized to reduce the
Integrated circuits, however, offer a large number of amount of adjustment required to achieve the initial
transistors, good component matching, and thermal time-delay intervals; and, once established, these intervals
tracking, all at low cost, which can be used to provide should experience less than ~ 1 percent change due to
excellent system performance. These Ic electronic IC parameter variations over the defined temperature
systems can thus be competitive with other techniques range. Finally, to achieve all of these design objectives
that reduce exhaust emissions, from both an economic at the lowest possible cost was the basic design goal
and a performance standpoint. stressed in the development of this IC.
In a fuel-injection system, it is desirable for certain
events to take place after an accurate delay in time from III. TIME-DELAY GENERATION
when a spot on the rotating distributor shaft has passed One method to generate accurate time delays is shown
a point of reference. To provide this function economically, in Fig. 2. This technique employs a reset switch S, a linear
a precision IC time delay generator has been developed, voltage sweep circuit (current source 1 in combination
which is capable of generating three separate time-delayed with capacitor C), an initial sweep voltage E, and three
output signals with accuracies of ~ 1 percent from —40° voltage comparators Cl, CS, and C’s.When the distributor
to + 125”C, and provides the automobile manufacturer rotates to the point of reference, the switch closes and
an economic building block for use in automotive electronic discharges the capacitor to the initial sweep voltage.
fuel-injection systems. After a given reset time At (when the capacitor is fully
discharged) the switch will open, allowing the current
II. PRIMARY DESIGN GOALS source to charge the capacitor from this initial sweep
The basic function of the IC time delay generator voltage at a fixed rate. The three comparator output
(Fig. 1) is to sense when a spot on the rotating distributor signals occur when the voltage across the sweep capacitor
increases to the respective comparator reference voltages
and thus produces the desired time-delayed outputs.
Manuscript received April 17, 1972; revised June 30, 1972.
W. F. Davis is with the Motorola Semiconductor Products
Division, Phoenix, Ariz. 85036. A. Linear Voltage Sweep
T. M. Frederiksen was with the Motorola Semiconductor Products
Division, Phoenix, Ariz. He is now with the National Semiconductor For the linear voltage sweep shown in Fig. 3, the
Corporation, Santa Clara, Calif. 95051. expression for the time delay tl is
DAVIS AND FREDERIKSEN : MONOLITHIC TIME-DEL.AYGENERATOR 463

+ 0, injection systems is approximate y 3 ms and the maximum

Q v~~
delay is about 100 ms. This timing range can be typically
.- VI achieved by allowing the capacitor voltage to ramp
1 1
RESET from an initial value of about 1 V to a maximum value
SWITCH I 02
Q (limited by the minimum automotive battery voltage)
C2 V2
of approximately 9 V. According to (2) and (3), the
lNITIAL SWEEP + s
VO?.TAGE_ N!’ ‘+ +5+ greatest pkrcent effect occurs in the shortest required
I E
- Ic 03
time delay interval when the difference voltage
=

VOLTAGE SWEEP
CIRCUIT
T
/-:-’ ~
V3
[(V, + @) – 1!?]is a minimum. This minimum value will
be 240 mV for the 3-ins time delay, since the linear slope
cOMPARATORS K, can now be defined as 12.5 ins/V. From (2), the worst
Fig. 2. Basic time-delaygenerator. case variation of &3 mV in the comparator offset voltage
(Darlington differential inputs) would produce a +l.5-
percent variation in the 3-ins time delay [1]. Also, for
a maximum variation of + 1 percent in the initial sweep

-4 b
voltage, a +4-percent change would occur in this same
1’ minimum delay interval, from (3). Thus, the required

E“-- --- VI -—- *l-percent time delay accuracy over the defined tem-
s v+
‘:2 c
perature range is difficult to achieve using this linear

1’
=
E

tl
t
voltage sweep technique not only because of the required
+ l-percent linear current source accuracy, but also
I
since the small variations in the comparator offset voltage
and the initial sweep voltage produce large errors in
(a) (b) the smallest time delay interval.
Fig. 3. ‘1’ime-delaygenerationusinga linearvoltage sweep genera- To reduce these IC parameter variations to a satis-
tor. (a) circuitry. (b) Resnlting waveform. factory level for this application, additional circuit
complexity would be required and a substantially larger
t, = At + K[(V, + r$) – E] (1) die area would result. This makes this linear voltage
sweep approach uneconomical, especially in view of the
where tight tolerance specifications and thus, other approaches
At reset switch closure time, were considered.
K slope of the linear voltage ramp (K = I/C),
B. Exponential Voltage Sweep
VL comparator reference voltage,
E initial sweep voltage, By replacing the precision current source with an
@ comparator offset voltage. external precision resistor, the external resistor–capacitor
sweep circuit that results can produce a precision expo-
The reset time At must be considerably smaller than the nential voltage sweep to again produce the desired time
second term of (1) to ensure that the maximum At variation delays, Fig. 4 [2]. The general expression for the time
will always produce less than a &l-percent change in the delay t, is
smallest time delay interval. In addition, variations in the
linear slope K, and thus the current source I, must always V.. – E
(4)
be within +1 percent, since the time delay is directly ‘L= At+ Rcln [ V.C–(V, *4) 1
proportional to these quantities. The normalized change where
in this time delay due to a change in the comparator
offset voltage is described by R external resistor value,
C external capacitor value,
(2) Voc positive supply voltage,
and the remaining parameters are as previously defined.
The normalized change due to variations in the initial The reset time At is again assumed negligible with respect
sweep voltage can also be written as to the second term of (4). The time delay, from (4), is
&w – AE essentially independent of the supply voltage V., provided
(3) the initial sweep voltage and the comparator reference
t, ‘( V,+ 1$) -E”
voltage are both referenced to V... The normalized
The term associated with time At has been omitted since change in this time delay due to a change in the com-
it is dominated by the linear voltage sweep term. parator offset voltage is described by
To evaluate (2) and (3), the magnitude of the pa-
rameters must be determined from the constraints of ~- Ad
t, =
. (5)
the fuel injection system. In general, the shortest required V,. – E
crankshaft referenced time-delay interval for most fuel ‘v” – ‘v’ * 4)] ln [ v,. – (v, * 4)1
464
+v~c
?+
v
(a) (b)
Fig. 4. Time-delay generation using an exponential voltage sweep
generator. (a) Circuitry. (b) Resulting waveform.
Similarly, the normalized change due to a change in the
initial sweep voltage can also be written as
Atl - AE
t, = V,, –E
(Vcc – E) In v,, – (V, 4= j
[ 1
The term associated with the time At has again been
omitted since it is dominated by the RC voltage sweep
term.
The constants used in the linear approach can also
be applied to evaluate (5) and (6), except the relationship
between the comparator reference voltage and the time
delay is exponential as defined by (4). A 24-ins RC time
constant is used to satisfactorily achieve the required
time delays. From (5), the maximum variation of +3 mV
in the comparator offset voltage would produce a +0.6-
percent variation in the 100-ms time-delay interval when
the magnitude of the term [V.c – (Vl + o)] is a mini-
mum, and a &O.3-percent variation in the 3-ins time
delay interval when this term is a maximum. A maximum
variation of &1 percent in the initial sweep voltage can
also be tolerated since a + l-percent variation would
result in the 3-ins time-delay interval according to (6).
This result sharply contrasts the maximum variations
allowed in these parameters with the linear voltage sweep
technique since greater desensitivity to IC parameter
variations is achieved with this exponential approach.
In addition, it is relatively easy for the maximum time-
delay error contributed by the IC to be less than +1
percent, since the maximum variations in the comparator
offset voltage and the magnitude of the initial sweep
voltage can be allowed and the need for a precision
current source on the die is eliminated. This permits
a smaller die area and relaxes the tight tolerance specifica-
tion for the IC to improve both the die yield per wafer
and the number of die available per wafer [3]. Thus, this
exponential voltage sweep technique has a clear advantage
over the linear voltage sweep method, from both an
economic and a performance standpoint and, as a result,
was the approach used in this IC design.
IV. THE RESET SWITCH
The reset switch performs several basic functions. At
the timing reference, it closes to discharge the capacitor
to a precise initial sweep voltage, and remains closed
lorw enough to ensure that the ca~acitor is fullv dis-
+
IEEE JOURNAL OF SOLID-STATECIRCUITS,DECEMBER 1972
+ v~~
GATING
Vcc
WJ
TERMINAL
R INPUT
REFERENCE
OUTPUT
..- VOLTAGE ; ---
F =)
‘~ s *C ~ ‘EGuLATOR *C
= = = =
(a) (b)
Fig. 5. Ideal switch simulation. (a) Desired switching circuit. (b)
,Switching function simulated by a gated voltage regulator.
charged before opening and allowing the capacitor voltage
to sweep. A switch is difficult to realize in the IC tech-
nology, but this switching function can be obtained with
a gated voltage regulator as shown in Fig. 5. At the
(6)
“ timing references, the regulator is gated ON to rapidly
discharge the capacitor to the initial sweep voltage E.
After the time At, the voltage regulator is gated OFF
to allow the capacitor voltage to begin the voltage sweep.
This switching function is ideally realized provided the
variations in the regulator reference voltage and error
voltage produce less than a + l-percent error in the
initial sweep voltage.
V. THE BASIC IC TIME DELAY GENERATOR
The basic IC time-delay generator consists of a control
flip-flop, a reset generator, a voltage regulator, and three
voltage comparators as shown in Fig. 6. Reference timing
information is derived from the distributor shaft and
alternately activates the set and reset inputs, to control
the input flip-flop. The output of this flip-flop is externally
available to provide phase reference information to the
remaining fuel injection circuitry. The reset generator
incorporates one reset capacitor CR to provide an accurate
gating pulse to the voltage regulator for each transition
of the flip-flop. At each timing reference, the transition
of the control flip-flop activates the reset generator to
gate the voltage regulator ON and to discharge the sweep
capacitor to the initial sweep voltage E. After time At,
this gating signal is removed and the resulting exponential
voltage sweep is applied to the inputs of three voltage
comparators, which, in sequence, produce the desired
time delayed outputs.
VI. ACCURACY CONSIDERATIONS
In practice, the initial time delay intervals are deter-
mined by externally adjusting the comparator reference
voltages. Once established, these delay intervals should
not vary more than & 1 percent over the defined tem-
perature range due to changes in the comparator offset
voltage, the reset time, and the initial sweep voltage.
By using the exponential voltage sweep, the maximum
variation in the comparator offset voltage can be tolerated
and thus additional circuit complexity to reduce this
variation is not required. However, the initial sweep
voltage must also be accurate to within + 1 percent,
and thus the voltage regulator circuitry, including the
DAvIS AND FREDERIKSEN : MONOLITHIC TIME-DEL.4YGENERATOR 465

It”- \l [V +
r-–––-––-
I qJ + ‘JLrL
~t. --”\
J&c
E+\
\.+p
$/%’)/+’0’ —.-— —

U,

I I
1 I
lrlc’ I-WI
I

‘1 (
I o o~
~T I I
RESET
I
VOLTAGE o V2
INPUT FLIP FLOP
GENERATOR REGULATOR I
I ‘REF
I
*
RES=
I
I

1- ———— ———

COMPARATORS J

Fig. 6. Basic IC time-delay generator.

reference voltage, must also provide this accuracy. The
reset time At could be made insignificant with respect to
the shortest time delay interval and thus would eliminate
the need for a precision reset generator. Unfortunately,
this time must be greater than the worst case sweep
capacitor discharge time (determined by the discharge
current capability of the voltage regulator) but more
important, it must be sufficiently large to eliminate the
effects of dielectric storage. This results from charge
being stored in the dielectric material while the capacitor
is charged and causes the capacitor voltage to increase
slightly above the initial sweep voltage immediately after
the time interval At, if this interval was not sufficiently
long to drain the charge from both the dielectric material
and the capacitor plates [4]. This effect can cause an
intolerable error in the initial sweep voltage. Unfor-
tunately, a satisfactory reset time that eliminates the
effects of dielectric storage is not always insignificant
with respect to the shortest time delay interval and,
as a result, the reset circuitry must maintain a required
accuracy.
A sufficient reset time interval depends on the dielectric
material and the value of the sweep capacitor. Nor the
required 24-ins time constant of this system, a 0.6&PF
sweep capacitor was employed, since this value is suffi-
ciently large to eliminate the dc loading effects on the
voltage sweep circuitry and small enough to allow rapid
discharge by the voltage regulator—yet permits a satis-
factory reset pulsewidth of only 200 ps. The variations
in this pulsewidth, however, cannot exceed &15 percent,
if variations in the 3-ins time delay are expected to be
less than A 1 percent.
These techniques ensure that for a given set of external
components and a defined temperature range (between
– 40° and + 125”C), the maximum time delay error,
due to parameter variations in the ICI will always be
less than +1 percent (the remaining accuracy will depend
upon the accuracy of the passive components).
A. The Indial sweep Voltage
The reference voltage E for the voltage regulator is
established by a monolithic resistive divider that must
be referenced to the power supply voltage V.., if variations
in V,. are to have a negligible effect on the time delays,
The voltage regulator, shown in Fig. 7, consists of a
noninverting unity gain dc amplifier that incorporates
negative feedback to accurately reproduce the reference
voltage across the sweep capacitor. The frequency stability
of this regulator is maintained by the dominant pole
produced at the output by these external RC components.
At the timing reference, the emitter current to the dif-
ferential amplifier is gated ON and since the capacitor
voltage will be significantly larger than the reference
voltage, a current 1 will enter the base of the Darlington-
connected output transistors, which rapidly discharges
the sweep capacitor to the reference voltage E. After
time At, the emitter current to the differential amplifier
is gated OFF and any loading effect on the capacitor by
the regulator is eliminated to allow the capacitor voltage
to begin an accurate exponential sweep. Additional
loading on the capacitor by the collector leakage current
of the output power transistor is minimized by connecting
a resistor across the base-emitter junction of this power
device to eliminate the beta multiplication of the collector-
base leakage current (Ic,o) and to approximate the
Ic 50 kdW2X current.
B. The Reset Pulse Generator
The reset pulse generator uses one external reset
capacitor, Cm, which is referenced to ground to produce
466 IEEEJOURNAL OF SOLID-STATECIRCUITS,DECEMBER 1972

.
Vcc

fJa
v
I I

j
.-+k t
~MpARATORS
Vz

+ +
‘Z v CR

-T

Fig. 9. Basic reset waveform generator.

Fig. 7. Gated voltage regulator that establishes the initial sweep cl,
voltage E. ——. % —

‘G-t (a)
‘REF
1 +
Vz q ~

~r
v
---1Atl ()
J ,,B = ,
qj
‘

1
%
Vz = I
‘- I
Vz I I (— .—— — =
7j- --1-- - -’ --— I

*t t
I I (b)
— At2 — Fig. 10. Reset waveformgeneratorcircuitry.
I I
I TO VOLTAGE
REGULATOR
v ~
I
c1
INPUT
Vz

L-\ t -- *, *T Vz (REF) ton t

~: t
(c) Atl
-4J
Atl At2 A(2

Fig. 8. Waveforms associated with the reset generator. (a)

Flip-flop waveform. (b)Resetwaveform. (c)Resulting At gating
pulses to reset the voltage regulator. Fig. 11. Reset comparator function.

a reset waveform that linearly ramps alternately between
the voltage Vz and ground potential. In addition, it
incorporates two voltage comparators that are both
referenced to the voltage Vz/2 to produce a regulator
gating pulse for each transition of the input flip-flop.
The waveforms associated with this reset generator are
shown in Fig. 8.
1) The Reset Waveform Generator: The reset waveform
is generated by the basic technique shown in Fig. 9. With
the switch open, the current source I charges the reset
capacitor CE to the voltage clamp Vz. The switch closes
at the first transition of the flip-flop to produce a dis-
charge current, also of value 1 (the difference between
the two current source values) that linearly discharges
DAVIS AND FREDERIKSEN : MONOLITHIC TIME-DBL.4YGENERATOR
To CR
TO F.F.
+ %
=
‘4
Fig. 12.
the capacitor from the voltage Vz to approximately
ground potential. The second flip-flop transition causes
the switch to again open and allows the current sourc!e I
to linearly charge the capacitor from ground potential
back to the voltage Vz. This reset waveform will be
symmetrical provided the discharge current is identical
to the charge current and the maximum variation in
the slope will be proportional to the maximum variation
in these charge and discharge currents.
The circuitry employed to realize this waveform gen-
erator is shown in Fig. 10. The current in the collectors
of the multiple-collector lateral p-n-p transistor Ql,
is derived from a common biasing network and has a
tolerance of less than &15 percent over the defined
temperature range. One of these collector currents is
controlled by a clifferential gate (transistors Qs and QJ,
which contributes a significant base current error IB
to the collector current of transistor Q,. By employing
transistors Q, and Q,, this current is multiplied by 2,
using emitter-area scaling, and is also inverted to produce
the discharge current 2(1 — 1~). Fortunately, h~l? is
characteristically a slow function of temperature for a
lateral p-n-p transistor, and as a result, the base current
contributes less than a ~ l-percent variation in this
discharge current. The charge current also includes this
base current error, since the lateral p-n-p transistor Q,
is connected in series with the second collector of tran-
sistor QI. Thus, the charge and discharge current for the
reset capacitor are both equal to (1 — 1~), and the
467
I
r-4 At F-
tE!L
I -$-
2 1,
t
TO VOLTAGE
REGULATOR
0s
*
Reset comparator circuitry.
maximum variations in these currents will contribute
less than a &15-percent error in the slopes and the
symmetry of the reset waveform.
2) The Reset Comparators: The reset gating pulses for
the voltage regulator are derived from the outputs of
two comparators that are both referenced to Vz/2 and
are alternately gated ON by the flip-flop. The reset wave-
form is applied to the comparator inputs as shown in
Fig. 11. For the first transition of the flip-flop, com-
parator C’, is gated OFF, and comparator C, produces an
output until the reset waveform voltage decreases to
the comparator reference voltage Vz/2. This produces
the gating pulsewidth At,. For the second transition
of the flip-flop, comparator CZ is gated OFF, and com-
parator C, produces an output until the reset waveform
voltage increases to the voltage Vz/2. This produces the
second gating pulse Att.
The reset comparator circuitry, Fig. 12, consists of
two differential comparators (transistors Q, and Q, and
transistors Q, and Q,,), which are both referenced to
V,/2 with the inputs driven out of phase. The emitter
currents for these differential pairs are alternately gated
ON by the flip-flop and the outputs are connected in
parallel to perform the oRing function. The output lateral
p-n-p transistor is activated by the output of either com-
parator to produce the controlled collector current I,
which is used to activate the voltage regulator. These
gating pulses will be symmetrical within ~ 15 percent
(assuming a perfect reset waveform) provided the maxi-
468 IEEE JOURNAL OF SOLID-STATECIRCUITS,DECE)MBER 1972

CR 01 ’32 03

+Vccr ---------- lr----- ----- ----- r

7 r--- 1 :
0 I T 1 T 1 1 . . . I T T T I T T IT T I T I

J15:K
10Kli!
!I
I I I’IWIIJ
1,
II

To
‘1
II
I
1= 1,
I 1,
5’ SK
I II
t I
t ‘1
II
I 2’ 2K
II
GI=TI .
10’
*“!!

::

IL
LZ
I -._
L-L
--s_-j
’-__
COMPARATORS
c

Fig. 13. Complete schematic of IC time-delay generator.

mum variation in the comparator reference voltage is

less than 415 percent.

VII. THE COMPLETEIC TIME DELAY

GENERATOR
The schematic of the IC time delay generator (Fig. 13)
shows the complete circuitry that includes the input
flip-flop, the biasing network, the reset generator, the
voltage regulator, and the three voltage comparators.
The biasing network provides the reset generator with
charge and discharge currents that have total variations
less than &15 percent over temperature. This network
also provides the reset capacitor voltage clamp Vz, the
reset comparator reference voltage Vz/2, and the emitter
currents for the three comparators. The loading effect
Fig. 14. Photomicrograph of the 56 X 61-mil monolithic time-delay
on the sweep capacitor by these output comparators is generator.
minimized by using small biasing currents in the
Darlington-connected differential input stages. Each
comparator also incorporates a differential-to-single-ended the IC—the most significant being the + l-percent
converter in the output to minimize the comparator maximum time delay error due to IC parameter variations
offset voltage and to ensure that the output switch point over the temperature range from —40° to + 125°C:
is essentially independent of temperature. The input
supply volt age range, 7–30 VdO;
flip-flop is triggered by alternately connecting the set
typical bias current (Vcc = 9.5 VJ, 5 mA;
and reset input terminals to + VCC. The input noise
peak capacitor discharge current, 150 mA;
immunity of the flip-flop is 3 V and the output can sink
time delay range, 3–1000 ms;
up to 5 mA of current and incorporates a 5-k~ pull-up
maximum At variation, +7 percent;
resistor.
maximum Ail? variation, &6 mV;
The photomicrograph (Fig. 14) shows the power
time delay accuracy [–40”C < T. < +125”C],
device (in the center of the IC die), which discharges
* 1 percent;
the main sweep capacitor. This relatively large transistor
set-to-set matching [– 40”C < T* < + 125”C], +1
provides a fast discharge capability for the sweep
percent.
capacitor. The wide collector and emitter metal widths
reduce the metal current density and thus improves the
VIII. SUMMARY
reliability. The 13 pad connections allow the IC to be
placed in a standard 14-pin dual-in-line plastic -package. By using the excellent device matching and thermal
The following list indicates the typical performance of tracking that the IC technology affords, a precision
IEEE JOURNAL OF SOLID-STATECIRCUITS,VOL.sC-7,NO. 6,DECEMBER ]972
monolithic IC time delay generator has been built, which
precisely controls the reset time and the initial ramp
voltage o Ean external RC sweep circuit and incorporates
precision voltage comparators to provide three separate
time-delayed outputs with accuracies of +1 percent
from – 40 to + 125”C. This approach eliminates the
need for a linear voltage sweep (and thus a precision
current source on the die), provides greater desensitivit y
to variations in the IC parameter specifications, and
allows a large number of die per wafer and a high die
yield per wafer to provide an economic precision building
block for automotive electronic fuel injection.
An Electronic Gyrator
HANS O. VOORMAN ANDARNOLD
Abstract—After a brief introductionto the gyrator concept, its
realizationas an accuratemonolithicintegratedcircuitis described.
The inherentelectronicproblemsare consideredand performance
criteria are defined. Data are given. Applications,particularlyin
electric filters, are discussed and it is shown that in the lower
frequency range the use of these “semifloating” gyratorscan be
very advantageous.The monolithicintegrationof the gyrator can
be seen”as a major steptowardintegratedselectivity.
INTRODUCTION
A.NY attempts have been made to replace LC
filters by filters which, while maintaining their
M excellent properties [1], do not require big and
costly inductors. A possible method is to replace each
coil by a gyrator terminated in a capacitor.
To replace a coil we need at least another energy
reservoir, e.g., a capacitor. If we compare the equations
for an inductor and a capacitor we see that the role
played by voltage and current is reversed (Fig. 1). To
simulate an inductance with a capacitor we must trans-
form the current ic to a voltage v~ and the voltage VC
to a current i~:
v~ = Rlic i~ = (1/RJvc, (1)
where RI and Rz are resistances. We thus get an in-
ductance L = RIR,C. In this way all normal values of
inductances up to very high values can be simulated
(e.g., R, = R, = 1 Mfl, C = 1 pF gives L = 1 MH).
Fig. 2 shows a circuit realizing (l). Only the signal-
Manuscript received April 20, 1972; revised July 31, 1972.
The authors are with the Philips Research Laboratories, Eind-
hoven, the Netherlands.
469
ACKNOWLEDGMENT
The authors wish to acknowledge the excellent labo-
ratory assistance of D. Culmer and the compact layout
design of A. Smith.
REFERENCES
[1] J. D. Graeme, G. E. Tobey, and L. P. Huelsman, Eds., Operational
A mpl@iers,Design and Applications. New York: McGraw-Hill,
1971, pp. 52-58.
[2] D. S. Babb, Pulse Circuits—switching and Shaping. Engle-
wood Cliffs, N. J.: Prentice-Hall, 1964, pp. 11–21.
[3] M. J. Gay, “Impact of economic considerations on consumer IC
design,” 197$ ISSCC Dig. Tech. Papers, pp. 122–123.
[4] M. Brotherton, Capacitors—Their Use in Electronic Circuits.
New York: Van Nostrand, 1946, ch. 2.
BIESHEUVEL
handling part is indicated. It consists of two differential
stages antiparallel. Each stage is supposed to convert
accurately a voltage into a current. The electronic circuit
(a two-port) together with the capacitor simulates an
inductance L = RIRZC.
If R, = R, the electronic two-port is ‘[lossless” and it
behaves as a gyrator, as defined by Tellegen [2]. The
symbol for a gyrator is shown in Fig. 3.
The differential stages of the gyrator can be integrated
in a monolithic process. For reasons of accuracy, however,
the gyration resistors R, and R, must be connected
exteimally. Hence, a simulated inductance consists of
an integrated circuit, two resistors, and a capacitor,
DESIGN
Many gyrator circuit configurations are known [3]-[5].
We present an accurate integrated realization using only
two external components (R,, RJ. This also gives the
most accurate inductance value for given component
tolerances’ and gives a low noise factor [6], [7].
Our circuit is based on the configuration of Fig, 2, The
inductance value is given by L = RIRZC (1 + 3), where
R,, R,, and C are values of external components and 8 is
the influence (variable, temperature dependent) of the
integrated electronic circuit. 16I must be made much
smaller than the tolerances of RI, Rz, and C, e.g., lower
1 We refer each time to inductance simulation instead of treating
the gyrator as a two-port because it is felt that the ‘very major
part of the applications of the gyrator will be inductance simulation.
In this case we have L = R,R,C but for a different design [5]
L = RIRBRsC/R2, which is somewhat less accurate for the same
component tolerances.