Effect of front and back gates on β-Ga2O3 nano-belt field-effect transistors

Shihyun Ahn, Fan Ren, Janghyuk Kim, Sooyeoun Oh, Jihyun Kim, Michael A. Mastro, and S. J. Pearton

Citation: Appl. Phys. Lett. 109, 062102 (2016); doi: 10.1063/1.4960651

View online: https://doi.org/10.1063/1.4960651
View Table of Contents: http://aip.scitation.org/toc/apl/109/6
Published by the American Institute of Physics

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 APPLIED PHYSICS LETTERS 109, 062102 (2016)

Effect of front and back gates on b-Ga2O3 nano-belt field-effect transistors

Shihyun Ahn,1 Fan Ren,1 Janghyuk Kim,2 Sooyeoun Oh,2 Jihyun Kim,2 Michael A. Mastro,3
and S. J. Pearton4
1
Department of Chemical Engineering, University of Florida, Gainesville, Florida 32611, USA
2
Department of Chemical and Biological Engineering, Korea University, Anam-dong, Sungbuk-gu,
Seoul 136-713, Korea
3
US Naval Research Laboratory, 4555 Overlook Ave. SW, Washington, DC 20375, USA
4
Department of Materials Science and Engineering, University of Florida, Gainesville, Florida 32611, USA
(Received 5 July 2016; accepted 28 July 2016; published online 8 August 2016)
Field effect transistors (FETs) using SiO2 and Al2O3 as the gate oxides for the back and front sides,
respectively, were fabricated on exfoliated two-dimensional (2D) b-Ga2O3 nano-belts transferred
to a SiO2/Si substrate. The mechanical exfoliation and transfer process produced nano-belts with
smooth surface morphologies and a uniform low defect density interface with the SiO2/Si substrate.
The depletion mode nanobelt transistors exhibited better channel modulation with both front and
back gates operational compared to either front or back-gating alone. The maximum transconduc-
tance was 4.4 mS mm1 with front and back-gating and 3.7 mS mm1 with front-gating only
and a maximum drain source current density of 60 mA mm1 was achieved at a drain-source volt-
age of 10 V. The FETs had on/off ratios of 105 at 25  C with gate-source current densities of
2  103 mA mm1 at a gate voltage of 30 V. The device characteristics were stable over more
than a month for storage in air ambient and the results show the potential of 2D b-Ga2O3 for power
nanoelectronics. Published by AIP Publishing. [http://dx.doi.org/10.1063/1.4960651]

There is a significant current interest in the use of two-
dimensional (2D) semiconductors for electronic devices
capable of high speed or low power operation. Graphene
is the most widely studied of these materials,1,2 but the
absence of a band gap under most conditions makes it diffi-
cult to realize conventional channel-layer devices such as
field-effect transistors (FETs).1–3 Alternatives include the
transition metal dichalcogenides (TMDs) WSe2 (Ref. 4) and
MoS2 (Ref. 5) because they generally possess a non-zero
bandgap in 2D form, even though it is typically 1 eV.6–13
This small band-gap limits their ability to be used in high
power applications.
The b-phase of Ga2O3 is a thermally and chemically sta-
ble semiconductor with a bandgap of 4.9 eV (Refs. 12 and
13) and it is attracting interest for use in both electronics for
high power switching and in truly solar-blind UV photode-
tectors. Of course, some of the new-found enthusiasm for the
material must be tempered by the fact that oxides typically
have poor thermal conductivities and also that their electrical
properties can be dominated by native defects. However, the
fact remains that Ga2O3 has a very high theoretical break-
down electric field (8 MV/cm),14 making it of interest for
high power electronics. Indeed, a recent report demonstrated
a 3.8 MV/cm breakdown field in Ga2O3 which surpassed the
bulk critical field strengths of GaN and SiC.15 There have
been a number of reports of transistor structures, including
metal-semiconductor field-effect transistors (MESFETs),
depletion-mode metal-oxide-semiconductor field-effect tran-
sistors (MOSFETs), and Schottky diodes16–19 fabricated on
either bulk or thin film b-Ga2O3. In analogy with the 2D
materials mentioned earlier, as well as single layers of black
phosphorus, the monoclinic structure of bulk b-Ga2O3 crys-
tals should allow cleavage into ultra-thin flakes in the (100)
direction even though b-Ga2O3 is not a van der Waals 2D
material.20,21 Indeed, back-gated transistors fabricated on
200 nm thick exfoliated Ga2O3 nanobelts have been shown
to exhibit very good dc performance up to 250  C, with well-
behaved saturation and transconductance characteristics,
high on-off ratios, and stable operation in air.22 In the work
by Kim et al.,22 the materials characteristics of the exfoliated
material were examined by Raman spectroscopy and atomic
force microscopy, and the high temperature (200  C) charac-
teristics of conventional back-gated FETs were tested.
Hwang et al.23 used what they termed nanomembranes of
20–100 nm thickness obtained by mechanical exfoliation
from bulk Ga2O3 crystals and transferred these onto a back-
gated Si substrate to demonstrate promising FET perfor-
mance with gate modulation ratio of 107 at a drain voltage
of 20 V, field-effect mobility of 70 cm2/Vs, and a sub-
threshold swing of 200 mV/dec.22
There are still many questions to explore to establish the
potential of Ga2O3 for power electronics in near 2D form of
the type envisaged for the more studied materials,24–28 such
as the influence of Ga2O3 thickness and doping (Sn and Si for
n-type, Mg for p-type) on device performance since we might
expect that devices based on thinner b-Ga2O3 flakes would
achieve higher on/off ratio but produce lower power opera-
tion. The effect of surface states would play an important role
in ultra-thin b-Ga2O3 based devices due to increased carrier
scattering.28 The dependence of modulation of the transistor
channel on the type of gating is also of interest. The use of
nanobelts does offer the ability to tailor the thermal properties
through the choice of substrate onto which they are trans-
ferred and currently there is limited availability of epitaxial
sources on semi-insulating substrates. The use of top-gated
transistor geometries on these nanobelt devices is preferred
because the thinner gate dielectric allows the use of a lower
gate voltage to achieve the same electric field strength, and a

0003-6951/2016/109(6)/062102/4/$30.00 109, 062102-1 Published by AIP Publishing.

062102-2 Ahn et al. Appl. Phys. Lett. 109, 062102 (2016)

high transistor density can be realized since the gate contacts

are electrically isolated from each other, unlike back-gated
structures.
In this study, thin flakes were mechanically exfoliated
from bulk b-Ga2O3 crystals using the scotch tape method.
The exfoliation process was repeated to obtain ultra-thin
flakes (or nano-belts), which were fabricated into field-effect
transistors (FETs) using conventional photolithography. No
surface protection layer was deposited on the nano-belt dur-
ing the device fabrication, measurement, or subsequent stor-
age. Our work differs from previous reports in which we
examined the effect of using front, back, and both gates on
the dc performance of the FETs. The resulting transistors
exhibited stable source-drain current densities of 60 mA/mm
and better channel modulation when both front and backgat-
ing was employed.
The starting sample was a bulk b-phase Ga2O3 single
crystal with (201) surface orientation (Tamura Corporation,
Japan) grown by the edge-defined film-fed growth method.
Hall effect measurements showed the sample was unintention-
ally n-type with an electron concentration of 3  1017 cm3.
The crystal structure of monoclinic b-Ga2O3 allows a facile FIG. 1. (Top) Schematic of fabricated b-Ga2O3 flake based field effect tran-
cleavage into thin flakes along the (100) direction, which has sistor. (Bottom) Optical image of fabricated device.
a larger lattice constant than other primary directions, i.e., a
[100] ¼ 12.225 Å, b [010] ¼ 3.039 Å, c[001] ¼ 5.801 Å.29,30 device fabrication processes. Note that the flakes are com-
We were able to separate nano-scale thickness b-Ga2O3 flakes posed of a layered structure, and there is no obvious reason
from the bulk b-Ga2O3 crystal by repeated application of the this could not be further exfoliated to few- or bi-layers, or
mechanical exfoliation technique using Scotch tape. This is even a mono-layer film. The selected area electron diffrac-
the same approach used for graphene exfoliation from highly tion pattern of this sample is shown in Figure 2 (bottom),
oriented pyrolytic graphite. The exfoliation process produced
planar Ga2O3 flakes with a thickness of approximately
200 nm. The mechanically exfoliated nano-belts were trans-
ferred to a SiO2/p Si (300 nm/500 lm) substrate. Prior to the
transfer, a back-gate Ti/Au (20 nm/80 nm) electrode was
deposited by electron beam evaporation on the Si substrate.
The b-Ga2O3 nano-belt was processed into an FET via a con-
ventional photolithography process consisting of metallization
by electron beam evaporation and photoresist lift-off. The
source and drain electrodes were defined by a Ti/Au (20 nm/
120 nm) metallization with a source to drain electrode spacing
of 8 lm. 15 nm of Al2O3 deposited by atomic layer deposition
was used as the gate oxide for the front side, while the SiO2
on top of the Si substrate served as the back gate oxide. The
gate length was 1 lm, gate width was 3.5 lm, and gate to
drain distance was 8 lm. A schematic of the device structure
is shown in Figure 1 (top) and an optical micrograph of the
completed device is shown in Figure 1 (bottom).
To characterize the structural quality of the b-Ga2O3
nano-belts,31 we examined the atomic structure and crystal
orientation using transmission electron microscopy (TEM).
The specimen was prepared using a focused ion beam, and
to protect the surface of the samples from Ga-ion bombard-
ments during the FIB fabrication, an additional carbon layer
was deposited above the b-Ga2O3 nano-belts. The dc perfor-
mance of the b-Ga2O3 nano-belt FETs were obtained at
25  C using an Agilent 4155C semiconductor parameter ana-
lyzer connected to a probe station.
Figure 2 (top) shows a high resolution TEM image of FIG. 2. (Top) TEM images of the exfoliated b-Ga2O3 micro-belt deposited
the exfoliated b-Ga2O3. It appears defect-free, and no strain on an SiO2/Si substrate. (Bottom) Selected area electron diffraction pattern
or damage was observed after the transfer and subsequent of the exfoliated b-Ga2O nano-belt.
062102-3 Ahn et al. Appl. Phys. Lett. 109, 062102 (2016)

revealing the lattice symmetry and the lattice parameters

of the exfoliated b-Ga2O3. The pattern corresponds to a
d-spacing of approximately 0.61 nm and a diffraction pattern
of the (200) lattice plane, which confirmed the b-Ga2O3 thin
flake is exfoliated in the [100] a-direction.29,31,32 Similarly,
TEM examination of transferred nano-belts on the SiO2/Si
substrates did not show any observable faults in the interface
between the b-Ga2O3 ultrathin flake and this substrate, con-
firming a van der Waals bonding arrangement in the hetero-
structure. One of the advantages of the exfoliation and
subsequent transfer on the target substrates is the absence of
the strain in the structure.
Figure 3 shows the drain I–V characteristics of the
b-Ga2O3 flake FET with front, back, or both gates opera- FIG. 4. Typical transfer characteristics of b-Ga2O3 flake FET with front or
both gates.
tional at 25  C. There is improved channel modulation with
both gates relative to individual front or back gating. The
drain-source current was effectively modulated by the gate- was observed, which indicates a good quality interface
source voltage with good saturation and sharp pinch-off charac- between the exfoliated b-Ga2O3 nano-belt and the SiO2
teristics, indicating that the channel layer is an n-type semicon- layer. We did not observe any change in electrical character-
ductor. This n-type conductivity is likely due to oxygen istics after storage and subsequent re-measurement over a
vacancies or impurities like Si or Sn which are donors in period of almost one month in an air ambient, as reported
Ga2O3.33,34 The source-drain current density was 60 mA mm1 earlier in studies where Ga2O3 FETs were measured up to
at 10 V when both front and back gating was employed. 250  C.22 This shows the stability of transistors based on
Figure 4 shows transfer characteristics of the b-Ga2O3 b-Ga2O3 in air is an attractive property relative to other
micro-belt TFTs for front or both-gate configurations (for 2D materials such as graphene, MoS2, and black phospho-
clarity, we do not show the backgate curves which rus.35–37 The calculated field-effect mobility (lFE) of
fell between those of the other two cases). The maximum the nano-belt FET was 1.35 cm2 V1 s1, comparable to
transconductance was 4.4 mS mm1 with both gates and
3.7 mS mm1 for the front gate operation. No electrical
breakdown was observed in our measurements up to
VDS ¼ 35 V and VGS ¼ 30 V at 25  C. Figure 5 (top) shows
the gate voltage dependent drain current and gate leakage
current of b-Ga2O3 flake FET with front, back, and both
gates and Figure 5 (bottom) shows the gate I–V characteris-
tics of b-Ga2O3 FET with front, back, and both gates. The
high on/off ratio of 105 (defined as the IDS at VGS ¼ 0 V
divided by the IDS at VGS ¼ 30 V) is an indication of the
quality of charge modulation in the channel as well as the
expected power added efficiency, linearity, noise figure, and
reliability of potential power amplifiers. The drain current
on-off ratio is highly dependent on the reverse gate leakage
current because the drain leakage current is correlated to
reverse gate leakage current in the pinched-off region. No
hysteresis on both the forward and reverse gate bias sweeps

FIG. 5. (Top) Gate voltage dependent drain current and gate leakage current
of b-Ga2O3 flake FET with front, back, and both gates. (Bottom) Gate I–V
FIG. 3. Drain I–V of b-Ga2O3 flake based FET with front, back, and both characteristics of b-Ga2O3 flake based device with front, back, and both
gates at 25  C. gates.
062102-4 Ahn et al. Appl. Phys. Lett. 109, 062102 (2016)

previous reports.22 We used the model of Zhou et al.,38 spe-

cifically developed for depletion-mode devices. Our Ga2O3
FETs have a depletion capacitance that can dominate the
oxide capacitance (Cox) depending on the gate voltage. In
other words, these are bulk conduction channel devices and
there is no inversion layer or sheet charge. As a consequence,
mobility in depletion-mode structures is often overestimated
due to “bulk” mobility contributions to carrier transport.38
The saturation mobility is obtained from the relation38
l ¼ m2/(W/2L) CG, where m is the slope of a regression fit
to the straight line portion of the (ID,SAT)1/2  VG transfer
curve, W is the gate width, L is the gate length, and CG is the
gate capacitance. The device performance can likely be
improved by control of the channel doping, which is possibly
given the recent advances in doping Ga2O3.39–41
In conclusion, n-type, depletion mode b-Ga2O3 nano-
belt FETs with [100] orientation were fabricated on flakes
obtained by mechanical exfoliation from a bulk crystal. A
comparison of front, back, or combined gating showed supe-
rior channel modulation for the latter. The nano-belt FETs
displayed an on/off ratios of 105 at 25  C. In a limited num-
ber of tests, there was no electrical breakdown up to biases
of VDS ¼ þ100 V and VGS ¼ 100 V and the stable perfor-
mance of the front and back-gated FETs shows the potential
of these structures for electronic applications.
The research at Korea University was supported by Basic
Science Research Program (NRF-2015R1D1A1A09057970)
through the National Research Foundation of Korea (NRF)
funded by the Korea Government Ministry of Science, ICT,
and Future Planning.
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