2012 7th International Conference on Electrical and Computer Engineering 438

20-22 December, 2012, Dhaka, Bangladesh

An Ultra Wideband LNA Design and Comparison

Between Different Corner Simulation
Md. Asif Mahmood Chowdhury,1,*
1
Electrical & Electronic Department, Bangladesh University of Engineering & Technology
Dhaka , Bangladesh .
*
asifmahmood200606107@gmail.com

Abstract—An wide-band Low Noise Amplifier (LNA) is

designed with differential output using IBM 90nm CMOS
process. This LNA circuit has a centre frequency of 18.3
GHz . Gain of this designed circuit at the centre frequency
is around 14 dB. It can be operated from around
14.2GHz to around 19.9 GHz with considerably high gain. -
3 dB bandwidth of this LNA is around 5.8 GHz . Power
consumption of this circuit is around 80-100 micro-watt.
Supply voltage of this LNA circuit is 1.4V . This slight
variations in the value of different parameters are found in
different corner simulations of the circuit.
Index Terms—Ultra-wideband, low power consumption,
high gain, high centre frequency , different corner analysis,
cascade stage .

I. INTRODUCTION
Ultra-Wideband (UWB) is a wireless digital
communication system exchanging data using short duration
pulses. Low cost implementation of the UWB promises high
throughput at short distances without interfering with other
existing wireless communication system[1].
In our design, we have proposed a Low Noise Amplifier
(LNA) for a UWB receiver using IBM 90nm CMOS process.
LNA is the first block of the UWB receiver end. It amplifies
the transmitted signal received by the receiving antenna. We
have used CS-CS (Common Source-Common Source)
Cascode stage topology of LNA, as this topology offers
higher gain and bandwidth compared to other topologies of Fig. 1 Schematic of LNA
LNA implementation [2]. We have included differential
output in our design as it gives better immunity against noise Our design is a modified version of a previously
due to supply voltage variation[3]. proposed LNA circuit [4]. There was a current source
After system level analysis, the proposed circuit has been which is replaced by a current mirror circuit. This
simulated in circuit level. In the simulation stage, we have current mirror circuit exist between node 18 and ground .
focused on optimizing LNA parameters like gain, bandwidth, A high pass filter circuit is placed between node 18
center frequency, power consumption etc. From circuit level and node 19. This high pass filter circuit is due to the
simulation, the gain is found to be around 13dB with center elimination of DC offset voltage in the output
frequency of 18.3GHz. The bandwidth is around 5.2 GHz waveform. At the end, our output of the circuit is
which is about 28% of the centre frequency. This is a differential output. We get this differential output from
promising finding since UWB process requires the bandwidth node 20 and node 23.
to be at least 20% of the centre frequency. Besides the power
consumption of our circuit is around 70 microwatts which is III. SIMULATION RESULT
also a optimistic result in terms of power dissipation. For observing the simulation result we have used
In a word, despite being a circuit level simulated design, HSpice A-2008.03 software as a simulator of our circuit.
our design promises to bring out a highly effective LNA We have used rf_9 model of mosfet in our design. We
system through the process of further development. have seen result for different process corners of mosfet.
II. SCHEMATIC DESIGN
Schematic design for our LNA circuit is given
below :

978-1-4673-1436-7/12/$31.00 ©2012 IEEE


We have seen result for different process corners of
mosfet. In a conventional way, process corner is a two
letter designator. The first letter refers to the N-
channel MOSFET (NMOS) corner, and the second letter
refers to the P channel (PMOS) corner. In this naming
convention, three corners exist: typical, fast and slow.
Fast and slow corners exhibit carrier mobility that are
higher and lower than normal, respectively. For example,
a corner designated as FS denotes fast NFETs and slow
PFETs. There are therefore five possible corners: Typical-
typical (TT) , fast-fast (FF), slow-slow (SS), fast-slow (FS),
and slow-fast (SF).
A. Typical Typical (TT) Corner
Different parameters calculated through hspice
simulation for Typical Typical corner are given below .
1) Gain Calculation : Here, centre frequency is 18.3
GHz.
Fig. 2 Frequency Response at output (TT corner)
Gain at centre frequency =20* log10 (Vout/Vin) dB
= 20* log10 (750m/150m) dB
= 13.979 dB
2) Bandwidth Calculation : For finding -3dB
bandwidth we have to find corresponding output
voltage due to gain of (13.979-3) or 10.979 db
Corresponding voltage is 525.93 millivolt.
These following two wave-shapes is representing
two corner frequencies for the calculation of -3dB
point.
Fig. 3 Frequency Response at output (showing cut off frequency value(left)
at -3dB point) (TT corner)
This above graph is showing the cut off frequency
value (left) at -3dB point.
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Fig. 4 Frequency Response at output (showing cut off frequency value(right)
at -3dB point) (TT corner)
From the above two graph, we get two -3dB frequency
limit. They are 20 GHz and 14.2 GHz. So . -3dB
bandwidth is (20-14.2)GHz or 5.8 GHz.
3) Power Consumption : The following curve is
showing the power consumption of our LNA circuit
with the typical-typical process corner.
Fig. 5 Power Consumption vs Frequency Curve (TT corner)
Power consumption of the circuit is 79.13879 microwatt.
This value of power consumption is good enough
considering the purpose of the usage of our circuit.
B. Fast –Fast (FF) Corner
Various parameters calculated through hspice simulation
for Typical Typical corner are given below .
1) Gain Calculation : Centre frequency is 18.3
GHz.
Fig. 6 Frequency Response at output (FF corner)
Gain at centre frequency=20* log10 (Vout/Vin) dB
= 20* log10 (760m/150m) dB
= 14.0944 dB
2) Bandwidth Calculation : For finding -3dB
bandwidth we have to find corresponding output
voltage due to gain of (14.0944-3) or 11.0944 dB
Corresponding voltage is 538.03 millivolt
.
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Fig 10 Frequency Response at output (SS corner)

Fig. 7 Frequency Response at output (showing cut off frequency
value(left) at -3dB point) (FF corner)
This above graph is showing the cut off frequency
value (left) at -3dB point.
Centre frequency is 18.3 GHz as like as previous analysis.
Gain at centre frequency = 20* log10(Vout/Vin) dB
= 20* log10(739.9m/150m) dB
= 13.8628 dB
2) Bandwidth Calculation : For finding -3dB
bandwidth we have to find corresponding output
voltage due to gain of (13.8628-3) or 10.8628 dB
Corresponding voltage is 521.87 milli volt.

Fig 8 Frequency Response at output (showing cut off frequency value(right)

at -3dB point) (FF corner)
From the above two graph, we get two -3dB frequency
limit. They are 19.9 GHz and 14.3 GHz. So . -3dB
bandwidth is (19.9-14. 3)GHz or 5.6 GHz.
3) Power Consumption : The following curve is
Fig 11 Frequency Response at output (showing cut off frequency value(left)
showing the power consumption of our LNA circuit at -3dB point) (SS corner)
with the typical-typical process corner.

Fig. 9 Power Consumption vs Frequency Curve (FF corner)

Fig 12 Frequency Response at output (showing cut off frequency
Power consumption of the circuit is 109.60285 value(right) at -3dB point) (SS corner)
microwatt. Now, it has been observed that power From the above two graph, we get two -3dB frequency
consumption of LNA circuit is changed when we are limit. They are 19.9 GHz and 14.2 GHz. So . -3dB
using fast-fast corner. The value of power consumption bandwidth is (19.9-14. 2)GHz or 5.7 GHz.
is increased when we change the process corner from 3) Power Consumption :
typical-typical process corner to fast-fast process corner.
C. Slow-Slow (SS) Corner
Gain , Bandwidth and power consumption are
determined for slow-slow corner analysis.
1) Gain Calculation :

Fig. 13 Power Consumption vs Frequency Curve (SS corner)

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Power consumption of the circuit is 64.63133
microwatt. Now, it has been observed that power
consumption of LNA circuit is changed when we are
using slow-slow corner. The value of power consumption
is decreased when we change the process corner from
fast-fast process corner to slow-slow process corner.
D. Fast-Slow (FS) Corner
1) Gain Calculation :
From the frequency response curve, we get two -
3db frequency limit. They are 19.9 GHz and 14.2 GHz.
So . -3db bandwidth is (19.9-14.2)GHz or 5.7 GHz
3 ) Power Consumption : Power consumption of the
circuit is 66.14786 microwatt. The value of power
consumption is increased when we change the process
corner from fast-slow process corner to slow-fast process
corner.
F. Result Comparison between Various Corner Simulation
We can compare the results for various corner
simulation having a glance in the following table.
TABLE I
COMPARISON BETWEEN DIFFERENT CORNER SIMULATION

Proces Power -3dB Gain at

s consumption(microwat bandwidt centre
Corner t) h (GHz) frequency(dB
)
Typical 79.13879 5.7 13.979
-typical
Fast- 109.60285 5.6 14.0944
Fig 14 Frequency Response at output (FS corner)
fast
Gain at centre frequency = 20* log10 (Vout/Vin) dB
Slow- 64.63133 5.7 13.8628
= 20* log10 (779.99m/150m) dB
slow
= 14.3200 dB
Fast- 105.68208 5.6 14.3200
2) Bandwidth Calculation : For finding -3dB
slow
bandwidth we have to find corresponding output
Slow- 66.14786 5.7 1.648
voltage due to gain of (14.3200-3) or 11.3200 dB.
fast
Corresponding voltage is 552.19 millivolt.
Using of the frequency response wave-shape from the IV. CONCLUSIONS
Hspice simulation we have found that two cut off
frequencies are 19.9 GHz and 14.3 GHz. So , -3dB This LNA circuit is designed to use in the medical
bandwidth is (19.9-14.3)GHz or 5.6 GHz. application where low power consumption, high gain and
3) Power Consumption : From the simulation result, ultra-wideband bandwidth are required. We have simulated
we have found that power consumption of the circuit is our design in circuit level using rf_9 model in Hspice A-
105.68208 microwatt. Now, it has been observed that 2008.03 Here, we have got very low power consumption,
power consumption of LNA circuit is changed when we high gain and ultra wide bandwidth(bandwidth is more
are using fast-slow corner. The value of power than 20% of centre frequency) from the simulation result
consumption is increased when we change the process ACKNOWLEDGMENT
corner from slow-slow process corner to fast-slow
process corner. This work was greatly supported by BUET central
E. Slow-Fast (SF) Corner library providing different important books and giving a
Power consumption, Gain and Bandwidth are chance to get access to the different important papers on
calculated from the frequency response wave-shape got internet.
from the hspice simulation of slow-fast corner analysis.
1) Gain Calculation :
REFERENCES

[1] 2006 bluetronics.net .[Online]. Available:

http://www.bluetronix.net/Ultra_Wideband_Technology.htm

[2] Choong-Yul Cha , Sang-Gug Lee, “A low power, high gain LNA
topology” , Microwave and Millimeter Wave Technology, 2000, 2nd
International Conference on. ICMMT 2000 p. 420-423
[3] Behzad Razavi Design of Analog CMOS Integrated Circuits . sixteen
reprint 2002 , Tata McGraw- Hill Edition 2002 .
Fig 10 Frequency Response at output (SS corner)
[4] Hangue PARK, Sungho LEE, Jaejun LEE , Sangwook NAM , “A 2.3-7
Gain at centre frequency = 20*log10(Vout/Vin) dB GHz CMOS High Gain LNA using CS-CS Cascode with Coupling C” IEICE
= 20*log10(719.9m/150m) dB TRANS. ELECTRON. ,VOL.E92-C, NO. 8 AUGUST 2009.
= 13.6248 dB
2 ) Bandwidth Calculation : For finding -3dB
bandwidth we have to find corresponding output
voltage due to gain of (13.6248-3) or 10.6248 dB.
Corresponding voltage is 509.71 millivolt.
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