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2, Ju l y 4 , 2 0 1 1
Q u a s i- R e s o na n t PWM
C on t r o ll er
Po we r M an a ge me nt & Su pp l y
N e v e r s t o p t h i n k i n g .
ICE2QS03
Revision History: July 4, 2011 Datasheet
Previous Version: 2.1
Page18 Updated outline dimension
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ICE2QS03
Features Description
• Quasiresonant operation till very low load ICE2QS03 is a quasi-resonant PWM controller
• Active burst mode operation at light/no load for low optimized for off-line switch power supply applications
standby input power (< 100mW) such as LCD TV, CRT TV and notebook adapter. The
• Digital frequency reduction with decreasing load digital frequency reduction with decreasing load
• Power cell for VCC pre-charging with constant enables a quasi-resonant operation till very low load.
current As a result, the overall system efficiency is significantly
• Built-in digital soft-start improved compared to other conventional solutions.
• Foldback correction and cycle-by-cycle peak The active burst mode operation enables an ultra-low
current limitation power consumption at standby mode with small and
• Auto restart mode for VCC Overvoltage protection controllable output voltage ripple. Based on the
• Auto restart mode for VCC Undervoltage protection BiCMOS technology, the product has a wide operation
• Auto restart mode for openloop/overload protection range (up to 26V) of IC power supply and lower power
• Latch-off mode for adjustable output overvoltage consumption. The numerous protection functions give
protection a full protection of the power supply system in failure
• Latch-off mode for Short-winding protection situations. All of these make the ICE2QS03 an
outstanding controller for quasi-resonant flyback
converter in the market.
Wp DO Lf
Cbus Snubber Cf VO
Ws
85 ~ 265Vac RVCC DVCC
CO
CVCC RZC2 RZC1
Wa
Dr1~Dr4
CZC
HV VCC ZC CPS
Power
Q1
Cell
Rb1
CDS
Gate
Zero Crossing Detection Driver GATE Rb2 Rovs1
GND Control Unit
Power Management Optocoupler
Digital Process Block Rc1
Current
CFB Active Burst Mode Limitation
CS
FB Protection Block
RCS Cc1 Cc2
Current Mode Control
TL431
ICE2QS03
Rovs2
CS (Current Sense)
1.2 Package PG-DIP-8 This pin is connected to the shunt resistor for the
primary current sensing, externally, and the PWM
signal generator for switch-off determination (together
with the feedback voltage), internally. Moreover, short-
ZC 1 8 GND winding protection is realised by monitoring the voltage
Vcs during on-time of the main power switch.
GND (Ground)
This is the common ground of the controller.
VVCC
3.3 Normal Operation
VVCCon i ii iii
The PWM controller during normal operation consists
VVCCoff of a digital signal processing circuit including an up/
down counter, a zero-crossing counter (ZC counter)
and a comparator, and an analog circuit including a
current measurement unit and a comparator. The
t1 t2 t switch-on and -off time points are each determined by
the digital circuit and the analog circuit, respectively. As
Figure 3 VCC voltage at start up input information for the switch-on determination, the
zero-crossing input signal and the value of the up/down
The time taking for the VCC pre-charging can then be counter are needed, while the feedback signal VFB and
approximately calculated as: the current sensing signal VCS are necessary for the
V ×C switch-off determination. Details about the full
VCCon vcc operation of the PWM controller in normal operation
t = ------------------------------------------ [1]
1 I are illustrated in the following paragraphs.
VCCch arg e2
where IVCCcharge2 is the charging current from the 3.3.1 Digital Frequency Reduction
startup cell which is 1.05mA, typically.
As mentioned above, the digital signal processing
Exceeds the VCC voltage the turned-on threshold circuit consists of an up/down counter, a ZC counter
VVCCon of at time t1, the startup cell is switched off, and and a comparator. These three parts are key to
the IC begins to operate with a soft-start. Due to power implement digital frequency reduction with decreasing
consumption of the IC and the fact that still no energy load. In addition, a ringing suppression time controller
from the auxiliary winding to charge the VCC capacitor is implemented to avoid mistriggering by the high
before the output voltage is built up, the VCC voltage frequency oscillation, when the output voltage is very
drops (Phase II). Once the output voltage is high low under conditions such as soft start or output short
enough, the VCC capacitor receives then energy from circuit . Functionality of these parts is described as in
the auxiliary winding from the time point t2 on. The VCC the following.
3.3.1.1 Up/down counter threshold voltages, VFBZL and VFBZH, are changed
The up/down counter stores the number of the zero internally depending on the line voltage levels.
crossing to be ignored before the main power switch is
switched on after demagnetisation of the transformer. clock T=48ms
This value is fixed according to the feedback voltage,
VFB, which contains information about the output
power. Indeed, in a typical peak current mode control,
a high output power results in a high feedback voltage, t
and a low output power leads to a low regulation VFB
voltage. Hence, according to VFB, the value in the up/ VFBR1
down counter is changed to vary the power MOSFET
VFBZH
off-time according to the output power. In the following,
the variation of the up/down counter value according to VFBZL
the feedback voltage is explained.
The feedback voltage VFB is internally compared with Up/down t
n+1
n+2
n+2
n+2
n+2
n+1
n-1
three threshold voltages VRL, VRH and VRM, at each counter 1
n
clock period of 48ms. The up/down counter counts then
Case 1 4 5 6 6 6 6 5 4 3 1
upward, keep unchanged or count downward, as
shown in Table 1. Case 2 2 3 4 4 4 4 3 2 1 1
Case 3 7 7 7 7 7 7 6 5 4 1
Table 1 Operation of the up/down counter
Figure 5 Up/down counter operation
up/down counter
vFB
action 3.3.1.2 Zero crossing (ZC counter)
Count upwards till In the system, the voltage from the auxiliary winding is
Always lower than VFBZL
7 applied to the zero-crossing pin through a RC network,
which provides a time delay to the voltage from the
Once higher than VFBZL, but Stop counting, no
auxiliary winding. Internally, this pin is connected to a
always lower than VFBZH value changing
clamping network, a zero-crossing detector, an output
Once higher than VFBZH, but Count downwards overvoltage detector and a ringing suppression time
always lower than VFBR1 till 1 controller.
Set up/down During on-state of the power switch a negative voltage
Once higher than VFBR1 applies to the ZC pin. Through the internal clamping
counter to 1
network, the voltage at the pin is clamped to certain
level.
In the ICE2QS03, the number of zero crossing is The ZC counter has a minimum value of 0 and
limited to 7. Therefore, the counter varies between 1 maximum value of 7. After the internal MOSFET is
and 7, and any attempt beyond this range is ignored. turned off, every time when the falling voltage ramp of
When VFB exceeds VFBR1 voltage, the up/down counter on ZC pin crosses the 100mV threshold, a zero
is initialised to 1, in order to allow the system to react crossing is detected and ZC counter will increase by 1.
rapidly to a sudden load increase. The up/down It is reset every time after the GATE output is changed
counter value is also intialised to 1 at the start-up, to to high.
ensure an efficient maximum load start up. Figure 5
The voltage vZC is also used for the output overvoltage
shows some examples on how up/down counter is
protection. Once the voltage at this pin is higher than
changed according to the feedback voltage over time.
the threshold VZCOVP during off-time of the main switch,
The use of two different thresholds VFBZL and VFBZH to the IC is latched off after a fixed blanking time.
count upward or downward is to prevent frequency
To achieve the switch-on at voltage valley, the voltage
jittereing when the feedback voltage is close to the
from the auxiliary winding is fed to a time delay network
threshold point. However, for a stable operation, these
(the RC network consists of Dzc, Rzc1, Rzc2 and Czc as
two thresholds must not be affected by the foldback
shown in typical application circuit) before it is applied
current limitation (see Section 3.4.1), which limits the
to the zero-crossing detector through the ZC pin. The
VCS voltage. Hence, to prevent such situation, the
needed time delay to the main oscillation signal Dt
should be approximately one fourth of the oscillation
period (by transformer primary inductor and drain-
source capacitor) minus the propagation delay from
thedetected zero-crossing to the switch-on of the main To avoid mistriggering caused by the voltage spike
switch tdelay, theoretically: across the shunt resistor at the turn on of the main
power switch, a leading edge blanking time, tLEB, is
T applied to the output of the comparator. In other words,
osc
Dt = ------------ – t [2] once the gate drive is turned on, the minimum on time
4 delay
of the gate drive is the leading edge blanking time.
This time delay should be matched by adjusting the In addition, there is a maximum on time, tOnMax,
time constant of the RC network which is calculated as: limitation implemented in the IC. Once the gate drive
R ×R has been in high state longer than the maximum on
t = C zc1 zc2-
× -------------------------------- [3] time, it will be turned off to prevent the switching
td zc R +R frequency from going too low because of long on time.
zc1 zc2
required maximum VCS versus various input bus about Active Burst Mode operation are explained in the
voltage can be calculated, which is shown in Figure 6. following paragraphs.
0.6
3.5.3 Leaving Active Burst Mode Operation
300 500 700 900 1100 1300
Iz c(uA)
1500 1700 1900 2100
The feedback voltage immediately increases if there is
a high load jump. This is observed by one comparator.
Figure 7 VCS-max versus IZC As the current limit is 34% during Active Burst Mode a
certain load is needed so that feedback voltage can
exceed VLB (4.5V). After leaving active busrt mode,
3.5 Active Burst Mode Operation maximum current can now be provided to stabilize VO.
In addition, the up/down counter will be set to 1
At light load condition, the IC enters Active Burst Mode
operation to minimize the power consumption. Details
immediately after leaving Active Burst Mode. This is IC is reset and the main power switch is then kept off.
helpful to decrease the output voltage undershoot. After the VCC voltage falls below the threshold VVCCoff,
the startup cell is activated. The VCC capacitor is then
VFB Entering Leaving charged up. Once the voltage exceeds the threshold
Active Burst Active Burst VVCCon, the IC begins to operate with a new soft-start.
Mode Mode
VFBLB In case of open control loop or output over load, the
VFBBOn
feedback voltage will be pulled up . After a blanking
VFBBOff
time of 24ms, the IC enters auto-restart mode. The
VFBEB blanking time here enables the converter to provide a
high power in case the increase in VFB is due to a
Blanking Window (tBEB) t sudden load increase. During off-time of the power
VCS switch, the voltage at the zero-crossing pin is
monitored for output over-voltage detection. If the
voltage is higher than the preset threshold vZCOVP, the
Current limit level IC is latched off after the preset blanking time.
1.0V
during Active Burst If the junction temperature of IC exceeds 140 °C, the IC
Mode
enter into autorestart mode.
VCSB
If the voltage at the current sensing pin is higher than
the preset threshold vCSSW during on-time of the power
VVCC t
switch, the IC is latched off. This is short-winding
protection.
During latch-off protection mode, when the VCC
voltage drops to 10.5V,the startup cell is activated and
the VCC voltage is charged to 18V then the startup cell
VVCCoff is shut down again and repeats the previous procedure.
There is also an maximum on time limitation inside
VO t ICE2QS03. Once the gate voltage is high longer than
Max. Ripple < 1% tOnMAx, it is turned off immediately.
4 Electrical Characteristics
Note: All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are
not violated.
4.3 Characteristics
4.3.9 Protection
Note: The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP
5 Outline Dimension
PG-DIP-8
(Leadfree Plastic Dual In-Line Outline)
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