Experiment sixteen

(N-1/2) frequency divider

First, the purpose of the experiment

1. Master the logic function of the 74193 synchronous four-bit binary reversible counter;
2. Design programmable counter and (N-1/2) divider with 74193

Second, the experimental principle

1, 74193 logic function:
74193 is a synchronous four-bit binary reversible counter; its function is shown in Table 1,
and its conventional symbol and pin diagram are shown in Figure 1:
among them:
(1) Carry signal Co : Co=Q3n . Q2n, Q1n . Q0n . Cpu is: When the counter state is switched
from "1111" to "0000". When the rising edge of the CPU comes, Co outputs a rising edge as
the carry signal;
(2) Borrow signal Bo=Q3n Q2n Q1n Q0n.CPD, the counter state changes from "0000" to
"1111". When the rising edge of CPD comes, Bo outputs a rising edge as a borrow signal.
2. Using 74193 to form a programmable counter;
(1) Figure 2 is a schematic diagram of 74193 composed of programmable counters: when
CPD="1", input clock pulse from Cpu, use NAND gate pair counter output Q3n. Q2n, Q1n.
Q0n to decode, and decode output feedback To the LD
When D3D2D1D0="0000", the counter is the 8421 code programmable N-ary (N=2~16)
addition counter; changing the code logic, it changes the number N, N and the simplified
decoding logic. The relationship is shown in Table 2.
(2) When Cpu = "1", input clock pulse from CPD, use NAND gate pair counter output Q3n.
Q2n, Q1n. Q0n to decode (decoding logic expression self-derived), and decode output
feedback To the LD
When D3D2D1D0="1111", the counter is the 8421 code bias code programmable
subtraction counter; changing the decoding logic changes the hexadecimal number N, please
design a decimal subtraction counter, the decoding logic does not have to be simplified.
(3) When CPD = "1", the clock pulse is input from the CPU, the carry signal Co is fed back to
the LD terminal, and the D3D2D1D0 is changed to form the 8421 bias code programmable
addition counter; the effective state of the circuit is the preset state D3D2D1D0 ( Half clock
cycle) ~ "1111" state (half clock cycle), please design a decimal addition counter
(4) When Cpu="1". Input clock pulse from CPD, feedback the borrow signal Bo to the LD end,
change D3D2D1D0 to group
The 8421 bias code programmable addition counter; the effective state of the circuit is
preset state D3D2D1D0 (half clock cycle) ~ "0000" state (half clock cycle), please design a
decimal subtraction counter
3. 74193 component (N-1/2) divider:
The 74193 component (N-1/2) divider circuit is shown in Figure 3:
(1) The 74193 programmable counter is cycled once, and the decoder outputs a negative
pulse to the LD terminal. At the same time, the negative pulse triggers the T' flip-flop to
make the QT' flip.
(2) QT' and Cp XOR output as programmable counter clock Cpu, ie: Cpu=QT'+Cp
1 When QT'=“0”, Cpu=Cp, the programmable counter is triggered on the rising edge of Cp,
2 When QT'=“1”, Cpu=Cp', the programmable counter triggers flip on the falling edge of Cp
Obviously, in two adjacent cycles of the counter, one cycle is flipped on the rising edge of CP
and the other cycle is flipped on the falling edge of Cp. Therefore, the numerical number N
of the programmable counter is reduced by 1/2 to the original (N-1/2) frequency division.
(3) When D3D2D1D0="0000", the relationship between N and decoding logic in the juice
frequency coefficient (N-1/2) is shown in Table 2.

Third, the experimental instrument

1, an oscilloscope
2, function signal generator 1
3, digital multimeter 1
4, multi-function circuit experiment box 1

Fourth, the experimental content

1. 74193 functional test;
Self-experimental experimental steps, verify its function according to the 74193 function
table:
2. 74193 constitutes a programmable counter:
(1) constitutes a 8421 code hexadecimal addition counter,
Connect the circuit according to Figure 2, let: LD= Q2. When Q1, D3D2D1D0="0000", input
the single pulse P+ (CPD="1") from the CPU, display the output with the LED, and list the
timing of the programming counter. Similarly, change the decoding logic according to Table
2 to verify
(2) constituting a 8421 code subtraction counter;
On the basis of the circuit of Figure 2, when D3D2D1D0="1001" is selected, the single pulse
P+ (Cpu="1") is input from the CPD, and the output is displayed by the digital tube. The
designed LD-end decoding logic is used to verify the designed design. Correctness of the
8421BCD code decimal subtraction counter
(3) 8421 code partial weight code method counter:
On the basis of Figure 2, let LD = Co, from the Cpu Han people single pulse Pt (CPD = "1 "),
use the luminous tube to display the output, press
The D3D2D1D0 designed by the requirement verifies the correctness of the designed 8421
code biased binary addition counter.
3. (N-1/2) upconverter:
(1) Connect the circuit according to Figure 3, use the TTL signal of the function signal
generator (f=100kHz) as the clock Cp, and use the double-track oscilloscope
Observe and record the working waveform of Cp Cpu.Q0, Q1.Q2.Q3, QT', LD;
(2) Change the LD decoding logic, observe the waveforms of Cp and LD, and verify the
relationship between the frequency division coefficient and the decoding logic.

V. Preview requirements
1, Table 2 is the decoding logic of D3D2D1D0="0000" programmable counter simplification,
please write unsimplified
The relationship between the decoding logic and the number N;
2. According to the requirements of Experimental Principle 2, the 8421 code bias code +
radix addition and subtraction counters are designed.

Sixth, the experimental report requirements

1, summarize the logic function of 74193;
2, write the design content of the preview requirements;
3. Draw the working waveform of the experimental content 3 and explain how the circuit
generates the (N-1/2) frequency divider.