module latch_infer (inputA, inputB, inputC, inputD, outputA);

input inputA, inputB, inputC, inputD; output outputA;

reg outputA;
always @ (inputA or inputB or inputC or inputD) begin
if (inputA & inputB) begin
if (inputC | ~inputD) outputA = 1'b1;
else
outputA = 1'bZ;
end
endmodule