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Clock Routing

High-speed digital clocks are among the most difficult signals to route.
A
common problem is how to distribute a clock from some type of source
(an
oscillator or gate output) to several different inputs across the board.
There are
basically two ways to do this: a “starburst” or a “daisy-chain” route.
The starburst
route places the clock source in the center of a “star,” with each clock
load at the
end of a route. The problem here is that each arm of the star is a
transmission
line. If these lines aren’t terminated correctly, the reflections and
ringing will all
combine at the center of the star, and can ruin the clock signal. If you
do terminate
each end of the star, the clock source may not have enough power to
drive
all of the terminations.
The other solution is to route the clock signal in a daisy chain. This is a
single, long route from the source, through each load one by one. The
line should
be terminated at the end to avoid ringing. This is a more difficult way
to route
the clock, but will often give superior results.

Decoupling capacitors:

This type of board has digital circuitry that runs above 20 MHz.
Common components
in this type of design include microprocessors or digital signal
processors,
static or dynamic RAM, flash memory, high-speed programmable logic,
and
complex mixed signal processors. There is often critical timing in the
design,
where signals must arrive within one nanosecond (ns) of each other.
These designs
also usually have large (more than eight bits) address and/or data
busses
which must be connected between chips.
The high-speed operation of these large busses creates tremendous
electrical
noise. When 16 or 32 CMOS lines change state simultaneously, a large
amount
of energy is required from the power supply. The supply cannot provide
the
power fast enough, because of the inherent inductance in even the
best-designed
distribution system. For this reason, power supply decoupling is even
more important.
Every pin which connects to the power supply must have a decoupling
capacitor (0.1 F ceramic is typical). This means that, for a
microprocessor or
DSP chip, there may be as many as 20 decouplers! In addition to the
0.1 F
decouplers on each power pin, you should provide a “bulk” decoupling
capacitor
for each large digital device. This is usually a larger capacitance (10 F
tantalum is typical) to provide an energy store for this hungry digital
chip!

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