Sunteți pe pagina 1din 32

Chapter 3: ARM Instruction Set [Architecture Version: ARMv4T]

A program is the information that you want to convey to CPU / Computing Engine

that you want to convey to CPU / Computing Engine Words ex : Sit, Stand Instruction
that you want to convey to CPU / Computing Engine Words ex : Sit, Stand Instruction

Words ex : Sit, Stand

to convey to CPU / Computing Engine Words ex : Sit, Stand Instruction ex : INC,

Instruction ex : INC, ADD

Sentence Function Paragraph Program
Sentence Function Paragraph Program

Sentence

Function

Sentence Function Paragraph Program
Sentence Function Paragraph Program

Paragraph

Program

ex : INC, ADD Sentence Function Paragraph Program High Level English and similar languages. Ex :
ex : INC, ADD Sentence Function Paragraph Program High Level English and similar languages. Ex :

High Level

ADD Sentence Function Paragraph Program High Level English and similar languages. Ex : A= A+B Medium

English and similar languages. Ex : A= A+B

Medium Level

Mnemonics or Assembly language. Ex : ADD A,B

Low Level

OPCODE Ex : 72 (0111 0010)

Compiler /

Mnemonics or Assembly language. Ex : ADD A,B Low Level OPCODE Ex : 72 (0111 0010)

InterpreterLevel Mnemonics or Assembly language. Ex : ADD A,B Low Level OPCODE Ex : 72 (0111

AssemblerLevel Mnemonics or Assembly language. Ex : ADD A,B Low Level OPCODE Ex : 72 (0111

Machine language Ex : 72 (0111 0010)

Level OPCODE Ex : 72 (0111 0010) Compiler / Interpreter Assembler Machine language Ex : 72
Level OPCODE Ex : 72 (0111 0010) Compiler / Interpreter Assembler Machine language Ex : 72

An instruction is the basic entity of program, using which we convey the information to processor.

Different architecture versions support different instruction set.

Famous ARM7TDMI family of processors belongs to ARMv4T architecture.

ARM7 family of processors normally operates in two states

ARM State (32 bit)

-

58 instructions

Thumb State (16 bit)

-

30 instructions

Each state has its own set of instructions. Developer has to use them in that state only.

In this presentation we will discuss only on instructions of ARM state belonging to ARMv4T

ARM7 family of processors is a 32 bit processor with 32 bit registers and 32 bit instructions. i.e., every instruction in ARM processors is 32 bit in ARM state.

processor with 32 bit registers and 32 bit instructions. i.e., every instruction in ARM processors is

ARM Instruction Syntax

{Label} <Instruction>{CC}{S} <Op_Dest>,{Op_Src1},{Op_Src2},{Barrel shifter operation}

*CC

=>

Condition

*Op_Dest

=>

Operand_Destination

*Op_Src

=>

Operand_Source

*{}

=>

Optional content

- Suffix “S” to any instruction updates the flags in CPSR

Ex : ADDEQS Rd, Rn, Rm, LSL #2

i.e., Rd = Rn + Rm * 4

If

Z=1

Else

Rd = Rd

Conditional Execution

* 4 If Z=1 Else Rd = Rd Conditional Execution Suffix Tested Status Flags Description EQ

Suffix

Tested Status Flags

Description

EQ

Z

set

Equal

NE

Z

clear

Not equal

CS/HS

C

set

Unsigned higher or same

CC/LO

C

clear

Unsigned lower

MI

N

set

Negative

PL

N

clear

Positive or zero

HI

C

set and Z clear

Unsigned higher

LS

C

clear or Z set

Unsigned lower or same

GE

N

equals V

Signed greater or equal

LT

N

not equal to V

Signed less than

GT

Z

clear AND (N equals V)

Signed greater than

LE

Z

set OR (N not equal to V)

Signed less than or equal

Barrel Shifter Operation

to V) Signed less than or equal Barrel Shifter Operation Shift Operation Syntax Logical Shift Left

Shift Operation

Syntax

Logical Shift Left by immediate

Rm, LSL #shift_imm

Logical Shift Left by register

Rm, LSL Rs

Logical Shift Right by immediate

Rm, LSR #shift_imm

Logical Shift Right by register

Rm, LSR Rs

Arithmetic Shift Right by immediate

Rm, ASR #shift_imm

Arithmetic Shift Right by register

Rm, ASR Rs

Rotate Right by immediate

Rm, ROR #shift_imm

Rotate Right by register

Rm, ROR Rs

Rotate Right with Extend

Rm, RRX

Classification of instructions

1.

Data Processing Instruction

-

Data movement , Arithmetic, Logical, Comparison, Multiply

2.

Branch instructions

3.

Load – Store instructions

4.

Single register, Multiple register, Stack operations, Swap

5.

Software interrupt instructions

6.

Program Status Register instructions

7.

Coprocessor Instructions

8.

Loading Constants

1. Data movement instructions

Syntax : <Instruction> {<cond>}{S} Rd, N

Instruction :

MOV

Rd = N

MVN

Rd = ~N

- “S” suffix with MOVE operations can update the C, Z

- “N” can be register or immediate data

- MOV/MVN instruction without barrel shifter operations

Example1 :

Before R1 = 0x00000000 R0 = 0x00000004 MOV R1, R0 After R1 = 0X00000004 R0 = 0X00000004

Example2 :

Before R1 = 0x00000000 MOV R1, #0x04 After R1 = 0X00000004

Example3 :

Before R1 = 0x00000000 R0 = 0x00000004 MVN R1, R0 After R1 = 0XFFFFFFFB R0 = 0X00000004

Example4 :

Before R1 = 0x00000000 R0 = 0x00000004 MOV R1, R0, LSR #1 After R1 = R0 = 0x00000004

Example5 :

Before R1 = 0x00000000 R0 = 0x00000004 MVN R1, R0, LSR #1 After R1 = R0 = 0x00000004

2.

Arithmetic Instructions

Syntax : <Instruction>{<cond>}{S} Rd, Rn, N

Instruction :

ADD

Rd = Rn + N

ADC

Rd = Rn + N + C

SUB

Rd = Rn N

SBC

Rd = Rn N - !C

RSB

Rd = N Rn

RSC

Rd = N Rn - !C

ADD, SUB, RSB instruction(without carry)

Example1 :

Before R2 = 0x00000000 R1 = 0x00000004 R0 = 0x00000003 ADD R2, R1, R0 After R2 = 0x00000007 R1 = 0x00000003 R0 = 0x00000004

Example2 :

Before R2 = 0x00000000 R1 = 0x00000004 R0 = 0x00000003 SUB R2, R1, R0 After R2 = 0x00000001 R1 = 0x00000003 R0 = 0x00000004

ADC, SBC, RSC instruction (with carry)

Example4 :

Before R2 = 0x00000000 R1 = 0x00000004 R0 = 0x00000003 C = 1 ADC R2, R1, R0 After R2 = 0x00000008 R1 = 0x00000003 R0 = 0x00000004

Example5 :

Before R2 = 0x00000000 R1 = 0x00000004 R0 = 0x00000003 C = 0 SBC R2, R1, R0 After R2 = 0x00000000 R1 = 0x00000003 R0 = 0x00000004

Example3 :

Before R2 = 0x00000000 R1 = 0x00000004 R0 = 0x00000003 RSB R2, R1, R0 After R2 = R1 = 0x00000003 R0 = 0x00000004

Example6 :

Before R2 = 0x00000000 R1 = 0x00000003 R0 = 0x00000004

C=0

RSC R2, R1, R0 After R2 = R1 = 0x00000003 R0 = 0x00000004

ADD, SUB instruction(with barrel shifter operation)

Example6 :

Before R2 = 0x00000000 R1 = 0x00000004 R0 = 0x00000003 ADD R2, R1, R0, LSL #1 After R2 = R1 = 0x00000003 R0 = 0x00000004

Example7 :

Before R2 = 0x00000000 R1 = 0x00000004 R0 = 0x00000004 SUB R2, R1, R0, LSR #1 After R2 = R1 = 0x00000003 R0 = 0x00000004

ADD with condition execution and suffix “S”

Example7 :

Before R2 = 0x00000000 R1 = 0x00000004 R0 = 0x00000003 ADDEQS R2, R1, R0, LSL #1 After

R2 = 0x0000000A if Z=1 else 0x00000000 and CPSR is updated

Example8 :

Before R2 = 0x00000000 R1 = 0x00000004 R0 = 0x00000003 ADDS R2, R1, R0, LSL #1 After

R2 = 0x0000000A

and CPSR is updated

3.

Logical instructions

Syntax

: <Instruction> {<cond>}{S} Rd, Rn, N

 

Instruction

: Bitwise logical operations

Sno

Instruction

Syntax

Description

Operation

1 AND

 

AND Rd, Rn, N

Logical AND

Rd = Rn & N

2 ORR

 

ORR Rd, Rn, N

Logical OR

Rd = Rn | N

3 EOR

 

EOR Rd, Rn, N

Logical XOR

Rd = Rn ^ N

4

BIC

BIC Rd, Rn, N

Logical Bit clear

Rd = Rn &~N

AND, ORR, XOR instruction

Example1 :

Before R2 = 0x00000000 R1 = 0x00000001 R0 = 0x0000000F AND R2, R1, R0 After R2 = 0x00000001 R1 = 0x00000001 R0 = 0x0000000F

BIC instruction

Example4 :

Before R2 = 0x00000000 R1 = 0x00000001 R0 = 0x0000000F BIC R2, R1, R0 After R2 = 0x00000000 R1 = 0x00000001 R0 = 0x0000000F

Example2 :

Before R2 = 0x00000000 R1 = 0x00000001 R0 = 0x0000000F ORR R2, R1, R0 After R2 = 0x0000000F R1 = 0x00000001 R0 = 0x0000000F

Example3 :

Before R2 = 0x00000000 R1 = 0x00000001 R0 = 0x0000000F EOR R2, R1, R0 After R2 = 0x0000000E R1 = 0x00000001 R0 = 0x0000000F

Example5 :

Before R2 = 0x00000000 R1 = 0x00000001 R0 = 0x0000000F BICS R2, R1, R0 After R2 = 0x00000000 and Z = 1 R1 = 0x00000001 R0 = 0x0000000F

ORR, EOR instruction with barrel shifter operation

Example6 :

Before R2 = 0x00000000 R1 = 0x00000001 R0 = 0x0000000F ORR R2, R1, R0, LSL #1 After R2 = 0x0000001F R1 = 0x00000001 R0 = 0x0000000F

Example7 :

Before R2 = 0x00000000 R1 = 0x00000001 R0 = 0x0000000F EOR R2, R1, R0, LSL #1 After R2 = 0x0000001F R1 = 0x00000001 R0 = 0x0000000F

4.

Comparison instructions

Syntax

: <Instruction>{cond} Rn, N

Instruction

:TST is logical AND and TEQ is a logical XOR operation

Sno

Instruction

Syntax

Description

Operation

1

CMP

CMP Rn, N

Compare

Rn – N

2

CMN

CMN Rn, N

Compare negate

Rn + N

3

TST

TST Rn, N

Test bits

Rn & N

4

TEQ

TEQ Rn, N

Test for equality

Rn ^ N

- Updates CPSR only without affecting the register content and these can be used in conditional execution

CMP, CMN, TST instruction

Example1 :

Before R1 = 0x00000004 R0 = 0x00000003 CPSR_nzcv CMP R1, R0 After CPSR_nzCv R1 = 0x00000004 R0 = 0x00000003

Example2 :

Before R1 = 0x00000004 R0 = 0x00000003 CPSR_nzcv CMN R1, R0 After CPSR_nzcv R1 = 0x00000004 R0 = 0x00000003

Example3 :

Before R1 = 0x00000004 R0 = 0x00000003 CPSR_nzcv TST R1, R0 After CPSR_nZcv R1 = 0x00000004 R0 = 0x00000003

TEQ instruction without & with barrel shifter operations

Example4 :

Before R1 = 0x00000004 R0 = 0x00000003 CPSR_nzcv TEQ R1, R0 After CPSR_nzcv R1 = 0x00000004 R0 = 0x00000003

Example5 :

Before R1 = 0x00000004 R0 = 0x00000002 CPSR_nzcv TEQ R1, R0, LSL #1 After CPSR_nZcv R1 = 0x00000004 R0 = 0x00000002

5.

Multiply instructions

Multiply instructions uses MAC unit hence they are not associated with the Barrel shifter operations

Operands has to be in the register. i.e., immediate operands are not supported

in the register. i.e., immediate operands are not supported Syntax : MUL{cond} Rd, Rm, Rn  

Syntax

:

MUL{cond} Rd, Rm, Rn

 

MLA{cond} Rd, Rm, Rn, Rs

Instruction

:

For 32 bit resultant operations

Sno

Instrn

Syntax

Description

Operation

1

MUL

MUL Rd, Rm, Rn

Multiply

Rd=Rm*Rn

2

MLA

MLA Rd, Rm, Rn, Rs

Multiply and

Rd=Rm*Rn + Rs

accumulate

MUL , MLA instruction

Example1 :

Before R2 = 0x00000000 R1 = 0x00000004 R0 = 0x00000003

MUL R2, R1, R0

After R2 = 0x0000000C R1 = 0x00000004 R0 = 0x00000003

Example2 :

Before R3 = 0x00000000 R2 = 0x00000003 R1 = 0x00000004 R0 = 0x00000002 MLA R3, R2, R1, R0 After R3 = 0x0000000E R2 = 0x00000003 R1 = 0x00000004 R0 = 0x00000002

Syntax

:

UMULL {cond} RdLo, RdHi, Rm, Rn

UMLAL {cond} RdLo, RdHi, Rm, Rn

Instruction

:

For 64 bit resultant operations

Sno

Instruction

Syntax

Description

Operation

1

UMULL

UMULL RdLo, RdHi, Rm, Rn

Unsigned

[RdHi,

Multiply Long

RdLo]=Rm*Rn

2

UMLAL

UMLAL RdLo, RdHi, Rm, Rn

Unsigned Multiply and accumulate Long

[RdHi, RdLo]=[RdHi, RdLo]+(Rm*Rn)

UMULL , UMLAL calculations

R3

= 0x00000003

R2

= 0x00000000

R1

= 0xF0000002

R0

= 0x00000002

--------------------------------------------------------------------------------------

UMULL R3,R2,R1,R0

= 0x1E0000004

=> R1*R0

R1*R0

= 0x1E0000004

[R3,R2]

= 0x000000003

-------------------------------------------------------------------------------------

UMLAL R3,R2,R1,R0

= 0x1E0000007

=> [R3,R2]+R1*R0

UMULL , UMLAL instruction

Example3 :

Before R3 = 0x00000000 R2 = 0x00000000 R1 = 0xF0000002 R0 = 0x00000002 UMULL R3, R2, R1, R0 After R3 = 0xE0000004 R2 = 0x00000001 R1 = 0xF0000002 R0 = 0x00000002

Example4 :

Before R3 = 0x00000003 R2 = 0x00000000 R1 = 0xF0000002 R0 = 0x00000002 UMLAL R3, R2, R1, R0 After R3 = 0xE0000007 R2 = 0x00000001 R1 = 0xF0000002 R0 = 0x00000002

Syntax

:

SMULL {cond} RdLo, RdHi, Rm, Rn

SMLAL {cond} RdLo, RdHi, Rm, Rn

Instruction

:

For 64 bit resultant signed operations

 

Sno

Instruction

 

Syntax

Description

Operation

1

SMULL

SMULL RdLo, RdHi, Rm, Rn

Signed Multiply Long

[RdHi, RdLo]=Rm*Rn

2

SMLAL

SMLAL RdLo, RdHi, Rm, Rn, Rs

Signed Multiply and accumulate Long

[RdHi, RdLo]=[RdHi, RdLo]+(Rm*Rn)

6.

Branch instructions

Syntax

:

<instruction>{cond} label

 

Instruction

:

Branch instructions alter the execution flow

Sno

Instruction

Syntax

Description

Operation

1

B

B label

Branch

PC = Label

2

BL

BL label

Branch with link

LR = PC

PC = Label

3

BX

BX Rm

Branch Exchange

PC = Rm & 0xfffffffe,

T

= Rm & 1

4

BLX

BLX Rm

Branch Exchange with link

LR = PC

PC = Rm & 0xfffffffe,

 

T

= Rm & 1

B / BX instruction are similar to JUMP instructions and the maximum possible jump is 32MB

BL / BLX instruction are similar to CALL instructions and hence they support subroutine. Return from subroutine is done using instruction MOV PC, LR

BX / BLX instructions are widely used to change the state of the processor from ARM to THUMB and vice versa

BLX instruction also supports label

Ex : BLX Label

Example1 :

Before R0 = 0x00000001 CPSR_nzcvt

BX R0

After

CPSR_nzcvT

7.

Program Status Register instructions

Syntax

:

<instruction>{cond} Rd, <CPSR / SPSR>

Instruction

:

Read / write operation on CPSR / SPSR

Sno

Instruction

Syntax

Description

Operation

1

MRS

MRS Rd, CPSR

Copy CPSR to GPR

Rd = CPSR

2

MSR

MSR CPSR_F, Rd

Copy GPR to CPSR_Field

CPSR_F = Rd

MSR CPSR_F, Rd Copy GPR to CPSR_Field CPSR_F = Rd CPSR_F CPSR_S CPSR_E CPSR_C On reset

CPSR_F CPSR_S CPSR_E CPSR_C On reset , Processor Mode Processor State Interrupts Hence, CPSR_C Default value of CPSR

=> CPSR_Flags [24:31] => CPSR_Status [16:23] => CPSR_Extention [8:15] => CPSR_Control [0:7]

= Supervisor(10011) = ARM state(T=0) = Disabled(I=F=1) = 0xD3 (11010011) = 0x000000D3

MRS, MSR instruction

Example1:

Before R3 = 0x00000000

CPSR=0x000000D3

MRS R0, CPSR After R0 = 0x000000D3

CPSR=0x000000D3

Example2:

Before R3 = 0xF0000000

CPSR=0x000000D3

MSR CPSR_F, R0 After

CPSR=0xF00000D3

R0 = 0xF0000000

MSR instruction also supports immediate value and writing to CPSR is possible only in privileged modes

8.

Load and Store instructions [ Single Register Transfer ]

STORE LOAD
STORE
LOAD

RAM memory address

RAM memory content

0x40000008

88

0x40000007

77

0x40000006

66

0x40000005

55

0x40000004

44

0x40000003

33

0x40000002

22

0x40000001

11

0x40000000

00

5 55 0x4000000 4 44 0x4000000 3 33 0x4000000 2 22 0x4000000 1 11 0x4000000 0

Syntax

: <instruction> {<cond>} Rd, addressing

Instruction

: These are the only instructions that works on the memory.

- LDR instruction copies memory content to the register

- STR instruction copies register content to the memory and it is the only instruction having source operand before the destination operand.

- Point to remember, Memory is byte aligned and registers are word(32bit) size

- There are 8 possible load and store instructions,

- 6 instructions for loading and storing of a unsigned word, half-word and byte values

- 2 instruction for loading signed byte and half-word values

- No load / Store instructions affects CPSR

- No need of signed extension in the store instruction as memory is byte aligned

- LDRSB / LDRSH are the only two sign extension instruction all other instruction append zero to the left of the number hence they are un-singed

Sno

Instn

Description

Syntax

Operation

1

LDR

Load a word from memory into register

LDR R0,[R1]

R0 =

memory32[R1]

2

STR

Store a word from register into the memory

STR R0,[R1]

memory32[R1] =

R0

3

LDRB

Load a byte from memory into register

LDRB R0,[R1]

R0 = memory8[R1]

4

STRB

Store a byte from register content into the memory

STRB R0,[R1]

memory8[R1]=R0

5

LDRH

Load a half-word from memory into register

LDRH R0,[R1]

R0 =

memory16[R1]

6

STRH

Store a half-word from register content into the memory

STRH R0,[R1]

memory16[R1] =

R0

7

LDRSB

Load a signed byte from memory into register

LDRSB R0,[R1]

R0 = Sign extended

memory8[R1]

8

LDRSH

Load a signed half-word from memory into register

LDRSH R0,[R1]

R0 = Sign extended

memory16[R1]

- Load a word to register R0 from RAM memory location 0x40000000

a word to register R0 from RAM memory location 0x40000000 31 01 R0 Mem32[0x40000000] =0x33221100 LDR

31

01

to register R0 from RAM memory location 0x40000000 31 01 R0 Mem32[0x40000000] =0x33221100 LDR and STR

R0

to register R0 from RAM memory location 0x40000000 31 01 R0 Mem32[0x40000000] =0x33221100 LDR and STR

Mem32[0x40000000] =0x33221100

LDR and STR instruction

Example1:

Before R0 = 0x99887766 R1 = 0x40000000 memory32[R1] = 0x33221100

R0 = 0x99887766 R1 = 0x40000000 memory32[R1] = 0x33221100 LDR R0, [R1] After R0 = 0x33221100

LDR R0, [R1]

After R0 = 0x33221100 R1 = 0x40000000 memory32[R1] = 0x33221100

Example2:

Before R0 = 0x99887766 R1 = 0x40000000 memory32[R1] = 0x33221100

STR R0, [R1]

R1 = 0x40000000 memory32[R1] = 0x33221100 STR R0, [R1] After R0 = 0x99887766 R1 = 0x40000000

After R0 = 0x99887766 R1 = 0x40000000 memory32[R1] = 0x99887766

LDRH and STRH instruction

Example3 :

Before R0 = 0x99887766 R1 = 0x40000004 memory16[R1] = 0x2211 LDRH R0, [R1] After R0 = 0x00002211 R1 = 0x40000004 memory16[R1] = 0x2211

LDRB and STRB instruction

Example5 :

Before R0 = 0x99887766 R1 = 0x40000004 memory8[R1] = 0x11 LDRB R0, [R1] After R0 = 0x00000011 R1 = 0x40000004 memory8[R1] = 0x11

Example4 :

Before R0 = 0x99887766 R1 = 0x40000004 memory16[R1] = 0x2211 STRH R0, [R1] After R0 = 0x99887766 R1 = 0x40000004 memory16[R1] = 0x7766

Example6 :

Before R0 = 0x99887766 R1 = 0x40000004 memory8[R1] = 0x11 STRB R0, [R1] After R0 = 0x99887766 R1 = 0x40000004 memory8[R1] = 0x66

LDRSH, LDRSB instruction (MSB/Sign bit gets extended to 32 bit)

Example7 :

Before R0 = 0x99887766 R1 = 0x40000000 memory32[R1] = 0x00008877 LDRSH R0, [R1] After R0 = 0xFFFF8877 R1 = 0x40000000 memory32[R1] = 0x00008877

Example8 :

Before R0 = 0x99887766 R1 = 0x40000000 memory32[R1] = 0x00008877 LDRSB R0, [R1] After R0 = 0x00000077 R1 = 0x40000000 memory32[R1] = 0x00008877

Index methods

Index Method

Data

Base address

Example

register

Post-index

Mem[base]

Base + offset

LDR R0,[R1],#4

Pre-index

Mem[base+offset]

Not updated

LDR R0,[R1,#4]

Pre-index with

Mem[base+offset]

Base + offset

LDR R0,[R1,#4]!

write-back

Addressing modes for Post-indexing methods:

Addressing Modes

Data

Base address

Example

register

Immediate

Mem[base]

Base + offset

LDR R0,[R1],#+4

Register

Mem[base]

Base + offset

LDR R0,[R1],+R2

Register scaled

Mem[base]

Base + offset

LDR R0,[R1],+R2,LSL #2

Same addressing modes are also applicable for Pre-indexing methods

- Barrel shifter operations / Register scaled addressing mode is not supported by singed byte load instructions (LDRSB/LDRSH) and half-word load / store instructions (LDRH/STRH)

- Offset can be + (positive) / - (Negative)

- Pre-index method is used in accessing elements in the data structure. Post and Pre- indexing with write back is used in traversing the array

LDR and STR instruction with post index

Example9 :

Before R0 = 0x99887766 R1 = 0x40000000 memory32[R1] = 0x33221100 LDR R0,[R1],#4 After R0 = 0x33221100 R1 = 0x40000004 memory32[R1] = 0x77665544

Example10 :

Before R0 = 0x99887766 R1 = 0x40000000 memory32[R1] = 0x33221100 STR R0,[R1],#4 After R0 = 0x99887766 R1 = 0x40000004 memory32[0x40000000] =

0x99887766

LDR with pre-index and pre-index with write back

Example11 :

Before R0 = 0x99887766 R1 = 0x40000000 memory32[R1] = 0x33221100

memory32[R1+4]=0x77665544

LDR R0,[R1,#4] After R0 = 0x77665544 R1 = 0x40000000 memory32[R1] = 0x33221100

Example12 :

Before R0 = 0x99887766 R1 = 0x40000000 memory32[R1] = 0x33221100

memory32[R1+4]=0x77665544

LDR R0, [R1,#4]! After R0 = 0x77665544 R1 = 0x40000004 memory32[R1] = 0x33221100

STR with pre-index and pre-index with write back

Example13 :

Before R0 = 0x99887766 R1 = 0x40000000 memory32[R1] = 0x33221100

memory32[R1+4]=0x77665544

STR R0,[R1,#4] After R0 = 0x99887766 R1 = 0x40000000 memory32[0x40000004] =

0x99887766

Example14 :

Before R0 = 0x99887766 R1 = 0x40000000 memory32[R1] = 0x33221100

memory32[R1+4]=0x77665544

STR R0, [R1,#4]! After R0 = 0x99887766 R1 = 0x40000004 memory32[R1] = 0x99887766

LDR instruction pre-index with write-back using Register and Register scaled addressing modes

Example15 :

Before R0 = 0x99887766 R1 = 0x40000000 R2 = 0x00000002 memory32[R1] = 0x33221100

memory32[R1+4]=0x77665544

LDR R0,[R1,+R2]! After R0 = 0x55443322 R1 = 0x40000002 memory32[R1] = 0x55443322

Example16 :

Before R0 = 0x99887766 R1 = 0x40000000 R2 = 0x00000002 memory32[R1] = 0x33221100

memory32[R1+4]=0x77665544

LDR R0, [R1,+R2,LSL #1]! After R0 = 0x77665544 R1 = 0x40000004 memory32[R1] = 0x77665544

9.

Load and Store instructions - [ Multiple Register Transfer ]

Advantage

: Load / Store multiple values in a single instruction

Dis-advantage : Increased Interrupt latency

Syntax : <instruction>{cc}<addressing_mode> Rn{!},<Register/s>

!

=> Write back / update Rn address

Registers

=> {Rn Rm} OR {Rn, Ro, Rp, Rm}

Addressing modes

=> Help to trace through the memory locations / registers

Sno

Instruction

Description

1 LDM

 

Load multiple words from memory into registers

2 STM

 

Store multiple words from registers into the memory

Addressing methods:

Addressing

Data

Start Address

End address

Rn!

Modes

IA

Increment After

Rn

Rn+4*N-4

Rn+4*N

IB

Increment Before

Rn+4

Rn+4*N

Rn+4*N

DA

Decrement After

Rn-4*N+4

Rn

Rn-4*N

DB

Decrement Before

Rn-4*N

Rn-4

Rn-4*N

=> Number of Registers

N

=> Base Register

Rn

Store Multiple

Load Multiple

STMIA

LDMDB

STMIB

LDMDA

STMDA

LDMIB

STMDB

LDMIA

R1=0x40000000C

R1=0x40000000C mem[0x40000000]=0x33221100 mem[0x40000004]=0x77665544 mem[0x40000008]=0xBBAA9988 mem[0x4000000C]=0xFFEEDDCC

mem[0x40000000]=0x33221100

mem[0x40000004]=0x77665544

mem[0x40000008]=0xBBAA9988

mem[0x4000000C]=0xFFEEDDCC

R0=0x400000000

mem[0x4000000C]=0xFFEEDDCC R0=0x400000000 Before R0=0x40000000 R1=0x4000000C R2=0x00000000
mem[0x4000000C]=0xFFEEDDCC R0=0x400000000 Before R0=0x40000000 R1=0x4000000C R2=0x00000000

Before

R0=0x40000000

R1=0x4000000C

R2=0x00000000

R3=0x00000000

R4=0x00000000

mem[0x40000000]=0x33221100

mem[0x40000004]=0x77665544

mem[0x40000008]=0xBBAA9988

mem[0x4000000C]= 0Xffeeddcc

Example18 :

LDMIA R0!,{R2-R4} After

R0=0x4000000C

R2=0x33221100

R3=0x77665544

R4=0xBBAA9988

Example19 :

LDMIB R0!,{R2-R4} After

R0=0x4000000C

R2=0x77665544

R3=0xBBAA9988

R4=0xFFEEDDCC

Example20 :

LDMDA R1!,{R2-R4} After

R1=0x40000000

R2=0x77665544

R3=0xBBAA9988

R4=0xFFEEDDCC

Example21 :

LDMDB R1!,{R2-R4} After

R1=0x40000000

R2=0x33221100

R3=0x77665544

R4=0xBBAA9988

Before

R0=0x40000000

Example22 :

Example24 :

R1=0x4000000C

R2=0x22222222

R3=0x33333333

R4=0x44444444

STMIA R0!,{R2-R4} After

R0=0x4000000C

mem[0x40000000]=0x22222222

mem[0x40000004]=0x33333333

STMDA R1!,{R2-R4} After

R1=0x40000000

mem[0x40000004]=0x22222222

mem[0x40000008]=0x33333333

mem[0x40000000]=0x33221100

mem[0x40000008]=0x44444444

mem[0x4000000C]=0x44444444

mem[0x40000004]=0x77665544

 

mem[0x40000008]=0xBBAA9988

Example23 :

Example25 :

mem[0x4000000C]=

0xFFEEDDCC

STMIB R0!,{R2-R4} After

STMDB R1!,{R2-R4} After

R0=0x4000000C

R1=0x40000000

mem[0x40000004]=0x22222222

mem[0x40000000]=0x22222222

mem[0x40000008]=0x33333333

mem[0x40000004]=0x33333333

mem[0x4000000C]=0x4444444

mem[0x40000008]=0x44444444

10. Stack operations

- There are no specific stack instructions like PUSH and POP in ARM. LDM and STM instructions with proper addressing modes are used to do stack operations.

- Stack can grown up / down in memory i.e., it can Ascending(A) / Descending(D)

- Stack pointer can point to last Filed(F) / Empty(E) memory location

- Monitoring the stack over flow / under flow is the programmers responsibility

Addressing

Descriptions

POP

=LDM

PUSH

=STM

Modes

FA

Full Ascending

LDMFA

LDMDA

STMFA

STMIB

FD

Full Descending

LDMFD

LDMIA

STMFD

STMDB

EA

Empty Ascending

LDMEA

LDMDB

STMEA

STMIA

EB

Empty Descending

LDMEB

LDMIB

STMEB

STMDA

FA =>

F => Full i.e., Stack pointer is pointing to the last filled/used memory location

A => Ascending i.e., Stack memory grows up in memory

Examples are similar to LDM / STM instructions. A change is addressing mode with base address register i.e., SP in this case

11.Swap Instructions

This instruction exchanges a word between a register and memory.

Example:

Before:

R0=0x00000000

R1=0x11112222

R2=0x00008500

Mem32[0x00008500]=0x12345678

SWP R0,R1,[R2] After:
SWP R0,R1,[R2]
After:

R0=0x12345678

R1=0x11112222

;R0=[R2], [R2]=R1, R1=unchanged

Mem32[0x00008500]=0x11112222

These instructions exchanges a word between a register and memory.

- These are an atomic operation i.e., it can not be interrupted by any other instruction.

Syntax : SWP{B}{<cond>} Rd, Rm, [Rn]

Sno

Instrn

Description

Example

Operations

1

SWP

swap a word between memory and a register

SWP R0,R1,[R2]

R0 = mem32[R2]

mem32[Rn] =R1

 

R1 = R1

2

SWPB

swap a byte between memory and a register

SWPB R0,R1,[R2]

R0 = mem8[R2]

mem8[R2] =R1

 

R1 = R1

Example26:

Example27:

Before:

Before:

R0=0x00000000

R0=0x00000000

R1=0x11112222

R1=0x11112222

R2=0x00008500

R2=0x00008500

Mem32[0x00008500]=0x12345678

Mem32[0x00008500]=0x12345678

SWP R0,R1,[R2] After:

SWPB R0,R1,[R2] After:

R0=0x12345678

R0=0x00000078

R1=0x11112222

Software Interrupt Instruction

R1=0x11112222

Mem32[0x00008500]=0x11112222

Mem32[0x00008500]=0x00000022

12. Software Interrupt Instruction

- It is a software exceptions that provides a mechanism for calling operating system routine

provides a mechanism for calling operating system routine - Every SWI instruction is associated with user

- Every SWI instruction is associated with user defined SWI_number

- It forces to change the system mode to supervisory mode

- It sets the PC to 0x08 in the vector table Syntax : SWI{<cond>} SWI_number

Sno

Instrn

Description

Example

Operations

1

SWI

Softer

Interrupt

SWI 0x123456

LR = 0x00008004 {i.e., present PC vlue} CPSR = nzcvqIft_SVC SPSR = nzcvqift_USER PC = 0x00000008 R0 = 0x12

SWI_handler

STMFD sp!, {r0-r12, lr}

LDR r10, [lr, #-4]

; Store registers r0-r12 and the link register

; Read the SWI instruction

BIC r10, r10, #0xff000000

; Mask off top 8 bits

BL service_routine

Branch to service routine with link

; r10 contains the SWI number &

LDMFD sp!, {r0-r12, pc} ; Return from SWI handler

13.Co-processor Instructions

Co-processors are used with ARM processor core for,

Expanding the computation ability(Floating point)

Expanding the controlling ability (Memory Management)

Most of the instructions are co-processor specific but, some instructions works between ARM processor core and co-processor. Few of them are mentioned below,

Instruction

Description

CDP

Coprocessor data processingperform an operation in a coprocessor

MRC / MCR

Coprocessor register transfermove data to/from coprocessor registers

LDC / STC

Coprocessor memory transferload and store blocks of memory to/from a coprocessor

Syntax:

CDP{<cond>} cp, opcode1, Cd, Cn {, opcode2}

<MRC|MCR>{<cond>} cp, opcode1, Rd, Cn, Cm {, opcode2}

<LDC|STC>{<cond>} cp, Cd, addressing

*cp => Co-processor number p0 to p15

*Opcode1 => Operations to take place on co-processor

*Cd => Co-processor destination register

*Cn => Co-processor primary register

*Cm => Co-processor secondary register/extended register

*Opcode2 => Secondary register modifier

Example :

Co-processor 15(P15) is called as system control coprocessor, such as memory management, write buffer control, cache control, and identification registers. It has a register-c0 which contains co- processor identification number.

Copy the content of register-c0 from co-processor P15 to r10 of ARM processor.

14.Loading constants

There is no ARM instruction that moves 32bit constant value to the register.

This is because, ARM instructions are 32 bit in size and hence they can not encode 32bit value in an instruction.

In general maximum immediate value that we can move to register using MOV instruction is 8 bit value i,e, 0xFF

Ex :

1. MOV R0,#0x000000FF works

2. MOV R0,#0xFFFFFFFF does not works

One method of making ex:2 possible is by using MVN instruction i.e., MVN R0,#0x00000000

Other method is to use pseudo instructions like LDR

Pseudo-instruction

LDR r0, =0xff

LDR r0, =0x55555555

ADR r7, lable

Actual instruction

MOV r0, #0xff

LDR r0, [pc, #offset_12]

ADD r7, pc, #offset

* We can observe this in dis-assembler

Syntax: LDR Rd, =constant

ADR Rd, label

Sno

Instruction

Description

Operation

1

LDR

Load constants

Rd=32 bit value

2

ADR

Load address

Rd=32-bit relative address

Ex : 1

STOP

ADR r7,STOP MOV R7,#0x00000002 MOV R2,#0x000000ff B STOP

 

Ex : 2

LDR r0, [pc, #constant_number-8-{PC}] MOV R7,#0x00000002 MOV R2,#0x000000ff constant_number DCD 0x55555555

LDR, LDRH, LDRB, LDM

SWP, SWPB STR, STRH, STRB, STM
SWP,
SWPB
STR, STRH, STRB, STM
LDRSB, LDRSH, AND, ORR, EOR, BIC, ADD, ADC, SUB, SUB BRS B,RS C CMP, CMN,
LDRSB, LDRSH,
AND,
ORR,
EOR,
BIC,
ADD,
ADC,
SUB,
SUB
BRS
B,RS
C
CMP,
CMN,
B,BL,BX,BLX
SWI
TST,
TEQ,
SUB BRS B,RS C CMP, CMN, B,BL,BX,BLX SWI TST, TEQ, MOV, MVN, LDR, ADR, MRS, MSR

MOV, MVN, LDR, ADR, MRS, MSR

MUL, MLA

UMULL, UMLAL

SMULL, SMLAL

LDR, ADR, MRS, MSR MUL, MLA UMULL, UMLAL SMULL, SMLAL CDP, MRC, MCR, LDC, STC ARM

CDP, MRC, MCR, LDC, STC

ARM instruction classification

1. Data Processing instructions(22)

Data Movement(2)

: MOV, MVN

Logical(4)

: AND, ORR, EOR, BIC

Arithmetic(6)

: ADD, ADC, SUB, SUBB, RSB, RSC

Compare(4)

: CMP, CMN, TST, TEQ

Multiply(6)

: MUL, MLA, UMULL, UMLAL, SMULL, SMLAL

2. Branch(4)

: B, BL, BX, BLX

3. Load-Store(12)

: LDR, STR, LDRH, STRH, LDRB, STRB, LDRSB, LDRSH, LDM, STM, SWP, SWPB

4. Software interrupt(1)

: SWI

5. Program Status(2)

: MSR, MRS

6. Co-processor (5)

: CDP, MCR, MRC, LDC, STC

7. Loading constants(2)

: LDR, ADR

Total number of instructions: 48