use ieee.std_logic_arith.

all;
use ieee.std_logic_unsigned.all;

entity semaforo is
port(clk: in std_logic;
rojo, ambar, verde: out std_logic);
end semaforo;

architecture solucion of semaforo is

signal contador: std_logic_vector(5 downto 0);
type ESTADOS is (S0,S1,S2);
signal EP,ES: ESTADOS;
begin
----------------------------------
process(clk)
begin
if rising_edge(clk) then
EP <= ES;
contador <= contador +1;
if contador = 43 then
contador <= (others=>'0');
end if;
end if;
end process;
----------------------------------
process(EP)
begin
ES <= EP;
case EP is
when S0=> ROJO <= '0'; AMBAR <= '0'; VERDE <= '1';
if contador = 20 then ES <= S1; else ES <= S0; end
if;
when S1=> ROJO <= '0'; AMBAR <= '1'; VERDE <= '0';
if contador = 23 then ES <= S2; else ES <= S1; end
if;
when S2=> ROJO <= '1'; AMBAR <= '0'; VERDE <= '0';
if contador = 43 then ES <= S0; else ES <= S2; end
if;
end case;
end process;
end solucion;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity semaforo2 is
port(clk,stop: in std_logic;
rojo, ambar, verde: out std_logic);
end semaforo2;

architecture solucion of semaforo2 is

signal contador: std_logic_vector(4 downto 0);
type ESTADOS is (S0,S1,S2);
signal EP,ES: ESTADOS;
signal rojo2: std_logic;
begin
ROJO <= ROJO2 when contador < 17 or contador > 22 else clk;
 ----------------------------------
process(clk)
begin
if rising_edge(clk) then
EP <= ES;
case EP is
when S0=> contador <= "00000";
when others => contador <= contador +1;
end case;
end if;
end process;
----------------------------------
process(EP)
begin
ES <= EP;
case EP is
when S0=> ROJO2 <= '0'; AMBAR <= '0'; VERDE <= '1';
if stop = '1' then ES <= S1; else ES <= S0; end if;
when S1=> ROJO2 <= '0'; AMBAR <= '1'; VERDE <= '0';
if contador = 2 then ES <= S2; else ES <= S1; end if;
when S2=> ROJO2 <= '1'; AMBAR <= '0'; VERDE <= '0';
if contador = 22 then ES <= S0; else ES <= S2; end
if;
end case;
end process;
end solucion;