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DIGITAL LOGIC DESIGN

( CE_118 )

CHAPTER 3:
Register Transfer
Specification & Design
(part_1)
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Outline
Ø Register Transfer (RT) design:
o FSMD model
o RT specification with
q Static-action tables
q ASM charts
Ø Procedure for synthesis from RT specification
Ø Design Optimization through
o Register sharing
o Functional unit sharing
o Bus sharing
o Unit chaining and Multiclocking
Ø Design Pipelining
o Unit pipelining
o Control pipelining
o Datapath pipelining
Ø Scheduling of flowcharts
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Outline
Ø Register Transfer (RT) design:
o FSMD model
o RT specification with
q Static-action tables
q ASM charts
Ø Procedure for synthesis from RT specification
Ø Design Optimization through
o Register sharing
o Functional unit sharing
o Bus sharing
o Unit chaining and Multiclocking
Ø Design Pipelining
o Unit pipelining
o Control pipelining
o Datapath pipelining
Ø Scheduling of flowcharts
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Register-transfer design
Ø Each standard or custom IC consists of one or more

datapaths and control units.

Ø To synthesize such IC we introduce the model of a FSM

with a datapath (FSMD).

Ø We demonstrate synthesis algorithms for FSMD model,

including component selection, resource sharing,

pipelining and scheduling.
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Design Model

High-level block diagram

Register-transfer-level block diagram

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Ones-counter specification
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FSDM Definition
ØIn chapter 1, we defined an FSM as a quintuple <S, I, O, f, h>
o where S is a set of states, I and O are the sets of input and output symbols:
f : S × I à S (next state) , and h : S × I à O (FSM output)
o More precisely,
q I = A1 × A2 ×…Ak with Ai (1 ≤ i ≤ k) is an input signal
q S = Q1 × Q2 ×…Qm with Qi (1 ≤ i ≤ m) is the flip-flop output
q O = Y1 × Y2 ×…Yn with Yi (1 ≤ i ≤ n) is an output signal

Ø To define a FSMD, we define a set of variables V = V1 × V2 ×…x Vq

which defines the state of the datapath by defining the values of all
variables in each state.
IC: a set of FSM input, ID: a set of datapath input
and I = IC x I D
O = O C x OD OC: a set of FSM output, OD: a set of datapath output

o where IC = A1 × A2 ×…Ak as before and ID = B1 × B2 ×…Bp,

o where OC = Y1 × Y2 ×…Yn as before and OD = Z1 × Z2 ×…Zr.
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FSDM Definition
Ø We can simplify function f : ( S ×V ) × I à S ×V
by separating it into two parts: fC and fD.
o The function fC defines the next state of the control unit
fC : S ×IC × STAT à S
o The function fD defines the values of datapath variables in
the next state, fD : S ×V × ID à V
fD :={fDi : V × ID à V : { Vj =ej | Vj V, ej Expr ( V × ID )}}

Ø Also, we can do the same thing with: h : S ×V × I à O

hC : S ×IC × STAT à OC (external control output)

hD : S ×V × ID à OD (external datapath output)

STAT: set of all status signals --.> relations between variables or experestion of variables
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FSMD specification of Ones-counter

State and output table

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FSMD specification of Ones-counter (cont.)

State and output table

State and output table with variable assignments

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FSMD specification of Ones-counter (cont.)

State and output table with variable assignments

State-action table
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Algorithmic-State-Machine (ASM) chart

Ø Graphic representation of FSMD model

Ø Equivalent to state-action table

Ø Similar to a flowchart used for program description

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ASM Symbols
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ASM rules
Ø Rule 1: The chart must define a unique next state for
each state and set of conditions.
Ø Rule 2: Every path defined by the network of condition
boxes (decision boxes) must lead to another state.

Undefined next state Undefined exit path

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ASM chart for

Ones-counter
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ASM chart for

Ones-counter
-
Custom Data path

State-based (Moore) chart

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State-action tables for Ones-counter

State-based table

D2 = Q2(next) = s2Data’LSB + s3 + s4(Data = 0)

= Q1Q’0Data’LSB + Q1Q0 + Q2Q’0(Data = 0)

D1 = Q1(next) = s1 + s2DataLSB + s4(Data ≠ 0)

= Q’2Q’1Q0 + Q1Q’0DataLSB + Q2Q’0(Data ≠ 0)

D0 = Q0(next) = s0Start + s2DataLSB + s4(Data = 0)

= Q’2Q’1Q’0Start + Q1Q’0DataLSB + Q2Q’0(Data = 0)
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State-action tables for Ones-counter

D2 = Q1Q’0Data’LSB + Q1Q0 + Q2Q’0(Data = 0) S1 = s4 =Q2Q’0
S0 = s1 + s4 = Q’2Q’1Q’0 +Q2Q’0
D1 = Q’2Q’1Q0 + Q1Q’0DataLSB + Q2Q’0(Data ≠ 0)
E = s3 = Q1Q0
D0 = Q’2Q’1Q’0Start + Q1Q’0DataLSB + Load = s1 = Q’2Q’1Q0
Q2Q’0(Data = 0) Done = Output Enalbe
= s5 = Q2Q0

si: state name

Si: control signal of SRwPL

State-based version
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ASM chart for

Ones-counter
-
Custom Data path
(cont.)

Input-based (Mealy) chart

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State-action tables for Ones-counter

Input-based table

D1 = Q1(next) = s1+s2 = Q’1Q0 + Q1Q’0

D0 = Q0(next) = s0Start + s2(Data ≠ 0)’

= Q’1Q’0Start + Q1Q’0 (Data ≠ 0)’
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Logic schematics for Ones-counter

S1 =s2( Data ≠ 0 ) = Q1Q’0( Data ≠ 0 )
D1 = Q’1Q0 + Q1Q’0 S0 = s1 + s2( Data≠0) = Q’1Q0 + Q1Q’0( Data ≠ 0 )
D0 = Q’1Q’0Start + E = s2DataLSB = Q1Q’0DataLSB
Q1Q’0 (Data ≠ 0)’ Load = s1 = Q’1Q0
Done = Output enable = s3= Q1Q0
Input-based version