ECE 242 – Electronic Circuits II

F2018

Course Description
“Electronic circuits and their limitations, including; differential pairs, biasing, the cascode configuration and
active loads. Differential and multistage amplifiers. Feedback, stability and compensation. CMOS logic circuits.”

This course will provide you with intermediate analog circuit analysis and design skills necessary for higher-level
studies in circuits. The Intended Learning Objectives for this course are as follows:

By the end of this course, students should be able to

• Analyze a multistage amplifier circuit to determine its figures of merit
• Design a multistage amplifier circuit based on given requirements
• Use appropriate lab equipment to build, debug, and characterize multistage amplifiers

Level: At least 2B Computer Engineering or Electrical Engineering

Prerequisites: ECE 240 and (ECE 205 or MATH 211). Corequisites: ECE 207

Details of this course syllabus are subject to change throughout the term.

Teaching Team
Course Instructor Prof. Adel Sedra, PEng
Section 1 Email: sedra@uwaterloo.ca
Office: E5 4003, 519-888-4567 x31696
Assistant: Chris Schroeder
Email: cschroeder@uwaterloo.ca
Office: E5 4131, 519-888-4567 x31466
Course Instructor Derek Wright, PhD, PEng
Section 2 Email: derek.wright@uwaterloo.ca
Office: E5 4117, 519-888-4567 x31163
Cell: 226-606-0651 (text preferred)
Lab Instructor Manisha Shah
Email: manisha@uwaterloo.ca
Office: E2 3343, 519-888-4567 x32832
Lecture TA Govindakrishnan (Govind) Radhakrishnan gradhakr@uwaterloo.ca
Lab TA Reza Mohammadi reza.mohammadi@uwaterloo.ca
Ayman Eltaliawy aeltaliawy@uwaterloo.ca
Ala Eldin Omer aeomomer@uwaterloo.ca

Notes and Textbook

• Course website on LEARN
• Required: A. Sedra and K. C. Smith, Microelectronic Circuits, 7th Ed., Oxford University Press, 2014.
ISBN-13: 978-0199339136

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ECE 242 – Electronic Circuits II F2018

Grading
Item Weight Notes
Final Exam† 50% Date and time TBD
Midterm Exam† 25% Date and time TBD
Labs 25%
†Exams are closed book

Schedule
Lecture Dates
• Tuesdays and Wednesdays starting September 11 and ending November 28 in E7 4417
o Section 1: 3:00 pm – 4:20 pm
o Section 2: 10:00 am – 11:20 am
• Extra Lectures: Thursday 9/13, 9/27, 10/18, 11/1, 11/15, and 11/29 in E7 4417
o Section 1: 12:30 pm – 1:20 pm
o Section 2: 11:30 am – 12:20 pm
• Midterm Week: October 22 through 26 (no lectures)

Tutorials
• Thursdays starting September 13 in E7 4417
o Section 1: 3:00 pm – 4:20 pm
o Section 2: 10:00 am – 11:20 am

Office Hours: Tuesdays and Thursdays 11:30 am – 1:30 pm in E5 4417 by appointment via
https://calendly.com/derek-wright/ece-242-office-hours

Detailed Schedule of Lectures

Week Lecture Date Week Lecture Date Week Lecture Date
1 1 Sept 11 5 9 Oct 11* 9 16 Nov 7
1 2 Sept 12 5 10 Oct 12* 10 17 Nov 13
2 MU1 Sept 13 6 11 Oct 16 10 18 Nov 14
2 3 Sept 18 6 12 Oct 17 10 MU5 Nov 15
2 4 Sept 19 6 MU3 Oct 18 11 19 Nov 20
3 5 Sept 25 7 Midterm Week 11 20 Nov 21
3 6 Sept 26 8 13 Oct 30 12 21 Nov 27
4 MU2 Sept 27 8 14 Oct 31 12 22 Nov 28
4 7 Oct 2 8 MU4 Nov 1 12 MU6 Nov 29
4 8 Oct 3 9 15 Nov 6 MUx = MakeUp lecture x

Detailed Schedule of Tutorials

Please work on the assigned problems prior to the tutorials and use the tutorial time to ask questions. Govind
will conduct the tutorials and will provide explanations of the more challenging problems. Office hours TBA.

Week Tutorial Date Week Tutorial Date Week Tutorial Date

2 1 Sept 13 6 5 Oct 18 11 9 Nov 22
3 2 Sept 20 8 6 Nov 1 12 10 Nov 29
4 3 Sept 27 9 7 Nov 8
5 4 Oct 4 10 8 Nov 15

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ECE 242 – Electronic Circuits II F2018

Course Content
We will begin with a brief review of MOSFET and BJT characteristics and small-signal equivalent circuits. The
course covers the following five major topics:
1. Chapter 8 – Basic building blocks of Integrated Circuit (IC) amplifiers (7 hours)
2. Chapter 9 – Differential and multistage amplifiers (10 hours)
3. Chapter 10 – Frequency response (7 hours)
4. Chapter 11 – Feedback (7 hours)
5. Chapter 14 – CMOS digital logic circuits (5 hours)

Detailed Course Content and Assigned Problems

Section Description
1. Basic Building Blocks of Integrated Circuit Amplifiers
8.1 IC Design Philosophy
8.2 IC Biasing – Current Sources, Current Mirrors and Current Steering Circuits
Problems: 8.1, 8.2, 8.6, 8.7, 8.12, 8.13, 8.22
8.3 The Basic Gain Cell
Problems: 8.25, 8.26, 8.27, 8.29, 8.41, 8.42, 8.43, 8.44
8.4 The Common-Gate and Common-Base Amplifiers
Problems: 8.52, 8.54, 8.60, 8.61
8.5 The Cascode Amplifier
(Excluding Sections 8.5.4, 8.5.5, 8.5.6)
Problems: 8.62, 8.63, 8.66, 8.68, 8.71, 8.73, 8.76, 8.78
8.6 Current Mirror Circuits with Improved Performance
Problems: 8.82, 8.84, 8.90
2. Differential and Multistage Amplifiers
9.1 The MOS Differential Pair
Problems: 9.1, 9.2, 9.3, 9.6, 9.9, 9.12, 9.15, 9.20, 9.23, 9.25
9.2 The BJT Differential Pair
Problems: 9.27, 9.28, 9.34, 9.36, 9.38, 9.39, 9.42, 9.47, 9.53
9.3 Common-Mode Rejection
Problems: 9.55, 9.56, 9.57, 9.60, 9.62, 9.63, 9.65, 9.68
9.4 DC Offset
Problems: 9.70, 9.73, 9.74, 9.75, 9.81
9.5 The Differential Amplifier with a Current-Mirror Load
Problems: 9.86, 9.87, 9.88, 9.92, 9.94, 9.98, 9.103, 9.104, 9.108, 9.110
9.6 Multistage Amplifiers
Problems: 9.113, 9.114, 9.119, 9.121, 9.124
3. Frequency Response
10.2 Internal Capacitive Effects and the High-Frequency Model of the MOSFET and the BJT
Problems: 10.14, 10.18, 10.21, 10.22
10.3 High Frequency Response of the CS and CE Amplifiers
Problems: 10.26, 10.27, 10.29, 10.32, 10.36, 10.38, 10.43, 10.44, 10.46
10.4 Useful Tools for the Analysis of the High-Frequency Response of Amplifiers
Problems: 10.51, 10.55, 10.59, 10.60, 10.63
10.5 High-Frequency Response of the Common-Gate and Cascode Amplifiers
Problems: 10.66, 10.70, 10.71, 10.73, 10.77

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ECE 242 – Electronic Circuits II F2018

Section Description
4. Feedback
11.1 The General Feedback Structure
Problems: 11.1, 11.3, 11.5, 11.8
11.2 Some Properties of Negative Feedback
Problems: 11.10, 11.13, 11.17, 11.19, 11.24
11.3 The Feedback Voltage Amplifier
Problems: 11.27, 11.28, 11.31, 11.33
11.4 Systematic Analysis of Feedback Voltage Amplifiers
Problems: 11.34, 11.35, 11.40, 11.42
11.5 Other Feedback Amplifier Types
Problems: 11.51, 11.53, 11.56, 11.58, 11.63, 11.65, 11.68, 11.74, 11.77, 11.80, 11.81

5. CMOS Logic Circuits

14.1 CMOS Logic Circuits
Problems: 14.1, 14.3, 14.7, 14.10, 14.11, 14.13
14.2 Digital Logic Inverters
Problems: 14.16, 14.18, 14.21, 14.24, 14.25
14.3 The CMOS Inverter
Problems: 14.31, 14.33, 14.35, 14.36
14.6 Power Dissipation
Problems: 14.63, 14.64

Labs
There will be three labs in total and one project, and you will be working together in pairs. During the course of
the labs, you will be building and designing commonly used circuit structures and blocks such as current mirrors,
differential amplifiers, and multistage amplifiers (which you will eventually convert to an op amp). Furthermore,
you will be investigating important concepts such as output resistance of practical circuits and the frequency
response of discrete amplifiers. There will be one lab quiz to assess your individual understanding of the lab
content (date TBA).

The labs will take place in E2-3344. In each lab, there is a Preparation, Laboratory, and Report section your group
must complete and submit. Please read the “general lab information” document, which will be posted on
LEARN, for important information regarding lab submission requirements, mark breakdowns, policies, etc.

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ECE 242 – Electronic Circuits II F2018

Notes and Policies

The following statements are a required part of every course outline.

Academic Integrity
To maintain a culture of academic integrity, members of the University of Waterloo community are expected to
promote honesty, trust, fairness, respect and responsibility. Check www.uwaterloo.ca/academicintegrity/ for
more information.

Grievance
A student who believes that a decision affecting some aspect of his/her university life has been unfair or
unreasonable may have grounds for initiating a grievance. Read Section 4 of “Policy 70, Student Petitions and
Grievances” (www.adm.uwaterloo.ca/infosec/Policies/policy70.htm). When in doubt, please be certain to
contact the department's administrative assistant who will provide further assistance.

Discipline
A student is expected to know what constitutes academic integrity. Check www.uwaterloo.ca
/academicintegrity/ to avoid committing an academic offense, and to take responsibility for his/her actions. A
student who is unsure whether an action constitutes an offense, or who needs help in learning how to avoid
offenses (e.g., plagiarism, cheating) or about rules for group work/collaboration should seek guidance from the
course instructor, academic advisor, or the Undergraduate Associate Dean. For information on categories of
offenses and types of penalties, students should refer to “Policy 71, Student Discipline”
(www.adm.uwaterloo.ca/infosec/Policies/policy71.htm). For typical penalties check Guidelines for the
“Assessment of Penalties” (www.adm.uwaterloo.ca/infosec/guidelines/penaltyguidelines.htm).

Appeals
A decision made or penalty imposed under “Policy 70, Student Petitions and Grievances”, other than a petition,
or “Policy 71, Student Discipline”, may be appealed if there are grounds. A student who believes he/she has a
ground for an appeal should refer to “Policy 72, Student Appeals”, www.adm.uwaterloo.ca
/infosec/Policies/policy72.htm.

Note for Students with Disabilities

The Office for Persons with Disabilities (OPD), located in Needles Hall, Room 1132, collaborates with all academic
departments to arrange appropriate accommodations for students with disabilities without compromising the
academic integrity of the curriculum. If you require academic accommodations to lessen the impact of your
disability, please register with the OPD at the beginning of each academic term.

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