2688 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 64, NO.
10, OCTOBER 2015
A New Approach to Multiple Soft Fault Diagnosis
of Analog BJT and CMOS Circuits
Michał Tadeusiewicz, Senior Member, IEEE, and Stanisław Hałgas
Abstract— This paper deals with multiple soft fault diagnosis of
nonlinear analog circuits and offers a method that allows locating
the faulty parameters and evaluating their values. The method
works with a system of nonlinear algebraic test equations, which
are not given in explicit analytical form, and actually may possess
multiple solutions. The solutions are specified by one or several
sets of the diagnostic parameter values that meet the test.
To find the multiple solutions, an extended systematic search
method has been developed. The diagnostic algorithm proposed
in this paper exploits this method and brings a new concept for
finding the actual solution. As a result, the diagnostic process
is considerably improved. It can be applied to bipolar junction
transistor and CMOS circuits manufactured in micrometer and
nanometer technologies. In the last case, however, the transistors
are characterized by intricate models (PSP 103 or BSIM 4).
In consequence, the CPU time increases due to very complex
sensitivity analyses of the circuits required by the diagnostic
method. In such a case, the proposed approach is useful at
the preproduction stage, where the CPU time is offline and not
crucial. For illustration, two numerical examples are given.
Index Terms— Analog circuits, bipolar and CMOS circuits,
fault diagnosis, multiple soft faults, nonlinearity.
I. I NTRODUCTION
F AULT diagnosis of analog circuits is an important
problem for design validation of electronic
devices [1], [2]. In general, the fault diagnosis consists
of detecting faulty circuits, locating faulty elements, and
evaluating their parameters. A fault is called soft when the
parameter deviates from its tolerance range, but does not
produce a short circuit or an open circuit. In some cases,
physical imperfections such as near-opens and near-shorts
may occur [2], [3]. During the last decades, a number of
methods focused on soft fault diagnosis of analog circuits have
been developed [4]–[15]. If most of the circuit simulations
take place after any testing, the diagnostic method is classified
as the simulation-after-test (SAT) approach, otherwise the
simulation-before-test (SBT) approach. Unlike the catastrophic
fault diagnosis, where the faulty parameters tend to infinity
or zero, which usually employs SBT approach [16], [17],
the soft fault diagnosis commonly uses SAT methods. They
are based on the measurements of the voltages at accessible
nodes and some analyses of the circuit under test. In dc case,
Manuscript received November 17, 2014; revised February 12, 2015;
accepted February 19, 2015. Date of publication April 27, 2015; date of
current version September 11, 2015. The Associate Editor coordinating the
review process was Dr. John Sheppard.
The authors are with the Department of Electrical, Electronic, Computer and
Control Engineering, Łódź University of Technology, Łódź 90-924, Poland
(e-mail: michal.tadeusiewicz@p.lodz.pl; stanislaw.halgas@p.lodz.pl).
Digital Object Identifier 10.1109/TIM.2015.2421712
0018-9456 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
the test equations, which involve the measured voltages and
the unknown parameters, are algebraic and usually nonlinear.
Most of the works focused on the fault diagnosis of analog
circuits address only the case when just one parameter
is faulty. Fewer papers are devoted to the multiple fault
diagnosis, where several parameters can be faulty. If the
parameters are slightly drifted from their nominal values,
the test equations can be linearized [10]. Otherwise, when
the parameter deviations are large, the nonlinearities of the
equations must be considered. These equations may actually
have multiple solutions, which means that several sets of
parameter values meet the diagnostic test. In such a case,
finding just one specific solution is rarely of interest. Hence,
references [7] and [12]–[15] propose an approach based on
the concept of finding multiple solutions of the test equation
and next selecting from them the actual one. In [12]–[15],
various methods such as the parametric homotopy [12],
the simplical homotopy [13], the restart homotopy [15],
or the block relaxation method [14] are used to compute
the multiple solutions. To find the actual one, another test is
arranged and the procedure is repeated. Next, the common
solution of the ones obtained using both tests is selected.
This common solution, being a set of the parameter values,
is considered as the actual one. Many numerical experiments,
performed to verify this approach, show its effectiveness.
However, in some cases, the methods applied to solve the test
equation fail. Moreover, this approach is time consuming due
to the necessity of finding multiple solutions of the equations
corresponding to both tests.
To overcome these drawbacks, a new concept is proposed
in this paper as follows. Two tests of the circuit are performed,
but only one of them is used to find the solutions. The other
allows checking whether the obtained solution is the actual
one. For this purpose, a very efficient method, which is an
extension of the search idea [18], [19], capable of finding
multiple solutions is applied. When a solution, being a set
of the parameter values, which meet the first test, has been
computed, a verification procedure is used. The circuit with
the obtained parameter values driven by the voltage sources
as in the second test is analyzed to find the output voltages.
If they are sufficiently close to the voltages provided by
the second test, the solution is considered as the actual one
and the computation process is terminated. Otherwise, the
method for solving the test equation is continued to find
other solution and the approach is repeated. The procedure
is carried out as long as the solution is obtained, which meets
the second test. The advantages of the proposed approach are
TADEUSIEWICZ AND HAŁGAS: NEW APPROACH TO MULTIPLE SOFT FAULT DIAGNOSIS OF ANALOG BJT AND CMOS CIRCUITS
avoiding computation of multiple solutions of the second test
equation and possibility of finding the actual solution at the
beginning of the computation process. Numerical experiments
show that the developed approach considerably improves and
speeds up finding the actual set of the parameter values.
In some cases, the CPU time is reduced up to 100 times.
II. P RELIMINARIES
This paper deals with multiple soft fault diagnosis of bipolar
junction transistor (BJT) and CMOS circuits, considering the
problem of multiple solutions of the test equations. For the
circuits comprising n parameters considered as possibly faulty,
the diagnostic test is arranged similarly as in [12]. The circuit
under test is driven by voltage sources applied to terminals
accessible for excitation and the output voltages are read at
r nodes accessible for measurement. For m sets of the input
voltage values, mr values of the output voltages are measured,
where mr ≥ n. We take n of the measured voltages values
and consider them as elements of the vector u = [u 1 · · · u n ]T ,
where T means transposition. Each of the voltages is a certain
function u i = fˆi (x), i = 1, . . . , n, of the circuit parameters
x 1 , . . . , x n , where x = [x 1 · · · x n ]T . As a result, the equation
f̂(x) = u is written, where f̂(x) = [ fˆ1 (x) · · · fˆn (x)]T . This
equation will be presented in the form
f(x) = 0 (1)
where f(x) = f̂(x) − u, and called a test equation. Unfortu-
nately, in real circuits, the nonlinear function f̂(x) is not given
in explicit analytical form. To apply the method proposed
in this paper, two tests, labeled A and B, are arranged as
described above, test A in order to find the solutions and test B
to verify whether a solution is the actual one. To differentiate
them, the equation of test B is labeled g(x) = 0, where
g(x) = ĝ(x) − u B .
Because in real circuits, the number of nodes accessible
for measurement and excitation is limited, the information
contained in the test equation may not be sufficient to find the
actual set of the parameters. From mathematical point of view,
it means that the test equation (1) possesses several solutions.
To find them, a method that allows obtaining multiple solutions
should be applied. An efficient approach for finding multiple
solutions is converting the algebraic problem into the solution
of differential equations, proposed in [18]. The Branin idea
was employed by Chao et al. [19] to develop a systematic
search method, which allows finding multiple dc operating
points of nonlinear resistive circuits. The method was then
extended in [20] to the computation of the input–output
characteristics, the analysis of nonlinear resistive circuits
driven by time-varying sources, the large change sensitivity
analysis of linear circuits, and the computation of multivariable
Nyquist plots.
This paper extends the concept of the systematic search [19]
for multiple solutions of the test equation and employs it in the
developed diagnostic algorithm. In the succeeding part of this
section, the main idea of the systematic search method [19] is
described.
To find multiple solutions of the algebraic test
equation (1), the problem is reformulated in terms of the initial
2689
value problem. For this purpose, the differential equations
d f i (x(t))
= − f i (x(t)), f i (x(0)) = 0, i = 1, . . . , n − 1
dt
d f n (x(t))
= ± f n (x(t)), f n (x(0)) = fn0 (2)
dt
are created. The solution of (2) is given by the equations
fi (x(t)) = f i (x(0))e−t = 0, i = 1, . . . , n − 1
f n (x(t)) = f n0 e±t . (3)
The initial condition x(0) is selected in such a way that
f i (x(0)) = 0 for i = 1, . . . , n − 1, i.e., x(0) lies on the space
curve l defined by the intersection of surfaces f i (x) = 0,
i = 1, . . . , n − 1. The first (n − 1) equations (3) show that
for any x(0) ∈ l, the trajectory x(t) remains on the curve l.
Because df/dt = (df/dx)(dx/dt), (2) in x-space have the
form
dx
= J−1 (x)[− f 1 (x) · · · − f n−1 (x) ± fn (x)]T (4)
dt
with the initial condition x(0) specified by (2), where
J(x) = df/dx is the Jacobian matrix of f(x). The solution
x(t) of the initial value problem (4) can be obtained by
numerical integration. Any point x(tk ) on the curve l for which
f n (x(tk )) = 0 is a solution of (1). In [19], it is proved that the
derivative of f n (x) in the direction of l is given by
∂ f n (x) detJ(x)
f n (x) = =  (5)
∂l n
i=1 ni (x)
2
where ni (x)(i = 1, . . . , n) are the cofactors of the Jacobian
matrix, corresponding to the last row of this matrix. If the
minus sign is assigned to f n (x) in (2), then according to (3),
f n (x) is forced to be attracted to zero along l. Otherwise, it is
forced to be diverged away from zero. In [19], it is proved
that in the course of the searching, the transition in the sign
assigned to fn (x) should be made at the points where the
Jacobian determinant changes sign and at the solution points.
III. E XTENSION OF THE S YSTEMATIC S EARCH M ETHOD
To solve numerically, the initial value problem (4), which
can be rewritten in the form dx/dt = J−1 (x)w(x), where
w(x) = [− f 1 (x) · · · − f n−1 (x) ± f n (x)]T , we apply the
explicit Runge–Kutta method of fourth order [21], [22], which
represents an appropriate compromise between the require-
ments of a low truncation error and a low computational
cost. Implicit integration methods are ineffective in this case
because they demand second-order sensitivity analyses of the
circuit.
Because the test equation (1) is not given in explicit
analytical form, the values of fˆi (x) (i = 1, . . . , n) and their
derivatives, with respect to x j ( j = 1, . . . , n), are determined
numerically for given values of x 1 , . . . , x n by performing
dc and sensitivity analyses of the circuit. In this way, we find
the required values of w(x) and the Jacobian matrix J(x).
However, to determine all the solutions, using the
systematic search approach, it is essential that there exists a
simple space curve l. Otherwise, e.g., if l is a multibranched
curve, some of the solutions may be lost. To overcome
2690 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 64, NO. 10, OCTOBER 2015

this drawback, we propose a method that generates several

space curves. Each of them is potentially capable of finding
multiple solutions.
To generate several space curves, we consider the system
of n − 1 equations
f 1 (x 1 , x 2 , . . . , x n−1 , x n ) = 0
f2 (x 1 , x 2 , . . . , x n−1 , x n ) = 0
·····················
f n−1 (x 1 , x 2 , . . . , x n−1 , x n ) = 0 (6) Fig. 1. Exemplary circuit.

and solve this system n times, for n − 1 different variables,

assuming nominal value of the remaining variable. At first,
we set x n = x nnom and solve (6) for x 1 , x 2 , . . . , x n−1 using the
Newton–Raphson algorithm. The solutions x 1∗ , x 2∗ , . . . , x n−1 ∗

together with x n nom form an n-vector denoted by x(0). This

vector defines the initial point on the first space curve l,
labeled l (1) [see (2)]. Using the search method, described
in Section II, the space curve l (1) is generated, which leads
to one or more solutions of test equation (1). To find other
possible solutions, we assume x n−1 = x n−1 nom , solve (6) for

x 1 , x 2 , . . . , x n−2 , x n and find a new initial n-vector that allows

generating other space curve l (2) by performing the procedure.
The approach may be repeated n times if it is necessary. The
last case considers x 1 = x 1nom and the variables x 2 , . . . , x n .
If some of the n systems of n − 1 equations cannot be
solved, because the Newton–Raphson algorithm fails, they are
discarded. Each of the space curves, in any case, is traced
in two directions. At first, (4) is solved using the minus sign
assigned to f n (x) and a part of this curve called N-part is
computed. After that, (4) is solved using the plus sign assigned
to f n (x) and the same initial point, tracing another part called
P-part of the space curve. The described method generally
allows finding more solutions of the test equation than the
search procedure, which exploits only one space curve.
In consequence, the risk of losing a solution decreases, but
it is achieved at expense of time consuming.
To simplify notation, the system of equations (6)
will be presented in the compact form p(x) = 0,
where p(x) = [ f 1 (x) · · · f n−1 (x)]T . In addition, vector
[x 1 · · · x k−1 x knom x k+1 · · · x n ]T will be denoted by x−k . In such
a case, the space curve generated by the solution x−k ∗ is
l (n−k+1) . faulty and have the resistances R1 = 330 , R2 = 1.00 k,
The aim of the diagnosis is finding the actual values of
the circuit parameters x 1 , . . . , x n , considered as potentially
faulty, that meet the diagnostic test. They are the solutions of
nonlinear algebraic test equation (1). Since this equation may
possess several solutions, several sets of the parameter values
that satisfy the test may exist and the problem arises how to
find the actual one. For this purpose, a verification procedure
is proposed as follows. We arrange two tests of the circuit,
labeled A and B and in any case measure the output voltages
at the accessible nodes. Test A leads to the diagnostic equation
whose solutions are searched using the extended systematic
search method. When a solution is obtained, which meets some
physical limitation, the circuit with the obtained parameter
values (components of the solution) driven by the voltage
sources as in test B is analyzed to find the output voltages.
Fig. 2. Part of the space curve with the points α and β that meet the
diagnostic test A.
If they are sufficiently close to the voltages provided by test B,
the solution is considered as the actual one.
To illustrate the procedure of tracing the space curve
and search for the solutions, we consider the circuit shown
in Fig. 1. The bipolar transistors are characterized by
the Gummel–Poon model with the following parameters—
BF = 400, BR = 4, IKF = 6 · 10−2 A, IS = 1.02 · 10−14 A,
ISE = 4.42 · 10−12 A, NE = 2, NC = 2, NF = 1, NR = 1,
RB = 3.3 , RC = 0.33 , RE = 0.81 , VAF = 121 V,
and VAR = 24 V. Nominal values of the resistors in this
circuit are indicated in Fig. 1. Let resistors R1 , R2 , and R3 be
and R3 = 820 , respectively. To diagnose the circuit, two
tests are arranged as follows. Test A—three sets of the input
(1) (2) (1)
voltages: 1) v in = 15 V, v in = 15 V; 2) v in = 9 V,
(2) (1) (2)
v in = 15 V; and 3) v in = 12 V, v in = 7 V are applied
and in each case the output voltage v 0 is measured. Similarly,
(1)
test B is performed, with the input voltages v in = 15 V,
(2) (1) (2) (1)
v in = 15 V; v in = 5 V, v in = 15 V; and v in = 15 V,
(2)
v in = 7 V. Accuracy of measurement is assumed to be
0.1 μV. To find x(0), a system of two equations of the
form (6), where x 1 = R1 , x 2 = R2 , and x 3 = R3nom is solved,
finding R1 = 9.228 k and R2 = 4.006 k. Hence, we obtain
the initial vector x(0) = [9.228, 4.006, 22.000]T. Part of the
space curve traced by the search method is shown in Fig. 2.
At the points α corresponding to the parameters R1 = 628 ,
TADEUSIEWICZ AND HAŁGAS: NEW APPROACH TO MULTIPLE SOFT FAULT DIAGNOSIS OF ANALOG BJT AND CMOS CIRCUITS
Fig. 3. Flowchart of the diagnostic algorithm.
R2 = 1.105 k, and R3 = 1.467 k and β corresponding to
the parameters R1 = 330 , R2 = 1.000 k, and R3 = 820 
equation f 3 (R1 , R2 , R3 ) = 0 is satisfied. In consequence, they
meet the diagnostic test A. The first obtained solution α is
virtual because it does not pass test B. The second one β
passes test B and is the actual solution.
The proposed algorithm for fault diagnosis, considering the
possibility of existence multiple solutions of the test equation
is shown in Fig. 3. Block systematic search method realizes
a process of finding the solutions of equation f(x) = 0
along the space curve l (n−k+1) , k ∈ {n, n − 1, . . . , 1}
using the systematic search method. The method starts from
the initial point of the space curve and traces its N-part.
2691
Fig. 4. Circuit for Example 1.
TABLE I
A RRANGED T ESTS A AND B—E XPERIMENTAL A PPROACH
When a solution is obtained, the search procedure is tem-
porarily locked to examine whether it meets physical lim-
itation. The procedure is unlocked and continued if the
solution is not accepted. If the number of the computation
steps m, reaches maximum M̃ the procedure begins trac-
ing P-part of the curve. When the total number of steps
m = M = 2 M̃, the method is locked. Thus, the output
of the block is the number m and a solution (if m < M).
The number M has been chosen on the basis of numerical
experiments.
The developed method is very effective under some assump-
tions that are difficult to satisfy in practice. It requires high
accuracy of the measurement of the output voltages in the
circuit under test, e.g., 0.1 μV in the above discussed example.
Such accuracy is necessary to make possible diagnosing
the parameters whose deviations have slight influence on
the tested voltages. If the variations of these voltages due to the
deviations of a parameter are smaller than the measurement
accuracy, it cannot be diagnosed on the basis of the test. Thus,
if the accuracy of measurement is decreased, then usually
less number of the parameters can be diagnosed. Moreover,
the method ignores influence of the self-heating of the chip
on the results of measurements and computations as well as
deviations of the parameters, which are considered as fixed.
In addition, the models describing the active devices are
considered as accurate. Thus, the method allows diagnosing
many parameters and gives a unique and accurate solution in
some idealized circumstances.
To adapt the method to real conditions, the require-
ment of high accuracy of the output voltage measurements
should be relaxed due to uncertainty in the measurement.
As a result, we modify the approach as follows. For
any point x on the space curve, we check whether
2692 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 64, NO. 10, OCTOBER 2015
TABLE II
R ESULTS G IVEN BY THE P ROPOSED M ETHOD
fˆn (x) ∈ [u n − u n , u n + u n ], where u n depends on the
measurement accuracy, instead of checking whether it meets
the equation f n (x) = fˆn (x) − u n = 0. Usually, several suc-
ceeding points on the space curve satisfy this requirement and
each of them should be considered as an approximate solution
of the test A equation. Thus, unlike to the ideal case, a set
of intervals of the parameter values {[x 1− , x 1+ ], . . . , [x n− , x n+ ]}
is obtained rather than a set of values. Moreover, under the
lower measurement accuracy, the parameters slightly affecting
the tested voltages cannot be diagnosed. The above-mentioned
drawbacks are the price we pay for taking the real restrictions
into account. Similarly, to check if x passes test B, we do
not verify the equation g(x) = ĝ(x) − u B = 0, but check
whether ĝ(x) ∈ [u B −u B , u B +u B ], where u B is a chosen
vector of deviations depending on the measurement accuracy.
On the basis of many numerical experiments, u n and u B
are set 5ε, where ε is the measurement accuracy. Having
the set of the intervals {[x 1− , x 1+ ], . . . , [x n− , x n+ ]} that pass
test B, we calculate average values x i = (1/2)(x i− + x i+ ),
i = 1, . . . , n and consider x = [x 1 · · · x n ]T as the approximate
solution.
IV. N UMERICAL E XAMPLES
The proposed algorithm has been implemented in Delphi
and tested using numerous BJT and MOS circuits. The
calculations were executed on PC with processor
Intel Core (TM) i7-2600. To illustrate effectiveness of
the algorithm, we consider two numerical examples. In all
the examples, the step size equals 0.01 for BJT circuits and
0.05 for CMOS circuits, and M = 20 000.
A. Example 1
The BJT circuit shown in Fig. 4 was built and laboratory
tested to verify the proposed method in a realistic framework.
The circuit comprises five transistors BC108B. Nominal values
of the resistors are indicated in Fig. 4. The measurement
accuracy of the tested voltages was 1 mV. Resistors R1 ,
R3 , and R4 are considered as possibly faulty. Resistors R2 ,
R5 , and R6 cannot be tested because they slightly influence
on the output voltages. Actual values of the resistors are
R2 = 5.058 k, R5 = 10.02 k, and R6 = 100.6 k.
In simulations, their nominal values are used. Tests A and B
are arranged, as described in Table I. To perform the analyses
required by the proposed method, the transistors are charac-
terized by the Gummel–Poon model with the parameters—
BF = 480, BR = 5, IKF = 0.071 A, IS = 7.59 · 10−15 A,
ISE = 7.477 · 10−15 A, ISC = 2.00 · 10−13 A, NE = 1.3808,
TABLE III
A RRANGED T ESTS A AND B—N UMERICAL A PPROACH
NF = 1, NR = 1, NE = 1.2, RB = 0, RC = 0, RE = 0,
VAF = 19.3 V, and VAR = 12.5 V. To form the intervals
[u i −u i , u i +u i ], u i = 5 mV has been used in both tests.
Two cases are considered using the tests arranged as shown
in Table I, comprising the voltages obtained experimentally.
The results given by the proposed method are summarized
in Table II. Time consumed by the method is 0.382 s in the
first case and 0.350 s in the second one.
This circuit is next diagnosed considering only the numeri-
cal tests under the same accuracy as in the experimental case.
The obtained test voltages are indicated in Table III, whereas
the results given by the proposed method are summarized
in Table IV. Time consumed by the method is 0.310 s in the
first case and 0.337 s in the second one.
If the accuracy of the tested voltages increases and equals
0.01 mV, a larger number of the parameters can be diagnosed.
For illustration, we consider five parameters—R1 , R2 , R3 ,
R4 , and R5 . The arranged tests A and B and the results
obtained are described in Table V. Time consumed by the
method is 0.270 s.
In all the above discussed cases, the results were provided
by space curve l (1) .
Under the accuracy 0.1 μV and appropriate tests, the
method allows testing all six parameters. For example,
for R1 = 47.00 k, R2 = 33.00 k, R3 = 3.00 k,
R4 = 3.00 k, R5 = 20.00 k, and R6 = 470.00 k, the
first solution found by the method lies on space curve l (3)
but it does not pass the verification test B. Then curve l (4)
is generated. The solution on this curve is the actual
one: R1 = 47.05 k, R2 = 33.03 k, R3 = 3.00 k,
R4 = 3.00 k, R5 = 20.01 k, and R6 = 470.19 k. Time
consumed by the method is 1.260 s.
Numerical experiments including 30 various cases show that
the method gives the actual solution corresponding to the first
obtained solution of the test A equation in 19 cases and to the
second obtained solution in 11 cases.
TADEUSIEWICZ AND HAŁGAS: NEW APPROACH TO MULTIPLE SOFT FAULT DIAGNOSIS OF ANALOG BJT AND CMOS CIRCUITS 2693

TABLE IV
R ESULTS G IVEN BY THE P ROPOSED M ETHOD

TABLE V
A RRANGED T ESTS AND THE O BTAINED R ESULTS

TABLE VI
A RRANGED T ESTS A AND B

Let all the transistors be potentially faulty, as shown

Fig. 5. CMOS-based voltage follower.
B. Example 2
Let us consider the CMOS benchmark operational
amplifier circuit [12], [23] operating as the voltage follower,
as shown in Fig. 5. The MOS transistors are represented
by the model built up in Level 1 of SPICE [24], [25]. The
nominal parameters of the MOS transistors are as follows:
pMOS—GAMMA = 0.53 V0.5 , IS = 10−16 A,
KP = 28.3 μA/V2 , PHI = 0.58 V, RD = RS = 94 ,
VTO = −0.84 V and nMOS—GAMMA = 0.38 V0.5 ,
IS = 10−16 A, KP = 79.7 μA/V2 , PHI = 0.53 V,
RD = RS = 63 , and VTO = 0.79 V.
Nominal channel width and length in meters of each
transistor are indicated in Fig. 5. We consider the channel
width/length W/L deviations of the transistors. The nominal
values of W/L of the transistors are as follows—3.750, 8.750,
50.000, 15.000, 15.000, 6.875, 6.875, and 75.000.
The circuit is diagnosed numerically assuming the accuracy
0.1 μV of the tested voltages at nodes 1 and 2. The diagnostic
tests A and B are arranged applying four sets of the input
voltages in each test, as depicted in Table VI.
in Table VII. The solution provided by space curve l (2) is
acceptable and meets the verification test B. The results are
summarized in Table VII. Time consumed by the method
is 0.343 s. The approach based on finding multiple solutions
corresponding to both tests and selecting the common solution
leads to the same results, but in much longer time 7.89 s.
Numerical experiments including 24 various cases show that
the method gives the actual solution corresponding to the first
obtained solution of the test A equation in 22 cases and to the
second obtained solution in two cases.
If the accuracy of the tested voltages is 1 μV, the method
gives the intervals of the parameter values (provided by space
curve l (2) ), as shown in Table VIII. Time consumed by the
method is 0.407 s.
Let the accuracy of the tested voltages be 0.1 mV and
the transistors T 1, T 5, T 6, T 7, and T 8 be considered as
possibly faulty, whereas the values of W/L of transistors
T 2, T 3, and T 4 are nominal. We arrange tests A and B,
as described in Table IX. On the basis of space curve l (2) ,
the method gives the results summarized in Table X. Time
consumed by the method is 0.297 s.
Example 2 deals with the circuit manufactured in microme-
ter technology, where the MOS transistors are characterized
2694 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 64, NO. 10, OCTOBER 2015

TABLE VII
R ESULTS OF E XAMPLE 2 FOR THE M EASUREMENT A CCURACY 0.1 μV

TABLE VIII
R ESULTS OF E XAMPLE 2 FOR THE M EASUREMENT A CCURACY 1 μV

TABLE IX
A RRANGED T ESTS A AND B

TABLE X nonlinear test equations (not given in explicit analytical form)

R ESULTS OF E XAMPLE 2 FOR THE M EASUREMENT A CCURACY 0.1 mV
using Level 1 model. However, the method proposed in
this paper can be applied to the circuits manufactured in
nanometer technology too. In such a case, the transistors
have to be characterized by very complex models, BSIM 4
or PSP 103 [26], [27]. Each of these models is specified
by several hundred equations, mostly nonlinear. For such
circuits, the sensitivity analyses, required by the diagnostic
method, must be carried out using the brute-force incremental
approach. In consequence, the method needs larger comput-
ing power and consumes much more CPU time. Thus, in
such a case, the method allows diagnosing the circuits in
the preproduction stage, where the CPU time is offline and
not crucial.
V. C ONCLUSION
The method developed in this paper deals with soft fault
diagnosis of nonlinear analog circuits and allows locating
several faulty parameters as well as evaluating their values.
The key problem of the diagnosis is solving a system of
that may possess multiple solutions. Each of the solutions is
a set of parameter values that meet the test. Another crucial
problem is selecting the actual one from the solutions. This
paper brings an efficient approach to resolve the problems. The
developed extended search method is a reliable tool for finding
multiple solutions of the system of test equations. In conse-
quence, there is little possibility of losing the actual solution.
Large number of numerical experiments show that the method
fails only in 1.3% of the considered cases. New procedure
proposed to verify the obtained solutions and find the actual
one considerably improves the approach applied in [12]–[15]
and speeds up the computation process. The advantages of
this approach is searching for the solutions corresponding to
only one test and terminating when the solution is obtained,
which passes the verification procedure, without necessity
of finding the remaining solutions. The CPU time increases
if few nodes are accessible for measurements in the circuit
under test. In such a case, the system of test equations
may possess several solutions, and the computation process
becomes more time consuming. The method allows testing
many parameters considered as potentially faulty and is very
effective if the measurement accuracy of the output voltages
is high. In a realistic framework, however, the demand of
high accuracy must be relaxed. In consequence, the parameters
whose influence on the output voltages is slight cannot be
tested. Moreover, the results are not points but intervals of
the parameter values. Fortunately, the middle points of these
intervals are very close to the actual values of the parameters
as numerical experiments reveal. The method can be applied
to fault diagnosis of BJT and CMOS circuits manufactured in
micrometer or nanometer technology.
TADEUSIEWICZ AND HAŁGAS: NEW APPROACH TO MULTIPLE SOFT FAULT DIAGNOSIS OF ANALOG BJT AND CMOS CIRCUITS
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Michał Tadeusiewicz (SM’92) received the
Ph.D. and D.Sc. degrees in electronic and
electrical engineering from the Lodz University of
Technology, Łódź, Poland.
He is currently a Full Professor with the
Department of Electrical, Electronic, Computer,
and Control Engineering, Lodz University of
Technology, and the Head of the Nonlinear Circuits
and Systems Division. He has authored and
co-authored about 194 technical papers, two books,
and 15 textbooks. His current research interests
include theory and analysis of nonlinear circuits and fault diagnosis of
analog circuits.
Stanisław Hałgas received the Ph.D. and
D.Sc. degrees in electronic and electrical engineering
from the Lodz University of Technology, Łódź,
Poland.
He has authored or co-authored about one
monograph, one textbook, and 100 technical papers.
His current research interests include nonlinear
circuits analysis and fault diagnosis of analog
circuits.