MODULE.

3.2. EXECUTION OF BRANCH INSTRUCTION

 A branch instruction replaces the contents of PC with the branch target address, which is
usually obtained by adding an offset X given in the branch instruction.
 The offset X is usually the difference between the branch target address and the address
immediately following the branch instruction.

Step Action

1 PCout , MAR in , Read, Select4,Add, Z in

2 Zout , PCin , Yin , WMF C
3 MDR out , IR in
4 Offset-field-of-IRout, Add, Z in
5 Z out , PCin , End
3.3 HARDWIRED CONTROL

To execute instructions, the processor must have some means of generating the control
signals needed in the proper sequence. The two categories are hardwired control and
microprogrammed control. Hardwired system can operate at high speed; but with little
flexibility.
CLK
Clock Control step Reset
counter

Step decoder

T 1 T2 Tn

INS1
External
INS2 inputs
Instruction
IR Encoder
decoder
Condition
codes
INSm

Run End

Control signals

Figure 7.11. Separation of the decoding and encoding functions.

In a hardwired organization, the control logic is implemented with gates, flip-flops, decoders and
other digital circuits. Hardwired control received its name because the control was implemented
in hardware and could not be easily changed. A hardwired control as the name implies, requires
changes in the wiring if the design has to be modified or changed. The control unit is
implemented as a state machine, with combinatorial circuits generating each of the control
functions on the basis of the current state and certain variables such as the op-code of the user
instruction undergoing execution. Its input logic signals are transformed into output logic signals
which are the control signals. A hardwired control unit must contain complex logic for
sequencing through the many micro-operations of the instruction cycle.
The hardwired implementations were faster, but too costly for most machines. It has the
advantage that it can be optimized to produce a fast mode of operation. The situation that arises
when the control unit is require to check the status of the condition or status flags in order to
choose between alternative courses of action; the hardwired control will handle this situation by
including an appropriate logic function like; End=T7.ADD + T6.BR+(T6.N+T4.N). BRN +… in
the encoder circuitry. For a given level of technology, hardwired control will be faster, since
there is no delay for microinstruction fetch from ROM before the control unit can produce a
control word.
3.4. MICROPROGRAMMED CONTROL

In microprogrammed control, a program generates the control signals. A control word (CW) is a
word whose individual bits represent the various control signals. A sequence of CWs
corresponding to the control sequence of a machine instruction constitutes the micro routine for
that instruction, and the individual control words in this micro routine are referred to as
microinstructions. The micro routines for all instructions in the instruction set of a computer are
stored in a special memory called the control store. The control unit can generate the control
signals for any instruction by sequentially reading the CWs of the corresponding micro routine
from the control store. To read the control, words sequentially from the control store, a micro
programmed counter is used.
 Fig: Basic organization of a micro programmed control unit

Every time a new instruction is loaded into the IR, the output of the block labeled “starting
address generator” is loaded into the PC. The PC is then automatically incremented by the
clock, causing successive microinstructions to be read from the control store. Hence, the control
signals are delivered to various parts of the processor in the correct sequence.

Fig: Organization of the control unit to allow conditional branching in the microprogram.
To support micro program branching, the organization of the control unit should be modified.
The starting and branch address generator loads a new address into the PC.

To allow implementation of a conditional branch, input to this block consists of the external
inputs and condition codes as well as the contents of the instruction register. In this control unit,
the PC is incremented every time a new microinstruction is fetched from the micro program
memory, except in the following situations:

 When a new instruction is loaded into the IR, the PC is loaded with the starting address
of the micro routine for that instruction.
 When a branch microinstruction is encountered and the branch condition is satisfied, the
PC is loaded with the branch address.
 When an End microinstruction is encountered, the PC is loaded with the address of the
first CW in the micro routine for the instruction fetch cycle.
ADD (Rs) +, Rd

1. PCout, MARin, Read, Select 4, Add, Zin

2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. Rsout, MARin, Read, Select 4, Add, Zin
5. Zout, Rsin
6. Rdout, Yin, WMFC
7. MDRout, Select Y, Add, Zin
8. Zout, Rdin, End
3.5 PROGRAMMABLE LOGIC ARRAY (PLA)

One way to design a combinational logic circuit it to get gates and connect them with
wires. One disadvantage with this way of designing circuits is its lack of portability.

You can now get chips called PLA (programmable logic arrays) and "program" them to
implement Boolean functions. I'll explain what it means to program a PLA.

Fortunately, a PLA is quite simple to learn, and produces nice neat circuits too.

Starting Out

The first part of a PLA looks like:

Each variable is hooked to a wire, and to a wire with a NOT gate. So the top wire is x2 and the
one just below is its negation, \x2.

Then there's x1 and just below it, its negation, \x1.

The next part is to draw a vertical wire with an AND gate. I've drawn 3 of them.
Let's try to implement a truth table with a PLA.

x2 x1 x0 z1 z0

0 0 0 0 0

0 0 1 1 0

0 1 0 0 0

0 1 1 1 0

1 0 0 1 1

1 0 1 0 0

1 1 0 0 0

1 1 1 0 1
Each of the vertical lines with an AND gate corresponds to a minterm. For example, the first
AND gate (on the left) is the minterm: \x2\x1x0.

The second AND gate (from the left) is the minterm: \x2x1x0.

The third AND gate (from the left) is the minterm: x2\x1\x0.

I've added a fourth AND gate which is the minterm: x2x1x0.

The first three minterms are used to implement z1. The third and fourth minterm are used to
implement z0.

This is how the PLA looks after we have all four minterms.

Now you might complain. How is it possible to have a one input AND gate? How can three
inputs be hooked to the same wire to an AND gate? Isn't that invalid for combinational logic
circuits?

That's true, it is invalid. However, the diagram is merely a simplification. I've drawn the each of
AND gate with three input wires, which is what it is in reality (there is as many input wires as
variables). For each connection (shown with a black dot), there's really a separate wire. We draw
one wire just to make it look neat.
The vertical wires are called the AND plane. We often leave out the AND gates to make it even
easier to draw.

We then add OR gates using horizontal wires, to connect the minterms together.

Again, a single wire into the OR gate is really 4 wires. We use the same simplification to make it
easier to read.
The horizontal wires make up the OR plane.

This is how the PLA looks when we leave out the AND gates and the OR gates. It's not that the
AND gates and OR gates aren't there---they are, but they've been left out to make the PLA even
easier to draw.

3.6 MICRO PROGRAM SEQUENCING

If all microprograms require only straightforward sequential execution of microinstructions
except for branches, letting a μPC governs the sequencing would be efficient. However, there are
two disadvantages:

 Having a separate microroutine for each machine instruction results in a large total
number of microinstructions and a large control store.
 Longer execution time because it takes more time to carry out the required branches.
 A micro program control unit consisting of 2 parts

 The control memory that store the micro instructions

 The associated circuits  control the generation of next address  called micro
program sequencer

 Micro program sequencer can be constructed by MSI(medium scale integration)

circuits for a particular application
• A micro prog sequencer attached to a control memory inspects certain bits of the micro
instruction from which it determines the next address for control memory

• A sequencer provides the following address-sequencing capabilities

• 1)increment the present address of the control memory

• 2) branches to an address as specified by the address field of the micro instruction

• 3) branches to a given address if a specified status bit is equal 1

• 4) transfer control to a new address as specified by an external source

• 5) has a facility for subroutine calls and return

• In most cases the instructions are read in successively

• Some instruction contains the address of next instruction

• The sequencer provide the capability for branching to any address, depending on the
status bit 1 or 0

• Some time control may transfer to non sequential micro instruction, thus the sequencer
provide the capability for branching to any one of two addresses depending on the status
bit 1 or 0

• Subroutines are programs used by other routines to accomplish a particular task.

• Micro programs that use subroutines must have the provision for storing the return
address during the subroutine call and restore the address during a subroutine return

• This is accomplished by placing the return address into a special register and then
branching to the beginning of the subroutine.

• This special register can then become the address source for setting the address register
for the return to the main routine
• The best way to organize a register file that store addresses for subroutine calls and
returns is to use a last-in-first-out(LIFO) stack.

•
Contents of IR OP code 0 1 0 Rsrc Rdst
1110 87 43 0

Address Microinstruction Textbook page 439

(octal)

000 PCout, MARin, Read, Select

4, Add, Zin
001 Zout, PCin, Yin, WMFC
002 MDRout, IRin
003 Branch  { PC 101 (from Instruction decoder);
PC5,4  [IR10,9]; PC3  [IR10]  [IR9]  [IR8]}
121 Rsrcout, MARin , Read, Select4, Add,in Z
122 Zout, Rsrcin
123 Branch  { PC 170;PC0  [IR8]}, WMFC
170 MDRout, MARin, Read, WMFC
171 MDRout, Yin
172 Rdstout, SelectY
, Add, Zin
173 Zout, Rdstin, End

Note:Microinstruction at location 170 is not executed for this addressing mode.

3.6.1 Microinstructions with next address field

The microprogram we discussed requires several branch microinstructions, which perform no

useful operation in the data path. A powerful alternative approach is to include an address
field as a part of every microinstruction to indicate the location of the next microinstruction
to be fetched.

 Pros: separate branch microinstructions are virtually eliminated; few limitations in

assigning addresses to microinstructions.
 Cons: additional bits for the address field (around 1/6)
 External Condition
Inputs codes

Decoding circuits

A R

Control store

Next address I R

Microinstruction decoder

Control signals

Figure 7.22. Microinstruction-sequencing organization.

3.7 HORIZONTAL AND VERTICAL MICROINSTRUCTIONS

The easiest way of structuring a microinstruction is to assign one bit for each control signal. But
this results in very long microinstructions and also only a very few of these will be set to one in a
particular clock cycle. So it is better to encode the microinstructions such that a group of bits
represent many control sequence, a particular pattern of these bits represents a particular
microinstruction. A horizontal microinstruction is a minimally encoded scheme and a vertical
microinstruction is a tightly encoded scheme. In general, a horizontal approach involves a wider
control store, but is capable of greater speed. The vertical approach requires a narrow control
store, but must be decoded in order to drive the actual control lines, thus introducing a delay in
driving the control lines.