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TRACE32 Directory
TRACE32 Index
STM8 .........................................................................................................................................
History ................................................................................................................................ 3
Introduction ....................................................................................................................... 4
Brief Overview of Documents for New Users 4
Demo and Start-up Script 4
Configuration ..................................................................................................................... 5
System Overview 5
Warning .............................................................................................................................. 6
Troubleshooting ................................................................................................................ 9
FAQ ..................................................................................................................................... 10
Debugger 10
Breakpoints ........................................................................................................................ 16
Software breakpoints 16
On-chip breakpoints for instructions 16
On-chip breakpoints for data 16
Support ............................................................................................................................... 18
Available Tools 19
Compilers 22
Products ............................................................................................................................. 23
Product Information 23
Order Information 23
Version 16-Nov-2018
History
This document serves as a guideline for debugging STM8 MCUs and describes all MCU-specific
TRACE32 settings and features.
Please keep in mind that only the Processor Architecture Manual (the document you are reading at the
moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by
Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your
first choice.
Architecture-independent information:
• “Debugger Basics - Training” (training_debugger.pdf): Get familiar with the basic features of a
TRACE32 debugger.
Architecture-specific information:
• “Processor Architecture Manuals”: These manuals describe commands that are specific for the
processor architecture supported by your debug cable. To access the manual for your processor
architecture, proceed as follows:
• “OS Awareness Manuals” (rtos_<os>.pdf): TRACE32 PowerView can be extended for operating
system-aware debugging. The appropriate OS Awareness manual informs you how to enable the
OS-aware debugging.
The on-chip FLASH and the EEProm memory can be programmed via the stm8.cmm script:
CD.DO ~~/demo/stm8/flash/stm8.cmm
Please be aware that you should check the Flash and EEProm size specified for your MCU in the stm8.cmm
before executing this script.
System Overview
PC
Windows / Linux / Mac OS
Target
Debug Cable
PODBUS IN
POWER DEBUG USB INTERFACE / USB 3
USB LAUTERBACH
Connector
POWER
SELECT
Cable
Debug
TRIG
EMULATE
DEBUG CABLE
DEBUG CABLE
USB
LAUTERBACH
POWER
7-9V
PODBUS OUT
AC/DC Adapter
1. Disconnect the debug cable from the target while the target power is
off.
2. Connect the host system, the TRACE32 hardware and the debug
cable.
Power down:
B::
RESet
The device prompt B:: is normally already selected in the command line. If this is not the case enter
B:: to set the correct device prompt. The RESet command is only necessary if you do not start
directly after booting the TRACE32 development tool.
SYStem.CPU STM8S005K6
MAP.UpdateOnce p:0x8000--0xffff
This is important to speed up the T32 GUI responsiveness. The specified address range will be
accesses only once after a break, thus avoiding unnecessary memory accesses.
SYStem.Mode Up
This command resets the CPU on the target, enables On-Chip-Debug Mode and issues a breakpoint
right after the reset interrupt routine.The CPU stops executing any instruction, and the user is able to
download the code and test. After this command is executed, it is possible to access memory and
registers.
DO ~~/demo/stm8/flash/stm8.cmm
A typical start sequence of the STM8 is shown below. This sequence can be written to an ASCII file (script
file) and executed with the command DO <filename>.
*) These commands open windows on the screen. The window position can be specified with the WinPOS
command.
Invalid memory access No special event Internal error, please consult your
size: <size> bytes (@ Lauterbach representative.
<address>)
Typically the SYStem.Up command is the first command of a debug session where communication with the
target is required. If you receive error messages like “debug port fail” or “debug port time out” while executing
this command, this may have the reasons below. “target processor in reset” is just a follow-up error
message.
• If the target has no power or the debug cable is not connected to the target, this results in the
error message “target power fail”.
• There is an issue with the SWD interface. Maybe there is the need to set jumpers on the target to
connect the correct signals to the SWD connector.
• The target is in an unrecoverable state. Re-power your target and try again.
Debugger
Debugging via
The debugger is accessed via Internet/VPN and the performance is very
VPN
slow. What can be done to improve debug performance?
Ref: 0307
The main cause for bad debug performance via Internet or VPN are low data
throughput and high latency. The ways to improve performance by the debugger
are limited:
The wanted breakpoint needs special features that are only possible to
realize by the trigger unit inside the controller.
Example: Read, write and access (Read/Write) breakpoints ("type" in Break.Set
window). Breakpoints with checking in real-time for data-values ("Data").
Breakpoints with special features ("action") like TriggerTrace, TraceEnable,
TraceOn/TraceOFF.
Default: STM8xxx.
Selects the processor type. All of the STM8 MCU cores with SWD Interface are supported.
Default: Denied.
Nonstop Lock all features of the debugger that affect the run-time behavior.
Nonstop reduces the functionality of the debugger to:
• Run-time access to memory and variables
• Trace display
The debugger inhibits the following:
• To stop the program execution
• All features of the debugger that are intrusive (e.g. action Spot for
breakpoints, performance analysis via StopAndGo mode, condi-
tional breakpoints etc.)
Default: Denied.
<mode>: Down
Go
Up
Default: Down.
Down Disables the debugger. The state of the CPU remains unchanged.
Up Resets the target and stops the CPU at the reset vector.
Default: OFF
If the system is locked, no access to the debug port will be performed by the debugger. While locked, the
debug connector of the debugger is tristated. The main intention of the SYStem.Lock command is to give
debug access to another tool.
Default: OFF.
If enabled, the interrupt enable flag of the EFLAGS register will be cleared during assembler single-step
operations. After the single step, the interrupt enable flag is restored to the value it had before the step. It is
turned on to make sure that no interrupt routine is serviced between break and go states.
Default: OFF.
If enabled, the interrupt enable flag of the EFLAGS register will be cleared during HLL single-step
operations. After the single step, the interrupt enable flag is restored to the value it had before the step.
The on-chip breakpoints can only cover specific ranges. If you want to set a marker or breakpoint to a
complex variable, the on-chip break resources of the CPU may be not powerful enough to cover the whole
structure. If the option TrOnchip.VarCONVert is set to ON, the breakpoint will automatically be converted
into a single address breakpoint. This is the default setting. Otherwise an error message is generated.
Software breakpoints
The STM8 MCUs support a total of two on-chip breakpoint registers which can be used as program
breakpoints to stop and debug the program which executes always in the Flash.
Data breakpoints are used to analyze the read and write accesses to global variables. The data breakpoints
can be triggered with respect to the data address or access type, i.e. read, write or both, or the data value.
The two instruction breakpoints of STM8 MCUs can be used as data breakpoints
In case of an on-chip data breakpoint, every load and store instruction is checked with respect to the
breakpoint address, access type and the value. The data breakpoints are especially useful to find out when
a global variable is written with a certain value. It is not possible to implement a similar breakpoint in software
without affecting the real-time behavior of the system. Since the load and store instructions work on RAM,
data breakpoints always point to addresses on RAM.
To access a memory class, write the class in front of the address. For example, use D to access the data
memory
Data.dump D:0x00
Data.dump P:0x00
Since the STM8 architecture uses a Unified Memory Architecture, the following two examples return the
same results.
Data.dump D:0x100
Data.dump P:0x100
Debug Cable
Pin Signal
1 VDD
2 PD1
3 GND
4 RESET[PA0]
Support
INSTRUCTION
INTEGRATOR
SIMULATOR
MONITOR
POWER
DEBUG
TRACE
FIRE
CPU
ICD
ICD
ICD
ICE
STM8AF5268 YES
STM8AF5269 YES
STM8AF5286 YES
STM8AF5288 YES
STM8AF5289 YES
STM8AF528A YES
STM8AF52A6 YES
STM8AF52A8 YES
STM8AF52A9 YES
STM8AF52AA YES
STM8AF6213 YES
STM8AF6213A YES
STM8AF6223 YES
STM8AF6223A YES
STM8AF6226 YES
STM8AF6246 YES
STM8AF6248 YES
STM8AF6266 YES
STM8AF6268 YES
STM8AF6269 YES
STM8AF6286 YES
STM8AF6288 YES
STM8AF6289 YES
STM8AF628A YES
STM8AF62A6 YES
STM8AF62A8 YES
STM8AF62A9 YES
STM8AF62AA YES
STM8AF6366 YES
STM8AF6388 YES
STM8AL3136 YES
STM8AL3138 YES
STM8AL3146 YES
STM8AL3148 YES
STM8AL3166 YES
STM8AL3168 YES
STM8AL3188 YES
STM8AL3189 YES
SIMULATOR
MONITOR
POWER
DEBUG
TRACE
FIRE
CPU
ICD
ICD
ICD
ICE
STM8AL318A YES
STM8AL31E88 YES
STM8AL31E89 YES
STM8AL31E8A YES
STM8AL3L46 YES
STM8AL3L48 YES
STM8AL3L66 YES
STM8AL3L68 YES
STM8AL3L88 YES
STM8AL3L89 YES
STM8AL3L8A YES
STM8AL3LE88 YES
STM8AL3LE89 YES
STM8AL3LE8A YES
STM8L001J3 YES
STM8L051F3 YES
STM8L052C6 YES
STM8L052R8 YES
STM8L101F1 YES
STM8L101F2 YES
STM8L101F3 YES
STM8L101G2 YES
STM8L101G3 YES
STM8L101K3 YES
STM8L151C2 YES
STM8L151C3 YES
STM8L151C4 YES
STM8L151C6 YES
STM8L151C8 YES
STM8L151F2 YES
STM8L151F3 YES
STM8L151G2 YES
STM8L151G3 YES
STM8L151G4 YES
STM8L151G6 YES
STM8L151K2 YES
STM8L151K3 YES
STM8L151K4 YES
STM8L151K6 YES
STM8L151M8 YES
STM8L151R6 YES
SIMULATOR
MONITOR
POWER
DEBUG
TRACE
FIRE
CPU
ICD
ICD
ICD
ICE
STM8L151R8 YES
STM8L152C4 YES
STM8L152C6 YES
STM8L152C8 YES
STM8L152K4 YES
STM8L152K6 YES
STM8L152K8 YES
STM8L152M8 YES
STM8L152R6 YES
STM8L152R8 YES
STM8L162M8 YES
STM8L162R8 YES
STM8S001J3 YES
STM8S003F3 YES
STM8S003K3 YES
STM8S005C6 YES
STM8S005K6 YES
STM8S007C8 YES
STM8S103F2 YES
STM8S103F3 YES
STM8S103K3 YES
STM8S105C4 YES
STM8S105C6 YES
STM8S105K4 YES
STM8S105K6 YES
STM8S105S4 YES
STM8S105S6 YES
STM8S207C6 YES
STM8S207C8 YES
STM8S207CB YES
STM8S207K6 YES
STM8S207K8 YES
STM8S207M8 YES
STM8S207MB YES
STM8S207R6 YES
STM8S207R8 YES
STM8S207RB YES
STM8S207S6 YES
STM8S207S8 YES
STM8S207SB YES
STM8S208C6 YES
SIMULATOR
MONITOR
POWER
DEBUG
TRACE
FIRE
CPU
ICD
ICD
ICD
ICE
STM8S208C8 YES
STM8S208CB YES
STM8S208MB YES
STM8S208R6 YES
STM8S208R8 YES
STM8S208RB YES
STM8S208S6 YES
STM8S208S8 YES
STM8S208SB YES
STM8S903F3 YES
STM8S903K3 YES
STM8SPLNB1 YES
STM8TL52F4 YES
STM8TL52G4 YES
STM8TL53C4 YES
STM8TL53F4 YES
STM8TL53G4 YES
Compilers
Product Information
Order Information