Digital Design Document

Sprinkler Design

Date: Feb 9th 2018

Contributions:
Daniel Schmalz (project leader): Ouput Control Module
Akarsh Ningoji Rao Kolekar: GPS Parsing
Tej Sharadbhai Kothari: SD Card Parsing

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 Revision Record
Date Author Comments
9 February Daniel Schmalz N/A
2018

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 Table of Contents
Section Page No.
List of Tables ............................................................................... Error! Bookmark not defined.
List of Figures ....................................................................................................................... iv
1 SCOPE................................................................................................................................. 1
1.1 System Identification ........................................................................................................................... 1
1.2 Document Overview ............................................................................................................................ 1

2 APPLICABLE DOCUMENTS ................................................................................................... 2

2.1 Internal Documents ............................................................................................................................. 2
2.2 External Documents ............................................................................................................................ 2

3 SYSTEM REQUIREMENTS ..................................................................................................... 3

3.1 Interfaces ............................................................................................................................................. 3
3.1.1 Inputs 3
3.1.1.1 Clock Signal ....................................................................................................................................3
3.1.1.2 RS232 .............................................................................................................................................3
3.1.1.3 SPI ..................................................................................................................................................3
3.1.1.4 GPIO Input ......................................................................................................................................3
3.1.2 Outputs ......................................................................................................................................................3
3.1.2.1 GPIO ...............................................................................................................................................3
3.2 System Design...................................................................................................................................... 4
3.2.1 SD Card.......................................................................................................................................................4
3.2.2 Rain Sensor ................................................................................................................................................4
3.2.3 GPS 4
3.2.4 TTL to 12V Power Driver ............................................................................................................................4
3.2.5 12V Solenoid Water Valve .........................................................................................................................5
3.2.6 FPGA 5
3.3 Sub-System Design for the FPGA Module ........................................................................................... 6
3.4 Component Level Design For the SPI IP Core ...................................................................................... 6
3.5 Component Level Design For the GPS Parsing Module ....................................................................... 7
3.6 Component Level Design For the SPI Parsing Module ........................................................................ 9
3.7 Component Level Design For the Output Control Module ............................................................... 11

4 APPENDIX A: INTERNAL DOCUMENTS ............................................................................... 13

4.1 GPS Parsing ICD.................................................................................................................................. 13
4.2 SPI Parsing ICD ................................................................................................................................... 14

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 4.3 Output Control ICD ............................................................................................................................ 15

List of Figures
Figure Page No.
Figure 1 - System Block Diagram ...................................................................................................................................1
Figure 2 - System Block Diagram ...................................................................................................................................4
Figure 3: FPGA Subsystem .............................................................................................................................................6
Figure 4: Altera SD Interface Block Diagram ..................................................................................................................6
Figure 5: GPS Parsing Block Diagram .............................................................................................................................7
Figure 6: Top Level GPS Diagram ...................................................................................................................................7
Figure 7: GPS Parsing ASM .............................................................................................................................................8
Figure 8: SPI Parsing Block Diagram ..............................................................................................................................9
Figure 9: SPI Parsing ASM ............................................................................................................................................10
Figure 10: Output Control Block Diagram ....................................................................................................................11
Figure 11: Output Control ASM ...................................................................................................................................12

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1 SCOPE
This Digital Design Document details the requirements and design for an automated sprinkler system.

1.1 System Identification

The system is an irrigation control system. It will utilize a SD card to upload desired times to water each
of the four regions. If the rain sensor detects rain, the system will not activate sprinklers at that time.
The GPS is used to update system time in order to determine whether it is time to start or stop the
sprinklers.

Figure 1 shows a block diagram of the system.

Figure 1 - System Block Diagram

1.2 Document Overview

This document establishes the requirements for the system and details the system, subsystem, and
component level designs.

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2 APPLICABLE DOCUMENTS
The following documents of the exact issue shown form a part of this specification to the extent
specified herein. In the event of an inconsistency between the documents referenced herein and the
content of this specification, this specification shall be considered a superseding requirement.

2.1 Internal Documents

 GPS Parsing ICD, pg. 13

 SPI Parsing ICD, pg. 14

 Output Control ICD, pg. 15

2.2 External Documents

Not applicable.

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3 SYSTEM REQUIREMENTS
3.1 Interfaces

3.1.1 Inputs
3.1.1.1 Clock Signal
The clock signal is provided by an on board oscillator component.
3.1.1.2 RS232
The timing input come from a GPS in the RS232 standard. A UART module takes in the serial data, then
outputs it to the FPGA 8 bits at time in parallel.
3.1.1.3 SPI
The designated start and stop times are written to an SD card. The FPGA extracts this information using
the SPI protocol. An IP designed by Altera (Altera UP SD Card Avalon Interface) interfaces with the IP
bus, and then outputs the data 32 bits at a time in parallel.
3.1.1.4 GPIO Input
The rain sensor inputs to a GPIO pin. This reveals whether or not it is raining.

3.1.2 Outputs
3.1.2.1 GPIO
4 GPIO pins indicate whether or not any of the four sprinklers should start.

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3.2 System Design
The block diagram shown in Figure 2 shows the block diagram design for the system level. Each of the
blocks will be examined in the sections below.

Figure 2 - System Block Diagram

3.2.1 SD Card
The SD card will be used to provide the programming to the irrigation system. It will detail when each of
the four zones are water. The file format for the SD card is shown in Listing 1. Starting with line 1, the
first “HHMM” denotes the start time in hours and minutes for region 1. The second “HHMM” on line 1
indicates the stop time for region 1. The next four lines give start and stop times for the remaining
regions in increasing order.

HHMMHHMM
HHMMHHMM
HHMMHHMM
HHMMHHMM
Listing 1: Input Data Format

3.2.2 Rain Sensor

The rain sensor for the system will be a Rain Bird Model CPRSDBEX Wired Rain Sensor. The sensor
provides an input to the system when rain is detected.

3.2.3 GPS
The GPS will be a NMEA compliant RS-232 based commercially available GPS unit.

3.2.4 TTL to 12V Power Driver

The TTL to 12V Power Driver is a voltage translation board. This board will convert the output of the
FPGA to the 12V power required by the Solenoid Water Valves.

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3.2.5 12V Solenoid Water Valve
The water valves are from various manufacturers and are currently on use on the farm. The new control
system will interface to the existing infrastructure.

3.2.6 FPGA
The FPGA board that will be used for this design is a DE10-Standard board from Terasic. Please see the
subsystem and component sections of this document that detail the FPGA design.

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3.3 Sub-System Design for the FPGA Module
The block diagram shown in Figure 3 shows the block diagram design for the sub-system level of the
FPGA module. Each of the blocks will be examined in the sections below.

Figure 3: FPGA Subsystem

3.4 Component Level Design For the SPI IP Core

For the SPI IP core, the Altera UP SD Card Avalon Interface extracts the information from the SD card
and outputs the data 32 bits at a time. For more details, see the data sheet.

Figure 4: Altera SD Interface Block Diagram

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3.5 Component Level Design For the GPS Parsing Module
Figure 5Figure 1 shows a block diagram of the GPS parsing module. Figure 6 shows the top level
connection from the external GPS module to the block diagram shown below.

Figure 5: GPS Parsing Block Diagram

Figure 6: Top Level GPS Diagram

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Figure 7Figure 5Figure 1 shows an ASM of the GPS parsing module

Figure 7: GPS Parsing ASM

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3.6 Component Level Design For the SPI Parsing Module
Figure 8Figure 5Figure 1 shows a block diagram of the SPI parsing module. The following 32 bit registers
store the ascii characters corresponding to a start or stop times of the form “HHMM” as detailed in
Listing 1.

Figure 8: SPI Parsing Block Diagram

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Figure 9Figure 7Figure 5Figure 1 shows the ASM of the SPI parsing module.

Figure 9: SPI Parsing ASM

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3.7 Component Level Design For the Output Control Module
Figure 10Figure 8Figure 5Figure 1 shows a block diagram of the Output Control Module.

Figure 10: Output Control Block Diagram

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Figure 11Figure 9Figure 7Figure 5Figure 1 shows the ASM of the Output Control Module.

Figure 11: Output Control ASM

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4 APPENDIX A: INTERNAL DOCUMENTS
4.1 GPS Parsing ICD

Name From To Size (in bits)

GPS_Sensor_Data GPS Sensor UART IP Core 9 (RS-232)

RxD_data_ready UART IP Core Counter to Parse Serial Data 1

RxD_data UART IP Core Counter to Parse Serial Data 8

RxD_data_ready UART IP Core Shift Register 1

RxD_data UART IP Core Shift Register 8

RxD_data_ready UART IP Core GPS_ASM 1

RxD_data UART IP Core GPS_ASM 8

char_count Counter to Parse Serial Data GPS_ASM 8

NMEA Shift Register GPS_ASM 24

PS State Variable Register GPS_ASM 3

NS GPS_ASM State Variable Register 3

clr_index GPS_ASM Counter for indexing output variable 1

inc_index GPS_ASM Counter for indexing output variable 1

index_counter Counter for indexing output variable GPS_ASM 32

time_ready_sig GPS_ASM Output Register Block 1

hours_sig GPS_ASM Output Register Block 16

minutes_sig GPS_ASM Output Register Block 16

time_ready_reg Output Register Block Buffer 1

hours_reg Output Register Block Buffer 16

minutes_reg Output Register Block Buffer 16

time_ready_out Buffer Output 1

hours_out Buffer Output 16

minutes_out Buffer Output 16

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4.2 SPI Parsing ICD

Name From To Size (bits)

Chip select FPGA SD card IP core 1

address FPGA SD card IP core 8

write_data FPGA SD card IP core 32

read_data SD card IP core FPGA 32

byteenable FPGA SD card IP core 4

read FPGA SD card IP core 1

write FPGA SD card IP core 1

wait_request SD card IP core FPGA 1

clock FPGA SD card IP core 1

reset FPGA SD card IP core 1

reset_n FPGA SD card IP core 1

SD_cmd Bidirectional Bidirectional 1

SD_dat Bidirectional Bidirectional 1

SD_dat3 Bidirectional Bidirectional 1

SD_Clock SD card IP core SD card 1

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4.3 Output Control ICD

Name From To Size (bits) Note

r?_start SPI Parser Mux 32 the '?' can be replaced with a 1,2,3, or 4

r?_stop SPI Parser Mux 32 the '?' can be replaced with a 1,2,3, or 4

r?_set Output_ASM Register 1 the '?' can be replaced with a 1,2,3, or 4

r?_clr Output_ASM Register 1 the '?' can be replaced with a 1,2,3, or 4

r?_out Register Output Port 1 the '?' can be replaced with a 1,2,3, or 4

region_sel Output_ASM Mux 2 -

time_g_start Comparator Output_ASM 1 -

time_g_stop Comparator Output_ASM 1 -

time GPS Module Comparator 32 -

NS Output_ASM Output_ASM 3 -
PS Output_ASM Output_ASM 3 -

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