Institut für Integrierte Systeme

Integrated Systems Laboratory

Department of Information Technology and Electrical Engineering

VLSI II:
Design of Very Large Scale Integration Circuits
227-0147-00L

Exercise 1

Practical Interfaces and Chip I/O

Prof. L. Benini
F. Gürkaynak

Last Changed: 2018-02-28 13:41:52 +0100

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1 Introduction
In VLSI I we have learned to use VHDL and System Verilog to describe hardware architectures. Ultimately, the
goal is to be able to use the function we developed in a real system. Thus, our block needs to interface with
the outside world. Many different kinds of interfaces exists and the choices we have depend on such things
as whether our block should become a chip on its own or a part of a larger chip. In the first case, we have
to decide on the type and the number of inputs/outputs (I/Os) we need. On the other hand, the number of
available I/Os may be limited, e.g., by the amount of chip area we have, or the number of pins on the chip
package. Yet, our design may have to meet certain bandwidth requirements (i.e., a certain amount of data
must be transferred into and out of the chip in a certain amount of time), resulting in conflicting constraints. It’s
the designer’s job to find a good solution. Designing your own high throughput interface would be an option,
but then you risk that your chip can only be used on a tester or in a custom-made system. In general, custom
interfaces are not a good choice since commercial parts usually only support certain standard I/O interfaces.
Many such interfaces exist, and choosing the right one to meet the bandwidth requirements without using too
much chip area and power can be hard. If your block is part of a larger chip, other types of interfaces are
required. Standardized on-chip interconnects and buses exists, and using them ensures that your block is
easily portable and exchangeable.
In the following exercise we will learn:
• how to select appropriate I/O drivers in a design
• what I/O interfaces are available and how to select the right one
• what chip packages are available and how to chose them
• how to connect different IP (intellectual property) blocks on-chip using a bus

Student Task: Parts of the text that have a gray background, like the current paragraph, indicate steps
required to complete the exercise.

2 Pad Types, Functionalities and Geometry

The interface of a digital circuit has a twofold purpose. On the one hand, sufficient power needs to be sup-
plied to the circuit. On the other hand, the I/O data transfer needs to be provided. Furthermore, pads play
an important role in protecting the circuit from electrostatic discharge (ESD). During handling and assembly,
voltage peaks as high as a few kV can occur. Without proper ESD protection, chips would not withstand such
conditions. To meet these requirements, a variety of pads are used.
Figure 1 (left) shows an input pad with ESD protection circuitry and buffers to condition the signal, while Fig-
ure 1 (right) shows a typical output pad. Output pads are similar to input pads, but have much larger buffers
to drive external loads. Also bi-directional pads exist. They allow data communication to happen in both di-
rections on a single bonding connection. In addition, there are specialized pads that are tolerant to high input
voltages. Depending on the type of I/O pad, pads can be programmed to include pull-up or pull-down resistors,
etc. Most technologies use separate power networks and different voltage levels for the power supply of the
core and of the I/O buffers in the pads (see 2). This is necessary, since the core is more sensitive to supply
voltage variations than the pads, and the pads can have very high peak-power consumption because they have
to drive large off-chip loads.

Pads may contribute significantly to the area of a design, depending mainly on the following parameters:
• Core area usage A: The area used to implement the functionality of the digital design.
• Number of I/O signals N: Wide data buses contribute significantly to the pin count of a digital design.
• Core power pads Npc : Each power/ground pad can only supply a certain amount of current. A sufficient
number of power/ground pads must be available to satisfy the demand of the design.

2
 Buffer

Buffer

Buffer

Buffer
Buffer

ESD ESD
Protection Protection

Landing Landing
Pad Pad
Bonding Bonding
Wire Wire

Figure 1: Data input pad (left), data output pad (right)

Vss
Input Pad
Core

Vdd
Vss
Vdd

Figure 2: Corner of a chip (left). Note the different power supply networks for core and pads. A bonded die is
shown on the right side

• I/O power pads Npio : A sufficient number of I/O power pads needs to be available to supply the I/O
drivers, even if many output signals change their value simultaneously, which may result in peak currents
that are many times higher than the average current consumption.

3
For the subsequent tasks consider the two pad geometries shown in 3.

150m 100m

Vdd

150m

225m
Vss Vdd
Vss

Figure 3: Two geometries of pads are available. Type I (left) and Type II (right). The arrow connects possible
input or output signals to the core.

Let us consider two designs:

• Design I: core area A1 = 0.5 mm2 , number of I/O signals N1 = 100, number of power pads are Npc 1 = 6
and Npio 1 = 6.
• Design II: core area A2 = 30 mm2 , number of I/O signals N2 = 100, number of power pads are Npc 2 = 6
and Npio 2 = 6.
The silicon area price per mm2 is 1‘800 CHF1 .

Student Task 1:
1. What is the cost of the designs, if only the core area is considered?

2. Assume that the core is square shaped. Which pad type are best to use for each design? Specify
the limiting factor in each solution?

3. For each design look at the variant with the lower overall area. How much has the die area increased
due to the pads?

In order to allow more pads to be placed, advanced solutions need to be considered. One possibility is to use
staggered pads, as shown in 4.
Reconsider Design I from the previous part.

Student Task 2:
1. How large is the die area if staggered pads are allowed? How much has the die area decreased
compared to Type II pads? Assume that the die is square shaped.

1 This is approximately the price for the technology we will use during the semester projects. This price is for an MPW (multi-project
wafer) run and includes the manufacturing of 10 samples.

4
 50m

150m
225m
Vdd
Vss

Figure 4: Staggered pads.

5
3 Choosing the Right Pads
In this part of the exercise, we will try to determine which I/O drivers to use for an (imaginary) circuit we have
designed. Assume, we have finished designing the entity top, and we want to finalize our design by adding
the I/O drivers at the chip level. Let’s not consider supply pads for the time being, and only think about the
I/O pads. The supply pads will be discussed in a later exercise. Figure 5 shows the system where the chip
containing our design will be used. There are four parts that we want to interface with each other:

SCLK SCLK

MISO MISO

MOSI MOSI

SS SS
DebugOut_TO(7:0)
Sensor
OpMode_SI(2:0)
High-speed tester interface

MemIn_DI(31:0)

MemOut_DO(31:0) Data_DIO(31:0)

MemRead_SO ReadEn_SI

MemAddress_DO(11:0) Addr_DI(11:0)

Test_TI Clk_CI
RAM
Reset_RBI

Clk_CI
top
chip

Figure 5: Block diagram of the system.

1. Memory: Our system includes a high speed external RAM. The main parameters of its interface are
listed below. The system has been designed to operate with a 250 MHz clock.

Properties (Memory)
Name Dir. Cin (pF) Level (V)
Data DIO Bidir 18.0 1.8
ReadEn SI In 10.0 1.8
Addr DI In 18.0 1.8
Clk CI In 8.0 1.8

Dynamic Parameters (Memory)

Name setup (ns) hold (ns) prop. del. (ns)
Data DIO 0.2 0.0 1.8
ReadEn SI 0.4 0.1 -
Addr DI 0.3 -0.4 -

2. Sensor: The system interfaces a sensor using a serial peripheral interface (SPI). The chip acts as
master and provides the clock. First, the master starts-up the sensor by sending configuration data over
the SPI. Once configured, the sensor produces data and stores it in a buffer. Then, the master collects
data from the sensor by constantly reading the buffer. A typical application requires around 100 such
data transfers per second.

6
 Pin Descriptions

Name Bits Direction Description

Clk CI 1 In 250 MHz clock input
Reset RBI 1 In Active low signal, 0=Reset
Test TI 1 In 0=normal operation, 1=test mode. During normal operation
this pin is tied to ground.

OpMode SI 3 In The chip has 5 different operation modes. The default oper-
ation mode is 011. The operation mode cannot be changed
while the chip is running.
DebugOut TO 8 Out This 8-bit interface is used to monitor the state of the chip
during test operation

MemIn DI 32 In 32-bit high-speed memory data

MemOut DO 32 Out 32-bit high-speed memory data
MemRead SO 1 Out 1=read from memory, 0=write to memory
MemAddress DO 12 Out 12-bit address for the external RAM

SCLK 1 Out SPI clock

MOSI 1 Out Data from master to slave
MISO 1 In Data from slave to master
SS 1 Out Slave select signal

Properties (Sensor)
Name Dir. Cin (pF) Level (V)
SCLK In 10.0 3.3
MOSI In 10.0 3.3
MISO Out - 3.3
SS In 10.0 3.3
3. Tester: Chip testers can be programmed to match all dynamic constraints of the chip at 1.8 V, thus no
special timing considerations are required for signals of this interface.
4. Our chip: The two tables on the next page show the pin description of our circuit and the dynamic
characteristics for all pins obtained through a synthesis of the top level.
Using all this information we can decide on which pads to use in our design. Now, that we know the char-
acteristics of the parts that we want to interface, let’s see whether we can meet them with the pads we have
available in our design library. In the given 65 nm UMC technology, two different kinds of pads are available
IUMA and IUMB, and both of them are available for three different voltages, 1.8 V, 2.5 V, and 3.3 V. In general
IUMB pads have higher driving capabilities and can drive higher loads. We will only consider IUMB pads in the
following. You can find more information on the different driving characteristics, propagation delays, etc. in the
pad library databook:
sh > evince /home/vlsi2/ex01/files/pad_databook.pdf &

7
 Dynamic Characteristics

Name Setup (ns) Hold (ns) Propagation Delay (ns)

Clk CI - - -
Reset RBI - - -
Test TI - - -

OpMode SI - - -
DebugOut TO - - -

MemIn DI 0.3 0 -
MemOut DO - - 0.2
MemRead SO - - 0.6
MemAddress DO - - 0.3

MISO 1.0 0 -
MOSI - - 1.0

Properties

Name Dir. Cin (pF) Level (V)

MemIn DI In 0.08 pF 1.8 V

Figure 6 shows the pad with its configuration pins. Depending on the configuration of the OE pin the pads can
be used as input pads, output pads, or bi-directional pads.
• Input pads can be programmed either as normal or Schmitt-triggered inputs (pin SMT), and with pull-up
or pull-down functionality (pins PU and PD).
• Output pads can be configured with different driving strength (pin PIN1 and PIN2), and either fast or
slow slew rate (pin SR). The higher the driving strength of a pad, the faster it is, but also the more power it
consumes. Examine the datasheet of an output pad in the databook. You will notice that the propagation
delay of the pad is given for different load capacitances, since the speed not only depends on how strong
the driver is, but also how large the load is that has to be driven.
• In bi-directional mode, the pins PIN1, PIN2, and SR are used to configure the driving strength and slew
rate of the output, while the pins SMT, PD, and PU are used to configure the inputs.
Although less pairs of power/ground pads are required when the I/O pads are set for slow slew rate, lets use
the fast slew rate setting for the pads in this exercise (SR=0) .

Student Task 3:
For each of the four interfaces discussed above determine which pads can be used and how they should
be configured for minimal power consumption. Answering the questions 1–3 first will help you to complete
the table in question 4. :
1. Where would you consider using Schmitt-triggered inputs?

2. What pads would you use for the sensor interface? What is the disadvantage of using different pads
on the same chip? Where could we make use of the special pull-up/-down functionality?

8
 Figure 6: 1.8 V configurable CMOS Bi-directional buffer. Cellname IUMA and IUMB.

3. Where and how can we use bi-directional pads in our system? What would we gain?

4. Which pads would you use for which I/O ports to ensure that the system can work at 250 MHz?

Name Pad Type OE PIN1 PIN2 SMT PU PD

Clk CI
Test TI
Reset RBI
OpMode SI
DebugOut TO
MemIn DI/MemOut DO
MemRead SO
MemAddress DO
SCLK
MISO
MOSI
SS

9
4 Choosing the Right I/O Interface
• I2C (Inter Integrated Circuit):
The I2C or I2 C (pronounced “i-squared-c”) is a low bandwidth interface using only 2 wires, a clock line
SCL and a bi-directional data line SDA. The original standard was specified for two bandwidths 100 Kbit/s
and 10 Kb/s. Recently the standard was revised to support also 400 Kb/s and 3.4 Mb/s. I2C is mainly
used to communicate with EEPROMs, sensors, programmable power supplies. Standard digital pads
can be used. Figure 7 a) shows how the I2C interface can be used to connect three slave devices to a
single master.
• I2S (Inter-IC Sound, Integrated Interchip Sound):
The I2S or I2 S is a low bandwidth protocol used in digital audio components. Left and right channel
can be selected by the WS line, as shown in Figure 7 b). Requires 3 wires and no bidirectional pins are
needed. Data flows in one direction only and standard digital pads can be used.
• SPI (Serial Peripheral Interface):
The SPI is a low to medium bandwidth interface, and in its simplest version requires 4 wires: SCK (clock),
MOSI (master output slave input), MISO (master input slave output), and SS (slave select). Multiple slaves
can be addressed using multiple SS lines as shown in Figure 8 a). The speed is not limited by any stan-
dard. The two separate data lines allow the SPI to support full-duplex data transfers. Recent extensions
are Dual or Quad SPI and use multiple bi-directional data lines. Clock speeds found in commercial pe-
ripherals using SPI may reach 100 MHz (i.e., 400 MBit/s bandwidth using Quad SPI). Most of the sensors
on the market rely on SPI. Dual and Quad SPI are mainly used for high capacity flash memory. Standard
digital pads can be used for the SPI.
• JTAG (Joint Test Action Group):
JTAG is a low bandwidth protocol and requires 5 wires TMS (mode select output), TDI (data input), TDO
(data output), TCK (clock output), TRST (reset output). JTAG uses standard digital pads and is mainly
used for debug/test. Multiple devices can be connected together as shown in Figure 8 b) and can be
selected with the TMS line.
• UART (Universal Asynchronous Receiver/Transmitter):
The UART is a low bandwidth interface using 2 wires, one for TX (transmission) and one for RX (recep-
tion). No clock signals are used (hence, asynchronous), the bandwidth in bits per second is called baud
rate, and must be known to both sender and receiver. Common baud rates are 9600, 19200, ..., 115200.
UART is mainly used for remote consoles or debug printf. The data is sent as illustrated in Figure 9.
• CAN (Controller Area Network):
CAN is a low to medium bandwidth interface which uses only two wires. It is a multi master serial interface
designed to be very robust against noise and collisions. CAN requires special I/O pads and is widely used
in automotive applications.
• GPIO (General Purpose I/O):
GPIO are generally used for low bandwidth communication, mainly to control actuators. No standard
defined.
• MIPI-CSI (Camera Serial Interface):
MIPI-CSI is a high bandwidth protocol which uses multiple differential data lines (up to 4), one differential
clock line, and an I2C port for configuration. Data flows in one direction only, and special pads are re-
quired that support sub-LVDS (low voltage differential signaling). The MIPI-CSI is widely used to interface
CMOS sensors.
• USB (Universal Serial Bus):
USB is a medium to high bandwidth protocol which uses one differential data line (D+, D-), and is defined
in different standards. USB 1.1 specifies the data rates 1.5 Mb/s (low bandwidth) and 12 Mb/s, while
USB 2.0 can reach up to 480 Mb/s, and USB 3.0 even up to 5Gb/s. USB is a complex protocol defining
multiple communication layers. The various versions have different requirements in terms of I/O pads
and encode/decode hardware, called PHY (physical layer, or physical interface).

10
 • PCIe (Peripheral Component Interconnect Express):
PCIe is a very high bandwidth protocol which uses up to 82 pins in its 16x configuration. It relies on
multiple differential data lines capable of handling up to 15 Gb/s per lane. PCIe requires a dedicated
PHY, and is used mainly to connect devices with very high demand in bandwidth.

Serial Clock (SCK)

Vdd
Rp
SDA
SCL Word Select (WS)

μC ADC DAC μC Serial Data (SD) LSB MSB LSB MSB

Master Slave Slave Slave Right Channel Left Channel Right Channel

(a) I2C (b) I2S

Figure 7: (a) I2C interface with 3 slaves, and (b) I2S interface timing with WS (word select) signal to change
between the right and the left channel in a stereo sound system.

SCLK SCLK
MOSI MOSI SPI
SPI MISO MISO Slave
Master SS1 SS
SS2
SS3
SCLK
MOSI SPI
MISO Slave
SS

SCLK
MOSI SPI
MISO Slave
SS

(a) SPI (b) JTAG

Figure 8: (a) SPI master with three slaves. Each slave is connected with a separate SS line to the master. (b)
JTAG interface with 3 devices. The TMS line is used to select the active device.

Figure 9: UART interface: Shows how the bits are transmitted on the TX line. A ’0’ starts a transmission of
typically 8 bits which is terminated with a stop bit of ’1’.

11
Student Task 4: Consider a small digital audio system consisting of one microprocessor, one digital
microphone, one ultra-low-power controllable power supply and a set of four actuators. Each actuator is
controlled by a 2 bit signal. In addition, assume that the system requires full test and debug capabilities.

• Draw the system with the appropriate interfaces

• What interfaces do you need for each component?

• How many pads do you need?

12
5 Choosing the Right On-Chip Interconnect
An integrated circuit incorporating all sorts of electronic components, conventionally found as seperate parts in
a larger system, is called a System-on-Chip (SoC). These components may be any kind of analog, digital and
interface circuits, called IPs (intellectual properties). It is not unusual to find SoCs that use tens or hundreds
of IPs. In order to reduce the time-to-market when developing an SoC, an efficient way to connect the various
IPs is to use standardized on-chip interconnect protocols. Those themselves are available as IPs. The most
commonly used on-chip interconnects are defined in the open-standard AMBA (Advanced Microcontroller Bus
Architecture) developed by ARM. The different protocols specified in AMBA are supported by the majority of
the IP vendors.
• APB (Advanced Peripherals Bus):
The AMBA APB is a 16 bit or 32 bit wide bus with only one master and up to 16 slaves. The data output
from the master is connected to all the slaves simultaneously, i.e. the interconnect is shared. Slave
select signals are generated by an address decoder to activate one slave at a time. Due to its simplicity,
it requires very little logic gates to implement it, and is thus commonly used in low complexity IPs where
bandwidth and latency are not critical. All signal transitions are related to the rising edge of the clock to
enable the integration of APB peripherals easily into any synchronous design. The APB is an unpipelined
protocol, and every transfer takes at least two cycles.
• AHB (Advanced High-Performance Bus):
The AMBA AHB is a 32 bit, 64 bit or 128 bit bus. It has multi-master support, but similar as in APB the
interconnect is shared, thus there can only be one active master at any time. Whenever a master is using
the bus, the others are stalled. Compared to APB, AHB is a more complex scheme based on multiplexors
and an arbiter that decides on which master is allowed to control the bus, and a decoder to determine
which slave is involved in the transfer. Figure 10 shows an example of a design with three masters and
four slaves connected via an AHB interface. The AHB doesn’t scale very well with growing numbers
of masters and slaves because the number of multiplexors and connections increases correspondingly,
which makes AHB increasingly inefficient. The data rate is limited by the wiring. AHB is employed mainly
in low complexity systems (e.g., microcontrollers) where high bandwidth is not a requirement but the
number of logic gates matters.
• AXI (Advanced Extensible Interface):
The AMBA AXI protocol is targeted at high-performance and high-speed systems, with the following
objectives:
1. be suitable for high-bandwidth and low-latency designs
2. enable high-frequency operation without using complex bridges
3. meet the interface requirements of a wide range of components
4. be suitable for memory controllers with high initial access latency
5. provide flexibility in the implementation of interconnect architectures
6. be backward-compatible with existing AHB and APB interfaces.
The key features of the AXI protocol are:
1. separate address/control and data phases
2. support for unaligned data transfers using byte strobes
3. burst-based transactions with only start address issued
4. separate read and write data channels to enable low-cost Direct Memory Access (DMA)
5. ability to issue multiple outstanding addresses
6. out-of-order transaction completion
7. easy addition of register stages to provide timing closure.

13
 The AXI protocol includes optional extensions that cover signaling for low-power operation.
AXI is based on 5 independent channels: AW (address write), DW (data write), B (write response), AR
(address read), R (read response). It supports bursts and multiple outstanding transactions, i.e., masters
can initiate transactions before they received responses to an earlier transaction. Connections are always
point to point and can easily be pipelined. Different transactions coming from different sources can be
interleaved.
• AXI Lite:
AXI Lite is derived from AXI but does not support bursts or outstanding transactions. AXI Lite is a 32 bit,
64 bit or 128 bit bus, but is usually used in its 32 bit version to connect low to medium bandwidth IPs.
• AXI Stream:
AXI Stream is again very similar to the AXI but uses a handshake protocol compatible with a single AXI
channel. It has a configurable data width, and transactions are always point to point without the need for
address lines. Example application include camera interfaces or filter blocks.

PWDATA
PRDATA
Slave
PADDR
#1
PSEL
...

PWDATA
PRDATA
Slave
PADDR
Master #2
PSEL
...

PWDATA
PRDATA •
PADDR •
PSEL1 •
PSEL2
...
PWDATA
PSEL16
PRDATA
... Slave
PADDR
#16
PSEL
...

Figure 10: (a) APB with 1 master and up to 16 slaves. (b) AHB with 3 master and 4 slaves.

14
 Component Ports Bandwidth/port Purpose
1x I2C 1 slave port 1 Mb/s data and configuration
4x 32 bit processor cores 1 master port 1.6 Gb/s data
1 master port 1.6 Gb/s data (instructions)
1x DMA module 2 master ports 3.2 Gb/s data
1 slave port 1 Mb/s configuration
1x Interrupt controller 1 slave port 1 Mb/s data and configuration
1x PCIe master 1 slave port 3.2 Gb/s data
1 slave port 1 Mb/s configuration
2x UART 1 slave port 1 Mb/s data and configuration
1x DDR controller 2 slave ports 3.2 Gb/s data
1 slave port 1 Mb/s configuration
1x Timer 1 slave port 1 Mb/s data and configuration
1x On-chip SRAM 1 slave port 3.2 Gb/s data
1x Boot-ROM 1 slave port 3.2 Gb/s configuration
1x SPI 1 slave port 50 Mb/s data and configuration

Table 1: System description: components and bandwidth requirements.

Student Task 5: Given an SoC with the components and requirements described in Table 1, draw the
schematic of a possible interconnect scheme that can handle the bandwidth requirements. An example is
shown in Figure 11. You may use interconnects of different types and connect them with bridges to obtain
the most area efficient solution. It is allowed to use different bus widths.
Hint: start by calculating the clock frequency of the cores and assume that data and instructions are
required simultaneously.

64 32
M S Some unit
64 Some unit
M
32
S Some unit
64
M Some unit
32
AXI AHB S Some unit
64 32 32
S 64 / 32 M S AXI / AHB M
32
S Some unit
32
Some unit M
32
S
64 Some unit
S

32 32
M APB / AHB S

32
S Some unit
APB
32
S Some unit

32
S
64 Some unit
M

Figure 11: Example showing how different IPs can be connected using different interconnect types. M and S
mean master and slave of a bus, respectively, while e.g. a bridge from AXI to AHB is denoted by
AXI/AHB.

15
6 Choosing the Right Package Type
Chip packages have to protect the bare silicon dies from environmental influences, such as light and moisture,
and also need to provide a robust mechanical and electrical connection from the chip to the PCB (printed
circuit board). A lot of different standard packages are available on the market. Still, special applications may
require the design of custom solutions. Many points have to be taken into account when deciding about the
most appropriate package (e.g., type of interface, signal speeds and levels, routing complexity on PCB, etc),
which makes choosing a package not always an easy task. Of course, also the chip itself has a large influence
in the choice of a package.

Student Task 6:
What are the properties of an ASIC design that influence the choice of the package type the most?

(a) PGA (b) QFP (c) PLCC (d) DIP (e) TSOP (f) BGA (g) QFN

The following table gives a simplified comparison of some common package types. The packages are rated in
5 categories from totally positive (++) to absolutely negative (- -)!

Type Number of Size Soldering Price Test Note

pins per pin complexity per pin costs
PGA Pin Grid Array 84 - 800 + ++ + + THD
QFP Quad Flat Pack 40 - 400 + + - - SMD
PLCC Plastic Leaded 32 - 124 - - ++ + Socket/SMD
Chip Carrier
DIP Dual Inline Package 8 - 64 -- ++ -- ++ THD, old
TSOP Thin Small 8 - 44 + + - - SMD
Outline Package
BGA Ball Grid Array 84 - 1849 ++ -- + -- SMD
QFN Quad Flat No-leads 8-200 + - - - SMD

THD: through hole device. SMD: surface mounted device.

We will now try to find a package for each one of the following five designs:
1. A 4 Mbit CMOS SRAM, organized as 262’144 words by 16 bits requiring 44 pins including power con-
nections.
2. The Pentium® III Coppermine with 370 pins.
3. An ASIC with 36 pins for a student prototype project.

16
 4. An EEPROM (electrically erasable programmable memory) device for miniaturized portable devices. The
memory is organized as 32 k x 8 bits with I2C interface and requires 8 pins.
5. A 62-pin ASIC design for an ultra small sensor device.

Student Task 7:
Take a look at the table describing the properties of the different package types and decide how appro-
priate each of the packages might be for the given designs. For each design and package give a rating
using the following categories:
[+] appropriate
[-] supported, but less appropriate
[x] not appropriate or not possible because of the pin count

PGA QFP PLCC DIP TSOP BGA QFN

SRAM
Pentium III processor
ASIC prototype
EEPROM
Sensor ASIC

Information on package types, costs, and schematics supported by EUROPRACTICE, which provides the
MPW service for our student projects, can be obtained at
http://www.europractice-ic.com/prototyping packaging.php.

17
7 Toplevel Design and the Problem with Reset Timing
In most digital circuits, an asynchronous reset signal is used to force all registers into a defined state immedi-
ately after power-up. However, care must be taken with reset timing, as will be demonstrated in this section.

1ns

active
Dout_DO ClkxCI
1111

Case1
D Q D Q D Q D Q
Case2
RST RST RST RST Case3
Clk_CI
Case4

RST_RBI Case5
0.5ns 1ns 1ns 1ns
Counter

Figure 12: A circuit with interconnect-delays on the reset signal (left), and a timing diagram with the clock
signal (Clk CI) and five cases of reset removal (right)

Consider the circuit shown in 12 that implements a counter. Its task is to count backwards the number of rising
clock edges after the reset signal is set to 1.

Student Task 8:
1. What are the register values after the active clock edge for the five different cases of reset removal
(see right side of 12).
Case # Register Values
1
2
3
4
5

2. What is the problem? Any suggestions how to solve it?

3. Find a circuit that conditions the Rst RBI signal such that the problem is solved. (Hints can be found
in the VLSI I script)

As you will see in Exercise 3, it is sensible to introduce a new layer in your design hierarchy to accommodate
the pads and the reset synchronization circuitry. In Figure 13 you see the counter (including a scan chain)
within the chip entity.

18
 Chip
Clk_CI Clk_CI
ScanOut_TO ScanOut_TO
ScanEn_TI ScanEn_TI Counter

ScanIn_TI ScanIn_TI
Dout_DO
RST_RBI RST_RBI
Dout0_DO

Dout1_DO

Dout2_DO

Dout3_DO

Figure 13: Chip level solution to the reset timing problem

Student Task 9:
1. Draw the needed pads into the figure and connect them to the ports (you do not need to care about
power pads at this point).
2. Add the reset synchronization circuitry and connect it to the counter.

You are done with this exercise.

E Present your results to an assistant to obtain a sample solution. E

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