15/11/2018 Checking the Timing Between Asynchronous Clock Group Paths

Checking the Timing Between Asynchronous Clock Group Paths

Doc Id: 033777 Product: PrimeTime SI Last Modified: 09/01/2011

Question:

I would like to verify the maximum delay on the asynchronous path in the following circuit.

u1 u2
+----+ +----+
clk1 |D Q|=============|D Q|
o---------------|CP | +--|CP |
+----+ | +----+
o-------------------------------+
clk2

In this circuit, clk1 and clk2 are asynchronous with each other, and both clocks are defined by the create_clock command
in SDC. To verify the delay from u1/CP to u2/D, I tried to constrain the path with the following command:

set_max_delay 1000 -from {u1/CP} -to {u2/D}

However, this command did not constrain the path, and PrimeTime reported a "No constrained paths" message when I ran
the report_timing command on these paths.

Is there a way to verify this kind of path? This circuit example is commonly used in asynchronous FIFOs. Even though clk1
and clk2 are intrinsically asynchronous with each other, the delay on the data paths must be limited to ensure the circuit
functionality.

Answer:

In Primetime SI, the set_clock_groups -asynchronous command makes two assumptions:

1. It assumes false paths between the clk1-to-clk2 and clk2-to-clk1 domain paths.
2. It assumes infinite timing windows for the active aggressor net from the asynchronous clock domains on a victim net—
that is, active asynchronous aggressor timing windows are always considered to overlap with the victim timing window.

Note:
When running Design Compiler or PrimeTime without PrimeTime SI, only the first assumption applies.

To check the timing between the asynchronous clock domains clk1 and clk2, use the set_clock_groups -asynchronous
command with the -allow_paths option, as shown in the following example:

set_clock_groups -asynchronous -name grp1 -group clk1 -group clk2 -allow_paths

Notes:

If the asynchronous relationship is already set before using the -allow_paths option, you must remove the
asynchronous relationship with the remove_clock_group command before applying the set_clock_groups -
asynchronous command with the -allow_paths option.
When using the -allow_paths option, you must also use the -asynchronous option.

With the -allow_paths option, Primetime SI does not apply the false paths between the specified asynchronous clock
domains. However, the tool applies an infinite timing window for the asynchronous clock domain's aggressor net.

Although the -allow_paths option has no effect in Design Compiler or PrimeTime without PrimeTime SI, you should
maintain consistency between your Design Compiler, PrimeTime, and PrimeTime SI constraints by using the
set_clock_groups -asynchronous command with the -allow_paths option.

The check_timing -override_defaults clock_crossing command reports as such the asynchronous clock
domains has valid clock crossings.

Design Compiler considers the asynchronous paths for timing optimization if the -allow_paths option is used.

To apply timing exceptions on the asynchronous paths and override the default single cycle behavior, you can apply the
set_multicycle_path or set_max_delay command if you use the set_clock_groups -asynchronous command

https://solvnet.synopsys.com/retrieve/print/033777.html 1/2
15/11/2018 Checking the Timing Between Asynchronous Clock Group Paths
with the -allow_paths option. For example:

pt_shell> set_clock_groups -asynchronous -name grp1 -group clk1 -group clk2

1
pt_shell> set_max_delay 10 -from u1/CP -to u2/D
1
pt_shell> report_timing -to u2/D
****************************************
Report : timing
-path_type full
-delay_type max
-max_paths 1
Design : test
Version: F-2011.06-SP1
Date : Tue Aug 23 12:12:12 2011
****************************************

No constrained paths.

Next, use the set_clock_groups -asynchronous command with the -allow_paths option:

pt_shell> remove_clock_groups -asynchronous -name grp1

1
pt_shell> set_clock_groups -asynchronous -name grp1 -group clk1 -group clk2 -allow_paths
1
pt_shell> set_max_delay 10 -from u1/CP -to u2/D
1
pt_shell> report_timing -to u2/D
****************************************
Report : timing
-path_type full
-delay_type max
-max_paths 1
Design : test
Version: F-2011.06-SP1
Date : Tue Aug 23 12:15:14 2011
****************************************

Startpoint: u1 (rising edge-triggered flip-flop clocked by clk1)

Endpoint: u2 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max

Point Incr Path

---------------------------------------------------------------
u1/CP (FD1) 0.00 0.00 r
u1/Q (FD1) 1.44 1.44 f
u2/D (FD1) 0.00 1.44 f
data arrival time 1.44

max_delay 10.00 10.00

library setup time -0.80 9.20
data required time 9.20
---------------------------------------------------------------
data required time 9.20
data arrival time -1.44
---------------------------------------------------------------
slack (MET) 7.76

© 2018 Synopsys, Inc. All Rights Reserved.

https://solvnet.synopsys.com/retrieve/print/033777.html 2/2