C8051F350

50 MIPS, 8 kB Flash, 24-Bit ADC, 32-Pin Mixed-Signal MCU

Analog Peripherals High-Speed 8051 µC Core

24-Bit ADC - Pipelined instruction architecture; executes 70% of instructions in 1 or 2
- 0.0015% nonlinearity system clocks
- Programmable throughput up to 1 ksps - Up to 50 MIPS throughput with 50 MHz clock
- 8 external inputs; programmable as single-ended or differential - Expanded interrupt handler
- Programmable amplifier gain: 128, 64, 32, 16, 8, 4, 2, 1 Memory
- Data-dependent windowed interrupt generator - 768 bytes data RAM
- Built-in temperature sensor (±3 °C) - 8 kB Flash; in-system programmable in 512 byte sectors (512 bytes are
Two 8-Bit Current DACs reserved)
Comparator Digital Peripherals
- 16 Programmable hysteresis values and response time
- 17 port I/O; all 5 V tolerant
- Configurable to generate interrupts or reset
- Hardware SMBus™ (I2C™ compatible), SPI™, and UART serial ports
- Low current (0.4 µA) available concurrently
Internal Voltage Reference - 16-bit programmable counter array with three capture/compare modules,
VDD Monitor/Brown-out Detector WDT
On-Chip Debug
- 4 general-purpose 16-bit counter/timers
- Realtime clock mode using PCA or timer and external clock source
- On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required) Clock Sources
- Provides breakpoints, single stepping, watchpoints - Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation
- Inspect/modify memory, registers, and stack - External oscillator: Crystal, RC, C, or clock (1 or 2 pin modes)
- Superior performance to emulation systems using ICE-chips, target - 2x clock multiplier to achieve 50 MHz internal clock
pods, and sockets
- Can switch between clock sources on-the-fly
Supply Voltage: 2.7 to 3.6 V
Package
- Typical operating current: 17 mA at 50 MHz
- 32-pin LQFP (lead-free package)
16 µA at 32 kHz
- Typical stop mode current: <0.1 µA Ordering Part Numbers
Temperature Range: –40 to +85 °C - C8051F350-GQ

Digital Power
VDD
GND
Analog 8 kB P0.0
AV+ Power 8 FLASH
AGND
C2D
Debug HW
P0.1
0 256 Byte P P0.2/XTAL1
Port 0
RST/C2CK
Reset 5 SRAM
Latch
0
P0.3/XTAL2
Brown-
1 512 Byte UART D P0.4/TX
POR XRAM r
Out v P0.5/RX
Timer 0,

External
C 1, 2, 3 P0.6/CNVSTR
XTAL1
XTAL2
Oscillator o SFR Bus 3-Chnl
X
B
P0.7
Circuit System PCA/
Clock r WDT
A
CP0 +
CP0+
24.5 MHz 2% R
Internal
Clock
Multiplier
e SMBus CP0A - CP0-

Oscillator
SPI Bus
VREF+
VREF- P1.0
Port 1
VREF Latch
P1.1
P P1.2
1
AIN0 P1.3
AIN1 Offset D P1.4/CP0A
DAC r
AIN2 v P1.5/CP0
A 24-bit 8-bit
AIN3 M Buffer
+
PGA
IDAC0
P1.6/IDAC0
+ ADC0
AIN4 U P1.7/IDAC1
X
AIN5 8-bit
IDAC1
AIN6 Temp C2D
AIN7 Sensor Port 2
P2.0/C2D
Latch

Precision Mixed Signal Copyright © 2005 by Silicon Laboratories 5.5.2005

 C8051F350
50 MIPS, 8 kB Flash, 24-Bit ADC, 32-Pin Mixed-Signal MCU

Selected Electrical Specifications

(TA = –40 to +85 C°, VDD = AV+ = 3.0 V, VREF = 2.5 V External, PGA Gain = 1x, MDCLK = 2.4567 MHz,
Decimation Ratio = 1920 unless otherwise specified)

PARAMETER CONDITIONS MIN TYP MAX UNITS

GLOBAL CHARACTERISTICS
Supply Voltage 2.7 3.6 V
Supply Current Clock = 50 MHz 17 mA
(CPU active) Clock = 1 MHz 0.5 mA
Clock = 32 kHz; VDD Monitor Enabled 16 µA
Supply Current Oscillator not running; VDD Monitor 0.1 µA
(shutdown) Disabled
Clock Frequency Range DC 50 MHz
24-BIT A/D CONVERTER
Resolution (no missing codes) 24 bits
Integral Nonlinearity Single-ended Mode ±15 ppm FS
Differential Mode
Offset Error ±5 ppm
Gain Error ±0.002 %
Common Mode Rejection 110 dB
Ratio (CMRR)
Power Supply Rejection, 80 dB
DC
Power Supply Current 230 µA

8-BIT CURRENT-MODE D/A CONVERTERS

Resolution 8 bits
Integral Nonlinearity ±0.5 LSB
Differential Nonlinearity Guaranteed Monotonic ±0.5 ±1 LSB

Package Information C8051F350DK Development Kit

D
D1 MIN NOM MAX
(mm) (mm) (mm)

A - - 1.60

A1 0.05 - 0.15

E1 E A2 1.35 1.40 1.45

b 0.30 0.37 0.45

32 D - 9.00 -

PIN 1 D1 - 7.00 -
IDENTIFIER
1
A2 e - 0.80 -

A E - 9.00 -

A1 E1 - 7.00 -
b e

Precision Mixed Signal Copyright © 2005 by Silicon Laboratories 5.5.2005

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