THE READER COLLEGE SARGODHA

Subject: Digital Logic Design Class: MSc.IT

Test: Max Marks: 20

Attempt All the Questions.

Q.No.1: Answer the following questions. /8(2+2+4)

a) Draw the circuit diagram of D-flip flop.

b) What is the difference between NAND gate SR late and NOR gate SR latch.
c) Determine the Q and Q’ for the D-input in the fig. if the flip-flop is negative edge
triggered.

Q.No.2: /12(3+6+3)
Explain the working of JK flip flop. Derive its characteristics and excitation equations. Also show
by diagram that how JK flip flop can be converted into T-Flip-Flop.