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A 0.8-6.3 GHz Spread Spectrum Clock Generator for SerDes Transmitter

Clocking

Conference Paper · December 2010

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 22nd International Conference on Microelectronics (ICM 2010)

A 0.8-6.3 GHz Spread Spectrum Clock

Generator for SerDes Transmitter Clocking

Rania H. Mekky,,2 and Mohamed Dessouki,3

I Electronics & Communication Dept. Ain Shams University, Cairo, Egypt.
2 MEMS Vision, Cairo, Egypt.
3 Mentor Graphics, Cairo, Egypt.
rania mekky@ieee.org
_

Abstract-The implementation of a fully integrated multi­ Since the L� fractional-N PLL is able to generate a fractional
standard low-jitter clock generator is presented. A L� division ratio, the output frequency does not have to be integer
fractional-N phase-locked loop (PLL) is chosen for 0.8 to 6.3 multiple of the reference frequency. Fully integrated PLL
GHz wireline Serializer-Deserializer (SerDes) transmitting clock targets wireline links protocols data with rates ranging from
and spread spectrum clock generator (SSCG) for Serial AT 0.8 to 6.3 GHz, like Ethernet (6.25, 3.125, l.25 GHz), XAUI
Attachment (SATA I, 11, 1lI) characterized by a spread (3.125 GHz), PCIe (5,2.5 GHz) and SATA I, II, III (l.5, 3,6
modulation of 5000 ppm. A mUlti-range voltage-controlled GHz). Design details and implementation are presented in
oscillator (YCO) is presented to handle the wide range of section n. The simulation results are given in section III .
operation. The PLL ex hibits less than 3.5ps rms jitter at 6.3 GHz
Finally, concluding remarks are drawn in section IV.
with power consumption of7 mW from 1.2 V and 2.5 V supply.
EMI reduction is 20 dB. The design has been implemented in 90
2 power
nm CMOS process and occupies an area ofO.14xO.16 mm •
Non sse
"
/
Index Terms- Phase-locked loop (PLL), Serializer­
5000 pp';:;" v �sse
Deserializer (SerDes), Spread spectrum clock generator (SSCG).
0.995f fo
o
(a) (b)
I. INTRODUCTION
Fig. I: (a) sse and non-SSe (b) Power spectral desinty of
on-retum-to-zero (NRZ) serial data communication is
N frequently used for Gb/s wireline link protocols. To
sse and non-SSe
II. L�FRACTIONAL-N PLL DESIGN
meet these increasingly demanding protocols cost-
effectively, Serializer-Deserializer (SerDes) transceivers have Fig. 2 shows the fractional-N PLL block diagram. The major
to span multiple data rates to have wide range of drawback of using fractional-N PLL is the output fractional
compatibility; hence, the SerDes transmitting PLL has to spurs. A L� modulator generates a pseudo-random sequence
cover as wide range as possible with satisfactory performance that controls the division ratio of the multi-modulus divider
[1]. The faster operating data rates results in a significant (MMD), so that the phase noise and spurious contents are
electromagnetic interference (EMl). EMI is one of the major
pushed to higher offset frequencies, where the existing PLL
noise sources in high-speed interfaces. Several methods for
loo p filter can easily cut them off [3].
EMI reduction have been used such as coaxial cables and
shield wires. However, spread spectrum clocking (SSC) is the l u,l
l' 2.5V Domain
simplest and most efficient method for EMI reduction. SSC is VCO
U
a frequency modulation technique, which spreads the clock
over larger range. The modulation frequency is usually
selected to be larger than 30 kHz (j",) to avoid the cross talk
with the audio band, spread spectrum clock generator (SSCG)
is standard for SATA I, 11, III with 5000 ppm frequency
deviation as shown in Fig. 1.

L� fractional-N phase-locked loop (PLL) based clock

generators are used in wireline communication to meet the
different standards requirements and SSCG by applying the
modulation on the frequency divider [2]. For motherboard
applications, the crystal oscillator frequency is 100 MHz.

978-1-4244-5816-5/09/$26.00 ©2009 IEEE

Two different supply domains are introduced (shown in Fig.
2). The phase-frequency detector (PFD), charge pump (CP),
loop filter (LF), voltage-controlled oscillator (VCO) are on
the 2.5 V domain (VDDA), the MMD and L� modulator are
on the 1.2 V domain (VDD). There is a voltage level shifter
between the two domains. The advantage of having two
supply domains is to isolate the sensitive analog circuits from
the MMD and L� modulator supply noise, which minimize
the rms jitter.
A. ELl Modulator
A third order multi-stage-noise-shaping (MASH) L�
modulator (shown in Fig. 3) is used to produce the fractional
division ratio N+LlN (0< LlN <1) by changing the divider
modulus among N-3, N-2, ...., N+3, N+4, where N is the
integer modulus of the frequency divider and LlN is the
average fractional number generated from the L� modulator.
However, the quantization noise degrades the total jitter since
the intrinsic modulus of the frequency divider is still an
integer. Dithering is achieved by adding pseudo random
sequence to the LSB [4].
chosen to meet the jitter requirements. As shown in Fig. 5, an
additional pole, R3C3, is added to suppress the reference and
fractional spurs, the additional attenuation, Alt, can be
obtained from (1)
Att = 20 log[(2iif:'efR3C3)2 + 1] (1)
The PLL stability becomes an important issue, so the PLL
bandwidth has to be carefully determined. The frequency
modulation of the SSCG requires large bandwidth to track the
frequency changes. On the other hand, narrow bandwidth is
needed to suppress the reference and fractional spurs. In
general, loop bandwidth has to meet in-band RMS phase
error (Brllls) less than 1 ° to meet the jitter requirements.
Ipump
-____....--_--'\Mr-1�O
...., Vetrl

Fig. 5: Third order loop filter

k The Dynamic range of the Lth order L� modulator has to meet

(2)

1 2L + 1 (OSR fL+'
.
2 1r2L ejJ
> [J;'FD)2
/1+
Y I7
(2)

where OSReffi fpf'7), Llfn are the oversampling ratio, PFD

frequency and in-band noise frequency, respectively, OSRejJ
is given by (3)
Fig. 3: Third order MASH �A modulator OSR ejJ =
jPFD (3)
2fc
B. SSCG ELl Input Generator where fe, is the PLL bandwidth. From (2-3 ) and with some
approximations the PLL bandwidth is obtained as
Fig. 4 shows the SSCG L� input generator used at the
input of the L� modulator. Up/Down counter is used to
generate the spread spectrum clocking profile, a frequency
f
C <
[(8 )2 (21ryL5l(2/�_I)
�
J2
.
L + 0.
+
.J PFD (4)

divider and a control logic control the counter according to

the protocol data rate. For third order L� modulator, fpFD is 100 MHz and Bnlls is less
than 1 O,!C has to be less than 2.44 MHz [5]. !c is chosen to be
2.4 MHz with 60° phase margin , which is sufficient to track
the frequency modulation of the SSCG with lock time is less
than lOflS.

D. Programmable Frequency Divider

Fig. 4: �A input generator
C. System Design and Loop Filter
The key component that is used to achieve the desired
transfer function is the loop filter (LF). The out-band
quantization noise from L� modulator will be suppressed by
the low-pass characteristics of the PLL, so the PLL order
must be at least one order higher than L� modulator. As the
L� modulator is third order, a forth order, type II PLL is
An extended division ratio multi-modulus divider (MMD)
is chosen to be the programmable frequency divider, to meet
the output frequency range (N=8-127) [6]. MMD is shown in
Fig. 6.lt consists of six typical 2/3 divider cells, for the high
operating frequencies, the first two stages are realized with
current-mode logic (CML) configuration, whereas the
remaining four stages are implemented in CMOS logic to
lower the power consumption. Each stage is optimized for the
given maximum operating frequency. The total current
consumption in the divider is 1.8 mA form 1.2 V supply.
 Fig. 6: Multi-modulus divider

7.0C Range_Ctrl�O
E. VCO 6.SC Ranb",_Ctrl�VDDA
6.0C
The ring oscillator is chosen to generate the PLL output S.SG

clock to achieve low power and area. Fig. 7 shows the s.oc 2
4.SC
N'
proposed VCO design. MI-M3 constitute the V-I circuit, ::s
4.0C
3.SC
which converts the control voltage (Veld) to current that drives ....: 3.0C
2.SC
the current-controlled oscillator (CCO) and controls the 2.0C
1.5G
output frequency of CCO. To maintain linear VCO l.OC
O.SG
conversion gain, Kvco, M2-� are designed with large widths o.oc
-o.sc
for minimum overdrive voltage. The minimum overdrive
0.6 0.8 l.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
voltage of the PMOS transistors guarantees that the NMOS
transistor MI stays in saturation for almost the entire Velr!
range, hence Kvco is linear. �-M6 perform a gain-boosting
Fig. 8: veo tuning curve
function, which is used to have high static and dynamic
power-supp Iy-rejection-ratio (PSRR) [7].
F. PFDICharge Pump
The multi-range ring oscillator is achieved by additional
current source, 1, which is added to the V-I circuit, when 1 is The PFD adopted in the system is a traditional tri-state
ON it shifts the whole frequency range. A low impedance PFD [8]. Fig. 9 shows the gain-boosting charge pump
switch M7 controls to the current source operation. MI-M7 are proposed in [9]. This architecture solves the current mismatch
high-voltage [0 devices, which operate from 2.5 V. The CCO problem due to channel length modulation and process
is composed of three pseudo-differential inverters that use variations. In addition to gain-boosting, which is used to
low-voltage core devices, which can oscillate on higher increase the output impedance of the CP, a low-voltage
frequency range than the high-voltage 10 devices. The supply cascode current mirror is used to enhance current matching
of the CCO, Vcco, does not exceed VDD over the process, over process corners. Matching between the two current
temperature and voltage variations. The CCO output voltage sources of the CP can be achieved with current mismatch
level after buffers is 1.2 V. Fig. 8 shows the post layout VCO equals to 0.6% in typical conditions and 1 % over all process
tuning curves ranging 0.4 to 6.5 GHz. Curve 1 (1 is OFF) has variations. The CP output compliance range of 0.3 to 2.2 V is
a tuning range from 0.4 to 4.6 GHz. Curve 2 (1 is ON) has a achieved for 2.5 V supply using the high-voltage 10 devices.
tuning range up to 6.5 GHz. The V-I circuit and CCO
consume 1.2 rnA from 2.5 V supply and the buffers consume
0.3 rnA from 1.2 V supply.

VDDA VDDA

Range Clrll

Fig. 7: veo Schematic Fig. 9: Gain-boosting charge pump

 III. SIMULATION RESULTS TABLE I. PERFORMACE SUMMARY

The proposed PLL has been implemented in 90 nm CMOS Order, Type Forth order, Type II

technology. Fig. 10 shows the output frequency spectrum for Reference Frequency ([,4) 100 MHz
SATA IT (3 GHz). Fig. 11 shows the SSC frequency spectrum Loop Bandwidth (fc) 2A MHz
for SATA n. The frequency is spreaded over 15 MHz (5000
Phase Margin 60°
ppm of 3 GHz) , the EMT reduction is 20dB. The non-SSC
Output Frequency Range (!o) 0.8 - 6.3 GHz
rms jitter is less than 3.5ps at 6.3 GHz. This value is obtained
SSCG Frequencies 1.5, 3, 6 GHz (SATA I, II, III)
from the hystogram of the output eye diagram of transient
SSCG Modulation Method Modulation of the rrequency divider
noise simulation. Fig.12 shows the system layout, the
capacitors have been implemented as NMOS capacitors, the Modulation profile ([,,,) 30-33 kHz triangular
2
system occupies an area of O.l4xO.l6 mm . Table 1. Frequency Deviation -5000 ppm

summerizes the post layout simulation results. EMI Reduction 20 dB

Lock Time Less than 10flS

0.0

l
RMS Jitter (non-SSC) Less than 3.5ps

-20.0 .. .. Supply Voltage 2.5 V, 1.2 V

3.5 mW from 2.5 V

Power Consumption
6i' -40.0 3.5 mW from 1.2 V
�
f-
Area o 14xO.16 mm'
... -60.0
... Process 90 nm CMOS Technology

-80.0 IV. CONCLUSION

Fully integrated low-jitter multi-standard PLL has been

2.8SG 2.90G 2.9SG 3.00G 3.0SG 3.10G 3.1SG 3 implemented. A multi-range YCO is proposed to handle the
f(Hz) wide range of operation. The system can support operating
frequency range from 0.8 to 6.3 GHz with less than 3.5 ps
Fig. 10: FFT for output frequency (SATA ll) rms jitter and power consumption of 7 mW at 6.3 GHz. The
system can also provide spread spectrum clock for SATA I,
II, III with 30 to 33 kHz triangular modulation profile and
5000 ppm frequency deviation with EM! reduction 20 dB.
2
The PLL occupies an area ofO.l4xO.l6 mm .
6i'
�
REFERENCES
t
...
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R. R Kennedy, M. 1. Gilsdorf, " A Verstaile 90-nm CMOS Charge­
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State Circuits, volAI, Aug. 2006.
f(Hz)
[2] Y-B. Hsieh and Y-H. Kao, " A Fully Integrated Spread Clock
Generator Using Two-Point Delta-Sigma Modultaion", IEEE
Fig. 11: FFT for sse (SATA ll) International Symposium on Circuits and Systems, ISCAS, May 2007.

[3] Mucahit Kozak & Izzet Kale. Rigorous Analysis of Delta Sigma
Modulators for Fractional-N PLL Frequency Synthesis. IEEE Trans.
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[4] Kaveh Hosseini & Michael Peter Kenne. Maximum Sequence Length
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[5] W.Rhee, 8.-S. Song and AAli,"A I.I-GHz CMOS fractional-N

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[9] R. H. Mekky and M. Dessouky. "Design of a Low-Mismatch Gain­

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Fig. 12: System layout

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