e-CAD AND VLSI LAB

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 CONTENTS

NAME OF THE EXPERIMENTERIMENT Page no.

i INTRODUCTION TO XILINX 9.2I

ii INTRODUCTION TO PORTING OF SPARTAN 3E

1 HDL CODE TO REALIZE ALL THE LOGIC GATES

2 DEIGN OF 2-TO 4-DECODER

3 DESIGN OF 8-TO-3 ENCODER(WITHOUT AND WITH PARITY)

4 DESIGN OF 8 TO-1 MULTIPLEXER

5 DESIGN OF 4 BIT BINARY TO GRAY CONVERTER

6 DESIGN OF MULTIPLEXER/ DE-MULTIPLEXER

7 DESIGN OF FULL ADDER USING 3 MODELING STYLES

8 DESIGN OF FLIP-FLOPS: SR,D,JK,T

9 DESIGN OF 4BIT BINARY ,BCD COUNTERS(SYNC&ASYNC)

10 FINITE STATE MACHINE DESIGN

11 CMOS inverter layout ( usingMicrowind3.5lit)

12 CMOS NAND.XOR AND NOR LAYOUT (using Micro wind 3.5lit)

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Xilinx Manual:

Xilinx ISE is a software tool produced by Xilinx for synthesis and analysis of HDL designs,
which enables the developer to synthesize ("compile") their designs, perform timing analysis,
examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the
target device with the programmer

In our Lab, the scope is limited to design and analyze the design using test benches &
simulation
The following is the step by step procedure to design in the Xilinx ISE:

1 New Project Creation

Once the Xilinx ISE Design suite is started, open a new project & enter your design
name and the location path By default „HDL‟ is selected as the top-level source type (If
not, please select Top-level source type as „HDL‟)

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2.Continue to the next window and check if the Preferred Language is selected as „Verilog‟

3. Proceed by clicking „Next‟ and create a „New Source‟ using the „Create New Source‟
Window

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 4. Select the source type as „Verilog Module‟ and input a filename and proceed to „Next‟
In the next window „Define Module‟ enter the ports

5. Finish with the new project setup with the „Summary‟ window

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6. Once „Finish‟ is selected a pop-up appears to create the directory Select „yes‟

7. Then proceed to „Next‟ in the “New Project Wizard‟ to „Add Existing Sources‟ „Add
source‟ if an existing source is available, If not proceed to „Next‟ and finish with the
„Project Summary‟ window

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Design Entry and Syntax Check
The ports defined during the „Project Creation‟ are defined as a module in the „filenamev‟
file

8. Input your design (Verilog code) within the module definition

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10. Select the design from the „Hierarchy “window In the below window of Processes
„Implement Design „would be orange (in color) ready for implementation

11. Double click on implement design, it turns green (in color) once the design is
implemented successfully and the Summary report is displayed

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12. Test-Bench creations, Simulation & Verification

To add a test-bench to the existing design, right click on the „v‟ file from the Hierarchy
window and select „New Source‟

13. Select „Verilog Text Fixture‟ from the Select Source Type and name the Test-Bench

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14. Continue to „Finish‟ and a test bench is added in the project area

15. Edit the test bench as per your simulation requirements and select „Behavioral
Simulation‟ in the „Design Window‟ In the Processes window Isim Simulator would be
displayed First Proceed with the Behavioral Check Syntax

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16. Double clicks on „Behavioral Check Syntax‟ & check for no errors

17. Then double click on „Simulate Behavioral Model‟ and the ISIM simulator window
would open Check for the outputs

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Procedure for porting the SPARTAN 3E
1. Go to User Constraints -> Assign package pins. Then the window shown as below is opened. Now we
have to give input and output port numbers in “Loc” coloum. Here we have two inputs and two
outputs.

2. Let inputs be L13 and L14 and outputs be F12 and E12 as shown below.

3. After giving port numbers, save the file as shown below.

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4. Now a window named Bus Limiter will open. Here select “symplify verilog default[]” and click OK.

5. Come back to program and follow: Generate Programming file -> Configure device

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6. Now iMPACT pop will open and there select “Configure devices using Boundary scan” , next click
FINISH.

7. Then Progress dialogue will open, showing “Executing command…….”. We have to wait until the
execution is completed.

8. After execution, the window shown as below will open. It shows device selection i.e., Spartan 500e.

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9. Already created .ucf file is added to Spartan as shown below:

10. Right click on the first icon -> select “assign new configuration file” as shown below:

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11. Then select .bit file as shown and click OPEN.

12. After opening file, again right click on first device ans select PROGRAM

13. Then click on APPLY as shown:

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14. Finally we will get a pop-up showing “program succeeded”. This will finish dumping process.

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EXPERIMENT: 1- HDL CODE TO REALIZE ALL LOGIC GATES
AIM: To develop the source code for logic gates by using VERILOG and obtain the simulation,
synthesis, place and route and implement into FPGA

SOFTWARE & HARDWARE:

1. XILINX 92i
2. FPGA-SPARTAN-3

LOGIC DIAGRAM:

AND GATE: OR GATE:

LOGIC DIAGRAM: TRUTH TABLE: LOGICDIAGRAM TRUTH TABLE:

A B Y=AB A B Y=A+B
0 0 0 0 0 0
0 1 0 0 1 1
1 0 0 1 0 1
1 1 1 1 1 1

NOT GATE: NAND GATE:

LOGIC DIAGRAM: TRUTH TABLE: LOGICDIAGRAM TRUTH TABLE
A B Y=(AB)’
A Y=A’
0 0 1
0 0 0 1 1
0 1 1 0 1
1 1 0

NOR GATE: XOR GATE:

LOGIC DIAGRAM: TRUTH TABLE: LOGICDIAGRAMTRUTH TABLE:

A B Y=(A+B)’
A B
0 0 1
0 1 0 0 0 0
1 0 0 0 1 1
1 1 0 1 0 1
1 1 0

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XNOR GATE:
LOGIC DIAGRAM: TRUTH TABLE:

A B
0 0 1
0 1 0
1 0 0
1 1 1
VERILOG SOURCE CODE:

module logicgates1(a,b,c);
input a;
input b;
output[6:0]c;
assign c[0]= a & b;
assign c[1]= a | b;
assign c[2]= ~(a &
b); assign c[3]= ~(a |
b); assign c[4]= a ^
b; assign c[5]= ~(a ^
b); assign c[6]= ~ a;

endmodule

Simulation output:

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Synthesis RTL Schematic:

RESULT:

Thus the OUTPUT‟s of all logic gates are verified by synthesizing and simulating the
VERILOG code.

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EXPERIMENT: 2-DESIGN OF 2-TO-4 DECODER

AIM: To develop the source code for decoder by using VERILOG and obtain the simulation,
synthesis, place and route and implement into FPGA

SOFTWARE & HARDWARE:

1. XILINX 9.2i
2. FPGA-SPARTAN-3.
3.
LOGIC DIAGRAM: TRUTH TABLE:

A B C Z(0) Z(1) Z(2) Z(3)

0 0 1 0 1 1 1
0 1 1 1 0 1 1
1 0 1 1 1 0 1
1 1 1 1 1 1 0

VERILOG SOURCE CODE:

module decoderbehv(a, b, en, z);

input a;
input b;
input en;
output [3:0] z;
reg [3:0] z;
reg abar,bbar;
always @ (a,b,en) begin
z[0] = (abar&bbar&en);
z[1] = (abar&b&en);
z[2] = (a&bbar&en);
z[3] = (a&b&en);
end
endmodule

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Simulation output:

Synthesis RTL schematic:

RESULT:

Thus the OUTPUT‟s of decoder are verified by synthesizing and simulating the VERILOG
Code

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EXPERIMENT: 3- DESIGN OF 8-TO-3 ENCODER
AIM: To develop the source code for logic gates by using VERILOG and obtain the simulation, synthesis,
place and route and implement into FPGA

SOFTWARE & HARDWARE:

1. XILINX 92i
2. FPGA-SPARTAN-3

ENCODER:
TRUTH
LOGIC DIAGRAM: TABLE:

D0 D1 D2 D3 D4 D5 D6 D7 X Y Z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

VERILOG SOURCE CODE:

module encoderbehav(d, a,b,c);

input [7:0] d;
output a;
output b;
output c;
reg a,b,c;
always @ (d [7:0]) begin
a= d[4] | d[5] | d[6] | d[7];
b= d[2] | d[3] | d[6] |
d[7]; c= d[1] | d[3] | d[5] |
d[7]; end
endmodule

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Simulation output:

Synthesis RTL schematic:

RESULT:

Thus the OUTPUT‟s of Encoded are verified by synthesizing and simulating the VERILOG
code

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EXPERIMENT: 4- 8X1 MUULTIPLEXER
AIM: To design and implement 8:1 Multiplexer.

SOFTWARE: Xilinx 9.2i, Simulator: ISE Simulator. Synthesis Device: spartan3E.

VERILOG CODE:

module Mux8x1(a, b, c, d, e, f, g, h, s1, s2, s3, y);

input a, b, c, d, e, f, g, h;

output y;

assign y= (s3==0)? (s2==0) ? ((s1==0)? a:b):(s1==0)?c:d:

(s1==0)? ((s1==0)?e:f):(s1==0)?g:h;

endmodule

SIMULATION:

Force commands:

force s1 0 0ns,1 5ns,0 10ns,1 15ns, 0 20ns, 1 25ns, 0 30ns, 1 35ns, 0 40ns;

force s2 0 0ns, 1, 10ns, 0 20ns, 1 40ns;

force s3 0 0ns, 1 20ns;

Wave forms

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SYNTHESIS RTL SCHEMATIC:

RESULT: Verilog code for 8X1 MULTIPLEXER has been simulated and synthesi

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EXPERIMENT: 5-DESIGN OF 4-BIT BINARY TO GRAY CONVERTER

AIM:
To develop the source code for binary to gray converter by using VERILOG and obtained
the simulation, synthesis, place and route and implement into FPGA

SOFTWARE & HARDWARE:

1. XILINX 92i
2. FPGA-SPARTAN-3

CODE CONVERTER (BCD TO GRAY):

TRUTH TABLE:

BCD GRAY
0000 0000
0001 0001
0010 0011
0011 0010
0100 0110
0101 0111
0110 0101
0111 0100
1000 1100
1001 1101

LOGIC DIAGRAM:

Behavioral Modeling:

module b2g_behv(b, g);

input [3:0] b;
output [3:0] g;
reg [3:0] g;

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 always@(b)
begin g[3]=b[3];
g[2]=b[3]^b[2];
g[1]=b[2]^b[1];
g[0]=b[1]^b[0];
end
endmodule

Simulation output:

Synthesis RTL schematic:

RESULT:
Thus the OUTPUT‟s of binary to gray converter are verified by synthesizing and simulating
the VERILOG code

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EXPERIMENT: 6-DESIGN OF MULTIPLEXER AND DEMULTIPLEXER
AIM:
To develop the source code for multiplexer and Demultiplexer by using VERILOG and
obtain the simulation, synthesis, place and route and implement into FPGA

SOFTWARE & HARDWARE:

1. XILINX 92i
2. FPGA-SPARTAN-3

MULTIPLEXER:

LOGIC DIAGRAM:
TRUTH TABLE:

SELECT OUTPUT
INPUT
S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

VERILOG SOURCE CODE:

module mux_behv(d, s0, s1,

y); input [3:0] d;
input
s0;
input
s1;
output
y;
reg y;
reg
s0bar,s1bar;
reg p,q,r,s;
always@(d or s0 or s1)
begin
s0bar=~s0;s1bar=~s
1;

p=(d[0]&s0bar&s1bar);
q=(d[1]&s0bar&s1);

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r=(d[2]&s0&s1bar);

s=(d[3]&s0
&s1); y=p |
q |r |s;
end
endm
odule

Simulation output:

Synthesis RTL schematic:

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DEMULTIPLEXER:

LOGIC DIAGRAM:
`
TRUTH TABLE:

INPUT OUTPUT
D S0 S1 Y0 Y1 Y2 Y3
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

Source Code:

module demux_behv(s0, s1,d, y, e);

input s0;
input s1; input
d,e; output
[3:0] y;
reg [3:0] y;
reg s0bar,s1bar;
always@(d or s0 or s1)
begin
s0bar=~s0;
s1bar=~s1;
y[0]=(d&s0bar&s1bar&e);
y[1]=(d&s0bar&s1&e);
y[2]=(d&s0&s1bar&e);
y[3]=(d&s0&s1&e);
end
endmodule

Simulation output:

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Synthesis RTL schematic:

RESULT:

Thus the OUTPUT‟s of Multiplexers and Demultiplexers are verified by synthesizing and
simulating the VHDL and VERILOG code

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EXPERIMENT: 7-DESIGN OF FULL ADDER USING THREE MODELLING
STYLES

AIM: To develop the source code for full adder using three modeling styles by using VERILOG and
obtained the simulation, synthesis, place and route and implement into FPGA

SOFTWARE & HARDWARE:

1. XILINX 92i
2. FPGA-SPARTAN-3

FULL ADDER:

LOGIC DIAGRAM: TRUTH TABLE:

A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

VERILOG SOURCE CODE:

Dataflow Modeling:

module fulladddataflow(a, b, c, sum,

carry); input a;
input b;
input c;
output sum;
output carry;
assign#2 p=a&b;
assign#2 q=b&c;
assign#2 r=c&a;
assign#4 sum=a^b^c;
assign#4carry =(p1 | p2) | p3;

endmodule

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Behavioral Modeling:

module fuladbehavioral(a, b, c, sum, carry);

input a;
input b;
input c;
output sum;
output carry;
reg sum,carry;
reg p1,p2,p3;
always @ (a or b or c)
begin sum = (a^b)^c;
p1=a & b;
p2=b & c;
p3=a & c;
carry=(p1 | p2) |
p3; end
endmodule

Structural Modeling:

module fa_struct(a, b, c, sum,

carry); input a;
input b;
input c;
output sum;
output carry;
wire t1,t2,t3,s1
xor
x1(t1a,b),
x2(sum,s1,c);
and
a1(t1,a,b),
a2(t2,b,c),
a3(t3,a,c);
or
o1(carry,t1,t2,t3);
endmodule

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Simulation output:

Synthesis RTL schematic:

RESULT:
Thus the OUTPUT‟s of full adder using three modeling styles are verified by
synthesizing and simulating the VERILOG code

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EXPERIMENT: 8-DESIGN OF FLIP FLOPS (SR, JK, and D)

AIM: To develop the source code for FLIP FLOPS by using VERILOG and obtained the simulation,
synthesis, place and route and implement into FPGA

SOFTWARE & HARDWARE: XILINX 92i, FPGA-SPARTAN-3

SR FLIPFLOP:

LOGIC DIAGRAM: TRUTH TABLE:

Q(t) S R Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 X
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 X

VERILOG SOURCE CODE:

Behavioral Modeling:

module srflipflop(s, r, clk, rst, q, qbar);

input s;
input r;
input clk;
input rst;
output q;
output qbar;
reg q,qbar;
always @ (posedge(clk) or posedge(rst)) begin
if(rst==1'b1) begin
q= 1'b0;qbar= 1'b1;
end
else if(s==1'b0 && r==1'b0)
begin
q=q; qbar=qbar;
end

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else if(s==1'b0 && r==1'b1)
begin
q= 1'b0; qbar= 1'b1;
end
else if(s==1'b1 && r==1'b0)
begin
q= 1'b1; qbar= 1'b0;
end
else
begin
q=1'bx;qbar=1'bx;
end
end
endmodule

Simulation output:

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Synthesis RTL schematic:

JK FLIPFLOP:

LOGIC DIAGRAM: TRUTH TABLE:

Q(t) J K Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

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VERILOG SOURCE CODE:

Behavioral Modeling:

module jkff(j, k, clk, rst, q, qbar);

input j;
input k;
input clk;
input rst;
output q;
output qbar;
reg q;
reg qbar;
always @ (posedge(clk) or posedge(rst)) begin
if (rst==1'b1)
begin
q=1'b0;
qbar=1'b1;
end
else if (j==1'b0 &&
k==1'b0) begin
q=q;
qbar=qbar;
end
else if (j==1'b0 &&
k==1'b1) begin
q=1'b0;
qbar=1'b1;
end
else if (j==1'b1 &&
k==1'b0) begin
q=1'b1;
qbar=1'b0;
end
else
begin
q=~q;
qbar=~qbar;
end
end
endmodule

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Simulation output:

D FLIPFLOP:
LOGIC DIAGRAM: TRUTH TABLE:

Q(t) D Q(t+1)
0 0 0
0 1 1
1 0 0
1 1 1

VERILOG SOURCE CODE:

Behavioral Modeling:
module dff(d, clk, rst, q, qbar);
input d;
input clk;
input rst;
output q;
output qbar;
reg q;
reg qbar;
always @ (posedge(clk) or posedge(rst)) begin
if (rst==1'b1)
begin
q=1'b0;
qbar=1'b1;
end
else if (d==1'b0)
begin
q=1'b0;
qbar=1'b1;
end

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 begin
q=1'b1
;
qbar=1
'b0;
end
e
nd
endmo
dule

Simulation output:

RESULT:
Thus the OUTPUT‟s of Flip flops using three modeling styles are verified by
synthesizing and simulating the VERILOG code

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EXPERIMENT-9- DESIGN OF 4BIT BINARY BCD COUNTERS (SYNC& ASYNC)

AIM: To design 4-bit binary bcd counter by using VERILOG and obtained the simulation,
synthesis, place and route and implement into FPGA.
SOFTWARE: Xilinx 9.2i, Simulator: ISE Simulator. Synthesis Device: Spartan3E.

PROGRAM:
module Counter_4Bit ( clk ,reset ,dout );

output [3:0] dout ;

reg [3:0] dout ;

input clk ;

wire clk ;

input reset ;

wire reset ;

initial dout = 0;

always @ (posedge (clk)) begin

if (reset)

dout <= 0;

else

dout <= dout + 1;

end

endmodule

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SIMULATION RESULT:

SYNTHESIS RTL SCHEMATIC:

RESULT: Hence BCD counter is designed by using VERILOG and obtained the simulation,
synthesis, place and route and implement into FPGA.

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 EXPERIMENT-10 -FINITE STATE MACHINE DESIGN

AIM: 1.Write a VHDL Program for a Moore machine for a given sequence 1011.

2. Simulate and Synthesis the Moore machine Using Xilinx.

SOFTWARE: Xilinx 9.2i, Simulator: ISE Simulator. Synthesis Device: Spartan3E.

BLOCK DIAGRAM:

PS
NS
Next state Memory Output
inputs generation decoder
Elements
(Input logic) (Output
(reg)
logic)

CLK

Present state
1

VHDL PROGRAM:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY moore_fsm_1011 IS

port(x,clk:in bit;z:out bit);

END moore_fsm_1011 ;

ARCHITECTURE fsm_1011 OF moore_fsm_1011 IS

type moore is(s0,s1,s2,s3,s4);

signal ps,ns:moore;

BEGIN

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comb_part:process(x,ps)

BEGIN

case ps is

when s0=>

if x='1'then

ns<=s1;

else

ns<=s0;

end if;

when s1=>

if x='0'then

ns<=s2;

else

ns<=s1;

end if;

when s2=>

if x='1'then

ns<=s3;

else

ns<=s0;

end if;

when s3=>

if x='1'then

ns<=s4;

else

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 ns<=s2;

end if;

when s4=>

if x='1'then

ns<=s1;

else

ns<=s2;

end if;

end case;

end process comb_part;

seq_part:process(clk)

BEGIN

if(clk='1' and clk' event)then

if(ps = s3 and x = '1')then

z <= '1';

else z <= '0';

end if;

ps<=ns;

end if;

end process seq_part;

END fsm_1011;

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SIMULATION:

SYNTHESIS RTL DIAGRAM:

RESULT: The functionality of the more machine for a given sequnce1011 is verified by writing
the VHDL code and studying the obtained waveform and synthesis results.

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 EXPERIMENT-11 –CMOS INVERTER LAY OUT

AIM: To design CMOS inverter lay out by using Micro wind tool and obtained the simulation.
SOFTWARE: Micro wind 3.5lit.

CMOS INVERTER SCHEMATIC:

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CMOS INVERTER LAYOUT:

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CMOS INVERTER SIMULATION RESULTS:

RESULT: The functionality of the CMOS INVERTER is verified by drawing layout and
obtained the simulation waveform.

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 EXPERIMENT-12 –CMOS NAND GATE LAY OUT

AIM: To design CMOS NAND gate lay out by using Micro wind tool and obtained the
simulation.
SOFTWARE: Micro wind 3.5lit.

CMOS NAND GATE SCHEMAATIC:

CMOS NAND GATE LAYOUT:

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53
CMOS NAND GATE SIMULATION RESULTS:

RESULT: The functionality of the CMOS NAND is verified by drawing layout and obtained the
simulation waveform.

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 EXPERIMENT-12 –CMOS NOR GATE LAY OUT

AIM: To design CMOS NOR gate lay out by using Micro wind tool and obtained the
simulation.
SOFTWARE: Micro wind 3.5lit.

CMOS NOR GATE SCHEMATIC:

CMOS NOR GATE LAYOUT:

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56
CMOS NOR GATE SIMULATION RESULTS:

RESULT: The functionality of the CMOS NOR is verified by drawing layout and obtained the
simulation waveform.

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 EXPERIMENT-12 –CMOS XOR GATE LAY OUT

AIM: To design CMOS XOR gate lay out by using Micro wind tool and obtained the
simulation.
SOFTWARE: Micro wind 3.5lit.

CMOS XOR GATE SCHEMATIC:

CMOS XOR GATE LAYOUT:

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CMOS XOR GATE SIMULATION RESULTS:

RESULT: The functionality of the CMOS XOR is verified by drawing layout and obtained the
simulation waveform

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