Outline

1. The need for PLL

2. PLL Specifications
3. PLL Structure
Introduction to PLL 4. Type-I PLL Design
5. More PLL Types
6. Exercise (written + Matlab)

Ahmed Ashry

Introduction to PLL Ahmed Ashry 2

Outline (1/6) Frequency selection

(1) The need for PLL.

•Why PLL is needed?

•Why not simple Oscillator?
•Why not simple VCO? • LO frequency choose which channel to select.
• Error in LO frequency = wrong channel or more distortion

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LO needed VCO is possible?
• Very accurate. • Ideally, VCO can be used
– Example: GSM 900MHz ± 0.1ppm = ± 90Hz to produce any desired
– On-chip LC oscillator = ± 10% = ± 90MHz frequency.
– Crystal Oscillators (XO) are accurate, but:
• Low Frequency ~ 10MHz. • However, practically this
• Fixed.
is impossible.
• Programmable:
– It is always needed to change the channel.
– XOs are fixed.
– What about VCO (Voltage Controlled Oscillator) ?

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VCO is possible? No! VCO is possible? No! (2)

• The needed accuracy • Process and

requires very stable temperature variations • VCO (or generally free-running oscillator) has
control voltage make it more difficult poor close-in phase noise compared to PLL.

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Outline (2/6) PLL Specifications (1)
• Tuning Range:
• The frequency band covered by the PLL.

(2) PLL Specifications. • It must cover the target application.

• GSM: 890MHz – 915MHz

•Tuning Range • Step size:

•Step Size • Must be at least equal to channel spacing.
• GSM: 200kHz
•Settling Time
•More…….
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PLL Specifications (2) PLL Specifications (3)

• Settling Time: • Frequency Stability:
• Fast switching between channels. • Accuracy of reference source.
• GSM: 280us (90Hz error) • GSM: 90Hz/900MHz =
0.1ppm

• Inaccurate frequency

wrong selection
worst BER

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PLL Specifications (4) Outline (3/6)
• Spurs (undesired
harmonics): cause
interferes with other
channels. (3) PLL Structure.
• Phase noise (random •PLL Block diagram.
fluctuation of carrier
frequency): cause •PLL Linear Model.
interferes with other •PLL Main Blocks.
channels.
•PLL Simple Design.
•PLL Phase Noise
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What is “Phase” ? PLL (Phase-Locked Loop)

• It is simply the number of cycles. V (t ) = A ⋅ sin (ω ⋅ t + ϕ o ) • PLL is a negative feedback system.
• 1 cycle = 2π • It compares “Phase” not “Amplitude”
• If the frequency is constant: V (t ) = A ⋅ sin (ϕ (t )) • When PLL is in lock (steady-state), feedback phase is
ϕ (t ) = ω ⋅ t + ϕo equal to the input phase.
• Or, generally:
t
ϕ (t ) = ∫ ω (t ) ⋅ dt
0

d
ω (t ) = φ (t )
dt

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PLL Linear Model PLL Blocks (1-Phase detector) 1
• PLL is a non-linear system. • XOR is the simplest PD
• However, under certain conditions (near lock), it
can be “linearized”.
• State variable is the phase.
∆φ = 0 → D = 0% → Vd = 0

π
∆φ = ± → D = 50% → Vd = Vdd / 2
2

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PLL Blocks (1-Phase detector) 2 PLL Blocks (2-Divider)

• For stable operation, • Toggle Flip-Flop T-FF can acts a divide by 2.
the loop should be • Cascading T-FFs can divide by 2n
designed, such that • Adding some logic can extend the division ratio
the nominal output to any integer.
of the PD is Vdd/2
• Kd=Vdd/π

π
∆φ = ± → D = 50% → Vd = Vdd / 2
2

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PLL Blocks (3-LPF) PLL Blocks (4-VCO)
• Filters the PD output. • VCO: Voltage Controlled Oscillator.
• Weak filtering (Wide BW) leads to “Spurs”. • Kvco: VCO sensitivity.
• Small BW leads to longer settling time. • fo: Free-running frequency.
• Filter structure determines PLL type. ω (t ) = KVCO ⋅ VC
t
ϕ (t ) = ∫ ω (t ) ⋅ dt
0

KVCO
ϕ (s ) = ⋅ VC
s

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PLL Design Fractional PLL

• Given: • What if the required channel spacing is smaller than
– Output frequency fout the available reference frequency?
– Channel spacing. df – Solution (1): Fractional-N PLL (out of our lecture scope)
• Required: – Solution (2): Reference division:
– fref=?
– N=?
• Steps:
• fref = df

• N=fout / fref

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Design Example PLL Phase noise (1)
• Design a PLL for GSM (fout = 900MHz, df=200kHz) • PLL phase noise is mainly
• Available reference is 13MHz. due to main sources:
1. Reference (input)
Low phase noise (clean source).
• Solution: Noise gain (N).
Low-pass Filter.
– M=13MHz/200kHz = 65
– N= 900MHz/200kHz = 4500 2. VCO
Higher phase noise.
Unity noise gain.
High-pass Filter.

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Phase noise (2) Outline (4/6)

• Each noise source is shaped with the corresponding
transfer function
– Reference: Gain=N LPF. (Close-in noise)
– VCO: Gain=1 HPF (Far-out noise) (4) Type-I PLL.
• It is clear that (N) and (BW) determine PLL Phase Noise.

•Type-I Design Equations.

•Design Example.

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Type I PLL Type I PLL
• Type I means there is only “one” integrator, • Second order
which is the VCO itself. feedback system
• Very simple structure. • Open loop gain:
• Rarely used in communication systems. (Type-II is preferred) K
A(s ) =
s (1 + sRC )
• Natural frequency:
• Open-loop gain:
• Closed loop gain: K
K 1 A(s ) ωn =
A(s ) = K d ⋅ F (s ) ⋅ vco ⋅ B (s ) = N RC
s N 1 + A(s )

K ωn2 • Damping coefficient:

A(s ) = K ⋅K B (s ) = N 1
K = d vco s + 2ξωn s + ωn2
2 ξ=
s (1 + sRC ) N 2 K ⋅ RC

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Zeta effect ξ BW effect ωn = 2π ⋅ f n

• Low values 0.045
step response
• Higher BW 1.4
step response

0.3MHz
cause 0.04
0.1
0.5
means fast 1.2 1MHz
3MHz
overshoot 0.035 0.7 settling. 1
3
0.03 5 0.8

Amplitude
• High values 0.025
• Settling with 5%
Amplitude

0.6
0.02
cause slow error, 0.4
0.015
settling Approximately: 0.2
0.01
4.6 1 0
0.005
ts ≈ ≈ 0 1 2 3 4
-6
• Optimum is 0 ξ ⋅ ωn f n
Time (sec)
x 10
0 1 2 3 4 5 6 7
0.707 Time (sec)

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PLL Type-I Design (1) PLL Type-I Design (2)
• Given: Steps:

– Output frequency fout fref = df

– Channel spacing. df N=fout / fref
– Settling time. ts
fn = 1/ts
– XOR detector
ωn = 2π ⋅ f n ξ = 0.707

• Required: RC =
1 ωn
K=
– fref=? 2ξωn 2ξ
N ⋅K
– N=? K vco =
• XOR detector -> Kd=Vdd/π Kd
– Ko=?
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Exercise 1 Solution (1)

• Design a type-I PLL with the following
• fref = df = 1MHz
specifications:
– Output center frequency 60MHz. • N=fout / fref = 60MHz/1MHz = 60
– Channel spacing 1MHz.
– Settling time 20us • fn = 1/ts = 50kHz
ωn = 2π ⋅ f n = 310kr / s ξ = 0.707

1 ωn
RC = = 2.3µs K= = 220kr / s
2ξωn 2ξ

R = 1kΩ C = 2.3nF

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Solution (2) Matlab Verification (Linear Model)
phase step response
• Kd=Vdd/π = 0.38V/rad • Matlab can be 70

used to verify the 60

N ⋅K linear model. 50
K vco = = 35M (r / s ) / V 40
Kd

Amplitude
30

K vco 20
Ko = = 5.6 MHz / V
2π 10

0
0 1 2 3 4 5 6
Time (sec) -5
x 10

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Matlab Verification (Time Model) Outline (5/6)

• Simulink Model. Vc_sim

To Workspace

In1

(5) More PLL Types.

Out1 In1 Out1 In1 Out1
ref In2

Phase detector
LPF VCO+divider

0.7

• Control voltage 0.6

settling.
0.5 •Type-II PLL.
0.4

•Fractional-N PLL.
Vc (V)

0.3

• Ripples due to
0.2
•All-Digital PLL.
0.1

reference signal. 0
0 10 20 30 40 50 60 70 80 90 100
time (us)

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Type-I Limitations (1) Type-I Limitations (2)
• Open loop gain: • Solution:
K – Add extra pole at origin, i.e. additional integrator.
A(s ) = – This adds additional “s” to the equation:
s (1 + sRC )
θ e (s ) s =0 = 0
• Phase error :
E (s ) =
(
s2 ⋅ s + 1
RC
) (
s s+ 1
RC
)⋅ ∆ϕ
1 θ e (s ) =
E (s ) = • Error due to phase step: s 2 + 2ξωn s + ωn2 s 2 + 2ξω n s + ωn2 θ e (t ) t =∞ = 0
1 + A(s )
(s+ 1 ⋅ ∆ϕ )
E (s ) = 2 RC
(
s⋅ s+ 1 ) θ e (s ) = RC
s + 2ξω n s + ωn2
2 – Now, we have “2” poles at origin (Filter + VCO)
Type-II
s + 2ξωn s + ωn2
θ e (s ) s = 0 ≠ 0 θ e (t ) t =∞ ≠ 0
• Phase step:
∆ϕ
θ in (s ) = • Steady-state error.
s

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Type-II Filter Implementation (1) Type-II Filter Implementation (2)

• Integrator: Capacitor. • Adding extra RC section.
• But, with 2 poles at origin, the • Adds additional pole and zero.
root-locus lies on the imaginary • Z<P
system is conditionally
axis. Z (s ) =
1 stable.
s ⋅C k (s + Z )
• The PLL is unstable (marginally). • By proper design, the desired Z (s ) =
s ⋅ (s + P )
• Filter modification is needed. BW and damping coefficient
(zeta) can be obtained.

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Type-II PFD (1) Type-II PFD (2)
• Phase detection is usually done using PFD • Better phase and frequency detection range.
(Phase-Frequency Detector) “instead of XOR”

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Complete Type-II PLL Outline (6/6)

• PFD:
– Phase-Frequency
Detector.
• CP:
(6) Exercise.
– Charge Pump.
• Z(s): •Written part.
– Filter
• VCO: •Matlab part.
– Voltage-Controlled
Oscillator

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References
• “Introduction to Charge Pump PLL Frequency Synthesizers”,
Ayman Ahmed, Si-Ware Systems.

• National Application Note:

http://www.national.com/an/AN/AN-1001.pdf#page=1
Thank you
• Fujitsu Application Note:
http://www.siliconrfsystems.com/Papers/U11614%20PLL%20Basics-%20Fujitsu.pdf

Questions?

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