Lab # 01: Introduction to Basic Logic Gates & DLD Trainer

Objectives
To know about the basic logic gates, their truth tables, input output characteristics and analyzing
their functionality. Introduction to logic gate IC’s, Integrated Circuits pin configurations and their
use.
Equipment Required
DLD Trainer, logic IC’s
Lab Instructions

✓ This lab activity comprises of two parts: In Lab Exercises and Lab report.
✓ The students should perform and demonstrate each lab task for step-wise evaluation.
✓ Only those tasks that completed during the allocated lab time will be credited to the
students. Students are however encouraged to practice on their own in spare time for
enhancing their skills.
✓ The instructor will provide a brief description of the various sections, of the
oscilloscope and function generator.

Lab Report Instructions

All questions should be answered precisely to get maximum credit. Lab report must ensure
following items:
✓ Lab objectives
✓ Results (graphs) duly commented and discussed
✓ Conclusion
Background Theory:

The Digital Logic Circuits can be represented in the form of (1) Boolean Functions, (2) Truth
Tables, and (3) Logic Diagram. Digital Logic Circuits may be practically implemented by using
electronic gates. The following points are important to understand.

• Electronic gates are available in the form of Integrated Circuits (IC’s) and they require a power.
• Supply Gate inputs are driven by voltages having two nominal values, e.g. 0V and 5, 12V
representing logic 0 and logic 1 respectively.
• The output of a gate provides two nominal values of voltage only, e.g. 0V and 5, 12V
representing logic 0 and logic 1 respectively. In general, there is only one output to a logic gate
except in some special cases.
• Truth tables are used to help show the function of a logic gate in terms of input values
combination with desired output.
• Logic Diagram is used to represent the Digital Logic Circuit in the form of symbols connected
with each other.

Part 1. Familiarize yourself with AM 2001 logic trainer:

The first part of this lab experiment is an exercise to have a general introduction to the AM 2001 logic
trainer and gather information about the trainer, how the logic trainer works and how we can use this trainer
for hardware implementation of our experiments. AM 2001 logic trainer has different hardware components
that can be categorized as follows:

• Logic switches
• Breadboard
• State monitors/LEDs
• 7 Segment Display

Figure 1.1 AM 2001 logic trainer

Logic Switches:
There are 8 logic switches present on AM 2001 trainer starting from S2 to S9. When a switch is in upward
direction it is representing a logic 0 and when a switch is in downward direction it is representing a logic
1.

Breadboard:
A breadboard is also present on the trainer. The breadboard contains serial and parallel connected interfaces.
With the help of bread board, we can easily connect logic switches and other peripherals on the trainer.

State Monitors / LEDs:

There are 16 logic state monitors or LEDs present on the trainer. The state monitors are LEDs are used to
monitor results. When a logic state monitor or led is on it is representing a logic 1 and when a logic state
monitor or LED is off it is representing a logic 0.

7 Segment Display:
There 3 seven segment displays present on the AM 2001 trainer. The seven-segment display is are used to
monitor results in decimal format. The 7-segment display contains 9 input connections and 4 output
connections. When a BCD coded number is provided to these input lines the corresponding digital number
appears on the seven segment.

Lab Tasks-Part 2
Study and verify the truth table of the logic gates
A logic gate is a basic building block of a digital circuit that has two inputs and one output. The relationship
between the i/p and the o/p is based on a certain logic. These gates are implemented using electronic
switches like transistors, diodes. But, in practice basic logic gates are built using CMOS technology, FETS
and MOSFET(Metal Oxide Semiconductor FET)s. Logic gates are used in microprocessors,
microcontrollers, embedded system applications and in electronic and electrical project circuits. The basic
logic gates are categorized into seven: AND, OR, XOR, NAND, NOR, XNOR and NOT.

Procedure
1. Place the IC on the Bread board as shown in the figure 1.2

Figure 1. 2

2. Using the power supply available at digital Logic Lab, connect pin7 (Ground) and pin14 (Vcc) to power
up IC.
3. Give number of possible combinations of inputs using the slide switches SW0-SW3 and note down the
output with help of LED for all gate ICs.
 Lab Task 1:

IC 7408 AND gate Inputs Outputs

A B Desired Observed

0 0

0 1
Figure 1.3 1 0

1 1

Table 1.1

Lab Task 2: Inputs Outputs

IC 7404 NOT gate
A Desired Observed

Figure 1.4
Table 1.2

Lab Task 3: Inputs Outputs

IC 7402 NOR gate
A B Desired Observed

0 0

0 1

1 0
Figure 1.5 1 1

Table 1.3
Lab Task 4: Inputs Outputs
IC 7432 OR gate A B Desired Observed

0 0

0 1

1 0

Figure 1.6 1 1

Table 1.4

Inputs Outputs
Lab Task 5:
IC 7486 XOR gate A B Desired Observed

0 0

0 1

1 0

1 1
Figure 1.7
Table 1.5
 Integrated Circuits pin configurations
OR Gate IC (7432)

AND Gate IC (7408)

XOR Gate IC (7486)

NAND Gate IC (7400)

NOT Gate IC (7404)
Sample Viva Questions

1. Explain what are the universal logic gates?

2. Define 0 and 1 in items of voltage values.

3. Explain what is a truth table?

Critical Analysis / Conclusion

(By Student about Learning from the Lab)
 Lab # 02: Introduction to proteus

Objectives
Learn to use Proteus Software for Simulation of Digital Logic Circuits.

Lab Instructions

✓ This lab activity comprises of two parts: In Lab Exercises and Lab report.
✓ The students should perform and demonstrate each lab task for step-wise evaluation.
✓ Only those tasks that completed during the allocated lab time will be credited to the students.
Students are however encouraged to practice on their own in spare time for enhancing their skills.
✓ The instructor will provide a brief description of the various sections, of the
oscilloscope and function generator.

Lab Report Instructions

All questions should be answered precisely to get maximum credit. Lab report must ensure following
items:
✓ Lab objectives
✓ Results (graphs) duly commented and discussed
✓ Conclusion

Part 1 - Proteus (Simulation Software)

Proteus has many features to generate both analogue and digital results over a virtual environment.
However, this lab will focus on only tools that will be used in digital schematic designs and verification of
basic logic gates.

Procedure

Right click on the ISIS icon present on desktop and open it.

Figure 2.1 ISIS icon

After right click on the ISIS this window will be shown

Figure 2.2 Interface of Proteus software window

Parts Browsing:
Proteus has many models of electronic equipment such as logic gates, many kinds of switches and basic
electronic devices. The equipment can be founded by clicking on and then a new window will pop-up and
wait for the parts information as shown in figure 2.3

Finding Steps:
1. Type information of device such as “OR gate” in box 1.
2. If some specific category is known, the device can narrow on focusing by selecting catalogue in the
box 2.
3. After the information is entered, the list of related devices will appear in the box 3, so that needed
device can be chosen and then click “OK” button to confirm selection in figure 2.3.

Figure 2.3 Pick Devices window in Proteus

 Figure 2.4 Pick selected Devices window in Proteus

Power supply and input signal Generator

All of the electrical circuits require power supplies. The power supplies for logic circuits are represented in
digital system design on Proteus because the schematic may be too complicated to understand for simulation
section. Therefore, power supplies will be needed as input power for a system. Moreover, all of the input
generators, such as ac generator, dc and pulse are contained in this category and it will be shown when is
clicked. In addition, “Ground” will not be contained in this group. Because it is not an input signal it is just
a terminal junction. Therefore, it will be grouped in terminal category as shown in figure 2.5 & 2.6.

Figure 2.5 Power supplies window in Proteus Figure 2.6 Terminals window in Proteus
Logic State:

In addition, there is another input that usually be used in digital circuit designed circuit but it does not exist
in real world as an equipment it is called as “LOGIC STATE”. It can be found in the picking part section
(type logic state and pick it figure 2.7).

Figure 2.7 Logic State in Proteus

Placing Equipment:

Selecting all devices needed to be placed on the circuit window (Grey window) and wiring it. It can be done
by following these steps:
1. Click on and select the first device that will be placed.
2. Place mouse wherever the device is preferred to be place and then click the left button of the mouse.
The device will be placed, if it is needed to be moved, click the right button of the mouse on the device
symbol to select the mouse. Then hold this device with the left mouse button and move it to any desired
place. (figure 2.8)

Figure 2.8 Placing the devices in Proteus

To wire devices together, click at the source pin of device and then move mouse cursor to destination pin
of the device. In this step the pink line will be appeared and it will be wire of circuit after clicking the mouse
on the destination pin of the circuit (as shown in figure 2.9).

Figure 2.9 Wiring devices to make a circuit

After wiring all devices and connect all inputs according to the circuit, the simulation is ready to be run by
clicking on Play button to run and stop button to stop. Logic probe or LED can be used to observe output
state.

Lab Task 1:
Implementation of AND gate on Proteus

Inputs Outputs

A B Desired Observed

0 0 0

0 1 0

1 0 0
Figure 2.10
1 1 1

Table 2.1
Take the components from Library by pressing the tab “Library”

Figure 2.11 Pick parts from library

Search the Components by name and then click OK to adding them in Devices Panel

Figure 2.12 Pick parts from library

Connect the components and the design by specific name

Figure 2.13 Connection the components

Press the “start” button to execute the design and verify the results

Figure 2.14 Design of logic AND gate

Lab Task 2:
Implementation of OR gate on Proteus

Inputs Outputs

A B Desired Observed

0 0 0

0 1 1
Figure 2.15
1 0 1

1 1 1

Table 2.2

Figure 2.16 Design of logic OR gate

Lab Task 3:
Implementation of NOT gate on Proteus

Inputs Outputs

A Desired Observed
Figure 2.17 0 1

1 0

Table 2.3

Figure 2.18 Design of logic NOT gate

Lab Task 4:
Implementation of NAND gate on Proteus

Inputs Outputs

A B Desired Observed

0 0 1

Figure 2.19
0 1 1

1 0 1

1 1 0

Table 2.4
 Figure 2.20 Design of logic NAND gate

Lab Task 5:
Implementation of XOR gate on Proteus

Inputs Outputs

A B Desired Observed

0 0 0

0 1 1
Figure 2.21
1 0 1

1 1 0

Table 2.5

Figure 2.22 Design of logic XOR gate

Lab Task 6:

Draw the schematic for following logic circuit in Proteus and fill in the table. Answer the questions at the
end.

A B C D F1 F2
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Table 2.6

Lab Task 7:

Construct XOR and XNOR circuits using AND, NOT and OR gates.
Sample Viva Questions
1. Write Boolean Logic equation for function F1 in terms of the inputs A, B, C, D.

2. Write Boolean Logic equation for function F2 in terms of the inputs A, B, C, D.

3. Verify the functionality of F1 and F2 on Proteus by comparing F1 and F2 in truth Table

with the outputs in the Proteus.

Analysis / Conclusion

( By Student about Learning from the Lab)

Lab # 3: Verification of basic theorems and universal gates
implementation on digital trainer using gate integrated circuits

Objectives

• To simulate and implementation of any logic function by using universals gates (NAND/NOR).
• To build the understanding of how to construct any combinational logic function using NAND or NOR
gates only.
• To verify theorems of Boolean algebra through logic gates

Equipment Required

• Logic gates (IC) trainer kit.

• Connecting patch chords.
• IC 7400 and IC 7402.

Lab Instructions

• This lab activity comprises of two parts: In Lab Exercises and Lab report.
• The students should perform and demonstrate each lab task for step-wise evaluation.
• Only those tasks that completed during the allocated lab time will be credited to the students. Students
are however encouraged to practice on their own in spare time for enhancing their skills.
• The instructor will provide a brief description of the various sections, of the
oscilloscope and function generator.

Lab Report Instructions

All questions should be answered precisely to get maximum credit. Lab report must ensure following
items:
✓ Lab objectives
✓ Results (graphs) duly commented and discussed
✓ Conclusion

Background theory
Digital circuits are more frequently constructed with universal gates. NAND and NOR gate are called
universal gates. Any Boolean logic function can be implemented using NAND only or NOR only gates.
NAND and NOR gates are easier to fabricate with electronic components than basic gates. Because of the
prominence of universal gates in the design of digital circuits, rules and procedures have been developed
for conversion from Boolean function given in terms of AND, OR, and NOT into its equivalent NAND
and NOR logic diagram.
In-Lab:

• This lab has three parts. In first part, implementation of any logic expression by using only NAND is
done. In second part, the same procedure is done by using NOR gate only. In third part, verify theorems
of Boolean algebra is done by logic gates.

Lab Tasks-Part-1

Lab Task 1: Implementing any logic expression by using only NAND gates

If we can show that the logical operations AND, OR, and NOT can be implemented with NAND gates,
then it can be safely assumed that any Boolean function can be implemented with NAND gates.

Procedure:

• Implementation AND, OR and NOT gates by using only NAND gates. Verify their truth tables.
• Insert the IC on the trainer’s breadboard.
• Use any one or more of the NAND gates of the IC for this experiment.
• Any one or more Logic Switches of the trainer (S1 to S9) can be used for input to the NAND gate.
• For output indication, connect the output pin of the circuit to any one of the LEDs of the trainer (L0
to L15).

Lab Task 1: Verification of NOT function

• Connect the circuit as per Figure 3.1.

• Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
• By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to that of an AND
gate. Record your observation in the table3.1 below.

A F=A’

Figure 3.1 NOT gate

Input Output
A F
0
1
Table 3.1
Lab Task 2: Verification of AND function

• Connect the circuit as per Figure 3.2.

• Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
• By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to that of an AND
gate. Record your observation in the table 3.2 below.

A (AB)’ F=AB
B

Figure 3.2 AND gate

Inputs Output

A B F

0 0

0 1

1 0

1 1

Table 3.2

Lab Task 3: Verification of OR function

• Connect the circuit as per Figure 3.3.

• Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
• By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to that of an AND
gate. Record your observation in the table 3.3 below.

A A’

F=A+B

B
B’

Figure 3.3 OR gate

 Inputs Output

A B F

0 0

0 1

1 0

1 1

Table 3.3

Lab Task 4: Verification of XOR function

• Connect the circuit as per Figure 3.4.

• Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
• By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to that of an AND
gate. Record your observation in the table 3.4 below

A (A(AB)’)’

F=A’B+AB’
(AB)’

B (B(AB)’)’

Figure 3.4 XOR gate

Inputs Output
A B F
0 0
0 1
1 0
1 1
Table 3.4
Lab Task 5: Verification of XNOR function

• Connect the circuit as per Figure 3.5.

• Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
• By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to that of an AND
gate. Record your observation in the table 3.5 below.

A (A(AB)’)’

F=AB+A’B’
(AB)’

B (B(AB)’)’

Figure 3.5 XNOR gate

Inputs Output

A B F
0 0

0 1

1 0

1 1
Table 3.5

Part 2 - Implementing any logic expression by using only NOR gates

If we can show that the logical operations AND, OR, and NOT can be implemented with NOR gates, then
it can be safely assumed that any Boolean function can be implemented with NOR gates.
Procedure

• Simulate AND, OR and NOT gates in proteus software, by using only NOR gates. Verify their truth
tables.
• Insert the IC on the trainer’s breadboard.
• Use any one or more of the NOR gates of the IC for this experiment.
• Any one or more Logic Switches of the trainer (S1 to S9) can be used for input to the NOR gate.
• For output indication, connect the output pin of the circuit to any one of the LEDs of the trainer (L0 to
L15).
Lab Tasks-Part-2

Lab Task 6: Verification of NOT function

• Connect the circuit as per Figure 3.6.

• Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
• By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to that of an AND
gate. Record your observation in the table 3.6 below.

Figure 3.6 NOT gate

Input Output

A F

Table 3.6

Lab Task 7: Verification of AND function

• Connect the circuit as per Figure 3.7

• Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
• By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to that of an AND
gate. Record your observation in the table 3.7 below.

Figure 3.7 AND gate

 Inputs Output

A B F

0 0

0 1

1 0

1 1

Table 3.7

Lab Task 8: Verification of OR function

• Connect the circuit as per Figure 3.8.

• Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
• By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to that of an AND
gate. Record your observation in the table 3.8 below.

Figure 3.8 OR gate

Inputs Output

A B F

0 0

0 1

1 0

1 1

Table 3.8
Lab Task 8: Verification of absorption theorem

Verify absorption theorem 𝑨 + (𝑨. 𝑩) = 𝑨

Draw circuit diagram

Truth table:

Inputs Outputs

A B Observed

0 0

0 1

1 0

1 1

Table 3.9
Lab Task 9: Verification of absorption theorem

Verify absorption theorem 𝑨. (𝑨 + 𝑩) = 𝑨

Draw circuit diagram

Truth table:

Inputs Outputs

A B Observed

0 0

0 1

1 0

1 1

Table 3.10
Lab Task 10: Verify De Morgan’s law. Show truth table and circuit diagram

1. 𝑿.𝒀 = 𝑿 + 𝒀

Draw circuit diagram

𝑿.𝒀

Draw circuit diagram

𝑿+𝒀

Truth table:

Inputs Outputs
Inputs Outputs
X Y Observed
X Y Observed
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
 𝟐. 𝑿+𝒀 = 𝑿. 𝒀

Draw circuit diagram

𝑿+𝒀

Draw circuit diagram

𝑿. 𝒀

Truth table:

Inputs Outputs
Inputs Outputs
X Y Observed
X Y Observed
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Sample Viva Questions

1. Write two characteristics of combinational circuits.

2. Explain what is the specialty of NAND and NOR gates?

Analysis / Conclusion

( By Student about Learning from the Lab)