EENG211/INFE211 Digital Logic Design

Experiment 5

Decoders/Demultiplexers and Multiplexers

# Student No Name Surname Sign

1
2
3

Objective:
1. Test the operation of 74x138 decoder. And using it as demultiplexer.
2. Implement the Boolean functions using 74x138 decode.
3. Testing the operation and implementing the Boolean function using 74151 multiplexer.

USED ICs: 74LS138, 74151, 7410, 7404

DATA INPUTS DATA SELECT

VCC 4 5 6 7 A B C

16 15 14 13 12 11 10 9

D4 D5 D6 D7 A B

D3 74151 C

D2 D1 D0 Y W S

1 2 3 4 5 6 7 8
GND
3 2 1 0 Y W STROBE

DATA INPUTS OUTPUTS

74138 3-line to 8-line decoder/demultiplexer 74151 8-line to 1-line data multiplexer

7410 3-input NAND 7404 Hex Inverter

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EENG211/INFE211 Digital Logic Design
Decoder Implementation
1) The following figure shows the pin numbers of 74138 decoder. The enable inputs are
connected to the logic switches, and the select inputs C, B, & A are connected to the
switches SW1 through SW3. The outputs are Y0 - Y7.

NOTE: The output is active low.

Table 1
Select
Enable Input Output
Input
G2A G2B G1 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
1 0 0 X X X 1 1 1 1 1 1 1 1
0 1 0 X X X 1 1 1 1 1 1 1 1
0 0 1 X X X 1 1 1 1 1 1 1 1
0 0 1 0 0 0 0 1 1 1 1 1 1 1
0 0 1 0 0 1 1 0 1 1 1 1 1 1
0 0 1 0 1 0 1 1 0 1 1 1 1 1
0 0 1 0 1 1 1 1 1 0 1 1 1 1
0 0 1 1 0 0 1 1 1 1 0 1 1 1
0 0 1 1 0 1 1 1 1 1 1 0 1 1
0 0 1 1 1 0 1 1 1 1 1 1 0 1
0 0 1 1 1 1 1 1 1 1 1 1 1 0

Q1) What is your observation & analysis on table 1?

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2) A combinational circuit has three inputs A, B and C, and three outputs F1, F2, and F3.
The simplified Boolean functions for the circuit are as follows:
F1 = AC + A'B'C'
F2 = A'B + AB'C'
F3 = AB + A'B'C
2.1) Connect and check the following circuit which implementing F1 and F2, using 74138
decoder and NAND gate. Record your data in table 2.

F1 = AC(B +B') + A'B'C'

= ABC + AB'C + A'B'C'
= M7 + M5 + M0

F2 = A'B (C + C') + AB'C'

= A'BC + A'BC' + AB'C'
= M3 + M2 + M4

NOTE: The output is active low; inverters are connected to the output before using or gate.
Invert OR = NAND.

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EENG211/INFE211 Digital Logic Design

Table 2
Enable Input Select Input Output

G2A G2B G1 C B A F1 F2
0 0 1 0 0 0
0 0 1 0 0 1
0 0 1 0 1 0
0 0 1 0 1 1
0 0 1 1 0 0
0 0 1 1 0 1
0 0 1 1 1 0
0 0 1 1 1 1

2.2) Implement and show the simplified 2.3) Construct a 4 x 16 line decoder using
Boolean functions: two 3 x 8 line decoders with enable.
F3 = AB + A'B'C

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EENG211/INFE211 Digital Logic Design
Multiplexers:
1) The following figure shows the block diagram of the 74151 MUX. Verify truth table 3 of
the MUX. Apply the inputs A B, & C with data switches SW3 – SW1.
Table 3
Strobe Select Output
S A B C Y
1 X X X 0
0 0 0 0 D0
0 0 0 1 D1
0 0 1 0 D2
0 0 1 1 D3
0 1 0 0 D4
0 1 0 1 D5
0 1 1 0 D6
0 1 1 1 D7

Q2) Explain how the multiplexer can be used as a parallel to serial converter?
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2) Implement the following Boolean function with an 8x1 multiplexer:
F(A,B,C,D) = Σ(0,3,5,6,8,9,14,15). Apply the inputs A, B, C, & D with data switches
SW4 – SW1 as indicated in table 4.

A B C D Output
0 0 0 0 0 1
1 0 0 0 1 A
7 S
2 0 0 1 0 0 0
1 4 D0
3 0 0 1 1 A' 3
4 0 1 0 0 0 D1
2
5 0 1 0 1 A' 0 D2 MUX
1 5
6 0 1 1 0 1 A D3 74151
15 D4 Y
7 0 1 1 1 A
14
8 1 0 0 0 1 D5
13
D6
9 1 0 0 1 A
12
10 1 0 1 0 0 D7

11 1 0 1 1 A' 11 10 9
12 1 1 0 0 0
13 1 1 0 1 A' B C D
14 1 1 1 0 1
15 1 1 1 1 A

Spring 2009-2010, EENG 115(EENG 211)/INFE 115(INFE 211) Digital Logic Design I, Lab Report.

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