Chapter1 2018

1.
Introduction to VLSI
1.1. Digital systems and VLSI
1.2. Gate Arrays
1.3. Standard Cells
1.4. Functional Blocks
1.5. CMOS Logic
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Digital systems and VLSI
 Digitalsystem is a system that operates on strings of
zeros and ones.
 transistors become smaller,
 they also become faster,
 dissipate less power, and
 are cheaper to manufacture.
 Transistors
can be viewed as electrically controlled
switches with a control terminal and two other
terminals that are connected or disconnected
depending on the voltage or current applied to the
control.
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Digital systems and VLSI cont.…
 The quiescent power dissipated by these base
currents, drawn even when the circuit is not
switching, limits the maximum number of
transistors that can be integrated onto a single die.
 By the 1960s, Metal Oxide Semiconductor Field
Effect Transistors (MOSFETs) began to enter
production.
 MOSFETs offer the compelling advantage that they
draw almost zero control current while idle.
 They come in two flavours:
 nMOS using n-type and
 pMOS, using p-type silicon
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 Moore’s Law:-
 “The number of transistors incorporated in a chip will
approximately double every 24 months.”
--Gordon Moore, Intel co-founder
 Moore's law is the observation that the number of transistors in
a dense integrated circuit doubles approximately every two
years.
 Advancements in digital electronics are strongly linked to
Moore's law: quality-adjusted microprocessor prices, memory
capacity, sensors and even the number and size of pixels in
digital cameras.
 Moore's law describes a driving force of technological and social
change, productivity, and economic growth.
 The period is often quoted as 18 months because of Intel
executive David House, who predicted that chip performance
would double every 18 months (being a combination of the effect
of more transistors and the transistors being faster).
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 Moore’s Law is driven primarily by scaling down the
size of transistors and, to a minor extent, by
building larger chips.
 The level of integration of chips has been classified
as:-
a) small-scale integration(SSI),
b) medium-scale integration(MSI),
c) large-scale integration(LSI), and
d) very large-scale integration(VLSI).
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 The monolithic integration of a large number of
functions on a single chip provides:
 Less area/volume and therefore, compactness
 Less power consumption
 Less testing requirements at system level
 Higher reliability, mainly due to improved on-
chip interconnects
 Higher speed, due to significantly reduced
interconnection length
 Significant cost savings
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 Small-scale integration(SSI) circuits, such as the 7404
inverter, have fewer than 10 gates, with roughly
half a dozen transistors per gate.
 Medium-scale integration(MSI) circuits, such as the
74161 counter, have up to 1000 gates.
 Large-scale integration(LSI) circuits, such as simple
8-bit microprocessors, have up to 10,000 gates.
 Moreover, as transistors have become so small, they cease
to turn completely OFF. Small amounts of current leaking
through each transistor now lead to significant power
consumption when multiplied by millions or billions of
transistors on a chip.
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 Based on the fundamental operating principles, the
circuits are classified into two main categories, i.e.,
1. static circuits and
2. dynamic circuits.
 The static CMOS circuits are further divided into sub-
categories such as
A. classical (fully complementary) CMOS circuits,
B. transmission-gate logic circuits,
C. Pass-transistor logic circuits and
D. cascade voltage switch logic (CVSL) circuits.
 The dynamic CMOS circuits are divided into sub-
categories such as
A. domino logic,
B. NORA, and
C. true single-phase clock (TSPC) circuits.
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 Dynamic logic is temporary (transient) in that output levels will
remain valid only for a certain period of time
 Static logic retains its output level as long as power is applied
 Dynamic logic is normally done with charging and selectively
discharging capacitance (i.e. capacitive circuit nodes)
 Precharge clock to charge the capacitance
 Evaluate clock to discharge the capacitance depending on condition of logic
inputs
 Advantages over static logic:
 Avoids duplicating logic twice as both N-tree and P-tree, as in standard
CMOS
 Typically can be used in very high performance applications
 Very simple sequential memory circuits; amenable to synchronous logic
 High density achievable
 Consumes less power (in some cases)
 Disadvantages compared to static logic:
 Problems with clock synchronization and timing
 Design is more difficult
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 In Static logic circuits, each output of the gate is
connected to either the high voltage power (VDD) bar or to
the lower voltage power(GND) at a certain point in time.
 Dynamic logic style incorporates the clock input in all the
gates.
 The operation of dynamic logic gates is divided in to two
phases i.e.
1. Pre-charge phase:-
 In this phase, the gate outputs are charged to the high level voltage
b/c the PMOS transistors are controlled by clock input which in this
phase is low.
2. Evaluate phase:
 In this phase, the outputs of the gate can conditionally changes to
low voltage level.
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Gate Arrays
A gate array circuit is a prefabricated silicon chip
circuit with no particular function, in which
transistors, standard NAND or NOR logic gates, and
other active devices are placed at regular
predefined positions and manufactured on a wafer,
usually called a master slice.
 A gate array or uncommitted logic array (ULA) is an
approach to the design and manufacture of
application-specific integrated circuits (ASICs), using
a prefabricated chip with active devices like NAND-
gates, that are later interconnected according to a
custom order by adding metal layers in the factory
environment.
 This layer is analogous to the copper layer(s) of a
printed circuit board (PCB).
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Gate Arrays
 In view of the fast prototyping capability, the gate
array (GA) comes after the FPGA
 Whilethe design implementation of the FPGA chip is
done with user programming, that of the gate array is
done with metal mask design and processing.
 Gate array implementation requires a two-step
manufacturing process: The first phase, which is
based on generic (standard) masks, results in an array
of uncommitted transistors on each GA chip.
 These uncommitted chips can be stored for later
customization, which is completed by defining the
metal interconnects between the transistors of the
array
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Gate Arrays cont.…
 Use a sea of basic transistors (pmos/nmos) or gates
(NAND/NOR)
• Can have cells which can provide a universal logic function
• Just need to add signal routing – only a few masks
Advantages:
• Reduced design time
• Less chance of errors
• Reduced production costs
• Decrease time to product
Disadvantages:
 Very Limited flexibility
 Need moderately high volume product
 Less easily protected IPR
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Standard Cells
 standard cell methodology is a method of designing
application specific integrated circuits (ASICs) with
mostly digital logic features.
 Standard cell methodology is an example of design
abstraction, whereby a low level very large-scale
integration (VLSI) layout is encapsulated into an abstract
logic representation (such as a NAND gate).
 Cell based methodology —the general class to which
standard cells belong —makes it possible for one
designer to focus on the high level (logical function)
aspect of digital design, while another designer focuses
on the implementation (physical) aspect.
 Along with semiconductor manufacturing advances,
standard cell methodology has helped designers scale
ASICs from comparatively simple single function ICs (of
several thousand gates), to complex multimillion gate
system on a chip (SoC) devices.
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Standard Cells cont…
 Design Using Standard Cell, pre-design by
professionals.
 Cells includes Verilog, Circuit, Layout Information
for NAND, NOR, D-FF
 Logic Design and Layout Design done by CAD.
 Logic Design --- by use of Cells with specified delays
 Layout Design – by use of Cells
 Generated Data is mainly interconnection wires.
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• A standard cell library must contain at least the
following cells to be able to implement any
function:
- NAND
- NOR
- NOT
- DFF
• Additionally, you can expand the standard cell
library to include additional cells like Tie-high,
Tie-low cells, I/O Pads, and multiple-input gates
(e.g. a 4-input NOR gate).
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 Advantages of standard cell libraries
 Designers save time and money by reducing the
product development cycle time.
 Reduce risk by using predesigned, pretested and
precharacterised standard cell libraries.
 Optimisation is possible.
 Disadvantages of standard cell libraries

 Time and expenses of designing or buying the
standard cell library.
 Time needed to fabricate all layers of ASIC for each
new design
 when the standard cell library must be ported to a
new fabrication process, the physical layout of all
the cells need to be changed.
 There are no naming conventions
 There are no standards for cell behavior
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 Note:-
 Both cell-based and gate-array ASICs use
predefined cells, but there is a difference—we
can change the transistor sizes in a standard cell
to optimize speed and performance, but the
device sizes in a gate array are fixed.
 This results in a trade-off in performance and
area in a gate array at the silicon level.
 The trade-off between area and performance is
made at the library level for a standard-cell
ASIC.
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List of Standard Cells
.  Inverter  Decoder 2 to 4
 Inverting Buffer  Half Adder 1bit
 Non-inverting Buffer  Full Adder 1bit
 Tri-state Non-inverting Buffer  Pos Edge DFF
 AND 2, 3, 4 inputs  Neg Edge DFF
 NAND 2,3,4 inputs  Scan Pos Edge DFF
 OR 2, 3, 4 inputs  Scan Neg Edge DFF
 NOR 2,3,4 inputs  RS NAND Latch
 XNOR 2,3 inputs  High-Active
 AND-OR  Clock Gating Latch
 AND-OR-Inverter  Non-inverting Delay line
 OR-AND  Pass Gate
 OR-AND-Inverter  Bidirectional Switch
 Multiplexer 2 to 1  Hold 0/1 Isolation Cell
 Multiplexer 4 to 1
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Classification of standard cell libraries
 Classical Libraries:
--- Theses are the most common logic elements
like gates, flip-flops, multiplexers, PAL,
memories etc.
 IP (Intellectual Property) offerings:
--- These include products like gate arrays and
CPLDs which are IP offerings by many companies.
Each one providing its own features and facilities
in the product.
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Fragment of an ASIC Library
Class Element
Combinational NAND, NOT, NOR, XOR
functions
Storage functions D flip-flop,Latch, J-K
flip-flop, shift register,
RAM, ROM
Information switches Selector, Multiplexer
Data Operator Adder, counter, ALU,
Decoder
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Standard cell Library cont….
 A typical standard cell library contains two main components:
1. Library Database :- Consists of a number of views often including
layout, schematic, symbol, abstract, and other logical or
simulation views.
 From this, various information may be captured in a number of formats
including the Cadence LEF format, and the Synopsys Milkyway format,
which contain reduced information about the cell layouts, sufficient for
automated "Place and Route" tools.
2. Timing Abstract Generally in Liberty format, to provide
functional definitions, timing, power, and noise information for
each cell.
 A standard cell library may also contain the following additional
components:
 A full layout of the cells
 Spice models of the cells
 Verilog models or VHDLVITAL models
 Parasitic Extraction models
 DRC rule decks
 An example is a simple XOR logic gate, which can be formed from
OR, INVERT and AND gates.
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MOSIS compatible design tools and cell libraries
 MOSIS compatible cell libraries are provided by

many organisations, commercial and non-
commercial both
 Commercial organisations are: Mentor Graphics,
Cadence, Artisan, Avant, Barcelona Design,
Tanner Research, LEDA systems etc.
 Non Commercial Organisations are:MSU’s SCMOS
Library, LASI, Ballistic, Magic etc.
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Standard Cells Provided by Mentor Graphics
 There are over 200 standard cells available for the
2.0 um, 1.2 um, and 0.8 um technology.
-- 2, 3, and 4-input AND, NAND, OR, NOR, AO
-- 2-input XOR and XNOR gates
-- 2-1 MUX gate
-- multiple drive strength buffers, inverters and tri-
state buffers
-- four D-type flip-flops: dff, dffs, dffr, and dffsr
-- four D-type latches: latch, latchs, latchr, latchsr
 All of these cells have quickpart models with timing
for full, backannotated simulation after layout
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New Trends in Standard Cell Libraries
 In a bid to improve the performance of standard-cell designs, vendors of
place-and-route and synthesis tools and cell libraries are teaming up to
develop a technique that is likely to lead to the death of the standard cell
itself.
 Prolific Inc. (Newark, Calif.) has launched a tool called Liquid Libraries that
will create tuned cells on the fly and insert them into the libraries used by
place and route tools
 Hot on the heels of Prolific's launch, Cadabra Design Automation (Santa
Clara, Calif.) is working on a new flow that would ultimately move library
generation as far forward as the synthesis phase, giving logic designers the
ability to tune parts of a design for low power consumption or speed
 Prolific is working with Cadence Design Systems, Magma Design Automation,
Monterey Design Systems and Sapphire Design Automation..
 Cadabra is working with Avanti, Cadence, Synopsis and Magma.
 The first fruit of the Cadabra project will be the power and performance
optimization (PPO) flow.
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Construction of a standard cell
A standard cell is a group of transistor and
interconnect structures that provides a boolean
logic function (e.g., AND, OR, XOR, XNOR, inverters)
or a storage function (flipflop or latch).
 The simplest cells are direct representations of the
elemental NAND, NOR, and XOR Boolean function,
although cells of much greater complexity are
commonly used (such as a 2 bit full adder, or muxed
D input flip-flop.)
 The cell's Boolean logic function is called its logical
view: functional behaviour is captured in the form
of a truth table or Boolean algebra equation (for
combinational logic), or a state transition table (for
sequential logic).
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Construction of a standard cell cont…
 Usually, the initial design of a standard cell is developed at
the transistor level, in the form of a transistor netlist or
schematic view.
 The netlist is a nodal description of transistors, of their
connections to each other, and of their terminals (ports) to
the external environment.
 A schematic view may be generated with a number of
different Computer Aided Design (CAD) or Electronic Design
Automation(EDA) programs that provide a Graphical User
Interface (GUI) for this netlist generation process.
 Designers use additional CAD programs such as SPICE or
Spectre to simulate the electronic behaviour of the netlist,
by declaring input stimulus (voltage or current waveforms)
and then calculating the circuit's time domain (analogue)
response.
 The simulations verify whether the netlist implements the
desired function and predict other pertinent parameters,
such as power consumption or signal propagation delay.
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Construction of a standard cell cont.…
 Since the logical and netlist views are only useful for abstract (algebraic)
simulation, and not device fabrication, the physical representation of the
standard cell must be designed too.
 Also called the layout view, this is the lowest level of design abstraction in
common design practice.
 From a manufacturing perspective, the standard cell's VLSI layout is the
most important view, as it is closest to an actual "manufacturing blueprint"
of the standard cell.
 The layout is organized into base layers, which correspond to the different
structures of the transistor devices, and interconnect wiring layers and via
layers, which join together the terminals of the transistor formations.
 The interconnect wiring layers are usually numbered and have specific via
layers representing specific connections between each sequential layer.
 Nonmanufacturing layers may be also be present in a layout for purposes of
Design Automation, but many layers used explicitly for Place and route
(PNR) CAD programs are often included in a separate but similar abstract
view.
 The abstract view often contains much less information than the layout
and may be recognizable as a Layout Extraction Format (LEF) file or an
equivalent.
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 After a layout is created, additional CAD tools are often
used to perform a number of common validations.
 A Design Rule Check (DRC) is done to verify that the
design meets foundry and other layout requirements.
 A Parasitic EXtraction (PEX) then is performed to
generate a PEX netlist with parasitic properties from the
layout.
 The nodal connections of that netlist are then compared
to those of the schematic netlist with a Layout Vs
Schematic (LVsS) procedure to verify that the
connectivity models are equivalent.
 The PEX netlist may then be simulated again (since it
contains parasitic properties) to achieve more accurate
timing, power, and noise models.
 These models are often characterized (contained) in a
Synopsys Liberty format, but other Verilog formats may
be used as well.
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 Finally, powerful Place and Route (PNR) tools may be used to pull
everything together and synthesize (generate) Very Large Scale
Integration (VLSI) layouts, in an automated fashion, from higher
level design netlists and floorplans.
 Additionally, a number of other CAD tools may be used to validate
other aspects of the cell views and models. And other files may be
created to support various tools that utilize the standard cells for a
plethora of other reasons. All of these files that are created to
support the use of all of the standard cell variations are collectively
known as a standard cell library.
 For a typical Boolean function, there are many different
functionally equivalent transistor netlists.
 Likewise, for a typical netlist, there are many different layouts that
fit the netlist's performance parameters. The designer's challenge
is to minimize the manufacturing cost of the standard cell's
layout(generally by minimizing the circuit's die area), while still
meeting the cell's speed and power performance requirements.
Consequently, integrated circuit layout is a highly labor intensive
job, despite the existence of design tools to aid this process.
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Application of standard cell
 enhances the efficiency of automated synthesis,
place, and route (SPR) tools.
 Indirectly, it also gives the designer greater freedom
to perform implementation trade-offs (area vs. speed
vs. power consumption).
 A complete group of standard cell descriptions is
commonly called a technology library.
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ASIC design Flow
1. Synthesis:-
 Using the technology library's cell logical view, the Logic Synthesis
tool performs the process of mathematically transforming the ASIC's
register transfer level (RTL) description into a technology
dependent netlist. This process is analogous to a software compiler
converting a high-level C program listing into a processor
dependent assembly language listing.
 The netlist is the standard cell representation of the ASIC design, at
the logical view level. It consists of instances of the standard cell
library gates, and port connectivity between gates. Proper
synthesis techniques ensure mathematical equivalency between
the synthesized netlist and original RTL description. The netlist
contains no unmapped RTL statements and declarations.
 The high level synthesis tool performs the process of transforming
the C level models (SystemC, ANSI C/C++) description into a
technology dependent netlist.
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2. Placement
 The placement tool starts the physical implementation of the
ASIC.
 With a 2D floor plan provided by the ASIC designer, the
placer tool assigns locations for each gate in the netlist.
 The resulting placed gates netlist contains the physical
location of each of the netlist's standard cells, but retains an
abstract description of how the gates' terminals are wired to
each other.
 Typically the standard cells have a constant size in at least
one dimension that allows them to be lined up in rows on the
integrated circuit. The chip will consist of a huge number of
rows (with power and ground running next to each row) with
each row filled with the various cells making up the actual
design.
 Placers obey certain rules:
 Each gate is assigned a unique (exclusive) location on the die
map.
 A given gate is placed once, and may not occupy or overlap the
location of any other gate.
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3. Routing
 Using the placed gates netlist and the layout view
of the library, the router adds both signal connect
lines and power supply lines.
 The fully routed physical netlist contains the listing
of gates from synthesis, the placement of each gate
from placement, and the drawn interconnects from
routing.
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4. DRC/LVS
 Design Rule Check (DRC) and Layout Versus Schematic (LVS) are verification
processes. Reliable device fabrication at modern deep sub-micrometer (0.13
µm and below) requires strict observance of transistor spacing, metal layer
thickness, and power density rules.
 DRC exhaustively compares the physical netlist against a set of "foundry
design rules" (from the foundry operator), then flags any observed violations.
 The LVS process confirms that the layout has the same structure as the
associated schematic; this is typically the final step in the layout process.
 The LVS tool takes as an input a schematic diagram and the extracted view
from a layout. It then generates a netlist from each one and compares them.
 Nodes, ports, and device sizing are all compared. If they are the same, LVS
passes and the designer can continue. LVS tends to consider transistor fingers
to be the same as an extra wide transistor. Thus, 4 transistors (each 1 μm
wide) in parallel, a 4finger 1 μm transistor, or a 4 μm transistor are viewed
the same by the LVS tool.
 Functionality of .lib files will be taken from SPICE models and added as an
attribute to the .lib file.
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ASIC design Flow summary
 A design flow is a sequence of steps to design an ASIC
1. Design entry. Using a hardware description language (HDL) or
schematic entry.
2. Logic synthesis . Produces a netlist—logic cells and their connections.
3. System partitioning. Divide a large system into ASIC-sized pieces.
4. Prelayout simulation. Check to see if the design functions correctly.
5. Floorplanning. Arrange the blocks of the netlist on the chip.
6. Placement . Decide the locations of cells in a block.
7. Routing . Make the connections between cells and blocks.
8. Extraction. Determine the resistance and capacitance of the
interconnect.
9. Postlayout simulation. Check to see the design still works with the
added loads of the interconnect.
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ASIC design Flow summary cont… Figure B
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 The physical size of a silicon die varies from a few millimetres on a
side to over 1 inch on a side, but instead we often measure the size
of an IC by the number of logic gates or the number of transistors that
the IC contains.
 As a unit of measure a gate equivalent corresponds to a two-input
NAND gate (a circuit that performs the logic function, F = 𝑨. 𝑩).
 A gate equivalent is a NAND gate 𝑭 = 𝑨. 𝑩 (IBM uses a NOR gate) or
four transistors.
 Often we just use the term gates instead of gate equivalents when
we are measuring chip size—not to be confused with the gate terminal
of a transistor. For example, a 100k-gate IC contains the equivalent of
100,000 two- input NAND gates.
 For digital standard cell designs, for instance in CMOS, a common
technology independent metric for complexity measure is gate
equivalents (GE).
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 There are four CMOS transistors in a two-input NAND gate (and a two-
input NOR gate too), so to convert between gates and transistors, you
multiply the number of gates by 4 to obtain the number of transistors.
 We can also measure an IC by the smallest feature size (roughly half
the length of the smallest transistor) imprinted on the IC.
 Transistor dimensions are measured in microns (a micron, 1𝞵m, is a
millionth of a meter).
 Thus we talk about a 0.5𝞵m IC or say an IC is built in (or with) a 0.5𝞵
m process, meaning that the smallest transistors are 0.5𝞵m in length.
 We give a special label, 𝝺 or lambda, to this smallest feature size.
Since lambda is equal to half of the smallest transistor length, X≈ 0.25
𝞵m in a 0.5 𝞵m process.
 Many of the drawings in this course use a scale marked with lambda
for the same reason we place a scale on a map.
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Functional Blocks
 Functional blocks are components of a certain integrated circuit(IC)
that used for performing specific function and those specific
functions are combined to make the hole function of the IC.
 For example a CPU have different functional blocks like ALU which
intended to make arithmetic and logic functions.
 Functional Blocks of CPU.
 ALU (Arithmetic & Logical Unit)
 Timing & Control unit
 Registers
 DMA unit, etc
 Functional units of computer.
 Input unit, memory unit, CPU, output unit.
 Functional blocks of a certain IC circuit may include:-
 Encoders
 Decoders
 Half-adders
 Full-adders
 Multiplexers
 De-multiplexers etc.
 Functional blocks can also be constructed From smaller functional blocks.
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CMOS Logic
 CMOS stands for Complementary Metal Oxide Semiconductor
 Complementary: there are N-type and P-type transistors. N-type transistors
use electrons as the current carriers. P-type transistors use holes as the
current carriers.
 Electrons are free carriers in the conduction band with energy of Ec or just
above the conduction band edge.

 Free electrons are generated by doping the silicon with an N-type impurity
such as phosphorous or arsenic.
 A hole is a current carrier due to the absence of an electron in a covalent
bond state, i.e. a missing electron which would otherwise be part of a
silicon-to-silicon bond. Holes are free carriers in the valence band with
energy of Ev or just below the valence band edge. Holes are generated by
doping the silicon with a P-type impurity such as boron.
 Metal: the gate of the transistor was made of aluminum metal in the early
days, but is made of polysilicon today (for the past 25 years or more).
 Oxide: silicon dioxide is the material between the gate and the channel
 Semiconductor: the semiconductor material is silicon, a type IV element in
the periodic chart. Each silicon atom bonds to four other silicon atoms in a
tetrahedral crystal structure.
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CMOS Logic
 CMOS stands for Complementary Metal Oxide Semiconductor
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CMOS Logic cont.…..
1. The Inverter
 Figure 1 shows the schematic and symbol for a
CMOS inverter or NOT gate using one nMOS
transistor and one pMOS transistor.
 The bar at the top indicates VDD and the triangle at
the bottom indicates GND.
 When the input A is 0, the nMOS transistor is OFF
and the pMOS transistor is ON. Thus, the output Y is
pulled up to 1 because it is connected to VDD but
not to GND.
 Conversely, when A is 1, the nMOS is ON, the pMOS
is OFF, and Y is pulled down to ‘0.’ This is
summarized in Table 1.1.
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1. Inverter cont……
Table 1.1 Inverter Truth Table
A Y
0 1
1 0
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2. The NAND Gate
 Figure 2(a) shows a 2-input CMOS NAND gate.
 It consists of two series nMOS transistors between Y and GND
and two parallel pMOS transistors between Y and VDD.
 If either input A or B is 0, at least one of the nMOS transistors
will be OFF, breaking the path from Y to GND. But at least
one of the pMOS transistors will be ON, creating a path from
Y to VDD. Hence, the output Y will be 1. If both inputs are 1,
both of the nMOS transistors will be ON and both of the pMOS
transistors will be OFF.
 Hence, the output will be 0. The truth table is given in Table
2 and the symbol is shown in Figure 2(b).
 Note that by DeMorgan’s Law, the inversion bubble may be
placed on either side of the gate. In the figures in this book,
two lines intersecting at a T-junction are connected.
 Two lines crossing are connected if and only if a dot is shown.
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2. The NAND Gate cont.…..
3. Table1.2 NAND gate truth table
A B Pull-Down Pull-Up y
Network Network
0 0 OFF ON 1
0 1 OFF ON 1
1 0 OFF ON 1
1 1 ON OFF 0
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2. The NAND Gate cont.…..
 k-input NAND gates are constructed using k-series nMOS transistors
and k parallel pMOS transistors.
 For example, a 3-input NAND gate is shown in Figure 3.
 When any of the inputs are 0, the output is pulled high through the
parallel pMOS transistors.
 When all of the inputs are 1, the output is pulled low through the
series nMOS transistors.
49
3. CMOS Logic Gates
 The inverter and NAND gates are examples of static CMOS logic gates, also
called complementary CMOS gates.
 In general, a static CMOS gate has an nMOS pull-down network to connect
the output to 0 (GND) and pMOS pull-up network to connect the output to
1 (VDD), as shown in Figure 4.
 The networks are arranged such that one is ON and the other OFF for any
input pattern.
Complementary CMOS logic gates
• nMOS pull-down
network
• pMOS pull-up
network
a.k.a. static CMOS
50
3. CMOS Logic Gates
VDD
In1
PMOS only
In2 PUN
(good for transfer 1)
InN
F(In1,In2,…InN)
In1
In2 PDN
NMOS only
InN
(good for transfer 0)
Pull-up Network (PUN) and Pull-down Network (PDN)

are Dual Logic Networks
51
3. CMOS Logic Gates
Transistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high
A B
X Y Y = X if A and B
X B Y = X if A OR B
Y
NMOS Transistors pass a “strong” 0 but a “weak” 1
52
3. CMOS Logic Gates
PMOS switch closes when switch control input is low
A B
X Y Y = X if A AND B = A + B
X B Y = X if A OR B = AB
Y
PMOS Transistors pass a “strong” 1 but a “weak” 0
53
(Use DeMorgan’s Law)
54
VDD
PDN : G  A  B  Connect to GND

PUN : F  A  B  A  B  Connnet toVDD
G ( In1, In2, In3,)  F ( In1, In2, In3,)
55
VDD
B
A
C
D
F  D  A  (B  C)
A
D
B C
56
VDD VDD
C
F SN4 A SN2
F SN1
SN2 B
A A
D D SN3
B C B C D SN1
F
(a) pull-down network (b) Deriving the pull-up network A

hierarchically by identifying
D
sub-nets
B C
SN2
SN1
(c) complete gate
57
 Full rail-to-rail swing: High noise margins
 Logic levels not dependent upon the relative device
sizes: Ratioless
 Always a path to Vdd or GND in steady state: Low
output impedance
 Extremely high input resistance; nearly zero steady-
state input current (input to CMOS gate)
 No steady-state direct path between power and
ground: No static power dissipation
 Propagation delay function of output load capacitance
and resistance of transistors
58
3. CMOS Logic Gates cont….
 AND gate
59
 OR gate
60
 A MOS transistor functions as a resistive element when in the active state.
 Realization of resistance in this form takes less silicon area in the IC as
compared to a resistance realized directly.
 pullup and pulldown represent such resistive elements.
 A typical instantiation here has the form
pullup (x);
 Here the net x is pulled up to the supply1 through a resistance. Similarly,
the instantiation
pulldown(y);
 pulls y down to the supply0 level through a resistance.
 The pullup and pulldown primitives can be used as loads for switches or to
connect the unused input ports to VCC or GND, respectively.
 They can also form loads of switches in logic circuits.
 The default strengths for pullup and pulldown are pull1 and pull0 respectively.
 One can also specify strength values for the respective nets.
61
 The pull-up and pull-down networks in the inverter each consist of
a single transistor. The NAND gate uses a series pull-down network
and a parallel pull-up network. More elaborate networks are used
for more complex gates.
 Two or more transistors in series are ON only if all of the series
transistors are ON.
 Two or more transistors in parallel are ON if any of the parallel
transistors are ON.
 This is illustrated in Figure 5 for nMOS and pMOS transistor pairs. By
using combinations of these constructions, CMOS combinational
gates can be constructed.
 In general, when we join a pull-up network to a pull-down network
to form a logic gate as shown in Figure 4, they both will attempt to
exert a logic level at the output. The possible levels at the output
are shown in Table 3.
 From this table it can be seen that the output of a CMOS logic gate
can be in four states.
62
• The 1 and 0 levels have been encountered with the inverter and NAND
gates, where either the pull-up or pull-down is OFF and the other
structure is ON.
• When both pull-up and pull-down are OFF, the high impedance or floating
Z output state results.
• This is of importance in multiplexers, memory elements, and tristate bus
drivers.
• The crowbarred (or contention) X level exists when both pull-up and pull-
down are simultaneously turned ON.
• Contention between the two networks results in an indeterminate output
level and dissipates static power. It is usually an unwanted condition.
TABLE 1.3 Output states of CMOS logic gates
Pull-up OFF Pull-up ON
pull-down OFF Z 1
pull-down ON 0 crowbarred
(X)(contention)
63
4. The NOR Gate
 A 2-input NOR gate is shown in Figure 6. The nMOS transistors are in
parallel to pull the output low when either input is high. The pMOS
transistors are in series to pull the output high when both inputs are
low, as indicated in Table 4. The output is never crowbarred or left
floating. Table 1.4 NOR Gate Truth table
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
64
4. The NOR Gate cont.….
 k-input NOR gates are constructed using k-series pMOS transistors
and k parallel nMOS transistors.
Example 1.1
Sketch a 3-input CMOS NOR gate.
SOLUTION: Figure 7 shows such a gate. If any input is high, the output
is pulled low through the parallel nMOS transistors. If all inputs are
low, the output is pulled high through the series pMOS transistors.
65
5. Compound Gates
 A compound gate performing a more complex logic function in a
single stage of logic is formed by using a combination of series and
parallel switch structures. For example, the derivation of the circuit
for the function 𝒀 = 𝑨. 𝑩 + (𝑪. 𝒅) is shown in Figure 8.
 This function is sometimes called AND-OR-INVERT-22, or AOI22
because it performs the NOR of a pair of 2-input ANDs.
 For the nMOS pull-down network, take the uninverted expression ((A·
B)+(C· D)) indicating when the output should be pulled to ‘0.’
 The AND expressions (A· B) and (C· D) may be implemented by series
connections of switches, as shown in Figure 8(a).
 Now ORing the result requires the parallel connection of these two
structures, which is shown in Figure 8(b).
66
5. Compound Gates cont….
 For the pMOS pull-up network, we must compute the complementary
expression using switches that turn on with inverted polarity.
 By DeMorgan’s Law, this is equivalent to interchanging AND and OR
operations.
 Hence, transistors that appear in series in the pull-down network
must appear in parallel in the pull-up network.
 Transistors that appear in parallel in the pulldown network must
appear in series in the pull-up network.
 This principle is called conduction complements and has already
been used in the design of the NAND and NOR gates.
 In the pull-up network, the parallel combination of A and B is placed
in series with the parallel combination of C and D.
 This progression is evident in Figure 8(c) and Figure 8(d). Putting the
networks together yields the full schematic (Figure 8(e)).
 The symbol is shown in Figure 8(f ).
67
68
This AOI22 gate can be used as a 2-input inverting multiplexer by connecting C=A as a
select signal. Then, Y=B if C is 0, while Y=D if C is 1.
Example 1.2
 Sketch a static CMOS gate computing Y=(A+B+C) · D.
 SOLUTION:- Figure 9 shows such an OR-AND-INVERT-3-1 (OAI31) gate. The nMOS
pull-down network pulls the output low if D is 1 and either A or B or C are 1, so D is
in series with the parallel combination of A,B, and C. The pMOS pull-up network is
the conduction complement, so D must be in parallel with the series combination of
A,B, and C
69
 The strength of a signal is measured by how closely it approximates
an ideal voltage source.
 In general, the stronger a signal, the more current it can source or
sink. The power supplies, or rails, (VDD and GND) are the source of
the strongest 1s and 0s.
 An nMOS transistor is an almost perfect switch when passing a 0 and
thus we say it passes a strong0. However, the nMOS transistor is
imperfect at passing a 1.
 The high voltage level is somewhat less than VDD. We say it passes
a degraded or weak1.
 A pMOS transistor again has the opposite behaviour, passing strong
1s but degraded 0s.
70
6. Pass Transistors and Transmission Gates
 A transmission gate is similar to a relay that can conduct in both
directions or block by a control signal with almost any voltage
potential.
 a transmission gate made up of two field effect transistors, in which
- in contrast to traditional discrete field effect transistors - the
substrate terminal (Bulk) is not connected internally to the source
terminal.
 The two transistors, an n-channel MOSFET and a p-channel MOSFET
are connected in parallel with this, however, only the drain and
source terminals of the two transistors are connected together.
Their gate terminals are connected to each other via a NOT gate
(inverter), to form the control terminal.
 As with discrete transistors, the substrate terminal is connected to
the source connection, so there is a transistor to the parallel diode
(body diode), whereby the transistor passes backwards.
71
 Transmission gates are used in order to realize electronic
switches and analog multiplexers.
 If a signal is connected to different outputs (changeover
switches, multiplexers), multiple transmission gates can be used
as a transmission gate to either conduct or block (simple
switch).
 A typical example is known as the 4066 4-way analog switch
which is available from various manufacturers.
 Logic circuits are constructed with the aid of transmission
gates, Usually can be smaller in comparison to traditional
transistorised logic circuits, and thus saves space on the silicon.
 Transmission gates represent a very useful application of logic
gates.
 A transmission gate allows a signal to pass only when a
certain condition is met, and the same gate can also invert
the signal if necessary.
72
 pass transistor logic (PTL) :
 describes several logic families used in the design of integrated circuits.
 It reduces the count of transistors used to make different logic gates, by
eliminating redundant transistors.
 Transistors are used as switches to pass logic levels between nodes of a
circuit, instead of as switches connected directly to supply voltages.
 This reduces the number of active devices, but has the disadvantage that the
difference of the voltage between high and low logic levels decreases at
each stage.
 Each transistor in series is less saturated at its output than at its input.If
several devices are chained in series in a logic path, a conventionally
constructed gate may be required to restore the signal voltage to the full
value.
 By contrast, conventional CMOS logic switches transistors so the output
connects to one of the power supply rails, so logic voltage levels in a
sequential chain do not decrease.
 Simulation of circuits may be required to ensure adequate performance.
73
 another way to implement logic functions using
transistors:
1. pass-transistor logic (NMOS only) and
2. transmission-gate logic (NMOS and PMOS
transistors).
 For some types of functions, this can lead to much more
efficient implementations than using gates.
 See the following 2:1 multiplexer for illustrating the the
above two way implementations using transistors:
74
a) Design using pass-transistor logic
 The 2:1 mux is 𝒁 = 𝑨𝑺 + 𝑩𝑺
 A multiplexer can be designed using various logics. The following figure shows
how a 2:1 MUX is implemented using a pass-transistor logic.
Fig.9.1. Design of a 2:1

MUX using pass-transistor
logic
• The pass-transistor logic attempts to reduce the number of transistors to implement a

logic by allowing the primary inputs to drive gate terminals as well as source-drain
terminals.
• The implementation of a 2:1 MUX requires 4 transistors (including the inverter required to
invert S), while a complementary CMOS implementation would require 6 transistors.
• The reduced number of devices has the additional advantage of lower capacitance.
75
 Figure 9.1.1: CMOS and PTL hybrid circuits.(a) Circuit design for an XOR gate with a
cascading CMOS inverter. (b) Output voltage levels for all four input states of the XOR
gate without (blue spheres) and with (green spheres) a cascading CMOS inverter. (c)
Circuit design for an XOR gate with a driving CMOS inverter. (d) Output voltage levels
for all four input states of the XOR gate without (blue spheres) and with (green spheres)
a CMOS inverter as its driving circuit.
CMOS-based carbon nanotube pass-transistor logic integrated circuits
76
CMOS-based carbon nanotube pass-transistor logic integrated circuits
77
b) Design using transmission gate logic
 A transmission gate is an electronic element and good non mechanical relay
built with CMOS technology. It is made by parallel combination of nMOS and
pMOS transistors with the input at the gate of one transistor (C) being
complementary to the input at the gate () of the other. The symbol of a
transmission gate is shown below in fig.9.2.
Fig.9.2: Symbol for tranmission gate
• The transmission gate acts as a bidirectional switch controlled by the gate

signal C.
• When C=1, both MOSFETs are on, allowing the signal to pass through the gate.
In short, A=B, if C=1.
• On the other hand, C=0, places both transistors in cut-off, creating an open
circuit between nodes A and B.
• Fig.9.3 shows the implementation of a 2:1 MUX using transmission gate logic.
78
b) Design using transmission gate logic
Fig.9.3: Circuit diagram of a 2:1

MUX using transmission gate
logic
Here, the transmission gates selects input A or B on the basis of the value
of the control signal S. When S=0, Z=A and when S=1, Z=B.
79
6. Pass Transistors and Transmission Gates cont….
 When an nMOS or pMOS is used alone as an imperfect
switch, we sometimes call it a pass transistor.
 By combining an nMOS and a pMOS transistor in parallel
(Figure 11(a)), we obtain a switch that turns on when a
1 is applied to g(Figure 11(b)) in which 0s and 1s are
both passed in an acceptable fashion (Figure 11(c)).
 We term this a transmission gate or pass gate. In a
circuit where only a 0 or a 1 has to be passed, the
appropriate transistor (n or p) can be deleted, reverting
to a single nMOS or pMOS device.
80
6. Pass Transistors and Transmission Gates cont.….
81
 Note that both the control input and its complement are
required by the transmission gate.
 This is called double rail logic. Some circuit symbols for
the transmission gate are shown in Figure 11(d).
 None are easier to draw than the simple schematic, so
we will use the schematic version to represent a
transmission gate in our case.
 In all of our examples so far, the inputs drive the gate
terminals of nMOS transistors in the pull-down network
and pMOS transistors in the complementary pull-up
network, as was shown in Figure 4.
82
 Thus, the nMOS transistors only need to pass 0s and the pMOS only
pass 1s, so the output is always strongly driven and the levels are
never degraded.
 This is called a fully restored logic gate and simplifies circuit design
considerably.
 In contrast to other forms of logic, where the pull-up and pull-down
switch networks have to be ratioed in some manner, static CMOS
gates operate correctly independently of the physical sizes of the
transistors.
 Moreover, there is never a path through ‘ON’ transistors from the 1
to the 0 supplies for any combination of inputs (in contrast to
single-channel MOS, GaAs technologies, or bipolar).
 This is the basis for the low static power dissipation in CMOS.
83
84
 A consequence of the design of static CMOS gates is that they
must be inverting.
 The nMOS pull-down network turns ON when inputs are 1,
leading to 0 at the output.
 We might be tempted to turn the transistors upside down to
build a non-inverting gate. For example, Figure 12 shows a
non-inverting buffer. Unfortunately, now both the nMOS and
pMOS transistors produce degraded outputs, so the technique
should be avoided.
 Instead, we can build non-inverting functions from multiple
stages of inverting gates.
 Figure 13 shows several ways to build a 4-input AND gate
from two levels of inverting static CMOS gates.
 Each design has different speed, size, and power trade-offs.
85
 XOR
 The circuit diagram of a two-input XOR gate is shown in Figure 13.1.
 The number of transistors required to implement this function is greatly
reduced using CMOS transmission gates than using the CMOS or NMOS
technologies.
 The output f is set to the value of x2 when x1 is equal to 0 by the top
transmission gate. On the other hand, the bottom transmission gate sets
the output f to the complement value of x2 when x1 is equal to 1.
Figure 13.1 XOR Gate Using Transmission

Gates
86
 Tristate (three-state) buffers are often used in I/O circuits to route multiple
signals into the same output, namely, serving as a multiplexer.
 Depending on circuit structures, there exists four types of tristate buffers
and inverters:
1. active-high enable buffer,
2. active-low enable buffer,
3. active-high enable inverter, and
4. active-low enable inverter.
 They are shown in Figure 15.13.
Figure 15.13: The four types of tristate buffers and inverters: (a) active-high enable
buffer; (b) active-low enable buffer; (c) active-high enable inverter; (d) active-low
enable inverter.
87
 See the tristate buffer in Figure 15.14(a). The two
common implementations of it are shown in Figures
15.14(b) and (c), respectively. i.e
 Using TG-based circuit;
 Using clocked CMOS (𝑪 𝑴𝑶𝑺) inverter circuit.

𝟐
 One is based on the cascading of an inverter and a

transmission gate (TG) switch and the other is based on a
clocked CMOS (𝑪𝟐 𝑴𝑶𝑺) inverter.
 Because two transistors are cascaded at the output of
either one, they have longer propagation delays
compared to standard inverters.
88
Figure 15.14: The general implementations of tristate
buffers:
• (a) logic symbol;
• (b) TG-based circuit;
• (c) C2MOS circuit. 89
 The general paradigm for designing a tristate buffer is
illustrated in Figure 15.15, where pMOS and nMOS
transistors are connected as a totem-pole just like an
inverter circuit.
 However, instead of connecting both gates of pMOS and
nMOS transistors together to the input, both gates are
controlled by an enable logic circuit (namely,
predriver), which has two inputs and two outputs.
 The design procedure is to derive the truth table of the
enable logic circuit, simplify it, and then implement
the results in CMOS gates.
 To illustrate this design procedure, an example is given
in the following.
90
Figure 15.15: The general paradigm of tristate buffers: (a) design principle;
(b) the resulting circuit.
91
 Example 15-5: (A tristate buffer design.) Assume that an
active-high enable tristate buffer is desired. Using the
paradigm depicted in Figure 15.15(a), design such a
buffer.
 Solution: As shown in Figure 15.15(a), both gates, x and y;
of the pMOS and nMOS transistors comprising the output
stage are controlled by the inputs, EN and D: From
the specifications, the circuit functions as a buffer if the
enable input EN is high and its output is in a high
impedance otherwise. As a result, the truth table is
obtained as displayed in Figure 15.15(a). Simplifying it, we
have
92
• The other three types of tristate buffer and inverter
circuits can be designed in a similar way. Hence, we omit
them here and leave them as exercises to the reader.
93
 Figure 15 shows symbols for a tristate buffer. When the enable
input EN is 1, the output Y equals the input A, just as in an ordinary
buffer. When the enable is 0, Y is left floating (a ‘Z’ value). This is
summarized in Table 1.5.
 Sometimes both true and complementary enable signals EN and 𝑬𝑵
are drawn explicitly, while sometimes only EN is shown.
 TABLE 1.5 Truth table for tristate
EN/𝑬𝑵 A Y
0/1 0 Z
0/1 1 Z
1/0 0 0
1/0 1 1
94
 The transmission gate in Figure 16 has the same truth table as a
tristate buffer.
 It only requires two transistors but it is a non-restoring circuit.
 If the input is noisy or otherwise degraded, the output will receive
the same noise.
 The delay of a series of non-restoring gates increases rapidly with
the number of gates.
95
 Figure 17(a) shows a tristate inverter. The output is
actively driven from VDD or GND, so it is a restoring
logic gate.
 Unlike any of the gates considered so far, the tristate inverter does
not obey the conduction complements rule because it allows the
output to float under certain input combinations.
 When EN is 0 (Figure 17(b)), both enable transistors are OFF,
leaving the output floating. When EN is 1 (Figure 17(c)), both
enable transistors are ON.
 They are conceptually removed from the circuit, leaving a simple
inverter. Figure 17(d) shows symbols for the tristate inverter. The
complementary enable signal can be generated internally or can be
routed to the cell explicitly. A tristate buffer can be built as an
ordinary inverter followed by a tristate inverter.
96
 Tristates were once commonly used to allow multiple units to drive a
common bus, as long as exactly one unit is enabled at a time. If multiple
units drive the bus, contention occurs and power is wasted. If no units drive
the bus, it can float to an invalid logic level that causes the receivers to
waste power. Moreover, it can be difficult to switch enable signals at exactly
the same time when they are distributed across a large chip. Delay between
different enables switching can cause contention. Given these problems,
multiplexers are now preferred over tristate busses.
97
 A multiplexer chooses the output from among several inputs based on a select
signal. A 2-input, or 2:1 multiplexer, chooses input D0 when the select is 0 and
input D1 when the select is 1. The truth table is given in Table 1.6; the logic
function is 𝒀 = 𝑺 · 𝑫𝟎 + 𝑺 · 𝑫𝟏.
 Table 1.6 Multiplexer Truth Table
S/𝑺 D1 D0 Y
0/1 X 0 0
0/1 X 1 1
1/0 0 X 0
1/0 1 X 1
98
8. Multiplexers cont…
 Two transmission gates can be tied together to form a compact 2-input multiplexer,
as shown in Figure 18(a).
 Nonrestoring mux uses two transmission gates
 Only 4 transistors
S
D0
S Y
D1
S
Fig. Transmission gate Multiplexer
99
 Again, the transmission gates produce a non-restoring multiplexer.
 We could build a restoring, inverting multiplexer out of gates in several ways. One is
the compound gate of Figure 18(e), connected as shown in Figure 19(a). Another is
to gang together two tristate inverters, as shown in Figure 19(b).
 This is possible because the select and its complement are mutually exclusive. The
tristate approach is slightly more compact and faster because it requires less
internal wire.
 Inverting multiplexer
 Use compound AOI22
 Or pair of tristate inverters
 Essentially the same thing
 Noninverting multiplexer adds an inverter
D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1
Fig-19-. Inverting Multiplexers

100
 The 4-to-1 mux is derived from a truth table as
 For 4 inputs, D0,D1,D2 and D3, we need 2 select lines.
 The table filling is random. That means, we can use 00 for D0, or D1 or D2 or D3 as
we want. We use 00 for D0
s0 s1 D3 D2 D1 D0 Out
0 0 -- -- -- D0 (~s0)&(~s1)&D0
0 1 -- -- D1 -- (~s0)&(s1)&D1
1 0 -- D2 -- -- (s0)&(~s1)&D2
1 1 D3 -- -- -- (s0)&(s1)&D3
𝐎𝐮𝐭 = ((~𝐬𝟎)&(~𝐬𝟏)&𝐃𝟎)|((~𝐬𝟎)&(𝐬𝟏)&𝐃𝟏)|((𝐬𝟎)&(~𝐬𝟏)&𝐃𝟐)|((𝐬𝟎)&(𝐬𝟏)&𝐃𝟑)
• This data-flow style expression is represented by the following

tri-state buffer implementation.
101
 Larger multiplexers can be built from multiple 2-input multiplexers or by directly
ganging together several tristates.
 The latter approach requires decoded enable signals for each tristate; the enables
should switch simultaneously to prevent contention. 4-input (4:1) multiplexers
using each of these approaches are shown in Figure 1.30.
 In practice, both inverting and non-inverting multiplexers are simply called
multiplexers or muxes.
S1S0 S1S0 S1S0 S1S0
D0
S0 S1
D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1
D3
Fig.20. 4:1 multiplexer
102
 In digital systems, we often need to distinguish the
following three memory elements:
 latch,
 flip-flop, and
 register.
 All of these three devices are constructed from bistable

devices.
 A latch is a level-sensitive bistable device whereas a flip-
flop is an edge-triggered bistable device.
 Both latches and flip-flops can be used as memory
(storage) elements.
 From an information viewpoint, a latch or flip-flop is a
device capable of storing 1-bit information. The word
“register" often means memory elements in digital
systems.
103
 A register is a device that consists of a specific number of
flip-flops. To be more specific, an n-bit register contains n
flip-flops. Hence, a flip-flop is a single bit register.
 As the name implies, a bistable device is a circuit having
two stable states. That is, it can remain at one state until
it is forced to change or transfer to another state by an
external way.
 One simple way to build such a bistable-state device is to
connect two inverters (NOT gates) in a cross-coupled
manner.
 In theory, an even number of inverters connected in a ring
structure is a bistable device, as illustrated in Figure
9.4(a).
104
Figure 9.5: An illustration of metastable state of typical latches: (a) basic concept;
(b) bistable circuit; (c) VTC(voltage transfer curve).
105
 So far, we have considered combinational circuits,
whose outputs depend only on the current inputs.
 Sequential circuits have memory: their outputs depend
on both current and previous inputs.
 Using the combinational circuits developed so far, we
can now build sequential circuits such as latches and
flip-flops. These elements receive a clock, CLK, and a
data input, D, and produce an output, Q. A D latch is
transparent when CLK=1, meaning that Q follows D.
 It becomes opaque when CLK=0, meaning Q retains its
previous value and ignores changes in D.
 An edge-triggered flip-flop copies D to Q on the rising
edge of CLK and remembers its old value at other times.
106
9.1. Latches
 Laches can be built using a multiplexer as shown below.
 The picture below uses a mux and a bi-stable device to design a latch.
 As you can see it above, the two inverters in series and a loop gives as a bi-
stable device.
 A D latch built from a 2-input multiplexer and two inverters is shown in
Figure 21(a).
 The multiplexer can be built from a pair of transmission gates, shown in
Figure 21(b), because the inverters are restoring.
Fig. (b)Mux Designed from Tri-state bufferes
107
9.1. Latches
108
9.1. Latches
 This latch also produces a complementary output, 𝑸. When CLK=1, the
latch is transparent and D flows through to Q(Figure 21(c)).
 When CLK falls to 0, the latch becomes opaque. A feedback path around
the inverter pair is established (Figure 21(d)) to hold the current state of Q
indefinitely.
 The D latch is also known as a level-sensitive latch because the state of the
output is dependent on the level of the clock signal, as shown in Figure
21(e).
 The latch shown is a positive-level-sensitive latch, represented by the
symbol in Figure 21(f ).
 By inverting the control connections to the multiplexer, the latch becomes
negative-level-sensitive.
109
9. Sequential Circuits cont…
9.1 Laches cont…
110
9.2 Flip-Flops
 Flip-flop can be constructed from laches.
 By combining two level-sensitive latches, one negative-
sensitive and one positive-sensitive, we construct the
edge-triggered flip-flop shown in Figure 22(a– b).
 The first latch stage is called the master and the second
is called the slave.
 While CLK is low, the master negative-level-sensitive
latch output (QM) follows the D input while the slave
positive-level-sensitive latch holds the previous value
(Figure 22(c)).
 When the clock transitions from 0 to 1, the master latch
becomes opaque and holds the D value at the time of
the clock transition.
111
.
Fig.22. we construct the edge-triggered flip-flop shown in

Figure 22(a– b) by using Laches.
112
9.2 Flip-Flops
 The slave latch becomes transparent, passing the stored
master value (QM) to the output of the slave latch (Q).
 The D input is blocked from affecting the output because the
master is disconnected from the D input (Figure 22(d)).
 When the clock transitions from 1 to 0, the slave latch holds
its value and the master starts sampling the input again.
 While we have shown a transmission gate multiplexer as the
input stage, good design practice would buffer the input and
output with inverters, as shown in Figure 22(e), top reserve
what we call “modularity.”
 Modularity is explained further in Section 1.6.2 and robust
latches and registers are discussed further in Section 10.3.
113
9.2 Flip-Flops cont.….
114
9.2 Flip-Flops cont….
 In summary, this flip-flop copies D to Q on the rising edge of the clock, as shown in
Figure 22(f ). Thus, this device is called a positive-edge triggered flip-flop (also
called a D flip-flop, D register, or master–slave flip-flop). Figure 22(g) shows the
circuit symbol for the flip-flop. By reversing the latch polarities, a negative-edge
triggered flip-flop may be constructed. A collection of D flip-flops sharing a common
clock input is called a register.
 A register is often drawn as a flip-flop with multi-bit D and Q busses.
 Note:
 flip-flops may experience hold-time failures if the system has too much clock
skew, i.e., if one flip-flop triggers early and another triggers late because of
variations in clock arrival times.
 In industrial designs, a great deal of effort is devoted to timing simulations to catch
hold-time problems.
 When design time is more important (e.g., in class projects), hold-time problems
can be avoided altogether by distributing a two-phase non-overlapping clock.
 Figure 23 shows the flip-flop clocked with two non-overlapping phases. As long as
the phases never overlap, at least one latch will be opaque at any given time and
hold-time problems cannot occur.
115
9.2 Flip-Flops cont….
116
 When CLK = 1, latch is transparent
 D flows through to Q like a buffer
 When CLK = 0, the latch is opaque
 Q holds its old value independent of D
 a.k.a. transparent latch or level-sensitive
latch
CLK
CLK
D
Latch
D Q Q
117 1: Circuits & Layout

Multiplexer chooses D or old Q
CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK
Q Q CLK
D Q D Q
CLK = 1 CLK = 0
CLK
118
 When CLK rises, D is copied to Q
 At all other times, Q holds its value
 a.k.a. positive edge-triggered flip-flop,
master-slave flip-flop
CLK
CLK
D
Flop
D Q
Q
119
 Built from master and slave D latches
CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch
Latch
QM
D Q
CLK CLK
QM Q
D
CLK = 0
QM
D Q
CLK = 1
CLK
120
 Back-to-back flops can malfunction from
clock skew
 Second flip-flop fires late
 Sees first flip-flop change and captures its result
 Called hold-time failure or race condition
CLK1
CLK1 CLK2 CLK2
Q1
Flop
Flop
Q1 Q2
D
Q2
121
 Nonoverlapping clocks can prevent races
 As long as nonoverlap exceeds clock skew
 We will use them in this class for safe design
 Industry manages skew more carefully instead
2 1
QM
D Q
2 2 1 1
2 1
1
2
122
 A CMOS transistor (or device) has four terminals:
 gate,
 source,
 drain, and
 bulk (tub or body or well).
 A CMOS transistor is a switch. The switch must be conducting or on to allow current to
flow between the source and drain terminals
 The transistor source and drain terminals are equivalent as far as digital signals are
concerned—we do not worry about labeling an electrical switch with two terminals.
 𝑽𝑨𝑩 is the potential difference, or voltage, between nodes A and B in a circuit; 𝑽𝑨𝑩
is positive if node A is more positive than node B.
 Italics denote variables; constants are set in roman (upright) type. Uppercase
letters denote DC, large-signal, or steady-state voltages.
 For TTL the positive power supply is called VCC (Vcc or Vcc), The 'C’ denotes that
the supply is connected indirectly to the collectors of the npn bipolar transistors (a
bipolar transistor has a collector, base, and emitter—corresponding roughly to the
drain, gate, and source of an MOS transistor).
123
 Following the example of TTL we used VDD (𝐕𝐃𝐃 or
𝑽𝑫𝑫 ) to denote the positive supply in an NMOS chip
where the devices are all n-channel transistors and
the drains of these devices are connected
indirectly to the positive supply. The supply
nomenclature for NMOS chips has stuck for CMOS.
 VDD is the name of the power supply node or net;
VDD represents the value (uppercase since VDD is a
DC quantity). Since VDD is a variable, it is italic
(words and multi-letter abbreviations use roman—
thus it is VDD, but Vdrain).
 Logic designers often call the CMOS negative supply
VSS or Vss even if it is actually ground or GND. we
shall use VSS for the node and Vss for the value.
 CMOS uses positive logic—VDD is logic '1' and VSS is
logic '0'.
124
 CMOS Transistors:-
 Figure 24 illustrates how electrons and holes abandon
their dopant atoms leaving a depletion region around a
transistor's source and drain.
 The region between source and drain is normally non-
conducting.
 To make an n-channel transistor conducting, we must
apply a positive voltage VGS (the gate voltage with
respect to the source) that is greater than the n-channel
transistor threshold voltage, Vtn (a typical value is 0.5V
and, as far as we are presently concerned, is a constant).
 This establishes a thin (≈50 A) conducting channel of
electrons under the gate.
 MOS transistors can carry a very small current (the
subthreshold current—a few microamperes or less) with
VGS < Vtn, but we shall ignore this.
125
 CMOS Transistors:-
 A transistor can be conducting (VGS > Vtn) without
any current flowing.
 To make current flow in an n-channel transistor we must
also apply a positive voltage, 𝑽𝑫𝑺 , to the drain with
respect to the source.
 Figure24 shows these connections and the
connection to the fourth terminal of an MOS
transistor—the bulk (well, tub, or substrate)
terminal.
 For an n-channel transistor we must connect the bulk to
the most negative potential, GND or VSS, to reverse bias
the bulk-to-drain and bulk-to-source pn-diodes.
 The arrow in the four-terminal n-channel transistor
symbol in Figure 24 reflects the polarity of these pn-
diodes.
126
FIGURE 24: An n-channel MOS transistor. The gate-oxide thickness, Tox, is approximately
100angstroms (0.01𝞵m). Atypical transistor length, L = 2𝝺. The bulk may be either the
substrate or a well. The diodes represent pn-junctions that must be reverse-biased.
127
 CMOS transistors cont….
 The current flowing in the transistor is
𝐜𝐮𝐫𝐫𝐞𝐧𝐭 𝐚𝐦𝐩𝐞𝐫𝐞𝐬 = 𝐜𝐡𝐚𝐫𝐠𝐞 𝐜𝐨𝐮𝐥𝐨𝐦𝐛𝐬 𝐩𝐞𝐫 𝐮𝐧𝐢𝐭 𝐭𝐢𝐦𝐞 𝐬𝐞𝐜𝐨𝐧𝐝 .−−−− −(𝟏)
 We can express the current in terms of the total charge in
the channel, Q(imagine taking a picture and counting the
number of electrons in the channel at that instant).
 If 𝑡𝑓 (for time of flight—sometimes called the transit time)
is the time that it takes an electron to cross between
source and drain, the drain-to-source current, 𝐼𝐷𝑆𝑛 , is
𝐈𝐃𝐒𝐧 = 𝐐/𝐭 𝐟 ------------------------------ (2)
 We need to find Q and 𝑡𝑓
The velocity of the electrons v (a vector) is given by the
equation that forms the basis of Ohm’s law:
𝐯 = – 𝛍𝐧 𝐄,−−−−−−−−−−−−−−−−− −(𝟑)
where 𝜇𝑛 is the electron mobility(𝜇𝑝 is the hole mobility) and
E is the electric field (with units 𝑣𝑚−1 ).
128
 Typical carrier mobility values are 𝜇𝑛 =
500– 1000 𝑐𝑚2 𝑉 −1 𝑆 −1 and 𝜇𝑝 = 100– 400 𝑐𝑚2 𝑉 −1 𝑆 −1
 Equation 3 is a vector equation, but we shall ignore
the vertical electric field and concentrate on the
horizontal electric field, Ex, that moves the electrons
between source and drain.
 The horizontal component of the electric field is
𝐸𝑥 = – 𝑉𝐷𝑆 / 𝐿, directed from the drain to the source,
where L is the channel length (see Figure 24).
 The electrons travel a distance L with horizontal
velocity 𝐯𝐱 = – 𝛍𝐧 𝐄𝐱 , so that
𝐋 𝐋𝟐
𝐭𝐟 = = -------------------------------(4)
𝐯𝐱 𝛍𝐧 𝐯𝐃𝐒
129
 Next we find the channel charge, Q. The channel and
the gate form the plates of a capacitor, separated by
an insulator—the gate oxide.
 We know that the charge on a linear capacitor, C, is
𝑄 = 𝐶𝑉.
 Our lower plate, the channel, is not a linear
conductor.
 Charge only appears on the lower plate when the
voltage between the gate and the channel, 𝑽𝑮𝑪 ,
exceeds the n -channel threshold voltage.
 For our non-linear capacitor we need to modify the
equation for a linear capacitor to the following:
𝑄 = 𝐶(𝑉𝐺𝐶 – 𝑉𝑡𝑛 )-------------------------(5)
130
 The lower plate of our capacitor is resistive and conducting current, so
that the potential in the channel, 𝑉𝐺𝐶 , varies.
 In fact, 𝑽𝑮𝑪 = 𝑽𝑮𝑺 at the source and 𝑽𝑮𝑪 = 𝑽𝑮𝑺 – 𝑽𝑫𝑪 at the drain.
 What we really should do is find an expression for the channel
charge as a function of channel voltage and sum (integrate) the
charge all the way across the channel, from x= 0 (at the source) to
x= L (at the drain).
 Instead we shall assume that the channel voltage, 𝐕𝐆𝐂 (𝐱), is a linear
function of distance from the source and take the average value of
the charge, which is thus
𝟏
𝐐 = 𝐂 𝐕𝐆𝐒 – 𝐕𝐭𝐧 – 𝐕𝐃𝐒 −−−−−− −(𝟔)
𝟐
• The classical capacitance formula is
𝝐𝑨
• 𝑪 = 𝒅 , where A is the Area ፣ Є is the di-electric constant and d is the distance
between plates. Using this, we can drive the following formulas
131
 The gate capacitance, C, is given by the formula for a
parallel-plate capacitor with length L, width W, and plate
separation equal to the gate-oxide thickness, Tox. Thus the
gate capacitance is
𝑾𝑳𝜺𝒐𝒙
𝑪 = = 𝑾𝑳𝑪𝒐𝒙 −−−−−−−−−−−−−− −(𝟕)
𝑻𝒐𝒙
 where 𝜀𝑜𝑥 is the gate-oxide dielectric permittivity.

 For silicon dioxide, 𝑆𝑖𝑂2 , 𝜀𝑜𝑥 ≈ 3.45𝑥10−11 𝐹𝑚−1 , so that,
for a typical gate-oxide thickness of 100 A (1𝐴° = 1 angstrom
= 0.1 nm), the gate capacitance per unit area, 𝐶𝑜𝑥 ≈
3𝑓𝐹𝜇𝑚−2 .
 Now we can express the channel charge in terms of the
transistor parameters,
𝟏
𝑸 = 𝑾𝑳𝑪𝒐𝒙 [ 𝑽𝑮𝑺 − 𝑽𝒕𝒏 − 𝑽𝑫𝑺 ]……………………………(8)
𝟐
132
 Finally, the drain–source current is
𝐐 𝐖 𝟏
𝐈𝐃𝐒𝐧 = = 𝛍𝐧 𝐂𝐨𝐱 (𝐕𝐆𝐒 −𝐕𝐭𝐧 ) − 𝐕𝐃𝐒 𝐕𝐃𝐒
𝐭𝐟 𝐋 𝟐
𝐖 ′ 𝐕𝐆𝐒 −𝐕𝐭𝐧 −𝟏𝐕𝐃𝐒 𝐕 ′
= 𝐤 𝟐 𝐃𝐒 ---------(9)
𝐋
The constant 𝐾 ′ is the process trans-conductance parameter (or intrinsic
trans-conductance):
𝑘′ = 𝜇𝑛 𝐶𝑜𝑥 . -------------------------(10)
We also define 𝛽𝑛 , the transistor gain factor (or just gain factor) as
′ 𝑊
𝛽𝑛 = 𝑘 ---------------------------------(11)
𝐿
 In electronics, gain is a measure of the ability of a two
port circuit (often an amplifier) to increase
the power or amplitude of a signal from the input to the output port
by adding energy converted from some power supply to the signal.
 It is usually defined as the mean ratio of the signal amplitude or
power at the output port to the amplitude or power at the input port
133
 The factor W/L (transistor width divided by length) is the transistor
shape factor.
 Equation 9 describes the linear region (or triode region) of
operation. This equation is valid until 𝑉𝐷𝑆 = 𝑉𝐺𝑆 − 𝑉𝑡𝑛 and then
predicts that 𝐼𝐷𝑆 decreases with increasing VDS, which does not make
physical sense.
 At 𝑽𝑫𝑺 = 𝑽𝑮𝑺 − 𝑽𝒕𝒏 = 𝑽𝑫𝑺 (𝒔𝒂𝒕) (the saturation voltage) there is no
longer enough voltage between the gate and the channel to support
any channel charge.
 Clearly a small amount of charge remains or the current would go to
zero, but with very little free charge the channel resistance in a small
region close to the drain increases rapidly and any further increase in
𝑉𝐷𝑆 is dropped over this region.
 Thus for 𝑉𝐷𝑆 > 𝑉𝐺𝑆 − 𝑉𝑡𝑛 (the saturation region, or pentode region,
of operation) the drain current 𝐼𝐷𝑆 remains approximately constant at
the saturation current, 𝑰𝑫𝑺 (sat)' where
𝛃𝐧 . . 𝟐
𝐈𝐃𝐒𝐧 𝐬𝐚𝐭 = 𝐕𝐆𝐒 − 𝐕𝐭𝐧 ; 𝐕𝐃𝐒 > 𝐕𝐆𝐒 − 𝐕𝐭𝐧 .−−−−−−−−−− −(𝟏𝟐)
𝟐
134
 Figure 25 shows the n-channel transistor 𝐼𝐷𝑆 − 𝑉𝐷𝑆 characteristics
for a generic 0.5𝞵m CMOS process that we shall call G5.
 We can fit Eq. 12 to the long-channel transistor characteristics
(W = 60𝞵m, L = 6𝞵m) in Figure 25(a).
 If 𝐼𝐷𝑆𝑛 (𝑠𝑎𝑡) = 2.5 mA (with 𝑉𝐷𝑆 = 3.0𝑉, 𝑉𝐺𝑆 = 3.0𝑉, 𝑉𝑡𝑛 =
0.65 𝑉, 𝑇𝑜𝑥 = 100𝐴), the intrinsic trans-conductance is
𝐿 6
2( )𝐼𝐷𝑆𝑛𝑠𝑎𝑡 2(60)2.5𝑋10−3
𝐾𝑛′ = 𝑊 = 2 = 9.05𝑥10−5
𝑥𝐴𝑉 −2
−− −13
(𝑉𝐺𝑆 − 𝑉𝑡𝑛 ) 2 (3.0 − 0.65)
or approximately 90𝜇𝑚𝐴𝑉 −2 .
 This value of 𝐾𝑛′ , calculated in the saturation region, will be
different (typically lower by a factor of 2 or more) from the
value of k measured in the linear region. We assumed the
mobility, 𝜇𝑛 , and the threshold voltage, 𝑣𝑡𝑛 , are constants—
neither of which is true.
135
136
 FIGURE 25 MOS n-channel transistor
characteristics for a generic 0.5 𝞵m process (G5).
 (a) A short-channel transistor, with W = 6 𝞵m and
L = 0.6 𝞵m (drawn) and a long-channel transistor
(W = 60 𝞵m, L = 6𝞵m)
 (b) The 6/0.6 characteristics represented as a
surface, (c) A long-channel transistor obeys a
square-law characteristic between 𝑰𝑫𝑺 and 𝑽𝑫𝑺
in the saturation region (𝑽𝑫𝑺 = 3 V).
 A short-channel transistor shows a more linear
characteristic due to velocity saturation.
 Normally, all of the transistors used on an ASIC
have short channels.
137
 For the p-channel transistor in the G5 process,
𝐼𝐷𝑆𝑝 (𝑠𝑎𝑡) = −850𝜇𝐴 (𝑉𝐷𝑆 = −3.0 𝑉, 𝑉𝐺𝑆 = −3.0 𝑉, 𝑉𝑡𝑝 =
−0.85 𝑉, 𝑊 = 60 𝜇𝑚, 𝐿 = 6 𝜇𝑚).
 Then
𝐿 6
2 (−𝐼𝐷𝑆𝑝 𝑠𝑎𝑡 ) 2( )(850)
𝐾𝑝′ = 𝑊 = 60
(𝑉𝐺𝑆 − 𝑉𝑡𝑝 )2 (−3.0 − (−0.85))2
= 3.68x10−5 𝜇𝐴 −−−−−−−−−−−−−−−−− −(14)
138
 P-Channel Transistors:-
 The source and drain of CMOS transistors look identical; we have to
know which way the current is flowing to distinguish them.
 The source of an n-channel transistor is lower in potential than the
drain and vice-versa for a p-channel transistor.
 In an n-channel transistor the threshold voltage, 𝑽𝒕𝒏 , is normally
positive, and the terminal voltages 𝑽𝑫𝑺 and 𝑽𝑮𝑺 are also usually
positive.
 In a p-channel transistor 𝑽𝒕𝒑 is normally negative and we have a
choice: We can write everything in terms of the magnitudes of the
voltages and currents or we can use negative signs in a consistent
fashion.
 Here are the equations for a p-channel transistor using negative
signs:
𝐖 𝟏
𝐈𝐃𝐒 = −𝐊 ′𝐩 𝐕𝐆𝐒 − 𝐕𝐭𝐩 − 𝐕𝐃𝐒 𝐕𝐃𝐒 𝐕𝐃𝐒 > 𝐕𝐆𝐒 − 𝐕𝐭𝐩−−−−−−−−𝟏𝟓
𝐋 𝟐
 Eq. 15 is for saturation(pentode region) for p-mos
−𝛃𝐩
𝐈𝐃𝐒𝐩 = (𝐕𝐆𝐒−𝐕𝐭𝐩 )𝟐 𝐕𝐃𝐒 < 𝐕𝐆𝐒 − 𝐕𝐭𝐩 −−−−−− −𝟏𝟓. 𝟏
𝟐
 Eq. 15.1 is for triode(linear region) of p-mos
139
 P-Channel Transistors cont.…..
 In these two equations 𝑉𝑡𝑝 is negative, and
the terminal voltages 𝑉𝐷𝑆 and 𝑉𝐺𝑆 are also
normally negative (and -3V<-2 V, for
example).
 The current 𝐼𝐷𝑆𝑝 is then negative,
corresponding to conventional current
flowing from source to drain of a p-channel
transistor (and hence the negative sign for
𝑰𝑫𝑺𝒑 𝒔𝒂𝒕 in Eq. 14).
140
1. Calculate 𝐼𝐷𝑆 and the resistance (the DC value
𝑉𝐷𝑆 /𝐼𝐷𝑆 of long-channel transistors with the following
parameters, under the specified conditions. In each
case state whether the transistor is in the saturation
region, linear region, or off:
i. 𝑛 − 𝑐ℎ𝑎𝑛𝑛𝑒𝑙: 𝑉𝑡𝑛 = 0.5𝑉, 𝛽𝑛 = 40𝜇𝐴𝑉 −2 :
𝑉𝐺𝑆 = 3.3𝑉: 𝑎). 𝑉𝐷𝑆 = 3.3𝑉 𝑏). 𝑉𝐷𝑆 = 0.0𝑉 𝑐). 𝑉𝐺𝑆
= 0.0𝑉, 𝑉𝐷𝑆 = 3.3 𝑉
ii. 𝑝 − 𝑐ℎ𝑎𝑛𝑛𝑒𝑙: 𝑉𝑡𝑝 = −0.6𝑉, 𝛽𝑝 = 20𝜇𝐴𝑉 −2 :
𝑉𝐺𝑆 = 0.0𝑉: 𝑎). 𝑉𝐷𝑆 = 0.0𝑉 𝑏). 𝑉𝐷𝑆 = −5.0𝑉 𝑐). 𝑉𝐺𝑆
= −5.0𝑉, 𝑉𝐷𝑆 = −5.0𝑉
141
 Fully Complementary CMOS Networks
Complex Gates - Example
1. Implement the function 𝐹 = 𝐴 𝐵 + 𝐶 using CMOS logic.
 Solution. In general:
 nMOS in series is used to implement AND logic
 pMOS in series is used to implement NOR logic
 nMOS in parallel is used to implement OR logic
 pMOS in parallel is used to implement NAND logic
Given a function F, to draw a fully CMOS network, follow
the following steps:
1. First take the complement of F to form F’
2. Implement F’ as an nMOS net and connect it to GRD
(pull-down net) and F.
3. Find dual of F’, implement it as a pMOS net and
connect it to +V (pull-up net) and F.
4. Connect switch inputs.
142
143
2. Draw a complete pass transistor logic circuits
consisting of all NMOS devices for the Boolean
expressions listed below.
a) 𝐹 = 𝐴𝐵 + 𝐴𝐵 𝐶
b) 𝐹 = 𝐴 + B𝐶 + 𝐶 𝐷
144
3. Determine the output logic function f(x1, x2, x3) of
the three-input CMOS logic circuit in Figure below.
Solution:
𝑉𝑓 = 𝑉𝑥1 (𝑉𝑥2 + 𝑉𝑥3 )
145
4. Implement the following logic functions using CMOS
transistors and calculate the number of transistors
required.
146
5. Determine the number of transistors in the logic
circuit in Figure below if the gates were
implemented in CMOS technology.
147
Review Questions
1. What is the difference between Gate array and standard
cell? Explain Briefly.
2. When did you think that MOS used as variable resistors and
Switches?
3. State the Moore’s law?
4. What is the corollary of Moore’s law?
5. What is the difference between MOSFETs and BJTs?
6. What is Rent’s Rule? Explain it clearly.
6. Explain Pass Transistors and Transmission Gates?
7. What is hold-time and setup-time? And what are the
how do the setup and hold time violation occur? How
to avoid setup and hold time violations?
7.1. draw the circuit diagram of AND transmission gate,
OR transmission gate ,NAND transmission gate, NOR
transmision gate
148
Review Questions cont….
8. Sketch a transistor-level schematic for a CMOS 4-
input NOR gate.
149
9.1. what is the difference between pass transistor and
transmission gates?
9.2. what are MOSIS CMOS design Rules? Explain and list
all of them.
9.3. what is the difference between race condition and
contention?
150
11. What type of bulk(well or substrate needed to build
a p-channel MOS transistor?
12. What type of bulk(well or substrate needed to build
a n-channel MOS transistor?
13. Explain clearly using graphs and mathematical
explanation the saturation(pentode) region,
triode(linear) region and cut-off region of n-mos and
p-mos transistors separately.
14. Clearly explain SPICE with its parameters?
151
Answers:
8. .
9. .
152
Answers:
10. .
153

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1.

 Disadvantages of standard cell libraries

 MOSIS compatible cell libraries are provided by

above the conduction band edge.

Pull-up Network (PUN) and Pull-down Network (PDN)

Transistors can be thought as a switch controlled by its gate signal

NMOS Transistors pass a “strong” 0 but a “weak” 1

PMOS switch closes when switch control input is low

PMOS Transistors pass a “strong” 1 but a “weak” 0

PDN : G  A  B  Connect to GND

(a) pull-down network (b) Deriving the pull-up network A

Pull-up OFF Pull-up ON

Fig.9.1. Design of a 2:1

• The pass-transistor logic attempts to reduce the number of transistors to implement a

CMOS-based carbon nanotube pass-transistor logic integrated circuits

CMOS-based carbon nanotube pass-transistor logic integrated circuits

Fig.9.2: Symbol for tranmission gate

• The transmission gate acts as a bidirectional switch controlled by the gate

Fig.9.3: Circuit diagram of a 2:1

Figure 13.1 XOR Gate Using Transmission

 Using clocked CMOS (𝑪 𝑴𝑶𝑺) inverter circuit.

 One is based on the cascading of an inverter and a

Fig-19-. Inverting Multiplexers

• This data-flow style expression is represented by the following

 All of these three devices are constructed from bistable

Fig. (b)Mux Designed from Tri-state bufferes

Fig.22. we construct the edge-triggered flip-flop shown in

117 1: Circuits & Layout

 where 𝜀𝑜𝑥 is the gate-oxide dielectric permittivity.

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