Third International Conference on Devices, Circuits and Systems (ICDCS'16) 275

Power Analysis of Bit interleaving 9T

SRAM array
1
Karthika .S , 2 Dr. N.M. SivaMangai
Department of Electronics and Communication,
Karunya University,Tamil Nadu, India
1
karthikapillai819@gmail.com
2
nmsivam@gmail.com

Abstract - S oft error issue is major concern in S RAM Many discussions have been made to
array. It can be overcome if the array is constructed improve the data retention ability of the SRAM cell
in bit interleaving architecture. Hence in this paper, in recent years. Many assist techniques have been
an analysis of bit interleaving S RAM array to
reported which concentrates on improving the cell-
overcome soft error using 9T S RAM cell has been
operating margins like write margin and Read
made. It shows that 9T S RAM array with bit
margin [1]. In order to obtain the same, many
interleaving architecture has less power and has good
stability when compared to shared word line
authors have suggested SRAM cell design with

architecture using 6T S RAM cell. Area, Power and
S NM has been compared for 6T S RAM and 9T
S RAM. Results indicates that 9T S RAM cell shows
power reduction of 75.89 % when compared to
conventional 6T S RAM cell with trade - off of 25.98
% increase in area. The 9T S RAM cell also has 63.03
% improvement in S NM than 6T S RAM cell.
Keywords – Bit interleaving , SRAM , SNM , Shared
word line
I. Introduction
High Stability and Low Power plays a
very important role in designing of SRAM (Static
Random Access Memory). Today’s era
advanced technologies demands for low power
consuming architectures with high stability. In
SoC, most of the area is occupied by SRAM and
hence it dominates the total power consumption as
well as system performance. So to maintain the low
power as well as stability remains the major theme
of SRAM designs.
more number of transistors [3-5].This helps in
improving the stability by having separate read port
and write port but most of them can be
implemented using word – line sharing architecture
not bit inter leaving architecture. Word line sharing
architecture increases the probability of soft errors
because all the bits of same words are kept adjacent
to each other whereas in bit interleaving
architecture bits of adjacent words are interleaved
in order to avoid the probability of soft errors. Also
cells arranged in an array undergoes half selected
issue which leads to more power consumption as
well as less stability. This problem can be
of overcome by using modified 9T SRAM cell
structure and the bit interleaving architecture[1].
So in this paper, an analysis of bit
interleaving SRAM array to overcome soft error
using 9T SRAM cell has been made. It shows that
9T SRAM array with bit interleaving architecture
has less power and has good stability when
compared to shared wordline architecture using 6T
SRAM cell. Rest of the paper is organized as

978-1-5090-2309-7/16/$31.00©2016 IEEE
Third International Conference on Devices, Circuits and Systems (ICDCS'16) 276

follows: Section II reviews the 6T SRAM cell. III. DESIGN METHODOLOGY

Section III explains the Design Methodology and
A single-ended read disturb-free 9T
Section IV analyses the power and stability of
SRAM cell has been used for bit-interleaving
SRAM cell. Section V concludes the paper.
architecture. It consist of a single bit line (BL) but
II. 6T SRAM CELL
an extra wordline (RWL) has been used for read
The conventional 6T SRAM cell is shown
operation. The read and write operations are
in Figure 1 ,which includes two back to back
assisted by NMOS transistor (M8) which is
inverters (M 5, M 2 , M 6 and M 1 ) and two access
controlled by CBLB. Figure 2 shows the 9T SRAM
transistors (M 3 and M 4 ).These access transistors are
cell. During the hold mode, RWL is made low and
used to provide path to the storage transistor(M 1
WL is made high which makes the transistors (M3
and M 2 ).SRAM includes three phases of operation
and M4 ) to be in off state hence isolating the
: write, precharge and read. The wordline (WL)
storage nodes from external disturbance. A t the
controls the operation of access transistors. During
same time, complementary signal of CBL (CBLB)
write operation, the wordline is made high and the
is made high, which turns the transistor M8 on. As
bitline( BL) and Bitlinebar (BLBAR) value is
a result, the data is retained in the cross coupled
stored in the storage nodes(out 1 and out 2 )
back-to-back inverter pair. A write operation is
respectively. The write phase is followed by the
initiated by making the WL to be low and
precharge phase during which the bitline (BL) and
activating the CBL signal to high which precharges
bitline bar (BLBAR) is precharged to Vdd by
the LWL signal to ‘1’. As a result , the value in bit
turning off the wordline. At the time of read phase,
– line is transferred to storage nodes through M3.
again the wordline is activated which leads to the
The Conventional SRAM cell suffers voltage
droping of either bitline or bitline bar based on the
dividing between access and pull-down transistors
value written.
which degrades the stored value.

Figure 1. Conventional 6T SRAM cell

The values stored in SRAM cell is prone to

external noises which will cause the stored data to
Figure 2. 9T SRAM cell
drop. So the circuit should be immune to the
external noises in order to have better performance This problem is solved using the
and data retention. The immunity of the circuit to controlling transistor M8 which is in off state
the noise is given on the basis of Static Noise during write hence isolating the storage nodes from
Margin or SNM. So, it is very important to have external noise. During the read operation, RWL is
high SNM value. activated and the BL is precharged to high . First
Third International Conference on Devices, Circuits and Systems (ICDCS'16) 277

and foremost, the BL is pre-charged to high. The
M1 and M4 transistors assist the read operation and
the opposite of the stored data is read out. Also the
M8 transistor isolates the storage node from read
current. After a read operation, the CBLB is again
made high, which makes the cell to be in hold
mode thus retaining the data.
IV . RESULTS AND DISCUSSION
For the next 25ns, the wordline is made low and the
bit lines (BL, BLBAR) are precharged to Vdd . After
50ns, the Read operation is initiated during which
the wordline (WL) is again made high that results
in the voltage drop of out 1 and out 2 remains at
Vdd. This indicates that the data “1” has been
stored SRAM cell. The immunity of the circuit to
the external noise is given in terms of SNM. Figure
5 shows SNM curve for conventional 6T SRAM

All the simulations has been carried out in cell. The basic SNM curve of SRAM is obtained by

45nm technology using cadence tool. Figure 3 superimposing the voltage transfer characteristics

shows the schematic view of 6T SRAM cell.
(VTC) of two back to back connected inverters.
The resulting two lobed curve is referred as the
“butterfly curve”. The SNM is represented as the
length of the side of the largest square that can be
embedded into the lobes of the curve. The SNM
value is 141. 5 mV

141.5 mV

Figure 3. Schematic view of 6T SRAM cell

Figure 4 shows the output waveform of

conventional 6T SRAM cell during write “1”
mode. From 0 to 25ns, the write operation is
activated by making the wordline to be at 1V(Vdd)
Figure 5 . SNM of 6T SRAM cell
and bitlines (BL,BLBAR) at 1V and 0V
respectively. Figure 6 Shows the layout of the 6T SRAM cell.

Figure 4. Output Waveform of 6T SRAM cell

Figure 6. Layout of 6T SRAM cell
Third International Conference on Devices, Circuits and Systems (ICDCS'16) 278

The area occupied by 6T SRAM cell is 4.86um

sq. Figure 9 shows the schematic view of 9T
382.84 mV
SRAM cell.

Figure 11. SNM of 9T SRAM cell

Figure 12 shows the layout of the 9T SRAM cell.

The area occupied by 9T SRAM cell is 6.566 um

Figure 9. Schematic view of 9T SRAM cell sq.

Figure 10 shows the output waveform of 9T

SRAM cell during write “1”.Initially wordline
(WL) is maintained at 1V and CBL at 0V which
initiates the HOLD mode. At 25ns , wordline is
changed to 0V and CBL, Bitline (BL) are charged
to 1V. At 50ns, Read operation is initiated by
turning the RWL to 1V. It leads to the droping of
bitline which indicates logic “1” is written.

Figure 12. Layout of 9T SRAM cell

Figure 13 shows the schematic view of 16 x 16

6T SRAM array.

Figure 10 The transient simulation during write “1

Figure 11 shows the Static noise margin curve of

9T SRAM cell. The SNM is obtained by
performing the DC analysis for the pair of inverter.
During the read operation, the feedback loop of
Figure 13. 16x16 6T SRAM array
inverter is cut down which isolates the storage
node from any sort of external disturbances. Thus Figure 14 shows the transient simulation of 16 x
providing a very high stability for 9T SRAM cell. 16 6T SRAM array. The 6T array undergoes the
The SNM value for 9T SRAM cell is 382.84 mV.
Third International Conference on Devices, Circuits and Systems (ICDCS'16) 279

problem of half selected cell which leads to extra

power consumption and drop in output voltage with
increase in number of stages. In 6T array when a
particular cell is accessed, all the adjacent cells
undergoes read operation which leads to voltage
drop at the storage node.

Figure 16. Transient Simulation of 16 x 16 9T

SRAM array

Table 1 shows the power comparison for 9T and

6T SRAM array.

Figure 14 . Transient Simulation of 16 x16 6T Table1. Power comparison of 9T and 6T SRAM

SRAM array array

Figure 15 shows the 16 x 16 9T SRAM array 6T SRAM array 9T SRAM array

Power
(uW) 95.84 23.10

V. CONCLUS ION

The 9T SRAM array with bit inter leaving

architecture has been constructed to overcome the
soft error issues. Results indicates that 9T SRAM

Figure 15 . 16 x 16 9T SRAM array cell shows power reduction of 75.89 % when

compared to conventional 6T SRAM cell with
Figure 16 shows the output waveform of 9T array. trade - off of 25.98 % increase in area. The 9T
The 9T array has an add on feature of column bit SRAM cell also has 63.03 % improvement in
lines which isolates the adjacent cell hence
SNM than 6T SRAM cell.
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