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Board name: Mother Board Schematic 1. System Block Diagram & Schematic page description;
Project name: N01 2. Power Block Diagram & Discription;
Version: VerA 3. Annotations & information;
initial Date: 4. Schematic modify Item and history;
New update: 5. Power on & off Sequence;
6. ACPI Mode Switch Timings;
7. Power On Sequence Map;
8. CLOCK Distribution;
C C
9. Power Distribution;
Topstar Confidential
B B
A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name Title
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 1 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
CONTENT
Speaker
Daught Board
A TOPSTAR TECHNOLOGY A
Swain Xu
Page Name System Block & Index
SD/MMC/MS/XD CARD
Size Project Name Rev
PG 22 A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 2 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
Chipset Power
Always power DDR Power
ISL6545
ISL6545 TPS51116
PU4/PU5 PU3
PU1/PU2
+V3.3AL,2A +V1.8
+V1.5S,3A +V0.9S
/+V5AL,3A
/+V1.05S,3A
MOSFET
B
Switch B
+V3.3S,2A
/+V5S,3A
LDO
+V2.5S,0.5A
A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name PWR Block & description
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 3 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
Voltage Rails
I2C SMB Address
+VDC Primary DC system power supply (6V-9.5V)
Device Address Hex Master
+VBATTERY Battery Power supply (6-8.4V) Clock Generator 1101 001x D2 ICH7-M
D D
+VCC_CORE Core Voltage for CPU
SO-DIMM0 1010 000x A0 ICH7-M
CPU Thermal Sensor 1001 100x 98 KBC
+V1.05S 1.05V for Calistoga & ICH7M core / FSB VTT Smart Battery 0001 011x 16 KBC
+V1.8 1.8V power rail for DDR2
PCIE Slot TBD TBD ICH7-M
PCB Layers
Top(Signal1)
VCC 2
Wake up Events
Signal 3 Trace Impedence:55ohm +/-15%
LID switch from EC
Signal4
Power switch from EC
Ground 5
Bottom(Signal6)
B B
PCB Footprints
3 5 4
USB Table
SOT23 SOT23_5
USB Port# Function Description
1 2 1 2 3
0 Standard USB2.0 Port
1 Standard USB2.0 Port
2 Standard USB2.0 Port
3 MINICARD_USB ns: Component marked "ns" is not stuff
4 CAM_USB
5 MINICARD_USB
A 6 CR_USB TOPSTAR TECHNOLOGY A
Swain Xu
7 NC Page Name
NOTE
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 4 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
D D
C C
B B
A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name Sch Modify and history
Size Project Name Rev
A3 A
A
Date: Wednesday, July 16, 2008 Sheet 5 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
+V3.3S 7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39
+V1.05S 7,8,9,11,12,17,20,28,35,36,37
FB29 35 1 2 RA0402_4
SRC10# CLK_PCIE_EXPCARD# 23
100ohm@100MHz,3A R631 22 R0402 5
29 PCI_CLK_EC PCI3/FSD
FB0805 33 MPCIE_CLKREQ R643 475,1% R0402 ns
SRC11/OE#_10 PCIE_CLKREQ# 23,24
R632 22 R0402 27M_SEL 6 32 MCH_CLKREQ R634 475,1% R0402 ns
23 PCI_CLK_DEBUG MCH_CLKREQ# 10
2
PCI4/SRC5_SEL SRC11#/OE#_9
R635 22 R0402 PCIF_ITP_EN 7 30 3 4
18 PCI_CLK_ICH PCIF5/ITP_EN SRC9 CLK_MCH_3GPLL 10
+VDDIO_CLK 31 1 2
SRC9# CLK_MCH_3GPLL# 10
C395 C396 CLK_XTAL_IN 60 RN11
C C394 10UF/6.3V,X5R 0.1uF/10V,X5R R640 10K R0402 XTAL_IN 33 C
SRC7/OE#_8 44
10UF/6.3V,X5R C0805 C0402 CLK_XTAL_OUT 59 43 RA0402_4
C0805 Set to SRC8 No more than 500 milXTAL_OUT SRC7#/OE#_6
C407
27pF/50V,NPO CLK_XTAL_IN
C0402 1
B B
Y5
14.318180MHz
XS2
C408
2
27pF/50V,NPO CLK_XTAL_OUT
C0402 +V3.3S
CLK_ICH14 C410 10PF/50V,NPO ns
BUS FREQUENCE SELECT C0402
MCH_CLKREQ R675 10K R0402 CLK_USB48 C411 10PF/50V,NPO ns
+V1.05S C0402
MPCIE_CLKREQ R646 10K R0402 PCI_CLK_DEBUG C412 10PF/50V,NPO ns
C0402
PCI_CLK_EC C413 10PF/50V,NPO ns
C409 C0402
R641 R650 R649 0.1UF/25V,Y5V TME R648 10K R0402 PCI_CLK_ICH C414 10PF/50V,NPO ns
56 1K 1K C0402 C0402
R0402 R0402 R0402 0:Normal mode
ns ns +V3.3S
1:No Overclocking
R642 0 R0402 ns CLK_BSEL0 R670 1K R0402
7 CPU_BSEL0 MCH_BSEL0 10
R651 0 R0402 ns CLK_BSEL1 R671 1K R0402
7 CPU_BSEL1 MCH_BSEL1 10
R647
R652 0 R0402 ns CLK_BSEL2 R672 1K R0402 10K
7 CPU_BSEL2 MCH_BSEL2 10
R0402
R0402
ns
R0402 R0402 BSEL2 BSEL1 BSEL0 frequency Swain Xu
R654 Page Name CK505M
10K
0 0 1 133MHz R0402 Size Project Name Rev
ns A3 A A
Date: Wednesday, July 16, 2008 Sheet 6 of 42
1 0 1 100MHz PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
9 H_D#[63:0]
U22B
H_D#[63:0] 9
U22A ICTP H_D#0 Y11 R3 H_D#32
9 H_A#[31:3] T1 +V1.05S D[0]# D[32]#
H_A#3 P21 V19 H_D#1 W10 R2 H_D#33
A[3]# ADS# H_ADS# 9 D[1]# D[33]#
H_A#4 H20 Y19 H_D#2 Y12 P1 H_D#34
A[4]# BNR# H_BNR# 9 D[2]# D[34]#
H_A#5 N20 U21 H_D#3 AA14 N1 H_D#35
A[5]# BPRI# H_BPRI# 9 D[3]# D[35]#
DATA GRP 0
H_A#6 R20 H_D#4 AA11 M2 H_D#36
A[6]# D[4]# D[36]#
0
GROUP
ADDR
H_A#7 J19 T21 H_D#5 W12 P2 H_D#37
A[7]# DEFER# H_DEFER# 9 D[5]# D[37]#
H_A#8 N19 T19 R63 R64 H_D#6 AA16 J3 H_D#38
A[8]# DRDY# H_DRDY# 9 D[6]# D[38]#
DATA GRP 2
D H_A#9 G20 Y18 56 330 H_D#7 Y10 N3 H_D#39 D
A[9]# DBSY# H_DBSY# 9 D[7]# D[39]#
H_A#10 M19 R0402 R0402 H_D#8 Y9 G3 H_D#40
H_A#11 A[10]# H_D#9 D[8]# D[40]# H_D#41
H21 A[11]# BR0# T20 H_BREQ#0 9 Y13 D[9]# D[41]# H2
H_A#12 L20 H_D#10 W15 N2 H_D#42
A[12]# D[10]# D[42]#
CONTROL
H_A#13 M20 F16 H_IERR# H_D#11 AA13 L2 H_D#43
H_A#14 A[13]# IERR# R65 1K,1% R0402 H_D#12 D[11]# D[43]# H_D#44
K19 A[14]# INIT# V16 H_INIT# 17 Y16 D[12]# D[44]# M3
H_A#15 J20 H_D#13 W13 J2 H_D#45 H_DSTBN#/H_DSTBP# should route
H_A#16 A[15]# H_D#14 D[13]# D[45]# H_D#46 as differential pair
L21 A[16]# LOCK# W20 H_LOCK# 9 AA9 D[14]# D[46]# H1
K20 Place testpoint on H_D#15 W9 J1 H_D#47
9 H_ADSTB#0 ADSTB[0]# T3 ICTP H_IERR# with a GND D[15]# D[47]#
T2 ICTP D17 D15 Y14 K2
9 H_REQ#[4:0] AP0 RESET# H_CPURST# 9 0.1" away 9 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 9
H_REQ#0 N21 W18 Y15 K3
REQ[0]# RS[0]# H_RS#0 9 9 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 9
H_REQ#1 J21 Y17 W16 L1
REQ[1]# RS[1]# H_RS#1 9 9 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 9
H_REQ#2 G19 U20 T4 ICTP V9 M4 ICTP
REQ[2]# RS[2]# H_RS#2 9 DP#0 DP#2 T5
H_REQ#3 P20 W19
REQ[3]# TRDY# H_TRDY# 9 9 H_D#[63:0] H_D#[63:0] 9
H_REQ#4 R19 H_D#16 AA5 C2 H_D#48
REQ[4]# H_D#17 D[16]# D[48]# H_D#49
9 H_A#[31:3] HIT# AA17 H_HIT# 9 Y8 D[17]# D[49]# G2
H_A#17 C19 V20 H_D#18 W3 F1 H_D#50
A[17]# HITM# H_HITM# 9 D[18]# D[50]#
H_A#18 F19 H_D#19 U1 D3 H_D#51
H_A#19 A[18]# H_BPM#0 ICTP H_D#20 D[19]# D[51]# H_D#52
E21 A[19]# BPM[0]# K17 T7 W7 D[20]# D[52]# B4
DATA GRP 1
H_A#20 A16 J18 H_BPM#1 ICTP H_D#21 W6 E1 H_D#53
A[20]# BPM[1]# T6 D[21]# D[53]#
H_A#21 D19 H15 H_BPM#2 ICTP H_D#22 Y7 A5 H_D#54
A[21]# BPM[2]# T8 D[22]# D[54]#
H_A#22 C14 J15 H_BPM#3 ICTP H_D#23 AA6 C3 H_D#55
DATA GRP 3
A[22]# BPM[3]# T9 D[23]# D[55]#
ADDR GROUP 1
A[33]# THRMDA 0.5" max for GTLREF 9 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 9
H_A#34 B15 E5 H_THERMDC 1K,1% T12 ICTP R4 D4
A[34]# THRMDC R0402 DP#1 DP#3 T13ICTP
H_A#35 A14 A[35]# COMP0 R68 27.4,1% R0402
9 H_ADSTB#1 B19 ADSTB[1]# THERMTRIP# H17 PM_THRMTRIP# 10,17,28 A7 GTLREF COMP[0] T1
T14 ICTP M18 R67 1K,1% R0402 ns ACLKPH U5 T2 COMP1 R70 54.9,1% R0402 Layout note:
AP1 R69 1K,1% R0402 ns DCLKPH ACLKPH COMP[1] COMP2 R72 27.4,1% R0402 Comp0,2 connec with Zo=27.4ohm,make
V5 DCLKPH COMP[2] F20
U18 R71 C19 T15 ICTP T17 F21 COMP3 R73 54.9,1% R0402 trace length shorter than 0.5"
17 H_A20M# A20M# BINIT# COMP[3]
T16 V11 2K,1% 0.1uF/10V,X5R T16 ICTP R6 MISC Comp1,3 connec with Zo=55ohm,make
17 H_FERR# FERR# BCLK[0] CLK_CPU_BCLK 6 R0402 EDM
J4 V12 C0402 EXTBGREF M6 R18 trace length shorter than 0.5"
17 H_IGNNE# IGNNE# BCLK[1] CLK_CPU_BCLK# 6 EXTBGREF DPRSTP# H_DPRSTP# 17
T17 ICTP N15
H CLK
+VCC_CORE 36,39
U22D
A2 VSS1 VSS162 N5 +V1.5S 10,11,12,20,23,24,35,36,37
A4 VSS2 VSS161 N7
A8 VSS4 VSS160 N9 +V1.05S 6,7,9,11,12,17,20,28,35,36,37
A15 VSS5 VSS159 N13
A18 VSS6 VSS158 N17
A19 P3 U22C +V1.05S
VSS7 VSS157
A20 VSS8 VSS156 P4
B1 VSS9 VSS155 P5 VTT1 C9
B2 VSS10 VSS154 P6 VTT2 D9
1
B5 P7 E9 C26 C27 C28 C29 C30 C31 C32 C33
VSS11 VSS153 +V1.05S VTT3 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R
D B8 P9 F8 + C34 D
1
VSS12 VSS152 VTT4 C0402 C0402 C0402 C0402 C0402 C0402 C0805 C0805 220uF/2.5V,POSCAP
B13 VSS13 VSS151 P13 VTT5 F9
B20 P15 G8 ns ns ns CT7343_19
2
VSS14 VSS149 VTT6 ns
B21 VSS15 VSS148 P16 V10 VCCF VTT7 G14
C8 VSS16 VSS147 P18 VTT8 H8
C17 VSS17 VSS146 P19 A9 VCCQ1 VTT9 H14
D1 VSS18 VSS145 R1 B9 VCCQ2 VTT10 J8
D5 VSS19 VSS144 R5 VTT11 J14
D8 VSS20 VSS143 R7 VTT12 K8
D14 VSS21 VSS142 R9 VTT13 K14
D18 VSS22 VSS141 R13 VTT14 L8
D21 VSS23 VSS140 R21 VTT15 L14
E3 VSS24 VSS139 T4 VTT16 M8
E6 VSS25 VSS138 T5 VTT17 M14
E7 VSS26 VSS137 T7 VTT18 N8
E8 T9 +VCC_CORE N14
VSS27 VSS136 VTT19
E15 VSS28 VSS135 T10 VTT20 P8
E16 VSS29 VSS134 T11 A10 VCCP1 VTT21 P14
E19 VSS30 VSS133 T12 A11 VCCP2 VTT22 R8
F4 VSS31 VSS132 T13 A12 VCCP3 VTT23 R14
F5 VSS32 VSS131 T18 B10 VCCP4 VTT24 T8
F6 VSS33 VSS130 U3 B11 VCCP5 VTT25 T14
F7 VSS34 VSS129 U6 B12 VCCP6 VTT26 U8
F17 VSS35 VSS128 U7 C10 VCCP7 VTT27 U9
F18 VSS36 VSS127 U15 C11 VCCP8 VTT28 U10
G1 VSS37 VSS126 U16 C12 VCCP9 VTT29 U11
G4 VSS38 VSS125 U19 D10 VCCP10 VTT30 U12
G7 VSS39 VSS124 V1 D11 VCCP11 VTT31 U13
G9 VSS41 VSS123 V4 D12 VCCP12 VTT32 U14
C G13 V6 E10 C
VSS42 VSS122 VCCP13
G21 VSS45 VSS121 V7 E11 VCCP14
H3 VSS46 VSS120 V8 E12 VCCP15
H4 VSS48 VSS119 V13 F10 VCCP16 VCCPC64 F14
H7 VSS49 VSS118 V14 F11 VCCP17 VCCPC63 F13
H9 VSS51 VSS117 V18 F12 VCCP18 VCCPC62 E14
H13 VSS52 VSS116 V21 G10 VCCP19 VCCPC61 E13
H16 W1 G11 +V1.5S
VSS53 VSS115 VCCP20
H18 VSS54 VSS114 W5 G12 VCCP21
H19 VSS55 VSS113 W8 H10 VCCP22
J5 VSS56 VSS112 W11 H11 VCCP23
J7 W14 H12 C35 C36
VSS57 VSS111 VCCP24 0.1uF/10V,X5R 10uF/6.3V,X5R
J9 VSS58 VSS110 W17 J10 VCCP25
J13 W21 J11 C0402 C0805
VSS59 VSS109 VCCP26 ns
J17 VSS60 VSS108 Y1 J12 VCCP27
K1 VSS61 VSS107 Y2 K10 VCCP28
K6 VSS62 VSS106 Y20 K11 VCCP29
K7 Y21 K12 Place near PIN D7
VSS63 VSS105 VCCP30
K9 VSS64 VSS104 AA2 L10 VCCP31 VCCA D7
K13 VSS65 VSS103 AA3 L11 VCCP32
K15 VSS66 VSS102 AA4 L12 VCCP33
K21 VSS67 VSS101 AA7 M10 VCCP34 VID[0] F15
L3 AA10 M11 D16 +VCC_CORE
VSS68 VSS100 VCCP35 VID[1]
L4 VSS69 VSS99 AA12 M12 VCCP36 VID[2] E18
L5 VSS70 VSS98 AA15 N10 VCCP37 VID[3] G15
L6 VSS71 VSS97 AA18 N11 VCCP38 VID[4] G16
L7 AA19 N12 E17 R106
VSS72 VSS96 VCCP39 VID[5] 100,1%
L9 VSS73 VSS95 AA20 P10 VCCP40 VID[6] G18
L13 P11 R0402
B VSS74 VCCP41 B
L15 VSS75 P12 VCCP42
L18 VSS76 R10 VCCP43 VCCSENSE C13
L19 VSS77 R11 VCCP44
M1 VSS78 R12 VCCP45
M5 VSS79 VSSSENSE D13
M7 VSS80
M9 Diamondville Layout Note: VCCSENSE
VSS81 and VSSSENSE lines R107
M13 VSS82
M21 should be of equal 100,1%
VSS83 R0402
N4 VSS84
length
+VCC_CORE
C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52
0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R
C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402
A A
+VCC_CORE TOPSTAR TECHNOLOGY
Swain Xu
Page Name Diamondville (PWR&GND)(2of2)
C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64
10uF/6.3V,X5R Size Project Name Rev
10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R C0805 A3 N01
A
C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805
Date: Wednesday, July 16, 2008 Sheet 8 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
+V1.05S
+V1.05S 6,7,8,11,12,17,20,28,35,36,37
+V1.05S
D D
U23A
7 H_D#[63:0] H_A#[31:3] 7
H_D#0 C4 F8 H_A#3
R108 H_D#1 HD0# HA3# H_A#4
F6 HD1# HA4# D12
221,1% H_D#2 H9 C13 H_A#5
R0603 H_D#3 HD2# HA5# H_A#6
H6 HD3# HA6# A8
H_D#4 F7 E13 H_A#7
H_D#5 HD4# HA7# H_A#8
E3 HD5# HA8# E12
H_XSWING Trace should be 10mil H_D#6 C2 J12 H_A#9
H_D#7 HD6# HA9# H_A#10
wide with 20mil C3 HD7# HA10# B13
H_D#8 K9 A13 H_A#11
spacing! H_D#9 F5
HD8# HA11#
G13 H_A#12
H_D#10 HD9# HA12# H_A#13
J7 HD10# HA13# A12
R109 C65 H_D#11 K7 D14 H_A#14
100,1% 0.1uF/10V,X5R H_D#12 HD11# HA14# H_A#15
H8 HD12# HA15# F14
R0402 C0402 H_D#13 E5 J13 H_A#16
H_D#14 HD13# HA16# H_A#17
K8 HD14# HA17# E17
H_D#15 J8 H15 H_A#18
H_D#16 HD15# HA18# H_A#19
J2 HD16# HA19# G15
H_D#17 J3 G14 H_A#20
H_D#18 HD17# HA20# H_A#21
N1 HD18# HA21# A15
H_D#19 M5 B18 H_A#22
H_D#20 HD19# HA22# H_A#23
K5 HD20# HA23# B15
+V1.05S H_D#21 J5 E14 H_A#24
H_D#22 HD21# HA24# H_A#25
H3 HD22# HA25# H13
H_D#23 J4 C14 H_A#26
H_D#24 HD23# HA26# H_A#27
N3 HD24# HA27# A17
R110 H_D#25 M4 E15 H_A#28
221,1% H_D#26 HD25# HA28# H_A#29
M3 HD26# HA29# H17
C R0603 H_D#27 N8 D17 H_A#30 C
H_D#28 HD27# HA30# H_A#31
N6 HD28# HA31# G17
H_D#29 K3
H_YSWING H_D#30 HD29#
Trace should be 10mil N9 HD30#
wide with 20mil H_D#31 M1 F10 +V1.05S
HD31# HADS# H_ADS# 7
H_D#32 V8 C12
spacing! HD32# HADSTB0# H_ADSTB#0 7
H_D#33 V9 H16
HD33# HADSTB1# H_ADSTB#1 7
R111 H_D#34 R6 E2
100,1% C66 H_D#35 HD34# H_AVREF R112
T8 HD35# HBNR# B9 H_BNR# 7
R0402 0.1uF/10V,X5R H_D#36 R2 C7 100,1%
HD36# HBPRI# H_BPRI# 7
HOST
C0402 H_D#37 N5 G8 R0402
HD37# HBREQ0# H_BREQ#0 7
H_D#38 N2 B10
HD38# HCPURST# H_CPURST# 7
H_D#39 R5 E1
H_D#40 HD39# HDVREF
U7 HD40#
H_D#41 R8 AA6
HD41# HCLKN CLK_MCH_BCLK# 6
H_D#42 T4 AA5 C67 C68 R113
HD42# HCLKP CLK_MCH_BCLK 6
H_D#43 T7 C10 0.1uF/10V,X5R 0.1uF/10V,X5R 200,1%
HD43# HDBSY# H_DBSY# 7
H_D#44 R3 C6 C0402 C0402 R0402
HD44# HDEFER# H_DEFER# 7
H_D#45 T5 H5 ns
HD45# HDINV0# H_DINV#0 7
H_D#46 V6 J6
HD46# HDINV1# H_DINV#1 7
+V1.05S H_D#47 V3 T9
HD47# HDINV2# H_DINV#2 7
H_D#48 W2 U6
HD48# HDINV3# H_DINV#3 7
H_D#49 W1 G7
HD49# HDPWR# H_DPWR# 7
H_D#50 V2 E6
HD50# HDRDY# H_DRDY# 7 Place close to PIN-E1/E2
H_D#51 W4 F3
HD51# HDSTBN0# H_DSTBN#0 7
R114 R115 H_D#52 W7 M8
HD52# HDSTBN1# H_DSTBN#1 7
54.9,1% 54.9,1% H_D#53 W5 T1
HD53# HDSTBN2# H_DSTBN#2 7
R0402 R0402 H_D#54 V5 AA3
HD54# HDSTBN3# H_DSTBN#3 7
H_D#55 AB4 F4
B HD55# HDSTBP0# H_DSTBP#0 7 B
H_D#56 AB8 M7
HD56# HDSTBP1# H_DSTBP#1 7
H_XSCOMP H_D#57 W8 T2
HD57# HDSTBP2# H_DSTBP#2 7
H_D#58 AA9 AB3
HD58# HDSTBP3# H_DSTBP#3 7
H_YSCOMP H_D#59 AA8
H_D#60 HD59#
AB1 HD60#
H_D#61 AB7
H_D#62 HD61#
AA2 HD62# HHIT# C8 H_HIT# 7
H_XRCOMP H_D#63 AB5 B4
HD63# HHITM# H_HITM# 7
HLOCK# C5 H_LOCK# 7 H_REQ#[4:0] 7
H_YRCOMP G9 H_REQ#0
HREQ0# H_REQ#1
HREQ1# E9
H_XRCOMP A10 G12 H_REQ#2
H_XSCOMP HXRCOMP HREQ2# H_REQ#3
Trace should be 10mil A6 HXSCOMP HREQ3# B8
R116 R117 wide with 20mil H_XSWING C15 F12 H_REQ#4
24.9,1% 24.9,1% H_YRCOMP HXSWING HREQ4#
J1 A5 H_RS#0 7
R0402 R0402 spacing! H_YSCOMP K1
HYRCOMP HRS0#
B6
HYSCOMP HRS1# H_RS#1 7
H_YSWING H1 G10
HYSWING HRS2# H_RS#2 7
HCPUSLP# E8 H_CPUSLP# 7,17
HTRDY# E10 H_TRDY# 7
945GMS
A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name Calistoga(HOST)
Size Project Name Rev
A3 N01 A
Date: Wednesday, July 16, 2008 Sheet 9 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
+V3.3S 6,7,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39
+V1.5S_PCIE 12
+V1.5S 8,11,12,20,23,24,35,36,37
+V1.8 +V1.8 12,14,34,36,37
+V1.5S_PCIE
U23F
U23B
D D
H27 SDVOCTRL_DATA EXP_COMPI R28
18 DMI_TXN0 Y29 DMI_RXN0 CFG0 C18 MCH_BSEL0 6 J27 SDVOCTRL_CLK EXP_ICOMPO M28
Y32 E18 Y26 R123
18 DMI_TXN1 DMI_RXN1 CFG1 MCH_BSEL1 6 6 CLK_MCH_3GPLL# GCLKN
Y28 G20 AA26 N30 24.9,1%
18 DMI_TXP0 DMI_RXP0 CFG2 MCH_BSEL2 6 6 CLK_MCH_3GPLL GCLKP SDV0_TVCLKIN# R0402
MISC
18 DMI_TXP1 Y31 DMI_RXP1 CFG3 G18 SDVO_INT# R30
J20 GMS_CFG5 T29
CFG5 SDVO_FLDSTALL#
18 DMI_RXN0 V28 DMI_TXN0 CFG6 J18
18 DMI_RXN1 V31 DMI_TXN1
18 DMI_RXP0 V29 DMI_TXP0 16 CRT_DDC_CLK H20 DDCCLK SDVO_TVCLKIN M30
V32 R130 R131 R132 H22 P30
DMI
18 DMI_RXP1 DMI_TXP1 16 CRT_DDC_DATA DDCDATA SDVO_INT
2.2K 2.2K 2.2K A24 T30
R0402 R0402 R0402 16 CRT_BLUE BLUE SDVO_FLDSTALL
A23 BLUE#
ns ns E25
16 CRT_GREEN GREEN
14 M_CLK_DDR0 AF33 SM_CK0 MCH_RSVD1 K32 F25 GREEN#
SDVO
AG1 K31 C25
VGA
14 M_CLK_DDR1 SM_CK1 MCH_RSVD2 16 CRT_RED RED
MCH_RSVD7 C17 D25 RED#
AJ1 F18 16 CRT_VSYNC R125 39 R0402 F27
SM_CK2 MCH_RSVD8 R120 39 R0402 VSYNC
AM30 SM_CK3 MCH_RSVD9 A3 16 CRT_HSYNC D27 HSYNC
CFG/RSVD
R121 255,1%R0603 H25 P28
REFSET SDVOB_RED#
14 M_CLK_DDR#0 AG33 SM_CK0# SDVOB_GREEN# N32
14 M_CLK_DDR#1 AF1 SM_CK1# 15 LVDS_BKLTCTL H30 LBKLT_CTRL SDVOB_BLUE# P32
15,29 LVDS_BKLTEN G29 LBKLT_EN SDVOB_CLKN T32
AK1 LCTLA_CLK F28
SM_CK2# LCTLB_DATA LCTLA_CLK
AN30 SM_CK3# E28 LCTLB_CLK
DDR2 MUXING
L_DDC_CLK G28 N28
L_DDC_DATA LDDC_CLK SDVOB_RED
14 M_CKE0 AN21 SM_CKE0 H28 LDDC_DATA SDVOB_GREEN M32
14 M_CKE1 AN22 SM_CKE1 15 LVDS_VDDEN K30 LVDD_EN SDVOB_BLUE P33
AF26 R122 1.5K,1% R0402 K27 R32
C SM_CKE2 LIBG SDVOB_CLKP C
AF25 SM_CKE3 J29 LVBG
J30 LVREFH
AG14 K29 +V1.5S
14 M_CS#0 SM_CS0# LVREFL
14 M_CS#1 AF12 SM_CS1#
AK14 SM_CS2# 15 MCH_LVDS_CLKAN D30 LACLKN TVDAC_A A21
AH12 SM_CS3# 15 MCH_LVDS_CLKAP C30 LACLKP TVDAC_B C20
A30 LBCLKN TVDAC_C E20
LVDS
AJ21 SMOCDCOMP0 A29 LBCLKP TV_REFSET G23
TV
AF11 SMOCDCOMP1 ICHSYNC# E31 MCH_ICH_SYNC# 18 TV_IRTNA B21
BM_BUSY# G21 PM_BMBUSY# 19 15 MCH_LVDS_YAN0 G31 LADATAN0 TV_IRTNB C21
PM
SMRCOMPP
AA33 SMVREF0 F33 LBDATAN0
CLK
945GMS
945GMS
Close to GMCH
ONE PIN, ONE CAP
B B
R733 SM_VREF_L 14,34
0
R0402 +V3.3S
A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name Calistoga(Graphic)
Size Project Name Rev
A3 N01 A
+V1.05S 6,7,8,9,12,17,20,28,35,36,37
+V1.5S 8,10,12,20,23,24,35,36,37
+V3.3S 6,7,10,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39
+V1.05S +V1.5S
U23H
A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name
Calisoga(DDRII&NCTF)
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 11 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
+V3.3S 6,7,10,11,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39
+V1.05S 6,7,8,9,11,17,20,28,35,36,37
+V1.05S
3A
+V1.5S 8,10,11,20,23,24,35,36,37
+V1.5S
U23D +V1.5S_PCIE 10
C72 C520 C73 C522
10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R T26 B20
120mA
VCC0 VCCA_TVDACA0 +V2.5S 37,38
C0805 C0805 C0805 C0805 R26 A20
VCC1 VCCA_TVDACA1
P26 VCC2 VCCA_TVDACB0 B22 +V1.8 10,14,34,36,37
N26 VCC3 VCCA_TVDACB1 A22
D M26 VCC4 VCCA_TVDACC0 D22 D
V19 VCC5 VCCA_TVDACC1 C22
U19 VCC6 VCCA_TVBG D23
C77 C78 C74 T19 E23
10uF/6.3V,X5R 4.7uF/10V,X5R 1uF/10V,X7R VCC7 VSSA_TVBG +V1.5S
W18 VCC8 VCCD_TVDAC F20
C0805 C0805 C0603 FB8
V18
T18
VCC9 VCCDQ_TVDAC F22
C28
20mA +V1.5S 100ohm@100MHz,3A +V1.5S_DPLLA
VCC10 VCCD_LVDS0 C79 FB0805
R18
W17
VCC11 VCCD_LVDS1 B28
A28 0.1uF/10V,X5R C80 1 2
50mA
VCC12 VCCD_LVDS2 C0402 10uF/6.3V,X5R
U17 VCC13 VCCHV0 E26
R17 D26 C0805 C84 C86
C81 C82 C75 VCC14 VCCHV1 10uF/6.3V,X5R 0.1uF/10V,X5R
W16 VCC15 VCCHV2 C26
0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R C0805 C0402
C0402 C0402 C0402
V16
T16
VCC16 VCCSM0 AB33
AM32
40mA
VCC17 VCCSM1 +V3.3S
R16 VCC18 VCCSM2 AN29
V15 VCC19 VCCSM3 AM29
U15 AL29 FB10
VCC20 VCCSM4 C76 100ohm@100MHz,3A +V1.5S_DPLLB
T15 VCC21 VCCSM5 AK29
0.1uF/10V,X5R C83 FB0805
AD33
VCCSM6 AJ29
AH29 C529 C530 C0402 10uF/6.3V,X5R 1 2
50mA
VCC_AUX1 VCCSM7 1uF/10V,X7R 1uF/10V,X7R C0805
AD32 VCC_AUX2 VCCSM8 AG29
AD31 AF29 C0603 C0603 C88 C89
VCC_AUX3 VCCSM9 10uF/6.3V,X5R 0.1uF/10V,X5R
AD30 VCC_AUX4 VCCSM10 AE29
AD29 AN24 C0805 C0402
VCC_AUX5 VCCSM11
AD28 VCC_AUX6 VCCSM12 AM24
AD27 VCC_AUX7 VCCSM13 AL24
AC27 AK24 C521 +V1.5S_MPLL
VCC_AUX8 VCCSM14 10uF/6.3V,X5R
+V1.5S
AD26
AC26
VCC_AUX9 VCCSM15 AJ24
AH24 C0805 1 2
45mA
C VCC_AUX10 VCCSM16 C
TBD AB26
AE19
VCC_AUX11 VCCSM17 AG24
AF24 C87 FB3 C95 C96
VCC_AUX12 VCCSM18 1uF/10V,X7R 100ohm@100MHz,3A 10uF/6.3V,X5R 0.1uF/10V,X5R
AE18 VCC_AUX13 VCCSM19 AE24
AF17 AN18 C0603 FB0805 C0805 C0402
C85 VCC_AUX14 VCCSM20
AE17 VCC_AUX15 VCCSM21 AN16
0.1uF/10V,X5R AF16 AM16 +V1.8 +V1.5S_HPLL
C0402 VCC_AUX16 VCCSM22
AE16
AF15
VCC_AUX17 VCCSM23 AL16
AK16 1 2
45mA
VCC_AUX18 VCCSM24
AE15 VCC_AUX19 VCCSM25 AJ16
J14 AN13 FB4 C99 C100 C101
VCC_AUX20 VCCSM26 C90 C91 C92 C93 100ohm@100MHz,3A 10uF/6.3V,X5R 10uF/6.3V,X5R 0.1uF/10V,X5R
J10 VCC_AUX21 VCCSM27 AM13
H10 AL13 1uF/10V,X7R 4.7uF/10V,Y5V 4.7uF/10V,Y5V 10uF/6.3V,X5R FB0805 C0805 C0805 C0402
VCC_AUX22 VCCSM28 C0603 C0805 C0805 C0805
AE9 VCC_AUX23 VCCSM29 AK13
AD9 VCC_AUX24 VCCSM30 AJ13
U9 VCC_AUX25 VCCSM31 AH13
AD8 VCC_AUX26 VCCSM32 AG13
C97 AD7 AF13 C98 FB5
0.47uF/25V,Y5V VCC_AUX27 VCCSM33 1uF/10V,X7R +V1.5S 100ohm@100MHz,3A +V1.5S_PCIE
AD6 VCC_AUX28 VCCSM34 AE13
C0603 C0603 FB0805
A14
VCCSM35 AN4
AM10 1 2
400mA
+V1.05S VTT0 VCCSM36 C102
D10 VTT1 VCCSM37 AL10
1uF/10V,X7R C156 C105 C106
780mA P9
L9
VTT2 VCCSM38 AK10
AH1 C0603 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R
VTT3 VCCSM39 C0805 C0805 C0805
D9 VTT4 VCCSM40 AH10
C477 C478 P8 AG10
4.7uF/10V,X5R 4.7uF/10V,X5R VTT5 VCCSM41
L8 VTT6 VCCSM42 AF10
C0805 C0805 D8 AE10
VTT7 VCCSM43 +V1.5S_3GPLL
P7 VTT8 VCCSM44 AN7
+V1.5S_MPLL
B
L7
D7
VTT9 VCCSM45 AM7
AL7 1 2
400mA B
VTT10 VCCSM46 +V1.5S_HPLL
A7 VTT11 VCCSM47 AK7
P6 AJ7 +V1.5S_DPLLA FB6
VTT12 VCCSM48 100ohm@100MHz,3A
L6 VTT13 VCCSM49 AH7
POWER
5
5
VSS110 U16
VSS109 AH16
VSS108 B17
VSS107 F17
VSS106 T17
VSS105 V17
VSS104 AK17
VSS103 D18
VSS102 H18
VSS101 U18
VSS100 AF18
VSS99 AH18
NC60 AM1 VSS98 AM18
NC59 AE4 VSS97 R19
NC58 AG4 VSS96 W19
NC57 AH4 VSS95 D20
NC56 AJ4 VSS94 AF20
AB17 MCH_RSVD42 NC55 W31 VSS93 AH20
AB12 MCH_RSVD41 NC54 AK4 VSS92 AK20
AB13 MCH_RSVD40 NC53 AL4 VSS91 AM20
AB15 MCH_RSVD39 NC52 AD4 VSS90 F21
AB18 MCH_RSVD38 NC51 AF4 VSS89 H21
AB20 MCH_RSVD37 NC50 AM4 VSS88 J21
AB24 MCH_RSVD36 NC49 Y7 VSS87 E22
AA24 MCH_RSVD35 NC48 A16 VSS86 G22
W24 MCH_RSVD34 NC47 AN2 VSS85 AF22
AA12 MCH_RSVD33 NC46 B16 VSS84 AJ22
AB14 MCH_RSVD32 NC45 C16 VSS83 AM22
AB16 MCH_RSVD31 NC44 D16 VSS82 B23
AB19 MCH_RSVD30 NC43 E16 VSS81 F23
AB21 MCH_RSVD29 NC42 F16 VSS80 H23
AB22 G16 A25
4
4
NC
NC29 VSS176 VSS67
NC28 AH19 B3 VSS175 VSS66 E27
NC27 AJ19 T3 VSS174 VSS65 G27
NC26 AK19 W3 VSS173 VSS64 M27
NC25 AL19 AD3 VSS172 VSS63 N27
NC24 AM19 AL3 VSS171 VSS62 P27
NC23 AN19 E4 VSS170 VSS61 R27
NC22 C23 H4 VSS169 VSS60 T27
NC21 E21 K4 VSS168 VSS59 U27
NC20 A31 N4 VSS167 VSS58 Y27
NC19 K33 R4 VSS166 VSS57 AA27
NC18 D24 V4 VSS165 VSS56 AB27
NC17 E24 AA4 VSS164 VSS55 AF27
NC16 F24 B5 VSS163 VSS54 AM27
NC15 G24 AJ5 VSS162 VSS53 D28
NC14 W32 AN5 VSS161 VSS52 J28
NC13 H24 K6 VSS160 VSS51 T28
VSS
3
3
Date:
U23E
945GMS
Page Name
Project Name
1
1
Sheet 13
TOPSTAR TECHNOLOGY
of 42
to others or used for any purpose other than that for which it was obtained without
PROPERTY NOTE: this document contains information confidential and property to
A
Rev
+V0.9S 34,37
+V1.8 10,12,34,36,37
DIM1
+V1.8 DDR2_SODIMM200
DDR200STD_5D2 SO-DIMM 0 +V3.3S 6,7,10,11,12,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39
+V1.8
112
111
117
118
103
104
187
178
190
155
132
144
156
168
149
161
138
150
162
96
95
81
82
87
88
21
33
34
15
27
39
28
40
9
2
3
11 MA_A_A[13:0]
C527 C121 C528
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
MA_DATA[63:0] 11
D 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R C122 C123 C124 D
MA_A_A0 102 5 MA_DATA0 C0805 C0805 C0805 0.1uF/10V,X5R 2.2uF/10V,X7R 2.2uF/10V,X7R
MA_A_A1 A0 D0 MA_DATA1 C0805 C0805
101 A1 D1 7 C0402
MA_A_A2 100 17 MA_DATA2
MA_A_A3 A2 D2 MA_DATA3
99 A3 D3 19
MA_A_A4
MA_A_A5
98
97
A4
A5
D4
D5
4
6
MA_DATA4
MA_DATA5 +V1.8 Layout note:电容靠近DDR slot VDD PIN
MA_A_A6 94 14 MA_DATA6
MA_A_A7 A6 D6 MA_DATA7
92 A7 D7 16
MA_A_A8 93 23 MA_DATA8
MA_A_A9 A8 D8 MA_DATA9 C125 C126 C127 C128 C129
91 A9 D9 25
MA_A_A10 105 35 MA_DATA10 0.1uF/10V,X5R 2.2uF/10V,X7R 0.1uF/10V,X5R 2.2uF/10V,X7R 0.1uF/10V,X5R
MA_A_A11 A10/AP D10 MA_DATA11 C0402 C0805 C0402 C0805 C0402
90 A11 D11 37
MA_A_A12 89 20 MA_DATA12
MA_A_A13 A12 D12 MA_DATA13
116 A13 D13 22
86 36 MA_DATA14
A14 D14 MA_DATA15 +V1.8
84 A15 D15 38
85 43 MA_DATA16
11 MA_A_BS#2 A16_BA2 D16
45 MA_DATA17
D17 MA_DATA18
11 MA_A_BS#0 107 BA0 D18 55
106 57 MA_DATA19 C130 C131 C132 C133 C134
11 MA_A_BS#1 BA1 D19
44 MA_DATA20 2.2uF/10V,X7R 0.1uF/10V,X5R 2.2uF/10V,X7R 0.1uF/10V,X5R 2.2uF/10V,X7R
D20 MA_DATA21 C0805 C0402 C0805 C0402 C0805
10 M_CS#0 110 CS0 D21 46
115 56 MA_DATA22
10 M_CS#1 CS1 D22 MA_DATA23
D23 58
MA_DM0 10 61 MA_DATA24
MA_DM1 DQM0 D24 MA_DATA25
26 DQM1 D25 63
MA_DM2 52 73 MA_DATA26
MA_DM3 DQM2 D26 MA_DATA27
67 DQM3 D27 75
C MA_DM4 130 62 MA_DATA28 C
MA_DM5 DQM4 D28 MA_DATA29
147 DQM5 D29 64
MA_DM6 170 74 MA_DATA30 +V0.9S
11 MA_DM[7:0] MA_DM7 DQM6 D30 MA_DATA31 RN1 56x4 RA0402_8
185 DQM7 D31 76
DDRII
123 MA_DATA32 1 2
D32 MA_DATA33 MA_A_A6
11 MA_A_WE# 109 WE D33 125 3 4
113 135 MA_DATA34 5 6 MA_A_A11
11 MA_A_CAS# CAS D34
108 137 MA_DATA35 7 8 MA_A_A7
11 MA_A_RAS# RAS D35
124 MA_DATA36
D36 MA_DATA37 RN2 56x4 RA0402_8
10 M_CKE0 79 CKE0 D37 126
80 134 MA_DATA38 1 2 MA_A_A12
10 M_CKE1 CKE1 D38 MA_DATA39
D39 136 3 4 MA_A_BS#2 11
30 141 MA_DATA40 5 6 MA_A_A9
10 M_CLK_DDR0 CK0 D40 MA_DATA41 MA_A_A8
10 M_CLK_DDR#0 32 CK0 D41 143 7 8
164 151 MA_DATA42
10 M_CLK_DDR1 CK1 D42 MA_DATA43 RN3 56x4 RA0402_8
10 M_CLK_DDR#1 166 CK1 D43 153
140 MA_DATA44 1 2
D44 MA_A_WE# 11
114 142 MA_DATA45 3 4
10 M_ODT0 ODT0 D45 MA_A_BS#1 11
119 152 MA_DATA46 5 6 MA_A_A13
10 M_ODT1 ODT1 D46
154 MA_DATA47 7 8
D47 MA_A_CAS# 11
MA_DQS0 13 157 MA_DATA48
MA_DQS1 DQS0 D48 MA_DATA49 RN4 56x4 RA0402_8
31 DQS1 D49 159
MA_DQS2 51 173 MA_DATA50 1 2 MA_A_A3
MA_DQS3 DQS2 D50 MA_DATA51 MA_A_A1
70 DQS3 D51 175 3 4
MA_DQS4 131 158 MA_DATA52 5 6 MA_A_A10
MA_DQS5 DQS4 D52 MA_DATA53 MA_A_A5
148 DQS5 D53 160 7 8
MA_DQS6 169 174 MA_DATA54
11 MA_DQS[7:0] MA_DQS7 DQS6 D54 MA_DATA55 RN5 56x4 RA0402_8
188 DQS7 D55 176
179 MA_DATA56 1 2
B D56 MA_A_RAS# 11 B
181 MA_DATA57 3 4 MA_A_A0
D57 MA_DATA58 MA_A_A2
6,19,23,24 SMB_DATA_S 195 SDA D58 189 5 6
197 191 MA_DATA59 7 8 MA_A_A4
6,19,23,24 SMB_CLK_S SCL D59 MA_DATA60
D60 180
R145 10K R0402 198 182 MA_DATA61
R146 10K R0402 SA0 D61 MA_DATA62 R149 56 R0402
+V3.3S
200 SA1 1010 000x D62 192
MA_DATA63 R148 56 R0402
M_CS#1 10
D63 194 M_ODT1 10
R152 56 R0402
M_CKE0 10
199 11 MA_DQS#0 R154 56 R0402
VDDSPD DQS#0 M_CKE1 10
29 MA_DQS#1 R155 56 R0402
DQS#1 MA_A_BS#0 11
1 49 MA_DQS#2 R157 56 R0402
10,34 SM_VREF_L VREF1 DQS#2 M_ODT0 10
C136 68 MA_DQS#3 R159 56 R0402
DQS#3 M_CS#0 10
C137 129 MA_DQS#4
0.1uF/25V,Y5V 2.2UF/10V,X7R C135 C138 DQS#4 MA_DQS#5
83 NC1 DQS#5 146
C0402 C0805 2.2UF/10V,X7R 120 167 MA_DQS#6
0.1uF/25V,Y5V NC2 DQS#6 MA_DQS#7
50 NC3 DQS#7 186
C0402 C0805 69
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
NC4 MA_DQS#[7:0] 11
GND0
GND1
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
163 NCTEST
close to DDR pin
47
133
183
77
12
48
184
78
71
72
121
122
196
193
8
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
201
202
10 PM_EXTTS#0
A
+V0.9S 每4个电阻两个0.1UF电容 TOPSTAR TECHNOLOGY
A
Swain Xu
Page Name DDRII SODIMM0
C139 C140 C141 C142 C143 C144 C145 C146 C147 C148 C149 C150 C151
Size Project Name Rev
0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R
A3 N01
C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 A
Date: Wednesday, July 16, 2008 Sheet 14 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
+V3.3AL 17,18,19,20,23,24,25,27,29,30,31,32,33,34,35,36,37,39
+V3.3S 6,7,10,11,12,14,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39
+V5AL 20,22,25,33,34,36,37
+VDC 23,25,31,33,34,35,37,39
+V5S 16,19,20,21,25,26,27,29,35,37,38,39
LCDVDD C0402 39 40
39 40
S
C R162 500mA 42 42
C
100K C153
D
R0402 0.047uF/16V,X7R
G
ns
SPWG Require LCDVDD rising time
3
3
2N7002 2N7002 100K
is 0.5-10ms,1-10ms is better SOT23 ns SOT23 ns
1 Q3
10 LVDS_VDDEN
2N7002E-T1 LVDS_VDDEN 1
100pF/50V,NPO
1
SOT23
2
2
100K 100K
R0402 ns ns +V5AL
R712 0 R0805
+V5AL_CAM
2 3
500mA
R204
10K Q15 C313 C296
R0402 SOT23 0.1uF/10V,X5R 10UF/6.3V,X5R
ns AO3415 C0402 C0805
1
B ns B
R730 10K
R0402
29 EC_BKLT_PWM R696 0 R0402 ns ns
3
R697 0 R0402 BKLT_PWM
10 LVDS_BKLTCTL
R168 C158 1
10K 100pF/50V,NPO 29 CAM_PWRON
R0402 C0402 Q16
2
R213 2N7002E-T1
100K SOT23
R0402 ns
ns
C182
100pF/50V,NPO
C0402
A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name
LVDS
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 15 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
+V5S 15,19,20,21,25,26,27,29,35,37,38,39
+V3.3S 6,7,10,11,12,14,15,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39
3
C0402 R0402
17
R172 C164 C162 D7
150,1% BAT54S
R0402 5.6pF/50V NPO 5.6pF/50V NPO SOT23 GND_VGA GND_VGA 6 GND
CONNECTOR TOP VIEW
C0402 C0402 ROUT 1 R NC
11
7 GND
2
GOUT SDA 5VDDCDA
2 G 12
FB13 GND_VGA 8 GND
47ohm@100MHz,500mA GND_VGA+V5_VGA BOUT 3 B HSYNC 13 HSYNC
10 CRT_GREEN 1FB0603 2 GOUT 9 NC
4 NC VSYNC 14 VSYNC
3
10 GND
R173 GND CLK 5VDDCCK
C165 C166 5 15
150,1% D8 shell
R0402 5.6pF/50V NPO 5.6pF/50V NPO BAT54S shell
C0402 C0402 SOT23 D-Sub
VGADMA
16
C167 C168 C169 C170
2
15PF/50V,NPO 15PF/50V,NPO 15PF/50V,NPO 15PF/50V,NPO
GND_VGA C0402 C0402 C0402 C0402
C GND_VGA+V5_VGA ns ns C
3
GND_VGA
R174 C171 C172 +V3.3S GND_VGA
150,1% D9
R0402 5.6pF/50V NPO 5.6pF/50V NPO BAT54S
C0402 C0402 SOT23 C173
0.1uF/10V,X5R
1
2
C0402
GND_VGA
150ohm电阻前 +V5_VGA
走线阻抗50ohm GND_VGA
GND_VGA
+V3.3S +V5_VGA
+V5_VGA
R175 R176
2.2K Q5 2.2K
R0402 BSS138 R0402
3
C0402 C0402
U6
1 5 +V3.3S D26
1
OE# VCC +V3.3S +V5_VGA BAT54S
B SOT23 B
10 CRT_HSYNC 2 A GND_VGA
2
3 GND Y 4
R179 R177
74AHCT1G125 Near U11/U12 ASAP 2.2K Q6 2.2K +V5_VGA
SOT23_5 R0402 BSS138 R0402 GND_VGA
U7 R178 39 R0402 HSYNC 5VDDCDA
10 CRT_DDC_DATA 2 3
1 OE# VCC 5
3
R180 39 R0402 VSYNC
10 CRT_VSYNC 2 A +V3.3S D27
1
3 4 BAT54S
GND Y SOT23
74AHCT1G125
2
SOT23_5
GND_VGA +V5_VGA
GND_VGA
R731
+V5_VGA 0
+V5_VGA R0805
D10 R732
D11 0
2
C176 2 R0805
HSYNC 3 0.1uF/10V,X5R
A
C0402 VSYNC 3 C177 A
1 0.1uF/10V,X5R TOPSTAR TECHNOLOGY
1 C0402
GND_VGA Swain Xu
BAT54S Page Name CRT CONN & S TV OUT & LIDR SWITCH
SOT23 GND_VGA BAT54S
SOT23 GND_VGA Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 16 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
1
ns
3
C180 J1
R185 1uF/10V,X7R JOPEN C181 U24A R187 R196
1
3
2
RTCX2 LAD1
AC4 LPC_AD2 23,29
4
RTC_RST# LAD2
AA3 RTCRST# LAD3 Y6 LPC_AD3 23,29
LPC
RTC
SM_INTRUDER# Y5 AC3
ICH_INTVRMEN INTRUDER# LDRQ0#
W4 INTVRMEN LDRQ1#/GPIO23 AA5
LAN
CPU
C ns LAN_RXD0 C
V4 LAN_RXD1 FERR# AG26 H_FERR# 7
T5 LAN_RXD2
AG24 +V3.3S
+ U7
GPIO49/CPUPWRGD H_PWRGD 7
R201
LAN_TXD0
- V6 LAN_TXD1
56
RTC_BAT1 V7 AG22 R0402
LAN_TXD2 IGNNE# H_IGNNE# 7
RTCBAT with Cable AG21 R192
ns R193 39 R0402 INIT3_3V# 10K
26 HDA_BITCLK U1 ACZ_BIT_CLK INIT# AF22 H_INIT# 7
R203 39 R0402 R6 AF25 R0402
26 HDA_SYNC ACZ_SYNC INTR H_INTR 7
根据机构 +V1.05S
AC-97/AZALIA
+V3.3S R195 39 R0402 R5 AG23
26 HDA_RST# H_RCIN# 29
定Cable尺寸 ACZ_RST# RCIN#
SATA
R211 24.9,1% R0402 DD12
AH10 SATARBIASN DD13 AH13
within 500 mils AG10 AH14
of the ICH7-M SATARBIASP DD14
DD15 AC15
+V3.3S
AF15
AH15
DIOR# IDE DA0 AH17
AE17
DIOW# DA1
AF16 DDACK# DA2 AF17
R194 10K R0402 AH16
R205 10K R0402 IDEIRQ
AG16 IORDY DCS1# AE16
AE15 DDREQ DCS3# AD16
ICH7M
A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name ICH7_M(1 of 4)
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 17 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
+V1.5S_PCIE_ICH 20
+V3.3S 6,7,10,11,12,14,15,16,17,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39
+V3.3AL 15,17,19,20,23,24,25,27,29,30,31,32,33,34,35,36,37,39
D D
RN22
10K +V3.3S
RA0402_8
U24B PCI_STOP# 1 2
E18 D7 PCI_REQ#0 PCI_REQ#1 3 4 U24D
AD0 REQ0# PCI_REQ#2
C18
A16
AD1 PCI GNT0# E7
C16 PCI_REQ#1 PCI_FRAME#
5
7
6
8
30 PCIE_RXN0_LAN F26
F25
PERn1 DMI0RXN V26
V25
DMI_RXN0 10
AD2 REQ1# 30 PCIE_RXP0_LAN PERp1 DMI0RXP DMI_RXP0 10
C184 0.1UF/10V,X7R C0402 E28
PCI-Express
D14 D8 PCI_GNT#5 PCI_TRDY# 7 8 K26 AB26
AD11 GNT5#/GPIO17 24 PCIE_RXN2_SLOT PERn3 DMI2RXN
B12 AD12 24 PCIE_RXP2_SLOT K25 PERp3 DMI2RXP AB25
C13 B15 C225 0.1UF/10V,X7R C0402 J28 AA28
AD13 C/BE0# 24 PCIE_TXN2_SLOT PETn3 DMI2TXN
G15 C12 R226 R227 R280 R228 RN23 C226 0.1UF/10V,X7R C0402 J27 AA27
AD14 C/BE1# BIOS strap pin 24 PCIE_TXP2_SLOT PETp3 DMI2TXP
G13 D12 1K 1K 1K 1K 10K +V3.3S
AD15 C/BE2# R0402 R0402 R0402 R0402 RA0402_8 +V1.5S_PCIE_ICH
E12 AD16 C/BE3# C15 M26 PERn4 DMI3RXN AD25
C11 ns ns ns 1 2 M25 AD24
AD17 PCI_IRDY# INT_PIRQB# Place AC coupling caps PERp4 DMI3RXP Place within 500
D11 AD18 IRDY# A7 3 4 L28 PETn4 DMI3TXN AC28
A11 E10 INT_PIRQC# 5 6 need to be within L27 AC27 mils of ICH
AD19 PAR INT_PIRQD# 250mils of the driver. PETp4 DMI3TXP
A10 AD20 PCIRST# B18 7 8
F11 A12 PCI_DEVSEL# P26 AE28
AD21 DEVSEL# PERn5 DMI_CLKN CLK_PCIE_ICH# 6
C F10 C9 PCI_PERR# P25 AE27 C
AD22 PERR# PERp5 DMI_CLKP CLK_PCIE_ICH 6
E9 E11 PCI_LOCK# RA0402_8 N28
AD23 PLOCK# PCI_SERR# 10K +V3.3S PETn5
D9 AD24 SERR# B10 N27 PETp5 DMI_ZCOMP C25
B9 F15 PCI_STOP# RN19 D25 DMI_IRCOMP_RR240 24.9,1% R0402
AD25 STOP# PCI_TRDY# PCI_LOCK# DMI_IRCOMP
A8 AD26 TRDY# F14 7 8 T25 PERn6
A6 F16 PCI_FRAME# PCI_SERR# 5 6 T24 F1
AD27 FRAME# PERp6 USBP0N USB_PORT_PN1 25
C7 INT_PIRQG# 3 4 R28 F2
AD28 PETn6 USBP0P USB_PORT_PP1 25
B6 C26 PLT_RST# PCI_PERR# 1 2 R27 G4
AD29 PLTRST# PETp6 USBP1N USB_PORT_PN0 25
E6 AD30 PCICLK A9 PCI_CLK_ICH 6 USBP1P G3 USB_PORT_PP0 25
D6 B19 SPI_SCK_ICH R2 H1
AD31 PME# SPI_CLK USBP2N USB_PORT_PN2 25
RN20 SPI_CE#_ICH P6 H2
SPI_CS# USBP2P USB_PORT_PP2 25
10K +V3.3S
Interrupt I/F P1 SPI_ARB USBP3N J4 MINICARD_USB_PN3 24
SPI
INT_PIRQA# A3 G8 INT_PIRQE# RA0402_8 J3 MINICARD_USB_PP3 24
INT_PIRQB# PIRQA# GPIO2/PIRQE# INT_PIRQF# INT_PIRQH# SPI_SI_ICH USBP3P
B4 PIRQB# GPIO3/PIRQF# F7 1 2 P5 SPI_MOSI USBP4N K1
INT_PIRQC# C5 F8 INT_PIRQG# INT_PIRQE# 3 4 SPI_SO_ICH P2 K2 USB_CAM_PN5 15
PIRQC# GPIO4/PIRQG# SPI_MISO USBP4P USB_CAM_PP5 15
USB
INT_PIRQD# B5 G7 INT_PIRQH# PCI_IRDY# 5 6 L4 MINICARD_USB_PN4 23
PIRQD# GPIO5/PIRQH# PCI_REQ#5 USBP5N
7 8 25 USB_PORT_OC1# D3 OC0# USBP5P L5 MINICARD_USB_PP4 23
AE5
MISC AE9
25 USB_PORT_OC0# C4
D5
OC1# USBP6N M1
M2 USB_CR_PN6 22
RSVD[1] RSVD[6] RN24 OC2# USBP6P USB_CR_PP6 22
AD5 RSVD[2] RSVD[7] AG8 D4 OC3# USBP7N N4
AG4 AH8 10K +V3.3S R455 E5 N3
RSVD[3] RSVD[8] T33 ICTPns RA0402_8 10K OC4# USBP7P
AH4 RSVD[4] TP3 F21 C3 OC5#/GPIO29
AD9 AH20 1 2 R0402 A2 D2
RSVD[5] MCH_SYNC# MCH_ICH_SYNC# 10 OC6#/GPIO30 USBRBIAS#
INT_PIRQF# 3 4 +V3.3AL B3 D1 USB_RBIAS_PN R245 22.6,1% R0402
ICH7M INT_PIRQA# OC7#/GPIO31 USBRBIAS
5 6
PCI_REQ#0 7 8 ICH7M Place within 500
mils of ICH
B B
+V3.3AL R238
+V3.3AL 10K
R0402
C188
0.1uF/10V,X5R U9
C0402 W25X40
SO8_50_150 ns
5
+V3.3S 6,7,10,11,12,14,15,16,17,18,20,21,23,24,25,26,27,28,29,30,35,36,37,39
+V3.3AL 15,17,18,20,23,24,25,27,29,30,31,32,33,34,35,36,37,39
+V5S 15,16,20,21,25,26,27,29,35,37,38,39
+V3.3AL +V3.3S
1
SMB_CLK 3 2 SMB_CLK_S 6,14,23,24
R246 R247 R248 R249
8.2K 8.2K 8.2K 8.2K
R0402 R0402 R0402 R0402
1
U24C
SMB_CLK C22 AF19 +V3.3AL
SMB_DATA SMBCLK GPIO21/SATA0GP
B22 SMBDATA GPIO19/SATA1GP AH18
SMB_LINK_ALERT# A26 AH19
SATA
SMB
GPIO
+V5S SMLINK0 LINKALERT# GPIO36/SATA2GP PC_BEEP R250 1K ns R0402
B25 SMLINK0 GPIO37/SATA3GP AE19
SMLINK1 A25 SMLINK1 PM_RI# R251 10K R0402
CLK14 AC1 CLK_ICH14 6
PM_RI# A28 B2
Clocks
RI# CLK48 CLK_USB48 6
SMB_ALERT# R252 10K R0402
A19 C20 ICH_SUSCLK T24 ICTPns
26 PC_BEEP SPKR SUSCLK
A27 SMB_LINK_ALERT# R253 10K R0402
15,29 PM_SUS_STAT# SUS_STAT#
7 PM_SYSRST# A22 SYS_RST# SLP_S3# B24 PM_SLP_S3# 29,36
C D23 SMLINK0 R254 10K R0402 C
SLP_S4# PM_SLP_S4# 29,37
AB18 F22 PM_SLP_S5# T30 ICTPns
10 PM_BMBUSY# GPIO0/BM_BUSY# SLP_S5# SMLINK1 R255 10K R0402
SMB_ALERT# B23 AA4 PM_ICH_PWROK
GPIO11/SMBALERT# PWROK PM_SLP_S3# R257 10K R0402
PM_STPPCI# AC20 AC22
Power MGT
6 PM_STP_PCI# GPIO18/STPPCI# GPIO16/DPRSLPVR PM_DPRSLPVR 10
PM_STPCPU# AF21 PM_BATLOW# R258 8.2K R0402
6 PM_STP_CPU# GPIO20/STPCPU#
+V3.3S C21 PM_BATLOW#
GPIO
TP0/BATLOW# PM_SYSRST# R260 10K R0402
A21
SYS
GPIO26
PWRBTN# C23 PM_PWRBTN# 29
B21 PCIE_WAKE# R264 1K R0402
R256 GPIO27
E23 GPIO28
10K C19 R293 0 R0402 PM_CLKRUN# R301 10K R0402
LAN_RST# BUF_PLT_RST# 10,18,23,24,29,30
R0402 AG18
29 PM_CLKRUN# GPIO32/CLKRUN#
RSMRST# Y4 PM_RSMRST# 29,36
VR_PWRGD_CLK_EN 6 AC19 GPIO33/AZ_DOCK_EN#
U2 GPIO34/AZ_DOCK_RST# GPIO9 E20
3
VRMPWRGD GPIO24
GPIO25 D20
AC21 GPIO6 GPIO35 AD21
29 EC_RUNTIME_SCI# AC18
E21
GPIO7 GPIO GPIO38 AD20
AE20
29 EXT_SMI# GPIO8 GPIO39
ICH7M
B B
+V3.3AL PM_RSMRST#
3
R389 100K 1 Q25
+V3.3S 2N2222
ns SOT23
2
ns
EC_PWROFF# 29
R298 10K R0402 EC_RUNTIME_SCI#
A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name ICH7_M(2 of 3)
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 19 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
1
B26 VSS[9] VSS[106] R17
100 SOD323 within 100mils of U24F
R0402 ICH7M PIN AD17
6mA G10 L11
860mA B28
C2
VSS[10] VSS[107] R18
T6
V5REF[1] Vcc1_05[1] VSS[11] VSS[108]
Vcc1_05[2] L12 C6 VSS[12] VSS[109] T12
AD17 L14 C189 C190 C223 C224 C27 T13
V5REF[2] Vcc1_05[3] VSS[13] VSS[110]
1
D L16 0.1UF/10V,X7R 1UF/10V,X7R 10UF/6.3V,X5R 10UF/6.3V,X5R D10 T14 D
C204 Vcc1_05[4] C0402 C0603 C0805 C0805 VSS[14] VSS[111]
F6 L17 + C524 D13 T15
1
1uF/10V,X7R V5REF_Sus Vcc1_05[5] 220UF/6.3V,OSCON VSS[15] VSS[112]
Vcc1_05[6] L18 D18 VSS[16] VSS[113] T16
C0603 +V5AL +V3.3AL AA22 M11 CAP6_6x7_3 D21 T17
2
Vcc1_5_B[1] Vcc1_05[7] VSS[17] VSS[114]
AA23 Vcc1_5_B[2] Vcc1_05[8] M18 D24 VSS[18] VSS[115] U4
AB22 P11 E1 U12
CORE
D14 Vcc1_5_B[3] Vcc1_05[9] ns VSS[19] VSS[116]
AB23 Vcc1_5_B[4] Vcc1_05[10] P18 E2 VSS[20] VSS[117] U13
Layout note: R275 1N4148WS
1
AC23 Vcc1_5_B[5] Vcc1_05[11] T11 E4 VSS[21] VSS[118] U14
0.1uF needs be placed 10 SOD323 AC24 T18 +V3.3S E8 U15
R0402 Vcc1_5_B[6] Vcc1_05[12] VSS[22] VSS[119]
within 100mils of pin AC25 U11 E15 U16
Place above cap Vcc1_5_B[7] Vcc1_05[13] VSS[23] VSS[120]
F6 of ICH7M AC26 Vcc1_5_B[8] Vcc1_05[14] U18 F3 VSS[24] VSS[121] U17
with 100milof
10mA ICH on the
AD26
AD27
Vcc1_5_B[9] Vcc1_05[15] V11
V12
F4
F5
VSS[25] VSS[122] U24
U25
bottom or 140 Vcc1_5_B[10] Vcc1_05[16] C192 VSS[26] VSS[123]
AD28 Vcc1_5_B[11] Vcc1_05[17] V14 F12 VSS[27] VSS[124] U26
mil on the top 0.1UF/10V,X7R
D26 Vcc1_5_B[12] Vcc1_05[18] V16 F27 VSS[28] VSS[125] V2
C191 near D28 T28 C0402
AD28 D27 Vcc1_5_B[13] Vcc1_05[19] V17 F28 VSS[29] VSS[126] V13
0.1uF/10V,X5R D28 V18 G1 V15
C0402 Vcc1_5_B[14] VCC PAUX Vcc1_05[20] +V3.3S +V3.3AL VSS[30] VSS[127]
E24
E25
Vcc1_5_B[15]
V5
30mA G2
G5
VSS[31] VSS[128] V24
V27
+V1.5S Vcc1_5_B[16] VccSus3_3/VccLAN3_3[1] VSS[32] VSS[129]
100 OHM@100MHz BEAD E26 Vcc1_5_B[17] VccSus3_3/VccLAN3_3[2] V1 G6 VSS[33] VSS[130] V28
+V1.5S_PCIE_ICH F23 W2 G9 W6
IN INTEL DEMO CIRCUIT Vcc1_5_B[18] VccSus3_3/VccLAN3_3[3] VSS[34] VSS[131]
FB15 0 R0805
770mA F24 Vcc1_5_B[19] VccSus3_3/VccLAN3_3[4] W7
C193 C194
G14 VSS[35] VSS[132] W24
G22
G23
Vcc1_5_B[20]
U6
50mA 0.1UF/10V,X7R 0.1UF/10V,X7R
G18
G21
VSS[36] VSS[133] W25
W26
C523 C525 C526 C195 C197 Vcc1_5_B[21] Vcc3_3/VccHDA C0402 C0402 VSS[37] VSS[134]
10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 0.1UF/10V,X7R C196
H22
0.1UF/10V,X7R H23 Vcc1_5_B[22]
R7
10mA +V1.05S
G24
G25
VSS[38] VSS[135] Y3
Y24
C0805 C0805 C0805 C0402 0.1UF/10V,X7R C0402 Vcc1_5_B[23] VccSus3_3/VccSusHDA VSS[39] VSS[136]
C0402
J22
J23
Vcc1_5_B[24]
AE23
14mA G26
H3
VSS[40] VSS[137] Y27
Y28
Vcc1_5_B[25] V_CPU_IO[1] VSS[41] VSS[138]
K22 Vcc1_5_B[26] V_CPU_IO[2] AE26 H4 VSS[42] VSS[139] AA1
C K23 AH26 +V3.3S Place within 100 H5 AA24 C
VCCA3GP
Vcc1_5_B[27] V_CPU_IO[3] C199 VSS[43] VSS[140]
IDE
mils on the C198 C205
L22
L23
Vcc1_5_B[28]
AA7
330mA bottom or 140 mil 0.1UF/10V,X7R 0.1UF/10V,X7R 4.7UF/10V,Y5V
H24
H27
VSS[44] VSS[141] AA25
AA26
Vcc1_5_B[29] Vcc3_3[3] on the top of ICH C0402 C0402 C0805 VSS[45] VSS[142]
M22 Vcc1_5_B[30] Vcc3_3[4] AB12 H28 VSS[46] VSS[143] AB4
M23 Vcc1_5_B[31] Vcc3_3[5] AB20 J1 VSS[47] VSS[144] AB6
N22 AC16 C200 J2 AB11
Vcc1_5_B[32] Vcc3_3[6] 0.1UF/10V,X7R VSS[48] VSS[145]
N23 Vcc1_5_B[33] Vcc3_3[7] AD13 J5 VSS[49] VSS[146] AB14
C0402 +V3.3S
IDE
P22 Vcc1_5_B[34] Vcc3_3[8] AD18 J24 VSS[50] VSS[147] AB16
P23 Vcc1_5_B[35] Vcc3_3[9] AG12 J25 VSS[51] VSS[148] AB19
R22 Vcc1_5_B[36] Vcc3_3[10] AG15 J26 VSS[52] VSS[149] AB21
R23 Vcc1_5_B[37] Vcc3_3[11] AG19 K24 VSS[53] VSS[150] AB24
PCI
Place within 100
R24
R25
Vcc1_5_B[38]
A5
330mA C201 C202 C203
K27
K28
VSS[54] VSS[151] AB27
AB28
mils on the Vcc1_5_B[39] Vcc3_3[12] 0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R VSS[55] VSS[152]
R26 Vcc1_5_B[40] Vcc3_3[13] B13 L13 VSS[56] VSS[153] AC2
+V1.5S bottom or 140 mil T22 B16 C0402 C0402 C0402 L15 AC5
on the top of ICH +V3.3S Vcc1_5_B[41] Vcc3_3[14] VSS[57] VSS[154]
T23 Vcc1_5_B[42] Vcc3_3[15] B7 L24 VSS[58] VSS[155] AC9
FB16 0 R0805 T26 C10 +V3.3A_RTC L25 AC11
Vcc1_5_B[43] Vcc3_3[16] VSS[59] VSS[156]
PCI
270mA T27
T28
Vcc1_5_B[44] Vcc3_3[17] D15
F9
L26
M3
VSS[60] VSS[157] AD1
AD3
Vcc1_5_B[45] Vcc3_3[18] VSS[61] VSS[158]
U22 Vcc1_5_B[46] Vcc3_3[19] G11 M4 VSS[62] VSS[159] AD4
C207 U23 G12 C209 C210 M5 AD7
0.01uF/25V,X7R Vcc1_5_B[47] Vcc3_3[20] 0.1UF/10V,X7R 0.1UF/10V,X7R VSS[63] VSS[160]
V22 Vcc1_5_B[48] Vcc3_3[21] G16 M12 VSS[64] VSS[161] AD8
C206 C0402 C208 C0402 C0402
10UF/6.3V,X5R 0.1UF/10V,X7R
V23
W22
Vcc1_5_B[49]
W5
6uA M13
M14
VSS[65] VSS[162] AD11
AD15
C0805 C0402 Vcc1_5_B[50] VccRTC +V3.3AL VSS[66] VSS[163]
W23 Vcc1_5_B[51] M15 VSS[67] VSS[164] AD19
Y22
Y23
Vcc1_5_B[52] VccSus3_3[1] P7 52mA M16
M17
VSS[68] VSS[165] AD23
AE2
Vcc1_5_B[53] VSS[69] VSS[166]
VccSus3_3[2] A24 M24 VSS[70] VSS[167] AE4
+V1.5S B27 C24 C211 C212 M27 AE8
B Vcc3_3[1] VccSus3_3[3] 0.1UF/10V,X7R 0.1UF/10V,X7R VSS[71] VSS[168] B
50mA AG28
VccSus3_3[4] D19
D22 C0402 C0402
M28
N1
VSS[72] VSS[169] AE11
AE13
Place within 100 +V1.5S VccDMIPLL VccSus3_3[5] +V3.3AL VSS[73] VSS[170]
VccSus3_3[6] G19 N2 VSS[74] VSS[171] AE18
mils on the Place within 100
bottom or 140 mil C213 mils on the 1.01A AB7
AC6
Vcc1_5_A[1]
K3
52mA N5
N6
VSS[75] VSS[172] AE21
AE24
on the top of ICH 0.1UF/10V,X7Rbottom or 140 mil Vcc1_5_A[2] VccSus3_3[7] VSS[76] VSS[173]
AC7 Vcc1_5_A[3] VccSus3_3[8] K4 N11 VSS[77] VSS[174] AE25
C0402 on the top of ICH AD6 K5 N12 AF2
near AG5 Vcc1_5_A[4] VccSus3_3[9] VSS[78] VSS[175]
ARX
+V5S 15,16,19,20,25,26,27,29,35,37,38,39
+V3.3S 6,7,10,11,12,14,15,16,17,18,19,20,23,24,25,26,27,28,29,30,35,36,37,39
D D
SATA HDD
+V5S V_HDD
SATA_HDD
FB32 0 R0805 Close to connector as possible SATA_HDD CONN
the same distance to connector SATA_S_50E
C444 C301 C300 P2
17 SATA_TXP0 TX
4.7uF/10V,Y5V 0.1uF/25V,Y5V 0.1uF/25V,Y5V P3 P1
17 SATA_TXN0 TX# GND0
C0805 C0402 C0402 C508 3300pF/50V,X7RC0402 P5 P4
17 SATA_RXN0 RX# GND1
C507 3300pF/50V,X7RC0402 P6 P7
17 SATA_RXP0 RX GND2
B B
TOPSTAR TECHNOLOGY
Swain Xu
Page Name SATA HDD
A A
Size Project Name Rev
A4 N01
A
Date: Wednesday, July 16, 2008 Sheet 21 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
+V5AL 15,20,25,33,34,36,37
FB19
VCC3V 600ohm@100MHz,1.5A
FB0805
VCC3VA
D D
C230 C231 C232 CFD2/SMD2/SDD2
0.1UF/25V,Y5V 4.7UF/10V,Y5V 0.1UF/25V,Y5V CFD3/SMD3/SDD3
C0402 C0805 C0402
OLD 3IN1 CONN.
VCC3V
MSD1 MSINS
VREF
MSCLK1 CFD1/SMD1/SDD1
CFA0/SMALE/MSBS CFD0/SMD0/SDD0 J6A
R278 CFD2/SMD2/SDD2 2
0 CFD3/SMD3/SDD3 DAT2_SD CARD_3V3
3 DAT3_SD VDD_SD 6
R0603 U25 CFA1/SMCLE/SDCMD 4
VCC18 UB6232 CMD_SD
48
47
46
45
44
43
42
41
40
39
38
37
QFPS48_0D5_1D6 SDCLK 7 SD+MMC C516
CLK_SD 0.1uF/10V,X7R
SMALE/MSBS
MSCLK
VREF
MSINSZ
MSD1
SMREZ/MMCD4
SMD3/SDD3
SMD2/SDD2
GND_4
VCC33_3
SMD1/SDD1
SMD0/SDD0
CFD0/SMD0/SDD0 9 8
C236 C237 CFD1/SMD1/SDD1 DAT0_SD VSS_SD2
10 DAT1_SD
0.1UF/25V,Y5V 4.7UF/10V,Y5V SDCD# 1 5 C517
C0402 C0805 EROM15/SDWPD CD_SD# VSS_SD1 1uF/10V,X7R
11 WP_SD#
CFD4/SMD4/MSD0 1 C0603
SMD4/MSD0 CFD6/SMD6/MSD2 3IN1
2 SMD5/MMCD6 SMD6/MSD2 36
SDCLK 3 35 CFD7/SMD7/MSD3
SDCLK SMD7/MSD3 CFA1/SMCLE/SDCMD J6B
4 SMWEZ/MMCD5 SMCLE/SDCMD 34
5 33 VCC3V MSCLK1 14 13 CARD_3V3
VREF GND_1 VCC33_2 SDCD# CLK_MS VCC_MS
6 SMCDZ SDCDZ 32
VCC3V 7 31 CFD7/SMD7/MSD3 15
C229 CARD_3V3 8
VCC33_1 GND_3
30 EROM15/SDWPD MSINS 16
DAT3_MS MS
0.1UF/25V,Y5V VBUS_5V VCC18 CRDVCC SDWPD CFD6/SMD6/MSD2 INS_MS
9 29 17 12
LEDZ/TESTEN/UATX
C0402 VCC3V REG18_O SMWPZ VCC18 CFD4/SMD4/MSD0 DTA2_MS VSS_MS1
10 REG33_O VCC18 28 18 DTA0_MS VSS_MS2 21
VCC5V MSD1
SMWPDZ/TEST0
11 VBUS SMBSYZ/MMCD7 27 19 DTA1_MS GND1 22
12 26 CFA0/SMALE/MSBS 20 23
C C234 GND_2 SDA/TEST3/UARX BS_MS GND2 C
SCL/TESTINTR 25
VCC33A_1
VCC33A_2
10uF/10V,Y5V C235 3IN1 C518 C519
GNDA_1
GNDA_2
C1206 0.1UF/25V,Y5V 0.1uF/10V,X7R 1uF/10V,X7R
SMCEZ
REXT
CARD_3V3 ns C0402 C0603
DM
XO
DP
XI
C233
13
14
15
16
17
18
19
20
21
22
23
24
1uF/25V,Y5V
C0805
XI
USB_CR_PP6 18
VCC3VA
USB_CR_PN6 18
VCC3VA
REXT
R282
0 Y3
R0402 12.000MHz
+V5AL R279 VBUS_5V XS2
0 1 2 XO R281
R0805 12.1K,1%
R0402
C238 C239
27pF/50V,NPO27pF/50V,NPO
C0402 C0402
PWR SW
4
5
6
S
R735 0 R0805 Q27
CR_Nops +V5AL AO6409 VBUS_5V
D
TSOP6_0D95_1D6
G
CR_PS
3
2
1
B SDCD_D# B
1
D37
SDCD# 3 BAT54C
SOT23 R736 C531 C532
2 4.7K C0402 C0402
CR_PS R0402 0.01uF/25V,X7R 0.01uF/25V,X7R
CR_PS CR_PS CR_PS
R737
2
D38
MSINS 3 BAT54C
SOT23 100K
1 MSINS_D# R0402
CR_PS CR_PS
R738 0 R0805
CR_Nops
A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name Card Reader(UB6232 USB)
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 22 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
+V3.3S 6,7,10,11,12,14,15,16,17,18,19,20,21,24,25,26,27,28,29,30,35,36,37,39
+V3.3AL 15,17,18,19,20,24,25,27,29,30,31,32,33,34,35,36,37,39
+V1.5S 8,10,11,12,20,24,35,36,37
+VDC 15,25,31,33,34,35,37,39
+DATA4
D -DATA4 D
+V3.3AL
1
D15 D16 +V3.3S PCIE_NUT1
ESDPAD_R0603 ESDPAD_R0603 Hole+Dowel
EGA1-0603-V05 EGA1-0603-V05 TH_200_132_112
ns ns R283
2
0 R284 R285
R0603 0 0 +V1.5S
ns R0603 R0603
+V3.3S_PCIE +V3.3AL_PCIE
1
MPCIE1
MINIPCIE_TEMP1
52
24
48
28
2
6
Keep USB2.0 Signal stub short
+3.3VAUX
+3.3V0
+3.3V1
+1.5V0
+1.5V1
+1.5V2
R288 0 R0402 +V3.3S +V3.3AL
R289 0 R0402
CHK1
90ohm@100MHz,0.5A
L4_0805 ns ICTP R286 R287
3 4 -DATA4 36 46 ns 10K 10K
18 MINICARD_USB_PN4 USB_D- LED_WPAN# T31
2 1 +DATA4 38 44 R0402 R0402
18 MINICARD_USB_PP4 USB_D+ LED_WLAN# Wireless_LED# 27
42 ns ns
T32
18 PCIE_TXN1_SLOT 31 PETN0
33 32 R292 0 R0402 ns
18 PCIE_TXP1_SLOT PETP0 SMB_DATA SMB_DATA_S 6,14,19,24
30 R291 0 R0402 ns
SMB_CLK +V3.3AL SMB_CLK_S 6,14,19,24
18 PCIE_RXN1_SLOT 23 PERN0
18 PCIE_RXP1_SLOT 25 PERP0
CHANNEL_CLK 5
3 R0402
R296 0 R0402 Debug CHANNEL_DATA 10K
+VDC 17 RESERVED0
R302 0 R0402 Debug 19 R300
10,18,19,24,29,30 BUF_PLT_RST# RESERVED1
20 R297 0 R0402
RESERVED_DISABLE HW_RATIO_OFF1# 29
R323 0 R0402 Debug 37
6 PCI_CLK_DEBUG RESERVED_PCIE0
+V3.3AL R295 0 R0603 39 RESERVED_PCIE1 R333 0 R0402 Debug
41 RESERVED_PCIE2 RESERVED_SIM0 16 EC_DEBG_Enable 29
R304 0 R0402 Debug 43 14 R338 0 R0402 Debug
17,29 LPC_FRAME# RESERVED_PCIE3 RESERVED_SIM1 PWR_SW_VCC2 25,31
R322 0 R0402 Debug 45 12 R339 0 R0402 Debug
17,29 LPC_AD0 RESERVED_PCIE4 RESERVED_SIM2 EC_DEBG_UTXD 29
R330 0 R0402 Debug 47 10 R340 0 R0402 Debug
17,29 LPC_AD1 RESERVED_PCIE5 RESERVED_SIM3 EC_DEBG_URXD 29
R331 0 R0402 Debug 49 8 ns
17,29 LPC_AD2 RESERVED_PCIE6 RESERVED_SIM4 T37
R332 0 R0402 Debug 51 ICTP
17,29 LPC_AD3 RESERVED_PCIE7
GND10
GND11
GND12
GND13
B
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9 +V3.3S_PCIE +V3.3AL_PCIE B
+V1.5S
A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name
PCIE MINI SLOT 1
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 23 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
+V3.3S 6,7,10,11,12,14,15,16,17,18,19,20,21,23,25,26,27,28,29,30,35,36,37,39
+V1.5S 8,10,11,12,20,23,35,36,37
+V3.3AL 15,17,18,19,20,23,25,27,29,30,31,32,33,34,35,36,37,39
D D
+DATA8
-DATA8
+V3.3S +V3.3AL +V3.3AL
1 1
D36 D35
EGA10603V05A1-B EGA10603V05A1-B R500 R506 R504
ESDPAD_R0603 ESDPAD_R0603 0 0 0
ns ns R0603 R0603 R0603 +V1.5S
2 2 ns
MPCIE2
MINIPCIE_TEMP1 +V3.3S +V3.3AL
Keep USB2.0 Signal stub short
52
24
48
28
2
6
+3.3VAUX
+3.3V0
+3.3V1
+1.5V0
+1.5V1
+1.5V2
R495 0
R496 0
R540 R502 R539
10K 10K 10K
CHK6 ns ns ns
90ohm@100MHz,0.5A
L4_0805
C
18 MINICARD_USB_PN3 3 4 -DATA8 36 46 T148 ns C
+DATA8 38 USB_D- LED_WPAN# T155 ns MiniPCIE_REQ#
18 MINICARD_USB_PP3 2 1 USB_D+ LED_WLAN# 44
42
18 PCIE_TXN2_SLOT 31 PETN0
33 32 R402 0 ns
18 PCIE_TXP2_SLOT PETP0 SMB_DATA SMB_DATA_S 6,14,19,23
30 R394 0 ns
SMB_CLK SMB_CLK_S 6,14,19,23
18 PCIE_RXN2_SLOT 23 PERN0
18 PCIE_RXP2_SLOT 25 PERP0
CHANNEL_CLK 5
CHANNEL_DATA 3
ns ICTP T150
17 RESERVED0
ns ICTP T146
19 RESERVED1
+V3.3AL
20 R503 0
RESERVED_DISABLE HW_RATIO_OFF2# 29
R532 0 37
R533 0 R0603 RESERVED_PCIE0
39 RESERVED_PCIE1
41 RESERVED_PCIE2 RESERVED_SIM0 16 T152ICTP ns
R0603 43 14 R491 R492
RESERVED_PCIE3 RESERVED_SIM1 T151ICTP ns
45 12 10K 10K
RESERVED_PCIE4 RESERVED_SIM2 T149ICTP ns
47 10 ns ns
RESERVED_PCIE5 RESERVED_SIM3 T154ICTP ns
49 RESERVED_PCIE6 RESERVED_SIM4 8 T153ICTP ns
51 RESERVED_PCIE7
B B
+V3.3S +V3.3AL
GND10
GND11
GND12
GND13
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
+V1.5S +V3.3S
+V3.3AL
A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name
USB Port
Size Project Name Rev
A3 N01 A
Date: Wednesday, July 16, 2008 Sheet 24 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
+V3.3S 6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,26,27,28,29,30,35,36,37,39
+V3.3AL 15,17,18,19,20,23,24,27,29,30,31,32,33,34,35,36,37,39
+V5S 15,16,19,20,21,26,27,29,35,37,38,39
+V5AL 15,20,22,33,34,36,37
+VDC 15,23,31,33,34,35,37,39
3
6 HOLE1 -DATA1 2 -DATA0 stub short 4 3 USB_PORT_PN0 18 +V3.3AL
7 3 +DATA0 1 2 PQ59
HOLE2 +DATA1 USB_PORT_PP0 18
8 L4_0805 2N7002E-T1
HOLE3 SWVCC2_SW_1 SOT23
GND 4 1
90ohm@100MHz,0.5A
1
SINGLE USB PORT D30 D29 CHK4 PC133
2
USB1 ESDPAD_R0603 ESDPAD_R0603 R335 0 R0603 PR163 1000pF/50V,X7R
EGA1-0603-V05 EGA1-0603-V05 GND_USB 1M C0402 PD32
R334 0 R0603 R0402 BAT54S
2
3 SOT23
GND_USB
GND_USB GND_USB
1
PWR_SW_VCC2 23,31
C C
3
R351 1K FAN_TACH_ON 1 Q23
2N2222 R352
+V5S C286 ns SOT23
2
ns 0
1000pF/50V,X7R
Q13 ns
BCP69-16
SOT223
4
3 2 Vfan
1
B B
R35
1
1K R24
1
10
R0603 R346 FAN_FB
USBCONN1
2
VCC_358 5.11K,1% 21 21
1
R36 U1A 2 1
4 4 3 3 USB_PORT_PN2 18
1K 0.1UF/25V,Y5V LM358 FAN_FB 6 5
6 5
8
10 9
1 12 12 11 11
1
- 2 Throttling/ 18 USB_PORT_OC1# 14 14 13 13
R349 Un-throttling +V3.3AL 16 15
16 15 USB_PORT_PP1 18
R22 18 17
15,29 LIDR# USB_PORT_PN1 18
4
C183 10K,1% 18 17
4.7K 20 20 19 19
R0402 22
2
0.1UF/25V,Y5V 22
R26 R25
High-5V 88242_2001
1 100K 2
FAN1_V 29 CNS2x10_1_R
200K R0402
Middle-4V
Low-3V
C94
C104
A
FAN1_V=3.30V,Vfan=5V 4.7UF/10V,Y5V 0.1uF/25V,Y5V
A
C0805 C0402
FAN1_V=2.65V,Vfan=4V 50 55 60 65 70 75 80 85 90 95 100
TOPSTAR TECHNOLOGY
Swain Xu
FAN1_V=1.98V,Vfan=3V Page Name Output Board
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 25 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
VCC5CDC +V5S
FB20
+V3.3S 6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,27,28,29,30,35,36,37,39
+V3.3S 1 2300ohm@100MHz,1.5A +V5S 15,16,19,20,21,25,27,29,35,37,38,39
FB0805
C252 C253 C254 C255 C256 C257 C258
C0402 C0402 C0805 C0402 C0402 C0805
0.1UF/25V,Y5V 0.1UF/25V,Y5V 10UF/6.3V,X5R 0.1UF/25V,Y5V 0.1UF/25V,Y5V 10UF/6.3V,X5R 0.1UF/25V,Y5V Headphone Jack
C0402
INPUT:HEADPHONE/LINE-OUT
U26
ALC662
Cross moat place OUTPUT:FRONT L/R
25
38
GND_AUD
1
9
QFPS48_0D5_1D6
VDD1
VDD2
AVDD1
AVDD2
LINE_OUT1
T39 ICTP ns A_GPIO0 2 35 C264 4.7uF/10V,X5R C0805 HP_OUT_L
GPIO0 FRONT-OUT-L HP_OUT_L R319 75 R0402 FB23 1
D
2300ohm@100MHz,1.5A 2 L D
ns A_GPIO1 3 36 C266 4.7uF/10V,X5R C0805 HP_OUT_R FB0805
T40 ICTP GPIO1 FRONT-OUT-R HP_OUT_R R320 75 R0402 FB24 1 2300ohm@100MHz,1.5A 3
37 FB0805 4 R
LINE1-VREFO-R C259 0.1UF/25V,Y5V C0402 HP_JD
GND_AUD 5
1
27 C265 10UF/6.3V,X5R C0805
VREF
1
D18 0.1UF/25V,Y5V D32 D31
11 28 VREFOUT R303 4.7K R0402 INT_MIC_L_R ESDPAD_R0603 C277 C278 C279 ESDPAD_R0603 ESDPAD_R0603 AZALIAJACK
17 HDA_RST# REST# MIC1-VREFO-L ns EGA1-0603-V05 C0402 EGA1-0603-V05 EGA1-0603-V05 AUDIO5A
6 ?? 100pF/50V,NPO 100pF/50V,NPO
17 HDA_BITCLK
2
BITCLK C0402 C0402
LINE1-VREFO-L 29
17 HDA_SYNC 10 SYNC
30 R317 2.2K R0402 MIC2_REF
MIC2-VREFO
17 HDA_SDOUT 5 SDOUT
LINE2-VREFO 31
R305 33 R0402 8
17 HDA_SDATA_IN0 SDIN
32 R306 4.7K R0402 INT_MIC_L_R GND_AUD
R307 51K R0402 C260 1uF/10V,Y5V C0603 C261 10pF/50V,NPO C0402 MIC1-VREFO-R
12 33 R308 10K R0402
29 BTL_BEEP PC-BEEP DCVOL VCC5CDC
ns
JACK_DET_A 13 34 JACK_DET_B
R309 75K R0402 C262 1uF/10V,Y5V C0603 JD1 JD2
C263
14 43
19 PC_BEEP 100pF/50V,NPO LINE2-L CEN-OUT Stereo Microphone Jack
C0402 15 LINE2-R LFE-OUT 44 INPUT:STEREO MIC-IN
R312
4.7K
R311
4.7K
MIC2_L C272 4.7uF/10V,X5R C0805 16
MIC2-L
ALC662 SIDESURR-OUT-L 45 D20
1N4148WS
OUTPUT:CENT/LFE
R0402 R0402 MIC2_R C273 4.7uF/10V,X5R C0805 17 46 MIC2_REF 1 2
MIC2-R SIDESURR-OUT-R SOD323
D24
18 47 EAPD R721 0 R0402 SHUTDOWN# 1N4148WS
CD-L SPDIFI/EAPD ns 1 2
REMOVE SHUTDOWN# 20 48 SOD323
CD-R SPDIFO
INT_MIC_L C267 1uF/10V,X7R C0603 21 R202 R220
MIC1-L SURR_OUT_L 4.7K 4.7K
SURR-OUT-L 39
update internal MIC circuit C268 1uF/10V,X7R C0603 22 R0402 R0402 MIC_IN1
MIC1-R R315 20K,1% R0402
C
JDREF 40 GND_AUD C
23 MIC2_L R310 75 R0402 FB21
1 2300ohm@100MHz,1.5A 2 L
LINE1-L SURR_OUT_R FB0805
Layout Note: SURR-OUT-R 41
CD-GND
24 MIC2_R R313 75 R0402 FB22
1 2300ohm@100MHz,1.5A 3
AGND1
AGND2
All of JD resistors should be LINE1-R R
GND1
GND2
FB0805 4
placed as close as possible to MIC2_JD 5
the sense pin of codec. 1
4
7
19
26
42
1
D17 C269 C270 C271 D33 D34
ESDPAD_R0603 ESDPAD_R0603 ESDPAD_R0603 AZALIAJACK
EGA1-0603-V05 C0402 100pF/50V,NPO 100pF/50V,NPO EGA1-0603-V05 EGA1-0603-V05 AUDIO5A
0.1UF/25V,Y5V C0402 C0402
2
GND_AUD
GND_AUD
HP_OUT_L GND_AUD HP_OUT_R GND_AUD
3
VCC5CDC VCC5CDC 2N7002DW 2N7002DW
SC70_6 SC70_6 JACK_DET_A R318 5.11K,1% R0402 HP_JD
AMP_SHDW 2 5 AMP_SHDW 2 5
GAIN0 GAIN1 Av(inv)
1
4
R722 R723
10K 10K 0 0 6dB
R0402 R0402
ns 0 1 10dB
GAIN0
GAIN1 Adjust Gain to 10dB 1 0 15.6dB
BY K' 080118 VCC5CDC
1 1 21.6dB D25
R724 R725
B B
10K 10K 1 2 JOPEN_3
R0402 R0402 R325 ns
ns 10K
R0402
0.1UF/25V,Y5V
Q12 C287 C0402 ns
2N7002
R327 1K R0402 1 0.1UF/25V,Y5V
29 AMP_SHDW
R329
Layout Note: FB26 1 2 FB0805 ns
2
0.1UF/25V,Y5V
GND_AUD
GND_AUD
Onboard Amp
C290 R336 U27
0.22uF/10V,X7R
20K TPA6017A2
onboard stereo
SURR_OUT_R
C0603 R0402 sop20_0d65_4d4g
INTSPR+
INTSPK1
INT_spkR 4Pin INT_MIC_L_R
microphone
17 RIN- ROUT+ 18
20K CNS4_R
R726 R0402 7 14 INTSPR- INTSPL- 4 4 6 6 MIC1
RIN+ ROUT- INTSPL+ Microphone
3 3
GND_AUD
C282 0.22uF/10V,X7R R326 10K R0402
C0603
9 LIN+ LOUT+ 4 INTSPL+ INTSPR+
INTSPR-
2 2
INT_MIC_L
R321
1K R0402 FB25 300ohm@100MHz,1.5A
+ BZ_D6027
ASSY
1 1 5 5 1 2 1
C283 0.22uF/10V,X7R 10 8 INTSPL- FB0805 2
GND_AUD BYPASS LOUT-
C0603 VCC5CDC
1
LED
D D
TCHARGE
+V3.3AL LED4_1210B
HA1B333B AMP&BLUE
Blue Color
B
R680 220 R0402 CHARGE_LED 4 2 TP_CHG_LED#
CHG_LED# 29
R
R682 220 R0402 BAT_STATE_LED 3 1 TP_BTL_LED#
BTL_LED# 29
C470 Orange color
0.1UF/25V,Y5V
C0402 TP
R684 220 R0402 PWR+ 1 2 TP_POWERLED# INT_spkR 6Pin
POWERLED# 29
CNS6_0D5_RA1
POWER
BL-HB335A-TRB 6 +V5S
6
8 8 5 5
C 4 C
4 TPCLK 29
7 7 3 3 TPDAT 29
TP_WIRELESS_LED#TESD11 1 2 EGA1-0603-V05 2
ns ESDPAD_R0603 2
1 1
+V3.3AL
TP_HDD_LED# TESD8 1 2 EGA1-0603-V05
ns ESDPAD_R0603 TP_CHG_LED# R709 10K R0402
ns
TP_CHG_LED# TESD9 1 2 EGA1-0603-V05
ns ESDPAD_R0603 TP_BTL_LED# R710 10K R0402
ns
TP_BTL_LED# TESD10 1 2 EGA1-0603-V05
ns ESDPAD_R0603 TP_POWERLED# R711 10K R0402
ns
TP_POWERLED# TESD12 1 2 EGA1-0603-V05
ns ESDPAD_R0603
H8
H1 H2 H4 H6 H9 H7
B B
HOLE
1
HOLE HOLE HOLE HOLE HOLE HOLE TH_256_118
1
TH_256_118 TH_256_118 TH_256_118 TH_256_118 TH_256_118 TH_256_118
ns ns CASE_GND ns
ns ns ns ns
GND_USB
GND_BAT
H3 H5
HOLE HOLE
1
1
TH_200_118 TH_200_118
A A
TOPSTAR TECHNOLOGY
ns ns
Swain Xu
Page Name
MDC/SSD
Size Project Name Rev
A3 N01 A
Date: Wednesday, July 16, 2008 Sheet 27 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
+V1.05S 6,7,8,9,11,12,17,20,35,36,37
+V3.3S 6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,29,30,35,36,37,39
+V3.3AL 15,17,18,19,20,23,24,25,27,29,30,31,32,33,34,35,36,37,39
D D
+V3.3S
+V1.05S
R362
10K R363
R0402 4.7K
R0402
ns
SHDN_LOCK#
R365
10K R368
6
R0402 100
5 2 R367 R0402
7 OVT_SHUTDOWN#
Q17 4.7K ns
C297 MMDT3904 R0402
SHDN_LOCK# 36
1
R366 1000pF/50V,X7R SC70_6 ns
C 100K C0402 R369 R371 C
R0402 470 1K
6
R0402 R0402
5 2 ns
3 7,10,17 PM_THRMTRIP#
ns
Q18 Q19 C299
1
2N7002E-T1 R370 C298 MMDT3904
1 SOT23 100K 0.1uF/10V,X5R SC70_6 2.2uF/10V,X7R
29 ALT_ON R0402 C0402 ns C0805
ns ns ns
2
R372
100K
R0402
OVP CIRCUIT
B VIN B
CPU
THRMTRIP# SHDN#
AND
THERM_ALERT#
VDC
Thermal
sensor
TOPSTAR TECHNOLOGY
Swain Xu
Page Name MDC&BT/FAN/OTP
A A
Size Project Name Rev
A4 N01
A
Date: Wednesday, July 16, 2008 Sheet 28 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
+V3.3S 6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,30,35,36,37,39
EC_V3.3AL EC_V3.3AL
+V3.3AL 15,17,18,19,20,23,24,25,27,30,31,32,33,34,35,36,37,39
+V3.3S +V5S
+V5S 15,16,19,20,21,25,26,27,35,37,38,39
C302 C303 C304 C305 C306 C307
+VDC 15,23,25,31,33,34,35,37,39
R375 10UF/6.3V,X5R 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V
10K C0805 C0402 C0402 C0402 C0402 C0402
R373 Q20 C308 R0402 FB27
8.2K 2N7002E-T1 4.7UF/10V,Y5V 120ohm/100MHz,500mA R377 +V3.3AL
Should have a 0.1uF capacitor close to every
1
R0402 SOT23 C0805 EC_RESET# FB0603 0
ns 1 2 EC_V3.3AL R0805 GND-VCC pair + one larger cap on the supply.
2 3 A20GATE C309 C310
17 H_A20GATE R739
3
D 100,1% Q21 0.1UF/25V,Y5V 0.1UF/25V,Y5V D
EC Output Signal! 1 MMBT3904-F R379 Stuff for DG C0402 C0402 PM_SLP_S4#
D21 R0402 SOT23 0 burn BIOS ROM,
1 1N4148WS R0402 Place near to PM_SLP_S3#
2
SOD323 R383 C311 ns keyboard LQFPS128_0D4_1D6 NB_OVT# R380 10K R0402
103
112
10K 0.01uF/25V,X7R U29 AD7 R381 10K
23
49
78
connector. R0402
R0402 C0402 C316 C317 AD6 R384 10K R0402
+V3.3S +V5S 100pF/50V,NPO 100pF/50V,NPO HDD_ZOUT R386 10K R0402
VREF
VCC1
VCC1
VCC1
AVCC
C0402 C0402 HDD_YOUT R385 10K R0402
Q22 HDD_XOUT R387 10K R0402
2N7002E-T1 EC_RESET# 50 104 AD7
RESET# AD7/GP67
1
ANALOG
2 3 RCIN# 51 108 HDD_YOUT
17 H_RCIN# 6 PCI_CLK_EC LCLK AD3/GP63
52 109 HDD_XOUT C312
EC Output Signal! 17,23 LPC_FRAME# LFRAME# AD2/GP62
EC_PCI_RST# 53 110 SYS_I_Sense 3300pF/50V,X7R
LRESET# AD1/GP61 SYS_I_Sense 40
D22 54 111 BAT_TEM C0402
19 INT_SERIRQ SERIRQ AD0/GP60
1 1N4148WS 56
17,23 LPC_AD0 LAD0
SOD323 57 113
17,23 LPC_AD1 LAD1 DA2/GP57 SET_I 40
17,23 LPC_AD2 58 114 IVT_I_ADJ 15
HOST BUS
LAD2 DA1/GP56
17,23 LPC_AD3 59 LAD3
EC_LPCSTS 60 +V3.3AL
R404 0 R0402 EC_RESET# LPCSTS
1 1 GP24/PWM0 73 BTL_BEEP 26
W83L951DG
PWM
2 R406 0 R0402 TEST# 62 72 EC_SPI_CS# R393 10K R0402
2 19 PM_CLKRUN# GP46/CLKRUN# GP25/PWM1 POWERLED# 27
3 SCANOUT15 A20GATE 63 71 EC_SPI_MOSI R392 10K R0402
3 GP45/GATE_A20 GP26/PWM2 FAN1_V 25
4 SCANOUT14 +V3.3AL RCIN# 64 70 EC_SPI_MISO R396 10K R0402
4 GP44/KBRST# GP27/PWM3 EC_BKLT_PWM 15
27 5 SCANOUT13 EC_SPI_SCK R395 10K R0402
27 5 SCANOUT12 R376 4.7K R0402 EC_LPCSTS I2C_CLK R397 4.7K R0402
28 28 6 6
C 7 SCANOUT11 SCANIN0 102 48 I2C_DATA R398 4.7K R0402 C
7 GP30/M_KR0/(FD0) GP70/KPS2_CLK OV_BAT_ALART 32
8 SCANOUT10 R448 4.7K R0402 EC_PCI_RST# SCANIN1 101 47 T42 ns SM_BAT_SDA2 R399 5.6K R0402
8 GP31/M_KR1/(FD1) GP71/KPS2_DAT
PS/2
9 SCANOUT9 SCANIN2 100 46 ICTP SM_BAT_SCL2 R400 5.6K R0402
9 GP32/M_KR2/(FD2) GP72/MPS2_CLK TPCLK 27
10 SCANOUT8 SCANIN3 99 45 LIDR# R401 10K R0402
10 GP33/M_KR3/TS(FD3) GP73/MPS2_DAT TPDAT 27
11 SCANOUT7 +V3.3AL RN6 SCANIN4 98 44 EC_IR_IN R422 10K R0402
11 GP34/M_KR4/ALE(FD4) GP74 CAM_PWRON 15
12 SCANOUT6 4.7K SCANIN5 97 43 EC_PWROFF# R403 10K R0402 ns
12 GP35/M_KR5/FWEN#/(FD5) GP75 HW_RATIO_OFF1# 23
13 SCANOUT5 RA0402_8 SCANIN6 96 PCIE_WAKE#_EC R405 10K R0402
13 SCANOUT4 SCANIN3 SCANIN7 GP36/M_KR6/FOEN#/(FD6) VOLUP R410 10K R0402
14 14 1 2 95 GP37/M_KR7/FCEN#/(FD7)
SMBUS
15 SCANIN0 3 4 SCANIN2 SCANOUT0 94 42 VOLDM R409 10K R0402
15 GP00/M_KC0/FD0 GP76/SDA0 I2C_DATA 7
16 SCANOUT3 5 6 SCANIN1 SCANOUT1 93 41 MEDIA R413 10K R0402
16 GP01/M_KC1/FD1 GP77/SCL0 I2C_CLK 7
17 SCANIN1 7 8 SCANIN0 SCANOUT2 92 40 MUTE R415 10K R0402
17 GP02/M_KC2/FD2 GP80/SDA1 SM_BAT_SDA2 32
18 SCANIN2 SCANOUT3 91 39 ALT_ON R416 10K R0402 ns
18 GP03/M_KC3/FD3 GP81/SCL1 SM_BAT_SCL2 32
KB ARRAY
19 SCANOUT2 7 8 SCANIN4 SCANOUT4 90 PWRSW# R421 10K R0402
19 SCANOUT1 SCANIN5 SCANOUT5 GP04/M_KC4/FD4 AC_OFF R424 10K R0402
20 20 5 6 89 GP05/M_KC5/FD5
21 SCANIN3 3 4 SCANIN6 SCANOUT6 88 38 LVDS_BKLTEN 10,15
TIMER
21 SCANIN4 SCANIN7 SCANOUT7 GP06/M_KC6/FD6 CNTR0/GP82
22 22 1 2 87 GP07/M_KC7/FD7 CNTR1/GP83 37 EC_DEBG_Enable 23
SCANIN5 SCANOUT8 EC_IR_IN
IR
23 23 86 GP10/M_KC8/FA8 CIR_RX/GP84 36
24 SCANOUT0 RA0402_8 SCANOUT9 85
24 SCANIN6 4.7K EC Input Signal! SCANOUT10 GP11/M_KC9/FA9
25 25 84 GP12/M_KC10/FA10
UART
26 SCANIN7 RN9 SCANOUT11 83 66
26 GP13/M_KC11/FA11 GP42/RXD EC_DEBG_URXD 23
R391 0 R0402 EC_BUF_PLT_RST# SCANOUT12 82 65
10,18,19,23,24,30 BUF_PLT_RST# GP14/M_KC12/FA12 GP43/TXD EC_DEBG_UTXD 23
SCANOUT13 81 EC_V3.3AL 8 1 EC_SPI_CS#
CNS26_1_R_UP SCANOUT14 GP15/M_KC13/FA13 EC_V3.3AL VCC CS# EC_SPI_MISO
80 GP16/M_KC14/FA14 7 HOLD# Q 2
ACES 85201-2402 SCANOUT15 79 121 EC_SPI_CS# EC_SPI_SCK 6 3 EC_V3.3AL
KBCON1 GP17/M_KC15/FA15 SCS/GP50 CLK W#
SPI
PCB_Mark0 77 120 EC_SPI_MOSI EC_SPI_MOSI 5 4
PCB_Mark1 GP20/nM_KC16 MOSI/GP51 EC_SPI_MISO D VSS
76 GP21/nM_KC17 MISO/GP52 119
PCB_Mark2 75 118 EC_SPI_SCK U12
R420 0 R0402 ns GP22/nM_KC18 SCK/GP53 W25X80A
Fuction P.M2 P.M1 P.M0 19 EXT_SMI# 74 GP23/nM_KC19 SOIC8_50_208
B B
VerA 0 0 0 GP47 61 EC_RUNTIME_SCI# 19 ns
MEDIA 22 117
EXTINT10/GPA0 GP54 BTL_LED# 27
VerB MUTE 21 116
0 0 1 VOLUP EXTINT11/GPA1 GP55 CHG_LED# 27
20 EXTINT12/GPA2 GP85 35 HW_RATIO_OFF2# 24
+V3.3AL Verc VOLDM
0 1 0 R423 1K R0402
19 EXTINT13/GPA3 GPIOA GP86 34
15,25 LIDR# 18 EXTINT14/GPA4 GP87 33
GPIO
R429 0 R0402 PCIE_WAKE#_EC17 31
19,23,24,30 PCIE_WAKE# EXTINT15/GPA5 GP90 PM_PWRBTN# 19
ns 16 30 EC_PWROFF# 19
31 AC_IN EXTINT16/GPA6 GP91
32 BATT_IN# 15 EXTINT17/GPA7 GP92 29 AMP_SHDW 26
R417 R418 R419 28 AC_OFF C315
10K 10K 10K GP93 R449 22pF/50V,NPO
GP94 27 CHG_ON 40
R0402 R0402 R0402 14 26 200,1% C0402
19,36 PM_RSMRST# EXTINT20/GPB0 GP95 BAT_OV_REV 32
ns ns ns R431 1K R0402 13 25 PROCHOT# XOUT24M R0402
25 PWRSW# EXTINT21/GPB1 GP96
PCB_Mark0 12 24
19,36 PM_SLP_S3# EXTINT22/GPB2 GP97 HW_OFF_BKLT# 15
PCB_Mark1 11
19,37 PM_SLP_S4# EXTINT23/GPB3
GPIOB
2
PCB_Mark2 10 Y4 R452
36 MAIN_PWROK EXTINT24/GPB4
9 68 ALW_PWROK 33 24MHZ 1M
10,19,39 IMVP_PWRGD EXTINT25/GPB5 GP40/FAN_TACH0
EC_BUF_PLT_RST# 8 EXTINT26/GPB6 FAN_TACH GP41/FAN_TACH1 67 EC_FAN_BACK 1 D19 FAN_BACK 25
XS2 R0603
R426 R427 R428 R432 0 R0402 EC_PM_SUS_STAT#7 1N4148WS
15,19 PM_SUS_STAT#
1
10K 10K 10K LABEL1 R434 1K EXTINT27/GPB7 XIN24M
+V3.3AL SOD323
R0402 R0402 R0402 Topstar Soft R0402 123 XIN24M R435
XIN
BIOS Ver: X.XX 31 ALWAYS_ON 6 EXTINT30/GPC0 SYSTEM CLK XOUT 122 XOUT24M 100K C318
EC Ver: X.XX 5 R0402 22pF/50V,NPO
BIU configuration 37 MAIN_ON EXTINT31/GPC1
4 C0402
should match flash XXXX年XX月XX日 34 V1_8_ON EXTINT32/GPC2
34 V0_9S_ON 3 EXTINT33/GPC3 XCIN 126
speed used EC/BIOS Label 2 RTC CLK 125
GPIOC
AGND
SOT23 The 0ohm RES will across the isolate Stuff for DG Page Name
GND
GND
GND
KBC(W83L951ADG)
EC Input Signal! island of anolog GND and digital GND burn BIOS ROM,
Place near to Size Project Name Rev
2 3 PROCHOT# R446 0 R0603 W83L951DG keyboard A3 N01
7 EC_PROCHOT# A
115
55
69
32
connector.
Date: Wednesday, July 16, 2008 Sheet 29 of 42
PROPERTY NOTE: this document contains information confidential and property to
R454 0 R0402 ns TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
+V3.3AL 15,17,18,19,20,23,24,25,27,29,31,32,33,34,35,36,37,39
+V3.3S 6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,35,36,37,39
Power domain chart
R658 3.6K R0402
+V3.3AL
RTL8101E VDD3D3_LAN
FB9
+V3.3AL 1 2 300ohm@100MHz,1.5A
R659 10K R0402 ns FB0805
10K is used only FB33
AVDD33 3.3V when 93C56 is used.
D D
+V3.3S 1 2 300ohm@100MHz,1.5A
VDD3D3_LAN DVDD15 U37 ns FB0805 VDD3D3_LAN
AVDD18 1.8V EECS 1 CS VCC 8
EESK 2 7 C425
EEDI/AUX SK NC1 0.1uF/10V,X5R
EVDD18 1.8V EEDO
3 DI NC2 6
C0402
4 DO GND 5
C419 C420 C421 C422 C423 C424 C426
DVDD15 1.5V 93C46 10UF/6.3V,X5R 10UF/6.3V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R
so8_50_150 C0805 C0805 C0402 C0402 C0402 C0402 C0402
ns
U38
53
46
37
16
59
58
33
52
49
43
41
38
32
21
15
48
47
45
44
2
RTL8101E Place close to VDD33_LAN PINS.
QFNS64_0D5_1G
LAN_TX0+
EESK
EEDI
EECS
VDD33_04
VDD33_03
VDD33_02
VDD33_01
NC19
EEDO
AVDD33_01
VDD15_10
NC8
NC18
VDD15_07
VDD15_06
NC14
NC11
NC7
VDD15_02
VDD15_01
LAN_TX0-
AVDD18
6 CLK_PCIE_LAN 26 REFCLK_P EVDD18_02 28 AVDD18
6 CLK_PCIE_LAN# 27 22 R666 R667
REFCLK_N EVDD18_01 49.9,1% 49.9,1%
18 PCIE_TXP0_LAN 23 14 R0402 R0402
HSIP NC6
18 PCIE_TXN0_LAN 24 HSIN NC3 11
18 PCIE_RXP0_LAN C430 0.1UF/10V,X7RC040229 8 C433 C434 C435 C436 C437 C438 C439
C428 0.1UF/10V,X7RC040230 HSOP AVDD18_02 10UF/6.3V,X5R 10UF/6.3V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R
18 PCIE_RXN0_LAN HSON AVDD18_01 5
C447 C0805 C0805 C0402 C0402 C0402 C0402 C0402
10,18,19,23,24,29 BUF_PLT_RST# 20 63 0.01uF/25V,X7R ns
PERSTB VCTRL15 DVDD15
1 C0402
VCTRL18 AVDD18
C
19,23,24,29 PCIE_WAKE# 19 LANWAKEB LAN_TX0+
Place close to AVDD18 PINS. C
+V3.3S R660 1K R0402 MDIP0 3
LAN_TX0-
Place close to AVDD18
36 ISOLATEB MDIN0 4
LAN_TX1+
Place Close to Chip Power Output PIN1
MDIP1 6
R661 15K R0402 54 7 LAN_TX1-
LED3 MDIN1
55 LED2 NC1 9
56 10 DVDD15
LED1 NC2
57 LED0 NC4 12
NC5 13
R662 2K,1% R0402 RSET 64 RSET Y6
CKTAL2 61
If use 8102E, R662 install 2.49K 1% 60 25MHz
Swain 080709 CKTAL1 XS2
62 NC20 C440 C451 C453 C454 C446 C455 C456
EGND1
EGND2
1 2
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
NC17
NC16
NC15
NC13
NC12
NC10
NC21
NC22
G1
G2
G3
G4
G5
G6
G7
G8
G9
51
50
42
40
39
35
34
18
17
C0402 C0402
Place close to DVDD15 PINS
Place close to DVDD15
Power Output PIN63
AVDD18
U39
TRAN16_50_272 RN15 CASE_GND
R348 13 5 0x4
N4 N2 RA0603_8 J5
0 12 N3 N1 4
R0402 1 2 RJ45
9
B LAN_TX0- TX0- RJ45_S B
9 TD- TX- 8 3 4
5 6 RJ45
11 6 MCT1 7 8
TDC CMT RJ45_TX0+ 1 TX0+
LAN_TX0+ 10 7 TX0+ CHK5 RJ45_TX0- 2 TX0- TX0+
TD+ 1CT:1CT TX+ 90ohm@100MHz RJ45_TX1+ TX0-
3 TX1+
LAN_TX1- 15 2 TX1- CMC8 ns MCT3 4 TX2+ TX1+
RD- RX- TX1- RJ45_TX1-
TX2+
4 L2+ L3+ 5 5 TX2- TX2-
14 3 MCT2 TX1+ 3 RJ45_TX1+ RJ45_TX1-
L3- 6 6 TX1- TX1-
RDC RXC TX0- L2- RJ45_TX0- TX3+
2 L1+ L4+ 7 7 TX3+
LAN_TX1+ 16 1 TX1+ TX0+ 1 RJ45_TX0+ MCT4 TX3-
L4- 8 8 TX3-
MCT1
MCT2
MCT3
MCT4
C463 RD+ 1CT:1CT RX+ L1-
0.01uF/25V,X7R C465
C0402 0.01uF/25V,X7R
C0402
10
R692 R693 R694 R695
75 75 75 75 CASE_GND
LAN_TX1+ VDD3D3_LAN LAN_TX1- R0402 R0402 R0402 R0402
LAN_TX1+
LAN_TX1-
LD9
AZC099-04S
4
SOT23_6 C498
ns 1000pF/2000V
C1206
A
C464 330pF/50V,X7R C0603 A
R668 R669 TOPSTAR TECHNOLOGY
C466 4.7uF/10V,Y5V C0805 49.9,1% 49.9,1% CASE_GND
<OrgAddr1>
R0402 R0402
C467 330pF/50V,X7R C0603 Page Name RTL8101E/8111C(GLAN)
C468 330pF/50V,X7R C0603 Size Project Name Rev
3
C448 A3 N01
0.01uF/25V,X7R A
CASE_GND C0402 LAN_TX0+ LAN_TX0- Date: Wednesday, July 16, 2008 Sheet 30 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained with the
expressed written consent of TOPSTAR
5 4 3 2 1
BATT+ 32,40
+V3.3AL 15,17,18,19,20,23,24,25,27,29,30,32,33,34,35,36,37,39
+VDC 15,23,25,33,34,35,37,39
ALW_EN
POWER_HOLD
Hole+Dowel PC1 PQ2
TH_61_45 0.1uF/25V,X7R AO4419
AD+ C0603 PD1 SO8_50_150
4
ns PF1 PFB1 SSM34PT PR4
G
7A 100ohm@100MHz,3A SMA 0.025,1%
1
5A 5A
D
FUSE1206 FB0805 R2512 5
1 2 3A 1 2 3A 1 3A 3
S
6 BATT+
2 7
1 8
1
1 2
PD2 1
PFB2 SSM34PT PD3
100ohm@100MHz,3A SMA SSM34PT
FB0805 SMA
GND_HOLD PC3
Hole+Dowel 0.1uF/25V,Y5V
40 Isense_SYSP
TH_61_45 C0402
ns
PC4 PC5
36,40 Isense_SYSN
1uF/25V,Y5V 1uF/25V,Y5V
1
C0805 C0805
5A 1 8
5A
+VDC
2 7
3 6
PQ3 S 5
AO4419 D
SO8_50_150 G
铜皮连接 PC6
4
Jack_GND PR10 0.01uF/25V,X7R
510K C0402
R0402
PR135
AD+ +V3.3AL 0
R0402
PR9 PD5
3
3
20K 1N4148WS
R0402 PQ4 SOD323 PQ7
2N7002 32,36 SHDN# 2N7002
1 SOT23 1 1 SOT23
23,25 PWR_SW_VCC2
PR144
1K
AC_IN 29
2
2
PR11 R0402
51K PR12 2
29 ALWAYS_ON
R0402 1K PC9
PR15 R0402 3 1000pF/50V,X7R
PC7 20K C0402
1000pF/50V,X7R R0402 ALW_EN 1
C0402
PD4 PR18
BAT54C 100K
SOT23 R0402
TOPSTAR TECHNOLOGY
Mayc
PFB4 100ohm@100MHz,3A
1 2 FB0805
PF2
7A
5A PFB5 100ohm@100MHz,3A
1 2 FB0805
5A FUSE1206
1 2 7 BATT+
BATT+
PC10 C157 BAT_B1 BAT_B2
1000pF/50V,X7R GND_BAT GND_BAT 0.1uF/25V,Y5V KEY
C0402
SM_BAT_SDA2 PR20 100 R0402 SM_BAT_SDA ns 6 SDAT
29 SM_BAT_SDA2
SM_BAT_SCL2 PR19 100 R0402 SM_BAT_SCL 5 SCLK
29 SM_BAT_SCL2
4 TEMP Screw 2*8mm Screw 2*8mm
Assembly Assembly
3 BAT_IN# 711000000013 711000000013
2 GND PD6
1N4148WS
1 GND BATCON1 SOD323
BATT_CONN
BATJ7_MC 29 BAT_OV_REV 1
9
ns
+V3.3AL GND_BAT
2
1 PQ8
PR21 2N2907 PR23
300K SOT23 1K PR24
3
R0402 PR22 ns R0402 51K
1K ns R0402
3
R0402
PQ9 1
BATT_IN# 29
2N2222
SOT23
2
ns PR25
2K PC11
OV_BAT_ALART 29
R0402 0.1UF/25V,X7R
ns C0603
SM_BAT_SDA2 ns
SM_BAT_SCL2
PR26 0 R0402
layout注意将此部分电路尽量放在板子上不热的地方
PC12 PC13
5.6pF/50V,NPO
C0402
5.6pF/50V,NPO
C0402
PR27 0 R0402
Battery Over Voltage Protection
PR28 0 R0402
GND_BAT GND_BAT
GND_BAT
PZD1 PZD2
+V3.3AL BAT54S +V3.3AL BAT54S
SOT23 SOT23
2
2
3 SM_BAT_SDA
PC14 3 SM_BAT_SCL
0.1uF/25V,Y5V 1 PC15
C0402 0.1uF/25V,Y5V 1
C0402
+VDC
D +V5AL D
5 VCC BOOT 1
PC16
4.7uF/10V,X5R PC17 PC21
C0805 PC18 PC19 4.7uF/25V,X7R
0.1uF/25V,Y5V 1000pF/50V,X7R 0.1uF/25V,X7R C1206
3 8 C0402 C0402 C0603
PR165 GND PHASE +V3.3AL
5
6
7
8
20K PR145
D
R0402 0 PQ60
ns R0402 AO4468
4 SO8_50_150
G
PR30
S
7 2 100K
COMP/SD UGATE R0402
2A
3
2
1
PR29 PL1
20K 1 +V3.3AL
5
6
7
8
R0402 PR146 5.2uH/5.5A ALW_PWROK
29 ALW_PWROK
D
PC23 PC22 0 V3_3AL
0.022uF/16V,X7R 47pF/50V,NPO R0402 TestP
2
C0402 C0402 6 4 4 PD27 LS2_1040 TPC60
FB LGATE
G
1N5819 PD9 ns
1
+
1
S
SOD123 BZT52C3V6S-F/3.6
PQ61 ns SOD323
3
2
1
2
AO4468 PC134
1
PR31 PR32 SO8_50_150 220UF/6.3V,OSCON
1K,1% 5.11K,1% CAP6_6x7_3
C R0402 R0402 C
PU1 PC117
ISL6545 0.1uF/10V,X5R
SOIC8_50_150 PR33 C0402
4.53K,1%
R0402
PR166 PD34
0 1N4148WS
R0402 SOD323
1
ns ns
+VDC +VDC
5 VCC BOOT 1
PC30
PC25 PC26 4.7uF/25V,X7R
B 4.7uF/10V,X5R C1206 B
C0805 0.1uF/25V,Y5V PC27 PC28
C0402 1000pF/50V,X7R 0.1uF/25V,X7R
3 8 C0402 C0603
PR167 GND PHASE
20K
R0402
5
6
7
8
ns PR147
D
0 PQ62
R0402 AO4468
7 2 4 SO8_50_150
COMP/SD UGATE
G
3A
S
PR34 PL2
20K +V5AL
63
72
81
1
5
PC31 0 LS2_1040
47pF/50V,NPO R0402 PD29
2
C0402 6 1N5819
1
FB LGATE 4 4
G
2
AO4468 ns
1
PR36 SO8_50_150
6.34K,1%
PR35 PU2 R0402 PC135 PC118
412,1% SOIC8_50_150 220UF/6.3V,OSCON 0.1uF/10V,X5R
R0402 ISL6545 CAP6_6x7_3 C0402
A
PR37 A
3.01 KOHM +/-1% TOPSTAR TECHNOLOGY
R0402 Mayc
+V0.9S 14,37
+V5AL 15,20,22,25,33,36,37
+V3.3AL 15,17,18,19,20,23,24,25,27,29,30,31,32,33,35,36,37,39
+VDC 15,23,25,31,33,35,37,39
+V1.8 10,12,14,36,37
2.5A 2A
+V1.8
DDR2用电源 +VDC
D PC40 D
PC35 PU3 4.7uF/25V,X7R
PC34 4.7uF/10V,X5R TPS51116 PC37 C1206
5
6
7
8
0.1UF/10V,X7R C0805 SOP20_0D65_4D4G PC36 1000pF/50V,X7R
C0402
D
PC41 0.1uF/25V,X7R C0402
0.1uF/25V,X7R C0603
1 20 C0603 4
VLDOIN VBST AO4468
G
PL8
500mA PQ14
S
2.2UH/14A V1_8
9 19 0 PR76 PR38 LS2_6530 ns TestP
10,14 SM_VREF_L
3
2
1
VDDQSNS DRVH R0402 10K 1 TPC60
5A
PC38 6 18
500mA 5A 5A ns
MODE LL 1 +V1.8
0.1uF/10V,X7R PL3
5
6
7
8
C0402 R0402 PC43
500mA 3.3uH/4.8A
2
D
DDR_GND 7 17 0 PR77 LS2_8836 C0402
VTTREF DRVL 0.1uF/10V,X7R
1
1
4 PD13 PZ1
D-CAP AO4468
G
PR40 10K R0402 11 8 SSM34PT + BZT52C2V0S-F/2.0V
1
29 V0_9S_ON S3 COMP PQ15
S
PR41 200K R0402 PC44 SMA PC136 SOD323
1
1000pF/50V,X7R 220UF/6.3V,OSCON
3
2
1
2
PR39 10K R0402 12 10 C0402 CAP6_6x7_3
29 V1_8_ON S5 VDDQSET PR44
PR42 200K R0402 R0402
4 15 F_5VAL 10
DDR_GND VTTSNS CS PR43
2A 2 14
R0402
20K
VTT V5IN +V5AL
+V0.9S PR45
C PC45 PC46 100K PC47 C
10uF/6.3V,X5R10uF/6.3V,X5R 3 13 R0402 ns 4.7uF/10V,X5R
VTTGND PGOOD +V3.3AL
C0805 C0805 C0805
ns F_5VAL
TGND
V0_9S1 5 16
TestP GND PGND
TPC60
DDR_PWG
DDR_PWG 36
21
ns V1_8_ON
400KHz PC48
1uF/10V,X7R
C0603
1
R0402
PJ2 PR46
JOPEN 0 DDR_GND
RESISTOR_1
ns +V3.3AL
2
+V3.3AL +V5AL
DDR_GND
PR48
20K
R0402
+V0.9S PR47
51K DDR_PWG
R0402
3
PQ16
1
B PR49 2N7002E-T1-E3 B
1K 1 SOT23 J4
R0402 JOPEN
RESISTOR_1
2
ns
2
3
PQ17
1 MMBT2222A
SOT23
2
PR50
20K
R0402
A A
TOPSTAR TECHNOLOGY Mayc
Swain Xu
Page Name +V1.8/+V0.9S DDR
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 34 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
+V3.3AL 15,17,18,19,20,23,24,25,27,29,30,31,32,33,34,36,37,39
+V3.3S 6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,36,37,39
+VDC 15,23,25,31,33,34,37,39
+V1.5S 8,10,11,12,20,23,24,36,37
+V1.05S 6,7,8,9,11,12,17,20,28,36,37
+V5S 15,16,19,20,21,25,26,27,29,37,38,39
D D
PR168 PD35
0 1N4148WS
R0402 SOD323
1
ns ns
+V5S +VDC
5 1 PC50
1.5A
VCC BOOT 0.1uF/25V,Y5V
PC49 C0402
4.7uF/10V,X5R
C0805 PC51 PC52 PC54
PR169 1000pF/50V,X7R 0.1uF/25V,X7R
mayc for L6783 0320 20K 3 8 C0402 C0603 C1206
R0402 GND PHASE 4.7uF/25V,X7R
5
6
7
8
ns PR150
D
0 PQ64
R0402 AO4468 PL10
+V3.3AL 4 SO8_50_150 2.2UH/14A
G
LS2_6530 ns
S
7 COMP/SD UGATE 2 1 080716VA:Co_lay.
3
2
1
PR170
4.7K
PR51
20K
3A
1 +V1.5S
5
6
7
8
R0402 R0402 PR152
D
PQ65 PC55 0 PL4
2
2N7002 47pF/50V,NPO R0402 3.3uH/4.8A
1
PR171 1 SOT23 C0402 6 4 4 PD30 LS2_8836
FB LGATE
G
1K PC56 1N5819 PD16 V1_5S
1
+
1
S
R0402 2 0.022uF/16V,X7R PQ66 SOD123 SOD323 TestP
3
3
2
1
1
1 PQ67 SO8_50_150 ns
29 V1_5S_ON
MMBT3904-F PR54 PR55
C 2K,1% 6.34K,1% PC121 C
2
CHIPPWROK#
CHIPPWROK 36
PQ20
PR56 MMDT3904
1K SC70_6
6
+V1.5S R0402
5 2 CHIPPWROK#
1
PR58
100K
R0402
PR60
1K
3
R0402
1 PQ21
+V1.05S MMBT2222A
SOT23
2
PR59
mayc for L6783 0320 100K
R0402
PR173 PD36
B 0 1N4148WS B
R0402 SOD323
1
ns ns
+V5S +VDC
5 1
1.5A
VCC BOOT
PC58 PC59 PC63
4.7uF/10V,X5R PC60 PC61 4.7uF/25V,X7R
C0805 0.1uF/25V,Y5V 1000pF/50V,X7R 0.1uF/25V,X7R C1206
C0402 C0402 C0603
3 GND PHASE 8
PR174
20K
+V3.3AL R0402
5
6
7
8
ns PR154 PL11
D
0 PQ68 2.2UH/14A
R0402 AO4468 LS2_6530 ns
7 2 4 SO8_50_150 1 080716VA:Co_lay.
COMP/SD UGATE
G
3A
S
1
3
PQ69 PC64 0
2N7002 47pF/50V,NPO R0402 1
2
1 SOT23 C0402 6 4 4 PD31
FB LGATE
G
1N5819 V1_05S
1
+
1
S
1
MMBT3904-F PR62 PR63 PC124
PR176 4.02K,1% 6.34K,1% 0.1uF/10V,X5R
2
30K SOD323
J8 R0402 PR64 BZT52C2V0S-F/2.0V
JOPEN 3.01 KOHM +/-1%
A RESISTOR_1 PC139 R0402 A
ns 0.1uF/25V,Y5V
2
C0402
ns
+V3.3S 6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,37,39
+V5AL 15,20,22,25,33,34,37
+V3.3AL 15,17,18,19,20,23,24,25,27,29,30,31,32,33,34,35,37,39
+V1.05S 6,7,8,9,11,12,17,20,28,35,37
+V1.5S 8,10,11,12,20,23,24,35,37
+VCC_CORE 8,39
+V1.8 10,12,14,34,37
+VDC 15,23,25,31,33,34,35,37,39
D D
OVP CIRCUIT
Power Good Logic CIRCUIT
PQ24
DTB114EK
+V3.3S SOT23
31,40 Isense_SYSN 2 3 SHDN# 31,32
PR67
PR65 20K
10K PR69
1
R0402 PC67 100K
PR66 0.1uF/25V,Y5V R0402
1K C0402 PR68
R0402 20K
35 CHIPPWROK MAIN_PWROK 29
R0402
2
PR70 0 PR71 PQ25
3
R0402 20K 1 DTB114EK PQ26
28 SHDN_LOCK#
PD20 1 1N4148WS R0402 SOT23 PC68 2N7002
34 DDR_PWG
SOD323 0.01uF/25V,X7R SOT23
3
C PQ27 C0402 1 C
MMDT3904
6
PZ2 SOD323 SC70_6
2
PD21 1 1N4148WS 2 1 5 2
19,29 PM_RSMRST# +V5AL
SOD323
PR72 BZT52C5V6S-F/5.6
1
1K PR73
R0402 PD22 1 1N4148WS PZ3 SOD323 20K
19,29 PM_SLP_S3#
SOD323 2 1 PR74 PR75 R0402
PC69 +V3.3AL PC70 100 PC71 20K
0.1uF/10V,X7R BZT52C3V6S-F/3.6 1uF/10V,X7R R0402 1000pF/50V,X7R R0402
C0402 C0603 C0402
PZ4
2 1
+V1.8
BZT52C2V0S-F/2.0V
SOD323
PZ5
2 1
+V1.5S
BZT52C2V0S-F/2.0V
SOD323
PZ6
2 1
+V1.05S
BZT52C2V0S-F/2.0V
SOD323
PZ7
+VCC_CORE 2 1
B B
BZT52C2V0S-F/2.0V
SOD323
PR78
1K PZ8
R0402 2 1
31,40 Isense_SYSN
BZT52C13S-F/13.0V
SOD323
080716VA:新料,料号申请中.
A A
TOPSTAR TECHNOLOGY
Mayc
Swain Xu
Page Name Power Good logic/OVP
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 36 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
+V3.3S 6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,39
+V3.3AL 15,17,18,19,20,23,24,25,27,29,30,31,32,33,34,35,36,39
+V5S 15,16,19,20,21,25,26,27,29,35,38,39
+V5AL 15,20,22,25,33,34,36
+V1.5S 8,10,11,12,20,23,24,35,36
+V2.5S 12,38
+V0.9S 14,34
+V1.05S 6,7,8,9,11,12,17,20,28,35,36
+VDC 15,23,25,31,33,34,35,39
+V1.8 10,12,14,34,36
D D
V5S1
+V5AL 1 8 TestP V3S1
2 7 TPC60 +V3.3AL 1 8 TestP
3 6 ns 2 7 TPC60
PQ50 S 5 +V5S 3 6 ns
PR136 AO4419 D PQ51 S 5 +V3.3S
PC125 510K SO8_50_150 G AO4419 D
0.01uF/25V,X7R R0402 PC126 SO8_50_150 G
4
C0402 0.01uF/25V,X7R
4
C0402
PC115
0.01uF/25V,X7R PC116
C0402 PR137 0.01uF/25V,X7R
510K C0402
R0402
PR138
0 PR139
R0402 0
MAIN_PWR_DN# R0402
PD38
1N4148WS
3
PR140 SOD323
3
10K PQ52 PR141 1
R0402 2N7002 30K PQ53
1 SOT23 R0402 2N7002
29 MAIN_ON
C 1 SOT23 C
29 MAIN_ON
EC
2
PC127
2
0.1uF/25V,Y5V PR142 PC128
C0402 510K 0.1uF/25V,Y5V PR143
R0402 C0402 510K
ns R0402
ns
+V1.8 +VDC
36mA
PR96
100
2
R0402
PR97
Add +V2.5S Discharge by mayc 100
R0402 PR98
V1_8DISCHG 510K
1
R0402
3
PR92 PQ38 2N7002
100 2N7002 SOT23
30mA 50mA 70mA 18mA R0402 21mA SOT23
PR99 10K 1 1 V1_8DISCHG
19,29 PM_SLP_S4#
R0402
2
2
B PR84 B
2
100 PR85 PR86 PR87 PR89 PR90 PR91 PR93 PR94 PR100
R0402 100 100 100 PR88 100 100 100 100 510K 510K
R0402 R0402 R0402 100 R0402 R0402 R0402 R0402 R0402 R0402
R0402
1
1
DISCHG
PR95
510K
R0402
A A
TOPSTAR TECHNOLOGY
Mayc
+V3.3AL 15,17,18,19,20,23,24,25,27,29,30,31,32,33,34,35,36,37,39
+V2.5S 12,37
+V5S 15,16,19,20,21,25,26,27,29,35,37,39
D D
PD25 1N4148WS
SOD323 V25S1
1 ns TestP
TPC60
ns
PU7
ADJ/GND
+V5S 3 VIN VOUT 2 +V2.5S
Vo 4
1 KIA1117-ADJ PR104
SOT223 301,1%
R0402
PC79 PC80
10uF/6.3V,X5R 10uF/6.3V,X5R
C0805 C0805 PR105
1K
C PR106 R0402 C
301,1%
R0402
B B
+VDC 15,23,25,31,33,34,35,37
+V5S 15,16,19,20,21,25,26,27,29,35,37,38
+VCC_CORE 8,36
+V3.3S 6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37
+V3.3AL 15,17,18,19,20,23,24,25,27,29,30,31,32,33,34,35,36,37
D PR178 PD37 D
0 1N4148WS
R0402 SOD323
1
ns ns
+VDC
+V5S
5 VCC BOOT 1
PC86
4.7uF/25V,X7R
PC81 PC82 C1206
4.7uF/10V,X5R PC83 PC84 PC85
C0805 0.1uF/25V,Y5V 1000pF/50V,X7R 0.1uF/25V,X7R 10uF/25V,X5R
3 GND 8 C0402 C0402 C0603 C1210
PHASE ns
PR179
20K
5
6
7
8
+V3.3AL R0402 PR158 PL12
D
ns 0 PQ40 2.2UH/14A
R0402 AO4468 LS2_6530 ns
7 2 4 SO8_50_150 1 080716VA:Co_lay.
COMP/SD UGATE
S
PR180 PR107 PL9
4.7K 20K +VCC_CORE
63
72
81
1
5
R0402 R0402 PR160 5.2uH/5.5A
D
PQ72 PC88 0 LS2_1040
C 2N7002 47pF/50V,NPO R0402 PC142 C
2
1 SOT23 C0402 6 4 4 220UF/6.3V,OSCON
FB LGATE AO4468
G
CAP6_6x7_3 + VCORE
1
PQ41
S
PC87 PD28 TestP
2
3
1
3
2
1
2
29 IMVP_ON 1 PQ73 C0402 BZT52C3V6S-F/3.6 ns
1
MMBT3904-F PR109 PD26 PC130
PR181 6.34K,1% 1N5819 0.1uF/10V,X5R
2
30K
J9 R0402 PR110
JOPEN PR108 2.49K,1%
RESISTOR_1 PC141 3.01 KOHM +/-1% R0402
ns 0.1uF/25V,Y5V R0402
2
C0402
ns
+V3.3AL
B B
+V3.3S
+V3.3AL
PR112
PR111 20K
+VCC_CORE 20K R0402
R0402
IMVP_PWRGD 10,19,29
CK505_CLK_EN# 19
PR113
3
10K PR116
R0402 30K PQ74
R0402 2N7002
3
1 SOT23
PQ42 19 CK505_CLK_EN#
1
MMBT2222A
2
A
SOT23 A
2
PU9
PC92 PR121 0
1.5A
1uF/10V,X7R VDDP 15 2 R0402 Isense_SYSN 31,36
CHG_GND VDDP ACSET
C0603
PR118
4.7 5V_internal_LDO PC94
R0402 1 0.1uF/25V,Y5V PC95 PC98 PC96 PC104
PC93 VDD C0402 PC97 SOD323 1000pF/50V,X7R 0.1uF/25V,X7R 10uF/ 25V 4.7uF/25V,X7R
1uF/10V,X7R 24 1N4148WS/75V/150mA C0402 C0603 C1210 C1206
C0603 DCIN 1
ns ns
31 Isense_SYSP 19 CSIP PR122 0
PR119 PC99 R0402 070906VA:Co-lay。
0.1uF/25V,Y5V 20 17 PR120
31,36 Isense_SYSN CSIN UGATE
C0402 R0402 0
5
6
7
8
10 R0402
PC102
D
PC100 PC101 PQ77
1000pF/25V,X7R 5600pF/50V,Y5V 5 16 VDDP AO4468
ICOMP BOOT 1
C0402 C0603 ISL6251HAZ 4 SO8_50_150 8.4V
G
1N4148WS/75V/150mA PR123 PL7 PR124
S
SSOP24_25_150 PC106 SOD323 10K 15uH/3.6A 50mOHM,1% PC109 BATT+
PC103 PC105 0.01uF/25V,X7R 6 0.1uF/25V,Y5V R0402 2Aphase LS2_1040 2A R2512 2A 0.1uF/25V,X7R
6 3
7 2
8 1
C0402 VCOMP C0402 C0603 VBATS1
1
5
R0402 10K 18 phase TestP
PHASE
D
TPC60
CHG_GND 3.3V 11 VADJ PC107 ns
4 PC108 PC110
10uF/ 25V
G
14 PD39 4.7uF/25V,X7R 1uF/25V,Y5V
LGATE
S
1N5819 C1206 C1210 C0805
1
3
Change from 10k to 6.98k 29 CHG_ON EN PQ49 SOD123 ns
3
2
1
13 AO4468 ns
PR126 PGND SO8_50_150
6.98K,1% 9 PR127
29 SET_I CHLIM
R0402 21
CSOP
PR125 PC111 2.2 R0402
15.4K,1% 2.39V_Vref 8 1uF/10V,X7R
VREF
SET_I 充电电流 R0402
CSON 22 C0603
PR128 10 ACLIM
0V 0A 10.5K,1%
R0402
CELLS 4
0.66V 400mA 0.1 Vref
23 ACPRN
PR130
100
3.3V 2A 设置适配器限流值为 7 R0402 Layout note:
55mV/25m ohm=2.2A. ICM SYS_I_Sense 29
PR129
Far away from critical signal trace
1.05K 1% GND 12
R0402 PC112
3300pF/50V,X7R
C0402
PR131 0
R0402
CHG_GND
CHG_GND
TOPSTAR TECHNOLOGY
1B 2A 2B
BATT+ +V5_STBY
PQ1 ALW_PWROK EC_RTC
D D
PD1 4A
1A +VDC
AD+
Always_On 4B +V3.3AL
PQ2
Power +V5AL
3A
2A ISL6545
AC_IN
PWRSWVCC2
V1_8_PWROK 11
ALWAYS_ON 7 DDR_PWROK 11
QB_PWRSWVCC2 +V3.3S 12
System Power 11 +V3.3S AS431 +V2.5S
6B 5A +V_S +V5S +V3.3S
PWRSWVCC2 PWRSW# DDR Power 10 +V1.8 +V1.8GDDR
+VDC
7B 6A TPS51116 +V0.9S
QB_PWRSWVCC2
+VDC
9 10 MAIN_ON
9
PM_RSMRST# 5B
+V3.3AL
V1_8_ON
V0_9S_ON
RST_Circuit 4A
PM_SLP_S4# 8 10 4A 4B
C MAIN_ON ALW_PWROK C
PM_SLP_S3# 8
DDR_PWROK 11
PM_RSMRST# 20 V1_5S_PWROK 15
MAIN_PWROK
EC_KBC PU7 V1_05S_PWROK 15
PC97551 SET_I
ICH7 7 PM_PWRBTN# V2_5S_PWROK 13
CHG_ON
NVVDD_PWROK 19
7 ALWAYS_ON MAIN_PWROK
IMVP_ON
to IMVP_ON SYS_I_Sense
Delay 100mS
VR_PWRGD_CK410_INV
+V1.5S
24 ISL6545
23 +V1.05S PU10 SET_I
H_PWRGD
CHG_ON
B
24 V1_5S_PWROK 15 B
V1_05S_PWROK 15
21 IMVP_ON
23 IMVP_PWRGD CK410_CLK_EN# 22
Calistoga VCC_CORE Clock
GMCH ISL6545 CK410M Note:
22
*A:For adapter in
+VCC_CORE *B:For battery only
H_CPURST# 25 23 VR_PWRGD_CK410_INV * :For all
H_PWRGD
CPU
A A
TOPSTAR TECHNOLOGY
CPURST# CPURST#
T15 T15
PCIRST# PCIRST#
PLTRST#
T14 T14
SUS_STAT# SUS_STAT#
T17 T17
T23 T23
(CPU PWRGD) (CPU PWRGD)
H_PWRGD T10 H_PWRGD
D T10 D
PM_ICH_PWROK (Input to ICH) PM_ICH_PWROK (Input to ICH)
IMVP_PWRGD IMVP_PWRGD
CK410_CLK_EN# CK410_CLK_EN#
+VCC_CORE +VCC_CORE
T08 T08
130ms 130ms
PWRSW#(Input to EC)
Press Power Button +V3.3AL,+V5AL,
+V5_STBY,EC_RTC
(PRESS POWER BUTTON)
+V5_STBY,EC_RTC AC_IN
+VDC
+VDC
T01 RTCRST#
RTCRST# T01
T02
VCCRTC T02
VCCRTC PLUG
PLUG Adapter
Main
Battery
V1_8_ON(EC Output)
V0_9S_ON(EC Output)
+V3.3S,+V5S,+V2.5S,+V1.5S,+V1.05S,+V1.8,
+V0.9S V1_8_ON(EC Output)
+V3.3S,+V5S,+V2.5S,+V1.5S,+V1.05S,+V1.8,
+V0.9S
T22a
ALWAYS_ON(EC Output)
ALWAYS_ON(EC Output)
T22c
+V3.3AL,+V5AL
IacN
RSMRST#(Input to EC)
IacN
ACIN
A A
TOPSTAR TECHNOLOGY
Page Name
Power ON/OFF Timing
Size Project Name Rev
A2 N01 B
Date: Wednesday, July 16, 2008 Sheet 42 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
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