THIRUVALLUVAR COLLEGE OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

EC 6601-VLSI DESIGN
ASSESMENT TEST – II

Total Marks: 100

PART-A (10X2=20)
1. State the advantages of transmission gates
2. Define Elmore’s constant
3. List the sources of static and dynamic gates
4. What is the value of Vout for the figure shown below Where Vth is threshold voltage of
transistor

5. Why single phase dynamic logic structure cannot be cascaded? Justify.

6. List the types of power dissipation
7. Give Elmore delay expression for propagation delay of an inverter.

8. Compare combinational and sequential circuit

9. What do you meant by lumped RC model?
10. List the advantages of CMOS structure.

PART-B ( 8X10=80)

1. Draw the CMOS logic circuit for the Boolean expression Z=[A(B+C)+DE]’ an explain
2. Explain the basic principle of transmission gate in CMOS design
3. Explain the domino logic with neat diagram
4. Discuss the low power design principle in detail
5. Write short notes on Ratioed circuits
6. Discuss about dynamic CMOS circuits
7. Explain the dynamic power dissipation in CMOS circuits with necessary diagrams and
expression
8. Estimate least delay and determine input capacitance of each stages for the logic
network shown in fig , which may be represent the critical path of a more complex logic
block this output of the network is loaded with capacitance which is 5 time larger than
the input capacitance of the first stage which is a minimum sized inverter
 THIRUVALLUVAR COLLEGE OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
EC 6601-VLSI DESIGN
ASSESMENT TEST – II

Total Marks: 100

PART-A (10X2=20)
1. State the advantages of transmission gates
2. Define Elmore’s constant
3. List the sources of static and dynamic gates
4. What is the value of Vout for the figure shown below Where Vth is threshold voltage of
transistor

5. Why single phase dynamic logic structure cannot be cascaded? Justify.

6. List the types of power dissipation
7. Give Elmore delay expression for propagation delay of an inverter.

8. Compare combinational and sequential circuit

9. What do you meant by lumped RC model?
10. List the advantages of CMOS structure.

PART-B ( 8X10=80)

9. Draw the CMOS logic circuit for the Boolean expression Z=[A(B+C)+DE]’ an explain
10. Explain the basic principle of transmission gate in CMOS design
11. Explain the domino logic with neat diagram
12. Discuss the low power design principle in detail
13. Write short notes on Ratioed circuits
14. Discuss about dynamic CMOS circuits
15. Explain the dynamic power dissipation in CMOS circuits with necessary diagrams
and expression
16. Estimate least delay and determine input capacitance of each stages for the logic
network shown in fig , which may be represent the critical path of a more complex logic
block this output of the network is loaded with capacitance which is 5 time larger than
the input capacitance of the first stage which is a minimum sized inverter