Tidue89a PDF

TI Designs: TIDA-01040
Battery Tester Reference Design for High Current

Applications
Description Features
Li-Ion battery formation and electrical testing require • Battery test subsystem with calibration control
accurate voltage and current control, usually to better achieving 0.01% full scale current control accuracy
than ±0.05% over the specified temperature range. • Supports up to 50-A applications with an input
This reference design proposes a solution for high- voltage (bus) from 8 V–16 V and output load
current (up to 50 A) battery tester applications (battery) from 0 V–4.5 V (5 V max)
supporting input (bus) voltages from 8 V–16 V and • LM5170 bidirectional buck, boost controller
output load (battery) voltages from 0 V–5 V. The
design utilizes TI's integrated multi-phase bidirectional • Programmable high-precision reference supplied by
controller, LM5170, combined with TI's high precision DAC80004
data converters and instrumentation amplifiers to • Voltage and current monitoring provided by the
achieve charge and discharge accuracies of 0.01% full ADS131A04 24 bit delta-sigma
scale. To maximize battery capacity and minimize • User-friendly control interface
battery formation time, the design uses highly-accurate
constant current (CC) and constant voltage (CV) Applications
calibration loops with a simplified interface. All key
design theories are described guiding users through • Battery test equipment
the part selection process and optimization. Finally,
schematic, board layout, hardware testing, and results
are also presented.
Resources
TIDA-01040 Design Folder

LM5170-Q1, LM2664, TPS709 Product Folder
LM5118 Product Folder
INA188 Product Folder
DAC80004 Product Folder
ADS131A04 Product Folder
TLV07, OPA2227, OPA827, THS4561,
Product Folder
LM6142
ASK Our E2E™ Experts
Vbus LM5118
10V
TPS70960
5V
Vbattery
LM2664M6
-5V BATTERY
UNDER TEST
Vbus: 8-16V High Precision Vbattery: 0-5V
CS
DIR=_1"
Lm Rcs
DIR=_0"
PGND
SN74LV4053 DIR
VIN HO1 LO1 LM5170 CSA1 CSB1

+
-
1 1
DIR INA188 OPA827
DIR 0 0
DIR
D (1-D) D
Gm COMP1
VINX PWM
RAMP1
Vramp - THS4561 REF5025
+ - +
+ -
CLK1 OPA827
- ADS131A04
ISETA - +
TLV07 + + -
CC ERR AMP
ISET CC
AGND THS4561
RAMP2
CONTROL
Vramp TIVA
CLK2
PWM
D (1-D) D
Gm
COMP2
-
DIR 1
0
1
0
+ REF5050 USB2ANY
OPA2277_A
LO CSB
DAC80004
EN1=1
DIR=1
-
Lm Rcs -
DIR=_1" +
LM6142_B +
DIR=_0" OPA2277_B
VSET CV
CV ERR AMP CONTROL
LM6142_A
+ EN1=1
- DIR=0
TIDUE89A – June 2018 – Revised September 2018 Battery Tester Reference Design for High Current Applications 1
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Copyright © 2018, Texas Instruments Incorporated
System Description www.ti.com
An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other
important disclaimers and information.
1 System Description
Demand for Li-Ion batteries continues to grow at an exponential pace. Battery formation and testing is an
important manufacturing step to maximize battery life and storage capacity requiring multiple charge and
discharge cycles. During these cycles, battery current and voltage must be precisely controlled. The TIDA-
01040 reference design provides an easy-to-design solution utilizing high accuracy constant current (CC)
and constant voltage (CV) calibration loops to achieve up to 0.01% full scale charge and discharge current
control accuracy. This solution supports charge and discharge rates of up to 50 A and provides a high-
precision DAC and ADC to regulate and monitor the battery voltage and current . Furthermore, the flexible
solution provides an option for additional higher current and multi-phase applications.
1.1 Li-Ion Formation

The Li-Ion battery manufacturing process includes electrode production, stack and jelly-roll construction,
cell assembly and end-of-line conditioning. Figure 1 shows a simplified Li-Ion battery manufacturing
process. Formation and testing at the end-of-line conditioning step are the process bottlenecks, limiting
throughput. To maximize battery life, quality and performance, battery test equipment must possess
accurate voltage and current control, often better than ±0.05%, over the specified temperature range.
Electrode Coating Cell Assembly Formation

x Mixing x Stacking/Wingding x Labelling
x Coating x Connect Electrodes x Formation
x Compressing x Insert Electrode Stack x Storage Aging
x Drying x Sub Assembly x Acceptance Testing
x Slitting x Heat Seal/Weld x Packing Shipping
Figure 1. Simplified Li-Ion Battery Manufacturing Process
Some battery test equipment has adopted linear regulators to easily meet the accuracy requirements of
formation and testing of batteries used in portable equipment, while compromising on efficiency. On larger
batteries, this approach will have challenges with heat management and efficiency. Switching regulators
have been widely used in battery test equipment for their better performance in efficiency and heating
management.
1.2 Li-Ion Battery Formation Profile

Figure 2 shows the typical Li-Ion battery formation profile which is similar to the battery charging profile.
This process can be divided into three phases: initial process, CC, and CV. At first, a small initial charge of
around 10% of the full-charge current is applied. This prevents the cell from overheating until such a time
that it is able to accept the full current of the constant-current phase. In reality, this phase is rarely needed
because most modern mobile devices are designed to shut down while there is still some charge left
because deep discharge, like overcharging, can damage the cell.
2 Battery Tester Reference Design for High Current Applications TIDUE89A – June 2018 – Revised September 2018
www.ti.com System Description
Voltage
4.2 V/4.35 V/Cell
Current
3.0 V/Cell
Initial CC CV
Figure 2. Regular Li-Ion Battery Formation Profile
Then, the battery is typically charged at a CC of 0.5 A. (typical) or less until the battery voltage reaches
4.1 or 4.2 V (depending on the exact electrochemistry). When the battery voltage reaches 4.1 or 4.2 V
(typical), the charger switches to a constant voltage phase to eliminate overcharging. Superior battery test
equipment manages the transition from CC to CV smoothly to ensure maximum capacity is reached
without risking damage to the battery. At higher charge current, the transition between CC and CV occurs
earlier, because the cell voltage is higher due to the voltage drop across the internal resistance of the cell,
and therefore the CV voltage is reached sooner.
1.3 Key System Specifications
Table 1. Key System Specifications

PARAMETER SPECIFICATIONS DETAILS
Vbattery_min 0V Battery-port minimum operating voltage
Vbattery_normal 4.2 V Battery-port normal operating voltage
Vbattery_max 5V Battery-port maximum operating voltage
Vbus_min 8V Bus-port minimum operating voltage
Vbus_normal 12 V Bus-port normal operating voltage
Vbus_max 16 V Bus-port normal operating voltage
FSW 100 kHz Switching frequency
Imax 25 A Maximum DC current per phase, bidirectional
ITotal_max 50 A Total maximum DC current at battery-port
Current control accuracy 0.01% Full-scale current control accuracy for charge and discharge
System Overview www.ti.com
2 System Overview
2.1 Block Diagram

Vbus LM5118
10V
TPS70960
5V
Vbattery
LM2664M6
-5V BATTERY
UNDER TEST
Vbus: 8-16V High Precision Vbattery: 0-5V
CS
DIR=_1"
Lm Rcs
DIR=_0"
PGND
SN74LV4053 DIR
VIN HO1 LO1 LM5170 CSA1 CSB1
+
-
1 1
DIR INA188 OPA827
DIR 0 0
DIR
D (1-D) D
Gm COMP1
VINX PWM
RAMP1
Vramp - THS4561 REF5025
+ - +
+ -
CLK1 OPA827
- ADS131A04
ISETA - +
TLV07 + + -
CC ERR AMP
ISET CC
AGND THS4561
RAMP2
CONTROL
Vramp TIVA
CLK2
PWM
D (1-D) D
Gm
COMP2
-
DIR 1
0
1
0
+ REF5050 USB2ANY
OPA2277_A
LO CSB
DAC80004
EN1=1
DIR=1
-
Lm Rcs -
DIR=_1" +
LM6142_B +
DIR=_0" OPA2277_B
VSET CV
CV ERR AMP CONTROL
LM6142_A
+ EN1=1
- DIR=0
Figure 3. TIDA-01040 Block Diagram
In this reference design, LM5170 is a buck-boost controller which charges or discharges the battery
depending on the "DIR" setting. The high precision current sense amplifier monitors the charging or
discharging current. SN74LV4053 is a 2-channel CMOS analog multiplexer/demultiplexer which converts
the bidirectional signal into a single directional signal. The INA188 device is high-precision instrumentation
amplifier which amplifies the cross voltage of the high-precision current sensor with low noise. TLV07 is an
error amplifier that compares the current with the reference control signal. LM6142 is a two-channel error
amplifier which compares the battery voltage or bus voltage with the reference control signal. "EN1" and
"DIR" signals enable the calibration of the bus voltage in boost mode or the battery voltage in buck mode.
Two OPA827 devices operate as buffers between the main control system and data acquisition system.
THS4561 is a differential amplifier which converts the single ended measurement signals to differential
signals. ADS131A04 is a four-channel, 24-bit delta-sigma ADC which monitors the current and voltage of
the battery. DAC80004 is a four-channel, 16-bit high precision DAC that provides reference control signals
to the CC and CV control with a two-channel amplifier OPA2277. There is also an onboard TIVA
processor that communicates between the ADS131A04 device and the PC. The USB2ANY interface
adaptor communicates between the DAC80004 device and the PC.
www.ti.com System Overview
2.2 Highlighted Products
2.2.1 LM5170-Q1
The LM5170-Q1 controller provides the essential high voltage and precision elements of a dual-channel
bidirectional converter for automotive 48-V and 12-V dual-battery systems. The controller regulates the
average current flowing between the high- and low-voltage ports in the direction designated by the DIR
input signal. The current regulation level is programmed through analog or digital PWM inputs. Dual-
channel differential current sense amplifiers and dedicated channel current monitors achieve typical
current accuracy of 1%. Robust 5-A half-bridge gate drivers are capable of driving parallel MOSFET
switches delivering 500 W or more per channel. The diode emulation mode of the synchronous rectifiers
prevents negative currents but also enables discontinuous mode operation for improved efficiency with
light loads. Versatile protection features include cycle-by-cycle current limiting, overvoltage protection at
both HV and LV ports, MOSFET failure detection, and overtemperature protection. An innovative average
current mode control scheme maintains constant loop gain allowing a single R-C network to compensate
both buck and boost conversion. The oscillator is adjustable up to 500 kHz and can synchronize to an
external clock. Multiphase parallel operation is achieved by connecting two LM5170-Q1 controllers for
three- or four-phase operation, or by synchronizing multiple controllers to phase-shifted clocks for a higher
number of phases. A low state on the undervoltage lockout (UVLO) pin disables the LM5170-Q1 device in
a low-current shutdown mode.
2.2.2 LM5118
The LM5118 wide voltage range buck-boost switching regulator controller features all of the functions
necessary to implement a high-performance, cost-efficient buck-boost regulator using a minimum of
external components. The buck-boost topology maintains output voltage regulation when the input voltage
is either less than or greater than the output voltage, making it especially suitable for automotive
applications. The LM5118 operates as a buck regulator while the input voltage is sufficiently greater than
the regulated output voltage and gradually transitions to the buck-boost mode as the input voltage
approaches the output. This dual-mode approach maintains regulation over a wide range of input voltages
with optimal conversion efficiency in the buck mode and a glitch-free output during mode transitions. This
easy-to-use controller includes drivers for the high-side buck MOSFET and the low-side boost MOSFET.
The regulators control method is based upon current mode control using an emulated current ramp.
Emulated current mode control reduces noise sensitivity of the pulse-width modulation circuit, allowing
reliable control of the very small duty cycles necessary in high-input voltage applications. Additional
protection features include current limit, thermal shutdown and an enable input. The device is available in
a power-enhanced, 20-pin HTSSOP package featuring an exposed die attach pad to aid thermal
dissipation.
2.2.3 TLV07
The TLV07 device is a 36-V, single-supply, low-noise, precision operational amplifier (op amp)
manufactured using TI’s laser trim operational amplifier technology. The input offset voltage of each
amplifiers is trimmed in production to obtain a low offset voltage of 100 µV (maximum). The TLV07 device
offers outstanding DC precision and AC performance, including rail-to-rail output, low offset voltage (±100
µV, maximum) and 1-MHz bandwidth. The TLV07 device is stable at G = 1, with capacitive loads up to
200 pF. The input can operate 100 mV below the negative rail and within 2 V of the positive rail. This wide
input voltage range, combined with a high CMRR of 120 dB, make the TLV07 well-suited when operated
in the non-inverting configuration.
Features:
• Low offset voltage: 100 µV (maximum)
• Rail-to-rail output
• Low noise: 19 nV / √Hz
• Unity-gain stable
• RFI filtered inputs
• Input range includes negative supply
• Gain bandwidth: 1 MHz
• Low quiescent current: 930 µA
• Full industrial temperature range: –40°C to +125°C
• Offered in the industry-standard 8-Pin SOIC package
2.2.4 LM6142
Using patent pending new circuit topologies, the LM6142 and LM6144 devices provide new levels of
performance in applications where low voltage supplies or power limitations previously made compromise
necessary. Operating on supplies of 1.8 V to over 24 V, the LM6142 and LM6144 devices are an excellent
choice for battery operated systems, portable instrumentation and others. The greater than rail-to-rail input
voltage range eliminates concern over exceeding the common-mode voltage range. The rail-to-rail output
swing provides the maximum possible dynamic range at the output. This is particularly important when
operating on low supply voltages. High gain-bandwidth with 650 μA per amplifier supply current opens
new battery-powered applications where previous higher power consumption reduced battery life to
unacceptable levels. The ability to drive large capacitive loads without oscillating functionally removes this
common problem.
2.2.5 OPA2277
The OPAx277 series precision operational amplifiers replace the industry standard OP-177. They offer
improved noise, wider output voltage swing, and are twice as fast with half the quiescent current. Features
include ultra-low offset voltage and drift, low bias current, high common-mode rejection, and high power
supply rejection. Single, dual, and quad versions have identical specifications, for maximum design
flexibility.
The OPAx277 series operational amplifiers operate from ±2-V to ±18-V supplies with excellent
performance. Unlike most operational amplifiers which are specified at only one supply voltage, the
OPAx277 series is specified for real-world applications; a single limit applies over the ±5-V to ±15-V
supply range. High performance is maintained as the amplifiers swing to their specified limits. Because the
initial offset voltage (±20 µV maximum) is so low, user adjustment is usually not required. However, the
single version (OPA277) provides external trim pins for special applications.
The OPA277 operational amplifiers are easy to use and free from phase inversion and the overload
problems found in some other operational amplifiers. They are stable in unity gain and provide excellent
dynamic behavior over a wide range of load conditions. Dual and quad versions feature completely
independent circuitry for lowest crosstalk and freedom from interaction, even when overdriven or
overloaded.
2.2.6 INA188
The INA188 is a precision instrumentation amplifier that uses TI proprietary auto-zeroing techniques to
achieve low offset voltage, near-zero offset and gain drift, excellent linearity, and exceptionally low-noise
density (12 nV/√Hz) that extends down to DC. The INA188 device is optimized to provide excellent
common-mode rejection of greater than 104 dB (G ≥ 10). Superior common-mode and supply rejection
supports high-resolution, precise measurement applications. The versatile three op-amp design offers a
rail-to-rail output, low-voltage operation from a 4-V single supply as well as dual supplies up to ±18 V, and
a wide, high-impedance input range. These specifications make this device ideal for universal signal
measurement and sensor conditioning (such as temperature or bridge applications). A single external
resistor sets any gain from 1 to 1000. The INA188 device is designed to use an industry-standard gain
equation: G = 1 + (50 kΩ / RG). The reference pin can be used for level-shifting in single-supply operation
or for an offset calibration.
2.2.7 DAC80004
The DAC80004, DAC70004, and DAC60004 (DACx0004) family of devices are highly accurate, low-
power, voltage-output, quad-channel, 16-, 14-, and 12-bit DACs respectively. The DACx0004 devices are
ensured monotonic by design and offer excellent linearity of less than 1 least-significant bit (LSB),
maximum. The reference input of the DAC is buffered internally using a dedicated reference buffer. The
DACx0004 devices incorporate a power-on-reset circuit that ensures the DAC output powers up at zero
scale or mid scale depending on status of the POR pin and remains in this state until a valid code is
written to the device. These devices consume very low current of 1 mA per channel making them ideal for
portable, battery-operated equipment. These devices also contain a power-down feature that reduces
current consumption to typically 3 µA at 5 V. The DACx0004 devices use a versatile 4- or 3-wire serial
interface that operates at clock rates up to 50 MHz. The DACx0004 devices also include an SDO pin to
daisy chain multiple devices. The interface is compatible with standard SPI™, QSPI™, MICROWIRE™,
and digital-signal processor (DSP) interfaces. The DACx0004 devices are offered in easy-to-assemble 14-
pin TSSOP packages or an ultra small 14-pin VSON package and are fully specified over the extended
industrial temperature range of –40°C to 125°C.
2.2.8 ADS131A04
The ADS131A04 is a 4-channel, simultaneously sampling, 24-bit, delta sigma ADC. Wide dynamic range,
scalable data rates, and internal fault monitors make the ADS131A04 ideally suited for energy monitoring,
protection, and control applications. Flexible power-supply options are available to maximize the effective
number of bits (ENOB) for high dynamic range applications. Asynchronous and synchronous master and
slave interface options are available, providing ADC configuration flexibility when chaining multiple devices
in a single system.
Features:
• Four simultaneously sampling differential inputs
• Data rates up to 128 kSPS
• Noise performance:
– Single-channel accuracy better than 0.1% at 10000:1 dynamic range
– ENOB: 19.1 bits at 8 kSPS
– THD: –100 dB at 50 Hz and 60 Hz
• Integrated negative charge pump
• Flexible analog power-supply operation:
– Negative charge pump: 3.0 to 3.45 V
– Unipolar supply: 3.3 to 5.5 V
– Bipolar supply: ±2.5 V
• Digital supply: 1.65 to 3.6 V
• Low-drift internal voltage reference: 4 ppm/°C
• ADC self checks
• Cyclic redundancy check (CRC) and hamming code error correction on communications
• Multiple SPI data modes:

– Asynchronous interrupt
– Synchronous master and slave
• Package: 32-pin TQFP
• Operating temperature range: –40°C to 125°C. Find more information at the product page of the
device: ADS131A04
2.2.9 THS4561
The THS4561 fully differential amplifier (FDA) offers a simple interface from single-ended sources to the
differential output required by high-precision ADCs. Designed for exceptional DC accuracy, low noise, and
ultra-low harmonic distortion, the device is well suited for data acquisition systems where high precision is
required with the best signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) through the
amplifier and ADC combination.
The THS4561 features the required negative rail input when interfacing a DC-coupled, ground-centered,
source signal to a single-supply, differential-input ADC. Very low DC error and drift terms support the
emerging 16-bit to 20-bit successive approximation register (SAR) input requirements. A 2.85-V to 12.6-V
supply range with a flexible output common-mode setting with low headroom to the supplies supports a
wide range of ADC input and DAC output requirements.
2.3 System Design Theory
2.3.1 Constant Current Control Design

For CC control, a high precision current sensor with low inductance and temperature coefficient is
necessary. The WSL2726 and WSLP2726 serial resistors are welded constructions of power metal strips
which are ideal for current sensing with 1% tolerance, maximum 75 ppm/°C temperature coefficient, 0.5-
nH to 5-nH inductance and less than 20-dB element TCR. See WSL2726 and WSLP2726 for detailed
parameters.
A mux is used to manage the bidirectional current when charging or discharging. This design uses the
SN74LV4053A, a triple 2-channel analog multiplexer/demultiplexer.
The next stage of the CC control loop chain is a zero-drift instrumentation amplifier INA188. This stage
amplifies the current signal across the current sensor with low noise and low output impedance.
For the instrumentation amplifier, the common-mode voltage affects the input and output range limitation.
The Vcm vs Vout Calculator for Instrumentation Amplifier design tool enables designers to easily
determine the input common-mode and output swing limitations of the chosen instrumentation amplifier to
ensure dynamic range and minimize prototyping time.
Figure 4. Vcm vs Vout Calculator for INA188
Figure 4 highlights the calculation results of the INA188 input and output range for this reference design.
In this case, the maximum common mode voltage is the same as the maximum voltage on the battery
side, so its maximum value is 5 V. When the INA188 is powered by 10 V and –5 V, and the gain is
configured at 44.48, the calculation results show the input range is from –107.5 mV to 214.9 mV. It fits
within the current signal range (±50 A × 1 mΩ = ±50 mV).
The CC control loop needs a high-precision error amplifier to calibrate to the target signal. TLV07 is a low-
noise, precision operational amplifier whose maximum offset voltage is less than ±100 µV and has a 1-
MHz bandwidth.
Due to the high current of this application, the high temperature will have an effect on the performance of
this board. The input offset voltage drift is a key parameter to consider when choosing the amplifier. The
input offset voltage drift of the TLV07 device is only 0.9 µV/°C. The maximum input offset voltage at 125°C
is: 0.9 µV × 125 = 112.5 µV. In the worst-case 50-A application, this input offset voltage will cause an error
of 112.5 µV / (50 A × 0.001 × 44.48) × 100% = 0.005058% on the control loop. This error is less than the
0.01% demanded accuracy, so the TLV07 device is a suitable amplifier.
9IE &7
9
9
9 9*
&Q
/7
9R
9
87/9
&Q
5N
9
Figure 5. TLV07 TINA-TI Stability Schematic
Figure 5 highlights the schematic used to test the stability of the TLV07 device. The TINA-TI schematic in
Figure 5 features a 1TF capacitor and 1TH inductor for simulation purposes. This is used to break the
feedback loop as the capacitor will be an open at DC while the inductor is a short. At high frequencies, the
inductor will be an open and the capacitor will be a short. The load the TLV07 device experiences at the
next stage of the system was also added on the right side of the schematic. This allows for the proper
simulation of the stability of the circuit.
Figure 6. TLV07 TINA-TI Stability Simulation Results
Figure 6 highlights the results from the TLV07 stability simulation including a phase margin of > 62°, which
implies stability. It is also important to consider the rate of closure between the loop gain and loaded open-
loop gain curves. The loaded open-loop gain curve is decreasing at –20 dB per decade at the point of
intersection with the noise gain curve. The noise gain curve is flat, meaning it is at 0 dB per decade. The
rate of closure is thus 20 dB per decade. For a circuit to be considered stable, the rate of closure has to
be less than 40 dB per decade. For more information about amplifier stability, see TI's Precision Labs - Op
Amps.
To verify the power stage and control stability, this reference design has adopted SIMetrix®/SIMPLIS® to
build simulation modes to verify the control performance.
Figure 7 shows the CC control simulation schematic. To keep the system working in CC control mode, V4
provides a DC voltage for D4 to conduct all the time. ISET1 and ISET2 capture the differential voltage
across the current sense resistor, E1 is an ideal differential amplifier to output a single-ended signal, R16
and C19 create a low pass filter, and X6 is the error amplifier used to calibrate the current signal to the
reference signal.
10p
C22
1k 100n
R29 C18
REF5V
44.48 AC 10m 0 X6
499
ISET1 CC_err
R16
V2
ISET2
LG_OUT LG_IN
E1 C19
IREF
10n
VN5
D4
2k
ISETA
R30
D1n4148
R20
ISETA
ISETA IREF
20k
2.224
5
R15 V1
V5
V4
10k 5
VN5
Figure 7. Constant Current Control Simulation Schematic
Figure 8 shows the transient simulation result. The "ISETA" pin is clamped to 1.67 V by V4 after power on.
With the increase of current, the output of error amplifier X6 decreases, and the CC control circuit takes
the control of the system. The final steady current is 50 A, in line with design parameters.
Figure 8. Constant Current Control Transient Simulation Results
Figure 9 shows the small signal performance of this CC control subsystem. The gain crossover frequency
is 22.15 kHz, and the phase margin is 69.57° which means this control circuit is stable and can provide
enough bandwidth.
Figure 9. CC Small Signal Simulation Results
2.3.2 Constant Voltage Control Design

For CV control, the bus voltage at boost mode needs to be monitored, so logic control is used to enable
the bus side at boost mode or battery side at buck mode. The buck-boost controller uses the "DIR"
command pin to set the work mode. This reference design uses the SN74LV1T00 and SN74LV1T32
devices to enable the different voltage sides.
The LM6142 device is dual high-speed and low-power amplifier that is used for calibrating the battery or
bus voltage with the reference control signal. The input offset drift is 3 µV/°C. At the worst case, 5-V
output voltage and 125°C, this drift will case 3 µV × 125 / (5 V × 26.7 / 31.12) × 100% = 0.008741157%
accuracy error, which can meet the demand of 0.01% accuracy.
For CV control simulation, remove the current control subsystem. Figure 10 shows the CV control
schematic. R20 and R15 determine the maximum DC current of the system, C12, R2, C20, R19, and C13
consist of a type Ⅲ compensator to provide enough bandwidth and phase margin. See Demystifying Type
Ⅱ and Type Ⅲ Compensators Using Opamp and OTA for DC/DC Converters for design theory details.
4V5_Vbatt
LG_OUT
V2 VREF
AC 10m 0
10p 3.86
LG_IN V4 V5
C20 5
R19 100n
C12 1k C13 VN5
100p R21 REF5V
R2 4.42k
20k CV_err
X8
R20
ISETA ISETA
R14 20k
26.7k
VN5 R15
10k
R18
VREF
10k
Figure 10. Constant Voltage Control Simulation Schematic
Figure 11 shows the transient performance of this subsystem. The final battery voltage is controlled by the
reference voltage, as expected.
Figure 11. Constant Voltage Control Transient Simulation Results
Figure 12 and Figure 13 show the steady state and small signal performance under CV control. The gain
crossover frequency is 1.01 kHz, and the phase margin is 79.22°, which means the CV control loop is
steady.
Figure 12. CV Steady State Simulation Results
Figure 13. CV Small Signal Simulation Results
2.3.3 System Simulation

Figure 14 shows the whole system simulation schematic. CC control and CV control are connected together with R20, R15, D4 and R30. A battery
is simulated with the R12Load and C14.
10p
Current Loop
12Vbatt
C22
60lq100
SW1
4V5_Vbatt 1k 100n
ISET1 ISET2
D1
S1 R29
1.9m 6.8u 1m 1m C18
VBat
IBat REF5V
Rbrk L1 Rsn Rsn4
RSS2 ESR3 HO1 RSS 44.48 X6

499
ESR1
10m 2m 100u
R48Load ESR2 R12Load ISET1
500u R16
CSA1 CSB1 500u
I1 + ISET2
1u 10m
D9 VSTO C11 S2 C19
LO1 E1 IREF
+ D2 VBATT
60lq100 12 66u IC=0 10n
RSS3 C7 +
60lq100 4.5
C4 C14 VN5
500m 286u IC=0
360u IC=0 100m
nDIR DIR nDIR
S6 S5 S4
D4
2k
CC_err
ISETA
R30
D1n4148
ISETA
D3
12Vbatt
1n IC=0
D1n4148
+
C16
IOUT1
D8
SYNCO
VCC IOUT2
VOSC1
D1n4148 IREF VREF
R10 DIR EN2 ISETD EN1
D10 V5
15k
CLK 2.224 3.86
5
D1n4148 V1 V4
U1
DT AGND OSC_SYNCI ISETA DIR EN2 ISETD SYNCO EN1 IOUT2 IOUT1 4V5_Vbatt
CSA2 CSA2 CSA1 CSA1 10p VN5
CSB2 CSB2 CSB1 CSB1

R7
VINX C20
BRKG
VINX R6 10k
R19 100n
BRKS
10k
C12
1k C13
R4 VCC R21
VIN 100p
Ramp2 REF5V
VCCA 4.42k
R2
96k 24.9
IPK 20k
CV_err
RAMP2 X8
R3
OPT
Cramp2 96k + R20
OVPA 100k
C1 ISETA
1n IC=0 RAMP1 ISETA
R14
UVLO UVLO Ramp1 1u IC=0 20k
R9 +
nFAULT 26.7k
Cramp1
53.5k COMP2
COMP1 1n IC=0 VN5 R15
SS VINX
OVPB 10k
+
R8 C2 R5 R50
+ SW2 HB2 HO2 LO2 PGND VCC LO1 HO1 HB1 SW1 +
10n
634 IC=0 634 1G
C8 R1 C5 R18
1n IC=0 C23 31.6k 1n IC=0 VREF
+ + 10k
C9 C24 C6
+
47n IC=0 220n IC=0 47n IC=0

+
220n IC=0 X2
HB2 LO2 LO1 HB1 CLK
R28
D5 D6
10k 60lq100 60lq100
R35
VCC
C10 REF5V
10k DIR UVLO EN1 EN2 U3
C25
IOUT1 IOUT2
DIR
+
2n IC=0 VCC
nDIR
+
2n IC=0 + +
VCC R11 C32 R12 C3
SW2 HO2 HO1 SW1
VCC1
10 9.09k 10n IC=0 9.09k 10n IC=0
5
SW2
60lq100
12Vbatt
D12
S10
6.8u 1m
ISET1
L3 Rsn2
CSA2 CSB2
HO2
S11
LO2 D13
60lq100
Figure 14. TIDA01040 System Simulation Schematic
Figure 15 shows the transient performance of this system. After power on, due to the low voltage at this
time, the CV loop outputs high voltage. It provides enough DC voltage for D4 to conduct, and the CC
control loop starts taking control of the whole system at about 2 ms. The current keeps a constant 50 A
and the battery voltage increases with time. At about 9 ms, the battery voltage reaches near 4.5 V. After
this time, the CV control error amplifier decreases the output voltage and it gets the control of the system.
The battery current then decreases and the battery voltage keeps steady after the switch from CC control
to CV control.
Figure 15. TIDA01040 System Transient Simulation Results
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3 Hardware, Software, Testing Requirements, and Test Results
3.1 Hardware Design
3.1.1 Power Bias

Figure 16 shows the power bias subsystem which supports power for the whole system whether in charge
or discharge mode. LM5170 needs a bias voltage of about 10 V, and the amplifiers need ±5 V to calibrate
the control signal. The LM5118 device is a wide input, current mode nonsynchronous buck-boost
controller which connects to the high- or low-voltage side manually depending on the mode. This is able to
provide 10 V for the LM5170 device, LDOs, and switched capacitor voltage converter. In this reference
design, U3 and U4 are used to provide isolated 5.0 V to the control subsystem and DAQ subsystem.
U3
R10 1 5 R164
IN OUT V5.0_Control
1.00k 0
U7 V-5
-5V
5 2 3 4
V5.0_Control V+ OUT EN NC
C34 C35
2
1
6 4 1µF 1µF
C1+ SD
C77 3 1 2
C1- GND GND
1uF
C76 C78 J16
1uF PM-CHP-LM2664M6-6 1uF TPS70950DBVR
AGND
AGND AGND
U4
1 5 R165
IN OUT V5.0_DAQ
0
3 EN NC 4
C36
1µF
C37
2 1µF
GND
V_HV
AGND TPS70950DBVR
J21
3 AGND
2
1
HTSW-103-07-G-S
C38
22µF C39 C40
0.1µF
V_LV 10µF
5,6,
7,8
Q14
SI7454DDP-T1-GE3
4
1,2,3
J4
V10-Aux
C41
PGND R53 U5
1
2
20.0k 1 18 0.1µF
VIN HB L3
2 19 D6
UVLO HO
4 EN HS 20
UVLO V10
MSS1278-473MLB
7 12 B530C-13-F
SS CS
C42
5 13 C43
5,6,
RAMP CSG
7,8
Q15 2.2µF
J23 180µF
SI7454DDP-T1-GE3
3 3 RT LO 15 4
2
1,2,3
1 11
SYNC VOUT
10
HTSW-103-07-G-S 8 D7 PGND PGND

FB CDBC5100-G
C49
C44 C45 R46 17 9
VCCX COMP
0.1µF 330pF 18.2k 16 VCC
6 1500pF PGND
AGND
AGND 21 EP PGND 14
C47 C48 C46 R47
1µF 1µF LM5118MH/NOPB R48 0.068
24.0k
0.056µF
PGND
PGND
NT2
Net-Tie
PGND R49 R50 R51
AGND 7.32k 52.3k 10.0
AGND
Figure 16. Power Bias Subsystem
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3.1.2 Main Power Convert Stage

Figure 17 shows the power stage. The power stage can be set to buck or boost mode using the LM5170
device. The two same power stages were connected in parallel to work in higher current applications, as
with the parallel MOSFETs. R21, R16, and R22 are high-power current sensing resistors whose
temperature coefficients are ±75 ppm/°C. R21 and R22 are used to monitor the current per channel to
balance the safety current, while R16 was used to detect the total two phase current to the CC control
loop and ADC. The parallel input and output capacitors provide low ESR with enough capacitance. The
detailed design guide is found in LM5170-Q1 Multiphase Bidirectional Current Controller. This proposed
solution can support higher power or current by employing larger inductors, high power MOSFETs, and
smaller current sense resistors.
SW1
V_HV Q1
TK65G10N1,RQ L1
CS1 CS2
4 3 R21
74436410470
Q2 Q3 4.7uH 0.001 C79
R22 TK65G10N1,RQ TK65G10N1,RQ
4
1
C56 C57 C58 C50 C51 C18 49.9k

39µF 39µF 39µF 39µF 39µF 100µF 1 1 0.01uF
R61 R62
10.0k 10.0k
3
C85
R24 R25 R56 R57
49.9k 49.9k 1.0 1.0
Q4 0.01uF
TK65G10N1,RQ R63 R64
R26 10.0k 10.0k
4 3 1.00 R27 R28
PGND 1.00 PGND 1.00 PGND
R29 CS1B
1
49.9k
LO1
ISEN+
ISEN-
R30
HO1 CS1A
1.00
V_LV
J9 V_HV J10
V_HV V_LV
108-0740-001 108-0740-001
T1 T2
R16
CXS70-14-C 0.001 CXS70-14-C
C54 C55 C20 C21

C22 C23 C24 C25 C62 C63 C64 C65 C66 C67 C26 C27 C28 C29 180µF 180µF 180µF 180µF
4.7µF 4.7µF 4.7µF 4.7µF 4.7µF 4.7µF 4.7µF 4.7µF 4.7µF 4.7µF 4.7µF 4.7µF 4.7µF 4.7µF
R31 R42
1.0 1.0
T3
T4
CXS70-14-C
J11 PGND CXS70-14-C
J12
PGND ISEN-
108-0740-001
108-0740-001
ISEN+
PGND
V_LV
C68 C69 C70 C71

SW2 4.7µF 4.7µF 4.7µF 4.7µF
V_HV Q10
TK65G10N1,RQ L2
4 3 R32
74436410470
Q11 Q12 4.7uH 0.001
R33 TK65G10N1,RQ TK65G10N1,RQ
4
4
1
49.9k
C59 C60 C61 C52 C53 C32 1 1 PGND
39µF 39µF 39µF 39µF 39µF 100µF
3
R58 R59
R35 R36 1.0 1.0
49.9k 49.9k
R37
Q13 1.00
TK65G10N1,RQ
4 3 PGND PGND
PGND R38 R39
1.00 1.00 CS2B
R40
1
49.9k
LO2 CS2A
R41
HO2
1.00
Figure 17. Main Power Convert Stage Subsystem
3.1.3 LM5170 Subsystem

Figure 18 shows the LM5170 control schematic. See the LM5170-Q1 EVM User Guide and LM5170-Q1
Multiphase Bidirectional Current Controller Data Sheet for the detailed design guide. The DIR pin can be
used to choose either buck or boost mode. The FB pin delivers the control signal from the CC and CV
control loops to the LM5170 device. The SYNCOUT pin, OPT pin, and SYNCIN pin can be used for
further multiphase applications.
VINX
V_LV
R1
95.3k J1
3
J6 C1 2
1 1000pF 1 VINX C2 R3
2 R2 0.01µF 9.09k
DIR R4 634
3 HTSW-103-07-G-S
100k C3 AGND
Header_3x1 AGND 1000pF
J7 R5
UVLO C4
1 95.3k
2 0.015µF
EN1 C5 V_HV R161
3
1000pF DNP FB
V_HV 0
Header_3x1 R60
R6 4.70k IOUT1
J8
1 49.9k
CS1A
2 AGND
EN2 C6
3
1µF
Header_3x1 AGND C80
V5.0_Control C72 C73 0.47µF
U1
LM5170QPHPRQ1 100pF 100pF
10
26
37
36
35
AGND
4
CS1B
SYNCOUT
16 7
UVLO
VINX
COMP1
IOUT1
VIN
CSA1
CSB1
NC NC
AGND J3
EN1 SW1
2 AGND
1 R7 28 33 R156
RAMP1 BRKS SW1
10.0k R155 10.0k
HTSW-102-07-G-S 8 RAMP2 BRKG 34
10.0k C7 VCC
AGND 39 0.22µF
DIR EN1
AGND D1
VCC 48 22 R54
DT HO1 HO1
J2 2.0
1 2 R102 44 24 PMEG6010CEH,115
OPT DNP DIR SW1
3 4 10.0k
nFAULT R11
5 6 40 SYNCIN HB1 23 VCC
IOUT1 R12 10.0k SYNCIN
7 8
SYNCOUT 49.9k
9 10 41 SYNCOUT LO1 20
IOUT2 LO1 V10
11 12
FB R13
13 14 47
SYNCIN OPT OSC
15 16 40.2k C10
UVLO 2.2µF R14
17 18 J5 AGND 46 AGND VCC 19
OVPB 24.9
19 20 3
OVPA
2 29 31
OPT VCCA
PEC10DAAN 1 VCCA
43 EN2 PGND 18
EN2
AGND HTSW-103-07-G-S PGND
45 ISETA
AGND
42
ISETD HB2
14 PGND VCC
30 13 C11
IPK SW2
1µF
27 15 D2
FAULT HO2 HO2 R55
12 17 2.0
SS LO2 LO2
PMEG6010CEH,115AGND
COMP2
IOUT2
3 21
OVPB
OVPA
CSA2
CSB2
FB NC NC
DAP
R15 5 32 C12
NC NC
C13 40.2k C14 0.22µF
100pF 0.01µF SW2
25
49
38
9
11
2
SW2
AGND
nFAULT CS2B
AGND AGND
AGND
C81
0.47µF
OVPA C74 C75
IOUT2 100pF 100pF
R160
OVPB DNP FB CS2A
0
C15
0.015µF AGND
C82 R17 C83 R18 C16
100pF 51.1k 100pF 54.9k 1000pF C17 R20
R19 0.01µF 9.09k
634
AGND PGND
NT1
Net-Tie
AGND PGND
Figure 18. LM5170 Subsystem
3.1.4 CC Calibration Subsystem

Figure 19 shows the CC calibration subsystem. The SN74LV4053 device converts the bidirectional current to one direction to be used in the CC
control loop. When the DIR pin is high, the whole system works in buck mode. The current flows from "ISEN+" to "1-COM" to "1Y1" to "INA188" to
"2Y1" to "2-COM" to "ISEN–". Otherwise in boost mode, the current flows from "ISEN–" to "2-COM" to "2Y0" to "INA188" to "1Y0" to "1-COM" to
"ISEN+". INA188 is a zero-drift, rail-to-rail-out instrumentation amplifier, that converts the voltage from the current sensing resistor to a proper
value. The gain of the CC control loop is (1 + 2 × 25 kΩ / R70) = 44.48. R71 and C110 form a low-pass filter which can filter significant switching
noise from the MOSFETs. The output signal from the filter is compared with the current reference signal through an error amplifier with
compensation. At power up, the battery voltage is very low. The CV calibration loop outputs a high voltage to the FB pin. At this time, D3 starts to
conduct and the CC calibration loop takes control of the whole system.
Buffer
V10
V5
0.1uF V5 C106 C107 0.1uF
U9 0.1uF 10uF
U13 C111
R65 R68
7
C99 16 12 2 INA188 AGND IBAT
7
ISEN+ VCC 1Y0
499 AGND 1Y1 13 499 U14A
C100 11 C104 1 V+ AGND 2 OPA827AIDR
DIR A RG R72
0.015uF 10 2 0.015uF 6
B 2Y0 R71 LPF
9 1 R70 6 IBAT_P 3
C 2Y1 0
1.15k 499 R73
R67 REF 10.5
AGND 6 INH 3Y0 5 AGND 8 RG
4
3 V- C110
0 3Y1
5
14 R69 3 50V
R66 1-COM
15 7 499 0.01uF 0.1uF
4
ISEN- 2-COM GND IBAT
499 4 8 C105
3-COM GND
C103 0.015uF -5V C112 C113
0.015uF AGND 10pF
SN74LV4053ATPWRQ1 AGND
AGND AGND
AGND
-5V C108 C109
AGND 0.1uF 10uF AGND AGND
AGND
C114
10pF V5
C115
R82
1.00k C116 C117
0.1uF 0.1uF 10uF
7
Error AMP
U15A CC
IBAT_P R74 2 TLV07IDR AGND
V+ 6 R162
10.0k FB
3 V- 2.00k
R93 D3
IREF D5
10.0k
4
C121
C118 -5V 10pF
1uF
C119 C120 AGND AGND

AGND 0.1uF 10uF
AGND
Figure 19. CC Calibration Subsystem
3.1.5 CV Calibration Subsystem

Figure 20 shows the battery-side CV calibration subsystem. It needs to monitor the battery side in buck
mode and the bus side in boost mode. The logic components U10, U11, and U12 are controlled by the
EN1 and DIR signal from the LM5170 device. U2 is a dual-channel high-speed rail-to-rail amplifier which
acts as an error amplifier to calibrate the terminal voltage to the reference voltage. When the system
works in buck mode, with the increase of the battery voltage, the CV calibration loop starts taking control
of the whole system to keep the battery voltage equal to the VREF voltage. Q16 is opened by the startup
command (EN and DIR), which allows the VREF signal to rise up slowly. Adjust R84 and C90 values to
set the REF ramp up rate which affects the inrush current after power on.
0.1uF
V10
C96
AGND
C102
R101 VBAT J35
VSET 4.2VDC
20.0k U8A
7
100pF OPA827AIDR
C87 2
R76
1
2
6
V_LV
4.42k 3
CV 50V R52
C89 10pF R78 10.5
R163 R80
4
26.7k
FB VBAT
0 1.00k
50V C98 0.1uF
R81 0.1uF 100pF
10.0k U2B -5V C97
8
LM6142AIM/NOPB AGND AGND

D9 6 VREF_LV
7 V+ AGND
B R84
V- 5
VREF
1N4448WX-TP 1.00M
4
R86
10.0k R88 V5A
C90 20.0
16V
10uF
5
AGND U11
3
Q16 1 SN74LV1T00DBVR
DIR
1 4
2
EN
2N7002E-T1-E3
2
3
C93
0.1µF
AGND
AGND
V5A
R90
4.99k
2
BOOST MODE D11

Green
1
3
Q17
1
2N7002E-T1-E3
2
AGND
Figure 20. CV Calibration Subsystem
Figure 21 shows the system soft start waveform with R84 = 1 MΩ, C90 = 10 µF, and the current setting =
10 A. This result shows that the reference voltage ramps up slowly causing the "ISETA" signal to ramp up
slowly as well. This soft start circuit has sharply decreased the inrush current at power on.
Figure 21. Soft Start Waveform
There is another software method to achieve this soft start performance: increasing the voltage reference
signal slowly at power on instead of giving the final reference voltage immediately.
3.1.6 DAC Subsystem

Figure 22 shows the DAC subsystem, which provides the reference signals for the CC and CV calibration subsystem. The DAC80004 device is a
high-accuracy, low power 16-bit DAC. It can be controlled through the USB2ANY interface. The REF5050 device has great noise performance
which provides a 5-V reference voltage for DAC. The OPA2277 device is a high-precision, low-noise amplifier which works as a buffer and
changes the output range of the DAC subsystem.
In this schematic, all four channels are connected to the amplifiers to be used to calibrate the offset voltage of the amplifier to achieve better
calibration performance. In real applications, only two channels can be used to provide voltage and current reference control signals.
V5.0_DAQ
C126 C127
1uF 0.1uF
-5V
V10
C129 C130
AGND 1uF 1uF
DVDD_3.3V AGND AGND
C128
Host Interface R103
J17 0.1uF
10k
10 9 CLRn
SCLK 8 7 LDACn DAC80004 V10
6 5 AGND U17
SDIN 4 3 SDO
8
SYNCn 2 1 3 VDD SDO 8 SDO U18A
R104 10k 2 OPA2277U J18
IREF
Header_5x2 1 LDAC VOUTB 11 1 1 2
IREF
2 SYNC VOUTD 10 R105 10k 3 3 4
AGND 9
CLR VOUTC
5 5 6
13 SDIN VOUTA 4 7 8
VREF
4
U16A 14 SCLK
R106 VREF
VREF_DAC 802-10-008-10-001000
10k -5V
L4 600 ohm 2 VIN VOUT 6 R96 0.51 7 REFIN PAD 15
V10
5 12
TRIM/NR GND
6
POR
C122 3 4 C123 C124 C125
TEMP GND
R97 R98 R99 DACx0004DMD AGND AGND AGND
1uF 1uF 10uF 1uF
TI-REF5050D8 10k 10k 10k

U16B
DVDD_3.3V R107
AGND AGND AGND AGND AGND AGND 10k
NC 7
1
DNC
8
DNC
8
U18B
R108 10k 6 OPA2277U
7
R109 10k 5
4
R110
10k
AGND
Figure 22. DAC Subsystem
3.1.7 DAQ Subsystem

Figure 23 shows the DAQ subsystem that consists of the ADS131A04, THS4561, and REF5025 devices. The THS4561 device can convert the
single-ended signal of the battery current and voltage to differential signals and provide suitable gain to drive the ADC. The ADS131A04 device is
a 24-bit, 128-kSPS delta-sigma ADC that allows battery parameters to be viewed in the GUI. It uses an onboard MCU, TIVA4, to communicate
with the GUI.
DVDD_3.3V
Vocm1 Vocm2 AVDD AVDD AVDD
AVDD
V5.0_DAQ C133 C134 C135 C136 C137 C138 C139 C140 C141
0.22uF C131 0.22uF C132 0.1uF 1uF 0.1uF 1uF 0.01uF 1uF 0.01uF 0.01uF 1uF
AGND AGND AGND AGND AGND AGND
R111 1.50k
C142 1500pF
AVDD
2 U19
3
Vocm1 R113
THS4561IDGKR
R112 1.50k 49.9 M0:Install pull-up resistor
1 4
AGND to IOVDD for Asynchronous
V+
Interrupt Mode Uninstall
C143 8 V- 5 pull-up resistor to leave M0
R114 1.50k 3900pF R115 floating for Synchronous
IBAT
7 49.9 AVDD DVDD_3.3V Slave Mode
6
R116 100k
AGND
U21
AVDD DVDD_3.3V
AGND 9 13 R120
AVDD VREFN
C144 1500pF 499
R118 DVDD_3.3V C145 C146
100 C147 15 12 1uF 0.1uF R121 R122 R123
IOVDD VREFP 100k 100k 100k
R117 1.50k 29 IOVDD
DVDD_3.3V
2700pF RESV 16
R119
100 1
AIN1N M0
30 AGND
31
M1
2 32
AIN1P M2
RESET 17
1
R124 1.50k R125 3 23 ADC_SPI_CS
AIN2N CS
100 C148 22 ADC_SPI_SCLK S1
SCLK
4 20 ADC_SPI_MOSI C149
AIN2P DIN
C150 1500pF 2700pF 21 ADC_SPI_MISO 10pF
R127 DOUT
2
DRDY 19 ADC_SPI_DRDY
100 5 AIN3N DONE 18 ADC_SPI_DONE
AVDD
6
AIN3P NC
24 AGND
2 U20 R135 0 Y1
3
Vocm2 R128
THS4561IDGKR CLKIN/XTAL1 25 1 2
49.9 G
R126 3.30k 1 4 7 AIN4N XTAL2 26 3 4
AGND G
V+
C151 8 V- 5 8 R137 1.00M R136 0
AIN4P
R129 3.30k 3900pF R130 VNCP
11
VBAT
7 49.9
6
R131 100k AGND 14 C152 C153

REFEXT
AGND
AVDD 10 20pF 20pF J19
AVSS
AGND 28
CAP GND
27 ADC_SPI_MISO 1 2
SPI_MISO
C154 1500pF ADC_SPI_MOSI 3 4
SPI_MOSI
AGND AGND ADC_SPI_CS 5 6
SPI_CS
ADS131A04IPBSR ADC_SPI_SCLK 7 8
C155 SPI_SCLK
R132 1.50k ADC_SPI_DRDY 9 10
1uF SPI_DRDY
ADC_SPI_DONE 11 12
C156 SPI_DONE
13 14
1uF AGND 15 16
U22A VREF_ADC
PRPC008DAAN-RC
2 6 R133
V5.0_DAQ VIN VOUT
TRIM/NR 5 0
AGND AGND
3 4 C157 R134 C158 C159 AGND
TEMP GND
C160 1000pF 1.00 100uF 100uF R138
1uF TI-REF5025DGK8 1.00k
C161 AGND AGND

AGND 1uF
AGND
Figure 23. DAQ Subsystem
Figure 24 shows how the full driver-ADC subsystem stability simulations are performed.
R6 1.5k
Vcc
+
VS2 5 C4 1.5n
C12 1T
Vin+
R1 10MEG
Vin+
R9 1.5k L6 1T
Vcc R2 49.9 R4 100
VCVS1 1
-
R8 130k
+
+ + +
C6 4n
+ +
C1 2.7n
Vocm
U1 THS4561 Aol
V
LoopGain
VG1 - -
- - R7 10MEG + PD R3 49.9 -
R10 1.5k
L1 1T Vcc R14 100

Vin-
Vin-
C13 1T
C5 1.5n
R11 1.5k
Figure 24. THS4561 Stability Simulation Schematic
Figure 25 shows the simulation results of the THS4561 stability. It shows that the crossover frequency is
about 9.58 MHz, and the phase margin is about 42.46°. These are indications of a stable circuit. To learn
more about amplifier stability, see TI's Precision Labs - Op Amps.
Figure 25. THS4561 Stability Simulation Results
Transient response simulations are also completed for the THS4561 and INA188 stage to further ensure
the proper functionality of this stage. Figure 26 shows the output of a 50-mV peak-to-peak, 1-kHz square
wave that is put into the circuit. Figure 27 displays the results of the transient response of this analog front
end stage. As seen, the output is a 2.2-V square wave, which corresponds to the expected gain of 44.48.
There is no oscillation present on the output so this stage is considered stable.
Figure 26. TIDA-01040 AFE Transient Schematic
Figure 27. TIDA-01040 AFE Transient Results
3.2 Software Design
3.2.1 DAC
This reference design uses the USB2ANY interface adapter to communicate with the DAC80004 device to
generate a reference signal for current and voltage control. First, open the USB2ANY Explorer, click
Select Interface to choose the SPI, then click the 3.3V ON button. Click the SPI tab above the Activity
Logging section. If the SPI tab does not appear, click around the words "Activity Logging" as sometimes
the tabs are hidden. Configure the GUI parameters as shown in Figure 28.
Figure 28. USB2ANY Configuration
The DAC80004 commands are found in the DACx0004, Quad 16-,14-,12-Bit, 1 LSB INL, Buffered,
Voltage-Output Digital-to-Analog Converters Data Sheet.
3.2.2 ADC
In this reference design, the Delta-Sigma ADC Evaluation Software is used to communicate with the
ADS131A04 device. See the Delta-Sigma ADC EvaluaTIon Software User's Manual and ADS131A04
Evaluation Module User's Guide for detailed information.
After launching this software, click the Scripts menu, then click Predefined and choose Basic startup with
Datarate @ 8kSPS as Figure 29 shows. Finally, click the Run button at the right side of the window.
Figure 29. ADC GUI Setting
The second step is to set the register of the ADC. Figure 30 shows the setting with an external reference
voltage. It also can modify clock settings and OSR settings.
Figure 30. ADC Register Setting
After setting the GUI and registers, the software can now capture the data: click the Data Analysis menu,
choose "ADC0" and "ADC1", change the Clock and VRef (V), then click the Collect Data button as
Figure 31 shows.
Figure 31. ADC GUI Collect Data
The raw data is shown on the GUI, but the mean value of current and voltage is needed.
Figure 32 illustrates the GUI when the Histogram menu at the left corner is clicked.
Figure 32. ADC GUI Data Analysis
Figure 32 shows the mean value on the bottom after analysis, but this is the full scale format. Divide by
8388607 (DEC of 0X7FFFFF), and multiply by "VRef", then the real current and voltage signal is obtained
as Equation 1 and Equation 2 show. This example was tested under CC control: the control current is 5 A,
the battery voltage is 3.1 V.
(1)
(2)
The expected value of channel 0 should be (Iset × Rcs × Gain_INA188 × Gain_ADC0) = 5 A × 1 mΩ ×
44.48 × 1 = 222.4 mV, and the expected value of channel 1 should be (Vset × Gain_ADC1) = 3.1 V × (1.5
k/3.30 k) = 1.4091 V. Those values are close to the mean value from the histograms. Due to the offset
and noise of the components, refer to Section 3.3.3.4 to calibrate the ADC. The result is a more accurate
value.
3.3 Testing and Results
3.3.1 Getting Started Hardware

This section gives brief information to set up and run the board. Figure 33 shows the sections of the
board.
CV DAC
Control
ADC
CC
Power
Control
Bias
Power
Stage
Figure 33. TIDA-01040 Hardware
This system has some configuration options. Table 2 highlights the purpose of each jumper as well as the
default configurations.
Table 2. Jumper Configuration

HEADER SIGNAL PINS FUNCTION DESCRIPTION DEFAULT
J1 UVLO (1,2) Enable from V_HV Y
(2,3) Enable from V_LV
J3 SYNCOUT (1,2) Clock output for multiphase configuration Y
J4 V10-Aux (1,2) Auxiliay power Y
J5 OPT (1,2) Multiphase configuration
(2,3) No Multiphase configuration Y
J6 DIR (1,2) BUCK mode Y
(2,3) BOOST mode
J7 EN1 (1,2) Onboard CH-1 enable
(2,3) Onboard CH-1 disable Y
J8 EN2 (1,2) Onboard CH-2 enable
(2,3) Onboard CH-2 disable Y
J14 V5 (1,2) Enable power supply for CC control Y
J18 IREF/VREF (1,2),(7,8) Enable DAC output signal for CC/CV control loop Y
J34 V_HV (1,2) Enable CV control for bus voltage(V_HV) N
J35 V_LV (1,2) Enable CV control for battery voltage(V_LV) Y
Table 2. Jumper Configuration (continued)

HEADER SIGNAL PINS FUNCTION DESCRIPTION DEFAULT
J37 V5A (1,2) Enable power supply for CV control Y
3.3.2 Test Setup

The test setup for a bidirectional charge and discharge converter requires a different setup for current and
voltage control loop tests. Figure 34 shows a block diagram of the hardware setup for the TIDA-01040
current control loop test.
Figure 34. Current Control Test Block Diagram
The power supply must be able to provide enough power in both charge and discharge mode. Configure
the TIDA-01040 board to BUCK or BOOST mode through the "DIR" header (J6). Then set current and
voltage control signals to control loop. Configure the electronic load to operate in CV mode whose value
should be smaller than the voltage set by the DAC. The CV control loop will give enough forward voltage
for D3, and the system can work in CC mode. The super capacitor is required to clamp the output voltage
and simulate the battery performance.
The reason for connecting a shunt resistor in BOOST mode is for monitoring the current flow out from the
battery (discharging current). In BUCK mode, it is easy to read the current flow into battery (charging
current) on the electronic load.
Figure 35 shows the block diagram of the hardware setup for the TIDA-01040 voltage control loop test.
Figure 35. Voltage Control Test Block Diagram
When testing the CV control performance, configure the system to work in CV mode. Configure the
electronic load to operate in CC mode with a value smaller than the current value set by DAC.
3.3.3 Test Results
3.3.3.1 Current Control Accuracy

The current accuracy depends on the current sensing resistor, the gain, offset, and drift of the current
amplifier, INA188, and TLV07 devices. These parameters vary from device to device. To achieve good
current control accuracy, the total gain and the offset of the designed circuit must be calibrated. Because
high temperature effects the drift of some device in the system, the relationship between the current
control signal and the real output current is not linear. Three point data is used to calibrate the CC control
considering the drift in a high current situation. In buck mode, the battery current is 5.479 A if the DAC
current reference signal code is 3229(DEC). The battery current is 34.932 A if the DAC current reference
signal code is 20522(DEC), and the battery current is 49.942 A if the DAC current reference signal code is
29360(DEC). From these three test results, the real gain and offset can be calculated as follows:
(3)
(4)
(5)
(6)
The current accuracy in boost mode can be calibrated with the same method. Using the gain and offset,
the output current value can be determined and compared to the actual test output current.
Figure 36 shows the full scale (FS) CC control accuracy of this reference design at buck (high side is 12
V, low side is 1 V) and boost (low side is 2 V, high side is 10 V) mode conditions. The output is controlled
within 0.01% in the whole range.
0.05
BUCK
0.04 BOOST
0.03
0.02
Accuracy (%, FS)
0.01
-0.01
-0.02
-0.03
-0.04
-0.05
0 5 10 15 20 25 30 35 40 45 50
Battery Voltage (mV) D001
Figure 36. CC Control Accuracy
To know the whether a change in voltage has any effect on the CC control accuracy, Table 3 shows test
current under different battery voltage and different current settings. The tested data shows that the
voltage setting has very little effect on the current control.
Table 3. CC Control with Different Battery Voltage

ISET
VBattery (V) 10 A 20 A 30 A 40 A 50 A
0.5 9.976 19.966 29.96 39.958 49.968
1 9.976 19.966 29.96 39.958 49.968
1.5 9.976 19.966 29.96 39.958 49.968
2 9.976 19.966 29.96 39.958 49.97
2.5 9.976 19.966 29.96 39.958 49.97
Table 3. CC Control with Different Battery Voltage (continued)

ISET
VBattery (V) 10 A 20 A 30 A 40 A 50 A
3 9.976 19.966 29.96 39.958 49.97
3.5 9.976 19.966 29.96 39.958 49.972
4 9.976 19.966 29.96 39.958 49.972
4.5 9.976 19.966 29.96 39.958 49.972
5 9.976 19.966 29.96 39.958 49.973
3.3.3.2 Voltage Control Accuracy

The voltage control accuracy of this system depends on the gain offset, offset of the resistor division, and
the LM6142 device. This also requires calibration to achieve good voltage control accuracy. Because the
voltage control subsystem is far away from the main power stage, use a simplified two points calibration
method to calibrate the gain as Equation 7 and Equation 8:
(7)
(8)
After calibration, the calculated output voltage can be compared with the actual test output voltage.
Figure 37 shows the accuracy of CV control at buck mode (high side 12 V, output current 10 A).
0.015
Buck
0.01
0.005
Accuracy (%)
-0.005
-0.01
-0.015
-0.02
1000 1500 2000 2500 3000 3500 4000 4500 5000
Figure 37. CV Control Accuracy
To determine whether the CV control accuracy will change with different current conditions, these
conditions must be tested. Table 4 shows the different calibrated gain and offset values at different
currents.
Table 4. CV Control Calibration Under Different Current

CURRENT (A) GAIN OFFSET
10 0.089015028 –0.073989981
20 0.089012064 –1.840658624
30 0.089006136 –3.57399591
40 0.089001921 –5.484399232
50 0.088994807 –7.164402077
Figure 38 and Figure 39 show the linear relationship between gain and offset with current.
0.08902
Gain
Linear (Gain)
0.089015
y = –0.0000005059x + 0.0890211667
0.08901
2
R = 0.9833534969
Gain
0.089005
0.089
0.088995
0.08899
10 15 20 25 30 35 40 45 50
Battery Current (A) D003
Figure 38. CV Calibration Gain vs Current
0.0000000
Offset
-1.0000000 Linear (Offset)
-2.0000000
y = 0.1782300000x + 1.7195000000
-3.0000000 2
R = 0.9997073727
Offset (mV)
-4.0000000
-5.0000000
-6.0000000
-7.0000000
-8.0000000
10 15 20 25 30 35 40 45 50
Figure 39. CV Calibration Offset vs Current
Use the equations in Figure 38 and Figure 39 to get the new gain and offset values under different
currents. Table 5 shows some sample values.
Table 5. CV Control Updated Calibration Under

Different Current
CURRENT (A) GAIN OFFSET
10 0.089016108 –0.0628
20 0.089011049 –1.8451
30 0.08900599 –3.6274
40 0.089000931 –5.4097
50 0.088995872 –7.192
Using the updated gain and offset, obtain the updated CV control accuracy with different current as
Figure 40 shows. The results show the CV control can almost maintain 0.01% accuracy within the whole
battery voltage range (1.0 V–4.5 V).
0.05
Buck, CC = 10 A
0.04 Buck, CC = 20 A
Buck, CC = 30 A
Buck, CC = 40 A
0.03 Buck, CC = 50 A
0.02
0.01
Accuracy (%)
-0.01
-0.02
-0.03
-0.04
-0.05
1000 1500 2000 2500 3000 3500 4000 4500 5000
Figure 40. CV Control Accuracy With Different Current
3.3.3.3 CC, CV Transformation

The complete battery formation profile should include both the CC control and the CV control. It is critical
to understand the performance of the system when transforming from CC mode to CV mode. Figure 41
and Figure 42 show the transformation under different current and different voltage settings.
60
CV = 4 V, CC = 10 A
CV = 4 V, CC = 20 A
CV = 4 V, CC = 30 A
50 CV = 4 V, CC = 40 A
CV = 4 V, CC = 50 A
40
Battery Current (A)
30
20
10
0
2000 2500 3000 3500 4000 4500
Figure 41. CC, CV Transformation Under Different Current Setting
60
50
40
Battery Current (A)
30
20
10
CV = 4 V, CC = 50 A
CV = 3.5 V, CC = 50 A
CV = 3 V, CC = 50 A
0
2000 2500 3000 3500 4000
Exce
Figure 42. CC, CV Transformation Under Different Voltage Setting
In Figure 41, with the increase in current setting, the CC control will start transforming to CV control at
lower voltage. Figure 42 shows that voltage setting has less effect on the switch from CC control to CV
control.
3.3.3.4 ADC Calibration

Two channels are used to monitor the battery current and voltage. The accuracy of this data acquisition
depends on the gain and offset of the THS4561 device and other components, so the output of the ADC
should be calibrated. Use a similar method to calibrate those two channels as the previous current and
voltage control loop:
ADC channel 1 calibration:
(9)
(10)
(11)
(12)
ADC channel 2 calibration:
(13)
(14)
Figure 43 and Figure 44 show the accuracy of this data acquisition after calibration.
0.05
0.04
0.03
0.02
Accuracy (%, FS)
0.01
-0.01
-0.02
-0.03
-0.04
-0.05
0 5 10 15 20 25 30 35 40 45 50
Figure 43. ADC Current Acquisition Accuracy
0.05
0.04
0.03
0.02
0.01
Accuracy (%)
-0.01
-0.02
-0.03
-0.04
-0.05
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Figure 44. ADC Voltage Acquisition Accuracy
The results show the ADC current acquisition accuracy is excellent. Although the ADC voltage acquisition
accuracy is not good in the low voltage range, battery tester applications usually are more concerned with
the accuracy in the high-voltage range. In battery tester applications, engineers can refer to
Section 3.3.3.1 and Section 3.3.3.2 to set the DAC to control the current and voltage after calibration.
Then engineers can refer to Section 3.3.3.4 to get the real output current and voltage after calibration and
adjust the DAC value to get the better performance.
Design Files www.ti.com
4 Design Files
4.1 Schematics
To download the schematics, see the design files at TIDA-01040.
4.2 Bill of Materials

To download the bill of materials (BOM), see the design files at TIDA-01040.
4.3 PCB Layout Recommendations
4.3.1 Layout Prints

To download the layer plots, see the design files at TIDA-01040.
4.4 Altium Project

To download the Altium Designer® project files, see the design files at TIDA-01040.
4.5 Gerber Files

To download the Gerber files, see the design files at TIDA-01040.
4.6 Assembly Drawings

To download the assembly drawings, see the design files at TIDA-01040.
4.7 Simulation Results

To download the simulation results, see the design files at TIDA-01040.
5 Software Files
To download the software files, see the design files at TIDA-01040.
6 Related Documentation
1. Texas Instruments, LM5170-Q1 Multiphase Bidirectional Current Controller Data Sheet
2. Texas Instruments, LM2664 Switched Capacitor Voltage Converter Data Sheet
3. Texas Instruments, TPS709 150-mA, 30-V, 1-μA IQ Voltage Regulators with Enable Data Sheet
4. Texas Instruments, LM5118 Wide Voltage Range Buck-Boost Controller Data Sheet
5. Texas Instruments, INA188 Precision, Zero-Drift, Rail-to-Rail Out, High-Voltage Instrumentation
Amplifier Data Sheet
6. Texas Instruments, DACx0004, Quad 16-,14-,12-Bit, 1 LSB INL, Buffered, Voltage-Output Digital-to-
Analog Converters Data Sheet
7. Texas Instruments, ADS131A0x 2- or 4-Chan, 24-Bit, 128-kSPS, Simultaneous-Sampling, Delta-Sigma
ADC Data Sheet
8. Texas Instruments, TLV07 36-V Precision, Rail-to-Rail Output Operational Amplifier Data Sheet
9. Texas Instruments, OPAx22x High Precision, Low Noise Operational Amplifiers Data Sheet
10. Texas Instruments, OPA827 Low-Noise, High-Precision, JFET-Input Operational Amplifier Data Sheet
11. Texas Instruments, THS4561 Low-Power, High Supply Range, 70-MHz, Fully Differential Amplifier
Data Sheet
12. Texas Instruments, LM6142/LM6144 17 MHz Rail-to-Rail Input-Output Operational Amplifiers
13. Texas Instruments, PMP15038 Test Results Technical Reference
www.ti.com About the Author
6.1 Trademarks
E2E is a trademark of Texas Instruments.
Altium Designer is a registered trademark of Altium LLC or its affiliated companies.
SPI, QSPI are trademarks of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
SIMetrix, SIMPLIS are registered trademarks of SIMetrix Technologies Ltd.
All other trademarks are the property of their respective owners.
7 About the Author

Sean Zhou is an application engineer at Texas Instruments, where he is responsible for developing
reference design solutions for the test and measurement industry. Sean has earned his master of science
in electrical engineering (MSEE) degree from the Soochow University in Suzhou, China.
Taras Dudar is a systems design engineer and architect at Texas Instruments, where he is responsible
for developing reference design solutions for the test and measurement industry. Previously, Taras
designed high-speed analog SOC integrated circuits for Gbps data communications. Taras has earned his
master of science in electrical engineering (MSEE) degree from the Oregon State University in Corvallis,
OR.
8 Acknowledgement
A special thank you goes out to Youhao Xi, Ryan Andrews, Uttama Kumar Sahu, Jasper Li and Bryan
Bloodworth for their support during the development of the TIDA-01040 reference design.
Revision History www.ti.com
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2018) to A Revision ......................................................................................................... Page
• Changed 'CC, CV' to 'constant current (CC) and constant voltage (CV)' .......................................................... 2
• Changed wording in Section 1.1 ........................................................................................................ 2
• Changed '0.5 C' to '0.5 A' ................................................................................................................ 3
• Changed wording throughout Section 2 ................................................................................................ 4
• Changed wording throughout Section 3 .............................................................................................. 18
• Changed information in Table 2 ....................................................................................................... 32
• Added Section 8 ......................................................................................................................... 43
44 Revision History TIDUE89A – June 2018 – Revised September 2018

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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TI Designs: TIDA-01040

Battery Tester Reference Design for High Current

TIDA-01040 Design Folder

ASK Our E2E™ Experts

VIN HO1 LO1 LM5170 CSA1 CSB1

1.1 Li-Ion Formation

Electrode Coating Cell Assembly Formation

Figure 1. Simplified Li-Ion Battery Manufacturing Process

1.2 Li-Ion Battery Formation Profile

Figure 2. Regular Li-Ion Battery Formation Profile

1.3 Key System Specifications

Table 1. Key System Specifications

2.1 Block Diagram

VIN HO1 LO1 LM5170 CSA1 CSB1

Figure 3. TIDA-01040 Block Diagram

2.2 Highlighted Products

• Multiple SPI data modes:

2.3 System Design Theory

2.3.1 Constant Current Control Design

Figure 4. Vcm vs Vout Calculator for INA188

Figure 5. TLV07 TINA-TI Stability Schematic

Figure 6. TLV07 TINA-TI Stability Simulation Results

Figure 7. Constant Current Control Simulation Schematic

Figure 8. Constant Current Control Transient Simulation Results

Figure 9. CC Small Signal Simulation Results

2.3.2 Constant Voltage Control Design

Figure 10. Constant Voltage Control Simulation Schematic

Figure 11. Constant Voltage Control Transient Simulation Results

Figure 12. CV Steady State Simulation Results

Figure 13. CV Small Signal Simulation Results

2.3.3 System Simulation

RSS2 ESR3 HO1 RSS 44.48 X6

CSA2 CSA2 CSA1 CSA1 10p VN5

CSB2 CSB2 CSB1 CSB1

47n IC=0 220n IC=0 47n IC=0

Figure 14. TIDA01040 System Simulation Schematic

Figure 15. TIDA01040 System Transient Simulation Results

3 Hardware, Software, Testing Requirements, and Test Results

3.1 Hardware Design

3.1.1 Power Bias

HTSW-103-07-G-S 8 D7 PGND PGND

AGND 7.32k 52.3k 10.0

Figure 16. Power Bias Subsystem

3.1.2 Main Power Convert Stage

C56 C57 C58 C50 C51 C18 49.9k

CXS70-14-C 0.001 CXS70-14-C

C54 C55 C20 C21

C68 C69 C70 C71

Figure 17. Main Power Convert Stage Subsystem

3.1.3 LM5170 Subsystem

Figure 18. LM5170 Subsystem

3.1.4 CC Calibration Subsystem

C119 C120 AGND AGND

Figure 19. CC Calibration Subsystem

3.1.5 CV Calibration Subsystem

LM6142AIM/NOPB AGND AGND

BOOST MODE D11

Figure 20. CV Calibration Subsystem

Figure 21. Soft Start Waveform

3.1.6 DAC Subsystem

DVDD_3.3V AGND AGND

TI-REF5050D8 10k 10k 10k

Figure 22. DAC Subsystem