Documente Academic
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83130 55025
48 SB antennas
DVOR 432
Doppler
Technical Manual
Part 1
Equipment Description
DVOR 432
Ed. 07.04 48 SB
DVOR 432
Equipment Description Preliminary Remarks
PRELIMINARY REMARKS
The equipment manuals for DVOR 432 (50 W and 100 W, single or dual) comprise:
This Technical Manual Part 1 includes the Equipment Description with the chapters below:
1 General Information
2 Technical Description Transmitter and Antenna Switching Unit
3 Technical Description Antenna System
4 Emergency Power Supply
5 Remote Maintenance and Monitoring Configuration (RMMC)
Annex DVOR Nextfield (optional)
Chapter 1 contains general system descriptions. The equipment−specific descriptions are contained
in Chapter 2, and the antenna−specific descriptions in Chapter 3. There are only slight differences
between the 50 W and 100 W versions (single or dual) as far as components and functions are con-
cerned. These versions are not therefore described separately; instead the relevant special feature
are made clear by means of notes. The nextfield monitoring option is described in the Annex to this
manual.
Since it is not possible to include modifications, such as those which may be made to circuitry details
or dimensioning in the interests of technical progress, in the Technical Manual, we should point out
that questions of detail should always be answered using the technical documentation supplied with
the system. It is possible that reference numbers of drawings or subassemblies used in this descrip-
tion are no longer contained in the set of drawings supplied (Volume A to C), but rather than (to con-
form with the system) they have been replaced by new drawings with another number. Please carry
out a once−only check on the basis of delivery list supplied and exchange where appropriate.
Description and use of the PC User Program will be found in the Technical Manual ADRACS, Code
No. 83140 55324.
MARK SYMBOLS
To get the best out of the navigation systems Navaids 400 you should study the contents of this manu-
al carefully. In particular you should familiarize yourself with the marks given in this manual which are
highlighted for easy recognition:
CAUTION WARNING
Ed. 07.04 48 SB A
DVOR 432
Preliminary Remarks Equipment Description
Title 07.04
A 07.04
B 09.05
I to X 07.04
AV−1 to 16 07.04
1−1 to 60 07.04
2−1 to 4 07.04
2−5 to 6 09.05
2−7 to 9 07.04
2−10 09.05
2−11 to 72 07.04
3−1 to 10 07.04
4−1 to 2 09.05
5−1 to 6 07.04
Trademarks: Microsoft and MS−DOS are registered trademarks, WINDOWS is a trademark of the Microsoft Corporation. IBM is a registered trademark of the International
Business Machines Corporation. Pentium is a registered trademark of the Intel Corporation. All other mentioned product names may be trademarks of the
respective manufacturers and must be observed.
Note Despite of careful editing work technical inaccuracies and printing faults cannot be excluded in this publication. Change of text remains reserved without notification.
B 48 SB Ed. 09.05
DVOR 432
Equipment Description Table of Contents
TABLE OF CONTENTS
Section Title Page
Ed. 07.04 48 SB I
DVOR 432
Table of Contents Equipment Description
Section Title Page
II 48 SB Ed. 07.04
DVOR 432
Equipment Description Table of Contents
Section Title Page
IV 48 SB Ed. 07.04
DVOR 432
Equipment Description Table of Contents
Section Title Page
Ed. 07.04 48 SB V
DVOR 432
Table of Contents Equipment Description
VI 48 SB Ed. 07.04
DVOR 432
Equipment Description Table of Contents
LIST OF FIGURES
Fig.−No. Title Page
Fig. 1−1 Enroute navigation with DVOR, principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
Fig. 1−2 Diagrammatic view of a DVOR installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3
Fig. 1−3 Azimuth as a function of the phase angle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−4
Fig. 1−4 Generation of the direction−dependent FM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−5
Fig. 1−5 Frequency spectrum of the DVOR (VOR) omnidirectional radio beacon . . . . 1−6
Fig. 1−6 (D)VOR signal amplitude modulated with 30 Hz and 9960 Hz . . . . . . . . . . . . 1−6
Fig. 1−7 Switching of the sideband antennas in the DVOR . . . . . . . . . . . . . . . . . . . . . . . 1−7
Fig. 1−8 Components with beryllium oxide ceramic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−16
Fig. 1−9 Basic structure of a DVOR system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−21
Fig. 1−10 Azimuth angle between aircraft and ground station . . . . . . . . . . . . . . . . . . . . . 1−23
Fig. 1−11 Arrangement of the electronically rotated DVOR antenna . . . . . . . . . . . . . . . . 1−24
Fig. 1−12 Generation of the modulated RF CSB, unmodulated USB (SB1) and . . . . . . 1−25
LSB (SB2) signals; feeding of the antenna via PDSU
Fig. 1−13 Concept of sideband signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−25
Fig. 1−14 Antenna Switching Unit subassemblies (ASU), block diagram . . . . . . . . . . . . 1−26
Fig. 1−15 Generation of sideband signals (example USB) . . . . . . . . . . . . . . . . . . . . . . . . 1−27
Fig. 1−16 Generation of the DVOR carrier signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−29
Fig. 1−17 Address Counter and RAM data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−30
Fig. 1−18 DVOR transmitter modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−31
Fig. 1−19 Concept of the DVOR VHF Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−32
Fig. 1−20 Concept of the Modulator 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−32
Fig. 1−21 Concept of Control Coupler CCP−D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−33
Fig. 1−22 Monitoring Concept, general view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−34
Fig. 1−23 Position of the monitor dipole in the radiated field . . . . . . . . . . . . . . . . . . . . . . 1−35
Fig. 1−24 Concept of Monitor Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−36
Fig. 1−25 Spectrum of the VOR multiplex signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−36
Fig. 1−26 Discrete Fourier Transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−37
Fig. 1−27 DVOR antenna monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−41
Fig. 1−28 Dual AN 400 Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−42
Fig. 1−29 Power supply, block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−46
Fig. 1−30 DVOR 432, 50/100 W, dual version; simplified block diagram . . . . . . . . . . . . . 1−47
Fig. 1−31 System software, overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−49
Fig. 1−32 Transmitter SW flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−50
Ed. 07.04 48 SB IX
DVOR 432
Table of Contents Equipment Description
Fig.−No. Title Page
Fig. 3−9 Setting trimming capacitor C5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
Fig. 3−10 Single radiator on sideband antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
Fig. 3−11 Single antenna, cover removed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
Fig. 3−12 Supports and framework, example installation . . . . . . . . . . . . . . . . . . . . . . . . . 3−9
Fig. 3−13 Framework decking and antenna circle with carrier antenna and . . . . . . . . . 3−10
sideband antennas
Fig. 3−14 Mast with monitor dipole (example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−10
Fig. 4−1 Discharge times (guiding values) by use of the VARTA battery set . . . . . . . . 4−3
Fig. 5−1 RMMC, overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−1
Fig. 5−2 Hierarchy of the RMMC system components . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−2
Fig. 5−3 Example Configuration: RCMS 443 for two ILS and VOR/DME/TACAN . . . . 5−5
X 48 SB Ed. 07.04
NAVAIDS 400
Conventional Navaids List of Abbreviations
ABKÜRZUNGSVERZEICHNIS
LIST OF ABBREVIATIONS
LISTE D’ABRÉVIATIONS
LISTA DE ABREVIATURAS
A Antenne
Antenna
Antena
AC Alternating Current
Courant alternatif
Corriente alterna
ACA Analogical Carrier Amplifier (BITE signal)
Amplificateur pour porteurs analogiques (signal BITE)
Amplificdor portador analogico (señal BITE)
ACC Alternating Current Converter
ADC Analog−Digital Converter
Convertisseur analogique/numérique
Convertidor analógico/digital
ADCS Analog−to−digital Converter Subsystem
Sous−système convertisseur analogique/numérique
Subsistema convertidor analógico/digital
ADR Analog Display Routine
Routine affichage analogique
Rutina de indicator analógico
ADRACS Automatic Data Recording And Control System
ADSB Alternating Double Sideband
Bande latérale double alternante
Banda lateral doble alternante
ADU Antenna Distribution Unit
Antennen−Verteileinheit
Ensemble de distribution d’antenne
Unidad de distribución de antena
AF Audio Frequency
Basse fréquence
Audiofrequencia
AFC Automatic Frequency Control
Commande automatique par fréquence
Control automático de frecuencia
AGC Automatic Gain Control
Commande automatique de gain
Control automático de ganancia
AM Amplitude Modulation
Modulation d’amplitude
Modulación de amplitud
CHAPTER 1
GENERAL INFORMATION
1.1 INTRODUCTION
The VOR (Very high frequency Omnidirectional Radio range) is a radio navigation aid recommended
by the ICAO and introduced internationally for short and medium range aircraft guidance. It can be
remote controlled and remote monitored.
The DVOR radio navigation equipment is a further development of the conventional VOR. Through
its utilisation of the Doppler effect and a wide−based antenna system it is able to produce a consider-
ably more precise azimuth signal. DVOR radio navigation installations are used mainly where the geo-
graphical conditions are difficult.
The principle on which the (D)VOR operates is based on the measurement of the phase angle of two
30 Hz signals radiated by the station. One signal (reference signal) is radiated with the same phase
in all directions. For the second 30 Hz signal (variable signal), the phase relationship relative to the
first signal changes as a function of the azimuth. The electric phase angle measured in the airborne
receiver corresponds to the azimuth angle.
Using the VOR receiver installed in his aircraft the pilot is able to obtain the following information from
a DVOR or VOR radio navigation installation:
1. The azimuth indication of the aircraft’s position relative to the ground beacon, i.e. the angle be-
tween magnetic North and the direction ground beacon to aircraft.
2. The bearing which indicates whether the aircraft is flying to the left or right of the preselected course
(position line) or whether it is exactly on it.
3. The "from/to" indication which shows whether the aircraft is flying toward the (D)VOR beacon or
away from it.
The aircraft position is marked by the intersection of two position lines, which can be obtained by
switching the VOR airborne receiver consecutively to the frequencies of two CVOR or DVOR beacons
(C=Conventional, D=Doppler). To evaluate the indications only a map is required, and the knowl-
edge of the CVOR or DVOR positions and a CVOR/DVOR frequency chart. In addition, a VOR beacon
can be approached on a homing flight using the CDI instrument (Course Deviation Indicator) or with
help of an automatic flight management system.
ÂÂÂÂ
ÂÂÂÂ ÂÂÂÂÂ
2
DVOR B
ÂÂÂÂÂ DVOR c
ÂÂÂÂÂ
ÂÂÂÂÂ
DVOR A
The DVOR system can be combined with a DME (Distance Measuring Equipment) to form a DVOR/
DME station. Then an aircraft can determine its position by referring to the location of a single DVOR/
DME station.
The DVOR equipment can be supplied already installed in a 10 ft container shelter. The DVOR−anten-
na system is mounted on a counterpoise optionally available in different heights as made necessary
depending on local conditions.
THALES ATM
Counterpoise
DVOR 432
Fig. 1−2 Diagrammatic view of a DVOR installation
1.2.2 Navigation Signal Parameters
As the basis for the explanation of the DVOR method, first the principle of the VOR method is de-
scribed.
1.2.2.1 VOR Method
The RF signal radiated by a VOR is modulated by two 30 Hz sinewaves. Both 30 Hz signals have a
certain phase relationship, which is dependent on the direction from which the signal is received. The
phase relationship is identical to the geographical angle between North and the direction of the air-
craft relative to the ground beacon (azimuth). One of the two 30 Hz modulations is irrespective of the
azimuth (reference signal), whilst the phase relationship of the second 30 Hz modulation to the refer-
ence signal varies with the azimuth (variable signal). The reference signal and the variable signal are
modulated in different ways.
The direction−independent (reference) signal frequency modulates a subcarrier of f0 ±9960 Hz with
a frequency shift of ±480 Hz. The subcarrier is then radiated as amplitude modulation of the carrier
f0 with 30 % modulation depth by a horizontally polarised antenna with omni−directional characteris-
tics. In addition, the carrier f0 is modulated with an identity code (1020 Hz) as well as with voice
(300...3000 Hz).
The direction−dependent (variable) signal is radiated by 2 crossed dipoles. The crossed dipoles re-
ceive sideband signals from the two sideband transmitters with a 90° phase difference in the enve-
lope. The carrier of the sideband signals is suppressed. This results in a signal−in−space with a "fig-
ure−eight pattern" rotating 30 times per second.
Since the carrier f0 is radiated by an antenna with omnidirectional characteristics, the superposition
of the carrier and the 30 Hz sidebands in the field − if the phase is correctly set − produces a pure
amplitude modulation, with the phase of the resulting 30 Hz signal being dependent on the azimuth,
related to the 30 Hz reference signal.
270° 90°
DVOR
t t
180°
f+p D fn
l0
If antenna A begins its orbit at point 1 and continues via 2 and 3 to 4, the frequencies received by the
two observers B1 and B2 will change as a function of time. If a reference signal with the same frequen-
cy is transmitted at the same time by an omnidirectional, central antenna M, the phase angle between
the reference signal (of antenna M) and the changing frequency (of antenna A) will be in proportion
to the azimuth (observer’s position), i.e. the phase relationship of signal M and A with respect to one
another is a function of the azimuth. The reference point is magnetic north (point 1), where both sig-
nals are in−phase.
1
Movement of radiator A
on a circular path A 1 2 3 4 1
f
t
B1
B1
2
M 4 f
t
B2
D
3 Reference Signal
t
It can be seen from the frequency spectrum (Fig. 1−5) that the azimuth−dependent frequency modu-
lation of the DVOR is located on the subcarrier f1= 9960 Hz. The two sidebands (f0+f1) and (f0 − f1)
are generated separately in the DVOR transmitter for this purpose, and radiated via "rotating" outer
antennas. The powers and phase relationships of the sidebands with respect to the carrier are set
such that when added in the farfield an amplitude−modulated composite signal re−emerges.
The depth of modulation of the individual frequencies can be adjusted within certain limits.The values
which apply for the normal cases are:
− 30 Hz navigation signal 30 %
− 9960 Hz auxiliary carrier 30 %
− Voice 30 %
− Identity code 10 %
Reference Signal
(VOR: Variable signal)
(VOR: Reference signal) Carrier (VOR: Reference signal)
Variable signal Variable signal
30 Hz FM 30 Hz FM
ËËËËËË ËËËËËËË
Deviation ±480 Hz Deviation ±480 Hz
ËËËËËË ËËËËËËË
Voice, Identity −30 Hz AM +30 Hz AM Voice, Identity
f0 − 9960 Hz
ËËËËËË f0
ËËËËËËË f0 + 9960 Hz
Subcarrier Subcarrier
Lower sideband Upper sideband
Fig. 1−5 Frequency spectrum of the DVOR (VOR) omnidirectional radio beacon
Composite RF signal
The subcarrier frequency deviation of ±480 Hz and the carrier frequency range of 108...118 MHz are
the same as with the conventional VOR. Taking a mean carrier frequency of 113 MHz (= 2.65 m) the
equation below reveals that the orbit must have a diameter of 13.5 m:
Df l
D+ ,
p fn
If the double sideband method is used (f0+f1 and f0−f1), the two sidebands whose focal points of
radiation are orbiting in the same direction are transmitted by antennas opposite one another on the
orbital path. To achieve this effect the antenna switching unit activates sideband antenna 1 with the
upper sideband (f0+9960 Hz) and sideband antenna 25 with the lower sideband (f0−9960 Hz) simul-
taneously (Fig. 1−7a). When antennas 1 and 25 reach their radiation peak, the adjacent antennas
2 and 26 are activated. As soon as these reach their radiation peak, the upper sideband of antenna
1 is switched to 3 and simultaneously the lower sideband of antenna 25 is switched to 27 (Fig. 1−7b).
This method of activation of the sideband antennas and the modulation of the sideband signals result
in a continuous, almost smooth orbiting of the focal points of radiation of the upper and lower side-
bands.
1 3 5 7
3 2 1 48 47 t
f0 + 9960 Hz
Upper sideband
2 4 6
M
25 27 29 31
f0 − 9960 Hz
26 28 30
Lower sideband
23 24 25 26 27
t
a) b)
1.2.3 Monitoring
According to ICAO, Annex 10 all navigation systems must be permanently monitored for correct radi-
ation by an independently operating monitoring system.
In the case of the DVOR this signal monitoring is performed by one or two monitors, whereby signal
components are obtained via equipment−internal coupling circuits and one (or two) monitor dipoles,
and supplied to the monitor.
In case of dual monitoring these are split by the monitor divider switch and transferred to the two moni-
tors, whereby the monitor 1 signal processing is driven by monitor signal processor 1 and the monitor
2 by monitor signal processor 2 in order to select the various signals in accordance with a specified
control sequence. The actual values of the signals are compared with nominal values by the proces-
sor. Any deviation from the nominal values exceeding specified tolerance thresholds always leads to
an alarm and to an automatic switchover to the standby transmitter or shut down of the system.
A special option is the nextfield monitoring facility. Nextfield monitoring is achieved by one or two next-
field dipoles located on the counterpoise edge. The DVOR installation including nextfield monitoring
comprises additional components and supplies for the antenna system.
The nextfield monitoring can be used with or without the standard nearfield monitor dipoles.
Reference signal
Modulation frequency 30 Hz ±0.01 %
Depth of amplitude modulation 30 % ±1 %, programmable 0 ... 39.9 %
in steps of 0.1 %
Course setting range 0 ... 359.9°, programmable in steps of 0.1°
Identity
Tone frequency 1020 Hz ±0.01 %
Keying (Morse code) Sequence of max. 4 letters, programmable
set time duration (quartz stabilized) Dot/Pause: 125 ms; Dash: 375 ms
Repetition time 7.5 s
Depth of amplitude modulation 0 ... 20 %, programmable in steps of 0.1 %
Voice
Range 300 ... 3000 Hz, flat within ±3 dB
Depth of amplitude modulation 0 ... 40 %, programmable in steps of 0.1 %
Stabilization and linearisation of carrier modulat. With feedback loops for envelope and RF phase
Distortions 3 % for the sum of all harmonic components
Carrier phase stability <±5°, referred to synthesizer reference phase
The DVOR 432 device of the Navaids air navigation system complies with the requirements of EC
Guideline 89/336/EEC in its implementation.
Individually, the device fulfills the requirements of the following EMC Guidelines:
− EN 55022 Ed. 1998 Interference Transmittal, Class B
− EN 50082−1 Ed. 1997 Interference Resistance
− ETS 300 339 Ed. 1998 EMC for Radio Transmission Devices
− EN60950 (IEC950) Device Safety
Furthermore, the device fulfills the requirements of the REG TP SSB FL 008 Licensing Test Regula-
tions for the radio transmission interface.
The supply voltage should always be disconnected by actuating switch TX1 or TX2 on the PMM sub-
assembly before removing a subassembly or a plug−in connection in order to avoid injury to persons
or subsequent damage to subassemblies (for exceptions see Part 2, Operation and Maintenance,
Chapter 6).
WARNING
Mains subunit ACC (BCPS): The device should be disconnected from the mains before
commencing maintenance or installation operations.
The heat sinks of the modulators (MOD−110P) and of the carrier amplifier (CA−100C)
may warm up during operation. This is normal and does not have any affect on the func-
tioning of the devices. Avoid touching the heat−sinks when the cabinet door has been
opened for any reason. When replacing this subassemblies it is recommended to let
them cool down for a while or take suitable measures (e.g. gloves). When replacing the
subassemblies SYN and CCP avoid touching the heat sinks of the MOD−110P.
When replacing subassemblies and plug−in cards containing electrostatically sensitive compo-
nents, special precautionary measures should be taken during removal, transport and installation in
order to prevent damage to the components.
PCB’s containing electrostatically sensitive components are marked with this symbol:
This type of damage may be caused when the person performing the subassembly replacement
bears a static charge due to friction with an insulated floor covering or with synthetic articles of cloth-
ing (eg. soles) and the charge is transferred to the terminals of the MOS components.
In order to avoid this, positive contact should be made between tsystem ground and the hand before
and during removal or insertion of the subassembly. Any body charge is then discharged to the sys-
tem ground. When the subassembly has been removed, the short−circuit bar provided should be
connected to the connector strip, and the subassembly placed in a special container or envelope.
When the subassembly is inserted the appropriate procedure should be followed. The sequence is
described below:
− Discharge the body by touching the system ground with both hands,
− Remove the subassembly from the special container,
− Remove the short−circuit bar from the subassembly,
− Touch the device ground,
− Insert the subassembly, if possible whilst retaining contact with the device ground.
Further instructions on this type of safety measure can be found in the Technical Manual, Part 2.
WARNING
Before starting up a battery, i.e. before filling an empty battery with acid, the relevant in-
structions in Part 2 should always be observed.
Protective goggles should be worn for all maintenance operations which involve opening the acid
screw caps. Any acid which spatters should be removed immediately from the clothing by washing
with water or any soda solution (100 g soda to 1 l water) on account of its highly caustic effect. Penetra-
tion of soda or soda solution into the cells should be avoided at all costs.
When the emergency battery is charged up during mains operation oxyhydrogen gas can result from
the decomposition of the water. For this reason the ventilation holes on the outside of the battery box
should not be sealed.
Some subassemblies in NAVAIDS installations are equipped with transistors containing beryllium
oxide. These transistors are in accordance with the latest state of the art and are used all over the
world.
The ceramic components with beryllium oxide incorporated in the transistors are completely harm-
less in a solid, compact state. The transistors mentioned in the table should never be dismantled or
shattered. Please take notice that if any of these transistors are opened, care should be taken to avoid
any beryllium oxide dust being produced as this is harmful to health.
This notice should also be observed when the components are scrapped or disposed of.
Always read the label on the battery. Thales ATM recommends only those with lithium copper oxide.
Other types of lithium battery, e.g. those with lithium sulphur dioxide, are not approved by Thales ATM
for use in navigation systems (see also instructions in Part 2, Operating and Maintenance, Chapter
6).
WARNING
Do not recharge, disassemble, heat above 100 °C or incinerate any lithium cell. Do not
short−circuit the cell or solder directly on it. Disregard of the norms regarding the use of
lithium batteries may cause the risk of fire, explosion and the leakage of toxic liquid and
gas. Run−down batteries are objects that can pollute the environment and must be dis-
posed of taking the proper precautions.
1.4.6 Miscellaneous
During thunderstorms work outside the shelter or on the antenna system is not allowed due to the
risk of lightning.
In addition to the above−mentioned instructions for avoiding damage and injury, locally valid safety
regulations should always be observed.
The monitor consists of the Monitor Signal Processor, which ensures of correct radiation of the signal.
It evaluates the signals of the internal sensors and the field dipole(s). The selected RF signals are am-
plified, normalized to a certain level, demodulated, filtered and converted to individual, digital values.
The Monitor Signal Processor evaluates the measured values by means of a Fourier analysis and
compares them with the reference values. The monitor changes over or shuts down the transmitter,
if a limit is exceeded. The results can be read out and interpreted locally or remotely via a connected
PC equipped with the suitable software (e.g. ADRACS). A system status indication is also displayed
on the local indication panel. The monitors exchange status signals. If one monitor fails, the intact
monitor decides immediately without waiting for a response from the other. This ensures that the mon-
itors react fast and correctly in all situations, even if one of them fails. The transmitters and the moni-
tors are independent of one another. Depending on the stipulated safety class, either one or two moni-
tors are provided.
The LRCI makes available the following interfaces:
− Communications of the individual functional groups
− Controls for the equipment
− local display and local control of the equipment for the operator
− Remote control functions
All relevant data or parameters can be set locally or remotely via an intelligent terminal (PC/Laptop).
A change−over or shut down is also possible. For integrity reasons data entry (input/change) is only
possible in the maintenance mode (monitors bypassed). Access to the system is barred by a pass-
word procedure with different security levels. The software to be used is referred to as ADRACS.
The battery−charging power supply (BCPS) supplies the entire system with the DC supply voltage
(nom. 48 V). The BCPS can be connected to a mains input voltage in the range from nominal 115 VAC
to 230 VAC. A floating battery connected in parallel ensures that the power supply is uninterruptible.
The BCPS applies the correct voltage required to keep the batteries fully charged. The construction
of the BCPS is modular, with a building−block concept allowing up to four 12 A modules.
Up to three modules (usually provided) are allowed to be used for a mains voltage of 115 VAC with
the normal wiring concept. For a 115 Vac supply with four modules provided, standard mains wiring
has to be adapted concerning diameter of supply cables, size of mains terminals and mains filter.
The main switch on the PMM (Power Management Module) switches on directly the power supply for
both monitors and the LRCI.
Fig. 1−30 provide an overview of the subassemblies and signal flow in the DVOR system.
ANTENNAS (DVOR)
CENTRE ANTENNA SIDEBAND ANTENNAS FIELD DIPOLE 1 FIELD DIPOLE 2
CARRIER 1...48 (optional)
ASU
PIN−Diode Switching Unit (PDSU)
control CSB SB1 SB2
RF−DUPLEXER
CSB
CSB
SB1
SB2
SB1
SB2
RF RF
Signal Generation Signal Generation
and and
Amplification Amplification
48 VDC nom.
(53,5 VDC) Local/Remote Communication Interface
DC/DC−Converter
Emergency Battery 48 V
Mains Telephone line RS 232
115/230 VAC Remote Control Local PC
* Signal divider to both monitors, if only one field dipole is used (standard).
270° (D)VOR
W O 90°
t t
S
180°
t
Counterpoise
RF processsing
Upper sideband
Modulator RF
USB (SB1) Duplexer
Synthesizer D
REF
Lower sideband
Modulator
LSB (SB2)
Fig. 1−12 Generation of the modulated RF CSB, unmodulated USB (SB1) and LSB (SB2)
signals; feeding of the antenna via PDSU
The sideband signal blending modulation and antenna switching control is implemented in the trans-
mitter cabinet. The signal processing of the antenna switching control has the task to process the USB
and LSB cw signals in a form to get the required feeding signal for the even and odd sideband anten-
nas. The basic signal processing concept for one sideband (USB) is shown in Fig. 1−13. The signal
processing for the second sideband is identical. In addition the phase relation USB to LSB with re-
spect to the carrier is measured for phase control purposes. The PIN−Diode Switching Unit assem-
blies are used to commutate the blended sideband signal to the sideband antennas. The blending
function itself is optimized to get a smooth transition and a minimum of spurious modulation on the
9960 Hz amplitude modulation.
Carrier antenna A49
(+47 dBm) A10
CSBin A09
A08 Sideband antennas
CSB
PIN−Diode Switching Unit A07
Z2 A06
26 dB Blending A05
Modulator
CSB cos A04
Blending
Z3 Modulator A01
20 dB sin
USB incident CSB (15 dBm) + USB reflected ASM
3 dB SIN blending COS blending
Detected Coupler odd antennas even antennas
USB
LO
10 kHz Bandpass
USB 10 kHz TP2 IF RF −5 dBm
MOD−SBB A48
A01
SIN ASU−C b
DPDT
switch ASM
COS SP12T
A23
A25
48V A47
30 Hz Sync.
+5 V
ASU−CIF −15 V
Transmitter cabinet Antenna Switch Control PDSU
ASU Control
ASU
D/A Converter
P 80186 Data Register Modulator USB
1 SBA
Phase reversal
Synthesizer
108 − 118 MHz
RF Reference LSB
D/A Converter
1 Control Coupler
P−Bus
The DVOR sideband signals USB and LSB generated by the transmitter are single sideband signals
(SSB−signals). The RF frequencies are 9960 Hz offset from the carrier frequency. Adding finally the
signal processed USB− and LSB−signals to the carrier in the radiated field, the double sideband
DVOR signal is generated.
In addition to the circuit shown in Fig. 1−15 used for the amplitude and phase control of USB and
LSB the feedback loop for the Carrier Signal is realized as an analog control circuit. A control amplifier
(part of the Modulator 110) receives the detected output signal and delivers the control voltage ac-
cording to the digital controlled reference input to the modulator. This analog control is necessary
due to the characteristic of the voice signal which is not periodic.
The Random Access Memory has stored the 30 Hz−periodic DVOR reference signal with the defined
30 Hz AM, the data for the identity signal (ID) are also loaded into a RAM and gets amplitude controlled
by the multiplying D/A−Converter, and both signals are added together by the summing amplifier.
In configurations where a voice signal is specified, also the level−controlled voice signal is added.
While the sideband signals USB and LSB have only the cw−modulation the carrier signal has besides
the 30 Hz AM reference signal in addition an amplitude modulation for the coded station identity signal
and optional with a voice signal (ground to air communication).The various modulation signals being
individual controlled in its amplitude (multiplying D/A−converter) are added together and build the
reference for the analog control loop for the carrier envelope.
The synchronism of the carrier AM signal to the sideband commutation of the ASU is achieved by a
30 Hz trigger signal to the ASU. The control procedure for the carrier RF−phase is not shown in Fig.
1−16. The carrier RF−phase is also controlled like the amplitude by an analog feedback loop. The
RF−reference signal (shown in Fig. 1−15) is used within the control coupler module to get the zero
IF−signal of the output of the carrier amplifier. The amplitude of this zero IF−signal will only be zero
volt, if the carrier signal is in phase quadrature to the RF−reference signal. This criteria is used to con-
trol the carrier RF−phase.
Summing Amplifier
0.5
S12 (t) 0
−0.5
−1 t
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035
1/30 s
2048
1536
1024
512
t
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035
The control process is implemented in time multiplex mode for the individual signals, with measure-
ments and data register updates of control data in a sequence of:
Besides the sideband modulation control function the microprocessor of the Modulation Signal Gen-
erator controls also the measurements of various internal signals of the transmitter as a Built−In Test−
function (BIT−function). The signal measurements are accomplished by the same A/D−Converters
as used for the modulation control signals. To achieve this, in front of the A/D−Converter an analog
multiplexer is used to select the desired signal. The BIT check against BIT warning limits gives an indi-
cation of non normal functional performance and allows to optimize maintenance and eases fault
location of defective modules. The processor internal BIT−check is executed interrupt controlled 5
times per second. In addition with 1 ms intervals the ID coding is controlled.
Since amplitude measurements of the sideband signals close to the zero crossings are inaccurate,
the control voltage is linearized by a special sw−routine in these zones. Starting at fixed interpolation
point addresses to the left and right of a zero crossing, it draws a straight line through the crossing
(i.e. it replaces the sine with its argument).
The procedure for phase control is similar, since the actual values available in the zero crossing region
are likewise inaccurate. Here, the control voltage is formed with the aid of interpolated values to the
left and right of the crossing. Since the amplitude−dependent phase shift in the modulator is small,
the phase control voltage only needs to be pre−distorted slightly.
− Synthesizer−D (SYN−D)
− Modulator−110 (MOD−110)
− Carrier Amplifier 100 W (CA−100C)
− Control Coupler−DVOR (CCP−D)
The RF−Duplexer (RFD) is used in case of an alarm to switch over to the standby transmitter. The
modules MSG−S and MSG−C are without any RF signal processing.
To DVOR antenna system
PDSU
MOD−110 CA−100C
Carrier
actual value
RFD
MOD−110 USB (SB1)
MOD−110
LSB (SB2)
MSG−S CCP−D
Frequency select
BITE
MSG−C
Transmitter 1 Transmitter 2
Communication Interface RS 232C
1.6.5.1 Synthesizer
See Fig. 1−19.
The carrier frequency of the DVOR transmitter is generated by a synthesizer. A Voltage Controlled
Oscillator (VCO) generates the DVOR frequency channels with a frequency spacing of 50 kHz. The
reference frequency is 20 MHz, which is divided by 400 to get the desired value for the frequency de-
tector, which is operated also at 50 kHz. Two further VCOs are phase locked to the carrier to generate
the USB and LSB frequencies. The data for the requested frequency channel is delivered via a serial
data command from the MSG−C module.
VCO LSB
Clock reference PLL2
RF Out LSB
f−9960 Hz
In −6 dB Out
20 dB 15 dB 10 dB 10 dB 13 dB
The control coupler for the DVOR has the function to demodulate the envelopes of the RF−carrier
and RF sideband signals and to detect the RF−phase of the carrier signal.
For the analog control loops, the carrier signal is divided for the precision amplitude demodulation
and for the phase detector. The carrier phase control loop uses the fact, that only signals being in
quadrate at mixer inputs (LO, RF) delivers zero volt at its IF−output.
The actual cw RF sideband signals get amplitude demodulated and are used to control the sideband
output power.
RF input signals:
RF
attenuator
3 dB
Carrier Amplitude
dB
Carrier SPxT select
CSB 3 dB
dB
USB dB
Amplitude
LSB dB
RF Bandpass
Filter
AGC
Amplifier
Sampling Precision
Oscillator Detector
Anti Aliasing
Divider Filter
Sample&Hold
Circuit
A suitable sensor position for the DVOR system is a nearfield Yagi antenna located >100m offset from
the DVOR counterpoise (typically 200 m). Usually one monitor sensor in a dualized monitor system
is used only; its signal is distributed between the two monitors in equal parts by means of an RF power
divider. As an option a nextfield monitoring capability is available.
typically 200 m
* Monitor antenna
Counterpoise
DVOR
* * nextfield monitor dipoles (optional)
The monitor antenna signal is supplied via a RF−band−pass filter (108 to 118 MHz) with steep edges
to an amplifier with a processor−controlled attenuator. This controlled amplifier amplifies the RF level
up to 6 dBm. The composite DVOR signal is demodulated by the precision demodulator, whereby
the DC and AC signal components map ideally the level and modulation depth of the received monitor
antenna signal. The bias voltages of the detector−diodes are compensated and do not falsify the
measurement of the modulation depth of the signal parameters. The straight forward amplifier design
provides the maximum possible gain stability.
The different modulation signal components have to be extracted out of the composite video signal.
The extraction is accomplished by hard− and software modules. The hardware modules to extract
the signal components are:
Due to the design specification the Monitor Signal Processor for the VOR and the Doppler VOR is
identical and provisions are provided for the DVOR antenna monitoring. First the processor−con-
trolled analog switch (Multiplexer1) selects one of the two signal sources (measurement signal or test
generator signal) for the following hardware processing.
Monitor dipole
12 bit D/A
converter
AGC
RF band−pass
filter Precision ID Discriminator
Controlled amplifier demodulator
ATE5
3
The following signal components (Fig. 1−25) after the hardware processing are fed to the Multiplexer
2 and selected for further processing by the microprocessor:
− DC− and 30 Hz AM component,
− Envelope of 9960 Hz subcarrier,
− 30 Hz FM (reference signal) and
− Identity tone (ID)
A single−pole 60 Hz low pass filter allows the non attenuated signal flow only of signal components
having a frequency of 60 Hz or lower. In addition to the signals to be monitored, the Multiplexer 3 is
also used to select and to measure test signals for equipment BIT. Mainly the supply voltages of the
transmitter 1 and 2 are a/d−converted and evaluated.
U(f)
A0
The further processing to extract signal components is accomplished by software. The next filter to
extract the signal components to be monitored is implemented by a Discrete Fourier Transformation
algorithm by the microprocessor. This requires the sampling and digitizing of the analog signals.
U(t) Ax [%]
100 A0
A1
t f [Hz]
0 30 60 90 120
Microprocessor
ȍx
31
A0 + n + A DC |A 1| + ǸR20(1) ) I2m(1) A DC + RF * Level
n+0
|A 30Hz|
ȍx |A 2| + ǸR20(2) ) I2m(2)
31
2p Modulation
depth +
A1 + n e*j32 n + A 30Hz A DC
n+0
|A 3| + ǸR20(3) ) I2m(3)
ȍx
31
A2 +
2p
e*j32 2n + A 60Hz |A 2| )
AAA.|A 5|
n Distortion +
A DC
|A 4| + ǸR20(4) ) I2m(4)
n+0
ȍx
31
2p
A3 + e *j 3n
+ A 90Hz Imaginary
part
n 32 f 30Hz + arctan
n+0 |A 5| + ǸR (5) ) I (5)
2
0
2
m
Real
component
ȍx
31
2p
A4 + n e*j32 4n + A 120Hz q + f Var * f Ref
n+0
ȍx
31
2p
A5 + n e*j32 5n + A 150Hz
n+0
The time interval for each DFT cycle of 64 interrupts is part of an overall time frame, which is periodic.
The overall time frame is three seconds and is shown in table 2 and the monitor frame in table 3.
DFT Measurement Interval for the Function Path in Fig. 1−24 / Remarks
Cycle #
0 − Evaluation of the DC−Component, MUX 1: 0
− Evaluation of 30 Hz AM MUX 2: 0
− Evaluation of the 60 Hz Component MUX 3: I
− Calculation of the 30 Hz AM Vector angle
1 − Evaluation of the 30 Hz FM Index MUX 1: 0
− Calculation of the 30 Hz FM Vector angle MUX 2: 1
− Calculation of the Azimuth (Angle AM − FM) MUX 3: I
2 − Evaluation of the 9960 Hz Envelope MUX 1: 0
− Calculation of the 9960 Hz Distortion MUX 2: 2
MUX 3: I
3 − Evaluation of the 9960 Hz Envelope MUX 1: 0
− Calculation of the 9960 Hz Distortion MUX 3: II /(provisionally only)
( 60/90/120/150 Hz)
4 − Calculation of the 1020 Hz AM MUX 2: 4
MUX 3: I
5 Testgenerator−Signal MUX 1: 1
− Evaluation of the DC−Component, MUX 2: 0
− Evaluation of 30 Hz AM MUX 3: I
− Calculation of the 30 Hz AM Vector angle.
6 Testgenerator−Signal MUX 1: 1
− Evaluation of the 30 Hz FM Index MUX 2: 1
− Calculation of the 30 Hz FM Vector angle MUX 3: I
− Calculation of the Azimuth (Angle AM − FM)
7 Testgenerator−Signal MUX 1: 0
− Evaluation of the 9960Hz Envelope MUX 2: 2
− Calculation of the 9960 Hz Distortion MUX 3: I
8 − Measurement of Temperature Sensor
9 DVOR only: Lower Sideband (LSB) MUX 1: 2
− Evaluation of the 60/90/120/150 Hz Components MUX 2: 0
− Calculation of the Distortion MUX 3: I
10 DVOR only: Upper (USB) minus Lower Sideband MUX 1: 3
− Evaluation of the 60/90/120/150 Hz Components MUX 2: 0
− Calculation of the Distortion MUX 3: I
The relationship sin wt + Ǹ1 * cos 2 wt means that the Am calculation (m = 0...5) can be restricted to the
cos values. In order to reduce the number of multiplication operations to a minimum, the symmetrical
properties of the cos function are exploited, leaving only 7 operations:
cos 11.25° ; cos 22.5° ; cos 33.75° ; cos 45° ; cos 56.25° ; cos 67.5° ; cos 78.75°.
These multipliers are stored in the memory as constants. The following calculations are performed:
Each DFT cycle has a duration of 64 interrupts (exact two complete 30 Hz periods). The first 32 mea-
sured data after the new DFT cycle has been selected are not used for DFT−signal processing, the
time is used to settle. The measurement data defined by interrupts #33 to #64 of a DFT cycle are used
for the signal analysis with a discrete Fourier transformation. Since 32 interrupts correspond to exactly
one 30 Hz period (and 64 interrupts to two 30 Hz periods), the measurements for each channel always
start at the same time with respect to the 30 Hz audio phase. This is important for the azimuth calcula-
tion, which takes direct account of the phase of the 30 Hz AM and 30 Hz FM signals. The measurement
and evaluation cycle is designed so that the values measured for the previous channel are evaluated
during the measurement period of the new selected channel. After the Fourier analysis and the evalua-
tion of the measured values of the different channels have been completed, the monitor checks the
results and assesses the radiated parameter. The monitor alarm check is a comparison of calculated
values of the monitor signal parameter against user programmed alarm and warning limits.
The identity signal is verified by measuring the 1020 Hz depth of modulation. Due to the signal struc-
ture (Morse code keying) the microprocessor checks dots, dashes and space for correctness.
The carrier frequency is monitored by internal signals in counting the frequency of a prescaler output
signal of the synthesizers in operation.
The complete design of the DVOR ASU is based on a concept in having a 50 Ω−matching with a good
VSWR during all switching conditions of the 30 Hz period. Due to this design the sideband antennas
can be used as receiving aerial for the carrier signal transmitted by the center antenna (A49). With
the arrangement shown in Fig. 1−27 at the mixer output a 9960 Hz signal of the considered sideband
is available. In cases the connection to one sideband aerial is missing the 9960 Hz signal gets a gap
in the signal. The 9960 Hz signals derived from the USB and LSB get analyzed and a missing sideband
antenna gets detected by the monitor signal processor.
To optimize the detection, the signal ’detected USB’ minus ’detected LSB’ is generated, in which the
30 Hz AM component of both signals is compensated. Thus the DFT of the USB − LSB gives 30 Hz
and harmonic components which are compared against alarm limits.
A03 USBout Z1
Blending USBin
3 dB
A02 Modulator
ASM
A01 Z3
sine
20 dB
USB reflected + USB incident
CSB (15 dBm) received
3 dB
COS blending Coupler Detected
SIN blending
even antennas odd antennas USB (SB1)
10 kHz 10 kHz
−5 dBm IF TP2 Band−pass USB (SB1)
A01 Mixer
A07 A05 A03
A08 A06 A04 A02
Battery Charging
Power Supply Local&Remote Communication Interface
Cabinet Fuse
Battery Fuse
Emergency PTT line Local PC
Mains 230 VAC
Battery (Pb)
48 V (53.5 V) * Status Exchange
Each equipment (ILS−LLZ, ILS−GP, CVOR, DVOR) includes the LCP which enables the control of
the LRCI functions and the local control by means of a microprocessor 80386 SX (or TI486), as well
as the status display of the station. It consists of a Local Control CPU board (LC−CPU) and a Local
Control Interface (LCI) for main status indication, equipment status and measurement data and
manual controls (switch commands) for basic control functions. Besides serial data interfaces to the
monitor and transmitter processors an RS 232C interface is also implemented for the local PC−con-
trol with ADRACS (Automatic Data Recording And Control System) and to the remote site via the Mo-
dem. Summary of the features:
− Communication to subsystems
− Interface to collocated stations (DME, NDB)
− Built−in−Test−Equipment
− BCPS Control
− Programming station parameters
The LCP represents the interface of the NAV−Station and the outside world e.g. Remote−Control.
The LCP controls ten serial control channels. A NAV−Station normally consists of two transmitters,
two monitors (which are called subsystems) and the LCP. There exists also the option of collocated
stations like NDB or DME which data are also available through the LCP. The Local Control Interface
(LCI) has indication lamps for the main status and a menu driven liquid crystal display (LCD) for indica-
tion of status and measurement data and manual controls to perform simple activities like ON/OFF
or CHANGE−TX. It is controlled by the LC−CPU.
Switching on the Station the LCP reads the configuration−files in the RAM−Floppy, initializes the Sta-
tion and brings it into a normal operational state. The communication between LCP and the subsys-
tems works after the master−slave principle. The LCP sends automatically telegrams (which are
called INTERNAL) with an configured frequency between 0.04 Hz and 10 Hz (in steps of 100 ms) to
the subsystems (monitors transmitters). From the answers of the subsystems the LCP gets the neces-
sary information to compose the Main Status of the station and to check if all subsystems are correctly
working and available.
If the remote control is connected, it is possible to get directly data from transmitters, monitors or the
LCP itself to have detailed status information or to program station parameters. Every time data are
requested from a PC the LCP sends also the INTERNAL telegrams to compose the Main−Status. For
reliability the telegrams are checked with a cyclic redundancy check (CRC) after ANSI X3.99−1979
with the CCIT V.41 generator polynomial.
PDSU/ASU−CIF
DCC +5/−15
ASU/BSG−D
DCC +15, −15, +5
5V 5V
5V 28 V 5V 28 V
+15 V +15 V
−15 V −15 V
28 V 28 V
CSL
LRCI
5V
F1 F2
Transmitter 1 Transmitter 2
TX1 TX2
NAV
PMM
ACC (BCPS−Module) Emergency Battery
54 VDC
Control line
CSB
SB2
SB1
A49
1) Installations 100 W: MOD−110P is replaced by a MOD−110 and a CA−100. The actual RF value output Carrier antenna 49
TRANSMITTER 1 and MONITOR 1 of the Mod−110 is terminated by a load, the actual RF value is now derived from the CA−100. ASU−C
A02
a
RF duplexer CSB
Phase values
Phase control SP12T
Control
SYN−D 30HZO 30HZE
SB2 A23
Sideband modulator SB2 A25
Monitor 1
Monitor 2
+15V +5 V
DCC05/15 Antenna switch ASU−CIF
−15 V
CCP−D control and 30HZ sync. −15V control
48V
RF changeover control
mod. signal
30 Hz AM/identity/voice/DC DC 48 V
Channel select/control
BIT−Signals Actual amplitude value SB
Control line BIT signals TRANSMITTER 2 and MONITOR 2
BIT signals
DCC 28 28 VDC for transmitter
Status
to transmitter 2 ASU / PMC−D
MSG−S
DC 48 V DC 48 V
5V LRCI
DC 48 V TX1
PMM to transmitter 2 DC48 V TX2
V.24 / RS232 Local Control CPU Local Control Interface
On/Off TX1/TX2
VAM MODEM* LCP
ACC Modem* RS232/TTL LC−CPU LCI
(optional)* LGM1200MD o. LGM 28.8 Modem*
ACC Tower Remote site/LGM1** DME/LGM2** NDB/LGM3** Inputs Outputs Diagnosis Analog DME−Interface
48 V nom. (voice etc.) (spare) (spare) ID−Interface
Local PC (optional
Battery ACC (ADRACS)
100 W only Mains 115 to 230 VAC
* optional ** optional for modem *** Standard is 1 monitor dipole, the signal of which is divided to both MSP−VD
Fig. 1−30 DVOR 432, 50/100 W, dual version; simplified block diagram
NAVAIDS
Software packages
User Software
ADRACS
Operation, maintenance
The transmitter software controls the transmitter functions. It is build up with the following software
modules.
− TRANSMITTER_INITIALIZATION
When a transmitter is switched on, this module initializes the transmitter HW for generating the
carrier and sideband modulation signals and resets all power output controlling devices. After the
synthesizer initialization, the antenna switching unit (ASU) is initialized and the adjusted power and
phase control values are set. Then the transmitter starts its operation.
− TRANSMITTER_MAIN_LOOP
After the transmitter initialization, the transmitter software enables the 1000 Hz and communication
interrupts and enters an endless loop. In the endless loop, the following actions take place:
S execution of LCP input commands, if the PROGRAM flag is set
S modulation control
S BITE measurement and evaluation
− COMPLETE_PROGRAMMING
If the PROGRAM flag has been set by the COMMUNICATION_INTERRUPT, this module interprets
and executes LCP input commands based on the specified transmitter command set (alarm limit,
calibration factors etc.)
The DVOR monitor SW is written in the high level language PL/M86 (Programming Language for Mi-
crocomputers for 80x86 processors) from INTEL. Some subroutines are realized in assembler
(ASM86) in order to optimize processing speed. The DVOR monitor SW performs the monitor control
functions. It can be roughly subdivided into the parts "system initialization" and the "system monito-
ring". The most important functions are as follows:
The SW has a relatively simple structure. It consists of main program, which implements the control
flow of the software as a "finite state machine". This method is also used in other modules to establish
their control flow. The tasks of each phase are assigned to main modules, which in turn can call other
submodules, in order to perform further tasks.
After power on the program clears the main memory (RAM) and initializes the interrupt controller, the
timers, the serial interface to the LCP and the various parallel interfaces required by the processor
for monitoring the transmitter. The operating data for the monitor are stored in the non−volatile main
memory (battery back−up). These data are secured by a CRC check word and checked during the
initialization. If the CRC check fails (for example due to low voltage of the back−up battery), the data
are cleared and set to default values stored in a table in the EPROM memory area. In this case, BITE
warning is displayed. After the system initialization, the program enters the main program endless
loop starting the monitoring process.
The data measurement for the monitoring process is controlled by a 960 Hz hardware interrupt, thus
providing equidistant data sampling. Besides the data input from the A/D converter, the 960 Hz inter-
rupt routine performs some further actions, like the management of the time and date counters.
The communication process for the data exchange with the LCP via a serial data link is also interrupt−
driven. However, the 960 Hz interrupt has the highest priority, i.e. if both interrupts occur simulta-
neously, the 960 Hz interrupt routine is carried out first.
After the initialization phase, the program activates the tasks defined for the remaining phases in an
endless loop. At the beginning of the loop, the monitor status variable determines, whether the normal
operation (monitoring process) is performed or an executive monitor action takes places (switch−
over or switch−off). The normal operation first selects the monitor channel for data sampling and then
carries out the data processing of the channel data previously measured. The channel selecting pro-
cess is based on a fixed channel selection scheme (channel selection table) and controlled by a frame
counter. The data processing for the previous channel is interrupted by the 960 Hz interrupt to get
and store the data of actual selected channel.
The main task of the DVOR monitor software is to ensure the integrity of the navigation signals ra-
diated by the active transmitter. If the monitor detects a faulty signal and its alarm delay counter has
expired, it switches the active transmitter off and puts the stand−by transmitter into operation. If this
transmitter also fails, the station is switched off. The main activities consists of
− MONITORING mode
− BYPASS mode.
The behavior in both modes is slightly different. In the BYPASS mode, the monitor accepts input com-
mands. It is used to adjust the monitor settings and during transmitter adjustment or maintenance.
The monitoring process is also performed, except that in the case of an alarm situation, executive
actions are blocked. In the monitoring mode, no input commands are accepted. The transmitter
states (on, off, aerial, stand−by) are full under monitor control.
However, the data output (monitor status, measurement results) is performed in both modes. When
the monitor is switched on, it always enters the bypass mode. There are two LCP commands for
changing manually from one mode to the other. The selected mode is indicated visually on the LCP
display by the lamp hBYPASSED".
Figure 1−33 shows the typical control flow for the monitoring process. While the data for the selected
channel are sampled (controlled by the 960 Hz interrupt, every 1.04 ms), the data of the previous
channel (DFT, alarm check and so on) are processed. The length of a channel (channel time) is 64
interrupts (66.67 ms) i.e. two 30 Hz periods. The data sampled during the first 32 interrupts are not
used, only the data of the second half (interrupts 32 to 63, one 30 Hz period) are stored for further
processing.
POWER
ON MAIN PROGRAM 960 Hz INTERRUPT PROGRAM
SYSTEM
INITIALIZATION
Set Monitor State = 0
START
Switch over action ok
Monitor State=0
Evaluation of Case
Monitor State
MONITOR N
Case 0 or Case 1,2,5
STATUS
"NORMAL"?
Alarm Case
Processing Y
.
. Check of
Channel Select INTERRUPT COUNTER
(x)
. >31 <=31
64 Interrupts x 1,04 ms = 66,7 ms
A
DFT Filtering
(x−1) Input from MSP
64 INTERRUPTS
Complete Programming
Do A
while Interrupt Counter
<64
Change over/Switch off Routine
− initialization
− monitoring process (monitor status = NORMAL)
− executive actions
For modularity reasons, the tasks of these activities are assigned to so called modules (an entity,
which can be compiled and tested separately). The hierarchical structure of these modules is shown
below:
MAIN$PROGRAM
INIT
CMOSRAM$CHECK
Initialization
EPROM$CHECK
CHANNEL$SELECTION
DFT$FILTER
ALARM$CHECK
ALARM$EVALUATION
COMPLETE$PROGRAMMING
MONITOR$MANAGEMENT
- Main Program
This is the control program. After the initialization, it enables the interrupts and enters an endless loop.
The 960 Hz hardware interrupt is the base for the time management. The control flow is implemented
by a finite state machine. At the beginning of the loop, the monitor state variable is evaluated. It con-
trols the transition between the defined monitor states. The states are defined as follows:
INIT
This module initializes the monitor hardware (interrupt controller, timers, serial controllers, output reg-
isters).
CMOSRAM_CHECK
This module checks the integrity of the monitor data in the non−volatile memory area (CRC check).
Based on the result of this check, the stored data are used (check ok) or set to default values (check
not ok, BITE indication).After that, all variables required for the monitor operation are initialized.
EPROM_CHECK
This module computes the BYTE−sum of the installed EPROM’s and compares this sum with the
checksums stored in the serial EEPROM. If an error is detected MONITOR FAULT is set.
CHANNEL_SELECTION
The channel selection routine updates the frame counter which checks the monitor channel timing,
and determines the next channel to be activated on the basis of a channel sequence table. It uses
the channel number to establish the channel selection code and outputs these to registers on the
MSP. It also updates the AGC settings. The routine also manages the channel setup in single−chan-
nel mode, if the monitor is in BYPASS mode. If the single channel mode is selected, the desired chan-
nel number is derived from the programmed channel number
DFT_FILTER
While the measured values of the new channel (x) are being sampled, this module performs a har-
monic analysis (DFT) for the 32 measured values of the previous channel (x−1), in order to compute
the RF level (mean of the 32 measured values) as well as the real and imaginary components of the
30 Hz signal and its first four harmonics (60 Hz, 90 Hz, 120 Hz, 150 Hz).
It determines the individual signal amplitude from the real and imaginary components. Finally, it saves
the computed values for future evaluation.
ALARM_CHECK
This routine uses the results of the DFT FILTER for a further signal evaluation and an alarm check.
Depending on the channel which needs to be processed (x−1), it checks the measured channel pa-
rameters against the set alarm limits, updates the associated alarm flags in the status field of the indi-
cation lamps.
ALARM_EVALUATION
This module starts by checking the MAINAL bit from the status exchange interface (messages from
the co−monitor). If the co−monitor has set the MAINAL bit, it has initiated a changeover or switch−off
procedure. In this case the routine determines the necessary transition to one of the defined alarm
states.
If MAINAL is not set, the routine checks the alarm status output of the ALARMCHECK module (alarm
flags in the status field of the indication lamps) and updates the alarm counter. The further proceeding
depends on the value of the alarm counter and on the monitor bypass, monitor fault and monitor con-
figuration conditions (AND, OR). Based on these conditions, it decides to stay in the current state or
to enter one of the alarm state.
COMPLETE_PROGRAMMING
If the monitor is in the BYPASS mode and the PROGRAM Flag has been set by the COMMUNICA-
TION_INTERRUPT, this module interprets and executes LCP input commands based on the specified
monitor command set (alarm limit, calibration factors etc.).
MONITOR_MANAGEMENT
This module is responsible for internal monitor house−keeping. It manages updates of status infor-
mation (aerial/standby flag, transmitter status, etc.). It continuously compares the set alarm limits with
the maximum permissible limit and sets MONITOR FAULT, if an alarm limit is set outside meaningful
values.
ALARM_EVALUATION
See above, alarm states 1, 2 and 5.
960_HZ_INTERRUPT
The 960 Hz hardware interrupt informs the processor that new, digitized measured values are avail-
able for input. The main task of the 960 Hz interrupt service routine is to accept the sampled data from
the MSP−CD A/D converter. The value of the interrupt counter is increment, and checked after each
interrupt to ensure that it is between 0 and 63. If the value reaches 64, the cycle for the current channel
evaluation is terminated by setting the counter to 0. Based on the interrupt counter, the program per-
forms some further tasks:
− generation of the 120 Hz dynamic monitor life signal
− up−dating of the elapsed time counter
− managing of the frequency measurement
− managing of the analogue BITE measurements
− managing of the identity code measurement
COMMUNICATION_INTERRUPT
This module controls the serial controller on the MSP−CD, which handles the data exchange with
the LCP via a serial interface (RS232C, V.24 level) according to the defined Navaids 400 communica-
tion protocol for the communication process hLCP to Sub−Units" (Sub−Units are the monitors and
transmitters). The LCP is the communication master. The synchronization to the start of telegram is
realized in software, the hardware handshake lines of the serial communication interface are not used.
Start
input
Bypass On
Load requested data to
yes no output buffer
Return
Fig. 1−35 Basic structure of COMMUNICATION INTERRUPT (valid for transmitter and monitor)
960 Hz INTERRUPT
No Action
> 31 <= 31
Input of Channel−Measurement
Data from MSP
End of Interrupt
Fig. 1−36 Basic flow diagram of the 960 Hz INTERRUPT service routine
Ê
ÊÊ
PC Terminal
T_ADW_CTRL
LCP T.BUTTON:OBSERVER
SUBSYSTEM_MANAGER
Internal Communication
T_BCPS T_AUTO
T_SUB T_SUB T_SUB T_SUB
I_AM PERFORM_EXTERNAL_ACTION
RS232 READY PERFORM_INTERNAL_ACTION
CHAPTER 2
TECHNICAL DESCRIPTION DVOR
TRANSMITTER AND ANTENNA SWITCHING UNIT (ASU)
2.1 GENERAL
2.1.1 System Overview
See Fig. 2−1 to 2−3.
The DVOR installation comprises the following main components and accessories:
− Transmitter rack housing the transmitter and monitor, single or dual, the antenna switching control
and RF feeding (ASU subassemblies) and a power supply/battery charging (BCPS)
− Emergency power supply (48 V lead battery)
These components are housed in a building or shelter. Since there is possibility of generated oxyhy-
drogen, the battery is separately housed.
− Antenna system
The DVOR antenna system comprises 49 individual antennas mounted on a counterpoise with a
diameter of approx. 26 m (optional: 30 m) and supported at a height of 3, 5, 7 or 10 m above the
ground by an appropriate number of struts.
− PIN−Diode Switching Unit (PDSU)
The PDSU is seen as part of the ASU subassemblies. As standard, it is located outside the shelter
and mounted with an appropriate support below the DVOR counterpoise. Optionally it can also
be mounted within the shelter.
− Monitor dipole
The nearfield monitor dipole is mounted on a mast in a distance of approx. 200 m from the center
of the counterpoise at a height of approx. 1.3 m above the counterpoise.
As an option, a nextfield dipole configuration can be used instead of or in addition to. For informa-
tion about nextfield monitoring refer to Annex Nextfield in this manual.
− Cable set
− Grounding
The cabinet and the PIN−diode switching unit below the counterpoise are connected via 5 coaxial
RF−cables and a control cable. The switching unit feeds the antenna system via 48+1 coaxial cables.
External signals obtained via the 1 (or optional 2) nearfield monitor dipole(s) are supplied to the moni-
toring system (consisting of 1 or 2 monitors). If only 1 nearfield monitor dipole is used (standard instal-
lation) the coaxial connecting cable between the monitor dipole and the monitor is led in the building
or shelter to a divider, which distributes equivalent signals to the dual monitors.
A grounding network must be laid around the shelter; but there are no special requirements made
with respect to its symmetry.
The DVOR transmitter can be controlled, monitored and maintained from the tower via a respective
remote control and monitoring system (e.g. RMMC).
1...48 A15...A47
49
4 Control
* optional
** Coupling cables between antennas 1...48 and the correspondent decoupling module
SB1/2
3 DVOR−Shelter
are optionally available; the standard version uses no coupling cables. A matcher module is
availiable as option.
Mon2*
Mon1
Tower Carrier
5
7 6
Antenna system
Monitor Dipole(s)
49 1...48
PIN−Diode Switching Unit
Transmitter Monitor
RS 232 RS 232
LRCI
Modem
Operating voltages RS 232
RMMC Terminal
(PC/Laptop)
DC−Converter
Supply voltage
Mains ACC (BCPS)
Transmitter rack
NOTE: Diagrammatic view, dual installation not shown for purpose of clarity.
PDSU
ASU−CIF
DC/DC Converter
* *
DC/DC DC/DC DC/DC DC/DC** DC/DC**
Converter Converter Converter Converter Converter
MOD−SBB
F2
BSG−D **
DC/DC
Converter on/off control on/off control**
on CSL sense
PMC−D sense (Iload/Ibat)
ASU−Interface control
sense
48 VDC
TX cabinet
CAUTION
Do not block or seal the holes for the cooling air supply at the bottom of the rack or the
cooling air outlet at the top of the rack (transmitter)!
WARNING
The heat sinks of the modulators (MOD−110P) and of the carrier amplifier (CA−100C)
may warm up during operation. This is normal and does not have any affect on the func-
tioning of the devices. Avoid touching the heat−sinks when the cabinet door has been
opened for any reason. When replacing this subassemblies it is recommended to let
them cool down for a while or take suitable measures (e.g. gloves). When replacing the
subassemblies SYN and CCP avoid touching the heat sinks of the MOD−110P.
Ed. 09.05
07.04 48 SB 2−5
DVOR 432
Description Transmitter and ASU Equipment Description
PDSU
Housing, not assembled
1 2 3
4 5 6
rear view
front view
1 LCP front panel with key switch
2 front door locking
3 rear door locking
4 Input SB−RF (2x 2); Output SB−antennas (2x 24)
5 Access opening and location of AF control and power supply input if PDSU is mounted indoor
6 Location of AF control and power supply input if PDSU is mounted outdoor
2−6 48 SB 09.05
Ed. 07.04
DVOR 432
Equipment Description Description Transmitter and ASU
1 2 3 4
rear view
front view
Ê ËË Ê Ê Ê
Ê ËË Ê Ê Ê
Ê ËË Ê Ê Ê
USB
LSB
Circulators
Modem*
Modem*
Modem*
BP−C
ASU control
Ê ËË Ê Ê Ê
VAM*
LCP USB
MDS−D*
RFD Components:
Ê Ê Ê Ê
PMC−D
CSB
MSP−1
MSP−2
DCC−3−05
CSL
RF−filter/Relays
Ê Ê Ê Ê
LSB
LSB
USB
Ê
Ê Ê
Ê Ê
Ê Ê
Ê
Ê Ê Ê Ê
cooling baffle
Ê Ê Ê Ê
Ê Ê Ê Ê
MOD−110P***
Ê Ê Transmitter 1 Ê Ê
MOD−110 or
BP−T /TX1
MOD−110
MOD−110
DCC−MV
MSG−C
MSG−S
Ê Ê Ê Ê
SYN
CCP
Ê Ê Ê Ê
Ê Ê Ê Ê
Ê Ê Ê Ê
CA−100/1
Transmitter 2**
Ê Ê Ê Ê
MOD−110** or
MOD−110P***
MOD−110**
MOD−110**
DCC−MV**
Ê Ê Ê Ê
MSG−C**
MSG−S**
SYN**
CCP**
Ê Ê Ê Ê
BP−T /TX2**
Ê Ê Ê Ê
Ê
Ê
PMM
Ê
Ê Ê
Ê
PMM
Ê
Ê
Ê Ê Ê Ê
DC/DC conv. 100 W
BP−DC BP−ASU
Ê Ê Ê Ê
MOD−SBB
MOD−SBB
Ê Ê Ê Ê
DCC−28**
BSG−D
ASU control
DCC−28
Ê Ê Ê CA−100/2**
Ê
Ê
Ê Ê
Ê Ê
Ê Ê
Ê
Ê Ê Ê Ê
AC/DC converter
Ê
ACC**
Ê Ê Ê Ê
ACC
ACC
−−
Ê
Ê Ê
Ê Ê
Ê
BP−BCPS
Ê
Ê
Subracks:
Front Rear
Fig. 2−6 Locations in the DVOR transmitter rack in the 50 W and up to 100 W versions
7 6
9
10 5
11
2−10 48 SB 09.05
Ed. 07.04
DVOR 432
Equipment Description Description Transmitter and ASU
2.2.3 Shelter
The Navaids shelter is used as permanent housing for electronic navaids equipment. The Standard
Shelter is a self−supporting transport unit which is especially suited for the whole range of transporta-
tion means. It stands all climatic conditions worldwide and is designed for a minimum life−cycle of
10 years with the exception of mechanical damages. To cover the requirements the Standard Shelter
bases on the definition on transport containers ISO/DIN standards. It consists of a self−supporting,
distortion resistant aluminium frame construction with eight ISO corners and standardized container
dimensions.
The walls are made of sandwich panels and give options for the fixing of various installation items.
The polyurethane layer ensures best thermal isolation. The floor is covered with an antistatic material
which is connected to the system ground to protect maintenance personnel and to avoid damage
of electronic equipment. The personnel door is located at the front side of the container. It is fitted with
a key lock and can be locked outside and from inside. The inner and outer sides of the shelter are
painted white (RAL 9002), and optionally with an additional outside finish in warning colours as per
ICAO Annex 10. The navaids shelter is anchored using the ISO corners and twist locks to four founda-
tion blocks. The shelter itself is splash−proof, resistant against sea climate and insensitive to salt wa-
ter, fungus and termites.
A complete electrical installation is already provided which can easily be adapted to specific project
requirements. The battery box, which is hermetically sealed from the interior in its operating state, is
accessible from the inside of the shelter and ventilated from the outside. Its shelf−type construction
provides space for a block of batteries (48 V, 256 Ah max.) for the Navaids equipment as well as for
collocated equipment. Ventilation is provided by one or two through−the−wall air conditioning units
and thermostat. The air conditioning equipment is designed to fulfil the environmental conditions for
all products installed in the container. One fire extinguisher is provided. Other options comprise ob-
struction lighting, heater, table and chair, book−shelves, or an additional sun roof.
2438
2991 2438
10 ft Container Shelter
Â
Â
Concrete foundation
L3
Residual
Current Breaker
N 40
I>
0.03
FI1
B2A
PE F4 F3 F1 F2 F5 F6 F7 F8 F9
change o.
Overvoltage
Protection
4 3 1
Spare 2 5 6 7 8 9 10
optional
..
optional
.... + 48 V
− set to heater
.... TX DME A/C1 A/C2 36 °C
....
Earth Collector Bar
20 protected wires
− −
+
twilight obstruction light
Signal lines 90 V/Type F
Emergency battery switch antenna
NF 600 OHM 48 V
Line Terminal Box
Fig. 2−10 Standard shelter, ground plan and electrical installation DVOR (example)
2.3.1 General
All plug−in or screw−on subassemblies (printed circuit boards) in the transmitter rack are described
in Section 2.3, the subassemblies of the antenna switching control and RF−supply which are located
in the transmitter rack and the outdoor PIN−Diode Switching Unit (PDSU) are described in Section
2.4. Their tasks are described and illustrated with the aid of simplified block diagrams. The integration
within the complete system is shown in block diagram Fig. 1−30. More details about the subassem-
blies (printed circuit boards), which may exceed the information given in the following description part
and figures, may be taken from the circuit diagrams listed in Fig. 2−11.
Monitor: 2.3.4
*) The code numbers given may differ to those of the delivered installation in individual cases. In such case the actual code
number can be taken from the delivery list of the installation or the drawing set.
** The MSP−CD, Ref. No. 83135 22301 replaces the MSP−VD, Ref. No. 83135 22300 and the MSP−D, 83135 22400 (nextfield only).
BFR1
V20 REF1
N39 to CCP
N24,59
N40 BFC1
to MSG−S
PLL0 VCO CSB 3 dB
G1 Divider Detector f=50 kHz f =108...118 MHz N4 V19 CSB1
20 MHz D3 N7,6 N11,59 to MOD−110
N
1
Phase/
frequency 3 dB
N9,8 N5,6,7 G2 N3
Reference Loop Filter
Oscillator Select 6 dB
D7 D1,2
V1 V2 V24 V23
6 dB
CSSYN1 BLPLL0
to MSP−VD/MSG−C
Frequency select
6 dB 6 dB
from MSG−C to MOD−110
N D6
40 BFM0
N2 D4 BFSBA0
G3 BFM0
V28 SB1/SBA
7868,400
kHz N17,60 to MOD−110P
Uref N43
N28
VCO SB1
f0−f f=9,96 kHz f0−9960 Hz
N47,49 V25 N16
D10 Detector N22
1
N Phase/
Frequency V39...43 2 dB V26 V27
D17 Select N51,50 N48 G4
Loop Filter
Select
D14,15 Comparator lo
V38 U1
IF HF
f0
N57
CSSYN2 setting
Frequency offset
f=9960 hz BFM0 BFM1
from MSG−C D23
Detector
Phase/ N BLPLL1
D21 to MSP−VD/MSG−C
Frequency BFM1 40
D16,11,12 D8 N15 V53
BFC2
V32 SB2/CSB2
N18 N21,64 to MOD−110P
Uref N45
N29
VCO SB2
F f0+9960 Hz
f0+f f=9,96 kHz
N53,52 V30 N20
Detector N23
Phase/
Frequency V44...48 2 dB V29 V31
D18 Select
N56,55 N54 G5
Loop Filter
Comparator lo
V49 U2
IF HF
f0
N58
BFM0 BFM2
D23
Detector
Phase/ N BLPLL2
D20 to MSP−VD/MSG−C
Frequency BFM2 40
D19,13,22 D9 N19 V54
The carrier frequency is amplitude−modulated in the carrier modulator (CSB) with a 30 Hz signal and
the identification (1020 Hz) and voice signals. The phase and amplitude of the carrier modulator are
analog−controlled. Since no SBO signal is generated in the DVOR system, the phase control voltage
is determined by comparing the measured phase value of the antenna switching unit with the setpoint
selected for the MSG−C. The position of the phase switch is computed by the MSG−C. The ampli-
tude control value is derived from the setpoint selected for the MSG−C and the actual value specified
by the control coupler (CCP).
The RF signal received from the synthesizer is supplied to an attenuator (−9 dB) at the input with a
level of 10 dBm. It is reduced there to a suitable level for the phase switch Z2. This switch allows proc-
essor−controlled phase shift keying (0°/180°) via IC4. The keying ratio can be adjusted slightly with
potentiometer R151, in order to optimize the carrier suppression in the sideband branch (factory ad-
justment). The RF signal is supplied to the first phase shifter Z3 with varicap diodes V25 and V26 and
then the second phase shifter Z1 with varicap diodes V16 and V17. The capacitance of these diodes
can be varied with a control voltage (UPH) via phase control circuit IC2, IC300 and IC1, in order to
set the transit phase of Z3 and Z1. Phase shifter Z3 enables the optimum phase control voltages
(approx. 5 V) of the next phase shifter Z1 to be set (for both the CSB and SBO). IC2 is fed with different
signals enabled by switch IC300 for individual purposes: In the MOD for CSB, IC2 acts as amplifier
for phase control for proportional control of the CSB signal. The I−controller IC1 compensates the
static phase offset and feeds a dc voltage to IC2, whilst IC2 compensates the phase of the CSB signal
as a function of the actual value. The input signals for IC1 and IC2 are obtained from the phase detec-
tor of the CCP. When the MOD is used as sideband transmitter, IC2 acts as amplifier for the control
value for setting the sideband phase. The SBO phase is controlled by software. The control signal
is received from the MSG−C. The RF preamplifier IC9/Q10 follows the phase shifter Z1. This stage
amplifies the level at the output of the phase shifter section to +13 dBm.
The RF output stage consists of three series−connected amplifier stages (Q11, Q12 and Q13). Each
stage is connected to the next stage, both at the input and at the output, by means of a complex trans-
formation network. The input signal is amplified by 10 dB in the RF driver stage Q11, modulated by
the RF driver stage Q12 and amplified by a further 13 dB in the RF output stage Q13. Q12 is modulated
with amplifiers IC6...8. The modulation amplifier disables the control circuit by means of a protection
circuit if the modulation signal is missed, to prevent possible damage to the RF power section. The
output network of Q13 is designed so that no tuning is necessary over the entire frequency bandwidth
from 108 to 118 MHz.
The output line contains a coupler (Z4), which extracts part of the RF at −20 dB and supplies it to the
CCP. When used as driver for the CA−100C this output is terminated by a load. Part of the reverse
RF power is supplied to a demodulator and made available as a BIT signal. The demodulated output
signal is made available via an amplifier (IC10) after decoupling as a BIT signal. The temperature of
the heatsink of the modulators is measured via R325 and fed to MSG−S for evaluation.
The location of the MOD−110 or MOD−110P (transmitter 1 and 2) is shown Fig. 2−6.
RF section 1 RF section 2
R325 to CCP
Detector
Phase switch Phase shifter Preamplifier controlled RF amplifier
0/180°
Reverse RF
IC10 ACxR
Q11 Q12 Q13 Z4
RF in RF out
from SYN Z2 Z3 Z1 IC9/Q10
UPH
R151 ACxM
dynamic
Phase control Driver Q4 IC10
IC4 IC2 Detector
AMC
to MSG−S
RF section 1 RF section 2
R325 to CCP
Detector
Phase switch Phase shifter Preamplifier controlled RF amplifier
0/180°
Reverse RF
IC10
ASBxR
Q11 Q12 Q13
Z4
RF in RF out
from SYN Z2 Z3 Z1 IC9/Q10
UPH
R151 ASBxM
Phase control Driver Q4 IC10
amplifier
IC4 IC2 Detector AMC
Q2, Q3
IC3 IC1
IC3 F1
AF section
Fig. 2−13 Modulator 110 and 110P (MOD−110, MOD−110P), block diagram
The CA−100C is a single−stage RF power amplifier for the 108...118 MHz frequency band with an
output power of 100 W. It operates with a balanced amplifier. The MOD−110 carrier modulator works
as a driver and outputs the control voltage, which is balanced by means of a filter and supplied to the
power FET V1A/V1B. The amplified signal is matched to an unbalanced line via a filter and supplied
to the −30 dB coupler at the output. Part of the forward signal is supplied to the CCP via the coupler.
The reverse signal is rectified and made available as a BIT signal (ACA1R). The signal upstream of
the coupler is likewise brought out as a BIT signal (ACA1) via another detector circuit.
The FET transistors and the wiring board are mounted on a heat sink, whose temperature is moni-
tored with R24. The 28 V supply conductors to the FETs are each protected by a soldered−in fuse
(F1/F2).
28 V
CSB to CCP
Detector −30 dB
R24
Reverse / BIT siganl
V5 ACA1R to MSG−S
Balancing filter Balancing filter
V1A
BIT−Signal
V4 ACA1 to MSG−S
F2/10 A
28 V
The CCP−D is used to condition the forward RF signal components obtained via bidirectional cou-
plers on the MOD−110P or CA−100C (version >30 W). It demodulates the envelope amplitudes and
the RF phase of the CSB and the amplitudes of SB1/SB2, and returns them to the modulator as actual
values. The exact envelope curve is demodulated from the carrier (CSB) for the amplitude control cir-
cuit. An actual voltage is derived for the phase control circuit by comparing the RF phase of the carrier
signal (CSB) with the reference signal (from the synthesizer). The desired signal is electronically
through−connected to the measuring device for digital control of the sidebands (SB1 and SB2); the
amplitude is measured directly, and the phase indirectly, by analyzing the Cartesian components (u
x sin and u x cos ).
The CSB forward signal is supplied to the coupler N54 via a 3 dB attenuator and split into two compo-
nents of equal magnitude. One of the signal components at N54 is used to obtain the actual values
for the analog carrier control loop. The signal required for analog control of the carrier is supplied via
an attenuator and the amplifier N30 to the coupler N49 and split. One signal component at N49 is
demodulated by the precision modulator (N8, N1), then amplified with N7 and made available as the
analog controlled variable FCIA for amplitude control in the CSB modulator. The signal picked off by
the amplifier N2 is supplied to the MSG with inverse polarity as the BITE ACIF signal.
The other signal component at N49 is supplied to the mixer U1 via a 12 dB attenuator. This mixer
compares the actual CSB phase of N49 with the phase of the reference frequency RFref, which is sup-
plied to it directly by the synthesizer via a 12 dB attenuator and the amplifier N31. If the useful signal
and the reference signal are in phase quadrature, U1 outputs a 0 V control voltage via a filter to the
amplifier N9. If the phase shift is increased or reduced however, U1 outputs a proportional voltage,
which is then amplified by N9 and supplied as the analog signal FCIP to the phase shifter in the
MOD−110P (CSB). The absolute value of the RF phase of the carrier is insignificant, though it must
remain constant as a function of time, temperature and modulation depth.
The second signal component of the CSB signal at N54 is supplied to the PIN diode switch N45. The
forward signal of SB1 is injected into this branch via N45 and that of SB2 via N47. The control signals
required for these switches are supplied by the MSG−C. They act on driver stages, which make the
necessary control currents available for the diode switches. The signal produced downstream of each
diode switch is used to obtain the actual values for the three digital loops that control the sidebands
and the carrier. It is supplied to the coupler N51 via a 7 dB attenuator and the amplifier N34, and from
there to a demodulator (N14, N5) that measures the amplitude. It is then made available via the ampli-
fier N15 as the VRFA signal. This signal used for digital sideband amplitude control is supplied to the
MSG−S, digitized and further processed in the MSG−C.
The location of the two CCP−D (transmitter 1 and 2) is shown in Fig. 2−6.
12 dB lo U1 IF P−CS
FCIP
N31 N9 Phase CSB
W1 RF
HFref
from SYN−D N53
12 dB
12 dB R1
R3
N45
9 dB A−S/C
W2
SB1 VRFA
from MOD−110P N14,N5 N15 Amplitude SB
7 dB
W5 9 dB
SB2
from MOD−110P
Signal select
Pin−Diode switch
20 dB
20 dB Z4
26 dB
Z8 Z3
1 1
Circulator Circulator
PMC−D USB 2 LSB 2
Z6 3 Z5 3
TX1 Control TX2
CSB RFD1−C SB1 RFD2−SB SB2
Harmonic filter Harmonic filter Harmonic filter
CSB USB LSB
Z7 Z1 Z2
50 Ohm/100 W/30 dB
50 Ohm/100 W/30 dB
50 Ohm/100 W
Side wall, left, rear view changeover signals Side wall, right, rear view
Fig. 2−16 RF−Duplexer (RFD1−C RFD2−SB) and ASU RF−components, block diagram
SYN
Clock generation Readout control Bus coupling Signal memory
Address
MOD−110
Bus coupling
Chip−Select signals
Decoder
DL0..15
Bus coupling
MSG−S
Processor with AT1..7
memory
peripherals DT0..15
control n
Port signals
CCP
Hardware control signals
Coincidence A/D converter
circuit control
PMC−D
ASU−interface
Par/Ser RS232
Interface to LCP
RS232 LCP
Reserve
MSG−C
− signal generation interface with signal memory (D57,58), address and data in/out registers
(D23,24,26,27,29,30)
− internal control (D31,32) and status register (D25,28)
− local address generation (D42..47)
− transfer and signal generation control circuits (D40,41,48..56) for MSG−S
The signals to be generated and controlled result from the type of installation. The sinusoidal modula-
tion signals are generated on the basis of a sine table with 16384 interpolation points per complete
period. The amplitude resolution is 13 bits. All the sinusoidal signals which are necessary to generate
the Navaids 400 signals can be derived from this table by means of address computations (modulus
16384).
control circuits
SC_AD2 T_CODE0
T_CODE1
7 OUT START_T
16 Bit EQ_CODE
Control Control Control Decoder Register STRT_STP_U
signals signals signals chip select Local Addr. START_AD
16 Bit ALC15
A/D signal gener. signal gener. D/A conv. Register
conversion D29,30 CS ALC16
D54,56 Control 1 SH_1_R
D53 D52 D55 SH_2_R
IN SPREF1
16 Bit SP4TC0
sample
to CCP
A/D Control Register SP4TC1
Conver. Interface signal point SP4TC2
control Register Local data
control generation input C1 SP4TC3
D51
CS D31,32 EN_SIN_COS
D49 D50 D59,60 D26,27
Register D23,24 CS
BLPLL1 SYN
Register Register SH ADR D28
KONC0...10
EN2 BLPLL0
D48 D46 D47
KOINC
DAT_EEP
ASC0..13 A/D direct control
Dekoder Interface control
Serial
Compare EEPROM D22 Watch Dog Trigger
MUX MUX MUX MUX
D40,41 D63 CLK
D42 D43 D44 DME_SHUT_DOWN
EN EN EN EN D45 EN2 0
POWE_ON_OFF
IN
8 Bit AERIAL_STBY
Register M2_FAULT
Counter/divider Status 1 M1_FAULT
491520 Hz Bit 8...15 5VM2
61440Hz D34 D25 5VM1
7.86432 TX DEF (TX address)
30720Hz D35 TC0..17
1920Hz MHz
120Hz D36
30Hz D37
D38
OUT
T15Hz 16 Bit CSL−OUT0..15
Register to ASU interface on
20 MHz PMC−D (DVOR)
CSL−OUT
RD/WR 2
CS
D17,18
Address
Timer IN
0 8 Bit
Register
CSL−IN CSL−IN0..7; from
ALE ASU interface on
PMC−D (DVOR)
DT/R EN1 D20
Processor 80C186 Data DTC0..15
SCC
P
INT S V3 V2
DEN D16
Control ATC0..15
Rx Tx
INT0
D1 SCC_INT
WDI
The transfer sequence of a value to the MSG−C signal memory is as follows. The registers involved
are D23,24 (output data), D26,27 (input data), D29,30 (signal memory addresses), D31,32 (control)
and D25,28 (status acknowledge). If the transfer control circuit does not react a BIT failure is set.
− output designation address of signal memory
− output designation data
− set transfer start with pulse output to transfer flip−flop
− interrogation of transfer flip−flop status
The transfer sequence of a value from the MSG−C signal memory is as follows:
− output source address of signal memory
− set transfer bit code
− set transfer start with pulse output to transfer flip−flop
− interrogation of transfer flip−flop status at input register
The transfer mode is set with Bit 0 and 1 of control register D31,32. The modes contain: write to signal
RAM, read from signal RAM, write to coincidence register, write to D/A converter (on MSG−S). The
transfer mode "10" sends a statement to the interface control (D49) to write data to the coincidence
register (D59,60). The processor sets the sample point in the coincidence register, at which the A/D
converter control shall execute the measurement synchronized to the timing of the signal generation.
The sideband RF amplitudes are controlled digitally in a "fast" and "slow" mode. Fast control is used
when the operator changes a value, slow control is used for the system in operation. The actual value
is measured as follows:
The sideband RF phases are also controlled digitally in a "fast" and "slow" mode. Fast control is used
when the operator changes a value, slow control is used for the system in operation. The slow control
is called up associated to the 1 ms interrupt. The actual value is measured as described for amplitude
measurement but channel VRFP of MUX1 is selected. If a fault occurs a BIT failure is set.
Analog and digital BIT signals are made available by the MSG−S for checking the reliability of the
signal generation circuits and the controlled subassemblies. The BIT measured values are checked
with configurable limits, and the results are stored in a table which can be displayed on the operator’s
PC if desired. If one of the monitored values is outside the specified limits, the transmitter CPU issues
a BITE warning on the main status panel. This warning is also output on the LCP (Local Control Panel).
The location of the two MSG−C (transmitter 1 and 2) is shown in Fig. 2−6.
The modulation signals which are preconditioned in the MSG−S are passed on to the appropriate
modulators. The MSG−S receives the signals for the amplitude and phase measurements via the
control coupler and forwards them to the MSG−C. The latter supplies the signals for controlling the
actual value measurements of the amplitude and phase. Fig. 2−20 shows the signal path for genera-
tion of the modulation signals for carrier and sidebands, fig. 2−21 the signal path of the transmitter
BIT signals to the MSG−C.
sign VZSB1
VZSB2
DA_LOCAL_CONTROL D/A converter MOD−110
carrier
DL_0..15 MODC1A
MODC2A MOD−110
DA−R−CONTROL D/A converter MODSB1A sidebands
MODSB1P
MODSB2A
DL_0..15 MODSB2P
MOD−110
input register Bit signals
n digital SYN
Driver BIT−Signals
A/D converter SAMPLE&HOLD ANALOG internal
1 MULTIPLEXER analog CCP
1,2
BIT−Signals
external
A/D converter Driver analog
2 SAMPLE&HOLD ANALOG
MULTIPLEXER
HW CONTROL SIGNALS 3,4
STATUS SIGNALS
PORT SIGNALS n
MSG−C MSG−S
N1 N3 N5 N8 N10 N11
Setting
DL0..7, 8..15
UREF_10VN
UREF D
AT1..7
10V A CSB1_ST
N17 N13 N15 D
A CSB1_ST6
Summing N14 N16
MODC1
CSB1 signal
DT0..7, 8..15
CSB1 Setting
D Identity 1020 Hz Uref CSB1 power
signal ID
A generation VOICE
N2 N4 N7 N9 N12
ID_ST
UREF_10V
ID_CODE Morse code keying SEL_SB2P= 0 : Phase control signal generated via RAM (ILS/VOR)
SEL_SB2P= 1 : Phase control signal generated via UREF (DVOR)
UREF_10VN
Setting SEL_SB2P N6 Select phase control signal
Mod. depth for SB2 modulator
voice
D VOICE_CSB
A SB2P_ST1
Setting
N19 N21,22 CSB2 power
Summing
CSB2 signal
Voice D
A CSB2
N26 N25 MODC2
D
A Setting
N18 N20 Phase control signal
N24 CSB1 modulator
D
A CSB_1_P
N33 N32 CSB1P
D
A
N29 N31
Setting
Generation SB1 power
Phase control signal
CSB1 modulator D
A SB1A
N27 N25 MODSB1A
SEL_SB1A= 0 : Amplitude modulation signal generated via RAM (ILS/VOR)
D SEL_SB1A= 1 : Amplitude modulation signal generated via UREF (DVOR)
SEL_SB1P= 0 : Phase control signal generated via RAM (ILS/VOR)
A SEL_SB1P= 1 : Phase control signal generated via UREF (DVOR)
N23 N24 SEL_SB1A
Setting
Generation Phase control signal
Ampl. mod. signal SEL_SB1P SB1 modulator
for SB1 modulator N28
D
A SB1P
N34 N32 MODSB1_P
D
A
N30 N31 Setting
Generation SB2 power
Phase control signal
SB1 modulator D
A SB2A
N42 N40 MODSB2A
SB2P_ST
D SEL_SB2A_0= 0 : Amplitude modulation signal generated via RAM (ILS/VOR)
A SEL_SB2A_0= 1 : Amplitude modulation signal generated via UREF (DVOR)
SEL_SB2A_1= 0 : Amplitude modulation signal selected with SEL_SB2A_0
N35 N37,38 SEL_SB2A_0 SEL_SB2A_1= 1 : Amplitude modulation signal generated as CSB signal
Generation SB2A_ST
Ampl. mod. signal SEL_SB2A_1
for SB2 modulator N41
D
A SB2P
3 Select signal N39 N40 MODSB2_P
D Control SEL_SB1A
register 1 SEL_SB1P Setting
A Low Byte SEL_SB2A_0 Phase control signal
N36 N38 D1 SEL_SB2A_1
SEL_SB2P SB2 modulator
Generation Control
Phase control signal register 2 8 Sign select signal
SB2 modulator Hi Byte for CSB and SB1,2
D2 −−−− not used in CVOR/DVOR
N46
MOD/2
bit 0 BLMODC2
BLMODSB2
BASU (DVOR)
BFR0
INPUT Register
BFC0
SYN
SEL1_4 BIT−signals BFSBA0
Control register Bit 8...15 BFSBB0
from
2 4
Spare
Low Byte EN2 D18
3
C1 D7 IGS_C1
IGS_SB1
IGS_C2
to modulators
Control register 8 IGS_SB2
2 P_MODE_C1
CTRL_15
C1
Hi Byte SEL2_4 VZC1
D9 VZSB1
VZID
VZC2
VZSB2
Generation VRFP
sign 3 bit 0 VCC
CSB1, SBO1 FF CSB1ST2
input signals identity D13 CSB1ST5
D15 CSB1ST6
from control WR_DAC CSB1S2
register D2 2 Analog IDST2
FF IDST1
(see 1 of 2) Generation Multiplexer VOICEST
sign SEL1_4I D14 3 CSB1PST1
CSB2, SBO2 CSB1PST2
SB1AST1
D16 Converter 2 EN SB1AST2
SEL2_4I SB1AST3
Sample SEL0..3 D10 SB1PST1
D SB1PST2
&
A Hold
D12 N44 SB1PST3
bit 0 CSB2ST2
CSB2S2
SB2AST1
SB2AST5
control Status control Analog SB2AST6
Multiplexer SB2AST7
from/to MSG−C SB2PST1
4 SB2PST2
SB2PST3
VN−15−M
VP+15_M
EN V+28−1−M
V+28−2−M
SEL0..3 D11 ASP3
−−−− not used in CVOR/DVOR ASP4
The calculated sum curve of SB1 (SBA) is called up from the signal RAM and fed to D/A converter
N23, the phase control signal of SB1 (SBA) to D/A converter N30. Both are conditioned via software
controlled switch N28 for the type of installation (CVOR or DVOR) and supplied to multiplying D/A
converters N27 (power setting) and N34 (phase control signal setting) before they are fed to the side-
band modulator SB1 (SBA).
The calculated sum curve of SB2 (SBB) is called up from the signal RAM and fed to D/A converter
N35, the phase control signal of SB2 (SBB) to D/A converter N36. The amplitude modulation signal
is conditioned via software controlled switch N41 for the type of installation (CVOR or DVOR) and led
to multiplying D/A converter N42 (power setting). The phase control signal is conditioned via software
controlled switch N6 for the type of installation (CVOR or DVOR) and supplied to multiplying D/A con-
verter N39 (phase control signal setting). The sideband modulation signals are fed to the sideband
modulator SB2 (SBB).
The generation of the signs is controlled with the signal WR_DAC in D13,15 (sign CSB1, SBO1, iden-
tity) and D14,16 (sign CSB2, SBO2) and fed to the modulators. Control register D9 supplies the inter-
nal gain switch (IGS) control on the individual modulators.
The MSG−S contains four 16 to 1 multiplexers (D5,6,10,11) for evaluation of the analog transmitter
BIT channels including temperature measurement circuits (N45,46) for CA−100C, MOD−110 and
MSG−S itself. In DVOR installations additional 16 inputs (located on BSG−D in ASU rack) are fed
to input 15* (signal ADVOR) of multiplexer 1 (D5).
The MSG−C calls the BIT signals via control register D7,9. The signals are fed to the sample and hold
circuit N43,44 and converted to digital signals with A/D converter 1 (D8) or 2 (D12) and read for further
processing in the MSG−C. The digital BIT signals from the synthesizer and modulators available at
input register D17,18 are selected via Decoder D4 and read via the data bus from the MSG−C.
* (counting 0 to 15 for a 16 input multiplexer it means IN14)
The location of the two MSG−S (transmitter 1 and 2) is shown in Fig. 2−6.
The monitor section, which has its own microprocessor, monitors the radiated signal and detects any
errors or faults that might be critical for aviation. In addition to executive tasks, the monitor data can
be used to identify any deviations or minor deficiencies in performance at an early stage, insofar as
they might have a detrimental effect on the future continuity of service or system availability (warning
monitor). The response to an alarm is a logic−controlled changeover or disconnection of the trans-
mitters. This logic is described here together with the monitor subassemblies. The monitor subas-
semblies thus comprise:
Processor with
Monitor dipole RF signal processing memory
Peripherals
control
voice, X12, front side Monitor Data
to/from LRCI
Test signal RS232
generator (CSL) Multiplexer AF signal processing Multiplexer Status to/from
Co−Monitor
PMC−D 1 2
(ASU interface)
IN/OUT
Register to/from CSL
Low pass Multiplexer Sample A/D convert.
Analog data 3 & 12 Bit IN/OUT Bit signals
Hold Register internal
DC voltages
All the other signals which pass through the MUX1 are amplified and filtered out in the AF signal proc-
essing section for subsequent evaluation and processing. The results of these circuits and the result
of the demodulated identification are supplied to a further 8:1 multiplexer MUX2 (N24). The signals
fed to the MUX2 are:
The output of MUX2 is fed to a 60 Hz low pass filter which amplifies and suppresses the high frequency
interference components of the FM demodulator signal and the 9960 Hz subcarrier rectifier signal
(9960 Hz and harmonics). This signal is fed to channel 0 of a 16:1 multiplexer MUX3 (N28). In addition
the 9960 Hz subcarrier rectified signal is directly fed to the channel 15 of the MUX3. The other channels
of MUX3 are assigned to BIT signals of the dc converter. The output of MUX3 supplies the signals
selected by the processor to a sample and hold circuit (N29) and the A/D converter (N30). The fre-
quency signals of the synthesizer are fed to a digital 8:1 multiplexer MUX (D31) and selected for fre-
quency measurement in circuit D32. The measurement is executed for carrier (CVOR,DVOR) and up-
per and lower sideband (DVOR only). Depending on the interrupt scheme, the processor requests
the respective instantaneous value for evaluation. The measurement and evaluation of the signals
(first order parameter) including the frequency measurement results of D32 are executed in a fixed
monitoring time frame based on the 960 Hz interrupt signal. Each 960 Hz interrupt marks a measuring
interval. That means the processor is informed that a new measuring value at the A/D converter (N30)
is ready for transfer. The measurement of the analog BIT signals at MUX3 and the evaluation of the
indication signal are integrated in the general channel timing.
to MSP−CD/x
FAUREC2
N18 N22 0 MAINAL1
4...7 N6 SEL Morse−Indicat. TEGAL1*
dc keyed acc. to OUT FIRAL1
16 Bit SECAL1*
ATIS Morse code Register NFIAL1*
dc+30 Hz AM TESTAL1*
voice output MON_EXIXST1
X12 TX1 ON
N7 150 Hz X30/a10 TX1 OFF
600 Ohm used for
to CSL
TX2 ON
3.5 mm jack bush 30 Hz FM TX2 OFF
dc offset +30 Hz FM measurement only TX1 AERIAL
TX2 AERIAL
CS POWER OFF
D17,18
POWER ON
from MSP−CD/x
2 MAINAL2
Limiter 9960 Hz 30 Hz FM X28 5 kHz 0 TEGAL2*
FIRAL2
V46 N19,20 V17..21,N23 N26 SECAL2*
reserve 3 NFIAL2*
TEG ATE5 TESTAL2*
IN !MOFAU2
0 SEL 16 Bit !MOFAU1
dc + interference 1 OUT Register RFR1/1
Analog RFR1/2
from CSL
2 MUX 2 16 Bit RFR2/1
9960 Hz AM−Dem. 3 Register RFR2/2
4 OUT RFR3/1
N25 not used 5..7
MUX/att RFR3/2
N17,V24,25 control CS
D20,21 RFR4/1
N24 RFR4/2
D28,29
AF signal CS 2
60 Hz D/A control
Decoder
5VT1 0 Watch dog trig.
15Vt1
SEL to D14
−1
4 D23 Interf. control
15VNT1
28VT11 6
BIT signals 28VT21
DC converter 5VM1 4 0 STS AD
from SYN1/2
5VT2 3 Morse Code
15VT2 OUT BLPLL0/1
15VNT2 −1
12 Bit BLPLL1/1
28VT12 BLPLL2/1
28VT22 Analog A BLPLL0/2
5VM2 MUX 3 S&H IN BLPLL1/2
ABAT BLPLL2/2
N29 D 16 Bit
UREF_10V N28 Register BTX1/T1
BTX2/T1
from CSL
N30 BTX3/T1
BTX1/T2
4
960 Hz
BTX2/T2
BTX3/T2
CS D26,27 CHOV1
UREF 7,86432 A/D conv. Power On Off
MHZ
UREF −9.1V Control
BFM0/1 0
SEL Register not used
BFM1/1 1 Digital
BFM2/1 MUX
2
BFM0/2 3 OUT Timer 1 Timer 2 CS
BFM1/2 4 16 bit 16 bit D30
BFM2/2 Serial
D31 DATEEP
not used 5..7 EEPROM
GATE
D35
SCC
Address P
INT S
Timer 0
D16
20 MHz
ALE Rx Tx
G2 DT/R RD/WR 2
RS232 LRCI
Data Rx/Tx
Processor 80C186 Reserve
D19,22
SCC INT
DEN Control
INT0
D1 INT1
ABAT WDI from D23
The results of the monitoring are supplied to the Local Control Panel (LCP) to inform the operator at
any time about the actual status of the installation. The data is exchanged with the LCP via a serial
RS 232 interface (D19,22). The communication is interrupt controlled via the serial communication
controller (SCC) D16. The baud rate is 19200 Hz. The LCP is master for starting a data exchange. It
permanently requests the indication information from the monitors. The communication flow is indi-
cated by LED at the front panel of the MSP−CD board.
The monitor processor comprises an 80C186 microprocessor (D1) and the peripherals needed for
various purposes. The processor functions are defined by the associated software. A live LED at the
front panel of the MSP−CD board indicates operation of the processor. The processor and its periph-
erals have the following structure:
The monitor checks the EPROM sets (D7,8) during the initialization phase. The checksum of each
EPROM is stored in the EEPROM (D35). The input/output registers are used for transmitter control
signals to the CSL (D18,21,27), status signals from the synthesizer (D26), internal control (D24,25,
D28,29), feedback (D30) and coordination signals (D17,20) for executive monitoring and status ex-
change with the co−monitor.
The location of the two MSP−CD (transmitter 1 and 2) is shown in Fig. 2−6.
Delay 2 DME−Interface
TDELAY 7.5 Hz counter M2_1
from TG/D2 M2_0
D1,19,34 M1_1
PAL=programmed array logic M1_0
Fig. 2−26 Control and Selector Logic (CSL), coaxial relays control
Battery monitoring (Fig. 2−27): In case of mains failure the power supply is continued without inter-
ruption by the connected emergency batteries. This means that the battery parameters have to be
tested to ensure the availability. The battery monitoring circuit (N15) measures the battery parame-
ters. The results are evaluated and respective actions are executed by the processor of the LCP. The
signals 1/2 (UBAT1±) and full (UBAT2±) battery voltage, battery current (IBAT±) and installation current
(ILOAD±) are supplied via differential amplifiers (N12) to the input of 16:1 multiplexer MUX (D11). The
current is proportional to the voltage drop over a resistor (0.002 ) located on the BCPS connection
panel (cabinet) each in the negative supply lines to battery and installation. The signals selected are
measured with the digital voltmeter DVM (D14) and fed to the LCP. The battery current is used as an
indication of the available battery capacity. As a result the DC converters for TX1/2 first are deactivated
by software command if the capacity falls below a programmed minimum value.
N17
user X22 UREF 2,5V Comp. PF54 to PMM* Low if
X19 X20 defined UBAT > 48V
X21 R jumper enabling optional
hold−in circuit N9,14 V35 UBATmin to CSB
Low if
UBAT1− N12 not used Bat. discharged
UBAT1+ 0
1
U1 or fuse F2 blown
2
UBAT2− N12 control (MUX0...3)
3 from LCP
UBAT2+ 4
5
IBAT− 6 DVM
N11 7 MUX A/D conv.
IBAT+ 8 to LCP
R6 9
R5 10 D14 measured votage value
11
ILOAD− 12
N11 13 X19: 1.7 V (=40.8 V)
ILOAD+ X20: 1.8 V (=43.2 V)
14 X21: 1.875 V (=45 V)
Analog in (from X84 BP−CD) 15 D11
Temp in (from X81 BP−CD) R5/R6 factory adjustment R = continuous setting (40.8...45 V)
Fig. 2−27 Control and Selector Logic (CSL), battery monitoring, over−discharge protection
DME interface (Fig. 2−28): The function of DME interface is to through−connect the identification
code or the identification sync. signal of the CVOR/DVOR if they are collocated with a DME, so that
the CVOR/DVOR and the DME identifications are synchronized according to a defined pattern. If one
of the systems fails, the system which is still operational is informed by means of a digital signal. A
DVOR failure causes the DME identification to fall out of sync with the DVOR. A DME failure is reported
to the MSP−CD of the DVOR. Jumper on the CSL allow to match the exchange signals to the collo-
cated DME. Electrical isolation is ensured by the optocouplers in the interface functional group.
X5...X8 1−2=Optocoupler interf. 1
X7
X5...X8 2−3=Optocoupler + Darlington interf. 2
PAL +15 3
ID_OUT+
5VT2 ST_1 (24ID)
CHOVI ST_2 1 X8
ID_CODE DME/T1 V28 U1 2 3
ID_CODE DME/T2 V27
X11 ID_OUT−
3 2
5VT1 V77,75
MON 1 FAULT (DMEID)
1
T30/T1 V97
T30/T2 MON 2 FAULT 1
M1_0 X5
DME_ID or SYNC
2 OP_OUT+
M1_1 +15 3 (DMSL)
M2_0
STATION Operational X6
M2_1 1
D33 2 3
X12
3 2 OP_OUT−
ASSOC=1−3, 4−6 V77,,78
DME_STATUS X25 IND=2−3, 5−6 1 (VOROP)
V96
1 2 3
P12 S5
1
DMSD1 U2 3 OP_IN+
2
Inverter (DMSR)
4 X15
P13 6
DMSD2 D20 1=DME off V98 5 OP_IN−
0=DME on
(DM0VS)
The local remote communication interface functional unit (LRCI) is the focal point for communication
between the various functional groups, the local control panel (LCP) and the remote control, and is
also used for certain other services (input for voice, weather report from the tower, etc.). The LRCI
consists of the following subassemblies:
Each installation contains an LCP, which controls the LRCI functions and is responsible for local con-
trol and the local main status of the station. In addition to the serial interfaces for communication with
the monitor and transmitter processors (MSP−CD and MSG−C), it has an RS232 interface for con-
necting the local control unit to a standard PC with the ADRACS software and controls communica-
tion with the remote site via the modems. The LCP is supplied by an individual DC−Converter module
/3 on the DCC−3−05 board with +5 V and with ±15 V from the DC converter on the CSL.
RS232 in/out RS232 RS232 RS232/485/TTL opto out opto in in/out in out
opto out
Local Control CPU (LC−CPU)
Microprocessor DIMM−PC/386−I or DIMM−PC/520−I
in/out
Input S
Local Control Interface commands Register port8 RS232 Channel 8
(LCI) 3 Rx/Tx PC Com 1
8 bit Local PC
Ubat Fault D13 D78 X4
Out5...7
Output RS485/
TTL TX1 on
Register 422
X7 3
TX1 off TTL Channel 5
to CSL TX2 on 8 bit SCC
16552 ILS MK20A
X2 TX2 off
AUX 1
Out4 D41
P RS232
port5 Rx/Tx configuration
jumpers
Control
33/100* MHz S
port10 RS232 Channel 10
Process. clock
Rx/Tx Mon 2
PC104 board D64
Address bus
DIMM−PC/386−I or
DIMM−PC/520−I
Data bus Optocoupler
Input via CSL
Register X6 Interface
7 Parallel
Reset 8 bit 4 Addin 1..4
4
S2 Ubat Fault D33 D36...39
SCC clock
PAL Battery microprocess.
Decoder SL−389 Supervisory to D13
D86 3,6 V D83 D74
X35 1.8432 MHz Optocoupler
battery on Output via CSL
X36 Interface
IRQ watch dog on
Input Register X6
BCPS1
3...6 TTL Register to PMM/
BCPS2 7
10 6 BCPS
BCPS3
14...15 HD−LED Life LED
from CSL 8 bit 6 6 Parallel
BCPS4 8 bit
X2 TX1 on D3..6, 16,17 Addout 1..6
D62 D17
TX2 on
from
power supply X5 DCC−3−05/3
S1/1...8* +5 V/+15 V/−15 V
* with DIMM−PC/520−I * for optional use and CSL
I/O
33/100* MHz controller
Process. clock
Address
Control
Battery supply
32.768 kHz
Watch Dog/Reset
HD−LED
* with DIMM−PC/520−I
The Local Control Interface (LCI) forms the local interface to the operator. It contains indication fields
for showing the local main status as well as a liquid crystal display (LCD) screen section, which is used
for control and indication functions useful for the operator to perform the most important control func-
tions locally and to recall measurement data of the transmiter and monitor. Additionally a key locked
switch function is established to change from local to remote control or to maintenance local opera-
tion. The graphics LCD screen can display up to 16 lines with up to 40 characters. The LCI is flush
mounted to the front door.
LCI LC−CPU
Audible
Alarm device B1 device
driver
X9
control lines
in/out
H1 to 3 Indicators Indicator
driver
Data
display data
Liquid Crystal Display Screen (TFT) brightness
R1
DC supply
key button S1 to 4
Key control
X4
key lock Interface
ALARM
Monitor−1 NORMAL EXECUTIVE
Monitor−2 NORMAL EXECUTIVE
WARNING
AERIAL TX−1 ON
DUMMY TX−2 OFF
NORMAL
MAINTENANCE
OPER. MODE REMOTE
REMOTE
LOCAL
MAINTENANCE
Fig. 2−34 Control Interface (LCI), visible front view (text example: system status screen)
receive path
TD
Microprocessor
RD
NOTE: When using the LGM1200MD the permanent line must be equipped with a termination
(600 Ohm/47 nF parallel) at the point where it ends (station and remote ends). The R/C
combination can be soldered onto the 9pin SubD connector together with the two−wire
line.
The location of the LGM1200D is shown in Fig. 2−6.
Software configuration is possible using AT or DNL commands while hardware configuration is per-
formed employing the DIP switches located at the bottom and on one side of the module. It is de-
signed for operation in public switched networks and consequently equipped with an integrated auto-
matic dialing facility (IAWD). Data connections can however also be set up by the subscriber dialing
manually and pressing the data key. Point−to−point operation on dedicated lines (leased or tie lines)
is likewise possible. Almost all the modem functions can be set by the data terminal equipment (DTE)
using a command set in accordance with CCITT Recommendation V.25bis. Correct operation of the
microprocessor and the signal processors is monitored by an integrated circuit, which initiates a
"master reset" if one of these processors malfunctions (watchdog).
A data connection can be set up by means of either the integrated automatic dialing facility or the
automatic call acceptance feature. It is also possible to dial out or to accept incoming calls manually.
No dialing takes place on dedicated lines. All the V.25bis commands and messages are exchanged
via the interfaces which are also used to transfer the actual data. After a call request with identification,
the LGM checks whether the subscriber line is already busy, i.e. whether the subscriber is in the pro-
cess of making a call.
If not, the outside line is seized. The LGM then transmits the dialed digits which have previously been
transmitted by the DTE. After the dialing procedure, an intermittent 1300 Hz tone is transmitted and
the modem waits for a constant 2100 Hz answer tone. As soon as this answer tone − which is trans-
mitted by modems with an automatic call acceptance facility − is identified, the two modems start
the prolog (handshake).
A data connection can only be terminated by the DTE, unless there is no carrier for more than 250
ms/10 s. In this case, the line seizure is canceled by the LGM. Eighteen switches are provided on the
If autodial is set, the connection is set up automatically by the modem. The telephone number is noti-
fied to the modem by means of a request (command). This call request with identification can be pre-
ceded by a command for setting the transmission parameters. The command and the desired data
(transmission parameters and telephone number) can be transmitted automatically using the com-
munication software, i.e. the user does not need to concern him or herself with this.
La Busy detection
a2
Lb
Modem controller
b2
G
E
Setting
The voice amplifier is supplied optional on request. It can be used in 100 W versions only. The task
of this subassembly is to process the voice signals received from the tower via a separate two−wire
telecommunications line to enable them to be supplied to the carrier modulator of the transmitter via
the modulation signal generator (MSG−S).
One part of the input stage of the VAM is located on the motherboard of the transmitter rack. It includes
two surge arresters, a transformer for potential isolation of the VAM from the telecommunication line
and − in the secondary circuit − a voltage−dependent zinc oxide protective resistor (VDR). On the
printed circuit board itself are further protective diodes (CR1..4) to prevent the AGC amplifier (IC3)
against remaining over−voltage conditions. IC3 contains two amplifiers and an AGC detector. The
gain is internally controlled as a function of the amplitude of the output via the AGC detector. IC3 is
supplied by the precise voltage regulator IC1.
The output signal of the AGC amplifier is amplified by 24 dB in IC5/1. It then drives the compressor
IC7 and the threshold switch control via IC5/2. The compressor reduces short−term amplitude fluc-
tuations in the AF signal. The signal then passes via an attenuating amplifier (IC8) to a 300 Hz high−
pass filter (IC9, 10) and a 3000 Hz low−pass filter (IC12, 13) for protection of the navigation signals.
The notch filter (IC11) eliminates from the voice signal the frequency components which are either
at the code frequency (1020 Hz) or very close to it. The threshold switch (Q1, Q2, IC4) prevents modu-
lation of the transmitter by the VAM if the voice signal is too weak, or if there is no voice signal at all.
The switch control signal is generated in the comparator IC4/1. The comparator is supplied first with
the rectified output signal of IC5/2 via IC6 and second with a threshold value derived from the voltage
regulator IC1 via decoupling circuit IC2/1. If the conditioned audio signal is below the set threshold
FET Q2 becomes conductive driven by transistor Q1 and the output of the VAM will be disabled. The
modulation factor of the transmitter can be set by means of a soldered resistor (R33) in the feedback
branch of the output amplifier (IC2/2).
R33
Comparator
Input circuit
line transformer IC5/2 IC6 IC4/1
T1
LV1
Reference
voltage
BP−CE
− DC converter +28 V/11 A nom., +15 V/2,5 A, −15 V/1 A, +5 V/3 A (DCC−MV)
− DC converter +28 V/14 A (DCC−28), used in a 100 W version only
− DC converter +28 V/11 A nom., +15 V/2,5 A, −15 V/1 A, +5 V/3 A (DCC−MV)
− DC converter +28 V/14 A (DCC−28), used in a 100 W version only
Group 1 is supplied with the supply voltage of +54 V by over−current circuit breaker TX1 (subassem-
bly PMM), and group 2 is supplied via TX2 (subassembly PMM). Group 1 (group 2) is switched on
and off via an on/off pulse from the LCP via the CSL. The output command for disconnection in case
of a fault is issued by the MSP. Normal ON/OFF commands are entered manually via the local control
interface (LCI), the local PC or the Remote Control. In single DVOR versions group 2 is not available.
Group 3 and 4 DC−converter modules are located on one printed circuit board DCC−3−05. Group
3 supplies the monitors and comprises the following units:
The two DC converters are linked on the input side by an OR circuit; they obtain their supply voltage
of 54 VDC via over−current circuit breakers TX1 and/or TX2. In single versions of the DVOR the
DCC−3−05/module 2 is not used.
Group 4 supplies the units belonging to the LRCI and the CSL and comprises the following unit:
NOTE: The supply voltage of the DC converter described here is a rated 54 V for mains operation
or 48 V for battery operation. In mains operation the operating voltage may rise to 65 V;
in battery operation it may fall to 43 V (monitoring limits). The permitted input voltage
range of the DC converter is therefore between 43 and 65 V. The term "variable input volt-
age" has therefore been used in a number of cases in the description which follows. The
various voltage specifications should therefore be interpreted within this context.
Control
Module 1
10,11 5VM1+/1.2 A
1 11
Pulse Width
Modulator
3
10
13,14 GND
12
2
13
4 14
15 PSMON1
On/Off
16 GNDCPS
Module 2
17,18 5VM2+/1.2 A
1 11
Pulse Width
Modulator
3
10
20,21 GND
12
2
13
4 14
22 PSMON2
On/Off
23 GNDCPS
26 48 v
31 48 V GND
32 GND
V Power section
− Primary safety and softstart circuit
− Input filter
− Power conversion stage 28 V
− Power conversion stage 5 V and ±15 V
− Rectifier and output filter
− Voltage regulators for ±15V
V Control and monitoring section
− Primary controller including
auxiliary voltage generator,
control input On/off,
oscillator, pulse width modulator, controller,
driver stage
− Secondary controller and monitor including
voltage and current monitor 28 V and 5 V,
over/under−voltage and temperature monitor,
BIT/Alarm signalling
The DC supply voltage is converted into an AC voltage in a forward converter (FWC) for 28 V and a
flyback−converter (FBC) for 5 V and ±15 V. Both converter work with a clock frequency of approxi-
mately 100 kHz. A transformers each, which also ensures electrical isolation of the secondary section,
transforms the input voltage to the required output voltage. The dc converter is primary protected
against overcurrent or short circuit by means of fuse NSI1 (30 A).
If the input voltage is connected incorrectly, diode D1 will be enabled and the fuse is blown to prevent
any damage. R1 prevents against overvoltage peaks up to 130 VAC. The power section is initially iso-
lated from the input by means of the FET transistors T1,T2, which are controlled by IC1 and act as
primary on/off switch. The ON or OFF command which enables the main and auxiliary voltage is sup-
plied via optocoupler IC2.
The incoming voltage is smoothed and noise is suppressed by L/C elements in the input filter. The
voltage is reduced in the power conversion stage by means of electronically controlled chopping. IC5
as primary control circuit generates the chopping frequency of 100 kHz and controls both the driver
stage T11...12,TR6 for the 28 V power section with OUT1 (FWC) and directly the 5 V/±15 V power
section with OUT2 (FBC).
Primary safety circuit Filter Primary power section Secondary power section
Uin+
IC1
U T1,2
48 Vdc TR1
D1 R1
D2 Rectifier Filter
T3
Uin− NSI1/30 A
6.3x32mm +
28 V/11 A
TR2
28 V current
−
T4
U0
D3
FWC current Rectifier Filter
+
5 V/3 A
5 V current
−
U0
TR4 Rectifier voltage
regulator
+15 V
IC101 +
+15 V/2.5 A
TR3
−
T5
U0
Rectifier voltage
FBC current regulator
−15 V U0
IC102 +
−15 V/1 A
−
OUT2
OK LED
Front panel
IC9 temperature
TR5
Uaux. overvoltage
sync2 BIT
Uaux. second. undervoltage signal
IC3 switch
enable T102
5 & 28 V
Remote RT/CT OUT IC7
On/Off current monitor
IC2 T8 Uaux. primary test connector
ref. volt. 28 V, 5 V secondary
Uref
disable
IC6 keep alive
IC8 voltage monitor
reference 28 V, 5 V
voltages
Auxiliary voltage generator Secondary controller and monitor ST2
The 5 V/±15 V power section (FBC) consists of FET transistor T5 and transformator TR3. T5 chops
the DC voltage. The chopped DC voltage is transformed by TR3 to three desired values with three
secondary windings. For the 5 V path the output voltage is rectified and smoothed via an output filter.
The secondary output current is monitored via the voltage drop on a series resistor. For the ±15 V
path the output voltages are rectified, smoothed and regulated to +15 V or −15 V with integrated volt-
age regulators IC101, 102. The regulated voltages are led via an smoothing output filter to the output.
The input voltage for the auxiliary voltage generator is extracted after the smoothing stage. The auxil-
iary voltage for primary and secondary controller and monitoring circuits is generated by an individual
converter built by IC3, T8 and TR5. It works with a clock frequency of approx. 100 kHz.
The output voltage is regulated directly via the turn−on time of the power stage in order to obtain
stabilized voltages of 28 V and 5 V. This regulation is implemented via the primary controller (IC5),
which obtains its information from the various current and voltage sensor circuits. The regulation
takes the form of changes in the pulse width, suppression of single clock pulses and deactivation.
The operational reliability of the converter is ensured by a number of monitoring circuits. The power
stages are protected against overvoltage, undervoltage and overcurrent conditions. It is interlocked
in the event of an automatic deactivation resulting from an overvoltage condition. This interlock can
be cancelled by interrupting the power supply or by entering the Tx OFF and Tx ON commands at
the keyboard of the rack or software command (PC).
A primary or secondary overcurrent condition will lead to pulse width control, which causes the output
voltage to be reduced. The current transformers TR1,TR4 monitor the primary power sections for
overcurrent conditions, whilst the secondary output current is monitored via the voltage drop on a
series resistor for the 28 V and 5 V path. As BIT signal a switch function, which indicates operation
of the DC converter, is implemented. In the event of a malfunction FET transistor T102 becomes con-
ductive and the front LED does not light.
V Power section
− Primary safety and softstart circuit
− Input filter
− Power conversion stage
− Rectifier and output filter
V Control and monitoring section
− Primary controller including
auxiliary voltage generator,
control input On/off,
oscillator, pulse width modulator, controller,
driver stage
− Secondary 28 V controller and monitor including
voltage and current monitor,
over/under−voltage and temperature monitor,
BIT/Alarm signalling
The DC supply voltage is converted into an AC voltage in a forward converter with a clock frequency
of approximately 100 kHz. A transformer, which also ensures electrical isolation of the secondary sec-
tion, transforms this voltage to the required output voltage. The dc converter is primary protected
against overcurrent or short circuit by means of fuse NSI1 (30 A). If the input voltage is connected
incorrectly, diode D1 will be enabled and the fuse is blown to prevent any damage. R1 prevents
against overvoltage peaks up to 130 VAC. The power section is initially isolated from the input by
means of the FET transistors T1,T2, which are controlled by IC1 and act as primary on/off switch. The
ON or OFF command which enables the main and auxiliary voltage is supplied via optocoupler IC2.
The incoming voltage is smoothed and noise is suppressed by L/C elements in the input filter. The
voltage is reduced in the power conversion stage by means of electronically controlled chopping. IC5
as primary control circuit generates the chopping frequency of 100 kHz and controls the driver stage,
which in turn controls the power section consisting of FET transistors T3,4, building a bridge with
D2,3. The bridge circuit chops the DC voltage. The chopped DC voltage is transformed by TR2 to the
desired value, then rectified and smoothed via an output filter.
The output voltage is regulated directly via the turn−on time of the power stage in order to obtain a
stabilized voltage of 28 V. This regulation is implemented via the primary controller (IC5), which ob-
tains its information from the various current and voltage sensor circuits. The regulation takes the form
of changes in the pulse width, suppression of single clock pulses and deactivation. The operational
reliability of the converter is ensured by a number of monitoring circuits. The power stage is protected
against overvoltage, undervoltage and overcurrent conditions. It is interlocked in the event of an auto-
matic deactivation resulting from an overvoltage condition. This interlock can be cancelled by inter-
rupting the power supply or by entering the Tx OFF and Tx ON commands at the keyboard of the
rack or software command (PC).
A primary or secondary overcurrent condition will lead to pulse width control, which causes the output
voltage to be reduced. The current transformer TR1 monitors the primary power section for overcur-
rent conditions, whilst the the secondary output current is monitored via the voltage drop on a series
resistor. As BIT signal a switch function, which indicates operation of the DC converter, is imple-
mented. In the event of a malfunction FET transistor T102 becomes conductive and the front LED
does not light.
Primary safety circuit Filter Primary power section Secondary power section
Uin+
IC1
T1,2
48 Vdc U
D1 R1
D2 Rectifier Filter
T3
Uin− NSI1/30 A
6.3x32mm +
T102
TR2 28 V/14 A
28 V current
−
T4
D3
FWC current
test connector
primary heat sink
Primary controller
TR6 θ
disable 5V
R173
OK LED
Front panel
IC9
TR5
Uaux.
temperature
overvoltage
sync2 Uaux. second. undervoltage BIT
IC3 switch signal
enable T102
5 & 28 V
Remote RT/CT OUT
On/Off current monitor
IC2 T8 Uaux. primary test connector
ref. volt. 28 V secondary
Uref
disable
IC6 keep alive
IC8 voltage monitor
reference 28 V
voltages
Auxiliary voltage generator Secondary controller and monitor ST2
After mains failure, first the remaining battery capacity is calculated from the LCP processor by mea-
suring the current drawn by the load. The result is compared with software−set user−defined battery
capacity limits (Ah). If these limits are reached the transmitter supplies CVOR/DVOR and the ASU sup-
ply (DVOR) are switched off first by a digital command of the LCP processor. The batteries are relieved
as a result. Next the ACC modules of the BCPS are shutdown via optocoupler input with the LCP mes-
sage line Addout2. Jumper X26 on the CSL can interrupt the line to the BCPS.
To prevent cut off by the over−discharge protection circuit on the CSL (V36) the battery voltage is
compared with a jumper−set user−defined value. If this value is reached the LCP processor switches
off the LRCI and Monitor supply via solid state relay K1 with command Addout1 just before the over−
discharge protection is enabled. The hold−in circuit and the over−discharge protection circuit on the
CSL remain operational. If mains is restored before the batteries are cut off by the CSL the hold−in
circuit on the CSL (V35) switches on the solid state relay K1. The LRCI, that is LCP and modem, be-
come operational and the CVOR/DVOR can be maintained via remote control.
0V
X26
Hold−in circuit
PF54
V35
−
BCPS back panel
over discharge
protection
H1,2,3
V36
ILOAD+
0V ILOAD−
IBAT−
PMM IBAT+
UBAT2+
UBAT1+
UBAT−
CSL
Navaids cabinet
The mains unit ACC−54 acts as a AC/DC converter, which generates a stabilized 54 VDC voltage ob-
tained from the mains voltage (wide range input: 115 VAC to 230 VAC, ±15 %). It takes the form of
a push pull switched−mode converter with electrical isolation of the input and output. Up to four
mains units connected in parallel buffer a 48V battery (24 lead cells), which can supply the connected
navigation system with voltage for several hours in case of a mains power failure.
The output voltage is 54 V. This ensures that the battery charge is permanently maintained (2.25 V
per cell, standby parallel operation). The supply to the navigation system from the mains and the bat-
tery trickle charge is still ensured in case of a power subrack failure. A power switch, a fuse, an LED
and two test jacks for the voltage ahead of the isolating diode are located on the front panel. The LED
signals the presence of the equipment output voltage, but not of the battery voltage. The AC/DC con-
verter consists mainly of the following functional groups:
In the input section the input voltage of 230 VAC passes a fuse, an overvoltage protector and an RF
filter to prevent RF interference voltages, is rectified with a bridge−connected rectifier and smoothed
by an electrolytic capacitor. The subassembly also contains a resistor which limits the current inrush.
This resistor is short−circuited by a relay contact (K1A) following current stabilization.
The DC voltage generated in the mains board is chopped in the power pc board with the aid of a push
pull power circuit with a frequency of 20 kHz. The square wave voltage generated in this way is
stepped down in a transformer and rectified. The input and output of the devices are electrically iso-
lated with the aid of this transformer. The DC voltage generated in this way is then smoothed with the
aid of a number of chokes and filter capacitors. The voltage is fed via an RF output filter to prevent
RF interference voltages and a further fuse to the output terminals.
The output voltage is regulated by modifying the pulse width for driving the switching transistor. The
20 kHz control pulses for the transistor chopper are generated in the flux converter controller. The
output current is measured by means of the series resistor in the output line. The voltage drop at this
resistor, which is a measure of the current flow, passes to the monitor DC/DC converter, where it
serves as the actual value for current limiting. The clock generator (oscillator frequency 400 kHz) sup-
plies after division of the frequency the generation of the auxiliary voltage and the controller DC/DC
converter.
An appropriate circuit enables the pulse width to be modified so that the output voltage can remain
roughly constant until the maximum output current of 12 A is reached. When this current is reached,
the pulse width is reduced accordingly. The resulting output characteristic is thus almost rectangular.
The input quantities received by the controller are the output voltage of 54 V and the voltage drop at
a series resistor. These quantities are used to control the pulse width by means of a nominal/actual
comparison. A further circuit interrupts generation of the control pulses in case of an over−voltage
62 V at the output of the power pc board. In such cases the output voltage is also interrupted.
L K1A Filter +
Filter
230 VAC 54 VDC
N −
PE F/1A
−Vout
PE
Temperature
PCFI
heat sink
Control
current measurement
control driver/bridge
bridge current PDCI
section
voltage AC PFCAC
voltage AC ACVLO
voltage DC PFCV
PFCG
Synchronization
R32
Flux converter
DC converter
PFCSync
Primäary
DCSYNC
Fine adjustment
output voltage
for optimization of
charging voltage
clock generator
divider
400 kHz
Secondary
auxiliary voltage
auxiliary voltage Remote
converter On/Off Status
LSB (SB2)
LSB
Z5 ASM
Z4
lo SP12T
MOD−SBB A48
A01
SIN ASU−C b
DPDT
switch ASM
odd SP12T
COS hi
A23
A25
*) In individual cases, the item numbers given here may differ from those of the system which is supplied. In cases of this
kind, the valid item number is that given in the delivery list for the system or in the documentation set.
Fig. 2−45 Circuit diagrams of subassemblies of the Antenna Switching Unit (ASU) function
The SB1 forward signal is coupled out via Z3, then split. One path is supplied to mixer U3. It is mixed
to the CSB signal of N3 for generation of a 9960 Hz signal for RF phase control (R1−10kHz). The other
path is supplied to mixer U2 and mixed with the return signal from Z3. This return signal incorporates
the carrier radiated by the center antenna and received by the sideband antennas. A 9960 Hz voltage
is supplied from the forward and return signals of SB1 for monitoring of the antenna and phasing.
The SB2 forward signal is coupled out via Z4, then split. One path is supplied to mixer U4. It is mixed
to the CSB signal of N3 for generation of a 9960 Hz signal for RF phase control (R2−10kHz). The other
path is supplied to mixer U1 and mixed with the return signal from Z4. This return signal incorporates
the carrier radiated by the center antenna and received by the sideband antennas. A 9960 Hz voltage
is supplied from the forward and return signals of SB2 for monitoring of the antenna and phasing.
The phase measuring circuit, built by D6, takes the form of a synchronous control unit, which mea-
sures the time difference between the two leading edges of the 9960 Hz measurement signals and
stores the result in a latch. This circuit operates independently of the processor and asynchronously
with regard to it. The MSG−C processor disables writing to the latch at the instants at which data is
transferred, in order to prevent the measured value being updated during this transfer. The latch is
the output register for the digital phase measured value supplied to the two MSG−C processors. The
processor of the passive transmitter (i.e. that which is not switched to the antenna) is interested only
in the measured values for the monitor phase. The processor of the active transmitter determines
when the multiplexer through−connects the signals for measuring the sideband phase and when it
through−connects the signals for measuring the monitor phase to the phase measuring circuit. If the
signals for measuring the monitor phase are supplied to the measuring circuit, the processor of the
passive transmitter will be informed to ensure that it only accepts monitor phase measured values.
These roles are exchanged when the transmitter is changed.
The PMC−D contains a reference voltage source, which supplies the D/A converter in the phase mea-
suring circuit and the sideband antenna monitoring with a temperature−stable reference voltage of
10 VDC.
Z8
CSB A49 (carrier antenna)
circulator
Z3
SB1/USB Z5 MOD−SBB
circulator
Z4
SB2/LSB Z6 MOD−SBB
Phase control
3 dB 3 dB 3 dB
N4 N3 N5
RF RF RF
U2 U3 U4 RF
U1
lo lo lo
mixer mixer mixer lo
IF IF IF mixer
X22 X23 X24 X21 IF
SB−antenna monitoring
low pass
+ MO 10kHz
to MSP−CD SBMON N23 −
ME 10kHz
to MSP−CD: 10kHz
Individual antenna fault (BIT), D5
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
M_ANT_DV +
antenna fault (BIT) −
M_ANT D cw N15
ÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
N16,28 3 2 1
X10
ÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
SBMON Compare level
to Mon1 Tx/Rx
to MSP−CD
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍ
to Mon2 D12,13
D16 SB ant. SB ant. D15
ÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
monitor. 5.8982 monitor.
D/A threshold MHz window
dedicated antenna fault comp. SB Mon compare
ÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
N26 30Hz position
recognition SB antenna threshold sync. control
(option; not implemented) N27
Compare out
Phase measurement ME 10kHz D6
clk 5 MHz Mon Stop Phase
Uref phase R1−10kHz
counter
9960 Hz XMT Start Phase
MUX
R2−10kHz
to TX1 Tx/Rx XMT Stop Phase
Phase measurement decoder
values for monitor D5,6 latch MO 10kHz
to TX2 RF phase data bus A0...7 Mon Start Phase
Fig. 2−46 Phase Monitor and Control (PMC−D) including ASU interface, block diagram
The standard SB antenna monitoring circuit, built by N15,16,28 and D5, permits an additional moni-
toring to detect missing sideband antennas. Its function is to supply a low−frequency analog signal
which changes in the event of a failure in one or more of the sideband antennas; the harmonic spec-
trum of this signal (30, 60, 90, 120 and 150 Hz) is evaluated by the DFT. It initiates a BIT alarm if a certain
harmonic component is exceeded. The alarm or warning limits can be set. To reduce the 30 Hz com-
ponent from the carrier modulation both 9960 Hz sideband signals are substracted. If one sideband
aerial is missing mainly a 60 Hz frequency component remains. The software of the signal processing
is adapted in a way not to pass the 30 Hz low pass filter on the MSP. Besides this signal derived from
the SB1 and SB2 processing also the actual processing of the 9960 Hz monitor signal remains.
An optional antenna monitoring circuitry (Fig. 2−46, hatched gray), built by D15,16 and N26,27, al-
lows to define the faulty antenna individually. The sideband antenna monitoring logic provides a shift-
able sample window signal centered around the expected maximum output power of the sideband
antennas (determined through the shape of the blending signals). The TX−software sets the sample
window point according to the sideband antenna it actually intents to monitor. Shifting the window
through all expected sideband antenna maxima, it can check the correct function of all sideband an-
tennas. The sample signal starts 64 clock pulses before and stops 64 clock pulses after the expected
maximum. It controls a comparator with two inputs:
− reference input signal (threshold, adjustable by the D/A converter set once during system installa-
tion, controlled by the TX−SW)
− envelope of the 10kHz sideband antenna signal ME−10K
If the comparator is enabled it compares two signals. If IN− is below IN+ the non inverting logical
output goes high. This will be detected by the monitoring logic and the antenna fault flag will be set.
The TX SW will evaluate this flag and determine which sideband antenna is concerned.
At time this function is not implemented.
2.4.3.3 ASU−Interface
The ASU−interface section is a part of the PMC−D subassembly, but comprises individual tasks. To-
gether with the BSG−D subassembly, the ASU−interface forms the data link between the DVOR
transmitter and the ASU subassemblies. The data communicated on this link includes control infor-
mation for the ASU subassemblies and information for transferring the phase values measured for
SB1 and SB2 − referred to the carrier − after they have been digitized and BIT signals. The ASU−in-
terface contains a multiplexer block (D1...D4) and interface drivers (D8...D11), which are used to con-
nect the control lines for the ASU. In the opposite direction, the measured phase values are supplied
from the ASU to the monitor processor (MSP−CD) via V.24 receivers (D5/6). A connected decoder
detects when the active monitor (in other words the monitor whose transmitter is currently switched
to the antenna) receives a phase value from the ASU.
The definition of each MOD−SBB to be dedicated to USB or LSB is achieved by jumper X8 and X9
which feed the input sine or cosine blending signals to the RF1 or RF2 modulator path.
V3
BIT signal
XSB SIN CON to BSG−D
actual value DEM XSB SIN
RF Modulator 1
demodulator
− U pin1 Rf
setpoint X ANT SEL USB/LSB
control from BSG−D
3 + N7,5 V23,24
Sine blending X9* AGC amplifier 0° N1
from BSG−D 1 W3
X HI out
to PDSU
sin
delay line W2
90°−Hybrid from MOD−SBB 2
XSB RF in
coupler 20 dB
W4
2P2T switch X LO out
to PDSU
90°
peak detector UDEM XSB SIN to BSG−D
Rf
to BSG−D
V25,26 comparator RF peak correction
N16,19
−3 dB N10 cw/SB power
divider peak detector
U RF offset cw/SB power
W1 X5 X4 X3 select
RF IN USB (LSB)
N2 demodulator N14,20
peak detector to BSG−D
from RFD2−SB comparator RF peak correction
1 N9 CW/SB power
−3 dB
Rf N11,21
UDEM XSB COS
to BSG−D
V27,28 V1
0° to BSG−D
B XSB RF CON
cos coupler 20 dB W5
90°−Hybrid to MOD−SBB 2
XSB RF out
The BSG−D represents the "control centre"in the ASU function. The BSG−D generates and pro-
cesses the blending signals, performs the control of the antenna switches and provides the dc power
supply for the ASU subassemblies. The tasks performed by the BSG−D are as follows:
− transmitter interface
− analog BIT signal selection
− blending signal generation
− blending signals amplitude control
− antenna select signal generation
− driver interface even antenna select signals
− driver interface odd antenna select signals
− dc power supply for ASU subassemblies
The blending signal generation is as follows: A crystal oscillator drives a 1:16 divider. This divider sup-
plies 368.640 kHz clock pulses to the 9 bit address counter (D17). The address counter controls the
start time with the data got from the BSG−D bus. It is used to read the precise shape of the "sine"
and "cosine" envelopes (blending function) stored in digital form in EPROM D1. It also controls trans-
fer of the data to the d/a converter memories. The repetition rate for the complete counter cycle is 720
Hz. The divider as well as the address counter is reset every 30 Hz cycle by the 30 Hz synchronisation
signal from the CSL fed by the PMC−D.
The EPROM stores 8 waveforms. Two of them are used and selected by software and load to two 8
bit latches. The blending waveform for the even antennas starts with the leading edge, the one for
the odd antennas with the trailing edge of the 720 Hz cycle frequency. The data from the latches are
d/a converted and fed to four further d/a converters used as amplitude control for the four control sig-
nals (USB SIN/COS and LSB SIN/COS) which are fed to the blending modulators MOD−SBB. The
amplitude of the four functions is set digitally via the appropriate latch settings. According to the set-
ting data for the blending waveform the multiplying d/a converters change the amplitude modulation
of the 9960 Hz components.
These values for setting the amplitude and all other setting functions for control are selected by the
MSG−C whose transmitter is switched to the antenna. The data signals are received via the PM−C
and forwarded to registers (data bus BSG−D). The control signals are received and decoded. The
selected register accepts the data from the bus synchronously with the internal clock. In addition to
the data for setting the amplitudes of the 4 blending functions the MSG−C also transmits the select
information for through−connection of the BIT signals, the antenna control code and the control sig-
nals for the phase measuring circuit.
The 4−bit code decoded in D18 determines which of the 16 analog BIT channels of the ASU is se-
lected by the analog multiplexer D8. The ADVOR output signal is supplied via the PMC−D (ASU−in-
terface) and distributed to the MSP−CD (1 and 2) for measured value acquisition. The MSP−CD of
the active transmitter (i.e. that switched to the antenna) evaluates these BIT signals. The selection
pattern for the 16 BIT channels of the antenna switching unit is laid down in the software; measure-
ments are performed cyclically.
The principle of double sideband switching used involves simultaneous radiation of the upper and
lower sidebands by diametrically opposite sideband antennas. In addition, the individual sideband
This sequence is controlled and initiated by the antenna counter. The antenna counter counts cycli-
cally from 0 to 23, and is reset automatically to 0 when a count of 24 is reached. The control signal
for the counter is the 720 Hz clock and the 30 Hz synchronization signal. The 30 Hz sync. signal is
derived from the 30 Hz clock of the MSG functional group; it is used to synchronize the 30 Hz antenna
rotation with the 30 Hz amplitude modulation of the carrier signal. A unique phase relation is thus de-
fined between the 30 Hz AM and the 30 Hz FM. The availability of the 720 Hz signal and the 30 Hz
sync. signal is indicated by LED H2 and H1 in front of the BSG−D.
To set the antenna counter (D18, D19) further control bus signals are used. The antenna counter deliv-
ers two control signal outputs, one for the even numbered and one for the odd numbered SB anten-
nas. It drives the SB antennas via bus driver and line drivers which include overvoltage protection.
A provision ( PLD D20) is made for possibly needed corrections (e.g. time delay for USB or LSB select
signals) if the zero point of the modulation deviates from the switching moment caused by delays.
The 30 Hz output signal of the antenna counter (30HZE, 30HZO) is used for control of the 2P2T
switches on the MOD−SBB.
Various control modes of the 48 sideband antennas are available to the user. They can be selected
by entering the appropriate software commands. All measurements necessary during the startup
phase and for repairs and maintenance are supported.
48 V dc
CS 720 Hz 30 Hz
address counter antenna counter
Blending signal and
generation control control logic
D17 D19,20
E
F
720 Hz
Blending function selection additional
address
Reference EPROM decoder
voltage signal shape Decoder D18
10 V (sin/cos) D1
8 Bit
CS CS CS CS analog BIT
selection
c0...3 control signal control signal
Latch Latch Latch Latch even antennas odd antennas
2,4,...,48 1,3,...,47
A B C D
D D D D Analog.
A A A A Mux. driver driver
N8 N7 N6 N5 D8 D7 D6
Blending signal Blending signal
amplitude control amplitude control
USB SIN USB COS LSB SIN LSB COS analog BIT signals BIT antenna switch 30HZE 30HZO
to MOD−SBB/1 to MOD−SBB/2 (ASU intern) signal control to MOD−SBB
to PMC−D/TX to PDSU
DC Converter J28
GND
48 V N1
+5V
N2 −15 V
48 RF
Control Control
to SB antennas
OUT2 OUT4 OUT24
from D1 P1 P2 P1 P2 P1 P2
MOD−SBB A
RF IN (EVLO) 12x
50 ohm termination
inactive(H)/active (L) H/L H/L H/L
J28
GND
from H/L J3
J27 Vcc
BSG−D 5V Decoder
Control U16,17
Decoder
D0...3 4 U18
ASU−CIF
DC supply
48 V +5/−15 V
DC on
Control
H/L H/L H/L
NOTE: J27, J28 must not be set 12
at the same time! Driver Driver Driver
D1
from D1
MOD−SBB A
12x P1 P2 P1 P2 P1 P2
RF IN (EVHI)
to SB antennas
OUT1 OUT3 OUT23
from H/L
MOD−SBB RF
RF IN (ODLO)
Vcc J3
Decoder
U16,17
Decoder
D0...3 4 U18
DC supply
+5/−15 V
from
MOD−SBB RF
RF IN (ODHI)
OUT25 OUT29 OUT47
ASU−C b to SB antennas
CHAPTER 3
TECHNICAL DESCRIPTION ANTENNA SYSTEM
3.1 GENERAL
See Fig. 2−1, 3−1.
The DVOR antenna system comprises the following system components:
− Antenna counterpoise with supports and framework, framework decking and antenna circle
(circle used during assembly for securing the sideband antennas)
− 48 sideband antennas
− 1 carrier antenna
− Cabling
− Monitor dipole
The electronic simulation of the antenna movement is described in Section 1.2.2.2.2 . In order for the
procedure to be implemented, antennas which are installed close together must be activated and fed
consecutively. This gives rise to the following problems concerning the antennas:
− Parasitic radiation coupled in from neighbouring antennas causes the radiation pattern to change
and results in spurious spectral components in the DVOR signals.
The individual radiators of the sideband antenna take the form of horizontally polarized omnidirec-
tional radiators (Alford loop antenna). The antenna elements of each individual radiator comprise 4
sheet metal strips which form a square frame (loop antenna), and which are embedded in a polysty-
rene frame (Fig. 3−11). The polystyrene frame forms the lower section of the antenna dome. It en-
ables the antenna elements to keep their shape, which ensures optimum electrical matching in the
entire sideband antenna.
Adjustable capacitors are provided at 2 of the diagonally opposite ends of the loop (supply points)
(Fig. 3−11). They are used to set the resonance of the loop in the 108 ... 118 MHz frequency range.
This resonance setting ensures a uniform current distribution (Fig. 3−2), and thus a perfect omnidi-
rectional pattern. The spacing of the capacitor plates (Fig. 3−2) as a function of the desired operating
frequency is shown in Fig. 3−3.
The RF is supplied symmetrically via crossed supply lines at the ends of the 4 loop sections. The re-
sulting alternating polarity ensures a uniform direction of current flow all round (Fig. 3−2). Each of
the 4 outer faces of the loop is approx. 550 mm (0.2 ) long. The optional Matcher or Decoupling Mo-
dule output (3−10/5) is connected to the balance−to−unbalance and matching transformer (see
Section 3.3.1.1).
ËËËËËËËËËË
ËËËËËËËËËË
ËËËËËËËËËË
+
ÊÊÊ
ÊÊÊ ÊÊÊÊ
ÊÊÊÊ Adjustable capacitor
ÊÊÊ ÊÊÊÊ
CA
ÊÊÊ ÊÊÊÊ
ÊÊÊ
ÊÊÊ ÊÊÊÊ
ÊÊÊÊ
Supply point
Current distribution
ÊÊÊ ÊÊÊÊ
−
−
ÊÊÊ
ÊÊÊ ÊÊÊÊ
ÊÊÊÊ
ÊÊÊ ÊÊÊÊ
ËËËËËËËËËËË
ËËËËËËËËËËË
ËËËËËËËËËËË
Spacing a
+
ËËËËËËËËËËË
Fig. 3−2 Current distribution and setting of the capacitors
13
12
11
CA
10
Frame
9
0
108 109 110 111 112 113 114 115 116 117 118 119 MHz
Fig. 3−3 Spacing of the capacitor plates as a function of the operating frequency
optional assemblies:
Antenna A3
Matcher
A48 A1 A2 A3 A4 A5 A6
from ASU
*** *** Antenna A3
*** ***
Decoupling
Module
optional
The balance−to−unbalance and matching transformer (Fig. 3−5/Z) is a component of the lower sec-
tion of the antenna dome (3−10/1); it comprises a pipe containing 2 inversely connected coaxial
cables (Z= 50 ohms). The result is automatically a balanced condition (see Fig. 3−5). If the cables
in this layout are twice terminated with Z, the transformer will be wideband and independent of the
length within limits (/8). The loop resistance provided is transformed to the desired input resistance
Z=50 ohms by selecting suitable lengths for the two cables. The glass−tube trimmer (3−5/CTr) at
the cable input of the transformer permits additional parallel transformation.
It is possible to set the optimum matching for each frequency of 108 ... 118 MHz by adjusting the spa-
cing of the capacitor plates (3−5/CA) and by adjusting the glass−tube trimmer CTr. In order to fulfill
the requirement for an active return loss of 26 dB, it should normally be sufficient to set CA as shown
in Fig. 3−3 and CTr as shown in Fig. 3−6. The short coaxial cable with a fixed length (approx. 90°),
which is located ahead of the balance−to−unbalance and matching transformer, is fed to the optional
Decoupling Module, which is accessible via the installation hole in the vertical pipe (Fig. 3−10/6).
The radiation pattern of the loop antenna is circular with a maximum deviation of ±0.5 dB. The vertical
pattern is shown in Fig. 3−7.
Loop resistance RA
Input resistance RA for CA 5 mm Ctr 0 turn
Input resistance RA for CA 5 mm Ctr 0 turn
Input resistance RA for CA 5 mm Ctr 0 turn
CA
RA
CA
Z CTr Z
26
24
22
20
18
16
14
12
10
CTr
8
matching transformer
108 109 110 111 112 113 114 115 116 117 118 119 MHz
L4 L4
L2
C3 C3
C2 L1 W1 C2 L1 W1
X1 X2 X1 X2
C1 C4 C1 C4
C5 L3 C5
L5 L5
R2 R2
X4
Matcher (Ref.No. 83134 00103) Decoupling Module (Ref.No. 83134 00101), optional
16
14
12
10
8
C5
6 Matcher/Decoupling Module
108 109 110 111 112 113 114 115 116 117 118 119 MHz
3
4
2 5
10 10
1 6
7
8
9
Twist drill
Framework Antenna ring Mounting device for carrier antenna Entry and ladder
Supports Braces Mounting area for the PDSU housing below counterpoise near the entry
Sideband antennas
on antenna circle
Carrier antenna (centre)
Fig. 3−13 Framework decking and antenna circle with carrier antenna and sideband antennas
Dipole
Mast
CHAPTER 4
EMERGENCY POWER SUPPLY
4.1 GENERAL
For use in Navaids 400, a set of lead batteries, comprising four bloc batteries, is connected in parallel
to the DC voltage supply from the mains unit BCPS. In case of a mains failure or disconnection of the
primary voltage for maintenance purposes, it is used to supply the Thales navigation installation. Bat-
teries, which are maintained at a permanent cell voltage of 2.25 V (standby parallel operation) by the
BCPS, are supplied by Thales as standard for NAV−installations (Navaids 400). Battery sets are avail-
able as lead acid batteries (type Vb...) or maintenance free lead batteries (type 12 VE...) using an elec-
trolyte which is fixed as a gel. The recommended battery type has a capacity tailored to the require-
ments of the Thales navigation installation. In such case should be noted, that the 54 V trickle charge
voltage supplied by the BCPS is a fixed output and can not be changed therefore.
NOTE: Alkaline batteries, e.g. Nickel Cadmium batteries, require a different charging method,
and cannot therefore be used in conjunction with the power supply BCPS
(module ACC 54, Ref. No. 58341 20100).
Batteries supplied by the customer have to correspond to the specification of recommended battery
sets. The following battery types are recommended for DVOR−installations:
System Mode Current at 48 V Capacity Type * No. of Thales Ref. No.
batt. operation bloc batteries for battery set
DVOR 50 W cold stdby ca. 11.25 A 54 Ah Vb 12144 4x 12 V bloc 83131 72242
56 Ah 12 VE 60 4x 12 V bloc 83131 72252
DVOR 50 W + cold stdby ca. 15 A 72 Ah Vb 12146 4x 12 V bloc 83131 72243
DME435 68 Ah 12 VE 75 4x 12 V bloc 83131 72253
DVOR 100 W cold stdby ca. 15.83 A 72 Ah Vb 12146 4x 12 V bloc 83131 72243
79 Ah 12 VE 90 4x 12 V bloc 83131 72254
DVOR 100 W + cold stdby ca. 19.58 A 72 Ah Vb 12146 4x 12 V bloc 83131 72243
DME435 102 Ah 6 VE 110 8x 6 V bloc 83131 72255
* Vb = lead acid batterie; 12 VE xx= maintenance free battery
CAUTION
Before the battery is connected the power supply unit BCPS must be connected to the
mains, and the output voltage must have reached its rated value; the reaching of this level
is displayed by lighting LED’s at the front panels of the AC/DC−converter in the cabinet.
The battery set is connected via two PVC−insulated cables as per DIN 57281, 16 mm2 (red and black
or blue). The length of this connection is restricted to a maximum of 10 m for electrical reasons. The
red cable should be connected to the positive terminal of the battery set (+), and the black cable to
the minus terminal (−). It should be connected to the transmitter rack corresponding the polarity at
the "B+" and "B−" terminals. The cables of "B+" and "B−" are fed via the fuse switch F20 (50 A) in
the fuse box to protect the batteries.
For monitoring purposes, the battery is connected via a measuring cable (5x 1.5 mm2) to the BCPS
(terminals 2, 1, F, F, 0). This cable is connected on one hand to the terminals BAT0, BAT1 and BAT2
in the battery fuse box, and connects on the other hand the auxiliary contact (BFUSE) at the fuse
switch F20 to terminals F, F. The measuring cables BAT0, BAT1, BAT2 are protected by the fuse switch
F21 (0.2 A).
The terminal signs for battery monitoring mean:
BAT0 (0) 0 V or −
BAT1 (1) 24 V (half battery voltage; not used in ILS 420)
BAT2 (2) 48 V or +
The test procedure for the battery measurement is described in the Technical Manual, Part 2, chapter
6, Maintenance (ILS), or chapter 5, Maintenance (CVOR/DVOR). The discharge times of the recom-
mended batteries related to the NAV−systems concerned are listed in the table in section 4.1.
CAUTION
Maintenance−free batteries have to be set into operation within a half year after delivery
to prevent drawback in lifetime of battery.
CHAPTER 5
REMOTE MAINTENANCE AND MONITORING CONFIGURATION
(RMMC)
5.1 APPLICATION AND DESIGN
The Remote Maintenance and Monitoring Configuration (RMMC) is used for remote monitoring, oper-
ation and maintenance of all the connected navigation systems. The network has a radially configured
architecture based on communication between the system components via switched or private lines
in the public network and dedicated lines in private networks.
The remote control system components allow all the networked navigation systems to be operated
optionally from central points, from normal operation of the dual systems with automatic changeover
in the event of a fault through manual operation to measurement and setting of all the possible signal
parameters, as well as detailed fault analyses on the basis of a wide range of measured values. They
facilitate new maintenance strategies, whereby importance is placed firstly on concentrating logistics
and qualified personnel, and secondly on responding to specific failures with systematic mainte-
nance activities rather than relying on periodic precautionary measures. This considerably improves
both maintenance efficiency and the economic efficiency of the systems throughout their service life.
Although these advantages only apply to the modern generation of air traffic control systems devel-
oped by Thales ATM, with the navigational aids, namely the enroute navigational systems CVOR and
DVOR, the approach and landing systems ILS and MLS, the ILS farfield monitor (FFM) for Localiser,
the TACAN 453 and the electronic TACAN antenna (ELTA 200), the DME 415/435, and the NDB 436
radio beacons, the extensive range of interface boards makes it possible to incorporate other collo-
cated systems in the remote control and monitoring strategy if desired.
RMC 443
Remote Maintenance Center
ÊÊÊ
RCSE 443
ÊÊÊ
INC
REU
PSTN
RCMS 443
Remote Control and Monitoring System
Ê
ÊÊÊ
RCSE 443
ÊÊÊ
Ê
INC
REU
RCMS 443
At the top, the Remote Maintenance Center (RMC−C) is used as central point to obtain an overview
of the status of all available systems. The RMC−C is connected via dialing modems to the public PTT
network to obtain serial data from the RMC−R, LCU 443 or RCMS 443.
At the RMC−R the main status of all en−route equipment (CVOR, DME−Transponder and TACAN−
ground stations) of one defined region are displayed continuously at the indication and control panel
(INC) of the RMC and at installed optional Remote Status Units (RSU) to the controller for en−route.
Besides en−route subsystems, the main status of the Landing Systems ILS and MLS are also dis-
played for maintenance purposes. The RMC−R is also connected to the PTT network via autodialing
modems. For special applications a fixed line interface may be provided. For maintenance activities
at the screen of the Personal Computer maintenance data are displayed. The maintenance technician
obtains all the data from the subsystems configured for this region with defined menus on the screen
of the data terminal (PC). It is possible to use the ADRACS software (Automatic Data Recording And
Control System) for maintenance purposes to control Navaids 400 family or System 4000 equipment
at the remote site. For MLS the MLS−menu technique is employed as well as respective ELTA−,
DME−, or TACAN−PC supervisory programs.
The RCMS 443 and the NAV LCU 443 are link control units and provide central points for communica-
tion between RMC’s and the navaids systems. While the RCMS is connected via twisted telephone
line pairs and modems to the ILS/MLS−equipment the NAV LCU 443 has direct RS−232/422 inter-
faces to the CVOR, DVOR, TACAN and ELTA−equipment, and DME. For small projects, it is possible
to connect the NAV LCU of en−route navigation systems via switched lines to an RCMS.
PTT
network
TAC ELTA
AZ EL DME/P
Std. bus modem 1200, 2400, 4800, 9600 DME 415, 435, TAC 453
The maintenance, fault analysis and documentation functions of the RMMC are implemented by con-
necting a PC system to the RCSE and installing the RMS or RCMS application software on it. The
difference in the names is a reflection of the definitions laid down by the U.S. FAA. An RMS designed
for maintenance purposes has direct, permanent access to the navigation systems via separate cable
connections, and is operated independently of the Remote Control and Status Equipment (RCSE),
while an RCMS uses the same communication paths for the maintenance functions as it does for re-
mote control and monitoring. The following functions are provided:
The local communication unit (LCU) comprises a remote control electronic unit (REU), which is
equipped according to the specific requirements of the NAV station. It serves as a communication
interface between the connected equipment and the public switched network, and as a common
point for connecting a service terminal (Laptop PC) for commissioning and maintenance purposes.
NOTE: In AN 400 en−route navigation systems (e.g. CVOR 431) no separate LCU device has
to be used as local communication interface. The LCU functionality is integrated in the
NAV 400 subrack, i.e. the LCU software is running on the already existing LCP board,
additional modems are used for communication purposes.
If a maintenance center is installed, it is possible to connect several different remote control systems
to a central REU via switched lines. The general status of all the remote control systems in the network
is indicated permanently on one or more INC panels. Any change in a status causes a connection
to be set up automatically from the LCU or the RCSE to the responsible center and all the current
status information to be transmitted. The center can also be set up to poll the regional stations periodi-
cally.
The center is fully equipped to exchange such data with the networked systems which is necessary
for it to be able to perform a detailed fault diagnosis. It communicates either directly with en−route
navigation systems via switched connections or with ILS substations via the Remote Control and Sta-
tus Equipment (RCSE) at each airfield.
RCMS
RCSE
ADDITIONAL
MODEM
PANELS
CTU RWY
Ê
ÊÊÊ
SELECT
REU
INC
LCU
FFM ELTA
Marker
VOR DME
DVOR TACAN
LOC GS DME
SYSTEM 2 (S 4000)
FFM ELTA
Marker
DME
CVOR TACAN
Fig. 5−3 Example Configuration: RCMS 443 for two ILS and VOR/DME/TACAN
Annex
Ed. 07.04 48 SB A
DVOR 432 Annex Nextfield
General Equipment Description
A to B 07.04
AN−1 to 16 07.04
Trademarks Microsoft and MS−DOS are registered trademarks, WINDOWS is a trademark of the Microsoft Corporation. IBM is a registered trademark of the
International Business Corporation. Pentium is a registered trademark of the Intel Corporation.
B 48 SB Ed. 07.04
Annex Nextfield DVOR 432
Equipment Description Introduction
CHAPTER 1
DVOR NEXTFIELD MONITORING, INTRODUCTION
1.1 GENERAL
This annex describes the principal function and the subassemblies of the option "Nextfield Monito-
ring", which are different to that of the standard description part of the DVOR monitoring using the
remote nearfield dipole. The following changed or new subassemblies are essentially used for the
option Nextfield Monitoring:
− Monitor dipole (max. 4) near counterpoise edge Ref.No. 58317 24017 and 88131 72411
− Monitor Signal Processor (MSP−CD) Ref.No. 83135 22301
− Monitor Divider Switch (MDS−D) Ref.No. 83134 20501
− RF−Duplexer, 2nd coupling out (RFD1−C) Ref.No. 58341 00840
− 2nd coupling out (RFD2−SB) Ref.No. 58341 00830
The signals picked up with 1 or max. 4 monitor dipoles located at the counterpoise edge are suitable
processed, and following fed to the inputs of the multiplexer on the MSP−CD.
circle of 48 SB antennas
Fig. 1−1 Arrangement of nearfield and nextfield monitor dipoles of the DVOR−antenna
HF−bandpass
filter Precision ID−discriminator
controlled amplifier demodulator
Peak
1020 Hz filter detector Processor 80C186
4 BIT−signals
III incl.
memory/peripherals/
Measurement signal
0 150 Hz low pass control circuitry
Testgenerator Sample
filter 0 &
signal Hold
1 60 Hz
low pass 12 bit A/D−
ASU DIF 10 kHz high pass Peak I Converter
to measure USB/LSB 2 detector filter
level filter 2
ASU SSB
to measure LSB level 3 II
FM−
10 kHz filter demodulator
1
ATE5
3
USB+LSB
CSB Mon.Meas.In
Norm.Out (A)
USB MSP−CD/1
LSB 9960 Hz AM
30 Hz FM−Level
30 Hz FM (ATE5)
R F R F R F
MDS−D
to MOD−SBB to MOD−SBB
Mon.Meas.In
from RFD: CSB USB LSB Norm.Out (A)
MSP−CD/2
Nextfield dipole 1 9960 Hz AM
Nextfield dipole 2 30 Hz FM−Level
Nextfield dipole 3* 30 Hz FM (ATE5)
Nextfield dipole 4*
alt. nearfield dipole * optional
Fig. 1−3 Extensions for the nextfield monitor signal, block schematic
The signal of the nextfield dipole has to be processed in a special way, before the signals 30 Hz FM
and the 9960 Hz modulation depth can be evaluated. An RF switch assembled with 3 inputs in mini-
mum is connected in series to the input of the MSP−CD in order to select the necessary RF−signals.
The levels of these RF−signals are matched by the processor controlled attenuator on the following
MSP. The 3 RF−signals are: Nearfield dipoles, USB+LSB, and CSB internal. An output line with 3 dB
coupler for the level normalized sensor signal A is added to the MSP−CD standard version. The signal
for the DFT1 evaluation (envelope of the 9960 Hz signal) is extracted from the sideband signals re-
ceived from the middle antenna :
[ USB ] + [LSB ] − [ signal of return port in the carrier line ]
Mixing this signal with the carrier frequency (limited CSB), the carrier with upper and lower sideband
is achieved. This 9960 Hz signal of mixer 1 (M1) is supplied to multiplexer 1 and evaluated well known
as standard. Attention is paid to the fact that the carrier signal has the correct RF−phase relationship
to the vector sum of the signals USB+LSB. It is adjusted with a phase shifter on the MDS−D using
a potentiometer each. Besides the sideband signal USB+LSB, also the carrier signal reflected by the
middle antenna is derived as interference signal from the directional coupler in the carrier branch. This
interference signal is in minimum 20 dB greater than the wanted signal USB+LSB. The middle an-
tenna therefore has carefully to be matched >20 dB (better 26 dB). The signals for evaluations of
DFT2a/b (30 Hz FM of USB and LSB) are derived from mixer 2 (M2).
The indication of alarms remains unchanged. This is, that the results of the monitoring for azimuth
and RF−level are linked in an OR−function for more than one nextfield dipole. The results of the evalu-
ation of 30 Hz FM for LSB and USB are not edited individually, but an addition of both 30 Hz FM vectors
is performed with the result of a sum of 30 Hz FM for the indication of the measurement value for the
30 Hz FM deviation and also for azimuth calculation.
The calculation of the 30 Hz AM is performed with the dc component of the same DFT−evaluation,
not related to the RF−level of a nextfield dipole.
The calculation of the 9960 Hz AM is performed with the 9960 Hz sidebands received from the middle
antenna which are related to the dc−component of the CSB forward signal. The measurement value
outputs are:
Individual inputs for upper and lower limits are to be performed for the new azimuth measurement
values. The measurement values for the RF−level of the four dipoles are equal to a large extent. They
all use the same AGC−adjusting value. On this premise the RF−level have the identical alarm limits
(UL/LL).
Mixed operation with field and nextfield dipole evaluation is not provided in multiplex mode. For near-
field or nextfield evaluation a new command is available (either/or, only alternatively selectable). The
number of nextfield dipoles is selectable. In this way the four inputs of the MDS−CD can be used for
up to 4 nextfield dipoles or for 3 nextfield dipoles and 1 field dipole. The monitor, LRCI and ADRACS
software are extended with the previous mentioned parameter and commands. At time both process
max. 2 nextfield dipoles or one field dipole.
CHAPTER 2
TECHNICAL DESCRIPTION NEXTFIELD
2.1 GENERAL
2.1.1 System Overview
See Fig. 2−1.
The DVOR installation including Nextfield Monitoring comprises additional components and supplies
for the antenna system. The monitoring system (consisting of 1 or to monitors) is supplied with exter-
nal signals, which are obtained via 1 or optionally 2 separately mounted nearfield dipoles or/and 1
or up to 4 nextfield dipoles at the edge of the counterpoise. If the nextfield dipoles are used, the signals
are supplied via suitable cables to the connectors on top of the DVOR−transmitter rack.
8 A24 8
A48 ** **
A16
** A1 A13
A47 **
A2 A12 A15
** A3 A4 A10 A11
A5 A6 A7 A8 A9
**
** ** ** ** ** ** **
** ** **
** ** **
1...48 A15...A47
49 1
4
Control 2
4
* optional
** Coupling cables between antennas 1...50 and the correspondent decoupling module SB1/2 DVOR−Shelter
are optionally available; the standard version uses a matcher module without coupling cables
Carrier
Tower
5
6
7
Compared with the standard version of the DVOR 432 with nearfield dipole the three additional out-
puts of the existing directional couplers located on the RFD1−C or RFD2−SB are used. The termina-
tion of the return path of coupler Z8 (CSB) is removed, because the outout is also used for the nextfield
feature. These four outputs are passed to the MDS−D. Furthermore there are 4 RF supply lines from
the connector board on top of the cabinet to the MDS−D, and 2 RF lines each between MDS−D and
both MSP. Also there are changes in use of the MSP−CD (additional 3 dB couplers and signal connec-
tions for ATE2/3) and changes of backpanel BP−CD (2 x 4 additional connection lines).
The wall entrance in the shelter contains 3 further connections for the monitor cables, has 4 monitor
connections altogether.
Ê Í ËË Ê Ê Ê
Ê Í ËË Ê Ê Ê
Ê Í ËË Ê Ê Ê
USB
LSB
Circulators
Modem*
Modem*
Modem*
BP−C
ASU control
Ê Í ËË Ê Ê Ê
VAM*
LCP USB
RFD Components:
Ê Í Ê Ê Ê
MDS−D
PMC−D
CSB
MSP−1
MSP−2
DCC−3−05
CSL
RF−filter/Relays
Ê Í Ê Ê Ê
LSB
LSB
USB
Ê
Ê Í Ê
Ê Ê
Ê Ê
Ê
Ê Ê Ê Ê
cooling baffle
Ê Ê Ê Ê
Ê Ê Ê Ê
MOD−110P***
Ê Ê Transmitter 1 ÊËËËËËËËËËËËÊ
MOD−110 or
BP−T /TX1
MOD−110
MOD−110
DCC−MV
MSG−C
MSG−S
Ê Ê Ê Ê
ËËËËËËËËËËË
SYN
CCP
Ê Ê Ê Ê
ËËËËËËËËËËË
Ê Ê Ê Ê
ËËËËËËËËËËË
Ê Ê Ê Ê
ËËËËËËËËËËË
CA−100/1
Transmitter 2**
Ê Ê Ê Ê
ËËËËËËËËËËË
MOD−110** or
MOD−110P***
MOD−110**
MOD−110**
DCC−MV**
Ê Ê Ê Ê
MSG−C**
MSG−S**
SYN**
CCP**
Ê Ê Ê Ê
BP−T /TX2**
Ê Ê Ê Ê
Ê
Ê Ê Ê Ê
ËËË Ê
ËË Ê Ê
PMM PMM
Ê ËËË Ê
ËËËËË Ê
ÊËËËËËËËËËËËÊ
DC/DC conv. 100 W
BP−DC
Ê Ê
ËË Ê
ËËËËËËËËËËË
MOD−SBB
MOD−SBB
Ê ËËË Ê
ËË Ê Ê
ËËËËËËËËËËË
DCC−28**
BSG−D
ASU control
DCC−28
Ê Ê
ËËËËË Ê Ê
ËËËËËËËËËËË CA−100/2**
Ê
Ê Ê
ËËËËË
Ê Ê
Ê Ê
ËËËËËËËËËËË
Ê
Ê Ê Ê Ê
AC/DC converter
Ê Ê Ê Ê
Battery and power supply connection
ACC**
Ê Ê Ê Ê
ACC
ACC
−−
Ê
Ê Ê
Ê Ê
Ê Ê
Ê
BP−BCPS
Subracks:
ËËË
NOTE:
Version 100 W
ÍÍ Nextfield option
The diagram shows the locations of the plug−in and screw−on subassemblies (printed circuit boards). The mo-
* optional ** not used in single version
Fig. 2−2 Locations in the DVOR transmitter rack in the 50 W and up to 100 W versions
TYPE OF INSTALLATION: DVOR 50W, 100 W; Dual version TYPE OF INSTALLATION: DVOR 50W, 100 W; Single version
SUBRACK Subassemblies used SUBRACK Subassemblies used
View from left to right Cabinet, preassembled assign. to Cabinet, preassembled
Front door LCP LCP
Cabinet on top Connector panel Connector panel
Cabinet, rear, left, top 1x coupler; CSB 1x coupler; 1x RF−Filter CSB
RFD1−D: load, 1x relay, −
1x RF−Filter
Cabinet, rear, right, top 2x coupler, 2x circulator; SB1/SB2 2x coupler; 2x circulator; SB1/SB2
RFD2−D: 2x relay; load, 2x RF−Filter
2x RF−Filter
Monitor&Control, left CSL CSL
MSP−CD Mon1 MSP−CD Mon1
MSP−CD Mon2 − −
MDS−D Nextfield − −
PMC−D ASU PMC−D ASU
− − −
Monitor&Control, upper VAM*/** (100 W) VAM*/** (100 W)
right − −
Modem* LGM1 Modem* LGM1
Modem* LGM2 Modem* LGM2
Modem* LGM3 Modem* LGM3
Monitor&Control, lower DCC−3−05 LCP DCC−3−05 LCP
right Mon1 Mon1
Mon2 −
Transmitter 1 MOD−110 SB1 MOD−110 SB1
MOD−110 SB2 MOD−110 SB2
SYN−D SYN−V
MSG−S MSG−S
MSG−C MSG−C
CCP−D CCP−V
MOD−110**/110P*** CSB MOD−110**/110P*** CSB
DCC−MV TX1 DCC−MV TX1
Cabinet, rear side CA−100** TX1 CA−100** TX1
Transmitter 2 MOD−110 SB1 not assembled
MOD−110 SB2
SYN−D
MSG−S
MSG−C
CCP−D
MOD−110**/110P*** CSB
DCC−MV TX2
Power Management PMM PMM
Cabinet, rear side CA−100** TX2 not assembled −
DC/DC−Converter MOD−SBB ASU MOD−SBB ASU
MOD−SBB ASU MOD−SBB ASU
BSG−D ASU BSG−D ASU
DCC−28** TX2 − −
DCC−28** TX1 DCC−28** TX1
AC/DC−Converter − −
ACC −
ACC ACC
ACC ACC
Cabinet rear, bottom Battery and power supply Battery and power supply
connection, mains filter connection, mains filter
*) The code numbers given may differ to those of the delivered installation in individual cases. In such case the actual code
number can be taken from the delivery list of the installation or the drawing set.
Fig. 2−4 Subassemblies for nextfield monitoring
from Transmitter 2 Nextfield monitor 1...4 or
1...3 and field dipole ASU subassemblies PDSU
CSB
SB2
SB1
Carrier antenna 49
Control
30HZO 30HZE
MDS−D
Control/BIT
Monitor Divider Switch TX1 PMC−D BSG−D
ASU interface t/f ASU int.
Control line
+15V
Norm. Signal A
DCC05/15
Norm. Signal A
Antenna switch
control and 30HZ sync. −15V control
BIT
signals BIT signals
MSP−CD MSP−CD
Monitor Signal Processor Monitor Signal Processor
CSL
(TEG)
V.24 / RS232 V.24 / RS232 Transmitter 2 and Monitor 2
Fig. 2−5 DVOR, nextfield supplement (excerpt from part 1, Fig. 1−30)
MOD−SBB MOD−SBB
20 dB
26 dB 20 dB Z4
Z8 Z3
1 1
Circulator Circulator
PMC−D USB 2 LSB 2
Z6 3 Z5 3
TX1 Control TX2
CSB RFD1−C SB1 RFD2−SB SB2
Harmonic filter Harmonic filter Harmonic filter
CSB via MDS−D USB LSB
Z7 to MSP−CD Z1 Z2
50 Ohm/100 W/30 dB
50 Ohm/100 W/30 dB
50 Ohm/100 W
Side wall, left, rear view changeover signals Side wall, right, rear view
to MSP−VD/x
9960 Hz AM FAUREC2
5 N18 N22 0 MAINAL1
6,7 N6 SEL Morse−indicator TEGAL1*
DC−keyed, conform to OUT FIRAL1
Morse code 16 Bit SECAL1*
ATIS Register NFIAL1*
Output DC+30 Hz AM TESTAL1*
voice X12 MON_EXIXST1
TX1 ON
600 Ohm N7 30 Hz TX1 OFF
3.5 mm jack bush TP10
to CSL
TX2 ON
for 30 Hz FM TX2 OFF
DC Offset+30 Hz FM measurements only TX1 AERIAL
TX2 AERIAL
CS POWER OFF
D17,18
POWER ON
from MSP−VD/x
2 MAINAL2
Limiter 9960 Hz 30 Hz FM X28 5 kHz 0 TEGAL2*
FIRAL2
V46 N19,20 V17..21,N23 N26 SECAL2*
3 NFIAL2*
from MDS−D TESTAL2*
30 Hz FM USB/LSB IN !MOFAU2
0 SEL 16 Bit !MOFAU1
DC + Interference 1 OUT Register RFR1/1
Analog RFR1/2
from CSL
N30 BTX3/T1
BTX1/T2
4
960 Hz
BTX2/T2
Fig. 2−7 Monitor Signal Processor (MSP−CD), excerpt from block diagram
NF−Dipol1 N37
N61 Decoder
N8 N10 Control
3 dB −U D1 from
−U MSP−CD/1
NF−Dipol2 N36
N60 N31
3 dB
N28
NF−Dipol3 N35
N59 N30
3 dB
N34 N12
NF−Dipol4 −U
N58
channel select
3 dB
N51 Decoder
N16 control
−U D2 from
N19
3 dB −U MSP−CD/2
N45
N50
N42
3 dB
N44
N49
M2RF from
U5
MSP−CD/2 3 dB
RF IF MDSD_9960_HZ_AM_M2
N77,78
4 dB N66
Lo
N48 N18
−U MDSD_9960_HZ_RF_M2
U6
M1RF from RF IF
N75,76
MSP−CD/1 Lo
4 dB N64 U3
control
RF IF N67,68 MDSD_9960_HZ_AM_M1
Limiter Lo
M1CSB U1
U2 MDSD_9960_HZ_RF_M1
N56 channel select RF IF N69,70
Lo
16 dB
6 dB Control
UPHM1 Uref
CSB N32 +15V
N55 Limiter N25
forward
U4
N11 N9 f Uref. 10V
M2CSB 14 dB −U V100,101
−U R409
N65 N33
N29 to
10 dB MSP−cd/1
Z1 RF−MON1
USB_LSB N27
N38 19,92 kHz
CSB N57 BPINM1M2 N1,2 Uref 10V
return 10 dB N72
BPISELM1
19,92 kHz FM detector
6 dB V34,35
N14 N40 N71 V43,44 N3
N39 −U N13 BP2SELM1
LSB N62
forward MDSD_30_HZ_FM_M1
channel select
6 dB
16dB
USB N63 UPHM2 Uref
+15V
forward N26
N46
N17 N15 f
14 dB Uref. 10V
−U V102,103
−U R414
N47 to
N43 MSP−CD/2
10 dB RF−MON2
Z2
N41
19,92 kHz
N54 BPINM1M2 N4,5 Uref 10V
N73
BPISELM2
10 dB 19,92 kHz FM detector
V39,40
BP2SELM2
N74 V45,46 N6
N52 N20
Signal path for MSP−D/2 N53 MDSD_30_HZ_FM_M2
The phase of signals RF−MON1, RF−MON2 is adjusted non−recurrently with R409 and R414 during
first alignment.