CLEVO W76xSUA - 6-71-M74S0-D06A PDF

Preface
Notebook Computer
W760SUA
Service Manual
Preface
I
Preface
Notice
The company reserves the right to revise this publication or to change its contents without notice. Information contained
herein is for reference only and does not constitute a commitment on the part of the manufacturer or any subsequent ven-
dor. They assume no responsibility or liability for any errors or inaccuracies that may appear in this publication nor are
they in anyway responsible for any loss or damage resulting from the use (or misuse) of this publication.
This publication and any accompanying software may not, in whole or in part, be reproduced, translated, transmitted or
reduced to any machine readable form without prior consent from the vendor, manufacturer or creators of this publica-
tion, except for copies kept by the user for backup purposes.
Brand and product names mentioned in this publication may or may not be copyrights and/or registered trademarks of
their respective companies. They are mentioned for identification purposes only and are not intended as an endorsement
of that product or its manufacturer.
Preface
Version 1.0
July 2009
Trademarks
Intel, Celeron and Intel Core are trademarks of Intel Corporation.
Windows® is a registered trademark of Microsoft Corporation.
Other brand and product names are trademarks and/or registered trademarks of their respective companies.
II
Preface
About this Manual

This manual is intended for service personnel who have completed sufficient training to undertake the maintenance and
inspection of personal computers.
It is organized to allow you to look up basic information for servicing and/or upgrading components of the W760SUA
series notebook PC.
The following information is included:
Chapter 1, Introduction, provides general information about the location of system elements and their specifications.
Chapter 2, Disassembly, provides step-by-step instructions for disassembling parts and subsystems and how to upgrade
elements of the system.
Appendix A, Part Lists
Preface
Appendix B, Schematic Diagrams
III
Preface
IMPORTANT SAFETY INSTRUCTIONS

Follow basic safety precautions, including those listed below, to reduce the risk of fire, electric shock and injury to per-
sons when using any electrical equipment:
1. Do not use this product near water, for example near a bath tub, wash bowl, kitchen sink or laundry tub, in a wet
basement or near a swimming pool.
2. Avoid using a telephone (other than a cordless type) during an electrical storm. There may be a remote risk of elec-
trical shock from lightning.
3. Do not use the telephone to report a gas leak in the vicinity of the leak.
4. Use only the power cord and batteries indicated in this manual. Do not dispose of batteries in a fire. They may
explode. Check with local codes for possible special disposal instructions.
5. This product is intended to be supplied by a Listed Power Unit with an AC Input of 100 - 240V, 50 - 60Hz, DC Output
of 19V, 4.74A (90 Watts) minimum AC/DC Adapter.
Preface
CAUTION
Always disconnect all telephone lines from the wall outlet before servicing or disassembling this equipment.
TO REDUCE THE RISK OF FIRE, USE ONLY NO. 26 AWG OR LARGER,

TELECOMMUNICATION LINE CORD
This Computer’s Optical Device is a Laser Class 1 Product
IV
Preface
Instructions for Care and Operation

The notebook computer is quite rugged, but it can be damaged. To prevent this, follow these suggestions:
1. Don’t drop it, or expose it to shock. If the computer falls, the case and the components could be damaged.
Do not expose the computer Do not place it on an unstable Do not place anything heavy
to any shock or vibration. surface. on the computer.
2. Keep it dry, and don’t overheat it. Keep the computer and power supply away from any kind of heating element. This
is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged.
Do not expose it to excessive Do not leave it in a place Don’t use or store the com- Do not place the computer on
Preface
heat or direct sunlight. where foreign matter or mois- puter in a humid environment. any surface which will block
ture may affect the system. the vents.
3. Follow the proper working procedures for the computer. Shut the computer down properly and don’t forget to save
your work. Remember to periodically save your data as data may be lost if the battery is depleted.
Do not turn off the power Do not turn off any peripheral Do not disassemble the com- Perform routine maintenance
until you properly shut down devices when the computer is puter by yourself. on your computer.
all programs. on.
V
Preface
4. Avoid interference. Keep the computer away from high capacity transformers, electric motors, and other strong mag-
netic fields. These can hinder proper performance and damage your data.
5. Take care when using peripheral devices.
Use only approved brands of Unplug the power cord before

peripherals. attaching peripheral devices.
Power Safety
Preface
The computer has specific power requirements:

• Only use a power adapter approved for use with this computer.
• Your AC adapter may be designed for international travel but it still requires a steady, uninterrupted power supply. If you are
 unsure of your local power specifications, consult your service representative or local power company.
Power Safety • The power adapter may have either a 2-prong or a 3-prong grounded plug. The third prong is an important safety feature; do
Warning not defeat its purpose. If you do not have access to a compatible outlet, have a qualified electrician install one.
Before you undertake • When you want to unplug the power cord, be sure to disconnect it by the plug head, not by its wire.
any upgrade proce- • Make sure the socket and any extension cord(s) you use can support the total current load of all the connected devices.
dures, make sure that • Before cleaning the computer, make sure it is disconnected from any external power supplies.
you have turned off the
power, and discon-
nected all peripherals Do not plug in the power Do not use the power cord if Do not place heavy objects
and cables (including cord if you are wet. it is broken. on the power cord.
telephone lines). It is
advisable to also re-
move your battery in
order to prevent acci-
dentally turning the
machine on.
VI
Preface
Battery Precautions
• Only use batteries designed for this computer. The wrong battery type may explode, leak or damage the computer.
• Do not continue to use a battery that has been dropped, or that appears damaged (e.g. bent or twisted) in any way. Even if the
computer continues to work with a damaged battery in place, it may cause circuit damage, which may possibly result in fire.
• Recharge the batteries using the notebook’s system. Incorrect recharging may make the battery explode.
• Do not try to repair a battery pack. Refer any battery pack repair or replacement to your service representative or qualified service
personnel.
• Keep children away from, and promptly dispose of a damaged battery. Always dispose of batteries carefully. Batteries may explode
or leak if exposed to fire, or improperly handled or discarded.
• Keep the battery away from metal appliances.
• Affix tape to the battery contacts before disposing of the battery.
• Do not touch the battery contacts with your hands or metal objects.
Battery Guidelines
The following can also apply to any backup batteries you may have.
Preface
• If you do not use the battery for an extended period, then remove the battery from the computer for storage.
• Before removing the battery for storage charge it to 60% - 70%.
• Check stored batteries at least every 3 months and charge them to 60% - 70%.

Battery Disposal
The product that you have purchased contains a rechargeable battery. The battery is recyclable. At the end of its useful life, under var-
ious state and local laws, it may be illegal to dispose of this battery into the municipal waste stream. Check with your local solid waste
officials for details in your area for recycling options or proper disposal.
Caution
Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by the manufacturer.
Discard used battery according to the manufacturer’s instructions.
Battery Level
Click the battery icon in the taskbar to see the current battery level and charge status. A battery that drops below a level of 10%
will not allow the computer to boot up. Make sure that any battery that drops below 10% is recharged within one week.
VII
Preface
Related Documents
You may also need to consult the following manual for additional information:
User’s Manual on CD
This describes the notebook PC’s features and the procedures for operating the computer and its ROM-based setup pro-
gram. It also describes the installation and operation of the utility programs provided with the notebook PC.
Preface
VIII
Preface
Contents
Introduction ..............................................1-1 Top with Fingerprint ...................................................................... A-3
Top without Fingerprint ................................................................. A-4
Overview .........................................................................................1-1 Bottom ........................................................................................... A-5
System Specifications .....................................................................1-2 LCD ............................................................................................... A-6
External Locator - Top View with LCD Panel Open ......................1-5 HDD ............................................................................................... A-7
External Locator - Front & Right side Views .................................1-6 DVD Super Multi .......................................................................... A-8
External Locator - Left Side & Rear View .....................................1-7
External Locator - Bottom View .....................................................1-8 Schematic Diagrams................................. B-1
Mainboard Overview - Top (Key Parts) .........................................1-9 System Block Diagram ...................................................................B-2
Mainboard Overview - Bottom (Key Parts) ..................................1-10 Penryn (Socket-P)1/2 ......................................................................B-3
Mainboard Overview - Top (Connectors) .....................................1-11 Penryn (Socket-P) 2/2 .....................................................................B-4
Mainboard Overview - Bottom (Connectors) ...............................1-12 SiS671DX - Host, PCIE 1/5 ...........................................................B-5
Disassembly ...............................................2-1 SiS671DX - DRAM 2/5 ..................................................................B-6
Preface
SiS671DX - MuTIOL 3/5 ...............................................................B-7
Overview .........................................................................................2-1 SiS671DX - PWR 4/5 .....................................................................B-8
Maintenance Tools ..........................................................................2-2 SiS671DX - GND 5/5 .....................................................................B-9
Connections .....................................................................................2-2 DDR2 SO-DIMM_1 .....................................................................B-10
Maintenance Precautions .................................................................2-3 DDR2 SO-DIMM_2 .....................................................................B-11
Disassembly Steps ...........................................................................2-4 SiS307ELV ...................................................................................B-12
Removing the Battery ......................................................................2-5 External VGA M92-S2-1 ..............................................................B-13
Removing the Hard Disk Drive .......................................................2-6 External VGA M92-S2-2 ..............................................................B-14
Removing the Optical (CD/DVD) Device ......................................2-8
External VGA M92-S2-3 ..............................................................B-15
Removing the System Memory (RAM) ..........................................2-9 External VGA M92-S2-4 ..............................................................B-16
Removing and Installing the Processor .........................................2-11
External VGA M92-S2-5 ..............................................................B-17
Removing the Wireless LAN Module ...........................................2-14 External VGA M92-S2-6 ..............................................................B-18
Removing the Bluetooth Module ..................................................2-15 External VGA M92-S2-7 ..............................................................B-19
Removing the Keyboard ................................................................2-16 Panel, CRT ....................................................................................B-20
Removing the Inverter Board ........................................................2-17 Inverter, BT, Fan ...........................................................................B-21
Removing the Modem ...................................................................2-18 968 - PCI, IDE, MuTIOL, SPI 1/4 ................................................B-22
Part Lists ..................................................A-1 968 - PCIE, LAN, GPIO 2/4 .........................................................B-23
Part List Illustration Location ........................................................ A-2 968 - USB, SATA 3/4 ...................................................................B-24
IX
Preface
968 - PWR GND 4/4 .................................................................... B-25

Clock Gen & Clock Buffer ........................................................... B-26
PHY Realtek 8201CL ................................................................... B-27
KBC-ITE IT8512E ....................................................................... B-28
JMB385 Card Reader ................................................................... B-29
Audio Codec ALC662 .................................................................. B-30
Audio AMP TPA6047A4 ............................................................. B-31
SATA HDD, Power Good, LID ................................................... B-32
Multi I/O, ODD, 3G, Click M74 .................................................. B-33
New Card, Mini PCIE, USB ........................................................ B-34
LED, PC Beep, TP, FP ................................................................. B-35
System Power ............................................................................... B-36
AC-In, Charger ............................................................................. B-37
VCore ........................................................................................... B-38
Preface
VDD3, VDD5 ............................................................................... B-39

1.05VS, 1.2V, 1.5V ...................................................................... B-40
1.8V, 0.9VS .................................................................................. B-41
VGA M92-S2 Power .................................................................... B-42
Click Finger Board for M76 ......................................................... B-43
Multi-Function Board ................................................................... B-44
Audio Board ................................................................................. B-45
Finger Sensor Board ..................................................................... B-46
Power Switch Board for M74 ....................................................... B-47
External ODD Board for M74 ...................................................... B-48
Finger Board for M74 .................................................................. B-49
Power Switch Board for M76 ....................................................... B-50
External ODD Board for W76 ..................................................... B-51
X
Introduction
Chapter 1: Introduction
Overview
This manual covers the information you need to service or upgrade the W760SUA series notebook computer. Information
about operating the computer (e.g. getting started, and the Setup utility) is in the User’s Manual. Information about driv-
ers (e.g. VGA & audio) is also found in User’s Manual. That manual is shipped with the computer.
Operating systems (e.g. Windows XP, Windows Vista, etc.) have their own manuals as do application software (e.g. word
processing and database programs). If you have questions about those programs, you should consult those manuals.
The W760SUA series notebook is designed to be upgradeable. See Disassembly on page 2 - 1 for a detailed description
1.Introduction
of the upgrade procedures for each specific component. Please note the warning and safety information indicated by the
“” symbol.
The balance of this chapter reviews the computer’s technical specifications and features.
Overview 1 - 1
Introduction
System Specifications
Processor Memory
Intel® Core™2 Duo Processor: 64-bit Wide DDRII (DDR2) Data Channel
T8100 (2.1GHz) / T8300 (2.4GHz) Two 200 Pin SO-DIMM Sockets Supporting DDRII (DDR2) 667MHz
(478-pin) Micro-FC-PGA Package, Socket P, 45nm (45 Nanometer) Memory Expandable up to 4GB (1024MB/ 2048MB DDRII Modules)
Process Technology, 3MB On-die L2 Cache & 800MHz FSB - TDP
Video Adapter
35W
T9300 (2.5GHz) / T9500 (2.6GHz) ATI Mobility Radeon HD 4570 Discrete Graphics On Board (PCIe * 16)
(478-pin) Micro-FC-PGA Package, Socket P, 45nm (45 Nanometer) 512MB GDDR2 Video RAM on board
Process Technology, 6MB On-die L2 Cache & 800MHz FSB - TDP Supports Microsoft DirectX® 10.1
35W
BIOS
T7300 (2.0GHz) / T7500 (2.2GHz)
1.Introduction
T7700 (2.4GHz) / T7800 (2.6GHz) One 8Mb SPI Flash ROM

(478-pin) Micro-FC-PGA Package, Socket P, 45nm (45 Nanometer) Phoenix™ BIOS
35W Storage
Processor (cont’d) One Changeable 12.7mm(h) Optical Device (CD/DVD) Type Drive (see
?$paratext>? on page 1 - 4)
Intel® Celeron® Processor:
Easy Changeable 2.5" 9.5 mm (h) SATA (Serial) HDD
T1600 (1.66GHz) / T1700 (1.86GHz)
(478-pin) Micro-FC-PGA Package, Socket P, 65nm (65 Nanometer)
35W Audio
575 (2.0GHz) / 585 (2.16GHz) High Definition Audio Compliant Interface
(478-pin) Micro-FC-PGA Package, Socket P, 65nm (65 Nanometer) Compliant with Microsoft UAA (Universal Audio Architecture)
2 * Built-In Speakers
35W
Built-In Microphone
Core Logic
Keyboard & Pointing Device
SiS 671DX + SiS968 Chipset
Full Size WinKey Keyboard
Display Built-in TouchPad (integrated scrolling key functionality)
15.6” HD 16:9 Wide Screen (1366 * 768) TFT LCD
1 - 2 System Specifications
Introduction
Interface Communication
Three USB 2.0 Ports 56K Fax Modem

One Headphone-Out Jack Built-In 10M/100Mb Base-TX Ethernet LAN
One Microphone-In Jack 802.11b/g Wireless LAN Mini-Card Module with USB interface
One S/PDIF-Out Jack (Option)
One RJ-11 Modem Jack 1.3M or 2.0M Pixel USB PC Camera Module (Factory Option)
One RJ-45 LAN Jack Bluetooth 2.1 + EDR (Enhanced Data Rate) Module (Factory Option)
One DC-In Jack OR
One External Monitor Port 3.5G Module:
UMTS/HSPDA-based 3.5G Module with Mini-Card Interface (Factory
Card Reader
Option)
Embedded 7-in-1 Card Reader (MS/ MS Pro/ SD/ Mini SD/ MMC/ RS Quad-band GSM/GPRS (850 MHz, 900 MHz, 1800 MHz, 1900 MHz)
MMC/ MS Duo) Note: MS Duo/ Mini SD/ RS MMC Cards require a PC UMTS WCDMA FDD (2100 MHz)
adapter
1.Introduction
Note that UMTS modes CAN NOT be used in North America.
Slots
Operating System
One ExpressCard/34/54 Slot
Two Mini-Card Slots with USB interface: Windows® Vista (with Service Pack 1)
Slot 1 for WLAN Module Windows® XP (with Service Pack 3)
Slot 2 for 3.5G Module (Factory Option)
Environmental Spec
Power
Temperature
Full Range AC/DC Adapter Operating: 5°C - 35°C
AC input 100 - 240V, 50 - 60Hz, Non-Operating: -20°C - 60°C
DC Output 19V, 4.74A (90 Watts) Relative Humidity
6 Cell Smart Lithium-Ion Battery Pack, 4400mAH Operating: 20% - 80%
9 Cell Smart Lithium-Ion Battery Pack, 7200mAH (Option) Non-Operating: 10% - 90%
Power Management Dimensions & Weight

Supports Wake on LAN 374mm (w) * 256mm (d) * 25-37.9mm (h)
Supports Wake on USB 2.7 kg With 6 Cell Battery & ODD
Supports Resume from Modem Ring
Security
Security (Kensington® Type) Lock Slot

Fingerprint ID Reader Module (Factory Option)
BIOS Password
System Specifications 1 - 3
Introduction
Optional
Optical Drive Module Options:

Super Multi Drive Module
Blu-Ray Combo Drive Module
802.11b/g Wireless LAN Mini-Card Module with USB interface
9 Cell Smart Lithium-Ion Battery Pack, 7200mAH
1.3M or 2.0M Pixel USB PC Camera Module (Factory Option)
Fingerprint ID Reader Module (Factory Option)
Bluetooth 2.1 + EDR (Enhanced Data Rate) Module (Factory Option)
OR
UMTS/HSPDA-based 3.5G Module with Mini-Card Interface (Factory
Option)
1.Introduction
Quad-band GSM/GPRS (850 MHz, 900 MHz, 1800 MHz, 1900 MHz)
UMTS WCDMA FDD (2100 MHz)
1 - 4 System Specifications
Introduction
External Locator - Top View with LCD Panel Open Figure 1

Top View
1 1. Optional Built-In
PC Camera
2. LCD
3. Speakers
4. Power Button
5. Hot Key Buttons
2
6. Keyboard
7. Built-In
Microphone
1.Introduction
8. Touchpad &
Buttons
9. LED Indicators
3 3
4
5
7
8
External Locator - Top View with LCD Panel Open 1 - 5

Introduction
Figure 2 External Locator - Front & Right side Views

Front Views
1. LED Indicators
1
1.Introduction
Figure 3
Right Side Views
2. S/PDIF-Out Jack
3. Microphone-In
Jack
4. Headphone-Out
Jack 2 3 4 5 6 7 8
5. USB 2.0 Port
6. Optical Device
Drive Bay (for
CD/DVD Device)
7. RJ-11 Phone
Jack
8. Security Lock
Slot
1 - 6 External Locator - Front & Right side Views

Introduction
External Locator - Left Side & Rear View

Figure 4
Left Side View
1. DC-In Jack
2. External Monitor
Port
3. RJ-45 LAN Jack
4. Vent/Fan Intake/
6 Outlet
5 5 7
2 3 4 5. 2 * USB 2.0 Ports
1
6. ExpressCard Slot
7. 7-in-1 Card
Reader
1.Introduction
Figure 5
Rear View
8. Battery
8
External Locator - Left Side & Rear View 1 - 7

Introduction
External Locator - Bottom View

Figure 6
Bottom View
1. Battery
2. RAM & CPU Bay
Cover 1
3. Vent/Fan Intake/
Outlet
4. Hard Disk Bay
Cover
1.Introduction
3 2
3 3

Overheating
To prevent your com-

puter from overheating
make sure nothing
blocks the vent/fan in-
takes while the com-
puter is in use.
1 - 8 External Locator - Bottom View

Introduction
Mainboard Overview - Top (Key Parts) Figure 7

Mainboard Top
Key Parts
1. KBC ITE IT8512E

2. Expresscard
Socket
1.Introduction
2 1
Mainboard Overview - Top (Key Parts) 1 - 9

Introduction
Figure 8 Mainboard Overview - Bottom (Key Parts)

Mainboard Bottom
Key Parts
1. CPU Socket
2. VGA Chip
3. North Bridge
4. Mini-Card
Connector
(WLAN Module)
5. Mini-Card 2 1
4
Connector
6. Memory Slots
1.Introduction
DDR2 So-DIMM
7. South Bridge
8. Card Reader 5
Socket
3
1 - 10 Mainboard Overview - Bottom (Key Parts)

Introduction
Mainboard Overview - Top (Connectors) Figure 9

Mainboard Top
3 Connectors
1 2
1. CCD Cable
Connector
2. Inverter Connector
3. LCD Cable
Connector
4. Keyboard Cable
Connector
5. Audio Cable
Connector
1.Introduction
6. Microphone Cable
Connector
7. Touch Pad
Connector
4 8. Fingerprint Cable
Connector
6
8 7
Mainboard Overview - Top (Connectors) 1 - 11

Introduction
Figure 10 Mainboard Overview - Bottom (Connectors)

Mainboard Bottom
Connectors
1. BT Cable
Connector
2. Multi-Board Cable
Connector 1
3. CD-ROM
Connector 2
4. HDD Connector
5. CMOS Bat.
Connector
1.Introduction
6. CPU Fan Cable

Connector
1 - 12 Mainboard Overview - Bottom (Connectors)

Disassembly
Chapter 2: Disassembly
Overview
This chapter provides step-by-step instructions for disassembling the W760SUA series notebook’s parts and subsystems.
When it comes to reassembly, reverse the procedures (unless otherwise indicated).
We suggest you completely review any procedure before you take the computer apart.
Procedures such as upgrading/replacing the RAM, optical device and hard disk are included in the User’s Manual but are
repeated here for your convenience.
2.Disassembly
To make the disassembly process easier each section may have a box in the page margin. Information contained under
the figure # will give a synopsis of the sequence of procedures involved in the disassembly procedure. A box with a  
lists the relevant parts you will have after the disassembly process is complete. Note: The parts listed will be for the dis-
Information
assembly procedure listed ONLY, and not any previous disassembly step(s) required. Refer to the part list for the previ-
ous disassembly procedure. The amount of screws you should be left with will be listed here also.
A box with a  will also provide any possible helpful information. A box with a  contains warnings.
An example of these types of boxes are shown in the sidebar. 

Warning
Overview 2 - 1
Disassembly
NOTE: All disassembly procedures assume that the system is turned OFF, and disconnected from any power supply (the
battery is removed too).
Maintenance Tools
The following tools are recommended when working on the notebook PC:
• M3 Philips-head screwdriver
• M2.5 Philips-head screwdriver (magnetized)
• M2 Philips-head screwdriver
• Small flat-head screwdriver
• Pair of needle-nose pliers
• Anti-static wrist-strap
2.Disassembly
Connections
Connections within the computer are one of four types:
Locking collar sockets for ribbon connectors To release these connectors, use a small flat-head screwdriver to
gently pry the locking collar away from its base. When replac-
ing the connection, make sure the connector is oriented in the
same way. The pin1 side is usually not indicated.
Pressure sockets for multi-wire connectors To release this connector type, grasp it at its head and gently
rock it from side to side as you pull it out. Do not pull on the
wires themselves. When replacing the connection, do not try to
force it. The socket only fits one way.
Pressure sockets for ribbon connectors To release these connectors, use a small pair of needle-nose pli-
ers to gently lift the connector away from its socket. When re-
placing the connection, make sure the connector is oriented in
the same way. The pin1 side is usually not indicated.
Board-to-board or multi-pin sockets To separate the boards, gently rock them from side to side as
you pull them apart. If the connection is very tight, use a small
flat-head screwdriver - use just enough force to start.
2 - 2 Overview
Disassembly
Maintenance Precautions
The following precautions are a reminder. To avoid personal injury or damage to the computer while performing a re- 
moval and/or replacement job, take the following precautions: Power Safety
Warning
1. Don't drop it. Perform your repairs and/or upgrades on a stable surface. If the computer falls, the case and other
Before you undertake
components could be damaged. any upgrade proce-
2. Don't overheat it. Note the proximity of any heating elements. Keep the computer out of direct sunlight. dures, make sure that
3. Avoid interference. Note the proximity of any high capacity transformers, electric motors, and other strong mag- you have turned off the
netic fields. These can hinder proper performance and damage components and/or data. You should also monitor power, and discon-
the position of magnetized tools (i.e. screwdrivers). nected all peripherals
and cables (including
4. Keep it dry. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly telephone lines). It is
damaged. advisable to also re-
5. Be careful with power. Avoid accidental shocks, discharges or explosions. move your battery in
2.Disassembly
•Before removing or servicing any part from the computer, turn the computer off and detach any power supplies. order to prevent acci-
•When you want to unplug the power cord or any cable/wire, be sure to disconnect it by the plug head. Do not pull on the wire. dentally turning the
machine on.
6. Peripherals – Turn off and detach any peripherals.
7. Beware of static discharge. ICs, such as the CPU and main support chips, are vulnerable to static electricity.
Before handling any part in the computer, discharge any static electricity inside the computer. When handling a
printed circuit board, do not use gloves or other materials which allow static electricity buildup. We suggest that
you use an anti-static wrist strap instead.
8. Beware of corrosion. As you perform your job, avoid touching any connector leads. Even the cleanest hands pro-
duce oils which can attract corrosive elements.
9. Keep your work environment clean. Tobacco smoke, dust or other air-born particulate matter is often attracted
to charged surfaces, reducing performance.
10. Keep track of the components. When removing or replacing any part, be careful not to leave small parts, such as
screws, loose inside the computer.
Cleaning
Do not apply cleaner directly to the computer, use a soft clean cloth.
Do not use volatile (petroleum distillates) or abrasive cleaners on any part of the computer.
Overview 2 - 3
Disassembly
Disassembly Steps
The following table lists the disassembly steps, and on which page to find the related information. PLEASE PERFORM
THE DISASSEMBLY STEPS IN THE ORDER INDICATED.
To remove the Battery: To remove the Keyboard:

1. Remove the battery page 2 - 5
2. Remove the Keyboard page 2 - 16
To remove the HDD:
To remove the Inverter Board:
2. Remove the HDD page 2 - 6
2. Remove the inverter board page 2 - 17
To remove the Optical Device:
2.Disassembly
To remove the Modem:

2. Remove the Optical device page 2 - 8
2. Remove the HDD page 2 - 6
To remove the System Memory: 3. Remove the Optical device page 2 - 8
1. Remove the battery page 2 - 5 4. Remove the processor page 2 - 11
2. Remove the System Memory page 2 - 9 5. Remove the keyboard page 2 - 16
6. Remove the modem page 2 - 18
To remove the Processor:
2. Remove the Processor page 2 - 11
To remove the Wireless LAN Module:
2. Remove the Wireless LAN page 2 - 14
To remove the Bluetooth Module:
2. Remove the Bluetooth page 2 - 15
2 - 4 Disassembly Steps
Disassembly
Removing the Battery

If you are confident in undertaking upgrade procedures yourself, for safety reasons it is best to remove the battery.
1. Turn the computer off, and turn it over.

Figure 1
2. Slide the latch 1 in the direction of the arrow.
Battery Removal
3. Slide the latch 2 in the direction of the arrow, and hold it in place.
4. Slide the battery 63 out in the direction of the arrow 4 . a. Slide the latch and hold
in place.
b. Slide the battery in the di-
a. rection of the arrow.
2.Disassembly
2 1
b.
3
4 
3. Battery
Removing the Battery 2 - 5

Disassembly
Removing the Hard Disk Drive

Figure 2 The hard disk drive can be taken out to accommodate other 2.5" serial (SATA) hard disk drives with a height of 9.5mm
HDD Assembly (h). Follow your operating system’s installation instructions, and install all necessary drivers and utilities (as outlined in
Removal Chapter 4 of the User’s Manual) when setting up a new hard disk.
a. Locate the HDD bay Hard Disk Upgrade Process

cover and remove the
screw(s).
1. Turn off the computer, and remove the battery (page 2 - 5).
2. Locate the hard disk bay cover and remove screw 1 & 2 .
a.
2.Disassembly
1 2

HDD System Warning
 New HDD’s are blank. Before you begin make sure:
You have backed up any data you want to keep from your old HDD.
• 2 Screws You have all the CD-ROMs and FDDs required to install your operating system and programs.
If you have access to the internet, download the latest application and hardware driver updates for the operating system you plan
to install. Copy these to a removable medium.
2 - 6 Removing the Hard Disk Drive

Disassembly
3. Remove the hard disk bay cover 63 .

4. Grip the tab and slide the hard disk in the direction of arrow 4 . Figure 3
HDD Assembly
5. Lift the hard disk out of the bay 5 .
Removal (cont’d.)
6. Remove the screw 6 and the adhesive cover 67 from the hard disk 68 .
7. Reverse the process to install a new hard disk (do not forget to replace all the screws and covers).
b. Remove the HDD bay
cover.
b. c. Grip the tab and slide the
HDD in the direction of
the arrow.
d. Lift the HDD assembly
3 out of the bay.
e. Remove the screws and
adhesive cover.
2.Disassembly
c. e.
4
7
d. 8

3. HDD Bay Cover
5 7. Adhesive Cover
8. HDD
• 2 Screws
Removing the Hard Disk Drive 2 - 7

Disassembly
Figure 4 Removing the Optical (CD/DVD) Device

Optical Device
Removal
2. Locate the hard disk bay cover and remove screw 1 & 2 .
3. Remove the hard disk bay cover 63 .
a. Remove the screws.
b. Remove the HDD bay 4. Remove the screw at point 4 , and use a screwdriver to carefully push out the optical device 6 at point 5 .
cover. 5. Insert the new device and carefully slide it into the computer (the device only fits one way. DO NOT FORCE IT; The
c. Remove the screw. screw holes should line up).
d. Push the optical device 6. Restart the computer to allow it to automatically detect the new device.
out off the computer at
point 6.
a. c.
2.Disassembly
4
1 2
d.
b.
 3
3. HDD Bay Cover
8. Optical Device 6
5
• 3 Screws
2 - 8 Removing the Optical (CD/DVD) Device

Disassembly
Removing the System Memory (RAM) Figure 5

The computer has two memory sockets for 200 pin Small Outline Dual In-line Memory Modules (SO-DIMM) supporting RAM Module
Removal
DDR2 667/800MHz. The main memory can be expanded up to 4GB. The SO-DIMM modules supported are 1024MB,
and 2048MB and DDRII Modules. The total memory size is automatically detected by the POST routine once you turn a. Remove the screws.
on your computer. b. Remove the cover.
Memory Upgrade Process

1. Turn off the computer, remove the battery (page 2 - 5).
2. Locate the component bay cover 1 , and remove screws 2 - 4 .
3. Carefully (a fan and cable are attached to the under side of the cover) lift up the bay cover.
4. Carefully disconnect the fan cable 5 , and remove the cover 1 .
2.Disassembly
a. b. 
Caution
2
The heat sink, and
1 CPU area in general,
contains parts which
3 1 are subject to high tem-
peratures. Allow the
area time to cool before
removing these parts.
5
4
 
Fan Cable 1. Component Bay
Cover
Make sure you reconnect the fan cable 5 before screwing down the bay cover.
• 3 Screws
Removing the System Memory (RAM) 2 - 9

Disassembly
Figure 6 5. Gently pull the two release latches ( 6 & 7 ) on the sides of the memory socket in the direction indicated by the
RAM Module arrows (Figure 6c).
Removal (cont’d.)
c. d.
c. Pull the release
latch(es).
d. Remove the module(s).
6 7
8

2.Disassembly
Single Memory
Module Installation
If your computer has a
single memory module,
then insert the module
into the Channel 0
(J_DIMM_1) socket. In
this case, this is the low-
er memory socket (the
socket closest to the
mainboard).
6. The RAM module(s) 8 will pop-up (Figure 6d), and you can then remove it.
7. Pull the latches to release the second module if necessary.
8. Insert a new module holding it at about a 30° angle and fit the connectors firmly into the memory slot.
9. The module’s pin alignment will allow it to only fit one way. Make sure the module is seated as far into the slot as it
will go. DO NOT FORCE the module; it should fit without much pressure.
 10. Press the module in and down towards the mainboard until the slot levers click into place to secure the module.
11. Replace the bay cover and screws (make sure you reconnect the fan cable before screwing down the bay
8. RAM Module(s) cover).
12. Restart the computer to allow the BIOS to register the new memory configuration as it starts up.
2 - 10 Removing the System Memory (RAM)

Disassembly
Removing and Installing the Processor

Processor Removal Procedure Figure 7
1. Turn off the computer, remove the battery (page 2 - 5) and the component bay cover (page 2 - 9). Processor Removal
2. The CPU heat sink will be visible at point A on the mainboard.
3. Loosen the CPU heat sink screws in the order 4 , 3 , 2 & 1 (the reverse order as indicated on the label). a. Remove the cover and
4. Carefully lift up the heat sink B (Figure 7c) off the computer. Iocate the heat sink.
b. Remove the screws in
the order indicated.
a. c. Remove the heat sink.
2.Disassembly
b. c.
3 2 B
1 4

B. Heat Sink
• 4 Screws
Removing and Installing the Processor 2 - 11

Disassembly
5. Turn the release latch C towards the unlock symbol , to release the CPU (Figure 8d).
Figure 8 6. Carefully (it may be hot) lift the CPU D up out of the socket (Figure 8e).
Processor Removal 7. See page 2 - 13 for information on inserting a new CPU.
(cont’d) 8. When re-inserting the CPU, pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!).
d. Turn the release latch to
unlock the CPU. d.
e. Lift the CPU out of the
socket.
C
2.Disassembly
Unlock Lock
e.

D Caution
The heat sink, and CPU area in

general, contains parts which are
subject to high temperatures. Al-
low the area time to cool before re-
moving these parts.

D. CPU
2 - 12 Removing and Installing the Processor

Disassembly
Processor Installation Procedure Figure 9

1. Insert the CPU A , pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!), and Processor
turn the release latch B towards the lock symbol (Figure 9b). Installation
2. Remove the sticker C (Figure 9c) from the heat sink.
3. Insert the heat sink D as indicated in Figure 9c. a. Insert the CPU.
4. Tighten the CPU heat sink screws in the order 1 , 2 , 3 , & 4 (the order as indicated on the label). b. Turn the release latch to-
wards the lock symbol.
5. Replace the component bay cover and tighten the screws (page 2 - 9).
c. Remove the sticker from
the heat sink and insert
the heat sink.
a. c. d. Tighten the screws.
C
A
2.Disassembly
D
b. d.
3 2

1 4 A. CPU
B D. Heat Sink
• 4 Screws
Removing and Installing the Processor 2 - 13

Disassembly
Figure 10 Removing the Wireless LAN Module

Wireless LAN 1. Turn off the computer, remove the battery (page 2 - 5) and the component bay cover (page 2 - 9).
Module Removal 2. The Wireless LAN module will be visible at point 1 on the mainboard.
3. Carefully disconnect cables 2 - 3 , then remove screw 4 from the module socket.
a. Remove the cover. 4. The Wireless LAN module 5 will pop-up.
b. Disconnect the cable
5. Lift the Wireless LAN module (Figure 10d) up and off the computer.
and remove the screw.
c. The WLAN module will a.
pop up. b.
d. Lift the WLAN module
out.
1 2
Note: Make sure you 3

2.Disassembly
reconnect the antenna 4

cable to ‘’1’’ +
‘’2’’socket (Figure
b).
c.
d.

5. WLAN Module. 5
• 1 Screw 5
2 - 14 Removing the Wireless LAN Module

Disassembly
Removing the Bluetooth Module Figure 11

Bluetooth Module
1. Turn off the computer, remove the battery (page 2 - 5) and the component bay cover (page 2 - 9).
Removal
2. The Bluetooth will be visible at point 1 on the mainboard.
3. Remove the screw 2 and turn the module over.
a. Remove the cover and Io-
4. Carefully separate the Bluetooth module from the connector 3 and disconnect the cable 4 . cate the Bluetooth.
5. Lift the Bluetooth module 5 (Figure 11d) up and off the computer. b. Remove the screw.
c. Disconnect the cable and
the connector.
a. d. d. Lift the Bluetooth module
up off the socket.
1
5
2.Disassembly
b. c.
4
d. 
2 5. Bluetooth Module
• 1 Screw
Removing the Bluetooth Module 2 - 15

Disassembly
Removing the Keyboard

1. Turn off the computer.
Figure 12 2. Remove the battery
Keyboard Removal 3. Remove the screws 2 - 3 and use a screwdriver to carefully push out the top cover module 5 at point 4 .
4. Remove the top cover module 5 and the screws 6 - 10 (Figure 12d),
a. Remove the battery. 5. Carefully lift the keyboard 11 up, being careful not to bend the keyboard ribbon cable (Figure 12e).
b. Remove the screws and 6. Disconnect the keyboard ribbon cable 12 from the locking collar socket 13 .
use a screwdriver to care- 7. Carefully lift up the keyboard (Figure 12f) off the computer.
fully push out the top cover
module at point 4 .
a. d. e.
c. Remove the Top cover
module. 1
6 7 8 9 10 12
d. Remove the screws. 11
2.Disassembly
e. Lift the keyboard up and

disconnect the cable from 13
the locking collar.
f. Remove the keyboard.
b.
4 5
2 3 f.
c.
5
 11
1. Battery
5. Top cover module
11. Keyboard
2 - 16 Removing the Keyboard

Disassembly
Removing the Inverter Board Figure 13

Inverter Board
Removal
2. Remove any rubber covers, screws 1 - 6 (Figure 13a), then run your finger around the middle of the frame to
carefully unsnap the LCD front panel module 7 from the back.
a. Remove the 6 screws
3. Discharge the remaining system power (see ?$paratext>? below). and unsnap the LCD
4. Remove screw 8 (Figure 13b) from the inverter, and carefully lift the inverter board up slightly. front panel module from
5. Disconnect cables 9 & 10 (Figure 13c) from the inverter, then remove the inverter 11 (Figure 13d) from the the back.
LCD back cover module. b. Remove the screw and
discharge the remaining
power from the inverter
a. b. board and lift the board
2 3 4 5 up slightly.
c. Disconnect the cables
2.Disassembly
from the inverter.
8 d. Remove the inverter.
c.
1 6
9 10
7
d. 
 11
Inverter Power Warning 7. LCD Front Panel
11. Inverter Board
In order to prevent a short circuit when re-
moving the inverter it is necessary to dis-
charge any remaining system power. To do • 6 Screws
so, press the computer’s power button for a
few seconds before disconnecting the in-
verter cable.
Removing the Inverter Board 2 - 17

Disassembly
Figure 14
Removing the Modem
Modem Removal 1. Turn off the computer, remove the battery (page 2 - 5), HDD (page 2 - 6), component bay cover (page 2 - 9), opti-
cal device (page 2 - 8), CPU (page 2 - 11), bluetooth (page 2 - 15) and keyboard (page 2 - 16).
a. Remove the screws. 2. Remove screws 1 - 22 from the bottom case.
b. Turn the computer over, 3. Turn the computer over, remove screws 23 - 24 and disconnect cables 25 - 28 (Figure 15b).
remove the screws and
disconnect the cable.
a. 10
1 3 5 6 7 8
2 4 9
21 22
11
2.Disassembly
20
12
17 18 19
14
16 15 13
b.
 24
25
23
• 24 Screws
28 27 26
2 - 18 Removing the Modem

Disassembly
4. Carefully lift the top case 29 up and off the computer (Figure 15c).
5. Remove screws 30 - 32 (Figure 15d) from the computer. Figure 15
6. Remove screws 33 - 34 (Figure 15e) and disconnect the cable 35 from the modem module. Modem Removal
7. Lift the modem up and separate the modem from the connector 36 . (cont’d.)
8. Lift the modem 37 off the computer.
c. Lift the cover off the
computer.
c. e. d. Remove the screws.
e. Remove the screws and
disconnect the connec-
tor.
f. Lift the modem out.
35
33 34
29
2.Disassembly
27
f.
d.
31
36 37

29. Top Case
37. Modem
30
• 5 Screws
32
Removing the Modem 2 - 19

Disassembly
2.Disassembly
2 - 20
Part Lists
Appendix A: Part Lists

This appendix breaks down the W760SUA series notebook’s construction into a series of illustrations. The component
part numbers are indicated in the tables opposite the drawings.
Note: This section indicates the manufacturer’s part numbers. Your organization may use a different system, so be sure
to cross-check any relevant documentation.
Note: Some assemblies may have parts in common (especially screws). However, the part lists DO NOT indicate the
total number of duplicated parts used.
Note: Be sure to check any update notices. The parts shown in these illustrations are appropriate for the system at the
A.Part Lists
time of publication. Over the product life, some parts may be improved or re-configured, resulting in new part numbers.
A - 1
Part Lists
Part List Illustration Location

The following table indicates where to find the appropriate part list illustration.
Table A- 1
Part List Illustration
Location
Parts
Top with Fingerprint page A - 3
Top without Fingerprint page A - 4
Bottom page A - 5
A.Part Lists
LCD page A - 6
HDD page A - 7
DVD Super Multi page A - 8
A - 2 Part List Illustration Location

Part Lists
Top with Fingerprint
Figure A - 1
Top with
A.Part Lists
Fingerprint
Top with Fingerprint A - 3

Part Lists
Top without Fingerprint
Figure A - 2
A.Part Lists
Top without
Fingerprint
A - 4 Top without Fingerprint

Part Lists
Bottom
Figure A - 3
Bottom
A.Part Lists
Bottom A - 5
Part Lists
LCD
Figure A - 4
A.Part Lists
LCD
A - 6 LCD
Part Lists
HDD
Figure A - 5
HDD
A.Part Lists
HDD A - 7
Part Lists
DVD Super Multi
Figure A - 6
A.Part Lists
DVD Super Multi
A - 8 DVD Super Multi

Schematic Diagrams
Appendix B: Schematic Diagrams

This appendix has circuit diagrams of the W760SUA notebook’s PCB’s. The following table indicates where to find the
appropriate schematic diagram.
Diagram - Page Diagram - Page Diagram - Page

Table B - 1
System Block Diagram - Page B - 2 External VGA M92-S2-7 - Page B - 19 System Power - Page B - 36 Schematic
Penryn (Socket-P)1/2 - Page B - 3 Panel, CRT - Page B - 20 AC-In, Charger - Page B - 37 Diagrams
B.Schematic Diagrams
Penryn (Socket-P) 2/2 - Page B - 4 Inverter, BT, Fan - Page B - 21 VCore - Page B - 38
SiS671DX - Host, PCIE 1/5 - Page B - 5 968 - PCI, IDE, MuTIOL, SPI 1/4 - Page B - 22 VDD3, VDD5 - Page B - 39
SiS671DX - DRAM 2/5 - Page B - 6 968 - PCIE, LAN, GPIO 2/4 - Page B - 23 1.05VS, 1.2V, 1.5V - Page B - 40
SiS671DX - MuTIOL 3/5 - Page B - 7 968 - USB, SATA 3/4 - Page B - 24 1.8V, 0.9VS - Page B - 41
SiS671DX - PWR 4/5 - Page B - 8 968 - PWR GND 4/4 - Page B - 25 VGA M92-S2 Power - Page B - 42
SiS671DX - GND 5/5 - Page B - 9 Clock Gen & Clock Buffer - Page B - 26 Click Finger Board for M76 - Page B - 43
DDR2 SO-DIMM_1 - Page B - 10 PHY Realtek 8201CL - Page B - 27 Multi-Function Board - Page B - 44 
DDR2 SO-DIMM_2 - Page B - 11 KBC-ITE IT8512E - Page B - 28 Audio Board - Page B - 45 Version Note
SiS307ELV - Page B - 12 JMB385 Card Reader - Page B - 29 Finger Sensor Board - Page B - 46
The schematic dia-
grams in this chapter
External VGA M92-S2-1 - Page B - 13 Audio Codec ALC662 - Page B - 30 Power Switch Board for M74 - Page B - 47 are based upon ver-
sion 6-7P-W76AA-
External VGA M92-S2-2 - Page B - 14 Audio AMP TPA6047A4 - Page B - 31 External ODD Board for M74 - Page B - 48 002. If your mainboard
(or other boards) are a
External VGA M92-S2-3 - Page B - 15 SATA HDD, Power Good, LID - Page B - 32 Finger Board for M74 - Page B - 49 later version, please
check with the Service
External VGA M92-S2-4 - Page B - 16 Multi I/O, ODD, 3G, Click M74 - Page B - 33 Power Switch Board for M76 - Page B - 50
Center for updated di-
agrams (if required).
External VGA M92-S2-5 - Page B - 17 New Card, Mini PCIE, USB - Page B - 34 External ODD Board for W76 - Page B - 51
External VGA M92-S2-6 - Page B - 18 LED, PC Beep, TP, FP - Page B - 35
B - 1
Schematic Diagrams
System Block Diagram
AC-IN,CHARGER CL EVO W760SUA System Block Diagram SYSTEM POWER
14.318 MHz +VCORE

MULTI I/O BOARD Colck Generator
SPK_R, RJ-11 ICS9LPR600 Intel Penryn Memory Termination
MODEM, CCD 56pins TSSOP

17 .1 *8 .1 *1.2 mm
PROCESSOR VDD3,VDD5,3.3V,5V
4 79 pi ns s ocket P DDRII
Au di o B oa rd SO-DIMM0
EXTERNAL VGA 3 5*3 5*2. 7mm 1.05VS,1.5V,1.2V
USB, SPDIF, MIC IN ATI M92-S2 DDRII
Sheet 1 of 50 HEADPHONE 631 balls BGA
23*23*1.92mm FOR FSB
SO-DIMM1
1.8V,0.9VS
System Block LCD CONNECTOR,
INVERTER LVDS (TV)
W760SUA 667/800 MHz Clock Buffer
ICS9P935
28pins SSOP
Diagram CLICK BOARD
SiS307ELV
169balls BGA
NORTH BRIDGE 17 .1*8 .1 *1 .2 mm
GPU CORE,1.1V
1 3*1 3*1. 7mm
TOUCH PAD SiSM671DX 533/667(/800) MHz
Synaptic RJ-11 SPDIF MIC HP
810602-1703 CRT 852balls TEBGA OUT IN OUT
35*35*2.4mm SHEET30
AZALIA
32.768 KHz Azalia Codec AUDIO AMP
MDC
EC MODULE Realtek TPA
SPI Mu TI OL 1G
ITE 8502E ALC662 6047A4
48pins LQFP 24pins TSSOP
128pins LQFP INT SPK
LPC 33 MHz MDC CON 9*9*1 .6m m 9 .8 *6.4 *1. 2mm SHEET 30,43
1 4*1 4*1. 6mm
SOUTH BRIDGE AZALIA LINK 24 MHz INT MIC
SiS968
INT. K/B EC SMBUS
570balls mBGA
PCIE 100 MHz
THERMAL SMART SMART 27*27*2.5mm
SENSOR FAN BATTERY GMAC
32.768KHz
F75383M
10/100M PHY New Card Mini PCIE
CARD READER
SATA I/II 3.0Gb/s RTL8201CL SOCKET SOCKET
USB2.0 48pins LQFP (USB0) (USB1) JMB385
PATA-133 480 Mbps 9*9*1.7mm
25 MHz
FINGER PRINTER BOARD
3G CARD USB & Phone
SATA HDD, SATA ODD CCD Jack B'd USB2 MINI PCIE 7IN1
LID (USB7) Bluetooth (USB5) (USB3)
USB4 FingerPrint GOLAN SOCKET
USB6
RJ-45
(Optional) 12 MHz
(Optional)
B - 2 System Block Diagram

Schematic Diagrams
Penryn (Socket-P)1/2
J SKT1 A J S K T 1B
4 H _A # [ 3 5 : 3 ] H_ A # 3 J4 H 1
A[3 ]# ADS# H_ AD S# 4 4 H _ D # [ 6 3: 0 ] H _D # [ 6 3: 0 ] 4
ADDR GROUP_0
H_ A # 4 L5 E 2 H _ D# 0 E2 2 Y2 2 H_ D# 3 2
A[4 ]# B N R# H_ B N R# 4 D[0 ]# D[3 2 ]#
H_ A # 5 L4 G 5 H _ D# 1 F2 4 AB2 4 H_ D# 3 3
H_ A # 6 K5 A[5 ]# B P RI# H_ BP R I# 4 H _ D# 2 E2 6 D[1 ]# D[3 3 ]# V2 4 H_ D# 3 4
A[6 ]# D[2 ]# D[3 4 ]#
DATA GRP 0
H_ A # 7 M3 H 5 H _ D# 3 G 22 V2 6 H_ D# 3 5
Sheet 2 of 50
DATA GRP 2
H_ A # 8 A[7 ]# D E F E R# H_ DE F E R# 4 H _ D# 4 D[3 ]# D[3 5 ]# H_ D# 3 6
N2 F 21 H_ DR DY # 4 F2 3 V2 3
H_ A # 9 J1 A[8 ]# D RD Y # E 1 H _ D# 5 G 25 D[4 ]# D[3 6 ]# T 22 H_ D# 3 7
H_ A # 1 0 A[9 ]# D BSY# H_ DB S Y # 4 H _ D# 6 D[5 ]# D[3 7 ]# H_ D# 3 8
N3 E2 5 U2 5
H_ A # 1 1 P5 A[1 0 ]# F 1 H_ BR 0 # H _ D# 7 E2 3 D[6 ]# D[3 8 ]# U2 3 H_ D# 3 9
H_ A # 1 2 A[1 1 ]# B R 0# H _ B R 0# 4 H _ D# 8 D[7 ]# D[3 9 ]# H_ D# 4 0
Penryn (Socket-P)
P2 K2 4 Y2 5
CONT RO L
H_ A # 1 3 L2 A[1 2 ]# D 20 H_ IE R R# H _ D# 9 G 24 D[8 ]# D[4 0 ]# W22 H_ D# 4 1
H_ A # 1 4 A[1 3 ]# IE R R# H_ IN IT # H _ D# 1 0 D[9 ]# D[4 1 ]# H_ D# 4 2
P4 B 3 J24 Y2 3
H_ A # 1 5 P1 A[1 4 ]# I N I T# H _ I N I T# 22 H _ D# 1 1 J23 D[1 0 ]# D[4 2 ]# W24 H_ D# 4 3
A[1 5 ]# D[1 1 ]# D[4 3 ]#
H_ A # 1 6 R1 H 4 H _ D# 1 2 H 22 W25 H_ D# 4 4
M1 A[1 6 ]# LO C K # H _ L OC K # 4 H _ D# 1 3 F2 6 D[1 2 ]# D[4 4 ]# AA2 3 H_ D# 4 5
4
4
H _A D S T B # 0
H _ R E Q# [ 4 : 0] H _R E Q #0
H _R E Q #1
H _R E Q #2
K3
H2
K2
AD ST B[0 ]#
R
R
R
E Q[ 0 ] #
E Q[ 1 ] #
E Q[ 2 ] #
R E S E T#
R S [ 0] #
R S [ 1] #
R S [ 2] #
C
F
F
G
1
3
4
3
H_ C P UR S T #
H _ C P U R S T# 4
H _ R S #0
H _ R S #1
H _ R S #2
4
4
4
4
4
H _ D S T B N #0
H_ D S T B P # 0
H_ D# 1 4
H _ D# 1 5
K2 2
H 23
J26
H 26
D[1 3 ]#
D[1 4 ]#
D[1 5 ]#
D S T B N [ 0] #
DS T B P [0 ] #
D[4 5 ]#
D[4 6 ]#
D[4 7 ]#
D S TB N [ 2 ] #
D ST BP[2 ]#
AA2 4
AB2 5
Y2 6
AA2 6
H_ D# 4 6
H_ D# 4 7
H _D S T B N # 2 4
H _D S T B P # 2 4
1/2
H _R E Q #3 J3 G 2 H 25 U2 2
H _R E Q #4 R E Q[ 3 ] # T RD Y # H_ T RD Y # 4 4 H _D I N V #0 DIN V [ 0 ]# DIN V [ 2 ]# H _D I N V #2 4
L1
R E Q[ 4 ] #
G 6
4 H _ A # [ 3 5: 3 ] H _A #1 7 H I T# H _ H I T# 4 4 H _ D # [ 6 3: 0 ] H _ D# 1 6 H_ D# 4 8 H _D # [ 6 3: 0 ] 4
Y2 E 4 N 22 AE2 4
H _A #1 8 U5 A[1 7 ]# H I T M# H _ H I TM # 4 H _ D# 1 7 K2 5 D[1 6 ]# D[4 8 ]# A D2 4 H_ D# 4 9
A[1 8 ]# D[1 7 ]# D[4 9 ]#
H _A #1 9 R3 A D4 H_ BP M 0 # R1 0 0 51 . 1 _ 1 %_ 0 4 1 .0 5 VS H _ D# 1 8 P2 6 AA2 1 H_ D# 5 0
A[1 9 ]# B P M [ 0] # D[1 8 ]# D[5 0 ]#
ADDR GROUP_1
H _A #2 0 W6 A D3 H_ BP M 1 # R1 0 1 51 . 1 _ 1 %_ 0 4 H _ D# 1 9 R 23 AB2 2 H_ D# 5 1
H _A #2 1 U4 A[2 0 ]# B P M [ 1] # A D1 H_ BP M 2 # R6 6 51 . 1 _ 1 %_ 0 4 H _ D# 2 0 L23 D[1 9 ]# D[5 1 ]# AB2 1 H_ D# 5 2
H _A #2 2 A[2 1 ]# B P M [ 2] # H_ BP M 3 # R9 2 H _ D# 2 1 D[2 0 ]# D[5 2 ]# H_ D# 5 3
DATA G RP 1
Y5 A C4 51 . 1 _ 1 %_ 0 4 M 24 A C2 6
DATA GRP 3
A[2 2 ]# B P M [ 3] # D[2 1 ]# D[5 3 ]#
XDP/ ITP SIGNALS

H _A #2 3 U1 A C2 H_ P R DY # R8 8 56 _ 1 % _0 4 H _ D# 2 2 L22 A D2 0 H_ D# 5 4
H _A #2 4 A[2 3 ]# P RD Y # H _ P R E Q# H _ D# 2 3 D[2 2 ]# D[5 4 ]# H_ D# 5 5
R4 A C1 M 23 AE2 2
H _A #2 5 T5 A[2 4 ]# P R E Q# A C5 H_ T CK H _ D# 2 4 P2 5 D[2 3 ]# D[5 5 ]# AF2 3 H_ D# 5 6
H _A #2 6 A[2 5 ]# T CK H_ T DI H _ D# 2 5 D[2 4 ]# D[5 6 ]# H_ D# 5 7
T3 A A6 P2 3 A C2 5
H _A #2 7 W2 A[2 6 ]# T DI A B3 H_ T DO R8 0 54 . 9 _ 1 %_ 0 4 H _ D# 2 6 P2 2 D[2 5 ]# D[5 7 ]# AE2 1 H_ D# 5 8
H _A #2 8 A[2 7 ]# TD O H _ T MS 1 .0 5 VS H _ D# 2 7 D[2 6 ]# D[5 8 ]# H_ D# 5 9
W5 A B5 T2 4 A D2 1
H _A #2 9 Y4 A[2 8 ]# T MS A B6 H _ T R S T# H _ D# 2 8 R 24 D[2 7 ]# D[5 9 ]# A C2 2 H_ D# 6 0
A[2 9 ]# T R S T# D[2 8 ]# D[6 0 ]#
H _A #3 0 U2 C 20 H_ D B R# H _ D# 2 9 L25 A D2 3 H_ D# 6 1
H _A #3 1 V4 A[3 0 ]# D B R# H _ D# 3 0 T2 5 D[2 9 ]# D[6 1 ]# AF2 2 H_ D# 6 2
H _A #3 2 W3 A[3 1 ]# H _ D# 3 1 N 25 D[3 0 ]# D[6 2 ]# A C2 3 H_ D# 6 3
H _A #3 3 A[3 2 ]# D[3 1 ]# D[6 3 ]#
AA4 THERM AL 4 H _ D S T B N #1 L26 AE2 5 H _D S T B N # 3 4
H _A #3 4 AB2 A[3 3 ]# M 26 D S T B N [ 1] # D S TB N [ 3 ] # AF2 4
H _A #3 5 A[3 4 ]# H _ P R OC H O T# 4 H_ D S T B P # 1 DS T B P [1 ] # D ST BP[3 ]# H _D S T B P # 3 4
AA3 D 21 H _ P R OC H O T# 2 2 4 H _D I N V #1 N 24 A C2 0 H _D I N V #3 4
V1 A[3 5 ]# P R OC H O T# A 24 H _ T H E R MD A DIN V [ 1 ]# DIN V [ 3 ]#
4 H _ A D S TB #1 AD ST B[1 ]# T HE RM DA H _ T H E R MD C C OM P 0
B 25 AD 2 6 R2 6
H _ A 2 0 M# A6 T H E R MD C R4 5 8 * 1K _0 4 Z0210 C 23 GT L R E F C OM P [ 0 ] U2 6 C OM P 1
22 H _ A 2 0 M# H_ F E R R# A 2 0 M# H _ T H R MT R I P # Z0211 D 25 TE S T1 M ISC C OM P [ 1 ] C OM P 2
ICH
A5 C 7 R1 2 6 * 1K _0 4 AA1
22
22
H_ F E R R#
H _I G N N E #
H _ I GN N E # C4 F E R R#
IG NN E #
TH E R M T R I P # H _ TH R M T R I P # 2 2 Z0212 C 24 TE S T2
TE S T3
C OM P [ 2 ]
C OM P [ 3 ]
Y1 C OM P 3 If used M672
H_ S T P CL K # D5
C 5 5 4 * 0. 1 u _ 1 0V _ X 7 R _ 0 4 Z 0 2 1 3 A F 2 6
Z 0 2 1 4 AF 1 TE S T4 E5 H _D P R S TP # 6 , 3 7 than del R3
22 H_ S T PCL K# S T P C LK # TE S T5 DP R S T P # H _D P S L P # 6
H_ INT R C6 H CLK Z 0 2 1 5 A2 6 B5 H _ DP S L P #
22 H _I N T R H_ NM I B4 L I N T0 A 22 Z0216 C 3 TE S T6 D PSL P# D2 4 H _ D P W R # _R R1 2 0 * 0_ 0 4
22 H _ NM I L I N T1 B CL K [0 ] H_ CL K _ CP U 2 5 TE S T7 DPW R # H _D P W R # 4
H_ S M I# A3 A 21 C P U_ B S E L 0 B2 2 D6 H _ P W RG D
22 H _S M I # SM I# B CL K [1 ] H_ CL K _ CP U# 2 5 25 C P U _ B S E L0 C P U_ B S E L 1 BSEL [0 ] P W R GO OD H _ CP U S L P # H _P W R G D 4
25 C P U _ B S E L1 B2 3 D7 H _C P U S LP # 2 2
Z 0 2 01 M4 C P U_ B S E L 2 C 21 BSEL [1 ] SL P# AE6 PS I#
Z 0 2 02 R SVD[0 1 ] 25 C P U _ B S E L2 BSEL [2 ] P SI# PSI # 37
N5
Z 0 2 03 T2 R SVD[0 2 ] C P U _G T LR E F F OX C ON N P Z 4 7 8 2A - 27 4 M-0 1
Z 0 2 04 R SVD[0 3 ] Layout Note:
V3
Z 0 2 05 B2 R SVD[0 4 ] R4 0 7 1 K _1 % _ 0 4
C686 Close to TEST4 (Pin AF26)
RESERVED
Z 0 2 06 R SVD[0 5 ] 1. 05 V S
D2
Z 0 2 07 D2 2 R SVD[0 6 ]
56_04 R SVD[0 7 ]
CPU_GRFE=0.7V
Z 0 2 08 D3 C 55 3 C 55 2 R4 0 6
1 .0 5 VS Z 0 2 09 F6 R SVD[0 8 ]
6-14-5603B-11B R SVD[0 9 ]
Layout Note:
1 u _ 6. 3 V _ X 5 R _ 0 6 0 . 0 1u _ 5 0 V _X 7 R _ 0 4 2K _ 1 % _ 04
R 15 0 1 K _ 04 CP U _ B S E L 2
R 45 9 1 K _ 04 CP U _ B S E L 1
0.5" max, Zo= 55 Ohms
R 46 0 1 K _ 04 CP U _ B S E L 0
F OX C O N N P Z 4 7 82 A -2 7 4 M- 0 1
R 14 9 6 8_ 0 4 H _ P R OC H O T# I f PR OCH OT # is r ou te d be tw ee n C PU , IM VP a nd M CH , ( S iS R ec om ma nd ati on 2 00 p) Layout note:

p ul l- up re si st or h as t o be 6 8 o hm ? 5 %. I f no t COMP0, COMP2: 0.5" Max, Zo=27.4 Ohms(20mil)
R 12 5 5 6_ 0 4 H _ T H R MT R I P #
R 13 4 5 6_ 0 4 H_ F E R R# u se , pul l- up r es is to r ha s to be 5 6 oh m ? 5% COMP1, COMP3: 0.5" Max, Zo=55 Ohms(5mil)
R 11 3 5 6_ 0 4 H _ S T P C LK #
R 13 1 5 6_ 0 4 H_ IN IT # Best estimate is 18 mils wide trace for outer
R 11 5 5 6_ 0 4 H_ IG NN E # I F US ED De sk to p CP U, H _C PU RS T#, H_ PW RG D, H_ BR D, ne ed layers and 14 mils wide trace if on internal
R 11 7 5 6_ 0 4 H_ S M I#
R 13 2 5 6_ 0 4 H _ A 2 0 M# a dd p ull h ig h re si st or layers.
R 12 2 5 6_ 0 4 H_ C P US L P #
R 13 0 5 6_ 0 4 H _ N MI C OM P 0
R 11 4 5 6_ 0 4 H _ I N TR C OM P 1
R 12 7 5 6_ 0 4 H_ D P S L P # R1 4 2 *2 0 m i _l s h ort -N MN P C OM P 2
C OM P 3
CPU to SB interface 3 .3 V Q 9 V _T H E R M
*N D S 3 5 2 A P _ N L
S D
R 10 8 *5 1 _ 04 H_ C P UR S T # R7 4 R8 5 R 4 41 R 4 49
R 11 6 *3 3 0 _0 4 H _ P W R GD C1 8 0
*0 . 0 1u _ 1 6V _X 7 R _ 0 4 R 1 35 C 16 3
Thermal IC 5 4. 9_ 1 % _0 4 27 . 4 _ 1 %_ 0 4 5 4 . 9 _ 1% _ 0 4 2 7 . 4 _1 % _ 0 4
G
R 10 6 *5 1 _ 04 H_ B R 0 # Z 02 2 3
* 10 0 K _ 0 4 *0 . 1 u _ 10 V _ X 7 R _ 0 4
Z 02 2 5 R 13 8 1 0K _ 0 4
R 14 7 5 6_ 0 4 H_ IE R R# R 1 52 V _ T HE R M
R 89 5 6_ 0 4 H _ P R E Q# U7 R 13 7 * 10 m i _l s h or t -N M N P
R 73 1 50 _ 1 % _0 4 H_ T DI R1 5 1 * 1 00 K _ 0 4 1 4 T H E R M _A LE R T # 27
R 58 3 9. 2_ 1 % _0 4 H _ T MS *3 3 0 K _ 04 H _ TH E R MD A 2 V DD T HE RM 6 Z 02 2 6 R 15 5 *0 _ 04
H_ D B R# Z 02 2 4 D+ AL ER T
R 14 8 1 50 _ 1 % _0 4
R 11 9 *5 6 _ 04 H_ D P W R# _ R Q 10 C 16 4 R 15 6 *1 0 K _ 04
V D D3
D
* MT N 70 0 2 Z H S 3 1 0 00 p _ 50 V _ X 7 R _ 0 4
I f us ed M6 72 t ha n 3 7
H _ TH E R MD C D- S D A TA S M D_ C P U_ T HE R M 2 7
27 TH E R M_ R S T # G 5 8 S M C_ C P U_ T HE R M 2 7
d el R 40 an d ad d R4 2 GN D S C LK
S
R 11 8 1 0_ 0 4 H_ D P W R# _ R W 83 L 7 71 A W G R 15 8 4 . 7K _ 0 4
V D D3
R 15 7 4 . 7K _ 0 4
C 15 4 1 0 0 p_ 5 0 V _ N P O _ 04
H _ P W R GD Layout Note: Layout Note:
R 65 2 7. 4_ 1 % _0 4 H_ T CK
R 57 6 80 _ 0 4 H _ T R S T#
Route H_THERMDA and Close to Thermal IC
H_THERMDC on same layer. ADM1032 1000p
10 mil trace on 10 mil spacing. F75383M 2200p
Penryn (Socket-P)1/2 B - 3
Schematic Diagrams
Penryn (Socket-P) 2/2
V C OR E
Check cap for santa rosa platform
PLACE NEAR CPU
C5 6 4 C5 7 7 C9 5 C5 6 5 C5 6 8 C 58 0
J S K T 1D
V CO RE V C OR E A4 P6 10 u _ 6 . 3 V _ 0 8 _H 1 2 5 1 0u _ 6 . 3 V _ 0 8 _H 1 2 5 1 0u _ 6 . 3 V _ 0 8 _H 1 2 5 *1 0 u _ 6 . 3V _X 5 R _ 08 1 0 u_ 6 . 3 V _ 0 8 _ H 1 2 5 1 0 u _6 . 3 V _ 0 8 _ H 1 2 5
VS S[0 0 1 ] VSS [ 0 82 ]
J SKT 1 C A8 P2 1
A 7 AB2 0 A1 1 VS S[0 0 2 ] VSS [ 0 83 ] P2 4
A 9 VC C[0 0 1 ] V CC [ 0 6 8] AB7 A1 4 VS S[0 0 3 ] VSS [ 0 84 ] R2
VC C[0 0 2 ] V CC [ 0 6 9] VS S[0 0 4 ] VSS [ 0 85 ]
A1 0 AC 7 A1 6 R5
A1 2 VC C[0 0 3 ] V CC [ 0 7 0] AC 9 A1 9 VS S[0 0 5 ] VSS [ 0 86 ] R2 2 V C OR E
A1 3 VC C[0 0 4 ] V CC [ 0 7 1] AC 1 2 A2 3 VS S[0 0 6 ] VSS [ 0 87 ] R2 5
VC C[0 0 5 ] V CC [ 0 7 2] VS S[0 0 7 ] VSS [ 0 88 ]

A1 5 AC 1 3 AF2 T1
A1 7 VC C[0 0 6 ] V CC [ 0 7 3] AC 1 5 B6 VS S[0 0 8 ] VSS [ 0 89 ] T4
A1 8 VC C[0 0 7 ] V CC [ 0 7 4] AC 1 7 B8 VS S[0 0 9 ] VSS [ 0 90 ] T 23 C5 0 C6 5 C1 2 3 C6 1 C5 9 3 C 59 4
VC C[0 0 8 ] V CC [ 0 7 5] VS S[0 1 0 ] VSS [ 0 91 ]
A2 0 AC 1 8 B1 1 T 26
B 7 VC C[0 0 9 ] V CC [ 0 7 6] AD 7 B1 3 VS S[0 1 1 ] VSS [ 0 92 ] U3 10 u _ 6 . 3 V _ 0 8 _H 1 2 5 1 0u _ 6 . 3 V _ 0 8 _H 1 2 5 *1 0 u _ 6. 3V _X 5 R _ 08 1 0 u_ 6 . 3 V _ 0 8 _ H 1 2 5 1 0 u_ 6 . 3 V _ 0 8 _ H 1 2 5 *1 0 u _ 6 . 3 V _ X5 R _ 0 8
B 9 VC C[0 1 0 ] V CC [ 0 7 7] AD 9 B1 6 VS S[0 1 2 ] VSS [ 0 93 ] U6
VC C[0 1 1 ] V CC [ 0 7 8] VS S[0 1 3 ] VSS [ 0 94 ]
B1 0 AD 1 0 B1 9 U2 1
VC C[0 1 2 ] V CC [ 0 7 9] VS S[0 1 4 ] VSS [ 0 95 ]
B1 2 AD 1 2 B2 1 U2 4
B1 4 VC C[0 1 3 ] V CC [ 0 8 0] AD 1 4 B2 4 VS S[0 1 5 ] VSS [ 0 96 ] V2
VC C[0 1 4 ] V CC [ 0 8 1] VS S[0 1 6 ] VSS [ 0 97 ] V C OR E
B1 5 AD 1 5 C 5 V5
VC C[0 1 5 ] V CC [ 0 8 2] VS S[0 1 7 ] VSS [ 0 98 ]
B1 7 AD 1 7 C 8 V2 2
Sheet 3 of 50 B1 8 VC C[0 1 6 ] V CC [ 0 8 3] AD 1 8 C1 1 VS S[0 1 8 ] VSS [ 0 99 ] V2 5

6-07-10611-7C0
VC C[0 1 7 ] V CC [ 0 8 4] VS S[0 1 9 ] VSS [ 1 00 ]
B2 0 AE9 C1 4 W1
VC C[0 1 8 ] V CC [ 0 8 5] VS S[0 2 0 ] VSS [ 1 01 ]
C 9 AE1 0 C1 6 W4 C5 9 C5 7 5 C1 1 8 C5 6 6 C1 4 6 C 12 9
C 10 VC C[0 1 9 ] V CC [ 0 8 6] AE1 2 C1 9 VS S[0 2 1 ] VSS [ 1 02 ] W23
VC C[0 2 0 ] V CC [ 0 8 7] VS S[0 2 2 ] VSS [ 1 03 ]
C 12 AE1 3 C 2 W26 10 u _ 6 . 3 V _ 0 8 _H 1 2 5 1 0u _ 6 . 3 V _ 0 8 _H 1 2 5 1 0u _ 6 . 3 V _ 0 8 _H 1 2 5 1 0 u_ 6 . 3 V _ 0 8 _ H 1 2 5 1 0 u_ 6 . 3 V _ 0 8 _ H 1 2 5 1 0 u _6 . 3 V _ 0 8 _ H 1 2 5
Penryn (Socket-P) C 13
C 15
C 17
C 18
VC
VC
VC
VC
C[0 2 1 ]
C[0 2 2 ]
C[0 2 3 ]
C[0 2 4 ]
V
V
V
V
CC
CC
CC
CC
[ 0 8 8]
[ 0 8 9]
[ 0 9 0]
[ 0 9 1]
AE1 5
AE1 7
AE1 8
AE2 0
C2 2
C2 5
D 1
D 4
VS
VS
VS
VS
S[0 2 3 ]
S[0 2 4 ]
S[0 2 5 ]
S[0 2 6 ]
VSS
VSS
VSS
VSS
[ 1 04 ]
[ 1 05 ]
[ 1 06 ]
[ 1 07 ]
Y3
Y6
Y2 1
Y2 4
VC C[0 2 5 ] V CC [ 0 9 2] VS S[0 2 7 ] VSS [ 1 08 ]
2/2
D 9 AF9 D 8 AA2 V C OR E
D 10 VC C[0 2 6 ] V CC [ 0 9 3] AF1 0 D1 1 VS S[0 2 8 ] VSS [ 1 09 ] AA5
VC C[0 2 7 ] V CC [ 0 9 4] VS S[0 2 9 ] VSS [ 1 10 ]
D 12 AF1 2 D1 3 AA8
D 14 VC C[0 2 8 ] V CC [ 0 9 5] AF1 4 D1 6 VS S[0 3 0 ] VSS [ 1 11 ] AA1 1
D 15 VC C[0 2 9 ] V CC [ 0 9 6] AF1 5 D1 9 VS S[0 3 1 ] VSS [ 1 12 ] AA1 4 C5 8 4 C1 2 4 C1 2 8 C4 9 C5 1 C 75
VC C[0 3 0 ] V CC [ 0 9 7] VS S[0 3 2 ] VSS [ 1 13 ]
D 17 AF1 7 D2 3 AA1 6
D 18 VC C[0 3 1 ] V CC [ 0 9 8] AF1 8 D2 6 VS S[0 3 3 ] VSS [ 1 14 ] AA1 9 1u _ 6 . 3 V _ X 5 R _ 0 6 *1 u _ 6 . 3V _ X5 R _ 06 1 u_ 6 . 3 V _ X 5 R _ 0 6 1 u _6 . 3 V _ X 5 R _ 0 6 1 u _6 . 3 V _ X 5 R _ 0 6 1 u _ 6. 3 V _ X 5 R _0 6
E 7 VC C[0 3 2 ] V CC [ 0 9 9] AF2 0 E3 VS S[0 3 4 ] VSS [ 1 15 ] AA2 2
E 9
VC C[0 3 3 ] V CC [ 1 0 0] P ower Plane 2A E6
VS S[0 3 5 ] VSS [ 1 16 ]
AA2 5
VC C[0 3 4 ] VS S[0 3 6 ] VSS [ 1 17 ]
E1 0 G 21 1 .0 5 VS E8 AB1
E1 2 VC C[0 3 5 ] VC CP [ 0 1] V6 E1 1 VS S[0 3 7 ] VSS [ 1 18 ] AB4
VC C[0 3 6 ] VC CP [ 0 2] VS S[0 3 8 ] VSS [ 1 19 ] V C OR E
E1 3 J6 E1 4 AB8
VC C[0 3 7 ] VC CP [ 0 3] VS S[0 3 9 ] VSS [ 1 20 ]
E1 5 K6 E1 6 AB1 1
E1 7 VC C[0 3 8 ] VC CP [ 0 4] M6 E1 9 VS S[0 4 0 ] VSS [ 1 21 ] AB1 3
VC C[0 3 9 ] VC CP [ 0 5] VS S[0 4 1 ] VSS [ 1 22 ]
E1 8 J21 E2 1 AB1 6
VC C[0 4 0 ] VC CP [ 0 6] VS S[0 4 2 ] VSS [ 1 23 ]
E2 0 K2 1 E2 4 AB1 9 C1 1 3 C1 0 0 C8 8 C5 8 5 C6 8 C 14 0
F 7 VC C[0 4 1 ] VC CP [ 0 7] M 21 F5 VS S[0 4 3 ] VSS [ 1 24 ] AB2 3
VC C[0 4 2 ] VC CP [ 0 8] Layout note: VS S[0 4 4 ] VSS [ 1 25 ]
F 9 N 21 Near pin B26 F8 AB2 6 1u _ 6 . 3 V _ X 5 R _ 0 6 1 u_ 6 . 3 V _ X 5 R _ 0 6 *1 u _ 6 . 3 V _ X5 R _ 0 6 1 u _6 . 3 V _ X 5 R _ 0 6 1 u _6 . 3 V _ X 5 R _ 0 6 1 u _ 6. 3 V _ X 5 R _0 6
VC C[0 4 3 ] VC CP [ 0 9] VS S[0 4 5 ] VSS [ 1 26 ]
F10 N 6 F11 AC 3
F12 VC C[0 4 4 ] VC CP [ 1 0] R 21 L1 2 F13 VS S[0 4 6 ] VSS [ 1 27 ] AC 6
F14 VC C[0 4 5 ] VC CP [ 1 1] R 6 H C B 1 6 08 K F - 1 21 T 2 5 F16 VS S[0 4 7 ] VSS [ 1 28 ] AC 8
F15
VC C[0 4 6 ] VC CP [ 1 2]
T21 130mA 1 .5 VS F19
VS S[0 4 8 ] VSS [ 1 29 ]
A C 11
F17 VC C[0 4 7 ] VC CP [ 1 3] T6 F2 VS S[0 4 9 ] VSS [ 1 30 ] A C 14 V C OR E
F18 VC C[0 4 8 ] VC CP [ 1 4] V2 1 C 846 C1 5 9 C 1 61 F22 VS S[0 5 0 ] VSS [ 1 31 ] A C 16
VC C[0 4 9 ] VC CP [ 1 5] VS S[0 5 1 ] VSS [ 1 32 ]
F20 W21 0 . 0 1 u _ 50 V _ X 7 R _ 0 4 F25 A C 19
AA 7 VC C[0 5 0 ] VC CP [ 1 6] *1 0 u _6 . 3 V _ X 5 R _ 0 8 G4 VS S[0 5 2 ] VSS [ 1 33 ] A C 21
AA 9 VC C[0 5 1 ] B2 6 Z 0 30 1 1 u_ 6 . 3 V _ X 5 R _ 0 6 G1 VS S[0 5 3 ] VSS [ 1 34 ] A C 24 C5 8 3 C8 5 C5 7 2 C5 8 1 C5 8 2 C 15 5
VC C[0 5 2 ] V C C A [ 0 1] VS S[0 5 4 ] VSS [ 1 35 ]
A A1 0 C 26 G2 3 AD 2
A A1 2 VC C[0 5 3 ] V C C A [ 0 2] G2 6 VS S[0 5 5 ] VSS [ 1 36 ] AD 5 0. 1u _ 1 0 V _ X 7 R _ 0 4 0 . 1 u_ 1 0 V _ X 7 R _ 0 4 0 . 1 u_ 1 0 V _ X 7 R _ 0 4 0 . 1 u_ 1 0 V _ X 7 R _ 0 4 0 . 1 u _1 0 V _ X 7 R _ 0 4 0 . 1 u _1 0 V _ X 7 R _ 0 4
A A1 3 VC C[0 5 4 ] AD 6 H_ V ID 0 H 3 VS S[0 5 6 ] VSS [ 1 37 ] AD 8
VC C[0 5 5 ] VID [ 0] H_ V ID 1 VS S[0 5 7 ] VSS [ 1 38 ]
A A1 5 AF5 H 6 A D 11
A A1 7 AE5 H2 1 A D 13
A A1 8 VC C[0 5 7 ] VID [ 2] AF4 H_ V ID 3 H2 4 VS S[0 5 9 ] VSS [ 1 40 ] A D 16
A A2 0 AE3 J2 A D 19
AB 9 AF3 J5 A D 22
AC 1 0 VC C[0 6 0 ] VID [ 5] AE2 H_ V ID 6 J22 VS S[0 6 2 ] VSS [ 1 43 ] A D 25
A B1 0
VC C[0 6 1 ] VID [ 6] H_ V ID[6 :0 ] 3 7
J25
VS S[0 6 3 ] VSS [ 1 44 ]
AE1
PLACE NEAR CPU
VC C[0 6 2 ] VS S[0 6 4 ] VSS [ 1 45 ]
A B1 2 K1 AE4
A B1 4 VC C[0 6 3 ] AF7 V C CS E NS E K4 VS S[0 6 5 ] VSS [ 1 46 ] AE8
VC C[0 6 4 ] V C CS E NS E VC C SEN SE 3 7 VS S[0 6 6 ] VSS [ 1 47 ] 1 .0 5 VS
A B1 5 K2 3 AE1 1
VC C[0 6 5 ] VS S[0 6 7 ] VSS [ 1 48 ]
A B1 7 K2 6 AE1 4
A B1 8 VC C[0 6 6 ] AE7 VSS SEN SE L3 VS S[0 6 8 ] VSS [ 1 49 ] AE1 6
VC C[0 6 7 ] V SSS E NSE VS SSEN SE 3 7 VS S[0 6 9 ] VSS [ 1 50 ]
L6 AE1 9
VS S[0 7 0 ] VSS [ 1 51 ]
F O X C O N N P Z 4 7 8 2 A -2 7 4 M-0 1 L21 AE2 3 C5 7 4 C8 6 C1 1 1 C4 6 C6 2
L24 VS S[0 7 1 ] VSS [ 1 52 ] AE2 6 +
.
R 21 R2 2 M2 VS S[0 7 2 ] VSS [ 1 53 ] A2 15 0 u _ 4 V _ B _ A 0 . 1 u_ 1 0 V _ X 7 R _ 0 4 0 . 1 u_ 1 0 V _ X 7 R _ 0 4 0 . 1 u_ 1 0 V _ X 7 R _ 0 4 0 . 1 u _1 0 V _ X 7 R _ 0 4
Layout note: VS S[0 7 3 ] VSS [ 1 54 ]
M5 AF 6
*1 5 m i l_ s h o rt -N MN*1P5 m il _ s h or t -N M N P M2 2 VS S[0 7 4 ] VSS [ 1 55 ] AF 8
Route VCCSENSE and
M2 5 VS S[0 7 5 ] VSS [ 1 56 ] AF 1 1 5/10
VSSSENSE traces at 27.4 VS S[0 7 6 ] VSS [ 1 57 ] 1 .0 5 VS
N 1 AF 1 3
VC O RE N 4 VS S[0 7 7 ] VSS [ 1 58 ] AF 1 6
ohms with 50 mils spacing.
N2 3 VS S[0 7 8 ] VSS [ 1 59 ] AF 1 9
Place PU and PD within 1 VS S[0 7 9 ] VSS [ 1 60 ]
N2 6 AF 2 1
inch of CPU. P3 VS S[0 8 0 ] VSS [ 1 61 ] A2 5 C1 2 6 C1 1 6 C7 7 C1 4 1 C1 3 0 C 67
VS S[0 8 1 ] VSS [ 1 62 ] AF 2 5
VSS [ 1 63 ]
0. 1u _ 1 0 V _ X 7 R _ 0 4 0 . 1 u_ 1 0 V _ X 7 R _ 0 4 0 . 1 u_ 1 0 V _ X 7 R _ 0 4 0 . 1 u_ 1 0 V _ X 7 R _ 0 4 *0 . 1 u _ 1 0 V _ X7 R _ 04 0 . 1 u _1 0 V _ X 7 R _ 0 4
F OX C ON N P Z 4 7 82 A - 27 4 M -0 1
.
B - 4 Penryn (Socket-P) 2/2

Schematic Diagrams
SiS671DX - Host, PCIE 1/5
R 1 96 *5 6 _ 04 N B _ P C R E Q#
1. 0 5 V S
U3 2 C 1 .2 VS N B _ P C I E _1 . 2 V S
B1 6 N 29 H _D #0 H_ D# [6 3 :0 ] 2 L 23
C 1 XA V D D C1 X A V DD HD0 # H _D #1
C 17 M 30 H C B 1 0 0 5K F -1 21 T 2 0
C 1X A V S S C1 X A V S S HD1 #
HD2 #
M 28 H _D #2 77mA
A1 7 L30 H _D #3 U3 2 D
C 4 XA V D D B1 8 C4 X A V DD HD3 # L29 H _D #4 C2 6 0 C2 6 2 P7
C 4X A V S S C4 X A V S S HD4 # PC IE AVD D
K2 8 H _D #5 R7 T5
W24 HD5 # K3 1 H _D #6 0. 0 1 u _5 0 V _ X 7R _ 04 0 . 1u _ 1 0V _X 7 R _ 0 4 T7 PC IE AVD D R EF CL K + T4 P C I E _ C L K _ N B 25
N B _ G TL R E F HV R EF HD6 # PC IE AVD D RE F CL K - P C IE _ CL K _ NB # 2 5
U 24 K3 0 H _D #7 U7
R 24 HV R EF HD7 # H 31 H _D #8 V7 PC IE AVD D
HV R EF HD8 # PC IE AVD D
INTERNAL VGA( M740S ) : R
N 24 G 34 H _D #9
HV R EF HD9 # H _D # 10
L21 H 32 23 , 3 3 P C I E _W A K E # D7 EXTERNAL VGA ( W760SU ) : 0.1U
HV R EF H D 10 # G 32 H _D # 11 G 16 PM E#
H D 11 # H _D # 12 6, 2 1 P C I_ INT # A I N T X#
K3 2
N B _ P C R E Q# R 34 H D 12 # F3 4 H _D # 13 E4 G6 Z 0 4 3 8 C6 1 6 0 . 1 u_ 1 0 V _ X7 R _0 4
P C R E Q# H D 13 # 12 P E0 RX0 PE RP 0 PETP0 PE 0T X 0 12
Z04 01 P3 2 F3 3 H _D # 14 E5 H 6 Z 0 4 3 9 C6 1 8 0 . 1 u_ 1 0 V _ X7 R _0 4
E DR DY # H D 14 # 12 P E0 RX0 # PE RN0 P E T N0 PE 0T X 0 # 12
F3 2 H _D # 15 F1 G4 Z 0 4 4 0 C6 1 5 0 . 1 u_ 1 0 V _ X7 R _0 4
H D 15 # H _D # 16 12 P E0 RX1 PE RP 1 PETP1 Z 0 4 4 1 C6 1 7 PE 0T X 1 12
2 H_ DP W R# E2 1 H 28 12 P E0 RX1 # G1 G5 0 . 1 u_ 1 0 V _ X7 R _0 4 PE 0T X 1 # 12
N C 2 (D P W R #) H D 16 # J30 H _D # 17 H3 PE RN1 P E T N1 J6 Z 0 4 4 2 C6 2 0 0 . 1 u_ 1 0 V _ X7 R _0 4
H 30 12 P E0 RX2 # H2 K6 0 . 1 u_ 1 0 V _ X7 R _0 4 PE 0T X 2 # 12
PCIE
F18 H D 18 # G 29 H _D # 19 H1 PE RN2 P E T N2 J4 Z 0 4 4 4 C6 1 9 0 . 1 u_ 1 0 V _ X7 R _0 4
25 H _ C LK _ N B CP U CL K H D 19 # H _D # 20 12 P E0 RX3 PE RP 3 PETP3 Z 0 4 4 5 C6 2 1 PE 0T X 3 12
25 H_ CL K _ N B # G 18 J29 12 P E0 RX3 # J1 J5 0 . 1 u_ 1 0 V _ X7 R _0 4 PE 0T X 3 # 12
CP U CL K # H D 20 # G 30 H _D # 21 K1 PE RN3 P E T N3 L6 Z 0 4 4 6 C6 2 3 0 . 1 u_ 1 0 V _ X7 R _0 4
L32 F3 0 12 P E0 RX4 # K2 M6 0 . 1 u_ 1 0 V _ X7 R _0 4
Sheet 4 of 50
2 H _ L OC K # P3 0 H L OC K # H D 22 # D 33 H _D # 23 L1 PE RN4 P E T N4 M4 Z 0 4 4 8 C6 2 5 0 . 1 u_ 1 0 V _ X7 R _0 4 PE 0T X 4 # 12
2 H _D E F E R # DE F E R # H D 23 # H _D # 24 12 P E0 RX5 PE RP 5 PETP5 Z 0 4 4 9 C6 2 7 PE 0T X 5 12
P3 1 D 34 12 P E0 RX5 # M1 M5 0 . 1 u_ 1 0 V _ X7 R _0 4
2 H _ TR D Y # F21 HT RD Y # H D 24 # B3 2 H _D # 25 N1 PE RN5 P E T N5 P6 Z 0 4 5 0 C6 2 8 0 . 1 u_ 1 0 V _ X7 R _0 4 PE 0T X 5 # 12
2 H _C P U R S T # CP U RS T # H D 25 # H _D # 26 12 P E0 RX6 PE RP 6 PETP6 Z 0 4 5 1 C6 3 0 PE 0T X 6 12
P2 8 B3 3 12 P E0 RX6 # N2 R 6 0 . 1 u_ 1 0 V _ X7 R _0 4
2 H _ P W R GD N 30 CP U P W RG D H D 26 # C 34 H _D # 27 P1 PE RN6 P E T N6 P4 Z 0 4 5 2 C6 2 9 0 . 1 u_ 1 0 V _ X7 R _0 4 PE 0T X 6 # 12
2 H_ B P R I# BPRI# H D 27 # 12 P E0 RX7 PE RP 7 PETP7 PE 0T X 7 12
2
2
2
H _B R 0 #
H _R S # 0
H _R S # 1
P3 3
K3 4
M 31
K3 3
B RE Q 0 #
RS 0 #
RS 1 #
H D 28 #
H D 29 #
H D 30 #
H D 31 #
D 31
A3 2
A3 1
C 31
B3 0
H
H
H
H
H
_D
_D
_D
_D
_D
# 28
# 29
# 30
# 31
# 32
12 P E0 RX7 #
Z 04 0 2
Z 04 0 3
Z 04 0 4
Z 04 0 5
R1
T1
T2
U1
V1
PE
PE
PE
PE
RN7
RP 8
RN8
RP 9
P E T N7
PETP8
P E T N8
P E T P 9 (H D V B P 2 )
P5
V6
W6
W4
W5
Z 0 4 5 3 C6 3 1
Z0454
Z0455
0 . 1 u_ 1 0 V _ X7 R _0 4
PE 0T X 7 #
HD V BP 2
12
11
SiS671DX - Host,
2 H _R S # 2 RS 2 # H D 32 # PE RN9 P E TN 9 (H D V B N 2 ) HDV B N2 11
PCIE 1/5
C 30 H _D # 33 Z 04 0 6 W1 Y 6
H D 33 # PE RP 1 0 P E TP 1 0 (H D V B P 1 ) HD V BP 1 11
M 34 A3 0 H _D # 34 Z 04 0 7 W2 AA 6
2 H _A D S # A DS # H D 34 # H _D # 35 Z 04 0 8 PE RN1 0 P E T N 1 0 (H D V B N 1 ) HDV B N1 11
2 H_ HIT M # N 34 D 28 Y1 AA 4 HD V BP 0 11
N 32 H I T M# H D 35 # G 28 H _D # 36 Z 04 0 9 AA1 PE RP 1 1 P E TP 1 1 (H D V B P 0 ) AA 5
2 H_ HI T # HIT # H D 36 # H _D # 37 Z 04 1 0 PE RN1 1 P E T N 1 1 (H D V B N 0 ) Z0462 HDV B N0 11
2 H_ DR DY # M 33 C 29 AB1 AB 6
L34 DR DY # H D 37 # C 28 H _D # 38 Z 04 1 1 AB2 PE RP 1 2 P E TP 12 AC 6 Z0463
2 H _ DBSY # DB S Y # H D 38 # H _D # 39 Z 04 1 2 PE RN1 2 P E T N 12
2 H _ B NR # M 32 E2 8 A C1 AC 4 HD V AP 2 11
B NR # H D 39 # E2 7 H _D # 40 Z 04 1 3 A D1 PE RP 1 3 P E TP 1 3 (H D V A P 2 ) AC 5
2 H _R E Q# [ 4 : 0 ] H_ R E Q# 0 H D 40 # H _D # 41 Z 04 1 4 PE RN1 3 P E T N 1 3 (H D V A N 2 ) HDV A N2 11
T34 C 27 AE1 AD 6 HD V AP 1 11
H_ R E Q# 1 R 30 HR E Q0 # H D 41 # G 26 H _D # 42 Z 04 1 5 AE2 PE RP 1 4 P E TP 1 4 (H D V A P 1 ) AE 6
H_ R E Q# 2 R 29
HR
HR
E Q1 #
E Q2 #
Host H D 42 #
H D 43 #
E2 6 H _D # 43 Z 04 1 6 AF1
PE
PE
RN1 4
RP 1 5
P E T N 1 4 (H D V A N 1 )
P E TP 1 5 (H D V A P 0 )
AE 4
HDV A N1
HD V AP 0
11
11
H_ R E Q# 3 R 32 D 26 H _D # 44 Z 04 1 7 A G1 AE 5
H_ R E Q# 4 HR E Q3 # H D 44 # H _D # 45 PE RN1 5 P E T N 1 5 (H D V A N 0 ) HDV A N0 11
P3 4 B2 6
HR E Q4 # H D 45 # A2 6 H _D # 46 SS
i 6 7 1 DX
H D 46 # H _D # 47
C 26
U 34 H D 47 # G 22 H _D # 48
2 H _ A DS T B # 0 HA S T B 0 # H D 48 # H _D # 49
AA3 4 C 24
2 H _ A DS T B # 1 HA S T B 1 # H D 49 # A2 5 H _D # 50
2 H _ A # [ 3 5 : 3] H D 50 #
H_ A# 3 T32 B2 4 H _D # 51
H_ A# 4 T28 HA 3 # H D 51 # C 25 H _D # 52
H_ A# 5 T31 HA 4 # H D 52 # A2 4 H _D # 53
H_ A# 6 T33 HA 5 # H D 53 # E2 3 H _D # 54
H_ A# 7 T30 HA 6 # H D 54 # E2 5 H _D # 55
H_ A# 8 U 32 HA 7 # H D 55 # G 24 H _D # 56
H_ A# 9 U 30 HA 8 # H D 56 # D 22 H _D # 57
H_ A# 1 0 HA 9 # H D 57 # H _D # 58
V3 4 C 22
H_ A# 1 1 U 29 HA 1 0 # H D 58 # E2 2 H _D # 59
H_ A# 1 2 HA 1 1 # H D 59 # H _D # 60
V3 3 C 23
H_ A# 1 3 V3 2 HA 1 2 # H D 60 # A2 3 H _D # 61
H_ A# 1 4 HA 1 3 # H D 61 # H _D # 62
V2 8 A2 2
H_ A# 1 5 V3 1 HA 1 4 # H D 62 # B2 2 H _D # 63
H_ A# 1 6 HA 1 5 # H D 63 #
W34
H_ A# 1 7 Y 33 HA 1 6 #
H_ A# 1 8 HA 1 7 #
W32 J32 H _D I N V #0 2
H_ A# 1 9 V3 0 HA 1 8 # DB I0 # E3 2
H_ A# 2 0 HA 1 9 # DB I1 # H _D I N V #1 2
W30 F2 7 H _D I N V #2 2
H_ A# 2 1 Y 34 HA 2 0 # DB I2 # F2 3
H_ A# 2 2 HA 2 1 # DB I3 # H _D I N V #3 2
Y 28
H_ A# 2 3 W29 HA 2 2 # H 33
H_ A# 2 4 HA 2 3 # H DS T B N0 # H _D S T B N # 0 2
Y 32 E3 1
H_ A# 2 5 Y 30 HA 2 4 # H DS T B N1 # B2 8 H _D S T B N # 1 2
HA 2 5 # H DS T B N2 # H _D S T B N # 2 2
H_ A# 2 6 Y 31 D 24
H_ A# 2 7 AA3 2 HA 2 6 # H DS T B N3 # H _D S T B N # 3 2
HA 2 7 #
H_ A# 2 8 AA3 0 H 34
H_ A# 2 9 AA2 9 HA 2 8 # H DS T B P 0 # D 32 H _D S T B P # 0 2
HA 2 9 # H DS T B P 1 # H _D S T B P # 1 2
H_ A# 3 0 AB3 3 A2 8
H_ A# 3 1 AB3 4 HA 3 0 # H DS T B P 2 # E2 4 H _D S T B P # 2 2
HA 3 1 # H DS T B P 3 # H _D S T B P # 3 2
H_ A# 3 2 AB3 2
H_ A# 3 3 HA 3 2 # N B _C OM P
AC 3 4 A2 1 R1 7 8 11 0 _ 1% _ 0 6
H_ A# 3 4 AB3 0 HA 3 3 # H P C OM P C 21 N B _C OM P #
H_ A# 3 5 HA 3 4 # H N C OM P
AB3 1
HA 3 5 # R1 8 3 10 _ 1 % _0 4 1. 0 5 V S
1 . 0 5V S
S i S 6 71 D X
R 1 95 C2 6 4
1 .8 V S C 1 XA V D D 1 .8 VS C 4 XA V D D 7 5 _ 1 %_ 0 4 0. 0 1 u _5 0 V _ X 7R _ 04
NB_GTLREF=0.7V
L 65 H C B 1 0 05 K F -1 2 1 T2 0 L1 8 H C B 1 00 5 K F - 1 2 1T 2 0
N B _G T LR E F
C 5 98 C 60 5 C6 0 6 C 21 0 C2 3 0 C2 4 0 R 1 92 C2 7 3 C2 5 5
* 10 u _ 1 0V _ Y 5V _ 0 8 0 . 1 u_ 1 0 V _ X7 R _0 4 0 . 01 u _ 50 V _ X 7 R _ 0 4 1 0 u_ 1 0 V _ Y 5 V _ 08 0 . 1u _ 1 0V _X 7 R _ 0 4 0. 0 1 u _5 0 V _ X 7R _ 04 1 5 0 _ 1% _ 0 4 0. 0 1 u _5 0 V _ X 7R _ 04 0 . 1u _ 1 0V _X 7 R _ 0 4
D05 10/15
N C1 0 N C_ 0 4 N C2 N C_ 0 4
Place under M671MX

C1 X AVS S C4 X A V S S
solder side
SiS671DX - Host, PCIE 1/5 B - 5

Schematic Diagrams
SiS671DX - DRAM 2/5
U 32B
9, 1 0 M _ A _ D Q [ 6 3 : 0 ]
M_ A _ D Q0 A D3 1
M_ A _ D Q1 M D0 A
A D3 0
M_ A _ D Q2 A G3 4 M D1 A A1 5
M D2 A D1 X A V D D D 1 XAVD D
M_ A _ D Q3 AE2 9 B1 5
M_ A _ D Q4 M D3 A D1 XA VSS D 1 XA V S S
AE3 2
1 .8 V S D 1 XAVD D M_ A _ D Q5 AF3 4 M D4 A AP1 1
M D5 A D4 X A V D D D 4 XAVD D
M_ A _ D Q6 AF3 1 AP1 0
M_ A _ D Q7 M D6 A D4 XA VSS D 4 XA V S S
L64 H C B 1 00 5 K F -12 1 T 2 0 AE3 0
A D2 8 M D7 A
9 ,1 0 M _ DM 0 D QM 0 A
AF3 2
9 ,1 0 M _ DQ S 0 D QS 0A
C5 9 7 C 6 11 C 6 12 AF3 3
9 ,1 0 M_ D QS 0 # D QS 0A #
9, 1 0 M _ A _ D Q [ 6 3 : 0 ] M _ A _ A [ 1 7 : 0] 9 ,1 0
1 0u _ 1 0 V _ Y 5 V _ 0 8 0 . 1 u _ 10 V _ X 7 R _ 0 4 0 . 0 1 u _5 0 V _ X 7 R _ 0 4 M_ A _ D Q8 AF2 8 AH 2 4 M _ A_ A0
M_ A _ D Q9 M D8 A MA 0A M _ A_ A1
AJ 3 4 AP2 5
NC 1 2 NC _ 0 4 M_ A _ D Q1 0 A H3 1 M D9 A MA 1A AM 2 5 M _ A_ A2
M D1 0 A MA 2A
M_ A _ D Q1 1 A G3 0 AL 2 5 M _ A_ A3
M_ A _ D Q1 2 M D1 1 A MA 3A M _ A_ A4
AF3 0 AP2 6
D1 X A V S S M_ A _ D Q1 3 A G3 2 M D1 2 A MA 4A AM 2 6 M _ A_ A5
M_ A _ D Q1 4 AJ 3 2 M D1 3 A MA 5A AN 2 6 M _ A_ A6
M_ A _ D Q1 5 M D1 4 A MA 6A M _ A_ A7
AJ 3 1 AK2 5
A H3 4 M D1 5 A MA 7A AP2 7 M _ A_ A8
9 ,1 0 M _ DM 1 D QM 1 A MA 8A
A H3 2 AP2 8 M _ A_ A9
1 .8 V S D 4 XAVD D 9 ,1 0 M _ DQ S 1 D QS 1A MA 9A M _ A_ A1 0
A H3 3 AK2 4
9 ,1 0 M_ D QS 1 # D QS 1A # M A 1 0A AN 2 4 M _ A_ A1 1
9, 1 0 M _ A _ D Q [ 6 3 : 0 ] M A 1 1A
L67 H C B 1 00 5 K F -12 1 T 2 0 M_ A _ D Q1 6 AK3 4 AP2 4 M _ A_ A1 2
M_ A _ D Q1 7 M D1 6 A M A 1 2A M _ A_ A1 3
A H3 0 AM 2 8
M_ A _ D Q1 8 AL 3 2 M D1 7 A M A 1 3A AM 2 7 M _ A_ A1 4
Sheet 5 of 50 C6 5 6
*1 0 u _ 10 V _ Y 5 V _ 0 8
C 6 58
0 . 1 u _ 10 V _ X 7 R _ 0 4
C 6 55
0 . 0 1 u _5 0 V _ X 7 R _ 0 4
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
Q1 9
Q2 0
Q2 1
Q2 2
A M3 3
AK3 2
A G2 9
A M3 4
M
M
M
M
D1 8 A
D1 9 A
D2 0 A
D2 1 A
DRAM M A 1 4A
M A 1 5A
M A 1 6A
M A 1 7A
AN 2 8
AP2 1
AP2 9
M
M
M
_ A_ A1 5
_ A_ A1 6
_ A_ A1 7
M _ F W D S DC L K O A _ D C2 9 1 * 10 p _ 5 0 V _ N P O _ 0 4
M D2 2 A
SiS671DX - DRAM
NC 1 3 NC _ 0 4 M_ A _ D Q2 3 AL 3 1 AM 2 3
M D2 3 A RA S A # M_ R A S # 9 ,1 0 M _ F W D S DC L K O A _ D#
9 ,1 0 M _ DM 2 AJ 3 0 AP2 2 M_ C A S # 9 ,1 0 C2 9 0 * 10 p _ 5 0 V _ N P O _ 0 4
AK3 3 D QM 2 A CA S A # AJ 2 3
9 ,1 0 M _ DQ S 2 D QS 2A W E A# M_ W E # 9 ,1 0
D4 X A V S S AL 3 4
9 ,1 0 M_ D QS 2 #
9, 1 0 M _ A _ D Q [ 6 3 : 0 ]
D QS 2A # ? ? ? ?
2/5 1 .8 V
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
Q2 4
Q2 5
Q2 6
Q2 7
A M3 2
AP3 2
AP3 1
A M2 9
M
M
M
M
D2 4 A
D2 5 A
D2 6 A
D2 7 A
F W D S D C L K OA
F W D S DC L K O A #
AK1 2
AH 1 2
M_ F W D S D C LK OA _ D _ R
M_ F W D S D C LK OA _ D # _R
R2 2 0
R2 1 9
* 1 0 mi l _ s ho rt - N M N
_P
* 1 0 mi l _ s ho rt - N M N
_P
F W D S DC L K O A _ D
F W D S DC L K O A _ D#
M_ F W D S D C LK OA _ D 2 5
M_ F W D S D C LK OA _ D # 2 5
M_ A _ D Q2 8 AK3 0
M_ A _ D Q2 9 M D2 8 A
AK2 9 AP2 3 M_ C S 0 # 9 ,1 0
M_ A _ D Q3 0 AJ 2 7 M D2 9 A C S0 A# AH 2 2
M D3 0 A C S1 A# M_ C S 1 # 9 ,1 0
M_ A _ D Q3 1 AK2 8 AM 2 2 Place close to
M D3 1 A C S2 A# M_ C S 2 # 10
R2 0 7 C2 8 9 9 ,1 0 M _ DM 3 A N3 2 AM 2 1 M_ C S 3 # 10
A M3 0 D QM 3 A C S3 A# M671MX
9 ,1 0 M _ DQ S 3 D QS 3A
1 K _ 1% _ 0 4 0 . 1 u_ 1 0 V _ X 7 R _ 0 4 A M3 1
9 ,1 0 M_ D QS 3 # D QS 3A #
M_DDRVREF=0.9V 9, 1 0 M _ A _ D Q [ 6 3 : 0 ] AK2 2 M_ O D T 0 9 ,1 0
M_ A _ D Q3 2 AK2 0 OD T 0A AP2 0
M_ D D R V R E F M D3 2 A OD T 1A M_ O D T 1 9 ,1 0
M_ A _ D Q3 3 A M2 0 AN 2 2
M_ A _ D Q3 4 M D3 3 A OD T 2A M_ O D T 2 10
A M1 9 AL 2 1 M_ O D T 3 10
R2 0 8 C2 8 8 C 287 M_ A _ D Q3 5 AJ 1 9 M D3 4 A OD T 3A
M D3 5 A
M_ A _ D Q3 6 A N2 0
M_ A _ D Q3 7 M D3 6 A
1 K _ 1% _ 0 4 0 . 1 u_ 1 0 V _ X 7 R _ 0 4 0 . 1 u _ 1 0 V _ X7 R _ 04 AJ 2 1 AN 3 0 M_ C K E 0 9 ,1 0
M_ A _ D Q3 8 AP1 9 M D3 7 A CK E A 0 AP3 0
M D3 8 A CK E A 1 M_ C K E 1 9 ,1 0 1 . 8V
M_ A _ D Q3 9 A H2 0 AH 2 6
M D3 9 A CK E A 2 M_ C K E 2 10
9 ,1 0 M _ DM 4 AK2 1 AK2 7 M_ C K E 3 10
AK1 9 D QM 4 A CK E A 3 M _ C O MP _ N R 20 5 3 6_ 1 % _ 0 6
Place under M671MX 9 ,1 0 M _ DQ S 4 D QS 4A
AL 1 9
solder side 9 ,1 0 M_ D QS 4 # D QS 4A #
9, 1 0 M _ A _ D Q [ 6 3 : 0 ]
M_ A _ D Q4 0 AK1 8 M _ C O MP _ P R 21 3 3 6_ 1 % _ 0 6
M_ A _ D Q4 1 AJ 1 7 M D4 0 A
M_ A _ D Q4 2 M D4 1 A
AK1 7
M_ A _ D Q4 3 AP1 6 M D4 2 A AD 1 8
M D4 3 A DD R VRE F 0 M _ DD R V RE F
M_ A _ D Q4 4 A H1 8 AD 2 3
M_ A _ D Q4 5 M D4 4 A DD R VRE F 1
AP1 8
M_ A _ D Q4 6 A N1 8 M D4 5 A
M_ A _ D Q4 7 AP1 7 M D4 6 A 1 . 8V
M D4 7 A
A M1 8
9 ,1 0 M _ DM 5 AL 1 7 D QM 5 A AJ 2 5 M _ C O MP _ P R2 2 4 4 0 . 2 _ 1 % _0 4
9 ,1 0 M _ DQ S 5 D QS 5A D D R C O MP
M_OCDVREF_P=0.874V
A M1 7 AK2 6 M _ C O MP _ N
9 ,1 0 M_ D QS 5 # D QS 5A # D D R C OM N M_ O C D V R E F _ P
9, 1 0 M _ A _ D Q [ 6 3 : 0 ] M_ A _ D Q4 8 A N1 6
M_ A _ D Q4 9 AK1 6 M D4 8 A R2 2 2 3 6 _ 1 % _0 6
M_ A _ D Q5 0 M D4 9 A M _ OC D V R E F _ P
A N1 4 AH 2 8
M_ A _ D Q5 1 AJ 1 5 M D5 0 A OC D V R E F P AJ 2 9 M _ OC D V R E F _ N
M_ A _ D Q5 2 AP1 5 M D5 1 A O CD V R E F N
M_ A _ D Q5 3 M D5 2 A
A M1 6
M_ A _ D Q5 4 AK1 5 M D5 3 A 1 . 8V
M_ A _ D Q5 5 AP1 4 M D5 4 A
M D5 5 A
A H1 6 M_OCDVREF_N=0.969V R2 0 6 3 6 _ 1 % _0 6
9 ,1 0 M _ DM 6 AL 1 5 D QM 6 A
9 ,1 0 M _ DQ S 6 D QS 6A
A M1 5 B6 M_ O C D V R E F _ N
9 ,1 0 M_ D QS 6 # D QS 6A # S 3 A UX S W # N B_ S3 AU XSW # 3 1
9, 1 0 M _ A _ D Q [ 6 3 : 0 ] M_ A _ D Q5 6 AL 1 3 R2 1 1 4 0 . 2 _ 1 % _0 4
M_ A _ D Q5 7 A M1 3 M D5 6 A
M_ A _ D Q5 8 M D5 7 A
A M1 2
M_ A _ D Q5 9 AJ 1 3 M D5 8 A
M_ A _ D Q6 0 A M1 4 M D5 9 A
M_ A _ D Q6 1 M D6 0 A
AK1 4
M_ A _ D Q6 2 A N1 2 M D6 1 A
M_ A _ D Q6 3 A H1 4 M D6 2 A
M D6 3 A
AK1 3
9 ,1 0 M _ DM 7 AP1 2 D QM 7 A
9 ,1 0 M _ DQ S 7 D QS 7A
AP1 3
9 ,1 0 M_ D QS 7 # D QS 7A #
S S
i 67 1 D X
B - 6 SiS671DX - DRAM 2/5

Schematic Diagrams
SiS671DX - MuTIOL 3/5
3 .3 VS C5 2 6
1 .8 V S 0 . 1 u_ 1 0 V _ X7 R _ 04
5
U2 6 R3 6 5
U3 2 A R3 5 2 1 3 3 _0 4
R 2 21 C 3 01 A H 10 F1 5 N B_ ENT EST 3 3_ 0 4 4 Z 06 1 8 DP RST P # _ INV
25 Z _ C LK 0 Z CL K E NT E S T Z 06 1 7 2
1 5 0 _ 1% _ 0 4 0 . 1 u _1 0 V _ X 7R _ 04 AP8 D 16 N B _ TE S TM OD E 0
21 Z D RE Q Z DR EQ T E S T MO D E 0 N B _ TE S TM OD E 1
A N8 E1 6 C 51 9 74 L V C 1 G 1 4G W
21 Z U RE Q Z UR EQ T E S T MO D E 1
3
F1 6 N B _ TE S TM OD E 2
Z _ VR EF T E S T MO D E 2 Z06 02
A M7 D 17 * 10 0 p _5 0 V _ N P O_ 0 4
21 ZST B_ D 0 A L7 Z S TB 0 T RA P 0 E1 7 Z06 03
21 Z S T B _ D# 0 Z S TB 0# T RA P 1
R 2 14 C 3 07 AP4 F1 7 Z06 04 R3 6 4
21 ZST B_ D 1 AP5 Z S TB 1 T RA P 2 *3 3 _ 0 4
21 Z S T B _ D# 1 Z S TB 1#
4 9 . 9 _ 1% _ 0 4 0 . 1 u _1 0 V _ X 7R _ 04
21 Z A D [ 16 : 0 ] Z AD0 Z06 05 22 S B _D P R S LP V R 2 2 S B _D P R S TP #
A K 10 AC 32
Z AD1 A M6 Z A D0 T RA P 3 AD 34 Z06 06
Z AD2 Z A D1 T RA P 4 Z06 07
A K 11 AB 28 3 .3 V S C1 6 8
Z AD3 A J 11 Z A D2 T RA P 5 AD 32 Z06 08 0 . 1 u_ 1 0 V _ X7 R _ 04
Z AD4 Z A D3 T RA P 6 Z06 09
AP7 AD 33
Z AD5 A J9 Z A D4 T RA P 7 AE 34 Z06 10
Z A D5 T RA P 8
5
Z AD6 AP6 AC 30 Z06 11 U6 R1 4 6
1 .8 V S Z AD7 A N6 Z A D6 T RA P 9 AC 29 Z06 12 R1 3 9 1 3 3 _0 4
Z AD8 AK9 Z A D7 T R A P 10 3 3_ 0 4 4 Z 06 2 0
Z _ C OM P _N Z AD9 Z A D8 Z 06 1 9 P M _ DP R S L P V R 3 7
R4 6 7 5 6_ 0 4 A M4 2
R4 6 8 5 6_ 0 4 Z _ C OM P _P
Z AD1 0
Z AD1 1
AK6
AK8
Z
Z
Z
A D9
A D1 0
A D1 1
C 16 9 74 L V C 1 G 1 7G W
Sheet 6 of 50
3
Z AD1 2 A N4 A5 A U X _ P W R OK
Z AD1 3 Z A D1 2 A U XO K D E L A Y _P W R G D A U X _ P W R OK 2 2 , 2 6
AK7 C 6 D E L A Y _P W R G D 3 1 , 3 7 * 10 0 p _5 0 V _ N P O_ 0 4
R1 9 3 4 . 7K _0 4 N B_ ENT EST Z AD1 4 A L5 Z A D1 3 PW RO K A7
SiS671DX -
Z AD1 5 Z A D1 4 P C I R S T# N B _ R S T# 11 , 3 1
A M5
C2 3 7 0 . 1 u _1 0 V _ X 7R _ 04 A U X _ P W R OK Z AD1 6 A M8 Z A D1 5
Z A D1 6 ASL R1 4 1 * 0_ 0 4
C2 3 6 0 . 1 u _1 0 V _ X 7R _ 04 D E L A Y _ P W R GD A L9
Z _ VREF Z V RE F
Z _ C O MP _ P AP9
R1 8 9
R1 9 1
R1 8 5
R1 8 4
0_04
0_04
0_04
0_04
D AC_ H SYN C
D AC_ VSY NC
D A C _ D D C A C LK
DA C _ DD CA D A T
Z _ C O MP _ N A M9
Z C M P _P
Z C M P _N
A G P S T OP #
AG PBU SY#
G 14
A6
A GP S TO P # 2 2
A GP B U S Y # 22
3 .3 VS C 2 43
*0 . 1 u _1 0 V _ X 7R _ 04
3 .3 VS C 2 28
*0 . 1 u _1 0 V _ X 7R _ 04
MuTITOL 3/5
R1 9 4 0_04 C L K _ 1 4M _ 67 1 MX A M 10 D 8
Z 4 XA V D D Z 4X A V D D VBVS YN C V B V S Y NC 1 1
A N 10 F7
Z 4X A V S S VBHS YN C VBHS YN C 1 1
NE AR S ISM 67 2
5
E7 U 12 R1 7 2
VBH CL K VBHC L K 11
5
R1 7 9 1 33 _ 0 4 U 8
D A C _R E D D 13 C 8 49 9 _ 1 %_ 0 4 4 Z 0 62 3 Z 0 6 25 1
19 D A C_ RE D R OU T V BCL K VBCL K 11
D A C _G R E E N C 12 E9 Z 0 62 1 2 4 H _ D P S LP #_ L S
3 .3 V S
W760SUA ? ? 19
19
D A C _ GR E E N
D A C _B LU E
D A C _B L U E C 13
G OU T
B OU T
V B CA D VBCA D 11
2
D 9 C2 4 4 7 4 L V C 1 G1 7 G W
V ACL K VACL K 11
3
19 D A C_ HS Y NC F 12 7 4 L V C 1 G0 8 GW
H SY NC
3
G 12 For SiS VB 307 1 00 p _ 5 0V _ N P O_ 0 4 6 -0 1- 74 10 8- Q6 1
Z06 01 19 DA C _ V S Y N C V SYN C
R1 8 6 4 . 7K _0 4
1 9 D A C _D D C A C L K
D 11
V GP I O 0
use only
NE AR S IS M6 72 E 12 AH 2 Z06 13
1 9 D A C _D D C A D A T V GP I O 1 N C0 AG 3 Z06 14
N C1 22 C P U _ S TP # 3 .3 VS 3 .3 VS
C2 4 6 * 0. 1u _ 1 6V _ Y 5 V _0 4 W7 60 SU A ? ? ? V C OMP D 15 C 2 41 C 2 39
VVBW N C 15 V C O MP *0 . 1 u _1 0 V _ X 7R _ 04 0 . 1u _ 1 0V _X 7 R _ 0 4
C2 4 9 * 0. 1u _ 1 6V _ Y 5 V _0 4 R1 8 0 *1 2 1_ 1 % _0 4 V RS E T C 14 V VBW N
V RSET
5
C2 5 1 * 0. 1u _ 1 6V _ Y 5 V _0 4 R1 8 7 *0 _ 04 Z 06 0 1 F 13 U 10
4 ,2 1 P C I _I N T #A IN T A#
5
U 11 R1 6 8 1
C L K _1 4 M_ 6 7 1 MX F 11 R1 7 7 1 33 _ 0 4 4
2 5 C L K _ 1 4M _ 67 1 MX V OS C I Z 0 62 4 Z 0 6 26 C P U S TP # 2 5
33 _ 0 4 4 2
A 12 Z 0 62 2 2
1 .8 V S E C LK A V D D DA CA V D D1 D A C A V DD 1
B 12 7 4 A H C 1 G3 2 GW
5mA DA CA V S S 1 D AC AVSS1
3
C2 3 3 7 4 L V C 1 G1 7 G W
3
L63 H C B 1 0 0 5K F -1 21 T 2 0 A 13
DA CA V D D2 B 13 D A C A V DD 2
DA CA V S S 2 *1 0 0 p_ 5 0 V _ N P O _ 04
D AC AVSS2
C 6 00 C 6 10 C 6 04 DC L KAVD D B 10
A 11 D CL KAV DD
D CL KAV SS
1 0 u _ 10 V _ Y 5 V _ 0 8 0 . 1 u _ 10 V _ X 7 R _ 0 4 0 . 0 1 u_ 5 0 V _ X7 R _0 4
Level Shitt
A9
E CL K A V D D B8 E CL KAVD D
E CL KAVSS 1.05V <=> 3.3V
Z 0 6 2 9 R 16 0 2 00 K _ 0 4
1 .0 5 VS 3 . 3V S
SS
i 67 1 D X R 17 5 1 50 _ 1 % _0 4 U 9 R 16 1 1 K _1 % _ 0 4
R 17 4 1 50 _ 1 % _0 4 1 8 R 16 2 1 K _1 % _ 0 4
D AC_ R ED C 797 * 10 p _ 50 V _ N P O_ 0 4 2 G ND E N 7
VR EF1 V RE F 2
2 ,3 7 H_ DP R S T P # R 17 3 * 1 0m i l _s h o r t -N M NZP0 6 27 3 6 D P R S TP #_ I N V
1 .8 V S D C LK A V D D D A C_ G RE E N C 798 * 10 p _ 50 V _ N P O_ 0 4 R 17 6 * 1 0m i l _s h o r t -N M NZP0 6 28 4 SC L 1 S C L2 5 H _ DP S L P # _ L S
5mA 2 H _ D P S LP # SD A1 S DA 2
L17 H C B 1 0 0 5K F -1 21 T 2 0 D AC_ BL U E C 812 * 10 p _ 50 V _ N P O_ 0 4 P C A 9 3 0 6D C U R C2 0 6
0 . 0 1u _ 5 0V _X 7 R _ 0 4
C 2 08 C 2 24 C 2 23
W760SU ? ? ?
1 0 u _ 10 V _ Y 5 V _ 0 8 0 . 1 u _ 10 V _ X 7 R _ 0 4 0 . 0 1 u_ 5 0 V _ X7 R _0 4
C2 4 5 * 0 . 1u _ 1 6 V _Y 5 V _ 04 V C O MP
C2 4 2 * 0 . 1u _ 1 6 V _Y 5 V _ 04 V V B W N
1. 8 V S L 61
H C B 1 00 5 K F -1 2 1 T2 0
1 .8 VS L19
H C B 1 0 0 5 K F -1 21 T 2 0 1. 5 V S L 62 DA C A V D D1
1 .8 V S
10mA Z4 XAVD D 73mA DA C A V DD 2
*H C B 1 0 0 5K F - 12 1 T 20
73mA
L26 H C B 1 0 0 5K F -1 21 T 2 0
C 2 11 C2 2 9 C2 2 7
C5 9 5 C6 0 8 C6 0 9
C 3 33 C3 3 1 C 3 29 * 1 0u _ 1 0V _Y 5 V _ 08 0 . 1u _ 1 0 V _X 7 R _ 0 4 0 . 01 u _ 50 V _ X 7 R _ 0 4
*1 0 u_ 1 0 V _ Y 5 V _ 0 8 0. 1u _ 1 0V _X 7 R _ 0 4 0. 1 u _ 1 0V _ X 7 R _ 0 4
1 0 u _ 10 V _ Y 5 V _ 0 8 0 . 1u _ 1 0 V _X 7 R _0 4 0 . 0 1 u_ 5 0 V _ X7 R _0 4 N C1 N C_ 0 4
N C1 1 N C _ 04
D A CA V S S 2
DA CA V S S 1
SiS671DX - MuTIOL 3/5 B - 7

Schematic Diagrams
SiS671DX - PWR 4/5
U32E
1.8V
6 64mA 1.2VS
W23
Y23 VCCM M13 2024mA
C268 C277 C298 C297 AA23 VCCM IVDD M14
AB23 VCCM IVDD M15 C257 C280 C272
10u_10 V_Y5V_ 08
10u_10V_Y5V_08*1 u_10V_06 1u_10V_ 06 AC23 VCCM IVDD M16
AC18 VCCM IVDD M17 1 0u_10V_Y5V_08
10u_ 10V_Y5V_08
10u_10V_Y5V_ 08
VCCM IVDD
AC20 VCCM IVDD M18
AC16 M19
1. 8V AD16 VCCM IVDD N16
VCCM IVDD
AD17 N17
664m A
AD19 VCCM IVDD N18 1.2VS

AD20 VCCM IVDD N20
C26 7 C283 C285 C284 AD21
VCCM IVDD
R22
2024mA
AD22 VCCM IVDD N22
1u_10V_06 *1u_10V_06 0. 1u_10V_X7R_0 4 0 .1u_10V_X7R_04 AJ22 VCCM IVDD N13 C286 C306 C254
VCCM IVDD
AJ24 VCCM IVDD P13
AL23 Y13 1 u_10V_06 1u_1 0V_06 1u_10V_06
AL26 VCCM IVDD Y22
AN21 VCCM IVDD T13
AN23 VCCM IVDD U13
Sheet 7 of 50 1.8VS
AN25
AN27
AN29
VCCM
VCCM
VCCM
VCCM
IVDD
IVDD
IVDD
IVDD
U22
V13
W13
2024mA
1.2VS
W22
392m A PWR
SiS671DX PWR 4/5 C664 C653 C659 C661
AP3
AB12
AB13
AC12
VCC1. 8
VCC1. 8
VCC1. 8
IVDD
IVDD
IVDD
IVDD
AA13
AA22
AB14
AB15
C266
1 u_10V_06
C300
0. 1u_10V_X7 R_0 4
C647
0. 1u_10V_ X7R_04
10u_10 V_Y5V_ 08
1u_10V_06 1u_10V_06 1u_10V_ 06 AC13 VCC1. 8 IVDD AB16
AC14 VCC1. 8 IVDD AB18
AC15 VCC1. 8 IVDD AB20
VCC1. 8 IVDD
AH6 VCC1. 8 IVDD AB22
1.8VS AH7 AF6
AJ4 VCC1. 8 IVDD AF7 1.2VS
392mA AJ5 VCC1. 8 IVDD AK3
AJ6 VCC1. 8 IVDD AG4 202 4mA
C259 C258 C261 AJ7 VCC1. 8 IVDD AG5
VCC1. 8 IVDD
AN2 VCC1. 8 IVDD AG6 C802 C648
*0.1u_10 V_X7R_04 0. 1u_10V_X7R_04 0 .1u_10V_X7R_04 AK4 AG7
AK5 VCC1. 8 IVDD R13 1 0u_10V_Y5V_08
10u_ 10V_Y5V_08
VCC1. 8 IVDD
AL1 VCC1. 8 IVDD AH3
AL2 AH4
AL3 VCC1. 8 IVDD AH5 FOR E M I
AL4 VCC1. 8 IVDD AJ1
AM1 VCC1. 8 IVDD AJ2
AM2 VCC1. 8 IVDD AJ3
AM3 VCC1. 8 IVDD AK1
VCC1. 8 IVDD
AN3 VCC1. 8 IVDD AK2
AN5 AC22
AN7 VCC1. 8 IVDD AC21 1.8VS 1.8VS
AN9 VCC1. 8 IVDD AC19
VCC1. 8 IVDD AC17 1.05VS
392 mA E8 IVDD C805 C80 6
1.8VS
F9
VDDVB1. 8
A19
80mA
C66 2 C265 C263 F8 VDDVB1. 8 VTT A20 0. 1u_10V_X7R_04 *0.1 u_10V_X7R_04
VDDVB1. 8 VTT B19 C603 C250 C602
VTT
1u_10V_06 0. 1u_10V_X7R_04 0 .1u_10V_X7R_04 E10 VDD1. 8 VTT B20
F10 C19 1 u_10V_06 1u_1 0V_06 10u_10V_Y5V_ 08
VDD1. 8 VTT C20
VTT D19
392mA N19 VTT D20
1.8VS N21 PVDDH VTT E19 1. 05VS
P20 PVDDH VTT E20
C649 C276 C253
P22
PVDDH VTT
F19 80mA
R21 PVDDH VTT F20
1u_10V_0 6 1 u_10V_06 0. 1u_10V_X7R_ 04 PVDDH VTT
T22 G19 C247 C60 1 1.8 V 1. 8V 1. 8V 1 .8V
U21 PVDDH VTT G20
V22 PVDDH VTT L18 0 .1u_10V_X7R_04 0.1u_10V_X7R_04
PVDDH VTT L19 C807 C80 8 C8 09 C810
87 6mA M11
VTT
L20
1.2VS N11 VDDPEX VTT M20 0. 1u_10V_X7R_04 0.1u_10V_X7R_04 *0. 1u_10V_X7 R_0 4 *0. 1u_10V_X7R_ 04
C305 C278 C275 P11 VDDPEX VTT M21
VDDPEX VTT
R11 VDDPEX VTT M22
10u_10V_ Y5V_08
*0.1u _10V_X7R_04 1u_10V_ 06 T11 M23
U11 VDDPEX VTT N23
V11 VDDPEX VTT P23
87 6mA W11 VDDPEX VTT R23
1.2VS VDDPEX VTT
Y11 VDDPEX VTT T23
C274 C2 52 C256 AA11 U23 1.8VS
AB11 VDDPEX VTT V23
1u_10V_06 0.1u_10V_X7R_04 *1u_ 10V_06
VDDPEX VTT M12 392mA
VTTP
N12
B5 VTTP P12 C294 C309 C271
C5 AUX_IVDD VTTP R12
92mA D6 AUX_IVDD VTTP T12 1 u_10V_06 0.1 u_10V_X7R_04 0. 1u_10V_X7 R_0 4
AUX_IVDD VTTP
VTTP U12
V12
1 mA G8 VTTP W12
1.2V 1. 8V AUX1.8 VTTP
VTTP Y12
C235 C234 C238 C311 C248 AA12
VTTP
1u_10V_06 1u_10V_06 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.01u_5 0V_X7R_04
SiS671DX
B - 8 SiS671DX - PWR 4/5

Schematic Diagrams
SiS671DX - GND 5/5
? ? 6-34-M52GS-020
H3 3 H 27 H 28
C 3 5 5 B 2 6 4 D 1 8 6 C 3 5 5 B 2 64 D 1 86 C 3 55 B 2 6 4 D 1 8 6
H4 H2 0 H1 9
2 9 2 9 2 9
3 8 3 8 3 8
4 1 7 4 1 7 4 1 7
5 6 5 6 5 6
M TH 3 1 5 D 1 1 1 M TH 3 1 5 D 1 1 1 M TH 3 1 5D 1 1 1
H3 5 M74? ? ? H3 4
C2 5 6 B 1 8 5 D1 4 6 H3 1 *C 2 56 B 18 5 D 14 6
C3 5 4 B1 9 7 D1 8 5
H8
2 9
A A1 7
A A2 0
A A3 3
A C3 3
AD 2 9
AE 3 3
AG 3 1
AH 2 9
AN 1 5
3 8
AA1 6
AA1 8
AA1 9
AA2 1
AA3 1
AB2 9
AC3 1
AE3 1
AF 2 9
A G3 3
AJ 1 0
AJ 1 2
AJ 1 6
AJ 1 8
AJ 2 6
AJ 2 8
A K 31
AL 1 0
AL 1 2
AL 1 6
AL 1 8
AL 2 8
AL 3 3
A N 11
AN1 3
A N 17
A B5
A C2
AC 3
AD 2
AD 4
AD 5
AF 4
AG 2
AH 1
A J 14
A J 20
A J 33
A L 14
A L 20
A L 30
AB3
AB4
AB7
AD3
AD7
AE3
AF 2
AF 3
AF 5
AJ 8
AL 6
AL 8
4 1 7
Sheet 8 of 50
U3 2 F 5 6
VS S
VS S
VS S
VS S
VS S
VS S
V SS
VS S
V SS
VS S
V SS
VS S
V SS
VS S
V SS
VS S
V SS
VS S
V SS
VS S
V SS
VS S
V SS
VS S
V SS
V SS
V SS
V SS
V SS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A3 M TH 3 1 5 D 1 1 1
B2 VS S T2 9
VS S V SS
B3 U 2 ? ? 6-34-M52NS-020
SiS671DX GND 5/5
B4 VS S V SS U 3
VS S V SS U 4
V SS
B2 1 U 5 M74? ? ?
B2 3 VS S V SS U 6 H 30 H 29 H3 2
B2 5 VS S V SS U 14 C 2 1 7 D1 1 1 C 3 54 B 1 9 7 D 1 8 5 C2 1 7 D1 1 1 H7 H3 H6
VS S V SS
B2 7 U 15 2 9 2 9 2 9
B2 9 VS S V SS U 16 3 8 3 8 3 8
B3 1 VS S V SS U 17 4 1 7 4 1 7 4 1 7
VS S V SS
C 1 U 18 5 6 5 6 5 6
C 2 VS S V SS U 19
C 3 VS S V SS U 20 M TH 3 1 5 D 1 1 1 M TH 3 1 5 D 1 1 1 M TH 3 1 5D 1 1 1
VS S V SS
C 4 U 31
VS S V SS U 33
V SS V 2
V SS
C 9 V 3
C1 0 VS S V SS V 4 H1 6 H 18 H1 3 H 14 H 22 H 26 H3 8 H2 3 H2 1 H1 7
C1 1 VS S V SS V 5 C 3 1 5 D 1 1 1 C 2 37 C2 3 7 C 237 C 6 7D 6 7 C 6 7 D6 7 C2 9 6 D1 6 6 2 9 2 9 2 9
VS S V SS
C1 6 V 14 3 8 3 8 3 8
C1 8 VS S V SS V 15 4 1 7 4 1 7 4 1 7
C3 2 VS S V SS V 16 5 6 5 6 5 6
VS S V SS
C3 3 V 17
D 1 VS S V SS V 18 M TH 3 1 5 D 1 1 1 M TH 3 1 5 D 1 1 1 M TH 3 1 5D 1 1 1
D 2 VS S V SS V 19
VS S V SS
D 3 V 20
D 4 VS S V SS V 29
D 5 VS S V SS A N3 3 H 12 H9 H 11 H 15 H1 0 H 36 H3 7
VS S V SS
D1 0 A N3 1 C 2 76 B 1 9 3 D 1 8 5 C 2 3 7 C 237 C 2 37 C2 3 7 C 1 7 8 D7 9 C1 7 8 D7 9 H5
D1 2 VS S V SS A N1 9 2 9
D2 1 VS
VS
S
S
GND V
V
SS
SS
W 3 3 8
D2 3 W 14 4 1 7
D2 5 VS S V SS W 15 5 6
D2 7 VS S V SS W 16
VS S V SS
D2 9 W 17 M TH 3 1 5 D 1 1 1
E1 VS S V SS W 18
E2 VS S V SS W 19
VS S V SS
E3 W 20
E6 VS S V SS W 21 S8
E1 1 VS S V SS W 31 S M D 9 8 X 17 8 R
VS S V SS
E1 3 W 33
E1 4 VS S V SS Y 2
1
E1 8 VS S V SS Y 3
VS S V SS
1
E2 9 Y 4
VS S V SS
E3 0 Y 5
E3 3 VS S V SS Y 7
VS S V SS
F2 Y 14 M1 M2 M6 M7 M 11 M 10 M4
VS S V SS
F3 Y 15 M- M A R K 1 M -MA R K 1 M -M A RK 1 M-M A R K 1 M -MA R K 1 M -M A R K 1 M- M A R K 1
F4 VS S V SS Y 16
VS S V SS
F5 Y 17
VS S V SS
F6 Y 18
F1 4 VS S V SS Y 19
VS S V SS
F2 2 Y 20
VS S V SS
F2 4 Y 21
F2 6 VS S V SS Y 29 M9 M 13 M5 M3 M 14 M8 M1 2
VS S V SS
F2 8 A A2 M- M A R K 1 M -MA R K 1 M -M A RK 1 M-M A R K 1 M -MA R K 1 M -M A R K 1 M- M A R K 1
VS S V SS
G 2 A A3
G 3 VS S V SS A A1 4
VS S V SS
G 7 A A1 5
VS S V SS
G1 0 A B1 7
P2 1 VS S V SS A B1 9
VS S V SS
T2 1 A B2 1
VS S V SS
V2 1 P 19
VS S V SS
VS S
VS S
VS S
VS S
VS S
VS S
V SS
VS S
V SS
VS S
V SS
VS S
V SS
VS S
V SS
VS S
V SS
VS S
V SS
VS S
V SS
VS S
V SS
VS S
V SS
V SS
V SS
V SS
V SS
V SS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
S 6 S3 S2 S 7 S5 S4 H2 5 H 24 H 2 H1
S MD 7 3X 1 3 6 R S M D 1 9 2 X 7 3S R S M D 1 9 2 X7 3 S R S MD 1 92 X 7 3 S R S M D 1 9 2 X 7 3S R S M D 1 9 2 X7 3 S R H4 _ 0 H 4_ 0 H 4_0 H4 _ 0
S i S 6 7 1 DX
G 33
H 4
H 29
J2
J7
J31
K 3
K 29
L2
L4
L5
L31
L33
M2
M3
M 29
N 4
N 5
N 7
N 31
P1 4
P1 5
P1 6
P1 7
P1 8
P2 9
R 4
R 15
R 18
R 31
T1 4
T1 5
T1 6
T1 7
T1 8
T1 9
T2 0
G3 1
H5
J3
J3 3
K4
K5
L3
L7
N3
N6
N 14
N1 5
N 33
P2
P3
R2
R3
R5
R1 4
R1 6
R1 7
R1 9
R2 0
R3 3
T3
T6
1
1
SiS671DX - GND 5/5 B - 9

Schematic Diagrams
DDR2 SO-DIMM_1
SO-DIMM 1 1 .8 V
112
117
103
104
183
184
122
196
150
149
11 1
1 18
13 3
1 21
19 3
1 62
1 38
16 1
95
81
82
88
47
12
48
78
72
40
28
96
87
77
71
8
J _ DI M 1
VS S
V SS
V SS
VS S
V SS
VS S
V SS
VD D
VD D
V DD
VD D
VD D
VD D
VD D
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V DD
V DD
V DD
V DD
V DD
5 , 1 0 M_ A _ A [ 1 7 : 0 ] M_ A _ A 0 1 02 5 M _A _ D Q5 M _A _D Q[ 6 3 : 0 ] 5 , 1 0
M_ A _ A 1 1 01 A0 D Q0 7 M _A _ D Q2
M_ A _ A 2 A1 D Q1 M _A _ D Q6
1 00 17
M_ A _ A 3 99 A2 D Q2 19 M _A _ D Q7
M_ A _ A 4 A3 D Q3 M _A _ D Q4
98 4
M_ A _ A 5 97 A4 D Q4 6 M _A _ D Q0
A5 D Q5
M_ A _ A 6 94 14 M _A _ D Q1
M_ A _ A 7 92 A6 D Q6 16 M _A _ D Q3
M_ A _ A 8 93 A7 D Q7 23 M _A _ D Q1 3
M_ A _ A 9 A8 D Q8 M _A _ D Q1 1
91 25
M_ A _ A 1 0 1 05 A9 D Q9 35 M _A _ D Q1 5
M_ A _ A 1 4 A 10 / A P D Q 10 M _A _ D Q1 4
90 37
M_ A _ A 1 5 89 A 11 D Q 11 20 M _A _ D Q1 2
M_ A _ A 1 6 1 16 A 12 D Q 12 22 M _A _ D Q8
M_ A _ A 1 7 A 13 D Q 13 M _A _ D Q9
86 36
84 A 14 D Q 14 38 M _A _ D Q1 0
M_ A _ A 1 3 A 15 D Q 15 M _A _ D Q1 6
85 43
M_ A _ A 1 1 1 07 A 16 / B A 2 D Q 16 45 M _A _ D Q2 0
BA0 D Q 17
M_ A _ A 1 2 1 06 55 M _A _ D Q1 8
Sheet 9 of 50 5 ,1 0
5 ,1 0
M
M
_ DM
_ DM
0
1
10
26
BA1
DM
DM
0
1
D Q 18
D Q 19
D Q 20
D Q 21
D Q 22
57
44
46
56
M
M
M
M
_A _ D
_A _ D
_A _ D
_A _ D
Q1 9
Q2 1
Q1 7
Q2 3
52 58 M _A _ D Q2 2
DDR2 SO-DIMM_1 5 ,1 0
5 ,1 0
5 ,1 0
5 ,1 0
5 ,1 0
M
M
M
M
M
_ DM
_ DM
_ DM
_ DM
_ DM
2
3
4
5
6
67
1 30
1 47
1 70
DM
DM
DM
DM
DM
2
3
4
5
6
D Q 23
D Q 24
D Q 25
D Q 26
D Q 27
61
63
73
75
M
M
M
M
_A _ D
_A _ D
_A _ D
_A _ D
Q2 4
Q2 5
Q2 9
Q2 7
1 85 62 M _A _ D Q2 8
5 ,1 0 M _ DM 7 DM 7 D Q 28 64 M _A _ D Q2 6
? ? ? ? ? ? ? !
D Q 29
13 74 M _A _ D Q3 0
5 ,1 0 M _ DQ S0 31 DQ S0 D Q 30 76 M _A _ D Q3 1 M _C L K _ D D R 0 M _ CL K _ DD R1
5 ,1 0 M _ DQ S1 DQ S1 D Q 31
51 123 M _A _ D Q3 9
5 ,1 0 M _ DQ S2 DQ S2 D Q 32 M _A _ D Q3 7
5 ,1 0 M _ DQ S3 70 125
1 31 DQ S3 D Q 33 135 M _A _ D Q3 5 C3 6 4 C3 6 6
5 ,1 0 M _ DQ S4 DQ S4 D Q 34 M _A _ D Q3 8
1 48 137
5 ,1 0 M _ DQ S5 1 69 DQ S5 D Q 35 124 M _A _ D Q3 2 *3 . 3 p _5 0 V _ N P O_ 0 4 *3 . 3 p _ 50 V _ N P O_ 0 4
5 ,1 0 M _ DQ S6 DQ S6 D Q 36
1 88 126 M _A _ D Q3 6
5 ,1 0 M _ DQ S7 DQ S7 D Q 37 M _A _ D Q3 4 M _C L K _ D D R 0 # M _ CL K _ DD R1 #
134
D Q 38 136 M _A _ D Q3 3
M_ R A S # D Q 39 M _A _ D Q4 7
1 08 141
5 ,1 0 M _ RA S # M_ W E # 1 09 RAS# D Q 40 143 M _A _ D Q4 0
5 ,1 0 M_ W E # W E# D Q 41
M_ C A S # 1 13 151 M _A _ D Q4 4
5 ,1 0 M _ CA S # CAS# D Q 42 153 M _A _ D Q4 3
M_ C S 0# 1 10 D Q 43 140 M _A _ D Q4 6
5 ,1 0 M_ C S 0 # M_ C S 1# S 0# D Q 44 M _A _ D Q4 5
5 ,1 0 M_ C S 1 # 1 15 142
S 1# D Q 45 152 M _A _ D Q4 1
M_ C K E 0 D Q 46 M _A _ D Q4 2
79 154
5 ,1 0 M_ C K E 0 M_ C K E 1 80 CKE0 D Q 47 157 M _A _ D Q4 9
5 ,1 0 M_ C K E 1 CKE1 D Q 48 159 M _A _ D Q4 8
D Q 49 M _A _ D Q5 0
173
D Q 50 175 M _A _ D Q5 5
M_ C L K _ D D R 0 D Q 51 M _A _ D Q5 3
30 158
2 5 M_ C L K _ D D R 0 M_ C L K _ D D R 0# 32 CK0 D Q 52 160 M _A _ D Q5 2
2 5 M _C L K _ D D R 0 # CK0 # D Q 53
M_ C L K _ D D R 1 1 64 174 M _A _ D Q5 1
2 5 M_ C L K _ D D R 1 M_ C L K _ D D R 1# 1 66 CK1 D Q 54 176 M _A _ D Q5 4
2 5 M _C L K _ D D R 1 # CK1 # D Q 55 179 M _A _ D Q5 6
M_ OD T 0 D Q 56 M _A _ D Q5 7
5 ,1 0 M_ O D T 0 1 14 181
M_ OD T 1 1 19 OD T0 D Q 57 189 M _A _ D Q5 8
5 ,1 0 M_ O D T 1 OD T1 D Q 58 M _A _ D Q6 2
191
1 95 D Q 59 180 M _A _ D Q6 1 1 .8 V
1 0 , 2 2 , 25 , 3 3 S _ D A T S DA D Q 60
1 97 182 M _A _ D Q6 0
1 0 , 2 2 , 25 , 3 3 S _ C LK S CL D Q 61 M _A _ D Q5 9
192
D Q 62 194 M _A _ D Q6 3
D Q 63
11
5 ,1 0 M _D QS 0# 29 DQ S# 0 R 4 71 C 6 71
5 ,1 0 M _D QS 1# DQ S# 1
49 83
5 ,1 0 M _D QS 2# 68 DQ S# 2 N C1 120 1 K _ 1 % _0 4 0 . 1 u _ 10 V _ X 7 R _ 0 4
5 ,1 0 M _D QS 3# DQ S# 3 N C2
1 29 50
5 ,1 0 M _D QS 4# DQ S# 4 N C3
5 ,1 0 M _D QS 5# 1 46 69 M V RE F 1
1 67 DQ S# 5 N C4 163
5 ,1 0 M _D QS 6# DQ S# 6 N CT E S T
1 86
5 ,1 0 M _D QS 7# DQ S# 7 R 4 72 C 6 72
MV R E F 1 1 1 K _ 1 % _0 4 0 . 1 u _ 10 V _ X 7 R _ 0 4
V RE F 198 Z 09 0 1 R 2 5 8 * 1 0m i l _ sh o rt -N MN P
SA0 Z 09 0 2 R 2 5 9
C3 5 9 1 99 200 * 1 0m i l _ sh o rt -N MN P
V DD S P D SA1
1 u_ 6 . 3 V _ X 5R _ 06
V SS
VS S
V SS
VS S
VS S
V SS
V SS
VS S
V SS
VS S
V SS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3 .3 VS A S 0A 42 1 -N 2A N -4 F
18
24
53
54
59
65
60
127
128
145
171
177
178
190
9
21
33
155
34
144
168
2
3
15
39
41
42
66
1 39
16 5
17 2
1 87
13 2
1 56
27
C3 6 0
0 . 1u _ 1 0 V _ X7 R _0 4
1 .8 V
C7 1 2 C3 9 7 C3 6 7 C3 6 8 C3 7 1 C3 9 6 C 39 5 C 31 5 C 303 C6 6 7 C6 6 8 C 3 65 C 304 C4 0 3 C 39 2
+ +
*1 5 0u _ 4 V _ B _ A 15 0 u _ 4V _B _ A 10 u _ 1 0V _Y 5 V _ 081 0u _ 1 0 V _Y 5 V _ 0 81 0u _ 1 0 V _ Y 5 V _ 0 81 0 u_ 1 0 V _ Y 5 V _ 0 81 0 u_ 1 0 V _ Y 5 V _ 0 80 . 1 u _1 0 V _ X 7 R _ 0 4 0 . 1 u _ 10 V _ X 7 R _ 0 4 0. 1u _ 1 0 V _X 7 R _0 4 0 . 1 u_ 1 0 V _ X 7R _ 04 0 . 1 u _1 0 V _ X 7 R _ 0 4 0 . 1 u _ 1 0V _ X 7 R _ 0 4 0 . 1u _ 1 0 V _ X7 R _0 4 0 . 1 u_ 1 0 V _ X 7R _ 04
B - 10 DDR2 SO-DIMM_1
Schematic Diagrams
DDR2 SO-DIMM_2
SO-DIMM 2 1 . 8V
5 ,9 M _ A _A [ 17 : 0 ]
112
117
118
103
104
183
184
122
193
162
150
161
1 11
13 3
12 1
1 96
13 8
1 49
96
95
82
87
88
47
12
48
78
71
72
40
81
77
28
8
J _ DIM 2
Layout Note:
VS S
V SS
V SS
VS S
V SS
VS S
V SS
V DD
VD D
V DD
VD D
VD D
VD D
V DD
VD D
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
5 ,9 M _ A _A [ 17 : 0 ] M _A _D Q[ 6 3 : 0 ] 5 , 9 Two pieces of 56 ohms must use one
M _ A_ A0 102 5 M _ A _ DQ 5
M _ A_ A1 101 A0 DQ 0 7 M _ A _ DQ 2 0.1U bypass capacitor.
M _ A_ A2 100 A1 DQ 1 17 M _ A _ DQ 6
M _ A_ A3 A2 DQ 2 M _ A _ DQ 7 0. 9 V S
99 19
M _ A_ A4 98 A3 DQ 3 4 M _ A _ DQ 4
M _ A_ A5 A4 DQ 4 M _ A _ DQ 0
97 6
M _ A_ A6 94 A5 DQ 5 14 M _ A _ DQ 1 M _A _ A 1 6 8 1 C6 9 6 0. 1 u _ 1 0V _ X 7 R _ 0 4
M _ A_ A7 A6 DQ 6 M _ A _ DQ 3
92 16 7 2 R N2 2
M _ A_ A8 93 A7 DQ 7 23 M _ A _ DQ 13 5 M_ OD T 2 6 3 5 6 _ 8P 4R _ 04 C3 8 9 0. 1 u _ 1 0V _ X 7 R _ 0 4
A8 DQ 8 5 M_ C S 2 #
M _ A_ A9 91 25 M _ A _ DQ 11 5 4
M _ A _ A 10 A9 DQ 9 M _ A _ DQ 15 5, 9 M_ R A S #
105 35
M _ A _ A 14 90 A1 0 /A P D Q1 0 37 M _ A _ DQ 14 M _A _ A 1 2 8 1 C6 9 8 0. 1 u _ 1 0V _ X 7 R _ 0 4
M _ A _ A 15 A1 1 D Q1 1 M _ A _ DQ 12 M _A _ A 0
89 20 7 2 R N2 3
M _ A _ A 16 116 A1 2 D Q1 2 22 M _ A _ DQ 8 M _A _ A 2 6 3 5 6 _ 8P 4R _ 04 C3 8 7 0. 1 u _ 1 0V _ X 7 R _ 0 4
M _ A _ A 17 A1 3 D Q1 3 M _ A _ DQ 9 M _A _ A 4
86 36 5 4
84 A1 4 D Q1 4 38 M _ A _ DQ 10
M _ A _ A 13 85 A1 5 D Q1 5 43 M _ A _ DQ 16 M _A _ A 6 8 1 C3 8 2 0. 1 u _ 1 0V _ X 7 R _ 0 4
A1 6 /B A2 D Q1 6
Sheet 10 of 50
M _ A _ A 11 107 45 M _ A _ DQ 20 M _A _ A 7 7 2 R N2 4
M _ A _ A 12 106 BA0 D Q1 7 55 M _ A _ DQ 18 M _A _ A 1 4 6 3 5 6 _ 8P 4R _ 04 C6 9 5 0. 1 u _ 1 0V _ X 7 R _ 0 4
BA1 D Q1 8 M _ A _ DQ 19 M _A _ A 1 7
57 5 4
D Q1 9 44 M _ A _ DQ 21
D Q2 0 M _ A _ DQ 17
10 46 8 1 C6 8 1 0. 1 u _ 1 0V _ X 7 R _ 0 4
5 ,9 M _D M0 DM 0 D Q2 1 5, 9 M_ C A S #
DDR2 SO-DIMM_2
26 56 M _ A _ DQ 23 7 2 R N1 0
5 ,9 M _D M1 DM 1 D Q2 2 5 M_ C S 3 #
52 58 M _ A _ DQ 22 6 3 5 6 _ 8P 4R _ 04 C6 8 6 0. 1 u _ 1 0V _ X 7 R _ 0 4
5 ,9 M _D M2 DM 2 D Q2 3 M _ A _ DQ 24 5, 9 M_ OD T 0
5 ,9 M _D M3 67 61 5 M_ OD T 3 5 4
130 DM 3 D Q2 4 63 M _ A _ DQ 25
5 ,9 M _D M4 DM 4 D Q2 5 M _ A _ DQ 29 M _A _ A 3
5 ,9 M _D M5 147 73 8 1 C6 8 5 0. 1 u _ 1 0V _ X 7 R _ 0 4
170 DM 5 D Q2 6 75 M _ A _ DQ 27 M _A _ A 5 7 2 R N9
5 ,9 M _D M6 DM 6 D Q2 7 M _ A _ DQ 28
185 62 6 3 5 6 _ 8P 4R _ 04 C6 8 4 0. 1 u _ 1 0V _ X 7 R _ 0 4
5 ,9 M _D M7 DM 7 D Q2 8 64 M _ A _ DQ 26 5, 9 M_ W E # M _A _ A 1 1 5 4
13 D Q2 9 74 M _ A _ DQ 30
5 ,9 M_ D QS 0 DQ S0 D Q3 0 M _ A _ DQ 31
5 ,9 M_ D QS 1 31 76 8 1 C3 8 6 0. 1 u _ 1 0V _ X 7 R _ 0 4
51 DQ S1 D Q3 1 123 M _ A _ DQ 39 7 2 R N8
5 ,9 M_ D QS 2 DQ S2 D Q3 2 M _ A _ DQ 37 5, 9 M_ C S 0 # M _A _ A 1 0
5 ,9 M_ D QS 3 70 125 6 3 5 6 _ 8P 4R _ 04 C3 8 8 0. 1 u _ 1 0V _ X 7 R _ 0 4
131 DQ S3 D Q3 3 135 M _ A _ DQ 35 M _A _ A 1 5 4
5 ,9 M_ D QS 4 DQ S4 D Q3 4 M _ A _ DQ 38
148 137
5 ,9 M_ D QS 5 169 DQ S5 D Q3 5 124 M _ A _ DQ 32 M _A _ A 1 5 8 1 C6 8 0 *0 . 1 u_ 1 0 V _ X7 R _0 4
5 ,9 M_ D QS 6 DQ S6 D Q3 6
188 126 M _ A _ DQ 36 7 2 R N7
5 ,9 M_ D QS 7 DQ S7 D Q3 7 134 M _ A _ DQ 34 M _A _ A 9 6 3 5 6 _ 8P 4R _ 04 C6 8 3 0. 1 u _ 1 0V _ X 7 R _ 0 4
D Q3 8 136 M _ A _ DQ 33 M _A _ A 8 5 4
M _R A S # D Q3 9 M _ A _ DQ 47
108 141
M _W E # 109 RA S # D Q4 0 143 M _ A _ DQ 40 8 1 C6 9 4 0. 1 u _ 1 0V _ X 7 R _ 0 4
M _C A S # W E# D Q4 1 M _ A _ DQ 44
113 151 7 2 R N6
CA S # D Q4 2 153 M _ A _ DQ 43 5, 9 M_ C K E 1 6 3 5 6 _ 8P 4R _ 04 C6 8 2 0. 1 u _ 1 0V _ X 7 R _ 0 4
D Q4 3 5 M_ C K E 2
M _C S 2 # 110 140 M _ A _ DQ 46 M _A _ A 1 3 5 4
M _C S 3 # 115 S0 # D Q4 4 142 M _ A _ DQ 45
S1 # D Q4 5 152 M _ A _ DQ 41 R4 8 3 56 _ 0 4 C6 9 7 0. 1 u _ 1 0V _ X 7 R _ 0 4
M _C K E 2 D Q4 6 M _ A _ DQ 42 5 M_ C K E 3
79 154 5, 9 M_ C S 1 # R2 5 5 56 _ 0 4
M _C K E 3 80 CK E 0 D Q4 7 157 M _ A _ DQ 49 R2 5 6 56 _ 0 4 C3 7 9 0. 1 u _ 1 0V _ X 7 R _ 0 4
CK E 1 D Q4 8 M _ A _ DQ 48 5, 9 M_ OD T 1
159 R2 5 7 56 _ 0 4
D Q4 9 173 M _ A _ DQ 50 5, 9 M_ C K E 0
D Q5 0
175 M _ A _ DQ 55
M _C L K _ D D R 2 30 D Q5 1 158 M _ A _ DQ 53
2 5 M _ CL K _ DD R2 CK 0 D Q5 2
M _C L K _ D D R 2 # 32 160 M _ A _ DQ 52 C6 8 7 1u _ 1 0V _0 6
2 5 M_ C L K _D D R 2 # M _C L K _ D D R 3 C K 0# D Q5 3 M _ A _ DQ 51
2 5 M _ CL K _ DD R3 164 174
M _C L K _ D D R 3 # 166 CK 1 D Q5 4 176 M _ A _ DQ 54 C6 9 0 10 u _ 10 V _ Y 5V _0 8
2 5 M_ C L K _D D R 3 # C K 1# D Q5 5 M _ A _ DQ 56
179
M _O D T 2 114 D Q5 6 181 M _ A _ DQ 57
OD T 0 D Q5 7
M _O D T 3 119 189 M _ A _ DQ 58
OD T 1 D Q5 8 191 M _ A _ DQ 62
195 D Q5 9 180 M _ A _ DQ 61
9 , 2 2, 2 5 , 3 3 S _ D A T SD A D Q6 0 M _ A _ DQ 60
9 , 2 2, 2 5 , 3 3 S _ C L K 197 182 ? ? ? ? ? ? ? !
SC L D Q6 1 192 M _ A _ DQ 59
D Q6 2 M _ A _ DQ 63
194
11 D Q6 3 M _ CL K _ DD R2 M_ C LK _ D D R 3
5 ,9 M_ D QS 0 # DQ S# 0
29
5 ,9 M_ D QS 1 # 49 DQ S# 1 83
5 ,9 M_ D QS 2 # DQ S# 2 NC 1
68 120 C3 8 3 C 39 3
5 ,9 M_ D QS 3 # DQ S# 3 NC 2
5 ,9 M_ D QS 4 # 129 50
146 DQ S# 4 NC 3 69 *3 . 3 p _5 0 V _ N P O_ 0 4 * 3. 3 p _ 5 0V _ N P O_ 0 4
5 ,9 M_ D QS 5 # DQ S# 5 NC 4 1. 8 V
167 163
5 ,9 M_ D QS 6 # 186 DQ S# 6 NC T E S T M _ CL K _ DD R2 # M_ C LK _ D D R 3#
5 ,9 M_ D QS 7 # DQ S# 7
3 .3 VS
1
M VR EF 2 VR EF Z 1 0 01 R 4 8 8
198 1 0K _ 0 4 R4 7 4 C6 7 5
C 3 70 199 SA0 200 Z 1 0 02 R 4 8 6 *1 0 m il _ sh o rt -N MN P
V D DS P D SA1
1 K _1 % _ 0 4 0. 1u _ 1 0V _X 7 R _ 0 4
1 u _ 6. 3V _ X 5 R _ 0 6
V SS
V SS
VS S
V SS
VS S
V SS
V SS
VS S
V SS
VS S
V SS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1 . 8V M V RE F 2
3. 3V S
24
41
53
42
54
59
60
66
127
128
145
171
177
178
9
21
155
34
132
156
168
2
3
27
39
18
65
1 39
16 5
17 2
1 87
1 90
33
1 44
15
A S 0 A 4 2 1- N 2 R N -4 F R4 7 3 C6 7 4
C8 4 7 C 3 74
1 K _1 % _ 0 4 0. 1u _ 1 0V _X 7 R _ 0 4
2 2u _ 6 . 3 V _ X5 R _0 8 0 . 1 u _ 10 V _ X 7 R _ 0 4
1 . 8V
C6 7 3 C3 1 0 C2 9 6 C3 6 1 C2 8 2 C3 6 9 C 362 C 6 66 C 354 C2 9 5 C6 6 5 C3 2 1 C3 1 3 C3 1 2 C3 5 7
+ +
*1 5 0 u_ 4 V _ B _ A *1 5 0 u_ 4 V _ B _ A 1 0u _ 1 0V _Y 5 V _ 0810 u _ 1 0V _ Y 5 V _0 810 u _ 1 0V _ Y 5V _0 810 u _ 10 V _ Y 5V _0 81 0 u _ 10 V _ Y 5V _ 0 80 . 1 u _ 10 V _ X 7 R _ 0 4 0 . 1 u _ 10 V _ X 7 R _ 0 4 0. 1 u _ 1 0V _ X 7 R _ 0 4 0. 1 u _ 1 0V _X 7 R _ 0 4 0. 1u _ 1 0V _X 7 R _ 0 4 0 . 1u _ 1 0V _X 7 R _ 0 4 0 . 1u _ 1 0 V _X 7 R _0 4 0 . 1u _ 1 0 V _ X7 R _0 4
DDR2 SO-DIMM_2 B - 11
Schematic Diagrams
SiS307ELV
1 . 8V S V B _P C I E V D D L1 L1<=400mils
Clos e t o 3 07 sid e
L 20 *H C B 1 6 0 8 K F -1 21 T 2 5 HDV BN2 _ R C6 3 4 *0 . 1 u_ 1 0 V _X 7 R _ 0 4
HDV B P 2 _R C6 3 2 *0 . 1 u_ 1 0 V _X 7 R _ 0 4 HD VBN 2 4
HD VBP2 4
C2 1 3 C2 2 0 C 2 26 C2 1 7 C2 0 9 C 2 25 HDV BN1 _ R C6 3 5 *0 . 1 u_ 1 0 V _X 7 R _ 0 4
HDV B P 1 _R HD VBN 1 4
C6 3 3 *0 . 1 u_ 1 0 V _X 7 R _ 0 4 HD VBP1 4
*1 0 u _1 0 V _ Y 5 V _ 0 8 *0 . 1 u_ 1 0 V _ X7 R _0 4 * 0. 1u _ 1 0V _ X 7 R _ 0 4 *0 . 1 u _ 10 V _ X 7R _ 04 *0 . 1 u_ 1 0 V _ X7 R _0 4 * 0 . 1u _ 1 0V _X 7 R _ 0 4 HDV BN0 _ R C6 3 9 *0 . 1 u_ 1 0 V _X 7 R _ 0 4
HDV B P 0 _R HD VBN 0 4
C6 3 6 *0 . 1 u_ 1 0 V _X 7 R _ 0 4 HD VBP0 4
HDV AN2 _ R C6 4 1 *0 . 1 u_ 1 0 V _X 7 R _ 0 4
HDV A P 2 _R HD VAN 2 4
C6 3 8 *0 . 1 u_ 1 0 V _X 7 R _ 0 4 HD VAP2 4
HDV AN1 _ R C6 4 5 *0 . 1 u_ 1 0 V _X 7 R _ 0 4 1. 8V S VB _ PC IE AVD D
V B _P C I E A V D D HDV A P 1 _R HD VAN 1 4
C6 4 3 *0 . 1 u_ 1 0 V _X 7 R _ 0 4 HD VAP1 4
General I/O Power HDV AN0 _ R C6 4 6 *0 . 1 u_ 1 0 V _X 7 R _ 0 4 L21 * H C B 1 00 5 K F -1 2 1 T2 0
HDV A P 0 _R HD VAN 0 4
C6 4 4 *0 . 1 u_ 1 0 V _X 7 R _ 0 4 HD VAP0 4
V B _ V D D3 V C6 0 7 C2 1 9 C 22 1
M 13
M 11
HDV Signals
M 12
M 10
L10
K1 0
K1 2
N1 2
N 13
N1 0
N 11
M9
M8
M7
M6
M5
M4
M2
L1 1
N 9
N 6
N 4
N 2
N1
M3
K5
K6
K7
K8
K9
L9
L6
K3
K4
J5
J6
J7
J8
J9
L1
L2
L3
M1
N8
N7
N5
N3
R1 6 3 *2 0 m li _ sh o rt -N MN P U 31 *1 0 u _1 0 V _ Y 5 V _ 0 8 *0 . 1 u_ 1 0 V _X 7 R _ 0 4 * 0. 0 1 u _ 16 V _ X 7R _ 04
3 .3 V S
V SS
V SS
VS S
VS S
H DV B P 1
H DV B P 0
H DV A N 2
H DV A N1
H DV A N0
H DV P HY V D D
H DV P HY V D D
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H D V P LL V S S
HD V B N2
H DV B P 2
HD V B N1
HD V B N0
HD VA P2
HD VA P1
HD VA P0
HD V P L L V DD
HD V P H Y V DD
HD V P H Y V DD
HDV P HY V D D
HD V P H Y V DD
HDV P HY V D D
H DV P H Y V DD
HD V P HY V D D
H DV P H Y V DD
HD V P HY V D D
C 2 00
Sheet 11 of 50 * 0 . 1u _ 1 0V _X 7 R _ 0 4
G 10
V D D 33 L7
1 .8 V S P C I E _ C L K _ H D V # 25
SiS307ELV
G4 HD V RE F CL K N L8
I VDD H DV R E F CL K P P C IE _ CL K _ HD V 2 5
C2 0 2 C 2 16 H4
J4 I VDD L4 V B _ H D V R S E T0 R 1 6 4 * 4 99 _ 1 % _0 4
I VDD H DVR SE T 0 V B _ H D V R S E T1 R 1 6 5
*0 . 1 u_ 1 0 V _ X7 R _0 4 * 0 . 1u _ 1 0V _X 7 R _ 0 4 H 10 L5 * 1 24 _ 1 % _0 4
H 11 I VDD H DVR SE T 1
I VDD
H 12 K 13 V A CL K 6
H 13 I VDD V A CL K J1 2 V B C LK _ R R4 6 1 *1 0 m li _ s ho r t -N MN P
I VDD V B CL K V B CL K 6
1 .8 V S K 11 V B HS Y N C 6
F5 VBH SYN C J1 1
V SS VBVSYN C V BVS Y NC 6
C2 0 5 C 2 07 F6 L1 3 V B CA D 6 Side-Band
F7 V SS VBHC A D L1 2
V SS V B HCL K V B HC L K 6 Signals
*0 . 1 u_ 1 0 V _ X7 R _0 4 * 0 . 1u _ 1 0V _X 7 R _ 0 4 F8
F9 V SS F 13
V SS E X T RS T N N B _ R S T# 6, 31
G5 E 11 Z 1 1 2 4
G6 V SS GP I O F / D V I N T N E 10 Z 1 1 2 5
V SS PFT EST O
G7 F 10 Z 1 1 2 6 3 .3 V S V B _ P L L 1V D D
G8 V SS PFT EST1 G1 1 Z 1 1 2 7
G9
H5
H6
V
V
V
V
SS
SS
SS
SS
307ELV PFT EST2
DA C RS E T
D A C C O MP
B2
B1
C1 8 6
V B _ DA C V DD
L 22 *H C B 1 0 0 5K F -1 21 T 2 0
H7 D2 Z11 28 *0 . 1 u _1 0 V _ X 7R _ 04 C 2 04 C 21 4 C2 1 5
H8 V SS T VDAC R D1 Z11 29
V SS T VDAC G Z11 30
H9 E2 * 1 0u _ 1 0V _ Y 5V _0 8 *0 . 1 u _ 10 V _ X 7R _ 04 *0 . 0 1 u_ 1 6 V _X 7 R _ 0 4
J 10 V SS T VD ACB E1 Z11 31 V B _D A C V S S
V SS TV C S Y N C
Z 1 10 2 G2 C2
Z 1 10 3 H 2 G PIO A D ACVD D V B _D A C V D D
C1
Z 1 10 4 H 1 G PIO B DA CV S S D3
Z 1 10 5 G1 G PIO C DA CV S S
E3 V B _D A C V S S
G 13 G PIO D DA CV S S E4
19 LC D V D D _ E N L C D V D D _ E N / / GP I O G DA CV S S
20 30 7 _ B LO N G 12 F4
Z 1 10 6 F 11 B L_ E N / / GP I O H DA CV S S
G PIO I
L V D S P HY V DD //T M DS P H Y V D D
Z 1 10 7 F 3
L V DS P H Y V D D/ /T M D S P HY V D D
L V D S P HY V DD //T M DS P H Y V DD
L V DS P H Y V D D/ /T M D S P HY V D D
L V DS P H Y V D D/ /T M D S P HY V DD
L V DS P HY V D D/ /T M D S P HY V DD
L V DS P HY V D D/ /T M D S P HY V DD
K2
LV D S P H Y V S S / / T M D S P H Y V S S
L V DS P HY V S S / /T M DS P H Y V S S
L V D S P HY V S S / /T M DS P H Y V S S
L VDSPH YV SS//T M D SPHY V SS
L V D S P H Y V S S / / T MD S P H Y V S S
L V D S P HY V S S / /T M DS P HY V S S
L V D S P HY V S S / /T M DS P HY V S S
G PIO J C OR E P L LV D D V B _P LL 1 V D D
LV D S P L L V D D / / T M D S P L L V D D
L V D S P LL V S S / / T MD S P L L V S S
Z 1 10 8 G3 J2 V B R CL K R1 6 6 *1 0 m i l_ s ho rt -N MN P
Z 1 10 9 F 2 G PIO K V B RCL K Z11 17 C L K _ 14 M _3 0 7 E LV 25
J1
Z 1 11 0 F 1 G PIO L V B OS C O K1
Z 1 11 1 H 3 G PIO M CO RE P L L V S S
Z 1 11 2 J3 G PIO N F 12
G PIO O L DID DC CL K //DV I DD CCL K P _ D D C _C L K 1 9
E 13
L X C2 N //DX C 1 N
LD I D D C D A T A / / D V I D D C D A T A P _ D D C _D A T A 1 9
LX C 2 P / / D X C 1 P
E 12 Z11 18
B L_ A D J / / D V I H P D
L X C1 N //NC 2
L X 4 N//D X 0 N
L X 5 N//D X 1 N
L X 6 N//D X 2 N
L X 2 P //N C1 1
L X 2 N//N C1 2
L X 0 N//N C1 0
LX C 1 P / / N C 1
LX 4P / / D X 0 P
LX 5P / / D X 1 P
LX 6P / / D X 2 P
E X T S W I NG
L X 3 P //N C5
L X 3 N//N C6
L X 1 P //N C3
L X 1 N//N C4
L X 7P / / N C 7
L X 7 N// NC8
LX 0 P / / N C 9
3 .3 V S V B _L V D S P L L V D D
R 1 40 L 13 *H C B 1 0 0 5K F -1 21 T 2 0
*6 . 0 4 K _ 1% _ 0 4
*S i S 3 07 E L V
A 8
B 3
A 3
B 5
Z 1 1 13 A 1 2
Z 11 1 4A 1 3
C 11
A1 0
A1 1
C 9
A9
C 7
A6
A7
C 6
A4
A5
Z 1 11 6 C 4
E5
E6
E7
E8
E9
D 10
D 12
A2
B4
B6
B7
B8
B9
B1 0
B1 2
B1 3
D 4
D 6
D 8
C1 3
C1 2
C1 0
C8
C5
Z 1 1 1 5 C3
D1 1
D1 3
B 11
D5
D7
D9
C 1 98 C 17 5 C1 7 1
C 1 77 R1 4 4
*1 u _6 . 3 V _ X 5R _ 06 *2 4K _1 % _ 04 * 1 0u _ 1 0V _ Y 5V _0 8 *0 . 1 u _ 10 V _ X 7R _ 04 *0 . 0 1 u_ 1 6 V _X 7 R _ 0 4
Z 11 3 4 E X TS W I N G
L V D S -L 2 P V B _ L V D S P LL V D D
19 L V D S -L 2 P L V D S -L 2 N
19 L V D S -L 2 N VB_ L AVD D
L V D S -L 1 P
19 L V D S -L 1 P L V D S -L 1 N
19 L V D S -L 1 N 3 .3 VS
L V D S -L 0 P V B _ DA CV D D
19 L V D S -L 0 P
L V D S -L 0 N
19 L V D S -L 0 N L1 4 *H C B 1 0 0 5K F -12 1 T 20
L V D S -L C LK P 3 .3 VS VB_ L AVD D
19 L V D S -L C LK P L V D S -L C LK N
19 L V D S -L C LK N
L15 *H C B 16 0 8 K F -1 21 T 2 5 C1 8 4 C1 8 5 C1 8 1
L V D S -U C L K P
19 LV D S -U C L K P
L V D S -U C L K N *0 . 1 u _1 0 V _ X 7R _ 04 *0 . 0 1u _ 1 6V _ X 7 R _ 0 4 *1 0 u_ 1 0 V _ Y 5 V _ 08
19 LV D S -U C L K N
C 1 96 C 19 0 C1 9 1 C1 8 9 C 18 8
L V D S -U 0 P R1 5 4 *2 0 mi l _ sh o rt -N MN P
19 L V D S -U 0 P L V D S -U 0 N
19 L V D S -U 0 N * 1 0u _ 1 0V _Y 5 V _0 8 * 0. 1 u _ 10 V _ X 7 R _ 0 4 *0 . 1 u _1 0 V _ X 7R _ 04 *0 . 1 u_ 1 0 V _X 7 R _ 0 4 * 0. 1 u _ 1 0V _ X 7 R _ 0 4
L V D S -U 1 P V B _D A C V S S
19 L V D S -U 1 P
L V D S -U 1 N
19 L V D S -U 1 N
L V D S -U 2 P
19 L V D S -U 2 P L V D S -U 2 N
19 L V D S -U 2 N
B - 12 SiS307ELV
Schematic Diagrams
External VGA M92-S2-1
U46A
U46E
4 PE0TX0 AF30 AH30 PEX_RX0 C868 0. 1u_10V_X7R_04 PE0RX0 4

4 PE0TX0# AE31 PCIE_RX0P
PCIE_RX0N
PCIE_TX0P AG31
PCIE_TX0N PEX_RX0# C869 0. 1u_10V_X7R_04 PE0RX0# 4 AA27 PCIE_VSS#1 GND#1 A3
AB24 PCIE_VSS#2 GND#2 A30
AB32 AA13
AE29 PCIE_RX1P PCIE_VSS#3 GND#3
4 PE0TX1 PCIE_TX1P AG29 PEX_RX1
PEX_RX1#
C870 0. 1u_10V_X7R_04 PE0RX1 4 AC24 PCIE_VSS#4 GND#4 AA16
4 PE0TX1# AD28 PCIE_RX1N PCIE_TX1N AF28 C871 0. 1u_10V_X7R_04 PE0RX1# 4 AC26 PCIE_VSS#5 GND#5 AB10
AC27 AB15
AD25 PCIE_VSS#6 GND#6 AB6
AD30 PCIE_RX2P PEX_RX2 PCIE_VSS#7 GND#7
4 PE0TX2 PCIE_TX2P AF27 PEX_RX2#
C872 0. 1u_10V_X7R_04 PE0RX2 4 AD32 PCIE_VSS#8 GND#8 AC9
4 PE0TX2# AC31 PCIE_RX2N PCIE_TX2N AF26 C873 0. 1u_10V_X7R_04 PE0RX2# 4 AE27 PCIE_VSS#9 GND#9 AD6
AF32 AD8
PCIE_VSS#10 GND#10
AG27 PCIE_VSS#11 GND#11 AE7
4 PE0TX3 AC29 AD27 PEX_RX3 C874 0. 1u_10V_X7R_04 PE0RX3 4 AH32 AG12
AB28 PCIE_RX3P PCIE_TX3P AD26 PEX_RX3# C875 0. 1u_10V_X7R_04 K28 PCIE_VSS#12 GND#12 AH10
4 PE0TX3# PCIE_RX3N PCIE_TX3N PE0RX3# 4 K32 PCIE_VSS#13 GND#13 AH28
L27 PCIE_VSS#14 GND#14 B10
AB30 AC25 PEX_RX4 C876 0. 1u_10V_X7R_04 M32 PCIE_VSS#15 GND#15 B12
4 PE0TX4 AA31 PCIE_RX4P PCIE_TX4P AB25 PE0RX4 4 PCIE_VSS#16 GND#16
PCI EXPRESS INTERFACE

PEX_RX4# C877 0. 1u_10V_X7R_04 N25 B14
4 PE0TX4# PCIE_RX4N PCIE_TX4N PE0RX4# 4 N27 PCIE_VSS#17 GND#17 B16
P25 PCIE_VSS#18 GND#18 B18
AA29 Y23 PEX_RX5 C878 0. 1u_10V_X7R_04 P32 PCIE_VSS#19 GND#19 B20
4
4
PE0TX5
PE0TX5#
Y28 PCIE_RX5P
Y30
PCIE_RX5N
PCIE_TX5P Y24
PCIE_TX5N
AB27
PEX_RX5#
PEX_RX6
C879
C880
0. 1u_10V_X7R_04
0. 1u_10V_X7R_04
PE0RX5 4
PE0RX5# 4
R27
T25
T32
U25
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
GND#20
GND#21
GND#22
GND#23
B22
B24
B26
B6
Sheet 12 of 50
4 PE0TX6 PE0RX6 4
W31 PCIE_RX6P PCIE_TX6P AB26 PEX_RX6# PCIE_VSS#24 GND#24
4
4
PE0TX6#
PE0TX7
W29
PCIE_RX6N PCIE_TX6N
Y27 PEX_RX7
C881
C882
0. 1u_10V_X7R_04
0. 1u_10V_X7R_04
PE0RX6# 4
PE0RX7 4
U27
V32
W25
W26
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
GND#25
GND#26
GND#27
B8
C1
C32
E28
External VGA M92-
V28 PCIE_RX7P PCIE_TX7P Y26 PEX_RX7# C883 0. 1u_10V_X7R_04 W27 PCIE_VSS#28 GND#28 F10
4 PE0TX7#
V30
PCIE_RX7N
U31 PCIE_RX8P
PCIE_TX7N
PCIE_TX8P
W24
W23
PE0RX7# 4 Y25
Y32
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
GND#29
GND#30
GND#31
GND#32
F12
F14
F16
F18
S2-1
PCIE_RX8N PCIE_TX8N GND#33 F2
GND#34 F20
U29 V27 M6 GND#35 F22
T28 PCIE_RX9P
PCIE_RX9N
PCIE_TX9P U26
PCIE_TX9N N11 GND#56
GND#57
GND#36
GND#37 F24
N12 F26
N13 GND#58 GND#38 F6
GND#59 GND#39
T30 PCIE_TX10P U24 N16 F8
R31 PCIE_RX10P
PCIE_RX10N PCIE_TX10N
U23 N18
N21
GND#60
GND#61
GND#62
GND GND#40
GND#41
GND#42
G10
G27
P6 GND#63 GND#43 G31
R29 PCIE_RX11P PCIE_TX11P T26 P9 GND#64 GND#44 G8
P28 T27 R12 H14
PCIE_RX11N PCIE_TX11N R15 GND#65 GND#45 H17
GND#66 GND#46
R17 GND#67 GND#47 H2
P30 T24 R20 H20
N31 PCIE_RX12P PCIE_TX12P T23 T13 GND#68 GND#48 H6
PCIE_RX12N PCIE_TX12N T16 GND#69 GND#49 J27
T18 GND#70 GND#50 J31
N29 P27 T21 GND#71 GND#51 K11
M28 PCIE_RX13P PCIE_TX13P P26 T6 GND#72 GND#52 K2
PCIE_RX13N PCIE_TX13N U15 GND#73 GND#53 K22
U17 GND#74 GND#54 K6
M30 P24 U20 GND#75 GND#55 T11
L31 PCIE_RX14P
PCIE_RX14N
PCIE_TX14P P23
PCIE_TX14N U9 GND#76
GND#77
GND#85
GND#86 R11
V13 GND#78
V16
L29 PCIE_RX15P GND#79
PCIE_TX15P M27 V18 GND#80
K30 PCIE_RX15N PCIE_TX15N N26 Y10 GND#81
Y15 GND#82
Y17 A32
Y20 GND#83 VSS_MECH#1 AM1
CLOCK GND#84 VSS_MECH#2
VSS_MECH#3 AM32
AK30
25 PCIE_CLK_VGA AK32 PCIE_REFCLKP
25 PCIE_CLK_VGA# PCIE_REFCLKN
CALIBRATION
Y22 R612 1.27K_1%_04 M92-S2
PCIE_CALRP
R732 10K_04 N10 AA22 R613 2K_1%_04
NC_PWRGOOD PCIE_CALRN 1.1VS_VGA
PEX_RST AL27 PERSTB
M92-S2
3.3V
C886
1u_6. 3V_Y5V_04
5
U47
21, 31 SB_PCIRST# 1
4 Z1202 R614 *10mil_short -NMNP PEX_RST
22 PCIE_RST# 2
MC74VHC1G08DFT1G R615
3
10K_04
R616 *0_04
External VGA M92-S2-1 B - 13

Schematic Diagrams
Re serv e
M 92 c heck
3. 3VS _V GA NOTE: Designs that do not include an EEPROM must still provide
PI N ST RAPS VRAM ID (Default 0, 0) access to the ROM interface signals for debug purposes
33
. VS _VG A PC I E FU LL T X OU TP U T SWI N G
R6 17 10K _04 GP I O0
Q-Die E-Die
U4 6B KBC_SPI_*_R = 0.1"~ 0.5"
PC I E TR AN S MI TT ER DE - EMPH A SI S E NA BL ED
R625 0 1 512Kbit
R6 18 10K _04 GP I O1 C 887 *0. 1u_1 6V_ Y5 V_0 4
R726 0 0 U 48
PC I E G EN 2 EN A BLE D Sam sung DDR 2 6 4x16 500 MHz A F2 M9 2_F LAS H VD D 8 5 G PI O 9
M 93 -S3 / M9 2- S 2 TX CA P_ DP A3 P V DD SI
R6 20 *10K _04 GP I O2 6-0 4-41 164- E30 AE 9 D VC N TL_ 0/ D V PD AT A_1 8 TXC AM_D P A3N A F4
L9 2 G PI O 8
R6 22 *10K _04 GP I O8 N9 D VC N TL_ 1 /NC A G3 SO
AE 8 D VC N TL_ 2 /NC TX 0P_ DP A2 P A G5 R6 23 *10 K_0 4 M9 2_F LAS H 3 1 G PI O 22
D VD AT A_ 12 / D V PD AT A_1 6
DPA TX0M_D P A2N WP # CE #
VG A E NA BL ED R 625 *0_04 A D9 R6 29 *10 K_0 4
R6 27 *10K _04 GP I O9 3. 3V S_ VG A A C1 0 D VD AT A_ 11 / D V PD AT A_2 0 A H3 6 G PI O 10
A D7 D VD AT A_ 10 / D V PD AT A_2 2 TX 1P_ DP A1 P A H1 SCK
D VD AT A_ 9 / D VP D ATA _12 TX1M_D P A1N
SE RI A L R O M T YP E O R MEMO R Y A PE RT UR E SI ZE SE LEC T A C8 M9 2_H O LD # 7 4
D VD AT A_ 8 / D VP D ATA _14 H O LD # VS S
R6 30 10K _04 GP I O1 1 DVP DATA [23: 20] . A C7 D VD AT A_ 7 / D VP C NT L_0 TX 2P_ DP A0 P A K3 G PIO _22_ ROMC SB(B IOS ROM Chip Sel ect)
R6 31 *10K _04 GP I O1 2 Vid eo M emor y I D AB 9 A K1 *EN 25 P05 -5 0G CP A 10 -K e xter nal pull -up (3.3 V) is r equi red if
R6 32 *10K _04 GP I O1 3 AB 8 D VD AT A_ 6 / D VP D ATA _8 TX2M_D P A0N
Set DVP as 1.8 -V
AB 7 D VD AT A_ 5 / D VP D ATA _6 A K5
a n e xter nal BIOS ROM chi p is use d.
AU D [1 ] A UD [ 0]
(VD DR4/ 5)
gen eral I/O . R 726 *0_04
AB 4
AB 2
D VD AT
D VD AT
A_
A_
4
3
DV PD A TA_ 4
/ D VP D ATA _19
TX CB P_ DP B3 P
TXC BM_D P B3N A M3 SERI AL E EPRO M 51 2 K/ 1M M ust be unco nnec ted if n o ex tern al B IOS ROM chip
i s u sed.
0 0 No a udi o f unct i on D VD AT A_ 2 / D VP D ATA _21
Y8 A K6
0 1 Aud o
i f or D s
ip al y Po rt and H D MI i f d ongl e s
i det ect ed D VD AT A_ 1 / D VP D ATA _2 TX 3P_ DP B2 P
1 0 Aud o
i f or D s
ip al y Po rt onl y Y7 D VD AT A_ 0 / D VP D ATA _0 TX3M_D P B2N A M5
1 1 Aud o
i f or bot h D si pla yP or t an d HD MI
DPB
TX 4P_ DP B1 P A J7
R6 33 *10K _04 V_V SY DVO A H6
TX4M_D P B1N L 81
R6 34 *10K _04 V_H S Y A K8 H CB 100 5KF - 121 T20
TX 5P_ DP B0 P (1. 8V @ 4 5m A V DD 1 DI )
TX5M_D P B0N A L7 1 .8 VS _VG A . VD D 1D I
R6 35 *10K _04 GE N ER I CC L10 9
H C B1 005 KF -1 21T2 0 L 82
M9 3-S 3 M
/ 92 -S 2 (1 8. V @ 2m A A 2V D D Q )
Sheet 13 of 50
IG N O RE VI P D EV I CE STR A PS W 6 18
. VS _VG A H CB 100 5KF - 121 T20
VS YN C _D AC 2 D PC _P VD D / D VP D ATA _11
. A 2VD D Q (1. 8V @ 7 0m A A V DD )
R6 36 10K _04 2 1 V6 D PC _P VS S / GN D M9 2-S 2 M
/ 93 -S 3 AV DD
C1 173
C1 174
C1 175
C 888
C 889
C 890
S9 S1 V4 .
HS Y NC _D A C2 DV PD A TA_ 3/ TXC C P_D P C3 P
C 891
C 892
C 893
R6 37 10K _04 A C6 D PC _V DD 1 8#1/ D VP D AT1 0 D VP C NT L_2/ TX CC M_D PC 3N U5
A C5
EN AB LE E XTE R NA L BI O S R O M D PC _V DD 1 8#2/ D VP D AT2 3 W 3
D V PD AT A_7 / TX0 P_D P C2 P
10u_ 6. 3V_ X5R _0 6
1u_6 .3 V_Y 5V _04
0. 1u_1 0V_ X7R _0 4
10 u_6. 3V _X 5R _06
1u _6. 3V _Y 5V_ 04
0. 1u _10 V_X 7R _04

R6 38 *10K _04 GP I O2 2 AA 5 V2
D PC _V DD 1 0#1/ D VP D AT1 5 D VP DA TA _1 / T X0M_D PC 2N
External VGA M92-
10 u_6. 3V _X 5R _06
1u _6. 3V _Y5 V_0 4
0. 1u _10V _X 7R _04
AA 6 D PC _V DD 1 0#2/ D VP D AT1 7 Y4
D VP C NT L_MV1 / TX1 P_D P C1 P W 5
D VP DA TA _9 / T X1M_D PC 1N
U1 D PC _V SS R #1 / D V PC LK D VP D ATA _13 / TX2 P_D P C0 P A A3

W 1 Y2
U3 D PC _V SS R #2 / D V PD AT 5 D VP CN TL _1 / T X2M_D PC 0N 2 1
Y6 D PC _V SS R #3 / G N D A A1 2 R 643 0_04 A2 VS SQ S 10
S2-2
D PC _V SS R #4 / G N D VD D R4 / D PC D _C ALR V DD R 4 S1
3. 3V S_ VG A R 6 42 4. 7K_ 04 AA 1 D PC _V SS R #5/ DV PC N TL_ MV 0 A VS SQ
3. 3VS _V GA R 6 45 4. 7K_ 04
19 I 2C C _S C L
DPC
R 641 10 K_0 4 GP O
I _2 3_C LK RE Q B 19 I 2C C _S D A
R 644 10 K_0 4 GP I O7 _BL ON 3. 3V S_ VG A
I2 CC _S C L R1
I2 CC _S D A R3 SC L
SD A I2C
G
Q 47 R A M26 VG A_ R
*MTN 7002 ZH S3 R7 36 R 737 GE NERA L P URPO SE I /O A K2 6 VG A _R
S MD _V G A_T HE R M S D GP I O0 U6 RB V G A_R 19
2 7 S MD_ VG A_ TH ER M *10K _04 *10 K_0 4 GP I O1 U1 0 G PI O _0 A L25 VG A_ G VG A _G
G
G PI O _1 G V G A_G 19
Q 48 GP I O2 T1 0 G PI O _2 GB A J25
*MTN 70 02Z HS 3 U8 VG A _B
SMC _V GA _TH E RM S D U7 G PI O _3_S MBD A TA A H 24 VG A_ B V G A_B 19
2 7 S MC_ VG A_ TH ER M GP I O5 T9 G PI O _4_S MBC LK B A G 25
T8 G PI O _5_A C _B ATT BB C 894 C8 95 C 896 R 649 R 650 R 65 1
GP I O7 _BL ON T7 G PI O _6 DAC1 A H 26 V _H SY
R 729 10K _04 GP I O8 P1 0 G PI O _7_B LO N HS Y NC A J27 V _VS Y V_H S Y 19 22p _50V _N P O_ 04
22p_ 50V _N PO _04
22 p_50 V_N P O_ 04 15 0_1% _04 150 _1%_0 4 1 50_1 %_04
33
. VS _V GA GP I O9 G PI O _8_R O MSO VS Y NC V_V SY 19
P4
GP I O1 0 P2 G PI O _9_R O MSI
D
GP I O1 1 N6 G PI O _10_ R OMS CK A D 22 R6 52 49 9_1%_ 04
Q 46 GP I O1 2 N5 G PI O _11 R SE T A VD D
G MTN 70 02Z H S3 GP I O1 3 N3 G PI O _12 A G 24
27 ,3 6 AC _I N # Y9 G PI O _13 AV DD A E2 2
S
N1 G PI O _14_ H PD 2 A VS SQ V DD 1D I
41 M92 _G PI O 15 M4 G PI O _15_ PW RC N TL_ 0 A E2 3 AV SS Q
G PI O _16_ SS I N V D D1 DI
R6 G PI O _17_ TH ER MAL _I NT VS S1 DI A D 23
W1 0
M2 G PI O _18_ H PD 3 3. 3V S_ VG A
P8
G PI O _19_ C TF M9 2-S2 M
/ 93 -S3 A M12
41 M92 _G PI O 20 G PI O _20_ PW RC N TL_ 1 R 2 / NC
P7 G PI O _21_ BB _E N R 2B / NC A K1 2
GPIO20 / GPIO15 FOR GP I O2 2 N8 VD D 3
GP I O_ 23_C LK R EQ B N 7 G PI O _22_ R OMC SB A L11 R 73 5
VCORE_VGA? ? ? ? G PI O _23_ C LKR E QB G 2 / NC A J11 22 _04
G 2B / NC
GPIO _23_ CLKR EQB Rese rved . R 712 2. 2K_ 04
3. 3V S_ VG A R 65 6 *1 0K_ 04 A K1 0 C 1161 0. 1u_ 10V _X7R _0 4 R 713 2. 2K_ 04
35 MIL GP I O2 4_TR S TB L 6 B2 / NC A L9
J TAG D EB UG 35 MIL GP I O2 5_TD I L5 JTA G _TR S TB B 2B / NC
P O RT 35 MIL GP I O2 6_TC K L3 JTA G _TD I U 50
35 MIL GP I O2 7_TMS L1 JTA G _TC K A H 12 1 8 S MC _V G A_T HE R M
35 MIL GP I O2 8_TD O K4 JTA G _TMS C / NC A M10 G PU _D P LU S 2 V DD S CL K 7 S MD _V G A_T HE R M
R 65 7 *5 .1 1K_ 1%_0 4 A F2 4 JTA G _TD O DAC2 Y / NC A J9 G PU _D MI NU S 3 D+ SD AT A 6 R 720 0 _04
3. 3VS _V GA
TE STE N CO MP / NC 4 D- ALE R T# 5 E C_ VG A_ ALE R T# 27
R 65 8 *5 .1 1K_ 1%_0 4 A B1 3 C 116 2 2200 p_50 V_X 7R _04 TH E RM# G ND
W 8 G EN ER I C A A L13 HS Y NC _D A C2 AD M103 2AR M
GE N ER I CC W 9 G EN ER I C B H 2S Y NC A J13 VS YN C _D AC 2 R 722 *0 _04
W 7 G EN ER I C C V2S Y NC
G EN ER I C D
A D1 0 VD D 1D I
G EN ER I C E_ HP D 4 A D 19
R6 60 10K _04 A C1 4 VD D 2D I / NC A C 19 R 725 2 .2 K_0 4 3. 3V S_V G A
H PD 1 V SS 2D I / NC
3. 3V S_ VG A
A E2 0
Optional External Ther mal Sensor
1. 8V S_V G A R 66 1 4 99_1 %_04 A2V D D / NC A2V D DQ
A E1 7
A C1 6 A2 VD D Q / NC
P L A C E V R EF G VR E FG
R6 62 C 899 A 2VS SQ A E1 9 2 1
D I V I DE R A N D C A P S 11
S1
C L O S E T O A SI C 249_ 1%_04 0. 1u _10V _X7 R_ 04
A G 13 R 663 715_ 1%_04 A 2V SS Q
L86 R 2S ET / NC
1 .8 VS _V GA HC B 1005 KF -1 21T2 0
DDC /AUX
.
D PL L_P VD D D D C1 CL K A E6
C9 00
C9 01
C9 02
1 .1 VS _VG A L87 . H C B1 005K F- 12 1T20 PLL /CLO CK A E5

A F1 4 DD C 1D AT A
( 1 8. V @ 12 0m A DP L L _P V D D) D PLL _PV D D
C 90 5 1 0u_6 .3 V_ X5R _0 6
C 90 6 1 u_6 .3 V_Y 5V _04
C9 07
A E1 4 A D2
(1 . 1V @ 30 0m A D PL L _V D D C ) D PLL _PV S S AU X1 P
10u_ 6. 3V_ X5R _ 06
1u_6 .3 V_Y 5V _04
0. 1u_1 0V _X7 R_ 04
D PL L_V DD C AU X1N A D4
D P LL_P VS S
0. 1u_1 0V_ X7R _0 4

A D1 4 D PLL _VD D C D D C2 CL K A C 11
A C 13
DD C 2D AT A
XTA LI N A M2 8 A D 13
XTA LO UT A K2 8 XTA LI N AU X2 P A D 11
2 1 XTA LO U T AU X2N
S12 S1 2 1 D DC C LK _AU X5 P A E1 6
D P LL_P VS S S1 3 S1 A D 16
D PL L_P VS S D D CD A TA_ AU X5N
A C1 V GA _D D CC LK 1 9 X TAL N
I
GP U _D PLU S T4 D D C6 CL K A C3
GP U _D MI N U S T2 D PLU S THE RMAL DD C 6D AT A V GA _D D CD A TA 19 R 659 1M_04 X TAL OU T
D MI N U S A D 20
D DC C LK _AU X3 P A C 20 X7
R5 D D CD A TA_ AU X3N 1 2
TSV D D A D1 7 TS _FD O A B2 2
TS VD D N C #1
A C1 7 TS VS S N C #2 A C 22 H SX8 40G A_ 27MH Z
1 .8 VS _VG A L88 . H C B1 005K F- 12 1T20 C 897 C 898
C 90 8
C 90 9
C9 10
T SV SS 22p _50V _N PO _0 4 22p _50V _N P O_ 04

(1 . 8V @ 20 m A T S V D D)
1 0u_6 .3 V_ X5R _0 6
1 u_6 .3 V_Y 5V _04
0. 1u_1 0V_ X7R _0 4
M9 2- S2
2 1
S 14 S1
TS VS S
B - 14 External VGA M92-S2-2

Schematic Diagrams
L89
1.8VS_ VGA HCB1 005KF-1 21T20 ( 1. 8V @2 00 m A DPE_V DD18 f or LV DS) DPE_VDD18 For 92, DPx_VDD10 = 1.1V
. U46G
For Future ASIC,
C9 11
Sheet 14 of 50
C9 12 C913 DP E/ F POWER DP A/B POWER
DPx_VDD10 = 1.0V
10u_6 .3V_X5R_06 1u_ 6.3V_Y5V_04 0.1u_ 10V_X7R_04 AG15 AE11
AG16 DPE_VDD18#1 NC_ DPA_VDD1 8#1 AF11
DPE_VDD18#2 NC_ DPA_VDD1 8#2
DPF_VDD10 AG20
DPE_VDD10#1 DPA_VDD1 0#1
AF6
DPA_VDD10 ( 1.1 V@ 2 00 m A DPA _V DD10 )
L90
HCB10 05KF-121 T20
.
1.1VS_VGA External VGA M92-
( 1. 1V @1 00 m A DPE_V DD10 For LV DS) AG21 AF7
DPE_VDD18
R671 *0_04 AG14
DPE_VDD10#2
DPE_VSSR#1
DPA_VDD1 0#2
DPA_VSSR#1 AE1
C914 C915
10u_ 6.3V_X5R_06 1 u_6.3V_Y5V_04

C916
0.1u _10V_X7R_04
S2-3
AH14 AE3
L91 AM14 DPE_VSSR#2 DPA_VSSR#2 AG1
1.8VS_ VGA HCB1005KF- 121T20 ( 1. 8V @2 00 m A DPF_V DD18 f or LV DS) AM16 DPE_VSSR#3 DPA_VSSR#3 AG6
AM18 DPE_VSSR#4 DPA_VSSR#4 AH5
. DPE_VSSR#5 DPA_VSSR#5
C9 17 C9 18 C919
DPF_VDD18
10u_6 .3V_X5R_06 1u_ 6.3V_Y5V_04 0.1u_ 10V_X7R_04 AF16 DPF_VDD18#1 NC_ DPB_VDD1 8#1 AE13
AG17 AF13
DPF_VDD18#2 NC_ DPB_VDD1 8#2
L92 DPF_VDD10 DPA_VDD10

1.1VS_ VGA HCB1005KF- 121T20 ( 1. 1V @1 00 m A DPF_V DD10 For LV DS) AF22 AF8
AG22 DPF_VDD10#1 DPB_VDD1 0#1 AF9
. DPF_VDD10#2 DPB_VDD1 0#2
C9 20 C9 21 C922
AF23 AF10 Co nnect D Pxx_CALR to VSS
DPF_VSSR#1 DPB_VSSR#1 th rough a 150-O
10u_6 .3V_X5R_06 1u_ 6.3V_Y5V_04 0.1u_ 10V_X7R_04 AG23 DPF_VSSR#2 DPB_VSSR#2 AG9
AM20 DPF_VSSR#3 DPB_VSSR#3 AH8 (1 %) resi stor.
AM22 AM6
AM24 DPF_VSSR#4 DPB_VSSR#4 AM8
DPF_VSSR#5 DPB_VSSR#5
D ual-link panel.
C onnect D PEF_CAL R to VS S throu gh a 150 -O
( 1%) resi stor.
R6 72 150_ 1%_04 AF17 DPEF_ CALR DPAB_CALR AE10 R673 150 _1%_04
L94
1.8VS_ VGA HCB1005KF- 121T20 ( 1. 8V @2 0m A ) DPE_PVDD 2 0m A 1.8VS_ VGA
AG18 DP PLL P OWER AG8
.
AF19 DPE_PVDD DPA_PVDD AG7
C926 C927 C928 DPE_PVSS DPA_PVSS C925
1.8 VS_VGA
10u_6. 3V_X5R_06 1u_6. 3V_ Y5V_0 4 0 .1u_10 V_X7R_ 04 DPE_PVDD 2 0m A 0. 1u_10V_X7R_ 04
2 1 AG19 AG10
S16 S1 AF20 NC_DPF_PVDD DPB_PVDD AG11
NC_DPF_PVSS DPB_PVSS
C1178
DPE_PVSS DPE_PVSS
0.1u_1 0V_X7 R_04
M92-S2

Schematic Diagrams
L 11 1 ( for DDR2 a nd GDDR3: 1 .8V@2.2 A VDDR1)

1 . 8V S _V G A H C B 2 01 2K F -5 00 T 40
1 2 C 93 2 C 9 33 C 94 4 C9 4 5 C 9 34 C 93 5 C 9 36 C 93 7 C9 3 8 C 9 39 C 94 0 C 9 41 C 94 2
1 0u _6 . 3V _ X 5R _0 6
1 0u _ 6. 3 V _X 5 R _0 6
0. 1 u _1 0V _ X 7R _ 0 4
0 . 1 u_ 10 V _X 7 R _ 04
0 . 1u _1 0V _ X 7R _0 4
10 u_ 6. 3 V _X 5 R _ 06
10 u_ 6 .3 V _ X5 R _ 06
1 u_ 6. 3 V _Y 5 V _0 4
1 u_ 6. 3 V _Y 5 V _0 4
1 u_ 6 . 3V _ Y5 V _0 4
0. 1 u_ 10 V _X 7 R _ 04
1u _6 . 3V _ Y 5V _ 04
1u _6 . 3 V_ Y 5V _ 04
(1.8V@500m APCIE_VDDR) L 96
P C I E _ VD D R H C B 1 00 5 KF -1 21 T 20 1. 8 V S_ V GA
U 4 6D C 95 7 C 9 58 C 95 9 C9 6 4
0 . 1u _1 0 V_ X 7R _0 4
1 0u _ 6. 3 V _X 5 R _0 6
.
0. 1 u_ 10 V _X 7 R _ 04
1u _6 . 3 V_ Y 5V _ 04
MEM I/O
PCIE
H1 3 AB2 3
H1 6 V DD R 1# 1 P CIE _ V DDR# 1 A C2 3
H1 9 V DD R 1# 2 P CIE _ V DDR# 2 A D2 4
V DD R 1# 3 P CIE _ V DDR# 3
Sheet 15 of 50
J1 0 AE2 4
J2 3 V DD R 1# 4 P CIE _ V DDR# 4 AE2 5
J2 4 V DD R 1# 5 P CIE _ V DDR# 5 AE2 6
L 97 (1.8V@110mAVDD_CT ) J9 V DD R 1# 6 P CIE _ V DDR# 6 AF2 5
V DDC_ CT V DD R 1# 7 P CIE _ V DDR# 7
1. 8 V S _V GA H C B1 0 05 K F- 1 2 1T 20 K1 0 A G2 6
C 9 65 C 96 6 C 9 67 C 96 8 K2 3 V DD R 1# 8 P CIE _ V DDR# 8 (1.1V@2APCIE_VDDC)
External VGA M92-

. V DD R 1# 9 1. 1 V S_ V GA
10 u _6 . 3V _ X 5R _ 0 6
K2 4
1 u _6 . 3V _ Y 5V _ 04
1 u_ 6. 3 V _Y 5 V _0 4
1u _6 . 3V _ Y 5V _ 04
K9 V DD R 1# 1 0 L 23
L1 1 V DD R 1# 1 1 P CIE _ V DDC# 1 L 24 C 97 0 C 9 71 C 97 2 C9 7 3 C 9 74 C 97 7
V DD R 1# 1 2 P CIE _ V DDC# 2
1 0 u_ 6. 3 V _X 5 R _ 06
L 98 (1.8V@170mAVDDR4) L1 2 L 25
1 u_ 6. 3 V _Y 5 V _0 4
1 u_ 6 . 3V _ Y5 V _0 4
1u _ 6. 3 V _Y 5 V_ 0 4
1u _6 . 3V _ Y 5V _ 04
1u _6 . 3 V_ Y 5V _ 04
1. 8 V S _V GA H C B 1 0 05 K F- 1 2 1T 20 V DDR4 L1 3 V DD R 1# 1 3 P CIE _ V DDC# 3 L 26
S2-4
. C 9 78 C 97 9 C 9 80 L2 0 M 22
0 . 1u _ 10 V _X 7 R _0 4
1 u_ 6. 3 V _Y 5 V _0 4
L2 1 N 22
10 u _6 . 3V _ X 5R _ 06
L2 2 V DD R 1# 1 6 P CIE _ V DDC# 6 N 23
V DD R 1# 1 7 P CIE _ V DDC# 7 N 24
P CIE _ V DDC# 8 R 22
P CIE _ V DDC# 9 T 22
LEVEL P C I E _V D D C #1 0 U 22
P C I E _V D D C #1 1
TRANSLATION V2 2
A A2 0 P C I E _V D D C #1 2
A A2 1 V D D _C T # 1 (0. 9V-1.2 V@1 6A VDDC) V C O R E _V GA
A B2 0 V D D _C T # 2 AA1 5 C 9 81 C 98 2 C9 8 3 C 9 84 C 98 5 C 9 86 C 98 7 C9 8 8 C 9 89 C 99 0 C 9 91 C 99 2 C 9 93
A B2 1 V D D _C T # 3 CORE V DDC# 1 N 15
1 u_ 6. 3 V _Y 5 V _0 4
1 u_ 6 . 3V _ Y5 V _0 4
1u _ 6. 3 V _Y 5 V_ 0 4
1 u _6 . 3V _ Y 5V _ 04
1 u_ 6. 3 V _Y 5 V _0 4
1 u_ 6. 3 V _Y 5 V _0 4
1u _6 . 3 V_ Y 5V _ 0 4
1 u_ 6 . 3V _ Y5 V _ 04
1u _ 6. 3 V _Y 5 V _0 4
1 u _6 . 3V _ Y 5V _ 04
1 u_ 6. 3 V _Y 5 V _0 4
1u _6 . 3 V_ Y 5V _ 04
1u _6 . 3V _ Y 5V _ 04
3 . 3V S _ VG A (3.3V@50m AVDDR3) V D D _C T # 4 V DDC# 2 N 17
C 9 94 C 99 5 C 9 96 C 99 7 M93-S3/M92-S2 V DDC# 3 R 13
V DDC# 4
1 0u _6 . 3V _ X 5R _ 0 6
1 u_ 6. 3 V _Y 5 V _0 4
POWER
R 16
1u _6 . 3V _ Y 5V _ 04
1u _6 . 3 V_ Y 5V _ 04
A A1 7 V DDC# 5 R 18
A A1 8 V D D R 3# 1 I/ O V DDC# 6 R 21
A B1 7 V D D R 3# 2 V DDC# 7 T 12
VD D R 4 VDD R5 A B1 8 V D D R 3# 3 V DDC# 8 T 15
Ra V D D R 3# 4 V DDC# 9 T 17
R 67 4 0_ 04 V1 2 V D D C #1 0 T 20
V D D R 4# 1 / V D D R 5 V D D C #1 1
V D D R 4 f or D V P D A T A [1 2 . . 23 ] Y1 2 U 13 C 10 1 5 C 1 0 16 C 1 01 7 C 10 18 C 1 01 9 C 10 2 0 C9 9 8
V D D R 4# 2 V D D C #1 2
1 0u _ 6. 3 V _X 5 R _0 6
10 u _6 . 3V _ X 5R _ 0 6
1 0 u_ 6. 3 V _X 5 R _ 06
1 0u _6 . 3V _ X 5R _0 6
L 99 (1.8V@170mAVDDR5) R 67 5 *0_ 0 4 U1 2 U 16
10 u_ 6 . 3V _ X5 R _ 06
10 u_ 6. 3 V _X 5 R _ 06
*1 u _6 . 3V _ Y 5V _ 04
1. 8 V S _V GA H C B 1 0 05 K F- 1 2 1T 20 V DDR5 V D D R 5 f or D V P D A T A [0 . . 1 1] Rb V D D R 4# 3 / V D D R 5 V D D C #1 3 U 18
C 10 12 C 1 01 3 A A1 1 V D D C #1 4 U 21
N C #1 / V D D R 4 V D D C #1 5
0 . 1u _ 10 V _X 7 R _0 4
. Y1 1 V1 5
1 u_ 6. 3 V _Y 5 V _0 4
D VC LK / V D D R 4 V D D C #1 6 V1 7
V1 1 V D D C #1 7 V2 0
N C #3 / V D D R 5 V D D C #1 8
U1 1 V2 1
F
or M92-S2: Install Raand Remove Rb N C #4 / V D D R 5 V D D C #1 9 Y 13
V D D C #2 0 Y 16 L 11 2
F
or M93-S3: Install Rb a
nd RemoveRa V D D C #2 1 Y 18 H C B 1 00 5 KF -1 21 T 20 VC OR E _ VG A
L 10 0 V D D C #2 2 Y 21 C 1 1 84 C 1 18 1
1 . 8V S _V G A H C B 1 00 5 KF -1 21 T 20 V DD RHA MEM CLK V D D C #2 3 .
1 u_ 6 .3 V _ Y5 V _0 4
10 u _6 . 3V _ X 5R _ 06
L1 7
. V DD RHA
C 1 02 1
1 u_ 6. 3 V _Y 5 V _ 04 L1 6 ISOLATED
2 1 V S S RHA
CORE I/O
L 10 1 (1.8V@40m APCIE_PVDD) S1 8 S1 M 13
1. 8 V S _V GA H C B 1 0 05 K F- 1 2 1T 20 GN D _V S S R H A P CIE _ P V DD PLL V DDCI# 1 M 15
C 1 02 2 C 10 23 C 1 02 4 A M3 0 V DDCI# 2 M 16
P CIE _ P V DD V DDCI# 3
0 . 1u _ 10 V _X 7 R _0 4
. M 17
10 u _6 . 3V _ X 5R _ 06
1 u_ 6. 3 V _Y 5 V _0 4
V DDCI# 4
M 18
L 10 2 L8 V DDCI# 5 M 20 (0.9V- 1.2V@2A VDDCI) L 10 3
V C OR E _ V GA H C B 1 00 5 KF -1 21 T 20 (0.9V-1.2V@120mA SPV10) N C _M PV 1 8 V DDCI# 6 M 21 V DDC I H C B 1 00 5 KF -1 21 T 20 V C OR E _ V GA
C 1 02 5 C 10 26 C 1 02 7 V DDCI# 7 N 20 C 1 02 8 C 10 29 C 1 03 0 C 10 3 1
V DDCI# 8
10 u _6 . 3V _ X 5R _ 0 6
0 . 1 u_ 10 V _X 7 R _ 04
. H7
.
1 u_ 6. 3 V _Y 5 V _0 4
1u _ 6. 3 V _Y 5 V_ 0 4
1 u _6 . 3V _ Y 5V _ 04
1 u_ 6. 3 V _Y 5 V _0 4
10 u_ 6. 3 V _X 5 R _ 06
N C _S P V 1 8
H8
SPV1 0
J7
SPVSS
2 1
S1 9 S1 BACK BIAS
M1 1
BBP# 1
M1 2
SPVSS BBP# 2
L 10 5
V C OR E _ V GA H C B 1 00 5 KF -1 21 T 20 (0.9V-1.2V@120mA BBP) M9 2-S 2
C 1 03 2 C 10 3 3
0 . 1u _1 0V _ X 7R _0 4
.
1u _6 . 3V _ Y 5V _ 04

Schematic Diagrams

U 46 C
17 MD A[ 63 .. 0 ] MD A 0 MA A0 MA A[ 1 2.. 0 ] 17
K27 K1 7
MD A 1 D QA_ 0 MAA _ 0 MA A1
J 29 J 20
MD A 2 H 30 D QA_ 1 MAA _ 1 H23 MA A2
MD A 3 H 32 D QA_ 2 MAA _ 2 G2 3 MA A3
MEMORY INTERFACE
G29 G2 4
F28 H24
F32 J 19
MD A 7 F30 D QA_ 6 MAA _ 6 K1 9 MA A7
MD A 8 C 30 D QA_ 7 MAA _ 7 J 14 MA A8
MD A 9 F27 D QA_ 8 MAA _ 8 K1 4 MA A9
MD A 1 0 D QA_ 9 MAA _ 9 MA A1 0
A28 J 11
MD A 1 1 C 28 D QA_ 1 0 MA A_ 1 0 J 13 MA A1 1
MD A 1 2 E27 D QA_ 1 1 MA A_ 1 1 H11 MA A1 2
MD A 1 3 G26 D QA_ 1 2 MA A_ 1 2 G1 1
MD A 1 4 D QA_ 1 3 MAA _13 / BA 2 A_ B A2 17
D 26 J 16
MD A 1 5 D QA_ 1 4 MAA _14 / BA 0 A_ B A0 17
F25 L15 A_ B A1 17
1. 8VS _VGA MD A 1 6 A25 D QA_ 1 5 MAA _15 / BA 1
D QA_ 1 6 D QMA #[7. . 0 ] 17
MD A 1 7 C 25 E3 2 D QMA #0
MD A1 8 E25 D QA_ 1 7 D QMA _ 0 E3 0 D QMA #1
MD A1 9 D QA_ 1 8 D QMA _ 1 D QMA #2
D 24 A2 1
R 678 MD A 2 0 E23 D QA_ 1 9 D QMA _ 2 C21 D QMA #3
MD A 2 1 F23 D QA_ 2 0 D QMA _ 3 E1 3 D QMA #4
*4 . 7K _0 4 MD A 2 2 D 22 D QA_ 2 1 D QMA _ 4 D12 D QMA #5
MD A 2 3 F21 D QA_ 2 2 D QMA _ 5 E3 D QMA #6
D R AM_ R S T MD A 2 4 D QA_ 2 3 D QMA _ 6 D QMA #7
E21 F4
MD A 2 5 D 20 D QA_ 2 4 D QMA _ 7
QSA [7 . . 0 ] 1 7
C 1 03 8 R 679
MD A 2 6
MD A 2 7
MD A 2 8
F19
A19
D QA_ 2 5
D QA_ 2 6
D QA_ 2 7
R D QSA _ 0
R D QSA _ 1
H28
C27
QS A0
QS A1
QS A2
Sheet 16 of 50
D 18 A2 3
* 1u _6 . 3 V_ Y 5V_ 04
*4 . 7K _0 4 MD A 2 9
MD A 3 0
MD A 3 1
F17
A17
C 17
D QA_ 2 8
D QA_ 2 9
D QA_ 3 0
R D QSA _ 2
R D QSA _ 3
R D QSA _ 4
E1 9
E1 5
D10
QS A3
QS A4
QS A5
External VGA M92-
MD A 3 2
MD A 3 3
MD A 3 4
E17
D 16
F15
D QA_ 3 1
D QA_ 3 2
D QA_ 3 3
R D QSA _ 5
R D QSA _ 6
R D QSA _ 7
D6
G5
QS A6
QS A7 S2-5
MD A 3 5 A15 D QA_ 3 4 H27 QS A#0 Q S A# [ 7.. 0 ] 17
MD A 3 6 D 14 D QA_ 3 5 W D QSA _ 0 A2 7 QS A#1
MD A 3 7 D QA_ 3 6 W D QSA _ 1 QS A#2
F13 C23
MD A 3 8 A13 D QA_ 3 7 W D QSA _ 2 C19 QS A#3
MD A 3 9 C 13 D QA_ 3 8 W D QSA _ 3 C15 QS A#4
MD A 4 0 E11 D QA_ 3 9 W D QSA _ 4 E9 QS A#5
MD A 4 1 A11 D QA_ 4 0 W D QSA _ 5 C5 QS A#6
MD A 4 2 D QA_ 4 1 W D QSA _ 6 QS A#7
C 11 H4
MD A 4 3 F11 D QA_ 4 2 W D QSA _ 7
MD A 4 4 A9 D QA_ 4 3 L18
MD A 4 5 D QA_ 4 4 OD TA 0 OD TA0 17
1.8V S_ VGA C9 K1 6
MD A 4 6 D QA_ 4 5 OD TA 1 OD TA1 17
F9
MD A 4 7 D QA_ 4 6
D8 H26 C LKA 0 1 7
R 68 0 MD A 4 8 E7 D QA_ 4 7 C LKA 0 H25
MD A 4 9 D QA_ 4 8 C LK A0B C LKA 0# 1 7
A7
1 00 _1 % _0 4 MD A 5 0 C7 D QA_ 4 9 G9
MD A 5 1 D QA_ 5 0 C LKA 1 C LKA 1 1 7
F7 H9
MD A 5 2 A5 D QA_ 5 1 C LK A1B C LKA 1# 1 7
MD A 5 3 E5 D QA_ 5 2 G2 2
MD A 5 4 D QA_ 5 3 R AS A0B R AS A0# 1 7
C3 G1 7
MD A 5 5 D QA_ 5 4 R AS A1B R AS A1# 1 7
E1
MD A 5 6 D QA_ 5 5
R 68 1 C 10 39 G7 G1 9 C AS A0# 1 7
MD A 5 7 G6 D QA_ 5 6 C AS A0B G1 6
MD A 5 8 D QA_ 5 7 C AS A1B C AS A1# 1 7
1 00 _1 % _0 4 0. 1u_1 0V _ X7 R _ 0 4 G1
MD A 5 9 G3 D QA_ 5 8 H22
MD A 6 0 D QA_ 5 9 C SA 0B _ 0 C SA 0 #_0 17
J6 J 22
MD A 6 1 J1 D QA_ 6 0 C SA 0B _ 1
MD A 6 2 J3 D QA_ 6 1 G1 3
MD A 6 3 D QA_ 6 2 C SA 1B _ 0 C SA 1 #_0 17
J5 K1 3
D QA_ 6 3 C SA 1B _ 1
1.8V S_ VGA
MV R EF K26 K2 0
MVR E FD A C K EA 0 C KE A0 17
MV R EF SA J 26 J 17
MVR E FS A C K EA 1 C KE A1 17
R 68 2
1.8V S_V GA R 68 3 *24 3_ 1 % _04 J 25 G2 5
N C _MEM_C A LR N 0 W E A0B W EA 0 # 1 7
1 00 _1 % _0 4 R 68 4 *24 3_ 1 % _04 K7 H10
N C _MEM_C A LR N 1 W E A1B W EA 1 # 1 7
R 68 5 2 43 _ 1%_ 04 J8 AB 16
K25 MEM_ C A LR P1 R SV D # 1 G1 4
N C _MEM_C A LR P0 R SV D # 2
R 68 6 *24 3_ 1 % _04 G2 0
R SV D # 3
L 10
R 68 7 C 10 40 D R AM_R S T D R AM_ R S T
TE ST_ MC L K K8
1 00 _1 % _0 4 0. 1u_1 0V _ X7 R _ 0 4 Debug TP TE ST_ Y C L K L7 C L KTE STA
C L KTE STB
DNI, FOR Future ASIC ONLY
M92 -S 2
R 68 8 R689
4 . 7K_ 04 4. 7K_0 4

Schematic Diagrams
512MB DDR2 MEMORY

MD A [ 63 . . 0] B GA 1 BG A2 BGA 3 B GA 4
16 MD A [ 63 . 0. ] A _B A 0 L2 B9 MD A 2 8 A _B A 0 L2 B9 MD A 6 A_ B A0 L2 B9 MD A 52 A _ BA 0 L2 B9 MD A 38
A_ B A0 A _B A 1 L3 BA0 D Q1 5 B1 MD A 2 6 A _B A 1 L3 BA0 D Q1 5 B1 MD A 2 A_ B A1 L3 BA0 D Q15 B1 MD A 49 A _ BA 1 L3 B A0 D Q15 B1 MD A 35
16 A_ B A0 A_ B A1 BA1 D Q1 4 D9 MD A 3 0 BA1 D Q1 4 D9 MD A 5 BA1 D Q14 D9 MD A 53 B A1 D Q14 D 9 MD A 37
16 A_ B A1 A_ B A2 MAA 1 2 R2 D Q1 3 D1 MD A 2 4 M AA 1 2 R2 D Q1 3 D1 MD A 1 MA A 12 R2 D Q13 D1 MD A 48 MA A 12 R2 D Q13 D 1 MD A 33

16 A_ B A2 MAA 1 1 P7 A1 2 D Q1 2 D3 MD A 2 7 M AA 1 1 P7 A 12 D Q1 2 D3 MD A 0 MA A 11 P7 A 12 D Q12 D3 MD A 51 MA A 11 P7 A 12 D Q12 D 3 MD A 32
MA A [1 2. . 0 ] MAA 1 0 M2 A1 1 D Q1 1 D7 MD A 3 1 M AA 1 0 M2 A 11 D Q1 1 D7 MD A 4 MA A 10 M2 A 11 D Q11 D7 MD A 55 MA A 10 M2 A 11 D Q11 D 7 MD A 39
16 MAA [ 1 2. . 0] M AA 9 P3 A 1 0/ A P D Q1 0 C2 MD A 2 5 MA A 9 P3 A 10 / A P D Q1 0 C2 MD A 3 MA A9 P3 A 10 / A P D Q10 C2 MD A 50 MAA 9 P3 A 10 / AP D Q10 C 2 MD A 34
C KE A 0 M AA 8 P8 A9 D Q9 C8 MD A 2 9 MA A 8 P8 A9 D Q9 C8 MD A 7 MA A8 P8 A9 D Q9 C8 MD A 54 MAA 8 P8 A9 D Q9 C 8 MD A 36
16 C KE A 0 C KE A 1 M AA 7 P2 A8 D Q8 F9 MD A 1 7 MA A 7 P2 A8 D Q8 F9 MD A 1 4 MA A7 P2 A8 D Q8 F9 MD A 45 MAA 7 P2 A8 D Q8 F9 MD A 63
16 C KE A 1 M AA 6 N7 A7 D Q7 F1 MD A 1 6 MA A 6 N7 A7 D Q7 F1 MD A 1 1 MA A6 N7 A7 D Q7 F1 MD A 42 MAA 6 N7 A7 D Q7 F1 MD A 60
C SA 0 #_ 0 M AA 5 N3 A6 D Q6 H9 MD A 1 8 MA A 5 N3 A6 D Q6 H9 MD A 1 5 MA A5 N3 A6 D Q6 H9 MD A 46 MAA 5 N3 A6 D Q6 H 9 MD A 62
16 C SA 0 #_ 0 C SA 1 #_ 0 M AA 4 N8 A5 D Q5 H1 MD A 1 9 MA A 4 N8 A5 D Q5 H1 MD A 1 3 MA A4 N8 A5 D Q5 H1 MD A 40 MAA 4 N8 A5 D Q5 H 1 MD A 59
16 C SA 1 #_ 0 M AA 3 N2 A4 D Q4 H3 MD A 2 0 MA A 3 N2 A4 D Q4 H3 MD A 8 MA A3 N2 A4 D Q4 H3 MD A 44 MAA 3 N2 A4 D Q4 H 3 MD A 57
WE A 0# M AA 2 M7 A3 D Q3 H7 MD A 2 2 MA A 2 M7 A3 D Q3 H7 MD A 9 MA A2 M7 A3 D Q3 H7 MD A 43 MAA 2 M7 A3 D Q3 H 7 MD A 58
16 WE A 0# WE A 1# M AA 1 M3 A2 D Q2 G2 MD A 2 1 MA A 1 M3 A2 D Q2 G2 MD A 1 0 MA A1 M3 A2 D Q2 G2 MD A 41 MAA 1 M3 A2 D Q2 G2 MD A 56
16 WE A 1# M AA 0 M8 A1 D Q1 G8 MD A 2 3 MA A 0 M8 A1 D Q1 G8 MD A 1 2 MA A0 M8 A1 D Q1 G8 MD A 47 MAA 0 M8 A1 D Q1 G8 MD A 61
R AS A 0 # A0 D Q0 A0 D Q0 A0 D Q0 A0 D Q0
Sheet 17 of 50 16
16
16
16
R AS A 0 #
R AS A 1 #
C AS A 0 #
C AS A 1 #
R AS A 1 #
C AS A 0 #
C AS A 1 #
C L KA 0 #
C LK A 0
CK E A 0
K8
J8
K2
CK
CK
V D D Q1
V D D Q2
V D D Q3
A9
C1
C3
C7 1. 8 VS _ V GA
C L KA 0 #
C LK A 0
CKE A0
K8
J8
K2
CK
CK
VD D Q1
VD D Q2
VD D Q3
A9
C1
C3
C7 1. 8 VS _ VG A
C LK A 1#
C L K A1
C K E A1
K8
J8
K2
CK
CK
V D D Q1
V D D Q2
V D D Q3
A9
C1
C3
C7 1 . 8V S _V GA
C LK A 1#
C L KA 1
C K EA 1
K8
J8
K2
CK
CK
V D D Q1
V D D Q2
V D D Q3
A9
C 1
C 3
C 7 1 . 8V S _V GA
CK E V D D Q4 CKE VD D Q4 CKE V D D Q4 CKE V D D Q4
External VGA M92-

OD TA 0 C9 C9 C9 C 9
16 OD TA 0 OD TA 1 V D D Q5 E9 VD D Q5 E9 V D D Q5 E9 V D D Q5 E9
16 OD TA 1 V D D Q6 G1 R 69 0 VD D Q6 G1 R 69 1 V D D Q6 G1 R 69 2 V D D Q6 G1 R 6 93
V D D Q7 VD D Q7 V D D Q7 V D D Q7
H C B1 00 5K F -12 1T 2 0
H C B 1 00 5K F -12 1T 20
H C B 1 00 5K F -12 1T 20
H C B 10 05 K F- 1 21 T 20
D QMA #[ 7 . . 0] C SA 0 #_ 0 L8 G3 C S A 0 #_ 0 L8 G3 C S A 1# _0 L8 G3 C S A 1# _0 L8 G3
16 D QMA #[ 7 . 0 ] CS V D D Q8 G7 CS VD D Q8 G7 CS V D D Q8 G7 CS V D D Q8 G7
QS A #[ 7. . 0 ] W EA 0 # K3 V D D Q9 G9 W EA 0 # K3 VD D Q9 G9 WE A 1# K3 V D D Q9 G9 WE A 1# K3 V D D Q9 G9
.
16 QS A #[ 7 . 0 ] WE V D D Q1 0 WE V D D Q1 0 WE V D D Q10 WE V D D Q10
S2-6
QS A 7[ . . 0]
16 QS A [ 7. . 0] R A SA 0 # K7 A1 R A SA 0 # K7 A1 R AS A 1# K7 A1 R A S A 1# K7 A1
RA S V DD1 E1 RAS VD D 1 E1 RAS VD D 1 E1 RAS V DD1 E1
C A SA 0 # L7 V DD2 J9 C A SA 0 # L7 VD D 2 J9 C AS A 1# L7 VD D 2 J9 C A S A 1# L7 V DD2 J9
CA S V DD3 M9 CAS VD D 3 M9 CAS VD D 3 M9 CAS V DD3 M9
D QMA #2 F3 V DD4 R1 J2 009 04 09 D Q MA# 1 F3 VD D 4 R1 J20 09 040 9 D QMA # 5 F3 VD D 4 R1 J 20 090 40 9 D QMA # 7 F3 V DD4 R 1 J 200 90 409
D QMA #3 B3 L DM V DD5 D Q MA# 0 B3 L DM VD D 5 D QMA # 6 B3 L DM VD D 5 D QMA # 4 B3 LD M V DD5
UD M J1 UDM J1 UDM J1 UDM J1
V DDL VD D L VD D L V DDL
C 1 04 1
C 1 04 2
C 10 43
C 10 44
J7 J7 J7 J7
V S S DL V SSDL V S SD L V SS D L
C 1 04 5
C 1 04 6
C 1 04 7
C 1 04 8
OD T A 0 K9 OD T A 0 K9 OD T A1 K9 OD TA 1 K9
1. 8 V S_ V GA OD T 1. 8 VS _ V GA OD T 1. 8V S _ VGA OD T 1 . 8V S _V GA OD T
Q SA 2 F7 QS A 1 F7 QS A5 F7 QSA 7 F7
L D QS L D QS L D QS LD Q S
0 .1 u_ 10 V _X 7 R _0 4
1 u_ 6. 3V _ Y 5V _0 4
0. 1 u_ 10 V _X 7R _ 04
1u _6 . 3V _ Y5 V _0 4
R 6 94 QSA # 2 E8 A7 R 69 5 Q SA # 1 E8 A7 R 69 6 QS A #5 E8 A7 R 69 7 QS A #7 E8 A7
L D QS V S S Q1 L D QS V S S Q1 L D QS V S SQ1 LD Q S V SS Q1
4 . 99 K _1 %_ 04
0 . 1u _1 0V _ X7 R _0 4
1 u_ 6. 3 V _Y 5V _ 04
0 . 1u _1 0V _X 7 R _0 4
1 u_ 6. 3 V_ Y 5V _0 4
B2 B2 B2 B2
4. 9 9K _ 1%_ 04
4. 9 9K _1 %_ 04
4. 99 K _1 %_ 04
V S S Q2 B8 V S S Q2 B8 V S SQ2 B8 V SS Q2 B8
V S S Q3 D2 V S S Q3 D2 V S SQ3 D2 V SS Q3 D 2
Q SA 3 B7 V S S Q4 D8 QS A 0 B7 V S S Q4 D8 QS A6 B7 V S SQ4 D8 QSA 4 B7 V SS Q4 D 8
QSA # 3 A8 U D QS V S S Q5 E7 Q SA # 0 A8 U D QS V S S Q5 E7 QS A #6 A8 U D QS V S SQ5 E7 QS A #4 A8 U D QS V SS Q5 E7
U D QS V S S Q6 F2 U D QS V S S Q6 F2 U D QS V S SQ6 F2 U D QS V SS Q6 F2
V S S Q7 F8 V S S Q7 F8 V S SQ7 F8 V SS Q7 F8
V R E F _B GA 1 J2 V S S Q8 H2 V R E F_ B GA 2 J2 V S S Q8 H2 V R EF _ B GA3 J2 V S SQ8 H2 VR EF _ BGA 4 J2 V SS Q8 H 2
VREF V S S Q9 H8 V RE F V S S Q9 H8 V RE F V S SQ9 H8 V RE F V SS Q9 H 8
A2 V SS Q1 0 A2 VS S Q1 0 A2 VS S Q10 A2 V S S Q10
R 6 98 C 10 49 E2 NC #A 2 A3 R 69 9 C 10 50 E2 NC# A 2 A3 R 70 0 C 10 51 E2 NC# A 2 A3 R 70 1 C 10 52 E2 N C # A2 A3
NC #E 2 VSS1 NC# E 2 VSS1 NC# E 2 V S S1 N C # E2 V S S1
4 . 99 K _1 %_ 04
0 . 1u _1 0V _ X7 R _0 4
A _ B A2 L1 E3 A _ BA 2 L1 E3 A _B A 2 L1 E3 A _B A 2 L1 E3
4. 9 9K _ 1%_ 04
0. 1 u_ 10 V _X 7R _ 04
4. 9 9K _1 %_ 04
0. 1 u_ 10 V_ X 7R _ 04
4. 99 K _1 %_ 04
0. 1u _1 0V _ X 7R _ 04
R3 NC #L 1 VSS2 J3 R3 N C # L1 VSS2 J3 R3 N C # L1 V S S2 J3 R3 N C # L1 V S S2 J3
R7 NC #R 3 VSS3 N1 R7 NC# R3 VSS3 N1 R7 NC# R3 V S S3 N1 R7 NC# R3 V S S3 N 1
R8 NC #R 7 VSS4 P9 R8 NC# R7 VSS4 P9 R8 NC# R7 V S S4 P9 R8 NC# R7 V S S4 P9
NC #R 8 VSS5 NC# R8 VSS5 NC# R8 V S S5 NC# R8 V S S5
K 4N 1 G16 4QE -H C 2 0 K4 N 1 G16 4QE -H C 2 0 K4 N 1G 16 4QE - H C 2 0 K 4 N 1G1 64 QE - H C 20

PLACE VREF DIVIDE R COMPONEN TS PLACE VR EF DIVIDER COMPONENTS PLACE VREF DIVIDER C OMPONENTS P LACE VREF DIVIDER COM PONENTS
AS CLO SE TO MEMOR Y AS POSSI BLE AS CLOSE TO MEMORY AS POSSIBL E AS CLOSE T O MEMORY A S POSSIBLE A S CLOSE TO MEMORY AS POSSIBLE
1. 8 V S_ V GA 1. 8 VS _ V GA 1. 8 VS _ VG A 1 . 8V S _V GA
C 10 53
C 10 54
C 10 55
C 10 56
C 10 57
C 10 58
C 10 64
C 10 65
C 10 66
C 10 67
C 10 68
C 11 37
C 11 38
C 1 07 4
C 1 07 5
C 1 07 6
C 1 07 7
C 1 07 8
C 1 07 9
C 1 08 5
C 1 08 6
C 1 08 7
C 1 08 8
C 1 08 9
C 1 14 1
C 1 14 2
C 1 09 5
C 1 09 6
C 1 09 7
C 1 09 8
C 1 09 9
C 1 10 0
C 1 10 6
C 1 10 7
C 1 10 8
C 1 10 9
C 1 11 0
C 1 14 5
C 1 14 6
C 1 11 6
C 1 11 7
C 1 11 8
C 1 11 9
C 1 12 0
C 1 12 1
C 1 12 7
C 1 12 8
C 1 12 9
C 1 13 0
C 1 13 1
C 1 14 9
C 1 15 0
0. 1u _1 0V _ X 7R _ 04
0. 1u _1 0V _ X7 R _ 04
0. 1u _1 0V _ X7 R _ 04
0 . 1u _1 0V _ X7 R _ 04
0 . 1u _1 0V _ X7 R _ 04
* 0. 1 u_ 16 V_ Y 5V _0 4
1 u_ 6. 3 V _Y 5V _ 04
1 u_ 6. 3 V _Y 5V _ 04
1 u_ 6. 3 V _Y 5V _ 04
1 u_ 6. 3 V _Y 5V _ 04
1 u_ 6. 3 V _Y 5V _ 04
1 0u _6 . 3V _ X5 R _ 06
1 0u _6 . 3V _ X5 R _ 06
0 . 1u _1 0V _ X7 R _0 4
0 . 1u _1 0V _ X7 R _0 4
0 . 1u _1 0V _ X7 R _0 4
0 . 1u _1 0V _ X7 R _0 4
0 . 1u _1 0V _ X7 R _0 4
* 0. 1u _1 6V _ Y 5V _0 4
1 u_ 6. 3 V _Y 5V _ 04
1 u_ 6. 3 V _Y 5V _ 04
1 u_ 6. 3 V_ Y 5V _ 04
1 u_ 6. 3 V_ Y 5V _ 04
1 u_ 6. 3 V_ Y 5V _ 04
1 0u _6 . 3V _X 5 R _0 6
1 0u _6 . 3V _X 5 R _0 6
0 . 1u _1 0V _X 7 R _0 4
0 . 1u _1 0V _X 7 R _0 4
0 . 1u _1 0V _X 7 R _0 4
0 . 1u _1 0V _X 7 R _0 4
0 . 1u _1 0V _X 7 R _0 4
*0 . 1u _1 6V _ Y5 V _0 4
1 u_ 6. 3 V_ Y 5V _0 4
1 u_ 6. 3 V_ Y 5V _0 4
1 u_ 6. 3 V_ Y 5V _0 4
1 u_ 6. 3 V_ Y 5V _0 4
1 u_ 6. 3 V_ Y 5V _0 4
1 0u _6 . 3V _X 5 R _0 6
1 0u _6 . 3V _X 5 R _0 6
0 1. u_ 10 V _X 7 R _0 4
0 1. u_ 10 V _X 7 R _0 4
0 1. u_ 10 V _X 7 R _0 4
0 1. u_ 10 V _X 7R _0 4
0 1. u_ 10 V _X 7R _0 4
*0 . 1u _1 6V _Y 5 V_ 04
1u _6 . 3V _ Y5 V _0 4
1u _6 . 3V _ Y5 V _0 4
1u _6 . 3V _ Y5 V _0 4
1u _6 . 3V _ Y5 V _0 4
1u _6 . 3V _ Y5 V _0 4
10 u_ 6. 3 V _X 5R _0 6
10 u_ 6. 3 V _X 5R _0 6
CL K A 0 C L K A1
16 CL K A 0 16 C L K A1
R 70 2 R 70 3
56 _0 4 56 _0 4
C 11 53 47 0p _5 0V _X 7R _0 4 C 11 54 470 p_ 50 V _X 7R _ 04
R 70 4 R 70 5
56 _0 4 56 _0 4
C L K A 0# C L K A1 #
16 C L K A 0# 16 C L K A1 #

Schematic Diagrams
1.8V TO 1.8VS_VGA
SYS15 V
NM OS
1. 8V
Q4 3
SI4 80 0BDY
8
R70 8 7 3 1. 8VS_VGA
6 2 >5A
1M_ 04 5 1
LVDS Interface C11 55 C1 156

R 709 C 117 9 C 11 80
4
1 .8 V_REG_ EN +
0.1 u_1 0V_X7R _04
10 u_1 0V_Y 5V_0 8
*1 00_ 04 *2 20u _4 V_ V_A *2 2u _6. 3V_X5R_ 08
U46 F R7 06 10K_ 04 C11 57 Q4 4
D
MTN70 02 ZH S3 Q 45
R7 07 10K_ 04 *220 0p _50 V_X7 R_0 4 *MTN7 002 ZHS3
G G
LV DS CO NTR OL AB11
VGA_BKLTEN 20
S
VAR Y_BL AB12
DIG ON VGA_EN AVD D 19
AH2 0
SU SB 35 ,4 1 Sheet 18 of 50
M9 2_L VDS-U CLKP 19 ON
External VGA M92-
TXCLK_ UP_D PF3 P
AJ1 9 M9 2_L VDS-U CLKN 1 9
TXCLK_ UN_ DPF3N
AL2 1
TXOUT_U 0P_D PF2 P AK20 M9 2_L VDS-U 0P 19
TXOU T_U 0N_ DPF2N
TXOUT_U 1P_D PF1 P AH2 2

AJ2 1
M9 2_L VDS-U 0N 1 9
M9 2_L VDS-U 1P 19
S2-7
TXOU T_U 1N_ DPF1N M9 2_L VDS-U 1N 1 9
AL2 3 M9 2_L VDS-U 2P 19
TXOUT_U 2P_D PF0 P
TXOU T_U 2N_ DPF0N AK22 M9 2_L VDS-U 2N 1 9
AK24 3.3 VS_ VGA
TXO UT_U3 P AJ2 3
TXOU T_U 3N 50 0mA
LV TMD P
+ C1 16 3 C1 164 C1 16 5 C 116 6
AL1 5 M9 2_L VDS-L CLKP 19
TXCLK_ LP_D PE3 P
TXCLK_ LN_ DPE3N AK14 M9 2_L VDS-L CLKN 1 9 1 00u _6 .3V_ B_A 4. 7u _6. 3V_X5R_ 06 4. 7u _6. 3V_X5R _06 0 .1u _1 0V_X7R_ 04
AH1 6 M9 2_L VDS-L 0P 19

TXOUT_L 0P_D PE2 P AJ1 5
TXOUT_L 0N_ DPE2N M9 2_L VDS-L 0N 1 9
AL1 7
TXOUT_L 1P_D PE1 P AK16 M9 2_L VDS-L 1P 19
AH1 8 M9 2_L VDS-L 2P 19
TXOUT_L 2P_D PE0 P AJ1 7
AL1 9
TXO UT_ L3 P AK18
TXOU T_L 3N
M92 -S2
3.3V TO 3.3VS_VGA
3A 3A
3 .3 V S D 3 .3 VS_ VG A
Q3 7
R 60 4 *1M_ 04 AO34 09
G
R 73 8
C88 5 0. 01 u_2 5V_X7R_ 06 *1 00 _04

R 605
2 2K_1 %_ 04
R 60 6 100 K_04
D
Q4 9
ADD
J20090409
G
*AO3 409
D
S
Q 38
SU SB# R 136 *1 0mil_s hor t- NMN P G MTN7 002 ZHS3
25 ,31 ,3 3,3 5, 39, 40 SU SB#
S

Schematic Diagrams
Panel, CRT
CRT
3 .3 VS
C1 6 *0 . 1 u _1 0 V _ X7 R _0 4 C1 4 *0 . 1 u _1 0 V _ X7 R _ 0 4 VS Y NC D S C RT _ VSYN C_ R Q2 2 R 3 9 9 2 . 2 K _ 04
5 VS 5 VS
G
MT N 7 0 0 2Z H S 3 Zo=75 Ohm
Q 34
R 9 R8 * MT N 7 0 02 Z H S 3 D DC A DA T D S C R T_ D D C A D A T _R
G
5
1
5
1
*3 9 0 _0 6 *3 9 0 _0 6 Z 1 70 6 B LU E 4 5 DA C_ B L UE _ R
5 VS GR E E N D A C _ G R E E N _R
R4 0 2 4. 7 K _ 0 4 D 25 SCS3 3 5 V 3 6
V S Y NC 4 2 C R T_ V S Y N C _R HS Y NC 4 2 C R T _ H S Y N C _R C A RED 2 7 DA C_ R E D_ R
HS Y NC C RT _ HS Y N C_ R 5 VS
D S 1 8
R4 0 1 4. 7 K _ 0 4
U 3 U 2 Q 35 LP 1
3
7 4 A H C T1 G 12 5 GW 7 4 A H C T1 G1 2 5 GW * MT N 7 0 02 Z H S 3 D DC A CL K D S C R T_ D D C A C LK _R F C A 32 1 6 K F 4 - 12 1 T0 3
G
J2 009 04 09 Q2 1
5 VS MT N 7 0 0 2Z H S 3 LP 2
G
J2 009 04 09 R 4 0 0 2 . 2 K _ 04 F C A 32 1 6 K F 4 - 12 1 T0 3
3 .3 VS HS Y NC 4 5 CRT _ HS Y NC
Zo=75 Ohm VSYN C 3 6 CRT _ V S Y N C
DDC A CL K 2 7 C R T _ D D C A C LK
DDC A DA T 1 8 CRT _ DD CA D A T
3 .3 VS J2 00 90 409
C
A
A
J _ C R T1
C 1 05 0 9-9 1 5 05 -L
Sheet 19 of 50
D2 6 D 3 D 4
B A V 9 9 R E C T I FB IAEVR9 9 R E C TI FBI AEVR9 9 R E C T I F I E R R ED 1 D2 R4 0 3 * 1K _ 0 4 D 23 * B A V 9 9 R E CE T IF IE R
3 . 3V S
AC
AC
AC
9 Z 1 70 1 C A A
5 VS
D A C_ RE D _ R G RE E N 2 R4 0 4 * 1K _ 0 4 CRT _ DD CA D A T A C
D A C _ GR E E N _ R 10 *S C S 7 51 V -4 0 C
5 VS
D A C_ B L UE _ R BL U E 3
Panel, CRT R 14 R2 3 R2 7 C1 9 C2 2 C2 4 C2 1 C1 8 C 17
4
5
11
12 C RT _ DD CA D A T C R T _H S Y N C
D 24
A C
* B A V 9 9 R E CE T IF IE R
A
C
1 5 0_ 1 % _0 4 1 50 _ 1 %_ 0 4 15 0 _ 1% _ 0 4 *2 2p _ 5 0V _ N P O_ 04
*2 2 p_ 5 0V _N P O_ 0*242 p _5 0 V _ N P O_ 0 4 4 7p _ 50 V _ N P O_ 044 7p _ 5 0V _ N P O_ 0447 p_ 5 0 V _N P O_ 0 4 13 C RT _ HS Y NC
6 D 21 * B A V 9 9 R E CE T IF IE R
14 C RT _ VSYN C A
7 C R T _V S Y N C A C
15 C R T _ D D C A C LK C
8
D 1 * B A V 9 9 R E CE T IF IE R
M 740S /M7 60S ? 75_1 % C 5 49 C 55 1 C5 5 0 C 15 A
G ND 1
GN D 2
C R T _D D C A C L K A C
1 0 0 0p _ 5 0V _ X 7 R _ 042 2 0p _ 50 V _ N P O_ 04 22 0 p _5 0 V _ N P O _0 41 0 0 0p _ 5 0V _ X 7 R _ 04 C
W 76 0SU A ? 15 0_1%
PANEL De fa ul t : W7 60 SU A * : M7 40 S/ W7 60 S
LV DS UP 2 L V DS L P 0 R3 6 * 0_ 0 4 LV D S -L 0 N L V D S -L 0 N 1 1 R1 6 9 * 0_ 0 4
LV DS UN 2 L V DS L N0 L V D S L N0 M9 2 _L V D S -L0 N D A C _R E D _ R DA C _ RE D 6
R3 5 0 _ 04 M9 2 _ LV D S -L 0N 18 R4 5 0 0 _ 04 VGA_ R 13
LV DS UP 0 L V DS L N1
LV DS UN 0 L V DS L P 1 R3 1 * 0_ 0 4 LV D S -L 0 P R1 7 1 * 0_ 0 4
L V D S -L 0 P 1 1 DA C_ G RE E N 6
LV DS UN 1 L V DS L N2 L VD SL P0 R3 0 0 _ 04 M9 2 _L V D S -L0 P M9 2 _ LV D S -L 0P 1 8 D A C _G R E E N _R R4 5 2 0 _ 04 VGA_ G 13
LV DS UP 1 L V DS L P 2
LV DS UC L KP L V DS L CL K N R5 2 * 0_ 0 4 LV D S -L 1 N L V D S -L 1 N 1 1 R1 7 0 * 0_ 0 4
LV DS UC L KN L V DS L CL K P L V D S L N1 R5 1 0 _ 04 M9 2 _L V D S -L1 N D A C _B L U E _R R4 4 8 0 _ 04 D A C _ B LU E 6
M9 2 _ LV D S -L 1N 18 VGA_ B 13
R6 0 * 0_ 0 4 LV D S -L 1 P R1 8 8 * 0_ 0 4
L VD SL P1 M9 2 _L V D S -L1 P L V D S -L 1 P 1 1 C R T _ H S Y N C _R DA C_ H S Y NC 6
R5 9 0 _ 04 M9 2 _ LV D S -L 1P 1 8 R4 4 2 0 _ 04 V_H SY 13
LV D S -L 2 N
5
6
7
8
8
7
6
5
5
6
7
8
8
7
6
5
R7 0 * 0_ 0 4 L V D S -L 2 N 1 1 R1 9 0 * 0_ 0 4 DA C_ V S Y NC 6
L V D S L N2 R6 9 0 _ 04 M9 2 _L V D S -L2 N CRT _ V S Y N C_ R R4 4 3 0 _ 04
M9 2 _ LV D S -L 2N 18 V_VSY 13
CP1 C P2 CP 3 C P4
*8 P 4C X 10 P * 8P 4 C X 1 0 P *8 P 4 C X 10 P * 8P 4 C X1 0 P R8 2 * 0_ 0 4 LV D S -L 2 P L V D S -L 2 P 1 1 R1 8 2 * 0_ 0 4
L VD SL P2 M9 2 _L V D S -L2 P C R T _ D D C A C LK _ R DA C_ D DCA C L K 6
R8 1 0 _ 04 M9 2 _ LV D S -L 2P 1 8 R2 9 0 _ 04 VGA_ DD CCL K 1 3
4
3
2
1
1
2
3
4
4
3
2
1
1
2
3
4
R4 7 * 0_ 0 4 LV D S -L C L K N R1 8 1 * 0_ 0 4
L V D S -L C L K N 11 DA C_ D DCA D A T 6
L V D S L CL K N R4 6 0 _ 04 M9 2 _L V D S -LC L K N M9 2 _ LV D S -L C L K N 1 8 C R T _ D D C A D A T_ R R3 4 0 _ 04 VGA_ DD CDA TA 1 3
R4 0 * 0_ 0 4 LV D S -L C L K P
L V D S -L C L K P 1 1
3 .3 V L V D S L CL K P R3 9 0 _ 04 M9 2 _L V D S -LC L K P
SYS1 5 V S Y S 1 5V M9 2 _ LV D S -L C L K P 1 8 J _L C D 1
R8 4 * 0_ 0 4 LV D S -U 0 N 1 2 E DID_ D A T
L VD SUN 0 M9 2 _L V D S -U 0 N L V D S -U 0N 1 1 L V DS U CL K N 1 2 E D I D _ C LK
R8 3 0 _ 04 M 92 _ L V D S - U 0N 18 3 4
Q 20 C1 3 L V DS U CL K P 5 3 4 6
LV D S -U 0 P 5 6 L V DS U N2
R 13 R1 2 1 6 R7 2 * 0_ 0 4 L V D S -U 0P 11 7 8
D D 0. 1 u _ 10 V _ X 7R _0 4 L VD SUP0 R7 1 0 _ 04 M9 2 _L V D S -U 0 P L V DS U N1 9 7 8 10 L V DS U P 2
M 92 _ L V D S - U 0P 1 8 L V DS U P 1 9 10
1 M _0 4 1 M_ 0 4 2 5 11 12
D D R6 2 * 0_ 0 4 LV D S -U 1 N 13 11 12 14 L V DS U N0
Z 1 7 03 Z 17 0 4 3 4 2A PL VD D
L VD SUN 1 R6 1 0 _ 04 M9 2 _L V D S -U 1 N
L V D S -U 1N 1 1
M 92 _ L V D S - U 1N 18
L V DS L CL K N 15 13 14 16 L V DS U P 0
Q 5 Q4 G S L V DS L CL K P 17 15 16 18
C
D
D T C 1 1 4E U A M TN 7 00 2 Z H S 3 S I 3 4 56 B D V -T 1-E 3 R5 4 * 0_ 0 4 LV D S -U 1 P 19 17 18 20 L V DS L N 2
ENAVD D L VD SUP1 M9 2 _L V D S -U 1 P L V D S -U 1P 11 L V DS L N1 19 20 L V DS L P 2
B R 5 R4 R5 3 0 _ 04 21 22
G C 9 R 3 M 92 _ L V D S - U 1P 1 8 L V DS L P 1 23 21 22 24
LV D S -U 2 N 23 24
S * 1 00 _ 1% _ 0 6 *2 0 0_ 1 %_ 0 6 R4 9 * 0_ 0 4 L V D S -U 2N 1 1 25 26 3 .3 V S
0 . 0 1 u_ 1 6V _ X 7 R _ 0 4 * 10 0 K _ 04 L VD SUN 2 R4 8 0 _ 04 M9 2 _L V D S -U 2 N L V DS L N0 27 25 26 28
M 92 _ L V D S - U 2N 18 27 28
E
Z 1 7 05 L V DS L P 0 29 30
R4 2 * 0_ 0 4 LV D S -U 2 P 29 30 C 3
L V D S -U 2P 11
D
L VD SUP2 R4 1 0 _ 04 M9 2 _L V D S -U 2 P 8 8 10 7 -3 00 0 1
M 92 _ L V D S - U 2P 1 8
Q3 0 . 1u _ 1 0V _ X 7R _ 04
G * MT N 7 0 0 2Z H S 3 R3 8 * 0_ 0 4 LV D S -U C L K N 2A
L V D S -U C L K N 1 1 PL VDD
L V D S U C LK N R3 7 0 _ 04 M9 2 _L V D S -U C LK N
7/ 13
S
M 92 _ L V D S - U C L K N 1 8 C6 C5
M odif y C4 from 0. 1uF c ha nge to L V D S U C LK P
R3 3
R3 2
* 0_ 0 4
0 _ 04
LV D S -U C L K P
M9 2 _L V D S -U C LK P
L V D S -U C L K P 1 1
4 . 7u _ 1 0V _ X 5 R _ 080 . 1 u_ 5 0V _Y 5V _0 6
0. 01uF f or LVD S powe r t ime . M 92 _ L V D S - U C L K P 1 8
3. 3 V S R4 1 6 * 0_ 0 4 P _ DDC _ DA T A
L VD SDAT A I2 CC_ S D A P _D D C _D A T A 1 1
R4 1 5 0 _ 04 I2 C C_ SDA 1 3
R 39 4 R 3 96 R4 1 7 * 0_ 0 4 P _ DDC _ CL K
P _D D C _C L K 1 1
L VD SCL K R4 1 9 0 _ 04 I2 CC_ S C L
I2 C C_ SCL 1 3
2 . 2 K _ 04 2. 2 K _ 0 4
R1 1 * 0_ 0 4 LC D V D D _ E N L C D V D D _E N 1 1
E NA V D D R1 0 0 _ 04 V GA _ E N A V D D
V G A _E N A V D D 1 8
LV D S C L K R 3 97 * 1 0m i l_ s h ort -N MNE P
D I D_ CL K
LV D S D A T A R 3 95 * 1 0m i l_ s h ort -N MNE P
D I D_ DA T
B - 20 Panel, CRT
Schematic Diagrams
Inverter, BT, Fan
INVERTER CONNECTOR
Bluetooth
3 . 3V 3 .3 V V IN_ INV
VIN
3 . 3V L5 3 VS_ BT
L53 H C B 1 60 8 K F -1 21 T 2 5 H C B 1 0 05 K F - 1 2 1T 2 0 5 0mi l
R 39 8 1 00 K _ 0 4 U 28 A C 54 8
14
7 4 LV C 0 8P W U 28 B C 54 7 C2 40 mil
14
1 7 4 LV C 0 8P W * 0. 1 u _ 10 V _ X 7R _0 4 C 23 C2 5
22 S B _ B L ON 3 Z 18 0 7 4 0 . 1 u_ 5 0 V _Y 5V _0 6 0 . 1u _ 25 V _ X 7R _ 06
2 6 0 . 1 u _1 0 V _ X7 R _0 4 10 u _1 0 V _ Y 5 V _ 08
27 B K L_ E N 5
J _ BT 1
7 U2 8 C J _I N V 1
14
1
7
74 L V C 0 8 P W J_BT1
Z 1 80 8 9 *1 0 mi l _s h o rt -N M N P 1 R 25 * 10 m i _l s ho rt -N
U SMN
B_ PN4 _ R 2
3 0 7_ B L ON _ 3V 2 23 US B _ P N 4 3
8 I N V _ B L ON R 5 64 I N V _B LO N _ R Z 18 0 2 U SMN
B_ P
P P 4_ R
Sheet 20 of 50
1 0 K _0 4 L1 23 US B _ P P 4 R 26 * 10 m i _l s ho rt -N 1 6
3 . 3V Z 1 80 9 1 0 L2 Z 18 0 3 3 4
4 27 B T_ D E T# B T _ E N# 5
R2 4 10 K _ 0 4
R 56 5 * 10 m il _ s ho r t -N MN P 5 6
14
6
7
R 2 C 4 C8 0 1 V DD 3 Q6 8 72 1 2-0 6 G0
D
12 1 M_ 0 4 8 7 2 13 -0 60 0 G MT N 70 0 2 Z H S 36- 20- 41 A1 0-1 06
2 7, 3 1 L ID_ S W #
2 2, 3 1 S B _ P W R O K
13
11 * 1 M_ 04 * 10 0 p _5 0 V _ N P O _0
0. 447 u _1 0 V _ Y 5 V _0 4
2 7 ,3 4 BT_ EN
G
Inverter, BT, Fan
S
U 28 D 6 -2 0- 41A 10 -1 06
7
7 4 LV C 0 8P W
J_INV1
2 7 LC D _ B R I GH T N E S S
1
3 . 3V 3 .3 V
6
MAIL KEY
SW 1
* TJ G-5 3 3 -S -T / R
M74? ?
HOT KEY
1 2 W E B _E MA I L #
3 4 W E B _ E MA I L # 2 7
R7 R6 C8
5
6
1 0K _ 0 4 1 0K _0 4 0 . 1 u_ 1 0V _X 7 R _ 0 4
L5 2 For M 740 S/ M7 60S

Z 18 1 0 3 0 7_ B L ON _3 V SW 2
Q1 T J G-5 3 3-S - T / R
C
D TC 1 14 E U A 1 2
L5 2 *0 _0 4 Z 1 8 01 B Q2 3 4
11 3 07 _ B L ON VIN
G
M T N 7 0 02 Z H S 3
18 V G A _ B K L TE N L5 4 W76? ?
S
5
6
0_ 0 4 PSW1~8
E
3 1
L5 4 4 2 R3 2 7
INTERNET KEY SILENT KEY
Fo rW7 60 SU A SW 3
M74? ? SW 5
* TJ G-5 3 3 -S -T / R 10 0 K _ 04 T J G-5 3 3-S -T / R
1 2 W E B _W W W # 1 2
W EB_ W W W # 2 7 AP_ KEY 40
3 4 Z 18 1 1 3 4
C7 C1 0
R 38 6
5
6
5
6
0 . 1 u_ 1 0V _X 7 R _ 0 4 0. 1 u _ 10 V _ X 7R _0 4
1 00 K _ 0 4
FAN CONTROL SW 4
T J G-5 3 3-S - T / R
1 2
3 4
5
6
5V S _ F A N 5V S U 41 W76? ?
C P U _F O N # 1 8
2 F ON GN D 7
40MIL VIN GN D
3 6
4 V OU T GN D 5
27 C P U _F A N VSET GN D
APE8 8 7 2
C P U _ F ON #
R 5 86
* 0_ 0 4
5V S 5V S _F A N
40MIL J _F A N 1
1
C 83 9
C 8 40 2
3
0 . 1 u_ 1 0 V _X 7 R _ 0 4
1 0 u _1 0 V _ Y 5 V _ 08 8 5 2 05 - 0 3 70 1
J_FAN1
27 C P U _ F A N S E N 3
R5 8 7 4 . 7 K _0 4 1
3 .3 VS
C A
D 40 S C S 5 5 1V - 30
Inverter, BT, Fan B - 21

Schematic Diagrams
968 - PCI, IDE, MuTIOL, SPI 1/4
? ? ? ? ? ?
6-16-47238-45A
PCI_AD16
PCI_AD31
PCI_AD30
9
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI _AD2
PCI _AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
AD2
PCI_AD1
PCI_AD0
3. 3
VS RN15
PCI _
PCI _
PCI _
8.2K_8P4R_04
1 8 PCI _INT#A
2 7 PCI _INT#B
PCI _INT#C
3 6
H5
K4
M1
M2
M4
R2
P5
R4
R3
T3
U1
U2
V1
J4
J3
K1
K2
J5
K3
L2
K5
L4
L3
L5
P3
R1
T1
T2
T4
T5
U4
U3
4 5 PCI _INT#D PCI_REQ#0
U36A
R535 8. 2
K_04 PCI _REQ#0 PCI_GNT#0
AD31
AD30
AD29
AD28
AD27
AD26
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
AD25
FOR MR510 V3
PCI_REQ#4 AVDD_IDE IDE_AVDD
RN14 H2 V4
PCI_REQ#3 PREQ4# AVSS_IDE IDE_AVSS
8.2K_8P4R_04 H1
PCI _REQ#1 PCI_REQ#2 PREQ3#
1 8 G3
2 7 PCI _REQ#2 PCI_REQ#1 G4 PREQ2#
3 6 PCI _REQ#3 PCI_REQ#0 G2 PREQ1#
4 5 PCI _REQ#4 PREQ0#
Sheet 21 of 50 RN29
4.7K_8P4R_04
5 4 PCI _FRAME#
Z1901
Z1902
Z1903
Z1904
J2
J1
H3
H4
PGNT
4#
PGNT
3#
PGNT
2#
PGNT
1#
ICHRDYA
IDREQA
IIRQA
CBLIDA
AE20
AB18
AB19
AC20
IDE_PDIORDY
IDE_PDDREQ
IDE_IRQ
Z1905
6 3 PCI _IRDY# PCI_GNT#0 G5 R307 10K_04
968 - PCI, IDE, 7

8
RN13
2
1
PCI _PLOCK#
PCI _SERR#
? ? ? ? ? ?
PCI_C/BE#
3
PCI_C/BE#
2
PCI_C/BE#
1
L1
M3
N5
PGNT
0#
C/BE3#
C/BE2#
AF20 IDE_PDIOR#
C/BE1# IIORA#
MuTIOL, SPI 1/4

4.7K_8P4R_04
1
2
8
7
PCI _T
RDY#
PCI _STOP#
4,6 PCI_INT
#A
PCI_C/BE#
0
PCI_INT#A
R5
F5
C/BE0#
INTA#
PCI IIOWA#
I DACKA#
AD19
AC19
IDE_PDIOW#
IDE_PDDACK#
3 6 PCI _DEVSEL# PCI_INT#B F4

INTB#
4 5 PCI_INT#C F3
PCI_INT#D INTC# IDE_PDA2
G1 AD21
INTD# IDSAA2 IDE_PDA1
AD20
PCI_FRAME# IDSAA1 IDE_PDA0
N1 AB20
IDE
1. 8
VS PCI_IRDY# N2 FRAME# IDSAA0
PCI_TRDY# M5 IRDY#
PCI_STOP# N3 TRDY#
STOP#
AC21 IDE_PDCS3#
PCI_SERR# IDECSA1# IDE_PDCS1#
R286 P2 AB21
SERR# IDECSA0#
P4
150_1%_04 PCI_DEVSEL# N4 PAR
PCI_PLOCK# P1 DEVSEL#
PLOCK# AE19 IDE_PDD0
SZVREF IDA0
V2 AD18 IDE_PDD1
25 PCLK_SB PCICLK IDA1 IDE_PDD2
D5 AC17
12,31 SB_PCIRST# PCIRST# IDA2 IDE_PDD3
R290 C434 AF18
IDA3 IDE_PDD4
AB16
49.9_1%_04 0.1u_10V_X7R_04 IDA4 AE17 IDE_PDD5
IDA5 AD16 IDE_PDD6
IDA6 AF16 IDE_PDD7
IDA7
AC26 AE16 IDE_PDD8
25 Z_CLK1 ZCLK IDA8 IDE_PDD9
AF17
IDA9 IDE_PDD10
V22 AC16
6 ZSTB_D0 V23 ZSTB0 IDA10 AD17 IDE_PDD11
6 ZSTB_D#0 ZSTB0# IDA11 AE18 IDE_PDD12
1. 8
VS IDE_AVDD V25 IDA12 AB17 IDE_PDD13
6 ZSTB_D1 ZSTB1 IDA13
V26 AF19 IDE_PDD14
6 ZSTB_D#1 ZSTB1# IDA14
L73 HCB1608KF-121T25 AC18 IDE_PDD15
IDA15
AA23
C766 C769 C770 6 ZUREQ AA24 ZUREQ
6 ZDREQ ZDREQ
*0.1u_10V_X7R_04 *0.01u_16V_X7R_0
4 *0.1u_1
0V_X7R_04 1.8VS
NC17 NC_04 R2
91 56_04 SZ CM P_ N AB24
ZCMP_N
MuTIOL SPI_CS0N
AE21 SPI_CS0#
R2
87 56_04 SZ CM P_ P AB25 AF21 Z1907
I DE_AVSS ZCMP_P SPI_CS1N
AD22 SPI_MISO
SPI
SPI _
DO AE22 SPI_MOSI
SPI_DI
AF22 SPI_CLK
SPI_CLK
1. 8
VS AVDD_SZ4X AA22 3.3VS
AVDD_SZ4X AVDD_Z4X
AB23
AVSS_SZ4X AVSS_Z4X
L37 HCB1608KF-121T25 AF23 SPI_TRAP R305 *4.7K_04
SPI _HARDWARE_TRAP
AB26
SZVREF ZVREF
0:LPC Intern al Pull down
ZAD10
ZAD16
C462 C441 C437
1
ZAD12
ZAD13
ZAD14
ZAD15
ZAD3
ZAD4
ZAD9
ZAD1
1:SPI Extern al Pull up
ZAD0
ZAD1
ZAD2
ZAD5
ZAD6
ZAD7
ZAD8
10u_10V_Y5V_08 0.01u_
50V_X
7R_04 0.1u_10V_X7R_04
NC4 NC_04 SIS968
ZA D1 Y25
ZA D7 W25
ZA D8 U21
ZAD 9 U24
ZAD 1 0 U22
ZA D1 4 T25
ZA D1 5 T26
ZAD 1 6 AA26
ZA D0 Y22
3
1
ZAD 4 Y26
Z AD 5 W22
Z AD 6 W24
Z AD 1 1 T22
Z AD 1 2 U25
Z AD 13 T23
ZAD 2 Y2
ZAD 3 W2
AVSS_
SZ4X
6 ZAD[16:0]
B - 22 968 - PCI, IDE, MuTIOL, SPI 1/4

Schematic Diagrams
968 - PCIE, LAN, GPIO 2/4
U3 6 B
R5 0 9 * 10 m i _l s h ort -N
Z 20M0N4P C7 3 6 22 p _ 50 V _ N P O_ 0 4
C8 A V S S _ GM A C C MP
A V S S _G MA C C M P 1 8 D9
A V D D _G MA C C M P 1 8 A V D D _ GM A C C MP
2
2 H _ I N I T# AC 23 R5 1 1
AE 26 IN IT # B8 Z 2 00 2 X5
3 .3 V
R N1 6 10 K _ 8 P 4 R _ 0 4
A G P S T OP #
2
2
2
H _ A 20 M #
H _ S MI #
H _ I NT R
AD
AC
23
22
A 2 0 M#
SM I#
IN T R
CPU_S O S C 2 5 MH O
OS C 2 5M H I
A8 Z 2 00 3
G TX C LK _ P H Y _ R
*1 M _0 4 X 8A 0 2 5 0 00 F G 1H _ 25 M H z
1
1 8 AE 25 A1 2
2 7 SC I# 2 H _ N MI AE 24 N MI G TX C LK F14 E X T CL K _ P HY C7 4 3 22 p _ 50 V _ N P O_ 0 4
2 H _ I GN N E # IG NN E # E XT C LK
3 6 P C I E _R S T # AF 24
4 5 SW I# 2 H_ F E R R# AF 25 F E RR # B1 1
2 H _S T P C L K # T XC L K _ P H Y 26 P ut cl os ed t o 96 8
AD 24 STPC L K# TX C LK
CP U_ S T P # 2 H _ CP U S L P # C P U S LP # / C P U S T O P #
R3 5 4 10 K _ 0 4 C1 2 T XE N _ P H Y 26
A G P B US Y # A E 23 TXEN C1 1 T X E R_ P H Y
P S O N# 6 A GP B U S Y # BM BU SY# TXER
R3 2 3 10 K _ 0 4
R5 1 4
R5 1 3
4. 7 K _ 0 4
10 K _ 0 4
PM E#
P W R _B TN # 2
2
H _ P R OC H O T#
H _ T H R MT R I P #
A C 24
A D 25
P R OC H O T #
T H E R M TR I P #
APIC TX D 0
TX D 1
D1 2
A1 3
B1 3
T XD 0 _P H Y
T XD 1 _P H Y
26
26
V _ LA N
S B _ MU T E # TX D 2 T XD 2 _P H Y 26
R6 0 3 *1 0 K _0 4 C1 3
Y5 TX D 3 T XD 3 _P H Y 26
27 LP C _ A D 0 L AD 0 R GMC MP _N
AA4 A1 4 R5 0 5 5 6 _ 04
27 LP C _ A D 1 L AD 1 R G MC MP _ N V _ LA N
GMAC
AB2 B1 4 R GMC MP _P R5 0 4 5 6 _ 04 R3 2 1
27 LP C _ A D 2 L AD 2 R GMC MP _P
AB3 C1 4
3 .3 VS 27 LP C _ A D 3 L AD 3 R GM V R E F R G MV R E F ? ? ? ? ? PH Y> >1 .5 V 15 0 _ 1% _ 0 4
R N1 2
1
10 K _ 8 P 4 R _ 0 4
8 GP I O0 2 7 L P C _F R A M E # L P C _ L D R Q#
AB1
AB4
L F R A ME #
L D RQ #
LPC R X C LK
A1 1
R X C LK _P H Y 2 6
R GM V R E F
2 7 S B _ T H E R M# L P C_ S IR Q AA5 C1 0
L CD ID0 27 L P C _S I R Q SI RQ RX DV RX D V _ P HY 26
3 6 E1 2 RX E R _ P HY 26
Sheet 22 of 50
4 5 RX E R C 46 6 R3 1 7
A1 0 R X D 0_ P H Y 2 6
RX D 0 C9 0 . 1u _ 1 0V _X 7 R _ 0 4 15 0 _ 1% _ 0 4
RX D 1 R X D 1_ P H Y 2 6
B9
R5 7 5 10 K _ 0 4 P M _C L K R U N # RX D 2 A9 R X D 2_ P H Y 2 6
RX D 3 R X D 3_ P H Y 2 6
968 - PCIE, LAN,

R5 7 6 10 K _ 0 4 SM I#
R5 7 7 10 K _ 0 4 L P C _ L D R Q# R T C _C L K O E2 E1 0
O S C3 2 K H O CO L C O L _P H Y 26
R T C _C L K I E1 E1 1
O S C3 2 K H I C RS E1 4 CR S _ P HY 2 6
R3 0 0 4. 7 K _ 0 4 AG PBUSY #
RTC MD C
MD I O
E1 3
MD C _ P H Y 2 6
MD I O_ P H Y 2 6
GPIO 2/4
R3 6 0 1K _ 0 4 S_ CL K F1
2 3 R T C _ P W R OK B A TO K
R3 6 9 1K _ 0 4 S_ DAT S B _P W R O K E4 D8 EESK
GA 20 # 2 0 , 3 1 S B _ P W RO K P W RO K GP I O 2 1 EED I
R5 1 8 10 K _ 0 4 F8
R3 4 7 10 K _ 0 4 SB_ KB C RST # GP I O 2 2 E8 EED O 3 .3 V
GP I O 2 3 EEC S
EEPROM
V C C _ R TC D1 A7
R T CV D D GP I O 2 4 U3 7
C 51 8 D2 M2 6 E E CS 1 8
R T CV S S P RX 0 + M2 5 P C I E _ R XP 0 _ N E W _ C A R D 3 3 EE SK 2 CS V CC 7 C7 6 3
P R X 0- P C I E _ R XN 0 _N E W _ C A R D 33 E E DI SK DC
1 u _ 6. 3 V _ Y 5V _ 0 4 N2 4 3 6
R3 5 3 10 K _ 0 4 S B _ DP RS L P V R PTX0 + N2 3 P C I E _ T X P 0 _N E W _ C A R D 33 E E DO 4 DI O RG 5 0 . 1u _ 1 0V _X 7 R _ 0 4
P T X 0- P CIE _ T X N0 _ NE W _ C A RD 3 3 DO G ND
R 5 34 *1 0m i l _s h o rt - N M NSPE N TE S T K2 6
HD Audio
D0 3 P RX 1 + K2 5 P C I E _ R XP 1 _ C A R D R E A D E R 2 8 3 . 3V R 52 0 4 . 7K _ 0 4 C A T 9 3C 4 6S - 26 4 9 0T
P R X 1- P C I E _ R XN 1 _C A R D R E A D E R 2 8
C 7 67 0 . 1 u_ 1 0 V _ X7 R _0 4 A U X_ P W R OK E5 L2 4 C 8 44 0 . 1 u_ 1 0 V _ X7 R _0 4
29 A Z _ S DIN 0 H DA _ S D I N0 PTX1 + P C I E _ T X P 1 _C A R D R E A D E R 2 8
32 A Z _ S DIN 1 C4 L2 3 C 8 45 0 . 1 u_ 1 0 V _ X7 R _0 4 P CIE _ T X N1 _ CA R DR E A DE R 2 8
C 7 64 0 . 1 u_ 1 0 V _ X7 R _0 4 S B _ P W RO K H DA _ S D I N1 P T X 1-
Y3 F26 Z 2 0 05
2 9, 32 A Z _ S D OU T H D A _ S D OU T NC 1 1
PCI-Express
Y2 F25 Z 2 0 06
2 9 , 3 2 A Z _S Y N C H DA_ SY NC NC 1 0 Z 2 0 07
3 .3 V R 34 9 * 1 0K _ 0 4 G2 4
B3 NC 9 G2 3 Z 2 0 08
2 9 , 3 0, 3 2 A Z _ R S T # Z 2 01 6 Y 1 H DA_ R ESET # NC 8 Z 2 0 09
R5 6 6 H2 6
2 9 ,3 2 A Z _ B I T CL K 0_04 H DA _ B IT _ CL K NC 7
NC 6
H2 5 Z 2 0 10 PCI-Express X1
J2 4 Z 2 0 11
Fix modem fail of NC 5 J2 3 Z 2 0 12
M76SUN bug C 8 03
NC 4 Lane 0 New Card
1 .8 V A V D D _ GM A C C MP
J20090409 For EMI 3 3 p _5 0 V _ N P O _ 04
Lane 1 Mini Card( Wireless LAN)
P2 6
P C L K 1 0 0P P C I E _C L K _ S B 2 5
A C PI /O t he rs
P2 5 P C I E _C L K _ S B # 25
L 42 H C B 1 0 05 K F -1 2 1 T 20 P C L K 10 0 N
2 5 C LK _1 4 M_ 9 6 8 AA2
S ENT E ST F2 O S CI R2 5
EN TEST A V D D _P E XT R X A V D D_ P E X T RX 3. 3 V
C 48 6 C4 8 9 34 S P K R OU T AA1 R2 6 A V S S _ P E X T RX
SP K A V S S _P E XT R X
0 . 1 u _1 0 V _ X7 R _0 4 0 . 0 1u _ 5 0V _X 7 R _ 0 4 P W R_ B T N# E6
27 P W R _B T N # P ME # A6 P W RB T N# P2 2 P -R S E T 0 R 30 4 4 99 _ 1 %_ 0 4
27 PM E# PM E# R SET0 D3 Mode function
C
N C8 NC_ 0 4 P S ON # E7 P2 1 P -R S E T 1 R 30 1 1 24 _ 1 %_ 0 4
31 P S O N# P S ON # R SET1 J20090409 R5 4 3 D3 8
A UX _ P W RO K C3
A V S S _ G MA C C M P 6 , 2 6 A U X_ P W R OK Z 20 0 1 A5 A U X OK R2 1 R 73 9 *0 _ 0 4 *2 . 2 K _ 04 *S C S 7 51 V -4 0
AC PIL ED P C IEPRSN T 1 R2 3
P C IEPRSN T 0
A
R 74 0 0 _0 4 R 5 41 * 1 0m i l _s h o r t -N M N P
SEED AT 28 K B C _A U X P W R OK 2 7
AUX POWER MAIN POWER
27 S CI#
S CI #
S W I#
D6
A4 G P I O7 / G P W A K #
GPIO GP I O 0
U5
AB5
P C I E _ P RS N T 0
G PIO 0 R 74 1
P C I E _P R S N T0 3 3
*0 _ 0 4
A U X _ P W R OK
A U X_ P W R OK 6, 2 6
27 S W I# S B _M U T E # G P I O8 / R I N G GP I O 1 / LD R Q 1 #/ P C I E _ H O T P LU G S B _ T H E R M# S B _ B L ON 20
C6 V5 R5 4 2 C7 7 9
C2 G P I O9 / H D A _ S D I N 2 G P I O 2/ T H E R M # W4 SM I#
31 S B _S U S C # A GP S T O P # SL P_ S5 # G P I O 3/ E X T S M I # C LK R U N # SM I# 27
F6 W3 R 3 5 7 * 0 _0 4 *3 3 0K _ 0 4 *1 0 u _1 0 V _ Y 5 V _ 0 8
6 A GP S T O P # C P U _S T P # D4 G P I O1 1 / S T P _ P C I #/ A G P S T OP # GP I O4 / C L K R U N # W2 L CD ID0 P M_ C LK R U N # 2 7
PCI-Express 6 C P U _S T P #
S B _D P R S LP V R D 3
G P I O1 2 / C P U S T P # GP I O 5 / P R E Q 5 #
W1 J MB _ D 3D
6 S B _D P R S LP V R P C I E _ R S T# B5 G P I O1 3 / D P R S L P V R G P I O6 / P G N T 5 # J MB _ D 3D 28
12 P C IE _ RS T # G P I O1 4 / A G P S T OP # / S 3 A U XS W #
C7
1 .8 VS 30mA A V DD _ P E X T RX 31
6
S B _S U S B #
S B _ D P RS T P # B7
SL P_ S3 #
Y4 Z 2 0 13 R3 6 1 S _C
* 10 m i _l s h or t -N MNLPK
S _ C LK 9 , 1 0 , 25 , 3 3
G A2 0 # D7 G P I O1 6 / D P R S T P # GP I O 1 9 W5 S _D A T
L 34 H C B 1 0 05 K F -1 2 1 T 20 27 GA 20 # S B _K B C R S T # B 4 G P I O1 7 / G A 20 # GP I O 2 0 S_ D AT 9 , 1 0 , 25 , 3 3
2 7 S B _ K B C R S T# G P I O1 8 / K B D R S T # 3 .3 V
C 42 2 C4 1 3 S I S 9 68
0 . 1 u _1 0 V _ X7 R _0 4 0 . 0 1u _ 5 0V _X 7 R _ 0 4 R 3 19 P M _ TH R M T R I P #
PM_ THR MTRIP # 3 8
D
N C3 NC_ 0 4 * 8 . 2K _ 0 4
R TC _ C L K O C7 8 2 1 5 p_ 5 0 V _ N P O _ 04 Q 17
Z 2 0 14 G
A V S S _P E XT R X * MT N 7 0 0 2Z H S 3
3
4
S
R 54 0 X6
C M2 0 0 S 3 27 6 8 12 2 0 _ 32 . 7 6 8K H z R3 1 4 Q 16
1 .8 V S H _ P R OC H OT #
1 0 M_ 0 4 * 8 . 2K _0 4 Z 2 0 1 5G
*M T N 7 0 02 Z H S 3
2
1
R 3 03 *1 0 K _ 0 4 P CIE_ PR SNT 0 R TC _ C L K I C7 6 5 1 5 p_ 5 0 V _ N P O _ 04
6- 22 -32 R7 6- 0B 1, H= 2. 4
968 - PCIE, LAN, GPIO 2/4 B - 23

Schematic Diagrams
968 - USB, SATA 3/4
USB0: NEW CARD

U 3 6C
USB1: MINI CARD
D2 6 A2 2
33 U SB_ PP0 U V0 + O S C 12 M H I C L K _ 1 2 M_ U S B 2 5
USB2: FINGER PRINTER 33 U SB_ PN 0 D2 5
E2 4 U V0 - B2 2 Z 2 1 01
33 U SB_ PP1 U V1 + OS C 1 2 MH O
USB3: PORT0 E2 3 R3 0 2 1 2 7 _1 % _ 0 4
33 U SB_ PN 1 U V1 - U SBR EF
34 U SB_ PP2 A2 0 F20
B2 0 U V2 + US B R E F
USB4: BLUETOOTH OR 3G 34 U SB_ PN 2 U V2 -
C1 9 B2 6
33 U SB_ PP3 U V3 + A V D D_ U S B P L L 1 8 US B P V DD 1 8
USB5: PORT1 Zo=90 Ohm 33 U SB_ PN 3 D1 9 B2 5 USB PV SS1 8
A1 8 U V3 - A VSS_ U SBPL L 1 8
20 U SB_ PP4 U V4 +
USB6: CCD B1 8 E2 1
20 U SB_ PN 4 U V4 - A V DD _ US B C M P 1 8 US B CM P A V D D1 8
C1 7
USB E2 0
33 U SB_ PP5 U V5 + A VS S _ USBC M P1 8 U S B C M P A V S S 18

USB7: PORT2 D1 7
33 U SB_ PN 5
A1 6
U V5 -
D2 1
8mA
32 U SB_ PP6 B1 6 U V6 + A V DD _ US B C M P 3 3 C2 1 UVD D3 3
32 U SB_ PN 6 U V6 - A VS S _ USBC M P3 3
C1 5 C 453 C 45 7
32 U SB_ PP7 U V7 +
D1 5
3 .3 V RN 2 8 32 U SB_ PN 7 U V7 - 0 . 1 u _ 1 0V _X 7 R _0 4 0 . 0 1 u_ 5 0 V _ X 7 R _ 0 4
10 K _ 8 P 4 R _ 04 U S B _O C # 0 A2 3
U S B _ OC # 7 33 U S B _ OC # 0 U S B _O C # 1 O C0 #
4 5 F21 N C 7 N C _ 04
3 6 U S B _ OC # 1 A2 4 O C1 #
33 U S B _ OC # 26 O C2 #
2 7 U S B _ OC # 3 U S B _O C # 3 B2 4 U S B C MP A V S S 3 3
U S B _ OC # 5 U S B _O C # 4 O C3 #
1 8 C2 3
Sheet 23 of 50 U S B _O C # 5 C2 4 O C4 #
O C5 #
R4 9 7 1 0 K_ 0 4 U S B _ OC # 0 A2 5
U S B _ OC # 4 U S B _O C # 7 O C6 # S ATAT XP0
R4 9 9 1 0 K_ 0 4 B2 3 A C1 3 SATAT XP0 3 1
O C7 # ST X0 + A D1 3 S A T AT XN0
S T X0 - S A T A T X N0 3 1
E1 6 AF1 2 S AT ARXP0
968 - USB, SATA

UV D D1 8 U V DD 18 SR X0 + S AT ARXN 0 SATAR XP0 3 1
E1 8 AE1 2 SA T AR XN0 3 1
1 .8 V U V DD 1 8 F15 U V DD 18 S R X0 - A C6 S ATAT XP1
284mA 284mA F16
U V DD 18 ST X1 +
A D6 S A T AT XN1
SATAT XP1 3 2
U V DD 18 S T X1 - S AT ARXP1 S A T A T X N 1 32
L38 H C B 10 0 5 K F -1 2 1 T 20 J19 AF5 SATAR XP1 3 2
H1 8 U V DD 18 SR X1 + AE5 S AT ARXN 1
3/4
U V DD 18 S R X1 - SA T AR XN1 3 2
H1 7
C 4 67 C4 6 5 H1 6 U V DD 18 AE8 S OS C 2 5 MH I R 5 08 *1 0 m i _l s h o rt -N M N P
H1 5 U V DD 18 XIN AF8 S OS C 2 5 MH O
U V DD 18 XO U T
0 . 1 u _ 10 V _ X 7 R _ 0 4 0. 0 1 u _ 5 0V _X 7 R _0 4 J15
U V DD 18 AA3 S A T A _ L E D#
HD A C T S A TA _L E D # 3 2 , 3 4
F22 A C1 I S W 1 R5 3 6 1 K_ 0 4
UV D D3 3 F19 U V DD 3 3 IS W IT C HO P E N 1 A D1 I S W 0 R5 3 7 1 K_ 0 4
F17 U V DD 3 3 IS W IT C HO P E N 0
8mA U V DD 3 3
3 .3 V U V DD 3 3
8mA
L39 H C B 10 0 5 K F -1 2 1 T 20 AF1 4
A V D D_ S A T A R X A V D D _S A T A R X
AF1 5
A VSS_ SAT AR X AVS S_ SATAR X
C 4 61 C4 5 6 AC 9 D2 2 Z 21 0 6
A VDD _ SAT APL L 3 3 A V D D _S A T A P L L 33 I P B _ OU T 0
AD 9 C2 2 Z 21 0 7
A V D D _S A T A P L L 33 I P B _ OU T 1
0 . 1 u _ 10 V _ X 7 R _ 0 4 0. 0 1 u _ 5 0V _X 7 R _0 4
AV SS_ SAT APL L 3 3
AC 8
AD 8
AVS S_ SATAPL L 3 3
AVS S_ SATAPL L 3 3
SATA T RA P 0
E2 2 Z CL K_ SE L
S A TA R E X T AF7
R EXT Z 21 0 8 R 3 2 2
D1 0 1 K_ 0 4
A TR A P
AE1 5
1 .8 V S 6mA A V D D _ S A TA R X 25 C L K _ S A TA
A D1 5
C LK 10 0 P
E9 P C I E _W A K E #
25 CL K_ SA T A# C LK 10 0 N P CIE W A K E P C I E _ W A K E # 4, 33
L71 H C B 10 0 5 K F -1 2 1 T 20
S I S 9 68
C7 3 0 C7 2 9
0 . 1 u_ 1 0 V _ X 7R _ 0 4 0. 0 1 u _ 5 0V _X 7 R _0 4 ? ? ? ? ?
MuTIOL Clock Select (ZCLK)
133MHz : Interanl Pull down
NC 1 5 N C _ 04 66MHz : External Pull up
R 5 0 7 1 2 K _ 1 % _ 04
S A T A RE X T 3 .3 V
AV SS_ SATAR X
ZC L K_ SEL R 29 6 *1 0 K _ 04
C7 3 9 2 2 p _5 0 V _ N P O_ 0 4
3 .3 V S 41mA A VDD _ SAT AP L L 3 3
L41 H C B 10 0 5 K F -1 2 1 T 20 3 .3 V
V C C _ R TC PC IE_ W A KE # R 31 6 10 K _ 0 4
C4 9 0 C5 0 0
D3 6 S C S 7 51 V - 40 D3 7 S C S 75 1 V -4 0
0 . 1 u_ 1 0 V _ X 7R _ 0 4 0. 0 1 u _ 5 0V _X 7 R _0 4 R 5 29 *1 5 m i l_ s h o rt -N
Z 2M1 N
10P A C C A
V DD 3
NC 9 N C _ 04
J_ R T C 1 R 5 28 1 K _ 04 D3 5 S C S 7 51 V - 40 R5 3 0 10 K _ 1 % _ 0 4
Z2 112 Z 2 1 11 A C
1 R TC _ P W R OK 22
A V S S _ S A TA P L L3 3
2 C 7 55 C7 5 7 N O1 C 753 C 77 1
8 5 20 4 -0 2 0 01
1 .8 V US B P V D D1 8 1 . 8V U S B C MP A V D D 1 8 2 2 u_ 6 . 3 V _ X 5 R _ 0 8 1u _ 6 . 3 V _ Y 5 V _ 0 4N O_ 0 4 1 u _ 6 .3 V_ Y5 V _ 0 4 1 0 u _1 0 V _ Y 5V _0 8
L69 H C B 10 0 5 K F -1 2 1 T 20 L35 H C B 1 0 0 5 K F -1 2 1 T2 0
7/ 18
C6 8 9 C6 8 8 C 43 6 C4 3 5 C7 75 f rom 1 0uF_ 10 V_ 08 c ha nge
0 . 1 u_ 1 0 V _ X 7R _ 0 4 0. 0 1 u _ 5 0V _X 7 R _0 4 0 . 1 u _1 0 V _ X 7 R _ 0 4 0 . 0 1u _ 5 0 V _ X 7R _ 0 4 to 22 uF_6 .3 V_ 08 f or RTC ti me
NC 1 4 N C _ 04 NC 5 N C _0 4
iss ue .
U SBPVS S1 8 US B CM P A V S S 1 8
B - 24 968 - USB, SATA 3/4

Schematic Diagrams
968 - PWR GND 4/4
1. 05 V S
22mA
AB2 2
AA2 1
U 23
W23
R 22
R 15
M 10
M 12
M 14
N 10
T2 1
V2 1
Y2 1
T1 5
P1 5
T1 7
R1 6
U 16
U1 7
K1 0
K 11
K1 2
L11
L14
L16
M1 1
M 13
M 15
1. 8V S
T 16
L1 0
L1 2
L 15
U3 6 D
N 11
VS S
V SS
VS S
VS S
V SS
VT T
V SSZ
VSS Z
VS SZ
V SSZ
VSS Z
VS SZ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VTT
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSS
1 .8 VS U 26 N 12
W 26 V DDZ VSS N 13 C4 4 8 C4 9 7 C4 6 4 C4 8 1 C4 9 5 C4 7 5 C4 7 4 C4 9 3
V DDZ VSS
A A 25 N 14
R 24 V DDZ VSS P1 0 1 0u _ 1 0 V _ Y 5 V _ 08*1 0 u _1 0 V _ Y 5 V _ 018u_ 1 0 V _ 06 1 u_ 1 0 V _ 06 0. 1u _ 1 0V _X 7 R _ 0 4 0 . 1u _ 1 0V _X 7 R _ 0 4 0 . 1u _ 1 0 V _X 7 R _0 4 0 . 1u _ 1 0 V _ X7 R _0 4
522mA T 24
V DDZ VSS
P1 1
V 24 V DDZ VSS P1 2
Y 24 V DDZ VSS P1 3
V DDZ VSS
P 18 P1 4
W 18 V DDZ VSS R 10 3. 3V S
V DDZ VSS
U 18 R 11
V 18 V DDZ VSS R 12
V DDZ VSS
V 19 R 13
W 19 V DDZ VSS R 14 C7 7 4 C7 3 4 C4 9 8 C5 3 1 C5 2 5 C5 2 4 C5 2 3 C7 6 8
N 18 V DDZ VSS T10
V DDZ VSS
T11 *1 0 u _1 0 V _ Y 5 V _ 0180u _ 1 0 V _Y 5 V _ 081 u_ 1 0 V _ 06 *1 u _1 0 V _ 0 6 0. 1u _ 1 0V _X 7 R _ 0 4 *0 . 1 u _1 0 V _ X 7R _ 04 *0 . 1 u _1 0 V _ X 7R _ 0 4 0 . 1u _ 1 0 V _ X7 R _0 4
R 18 VSS T12
IV DD VSS
R 17 T13
V 17 IV DD VSS T14 2. 5V c ha ng e to 3 .3 V
IV DD VSS
V 13 U 10
V 12 IV DD VSS U 11 3 . 3V V_ L AN
V 11 IV DD VSS U 12
IV DD VSS
V 10 U 13 L40 H C B 1 6 08 K F -1 2 1 T 25
K9 IV DD VSS U 14
IV DD VSS
M9 U 15 C4 8 2 C 47 2 C 47 1 C7 3 3 C 47 7
IV DD VSS
Sheet 24 of 50
N9 D 13
IV DD VSS
P9 D 11 1 u_ 1 0 V _ 0 6 1 u _1 0 V _ 0 6 *1 u _ 1 0V _0 6 0 . 1 u_ 1 0 V _ X7 R _0 4 *0 . 1 u _ 10 V _ X 7 R _ 0 4
R9 IV DD VSS B1 2
T9 IV DD VSS B1 0
IV DD VSS
U9 AC 2 5
IV DD VSS
968 - PWR GND 4/4

J 14 AD 2 6
IV DD VSS 1. 8V S V _ A V D D _ S A TA 1. 8V
T 18
IV DD D 14
USB VSS
V 16 E1 5 R 320 *2 0 m li _ s ho rt - N MN P
3 .3 VS V 15 P VDD USB VSS A1 5
P VDD USB VSS
V 14 B1 5 C 46 8 C 48 8 C4 8 3 C4 9 1 C7 3 1 C7 3 2
29mA T8
N8
L9
P
P
P
P
VDD
VDD
VDD
VDD
Power/Ground USB
USB
USB
USB
VSS
VSS
VSS
VSS
C 16
D 16
A1 7
1 0 u_ 1 0 V _ Y 5 V _ 0 81 u _1 0 V _ 0 6 0 . 1 u_ 1 0 V _ X7 R _0 4 0. 0 1 u _ 50 V _ X 7 R _ 0 4 1 u_ 1 0 V _ 06 0 . 1u _ 1 0V _X 7 R _ 0 4
W 17 B1 7
O VDD USB VSS
W 16 E1 7
W 15 O VDD USB VSS C 18
O VDD USB VSS 1. 8V S V _A V D D _S B P C I E 1 . 0 5V S
W 14 D 18
W 13 O VDD USB VSS A1 9
W 12 O VDD USB VSS B1 9 R 310 *2 0 m li _ s ho rt - N MN P
O VDD USB VSS
K8 E1 9
L8 O VDD USB VSS C 20 C 46 3 C 45 2 C4 4 0 C4 4 9 C7 2 4 C7 1 8
O VDD USB VSS
M8 D 20
P8 O VDD USB VSS A2 1 1 0 u_ 1 0 V _ Y 5 V _ 0 81 u _1 0 V _ 0 6 0 . 1 u_ 1 0 V _ X7 R _0 4 0. 0 1 u _ 50 V _ X 7 R _ 0 4 1 u_ 1 0 V _ 06 0 . 1u _ 1 0V _X 7 R _ 0 4
O VDD USB VSS
R8 B2 1
U8 O VDD USB VSS D 23
V8 O VDD USB VSS D 24
O VDD USB VSS
C 25
J 18 USB VSS C 26
1 .8 V IV DD _A U X USB VSS
J 17 K1 3
J 16 IV DD _A U X USB VSS K1 4
19mA J 10
IV DD _A U X USB VSS
K1 5
Put under SiS968 solder side
J8 IV DD _A U X USB VSS K1 6
J9 IV DD _A U X USB VSS K1 7
IV DD _A U X USB VSS
L13
H 19 USB VSS L17 1 .8 VS 1. 05 V S
3 .3 V O VDD _ AUX USB VSS 1. 8V
H9
H8 O VDD _ AUX AB6
O VDD _ AUX A VSS_ SATA
F7 AB7
4mA J 11 O VDD _ AUX A VSS_ SATA AB1 2 C5 3 3 C4 8 7 C4 6 0 C4 4 3 C4 5 9 C4 2 8
J 12 O VDD _ AUX A VSS_ SATA AB1 3 C6 7 0 C 6 69
O VDD _ AUX A VSS_ SATA
AB1 4 0. 1 u _ 1 0V _ X 7 R _ 0 4 0. 1u _ 1 0V _X 7 R _ 0 4 0 . 1u _ 1 0V _X 7 R _ 0 4 0 . 1u _ 1 0 V _X 7 R _0 4 0 . 1u _ 1 0 V _ X7 R _0 4 0. 1 u _ 1 0V _ X 7 R _ 0 4
H 10 A VSS_ SATA AB1 5 0 . 1u _ 1 0 V _X 7 R _0 4 0 . 1 u _ 10 V _ X 7 R _ 0 4
V _ LA N G MI I V DD _A UX A VSS_ SATA
H 11 AC 2
H 12 G MI I V DD _A UX A VSS_ SATA AC 3
G MI I V DD _A UX A VSS_ SATA
H 13 AC 4
J 13 G MI I V DD _A UX A VSS_ SATA AC 5 3 .3 VS 3 .3 V
G MI I V DD _A UX A VSS_ SATA AC 7
A VSS_ SATA
V _ A V D D_ S B P CIE K 18 AC 1 2
L 18 A VDD PEX A VSS_ SATA AC 1 4
A VDD PEX A VSS_ SATA
L 19 AC 1 5 C4 9 2 C4 9 6 C4 6 9 C4 9 4 C 47 6 C 4 50 C 5 11
M 18 A VDD PEX A VSS_ SATA AD 2
153mA M 19
AD 3 0. 1 u _ 1 0V _ X 7 R _ 0 4 0. 1u _ 1 0V _X 7 R _ 0 4 0 . 1u _ 1 0V _X 7 R _ 0 4 0 . 1u _ 1 0 V _X 7 R _0 4 0 . 1 u _1 0 V _ X 7R _ 0 4 0 . 1 u _1 0 V _ X 7 R _ 0 4 0 . 1 u _ 10 V _ X 7 R _ 0 4
N 19 A VDD PEX A VSS_ SATA AD 4
H 21 A VDD PEX A VSS_ SATA AD 5
J 21 AD 7
K 21 A VDD PEX A VSS_ SATA AD 1 2
A VDD PEX A VSS_ SATA V _ A V DD _ S B P C IE V_ L AN V_ A VDD _ SAT A
L 21 AD 1 4
M 21 A VDD PEX A VSS_ SATA AE1
N 21 AE2
M 22 A VDD PEX A VSS_ SATA AE3
H 22 A VDD PEX A VSS_ SATA AE4 C4 4 2 C 455 C4 7 8 C4 7 0 C 48 0 C4 8 4
AE6
A VSS_ SATA AE7 0 . 1u _ 1 0 V _ X7 R _0 4 0 . 0 1 u _5 0 V _ X 7R _ 0 4 0 . 1 u_ 1 0 V _ X7 R _0 4 0. 1 u _ 1 0V _ X 7 R _ 0 4 0 . 1 u _1 0 V _ X 7R _ 04 0 . 01 u _ 50 V _ X 7 R _ 0 4
A VSS_ SATA
V _ AV D D_ SA T A AB8 AE9
AB9 A VDD _S A TA A VSS_ SATA AE1 1
A VDD _S A TA A VSS_ SATA
A B 10 AE1 3
A B 11 A VDD _S A TA A VSS_ SATA AE1 4
190mA A C 10 A VDD _S A TA A VSS_ SATA AF2
A C 11 AF3
A D 10 A VDD _S A TA A VSS_ SATA AF4
A D 11
A E 10 A VDD _S A TA AF6
A F 10 AF9
V9 A VDD _S A TA A VSS_ SATA AF1 1
W8 A VDD _S A TA A VSS_ SATA AF1 3
AVSSP EX
A VSSPEX
AVSS PEX
AVS SPEX
AVSSPE X
AV SSPEX
AVSSP EX
A VSSPEX
AVSS PEX
AVS SPEX
AV SSPEX
AVSSPE X
AV SSPEX
AVSSP EX
A VSSPEX
AVSS PEX
AVS SPEX
AVSSPE X
AV SSPEX
AVSSP EX
A VSSPEX
AVSS PEX
AVS SPEX
AV SSPEX
AVSSPE X
AV SSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX

W9
W 10 A VDD _S A TA
A VDD _S A TA
W 11
A VDD _S A TA
S I S 9 68
N 26
G 22
H 24
G 26
P2 4
P2 3
N2 2
N 25
M 23
K2 2
L26
K2 4
K2 3
J26
H2 3
G 25
F24
F23
E2 6
E2 5
P1 6
M 17
N1 7
M 16
N1 6
N 15
M2 4
L2 2
J 22
L2 5
J 25
P 17
968 - PWR GND 4/4 B - 25

Schematic Diagrams
Clock Gen & Clock Buffer
C4 0 2 C 39 8 C3 7 6
3 .3 V S C L K GE N _ V D D H _ CL K _ CP U C3 7 5 * 10 p _ 50 V _ N P O _ 04
0. 1u _ 1 0V _ X 7 R _ 0 4 0 . 1 u _1 0 V _ X7 R _0 4 0 . 1 u _1 0 V _ X7 R _0 4 U 33 H _ CL K _ CP U # C3 7 7 * 10 p _ 50 V _ N P O _ 04
L 70 H C B 1 60 8 K F -1 2 1T 2 5 2 55 H _ C LK _ N B _R 1 4 R N1 7
VD DRE F C P U T _ L 0F H _ C LK _ N B #_ R H _ CL K _ NB 4 H _ CL K _ NB
14 54 2 3 3 3 _4 P 2 R _ 0 4 C3 8 1 * 10 p _ 50 V _ N P O _ 04
C 71 5 C7 0 6 C 41 4 C3 7 8 19 VD DPC I C P U C _ L 0F 52 H _ C LK _ C P U _ R 1 4 R N1 8 H _ CL K _ NB # 4 H _ CL K _ NB # C3 8 5 * 10 p _ 50 V _ N P O _ 04
VD DPC I C P UT _ L 1 H _ C LK _ C P U # _ R H _ CL K _ CP U 2
23 51 2 3 3 3 _4 P 2 R _ 0 4
1 0 u _1 0 V _ Y 5 V _ 081u _ 1 0V _0 6 1 u _1 0 V _ 0 6 0 . 1 u _1 0 V _ X7 R _0 4 24 VD DZ CP U C_ L 1 H _ CL K _ CP U # 2 P C IE _ CL K _ CA R DR E A DE R C4 1 1 * 10 p _ 50 V _ N P O _ 04
VD D4 8 PCI E _C L K _N B _ R P C I E _ C L K _ C A R D R E A D E R #C 4 1 6
56 44 1 4 R N2 0 * 10 p _ 50 V _ N P O _ 04
39 VD DCP U PCIET _ L 0 43 PCI E _C L K _N B # _R 2 3 3 3 _4 P 2 R _ 0 4 PC IE _ CL K _ NB 4
VD DPC IEX PC IEC_ L 0 PCI E _V G A _ R PC IE _ CL K _ NB # 4 P C IE _ CL K _ NE W
29 41 1 4 R N2 1 C4 0 7 * 10 p _ 50 V _ N P O _ 04
VD DPC IEX PCIET _ L 1 40 PCI E _V G A _ R # 2 3 3 3 _4 P 2 R _ 0 4 PC I E _C L K _ V GA 1 2 P C IE _ CL K _ NE W # C4 1 0 * 10 p _ 50 V _ N P O _ 04
PC IEC_ L 1 PCI E _C L K _S B _R PC I E _C L K _ V GA # 1 2
7 38 1 4 R N2 5
8 GN DR E F PCIET _ L 2 37 PCI E _C L K _S B #_ R 2 3 3 3 _4 P 2 R _ 0 4 PC IE _ CL K_ SB 2 2 P C IE _ CL K _ S B C4 0 4 * 10 p _ 50 V _ N P O _ 04
GN DPC I PC IEC_ L 2 PCI E _C L K _N E W _ R PC IE _ CL K_ SB# 2 2 P C IE _ CL K _ S B #
13 36 1 4 R N1 1 C4 0 8 * 10 p _ 50 V _ N P O _ 04
20 GN DPC I PCIET _ L 3 35 PCI E _C L K _N E W # _ R 2 3 3 3 _4 P 2 R _ 0 4 PC I E _ C L K _ N E W 33
GN DZ PC IEC_ L 3 PCI E _C L K _C A R D _ R PC IE _ CL K _ NE W # 3 3 P C IE _ CL K _ NB
27 34 1 4 R N2 6 C3 9 9 * 10 p _ 50 V _ N P O _ 04
53 GN D4 8 P C I E T _ L 4F 33 PCI E _C L K _C A R D # _R 2 3 3 3 _4 P 2 R _ 0 4 PC IE _ CL K _ CA R DR E A DE R 2 8 P C IE _ CL K _ NB # C4 0 0 * 10 p _ 50 V _ N P O _ 04
GN DC P U P C I E C _ L 4F PCI E _C L K _H D V _ R PC IE _ CL K _ CA R DR E A DE R# 2 8
42 31 1 4 R N2 7
R2 6 2 * 0_ 0 4 32 GN DPC IEX P C I E T _ L 5F 30 PCI E _C L K _H D V # _ R 2 3 3 3 _4 P 2 R _ 0 4 PC IE _ CL K _ HD V 1 1 P C IE _ CL K _ HD V C4 2 4 * 10 p _ 50 V _ N P O _ 04
1 8 , 3 1, 3 3 , 3 5, 3 9 , 4 0 S U S B # GN DPC IEX P C I E C _ L 5F PC I E _ C L K _ H D V # 11 P C IE _ CL K _ HD V # C4 2 9 * 10 p _ 50 V _ N P O _ 04
49 CL K _ S A T A _ R 1 4 R N1 9 C L K _S A TA
S A T A CL K T _ L C L K _S A TA 23
Sheet 25 of 50 3 .3 V S
R 26 1 1 0 K _ 04 CL K E N 1
(C L K _ S T OP # )/ V T T P W R GD / P D # S A T A C LK C _ L
48 CL K _ S A T A # _ R 2 3 3 3 _4 P 2 R _ 0 4 C L K _S A TA #
C L K _S A TA # 2 3
C L K _S A TA
C L K _S A TA #
C3 9 0
C3 9 4
* 10 p _ 50 V _ N P O _ 04
* 10 p _ 50 V _ N P O _ 04
D
21 Z _ CL K 0 _ R R 27 8 22 _ 0 4 Z _ C LK 0
ZC L K0 22 Z _ CL K 1 _ R R 49 1 22 _ 0 4 Z _ C LK 1 Z _ C LK 0 6 Z _ C LK 0 C4 1 8 * 10 p _ 50 V _ N P O _ 04
ZC L K1 Z _ C LK 1 21
G R 49 4 * 10 m i _l s h ort -N MNZ P23 0 1 2 8 W7 60S UA ? ? ?
Clock Gen & Clock

37 CL KE N # Q1 2 6 C P US T P # *(C P U _ S T OP #)/ R E S E T # 3 CL K G E N_ F S L 0 R 26 0 *3 3 _0 4 C L K _1 4 M_ 6 7 1M X Z _ C LK 1 C7 0 1 * 10 p _ 50 V _ N P O _ 04
* *F S L 0 / R E F 0 _ 2 x C L K _1 4 M_ 6 7 1M X 6
S
MT N 7 0 0 2Z H S 33. 3 V S L3 3 C L K GE N _ V D D A 4 CL K G E N_ F S L 1 R 26 5 33 _ 0 4 C L K _1 4 M_ 9 6 8
H C B 10 0 5 K F -1 21 T 2 0 *F S L 1 / R E F 1 _ 2 x R 26 3 33 _ 0 4 C L K _1 4 M_ 3 0 7E L V C L K _1 4 M_ 9 6 8 2 2 C L K _1 4 M_ 6 7 1M X C3 7 2 * 10 p _ 50 V _ N P O _ 04
C L K _1 4 M_ 3 0 7E L V 1 1
50 9 CL K G E N_ F S L 2 R 47 8 33 _ 0 4 PC L K_ SB
VD DA ** F S L 2/ P C I C LK 0 _ 2 xF 10 CL K G E N_ F S 3 R 48 1 33 _ 0 4 K B C_ PCL K PC L K_ SB 2 1 C L K _1 4 M_ 9 6 8 C3 9 1 * 10 p _ 50 V _ N P O _ 04
**F S 3/ P C I C LK 1 _ 2 xF K B C_ PCL K 2 7
Buffer C7 2 2 C3 8 4
10 u _ 10 V _ Y 5V _ 0 8 0. 1u _ 1 0V _ X 7 R _ 0 4
C 38 0
0 . 0 1 u_ 5 0 V _X 7 R _ 0 4
47
GN D A
** F S 4 / P C I C L K 2
*(P C I _ S TO P # )/ P C I C L K 3
**M OD E / P C I C L K 4
(P E C L K R E Q0 # )/ P C I C L K 5
11
12
15
16
17
CL K G E N_ F S 4
S T P _ P CI #
C L K G E N _ MO D E
P E C LK R E Q0 #
P E C LK R E Q1 #
R 27 0
R 27 1
R 48 5
*3 3 _0 4
*0 _ 04
*0 _ 04
P C L K_ CAR D
MI N I _ C A R D _ C L K R E Q#
C L K _1 4 M_ 3 0 7E L V
PC L K_ SB
C3 7 3
C6 7 8
* 10 p _ 50 V _ N P O _ 04
* 10 p _ 50 V _ N P O _ 04
(P E C L K R E Q1 # )/ P C I C L K 6 18 P C L K _ D E B U G _R N E W _ C A R D _ C L K R E Q# 3 3 K B C_ P CL K C6 7 9 * 10 p _ 50 V _ N P O _ 04
P CIC L K 7
R2 6 9 *1 0 mi l _ sh o rt - N M
Z N
23P0 2 4 5 26 S E L 2 4_ 4 8 # R 49 3 *3 3 _0 4 C L K _4 8 M_ C A R D P C L K _ CA R D C4 0 1 * 10 p _ 50 V _ N P O _ 04
9 , 1 0, 2 2 , 3 3 S _D A T S D A TA * *S E L 2 4_ 4 8 #/ 2 4 _ 48 M H z
R2 6 6 *1 0 mi l _ sh o rt - N M 23P0 3 4 6
Z N
9 , 1 0, 2 2 , 3 3 S _C L K S C LK 25 C L K _ 1 2M _ U S B _ R R 49 2 33 _ 0 4 C L K _1 2 M_ U S B C L K _4 8 M_ C A R D C7 0 5 * 10 p _ 50 V _ N P O _ 04
12 M H z C L K _1 2 M_ U S B 2 3
C L K _1 2 M_ U S B C7 0 4 * 10 p _ 50 V _ N P O _ 04
X1
X2
M _ CL K _ DD R0 # C3 3 7 * 10 p _ 50 V _ N P O _ 04
I C S 9 L P R 6 0 0 C G LF M _ CL K _ DD R0 C3 4 0 * 10 p _ 50 V _ N P O _ 04
6
M _ CL K _ DD R1 # C3 4 5 * 10 p _ 50 V _ N P O _ 04
M _ CL K _ DD R1 C3 4 7 * 10 p _ 50 V _ N P O _ 04
M _ CL K _ DD R2 # C3 3 8 * 10 p _ 50 V _ N P O _ 04
X3 M _ CL K _ DD R2 C3 4 1 * 10 p _ 50 V _ N P O _ 04
Z 23 0 4 2 1 Z 23 0 5
M _ CL K _ DD R3 # C3 5 3 * 10 p _ 50 V _ N P O _ 04
X8 A 0 1 4 31 A F K 1 H _1 4 . 3 18 1 8 MH z M _ CL K _ DD R3 C3 4 9 * 10 p _ 50 V _ N P O _ 04
C6 7 6 C6 7 7
ST P _ P C I# R2 6 7 *1 0 K _0 4
33 p _ 50 V _ N P O_ 0 4 33 p _ 50 V _ N P O_ 0 4 3 .3 V S
P E CL K RE Q 0 # R2 7 4 *1 0 K _0 4
P E CL K RE Q 1 # R4 8 7 *1 0 K _0 4
3 .3 V S
Place CRYSTAL Within 500 R4 7 5 *1 K _ 04
mils of ICS9LPR600 C L K G E N _ MO D E R 48 2 1 0 K _ 04
C L K GE N _F S L0 R4 7 6 2. 2 K _ 0 4 CP U _ B S E L 0 2
C L K GE N _F S L1 R2 6 4 2. 2 K _ 0 4 CP U _ B S E L 1 2
C L K GE N _F S L2
Clock Generator Pin 15
R4 7 9 2. 2 K _ 0 4 CP U _ B S E L 2 2
R5 6 3 *2 . 7 K _0 4 Status(LO)Non-STUFF (HI)PULLl-UP
1. 8V S
C L K GE N _F S 3 R4 8 0 2. 7 K _ 0 4
C L K GE N _F S 4
Mode Desktop mode Mobile mode
R2 6 8 *2 . 7 K _0 4 3 .3 V S
L 66 C3 4 2 C 35 1 C3 5 2
H C B 1 60 8 K F -1 2 1T 2 5 Pin 1 VTTOWRGD/PD# CLK_STOP#
0 . 1u _ 1 0V _ X 7 R _ 0 4 * 0. 1 u _ 10 V _ X 7 R _ 04 0. 1u _ 1 0V _ X 7 R _ 0 4
C L KBUF _ VD D H os t C lo ck
Pin 12 PCICLK3 PCI_STOP#
C6 5 4 C6 5 7 C 35 6 FS 4 F S3 BS EL2 B SE L1 BS EL0 F re que nc y
1 0u _ 1 0V _ Y 5V _ 0 8 0 . 1u _ 1 0V _ X 7 R _ 0 4 * 0. 1 u _ 10 V _ X 7 R _ 04 U1 5 0 1 1 0 1 10 0 M Hz Pin 16 PCICLK5 PECLKREQ0#
3 7
V DD1 .8 VD DA1 .8 CL K B U F _ A V DD
11 0 1 0 0 1 13 3 M Hz
25 V DD1 .8 1 M_ C LK _ D D R 3# _ R 2 3 R N5 M _ CL K _ DD R3 #
V DD1 .8 D DR C0 M_ C LK _ D D R 3_ R M_ C LK _ D D R 3 # 1 0 Pin 17 PCICLK6 PECLKREQ1#
21 2 1 4 * 4P 2 R X0 _ S h o r t -N M N PM_ 0_ 4C L K _ D D R 3 M_ C LK _ D D R 3 1 0 0 1 0 1 1 16 6 M Hz
V DD1 .8 D DRT 0
10 5 M_ C LK _ D D R 1# _ R 1 4 R N4 M _ CL K _ DD R1 # 0 1 0 1 0 20 0 M Hz
5 M_ F W D S D C L K OA _ D #
9 C L K _ INC D DR C1 4 M_ C LK _ D D R 1_ R 2 3 * 4P 2 R X0 _ S h o r t -N M N PM_ 0_ 4C L K _ D D R 1
M_ C LK _ D D R 1 # 9 Pin 28 RESET# CPU_STOP#
5 M _F W D S D C L K OA _ D C L K _ INT D DRT 1 M_ C LK _ D D R 1 9
R 24 8 *0 _ 04 Z 2 3 06 20 13 M_ C LK _ D D R 0# _ R 1 4 R N2 M _ CL K _ DD R0 #
9, 1 0 , 2 2, 3 3 S _ D A T Z 2 3 07 S DA T A D DR C2 M_ C LK _ D D R 0_ R M_ C LK _ D D R 0 # 9
9, 1 0 , 2 2, 3 3 S _ C L K R 24 7 *0 _ 04 19 12 2 3 * 4P 2 R X0 _ S h o r t -N M N PM_ 0_ 4C L K _ D D R 0 M_ C LK _ D D R 0 9
S CL K D DRT 2
F B _ I NA 18 15 M_ C LK _ D D R 2# _ R 2 3 R N3 M _ CL K _ DD R2 # 1 .8 V S C L K B U F _A V D D
F B _I N D DR C3 M_ C LK _ D D R 2 # 1 0
R2 4 6 2 2 _0 4 F B _ OU T A 17 16 M_ C LK _ D D R 2_ R 1 4 * 4P 2 R X0 _ S h o r t -N M N PM_ 0_ 4C L K _ D D R 2
F B _O U T D DRT 3 M_ C LK _ D D R 2 1 0
L6 8 H C B 10 0 5 K F -1 21 T 2 0
C3 4 4 8 23
G ND D DR C4
6 22 C 66 0 C3 4 6 C 66 3
1 0p _ 50 V _ N P O_ 0 4 28 G ND D DRT 4
G ND
24 27 1 0 u_ 1 0 V _ Y 5 V _ 08 0. 1 u _ 10 V _ X 7 R _ 0 4 0 . 0 1u _ 5 0V _X 7 R _ 0 4
14 G ND D DR C5 26
G ND D DRT 5
ICS 9 P 9 3 5
B - 26 Clock Gen & Clock Buffer

Schematic Diagrams
PHY Realtek 8201CL
PHY Address : 01
U13
25 32
22 MDC_PHY MDIO_PHY 26 MDC PWFBOUT 36 PWFBOUT
22 MDI O_PHY MDIO AVDD33 V_LAN_3.3
Clo se to RTL8 201CL 22 TXD0_PHY 6
5 TXD0
22 TXD1_PHY 4 TXD1 29
22 TXD2_PHY TXD2 AGND
C319 22 TXD3_PHY 3 TXD3 AGND 35
27p_50V_NPO_04 R239 *10mil_short-NM
TX
NP
EN_PHY_R 2
PHY_XTAL1 22 TXEN_PHY R240 22_04 TXCLK_PHY_R 7 TXEN
22 TXCLK_PHY R215 *10mil_short-NM
RX
NPDV_PHY_R 22 TXC
22 RXDV_PHY RXDV
22 RXD0_PHY R216 *10mil_short-NM
RX
NPD0_PHY_R 21 RXD0 NC1 27 Z2401
R223 *10mil_short-NM
RX
NPD1_PHY_R 20
22 RXD1_PHY R227 *10mil_short-NM
RX
NPD2_PHY_R 19 RXD1
22 RXD2_PHY RXD2 CLOSE TO LAN CHIP CLOSE TO TRANSFORMAL
X2 22 RXD3_PHY R231 *10mil_short-NM
RX
NPD3_PHY_R 18 RXD3
R228 22_04 RXCLK_PHY_R 16 31 MDI1+
X8A025000FG1H_25MHz 22 RXCLK_PHY COL_PHY 1 RXC TPRX+ 30 MDI1-
C327 22 COL_PHY CRS_PHY 23 COL TPRX-
22 CRS_PHY CRS
27p_50V_NPO_04 22 RXER_PHY RXER_PHY 24 RXER/FXEN
PHY_XTAL2 PHY_XTAL1 46 33 MDI0-
PHY_XTAL2 47 X1 TPTX- 34 MDI0+
X2 TPTX+
LED_TX 9
LED1 10 LED0/ PHYAD0 28 LAN_RTSET
LED2 12 LED1/ PHYAD1 RTSET 43 ISOLATE
LED2/ PHYAD2 ISOLATE
LED3 13 40 RPTR R197 R198
LED4
PWFBIN
15
8
14
LED3/ PHYAD3
LED4/ PHYAD4
PWFBIN
RPTR
SPEED
DUPLEX
ANE
39
38
37
41
SPEED
DUPLEX
ANE
LDPS
49.9_1%_04
Z2402
49.9_1%_04 R200
49. 9_1%_04
R199
49. 9_1%_04
Sheet 26 of 50
DVDD33 LDPS
PHY Realtek
48 44 MII/SINB
V_LAN_3.3 DVDD33 MII/SNI B/RTT3 42 LAN_RST# R229 *10mil_short -NMNP C269 Z2403
RESETB AUX_PWROK 6,22
11 DGND0
17 0.1u_10V_X7R_04 C270
45 DGND1
DGND2
RTL8201CL-VD-LF
0. 1u_10V_X7R_04
8201CL
R453 *10mil_short -NMNP R455 *10mil_short-NMNP
MLMX1+_R 1 2 MLMX1+ MLMX0+_R 1 2 MLMX0+
MLMX1-_R 4 3 MLMX1- MLMX0-_R 4 3 MLMX0-
L59 L60
*WCM2012F2S-161T03 *WCM2012F2S-161T03
R454 *10mil_short -NMNP R456 *10mil_short-NMNP
V_LAN_3.3 L16
PWFBOUT MDI0+ 7 10 MLMX0+_R J_RJ45

MDI0- 8 TD+ TX+ 9 MLMX0- _R MLMX0- 1 DA+ GND1
TD- TX- MLMX0+ shield
R225 2 DA- shield GND2
Z2404 4 12 Z2406 MLMX1- 3 DB+
*5.1K_04 R167 R159 Z2405 5 NC NC 13 Z2407 MLMX1+ 6
NC NC DB-
LAN_RST# MDI1+ 1 16 MLMX1+_R
*15mil_short-NMNP *15mil_short-NMNP MDI1- 2 RD+ RX+ 15 MLMX1- _R 4
RD- RX- DC_NP 5 DC+
RD_CT RX_CT DC-
C299 3 RD_CT RX_CT 14 7 DD+
M54 0JE? ? ? TD_CT 6 11 TX_CT DD_NP 8 DD-
*0.1u_10V_X7R_04 TD_CT TX_CT
C218 C194 C1099-108A4
0. 01u_50V_X7R_04 0.01u_50V_X7R_04 NS0013LF R97 R98 R96 R90
6-19-21001-026 75_1%_04 75_1%_04 75_1%_04 75_1%_04

V_LAN_3.3 Z2408
R202 1.5K_04 MDI O_PHY C66
R238 5.1K_04 COL_PHY
R241 5.1K_04 LED_TX 1000p_2KV_12_H125
R232 5.1K_04 MII/SINB
RN31 5.1K_8P4R_04
8 1 LDPS
7 2 SPEED
6 3 DUPLEX
5 4 ANE
R201 2K_1%_04 LAN_RTSET

RN1 10K_8P4R_04
8 1 LED4
7 2 LED3
6 3 LED2
5 4 LED1
RN32 5.1K_8P4R_04 PWFBOUT L25 PWFBIN 3.3V V_LAN_3.3

8 1 CRS_PHY HCB1608KF-121T25 CLOSE TO
7 2 RXER_PHY PWFBIN L27 HCB1608KF-121T25
6 3 RPTR
5 4 ISOLATE C320 C326 C332 C334 C317 C279 C330
*0.1u_10V_X7R_04 10u_6. 3V_08_H125 0. 1u_10V_X7R_04 10u_6.3V_08_H125 0.1u_10V_X

7R_04 0.1u_10V_X7R_04 10u_6.3V_08_H125
PHY Realtek 8201CL B - 27

Schematic Diagrams
KBC-ITE IT8512E
K B C_ A V D D L36 R3 3 1 1 0K _ 0 4 W DT _ E N
VDD 3
H C B 1 00 5 K F -1 21 T 2 0
V D D3 PJ 7
VDD 3 V DD 3
C 7 38 C4 2 7 C5 0 2 C 44 6 R3 2 9 R 3 28 W D _ D I S A B LE 1 2
C 44 4 C 4 47
1 0 u _1 0 V _ Y 5 V _ 080. 1 u _ 10 V _ X 7R _ 04 0 . 1u _ 1 0V _ X 7 R _ 0 4 * 0. 1 u _1 0 V _ X 7R _0 4 *1 0 K _0 4 *1 00 K _ 0 4
0 . 1 u_ 1 0 V _X 7 R _ 0 4 0 . 1 u _1 0 V _ X7 R _0 4 20 m i l
R5 1 0 *1 0 K _ 04 W D _ DISA BL E R5 1 2
C4 7 9
G
U2 2 10 0 K _ 0 4
0. 1 u _ 10 V _ X 7R _ 04 KBC_ A G ND Z 25 0 8 3
M R# Z 2 50 9 S K B C _ W R E S E T#
3 .3 VS 1 D
1 J_KB1/J_KB2 24 5 R ESET#
VC C
4 Q1 8 C7 4 1
WD I
127
J _ K B 1 _7 4 S J _ K B 2 _ 76 S J_ K B 3 _ W 7 6S C4 8 5 2 *M T N 7 0 02 Z H S 3
11 4
1 21
11
26
92
74
G ND
50
3
U2 0 *8 5 20 1 -2 40 5 1 8 52 0 1 -24 0 5 1 * 85 2 01 - 2 4 05 1 1u _ 1 0V _0 6
*0 . 1 u_ 1 0 V _ X7 R _ 0 4 A * A T3 5 1 0I G V -2 . 93 -C -C -T 1
VSTB Y
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
VBAT
V CC
A V CC
10 58 K B -S I0 4 KB- SI0 4 K B -S I 0 4 3 IN1
22 LP C _ A D 0 LA D 0 KSI0 /S T B#
9 59 K B -S I1 5 KB- SI1 5 K B -S I 1 5
22 LP C _ A D 1 8 LA D 1 K S I 1/ A F D # 60 K B -S I2 6 KB- SI2 6 K B -S I 2 6
22 LP C _ A D 2 LA D 2 KSI2 /INIT #
7 61 K B -S I3 8 KB- SI3 8 K B -S I 3 8
22 LP C _ A D 3 K B C_ P CL K 13 LA D 3 K S I3 /S L IN# 62 K B -S I4 11 KB- SI4 11 K B -S I 4 11
25 K B C _ P C LK LP C C L K K SI4
6 63 K B -S I5 12 KB- SI5 12 K B -S I 5 12
22 L P C _F R A ME # 5 LF R A ME # K SI5 64 K B -S I6 14 KB- SI6 14 K B -S I 6 14 V D D3
22 LP C _S I R Q SERIR Q LPC K/B MATRIX K SI6 K B -S I7 KB- SI7 K B -S I 7
22 65 15 15 15
2 8 , 31 , 3 3 L P C _ R S T # LP C R S T # / W U I 4 / G P D 2 ( P U ) K SI7 C VDD 3
Sheet 27 of 50
K B C _ W R E S E T# 14 36 K B -S O 0 1 KB- S O0 1 K B -S O0 1 AC
W RS T # K S O 0 / P D0 D04 RA
37 K B -S O 1 2 KB- S O1 2 K B -S O1 2 S MC _B A T D3 4 A R 5 03 * 1 0K _ 0 4
K B C _G A 2 0# K S O 1 / P D1 K B -S O 2 KB- S O2 K B -S O2 36 S MC _B A T M OD E L_ I D
126 38 3 3 3 B A V 9 9 R E C TI F I E R
A C _I N # 4 GA 2 0 / GP B 5 K S O 2 / P D2 39 K B -S O 3 7 KB- S O3 7 K B -S O3 7 C R 5 01 1 0 K _ 04
1 3, 3 6 A C _I N # K B R S T # / GP B 6 ( P U ) K S O 3 / P D3 K B -S O 4 KB- S O4 K B -S O4
34 LE D _ A C I N # 16 40 9 9 9 AC
P W U R E Q# / GP C 7 ( P U ) K S O 4 / P D4
KBC-ITE IT8512E
T H E R M_ A L E R T # 2 0 41 K B -S O 5 10 KB- S O5 10 K B -S O5 10 S MD _B A T D3 3 A RB
2 T H E R M_ A L E R T # L8 0 L LA T / G P E 7( P U ) K S O 5 / P D5 K B -S O 6 13 KB- S O6 K B -S O6 36 S MD _B A T
42 13 13 B A V 9 9 R E C TI F I E R
W EB_ AP# 23 K S O 6 / P D6 43 K B -S O 7 16 KB- S O7 16 K B -S O7 16 C
40 W EB_ AP# W E B _ E MA I L# E C S C I #/ G P D 3 ( P U ) K S O 7 / P D7 K B -S O 8 17 KB- S O8 K B -S O8 B A T _D E T
2 0 W E B _E M A I L # 15 44 17 17 36 B A T_ D E T AC
E C S M I #/ G P D 4 ( P U ) K S O 8/ A C K # 45 K B -S O 9 18 KB- S O9 18 K B -S O9 18 D3 1 A
DAC K S O9 / B U S Y
K S O1 0 / P E
46 K B -S O 1019 KB- S O1 0 19 K B -S O1 0 19 B A V 9 9 R E C TI F I E R D03A/B? D04?
C P U _ F A N _R 76 51 K B -S O 1120 KB- S O1 1 20 K B -S O1 1 20 C MOD EL _I D RA RB MOD EL _I D RA RB
77 DA C 0/ G PJ 0 K S O 11 / E R R # 52 K B -S O 1221 KB- S O1 2 21 K B -S O1 2 21 AC
DA C 1/ G PJ 1 K S O1 2 / S L C T
W L A N _P W R 78 53 K B -S O 1322 KB- S O1 3 22 K B -S O1 3 22 B A T 1_ V O LT D 3 0 A M7 X0 S 10 K X M7 X0 S X 1 0K
33 W L A N_ P W R W LA N _ E N 79 DA C 2/ G PJ 2 K S O1 3 54 K B -S O 1423 KB- S O1 4 23 K B -S O1 4 23 36 B A T 1 _V OL T B A V 9 9 R E C TI F I E R
33 , 3 4 W L A N _ E N E C _ V G A _ A LE R T # DA C 3/ G PJ 3 K S O1 4 K B -S O 1524 KB- S O1 5 K B -S O1 5
80 55 24 24 C M7 X0 SU X 1 0K M7 X0 SU 10 K X
1 3 E C _ V G A _A LE R T#
30 K B C _ MU TE #
K B C _ MU TE # 81 DA C
DA C
4/ G
5/ G
PJ
PJ
4
5
IT 85 12 E K S O1 5 C H G_ C U R S E N A C
D2 9 A
ADC FLASH F or M 74 0S For M 76 0S Fo r W76 0S *B A V 9 9 R E C E T I F I E R
B A T_ D E T 66 1 00 C
B A T_ V O LT _ R 67 A DC 0/ G PI0 F LF R A ME # / G P G2 1 01 K B C _S P I _C E # TO T A L_ C U R AC
C H G _C U R S E N _ R A DC 1/ G PI1 F L A D 0/ S C E # K B C _S P I _S I
68 1 02 D8 A
T O TA L _ C U R _ R 69 A DC 2/ G PI2 F LA D 1 / S I 1 03 K B C _S P I _S O *B A V 9 9 R E C E T I F I E R V DD 3
A DC 3/ G PI3 F L A D 2/ S O Z 2 5 04
70 1 04
3 G _D E T # 71 A DC 4/ G PI4 F L A D 3 / G P G6 1 05 K B C _S P I _S C L K C C D _ D E T# R 2 93 1 0 K _ 04
32 3 G_ D E T# C C D _D E T # A DC 5/ G PI5 F L CL K /S C K C CD_ E N
32 CC D_ DE T # 72 1 06 C C D _E N 32
M OD E L _I D 73 A DC 6/ G PI6 ( P D )F L R S T # / W U I 7 / GP G 0 / TM K B C_ S W I# R 30 9 * 10 m i _l s ho rt - N MN P 3 G_ D E T # R 2 89 1 0 K _ 04
A DC 7/ G PI7 SW I# 22
GPIO
SMBUS 56 K B C _ GA 2 0 # R 33 3 * 10 m i _l s ho rt - N MN P S M C_ B A T R 5 06 4 . 7 K _ 04
S MC _ B A T 110 ( P D )K S O 16 / G P C 3 57 K B C _ S US B # 3 1 GA 2 0 # 22
S MC LK 0 / G PB3 ( P D )K S O 17 / G P C 5 K B C _ S US C # 3 1
S MD _ B A T 111 K B C _ S MI # R 31 1 * 10 m i _l s ho rt - N MN P S M D_ B A T R 3 32 4 . 7 K _ 04
115 S MD A T0 / G PB4 93 P M _C L K R U N # S MI # 22
2 S MC _C P U _ T H E R M S MC LK 1 / G P C1 ( PD )GP H 0 /ID0 PM _ CL KRU N# 2 2
116 94 L E D _ T H R OT T LE # K B C_ S CI # R 31 3 * 10 m i _l s ho rt - N MN P BA T _ DET R 2 85 1 0 K _ 04
2 S MD _C P U _ T H E R M S MC _ V G A _T H E R M 1 1 7 S MD A T1 / G P C2 ( PD )GP H 1 /ID1 95 C TX 1 SCI# 22
1 3 S M C _ V G A _T H E R M S MD _ V G A _T H E R M 1 1 8 S MC LK 2 / G P F 6( P U ) ( PD )GP H 2 /ID2 W D T_ E N
J20090409 K B C_ RS T #
96 R 31 2 * 10 m i _l s ho rt - N MN P
1 3 S M D _ V G A _T H E R M S MD A T2 / G P F 7( P U ) ( PD )GP H 3 /ID3 97 W L A N _D E T# W D T _E N 3 3 S B _K B C R S T# 2 2
( PD )GP H 4 /ID4 B T _ DE T # W L A N _D E T # 3 3 K B C_ P W RB T N #
PWM 98 B T _ DE T # 2 0 R 31 8 * 10 m i _l s ho rt - N MN P P W R_ B T N# 2 2 C 47 3 * 10 p _ 50 V _ N P O _0 4
B R I GH T N E S S 24 ( PD )GP H 5 /ID5 99 K B C _P C L K R 31 5 *1 0 _ 04 Z 25 1 0
B E EPP _ E C P W M0 / GP A 0( P U ) ( PD )GP H 6 /ID6 3 G_ E N D D _ ON 38 K B C_ RS M RS T #
34 KBC _ BEEP C 4 51 * 10 m i l_ s h ort -N MN 25 1 07 3 G_ E N 32 R 29 5 * 10 m i _l s ho rt - N MN P K B C _ A U XP W R O K 22
28 P W M1 / GP A 1( P U ) ( PD )GP G 1 /ID7
3 4 L E D _ S C R OL L # P W M2 / GP A 2( P U )
34 L E D _N U M # 29 EXT GPIO
30 P W M3 / GP A 3( P U ) 82 K B C _S MI # B A T 1_ V O LT B A T _V O L T_ R
34 L ED_ C AP# P W M4 / GP A 4( P U ) ( P D )E GA D / GP E 1 K B C _S C I #
LOW ACTIVE 3 4 L E D _ B A T _C H G # 31 83 R 28 3 10 0 _ 04 C4 2 6 1 u _1 0 V _ 06
32 P W M5 / GP A 5( P U ) ( P D )E GC S #/ GP E 2 84 K B C _P W R B T N # C H G_ C U R S E N C H G_ C U R S E N _R
34 L E D _ B A T _ F U L L # P W M6 / GP A 6( P U ) ( P D )E GC LK / GP E 3 VD D3
34 LE D _ P W R # 34 R 49 0 *1 00 _ 0 4 C6 9 2 * 1u _ 1 0V _ 0 6
P W M7 / GP A 7( P U ) TO T A L_ C U R TO T A L_ C U R _ R
WAKE UP 35 K B C _R S MR S T # R 28 4 *1 00 _ 0 4 C4 2 5 * 1u _ 1 0V _ 0 6
PS/2 ( P D )W U I 5/ GP E 5
8 0C L K 85 17 K B C _R S T # N C1 6
33 8 0 CL K 3 IN1 86 P S 2 C L K 0 / GP F 0 ( PU ) ( P D )LP C P D # / W U I 6/ GP E 6
33 3I N 1 P S 2 D A T 0 / GP F 1 ( PU )
80 P O R T _D E T # 87 PWM/COUNTER
3 3 8 0 P OR T _ D E T # P ME # 88 P S 2 C L K 1 / GP F 2 ( PU ) 47 N C_ 0 4
22 P ME # P S 2 D A T 1 / GP F 3 ( PU ) ( P D )TA C H 0 / G P D 6 C P U_ F A N S E N 2 0
J20090409 89 48 C 44 5 KBC_SPI_*_R = 0.1"~0.5"
3 2 , 34
3 2 , 34
T P _ CL K
T P_ DAT A
90 P S 2 C L K 2 / GP F 4 (
P S 2 D A T 2 / GP F 5 (
PU
PU
)
)
( P D )TA C H 1 / G P D 7 0. 1 u _ 10 V _ X 7R _ 04 8 Mb it
1 20
( P D )T M R I 0 / W U I 2 / G P C 4 1 24 V C OR E _O N 3 7 U2 1
TH E R M _R S T #
WAKE UP ( P D )T M R I 1 / W U I 3 / G P C 6 S P I _V D D KBC_ SP I_ S I_ R K BC_ SP I_ S I
2 T H E R M_ R S T# 125 8 5
P W R S W / GP E 4 ( P U ) VDD SI R 29 9 47 _ 0 4 C4 3 8 * 33 p _ 50 V _ N P O _0 4
P W R _S W #
CIR CRX 0 K B C _ S P I _ S O_ R K BC_ SP I_ S O
40 P W R_ S W # 18 1 19 ? ? ? 2
L ID_ SW # 21 R I 1 # / W U I 0 / GP D 0 ( P U ) ( P D ) CRX /G P C0 1 23 CT X 0 R 32 6 1K _ 0 4 SO R 32 5 15 _ 1 %_ 0 4 C5 0 1 * 33 p _ 50 V _ N P O _0 4
2 0 , 31 LI D _S W # R I 2 # / W U I 1 / GP D 1 ( P U ) ( P D )C T X/ GP B 2 K B C_ F L A S H KBC_ SP I_ CE# _ R K BC_ SP I_ CE #
3 1
W P# C E# R 32 4 15 _ 1 %_ 0 4 C4 9 9 * 33 p _ 50 V _ N P O _0 4
W EB_ W W W #
GP INTERRUPT LPC/WAKE UP K B C_ S W I# K B C_ S P I_ S CL K _ R K B C _ S P I _ S C LK
20 W EB_ W W W # 33 19 6
GI N T/ G P D 5 ( P U ) ( P D )L 8 0H L A T/ GP E 0 R 29 7 4. 7 K _ 0 4 S CK R 29 8 47 _ 0 4 C4 3 9 * 33 p _ 50 V _ N P O _0 4
1 12 Z 2 51 1 7 4
( P D )R I N G# / P W R F A I L# / L P C R S T #/ GP B 7 C H G _E N 36 H OL D # V S S
B T_ E N 108
UART S S T 25 V F 0 8 0 B
2 0 , 34 B T_ E N RX D/G P B 0 ( P U )
CLOCK
B K L_ E N 109 2 Z 25 0 6
AVSS
20 B K L_ E N TX D / GP B 1 ( P U ) CK3 2 KE J _ S PI1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1 28 Z 25 0 7
CK 3 2 K
R3 3 4 *1 0 M_ 04 2 1 S P I_ V DD
I T 85 0 2 E - J K B C _ S P I _ S C LK _ R 4 3 K B C _ S P I _ C E #_ R J_ S PI1 P IN ? ? L V2 20 J SP ID BG
1
27
91
113
75
KBC_ S PI_ SI_ R K B C _ S P I _ S O _R
Z 2 5 0 5 12
49
1 22
6 5
X4 C M2 0 0S 3 2 7 68 1 22 0 _ 32 . 7 6 8K H z 8 7
4 1
WE B0-- ->AP KE Y 3 2
C5 0 4
*S P N Z -0 8S 3-B -C -0 -P
WE B1-- ->E M AILKEY EC? ? 8512 8502

R 5 74
0_ 0 4
C5 0 3
1 2p _ 5 0V _ N P O_ 04
1 2p _ 5 0V _N P O_ 0 4
R574 R 0_04 C 0.1U_04 J _H 8D B G1

WE B2-- ->W WW KEY NC 6 N C_ 0 4 W DT _ E N
2 1 V DD 3
4 3
J_H8DBG1
R3 0 6 *1 0 mi l _ sh o rt -N M
B RN P
I GH T N E S S C P U _ F A N _R 3I N 1 6 5 8 0C LK
2 0 L C D _ B R I GH TN E S S 2 1
K B C _ A GN 2D 0 C P U_ F A N R 3 08 12 0 K _ 04 8 7 8 0P O R T _ D E T #
C4 5 4 * 0. 1 u _ 16 V _ Y 5 V _ 0 4 C 4 58 0. 1u _ 10 V _ X 7R _ 04 10 9 10 9
*S P U F Z -1 0 S 3-V B -0-B
J20090409
B - 28 KBC-ITE IT8512E
Schematic Diagrams
JMB385 Card Reader
3 .3 V S
3 .3 VS
R5 7 8 4 . 7 K _ 04 S D_ C D#
RN 3 3
V CC _ CA R D 1 8 M S _ INS #
2 7 M DIO 7 C 820
3 6 SD W P
4 5 M DIO 1 3 0 . 1 u _ 1 0 V _ X7 R _ 0 4
10 K _8 P 4 R _ 0 4
R5 8 0 2 00 K _0 4 M DIO 1 2
R5 8 2 2 00 K _0 4 M DIO 1 4
M D I O1 0
M DIO 1 1
MD I O 1 2
M D IO 9
M DIO 8
3 .3 VS
Card R eader Pull A P V D D 1. 8
36
35
33
32
31
30
29
28
27
26
25
High/L ow U 40
34
C 823
M D IO 8
M D IO 1 1
Sheet 28 of 50
N C
N C
G N D
M D I O9
M DIO 1 0
M D I O1 2
NC
G ND
GN D
Resist ors
TAV3 3
C 8 24
A P V D D1 .8
3 .3 VS 0 . 1 u _ 1 0 V _ X 7R _ 0 4
0 . 1 u _ 1 0V _X 7 R _ 04 37 24 C 825
38 DV 18 GN D 23 M D I O1 3
PC IES_ EN M DIO 1 3
39 22 M D I O1 4 0 . 1 u _ 1 0 V _ X 7R _ 0 4
3 .3 VS
MD I O 7
SD W P
40
41
S D / MS C L K 4 2
S D C MD / MS B S 4 3
PC
MD
MD
MD
IES
IO 7
IO 6
IO 5
M DIO 1 4
C R_ L ED N
D V3 3
R EG _ CT R L
21
20
19
18
C R1 _ L ED N
30MIL
V C C_ C A R D
Card Reader Power JMB385 Card
44 MD IO 4 JMB385 D V1 8 17
C 8 26
MD I O 3
MD I O
MD I O 1
0 . 1 u _ 1 0V _X 7 R _ 04MD I O 0
2
45
46
47
48
DV
MD
MD
MD
33
IO 3
IO 2
IO 1
C R 1 _P C T L N
C R1 _ C D0 N
C R1 _ C D1 N
S E E CL K
16
15
14
13
S D _ C D#
M S _ IN S#
S E E C LK
SE ED AT
C8 4 1 R 58 8
Reader
MD IO 0 S E E DA T
A P C LK P
APC L KN
0. 1u _ 1 0 V _ X 7 R _ 0 4 7 5 _ 1% _ 0 4
APR EXT
X RS T N
APG N D
A PRX P
A P V DD
APR XN
A PT XN
AP T XP
XT EST
APV1 8
1
2
3
4
5
6
PR EXT 7
8
9
10
APT X N 1 1
12
J MB 3 8 5 -L GE Z 0 A
D 39 A C *S C S 7 5 1 V -4 0
G N D
J M B _ D3 D 22
P C IE _ T X P1 _ C ARD R EAD ER
P C I E _T X N 1 _ C A R D R E A D E R
APT XP
L P C _R S T #
2 7, 31 , 3 3 L P C _ R S T # SEED AT 2 2
D3 Mode function
C 82 7 0. 1 u _ 1 0 V _ X 7 R _ 0 4 J20090409
2 5 P C IE _ CL K _ C A R DR E A D E R # P CIE _ RX P 1 _ CA RD RE A D E R 22
C 82 8 0. 1 u _ 1 0 V _ X 7 R _ 0 4
2 5 P C IE _ CL K _ C A R DR E A D E R P C I E _ R X N 1_ C A R D R E A D E R 22
AP VDD 1 .8 A P VDD 1 .8
C8 2 9 C 8 30 C 8 31
C8 3 2 C8 3 3
10 0 0 p _ 5 0V _X 7 R _ 040 . 1 u _ 1 0V _X 7 R _ 041 0 u _ 10 V _ Y 5 V _ 0 8
P C I E _ T X N 1 _ C A R D R E A D E R 22
0. 1u _ 1 0 V _ X 7 R _ 0 410 u _ 1 0 V _ Y 5 V _ 0 8
P C IE _ T X P 1 _ CA R D RE A DE R 2 2
R5 8 5
8 .2 K_ 0 4
Card Reader
Connector
J _C A R D - R E V 1
S D_ C D# P1
M D I O2 P2 CD _ S D
M D I O3 P3 DA T 2 _ S D
C D / D A T 3_ S D
S D C M D / MS B S P4
CM D_ S D
P5
P6 VSS_ SD V CC _ CA R D
VCC _ CA RD VDD _ SD
S D/M S C L K P7 S D / M S CL K
CL K _ S D
C8 4 2 P8
M D I O0 P9 VSS_ SD
0 . 1 u_ 1 0 V _ X 7 R _ 0 4M D I O1 P1 0 DA T 0 _ S D C 835 C8 3 7 C8 3 8
S DW P DA T 1 _ S D
P1 1
W P_ SD
P1 2 * 1 0p _ 5 0 V _ N P O_ 0 4 0 . 1 u_ 1 0 V _ X 7 R _ 0 4*1 0 u _ 10 V _ Y 5 V _ 0 8
P1 3 VSS_ M S
VCC _ CA RD V C C _ MS
S D/M S C L K P1 4
M D I O3 SCL K _ M S
C8 4 3 P1 5
M S _ IN S# P1 6 DA T 3 _ M S
I N S _M S
Near Cardreader CONN
0 . 1 u_ 1 0 V _ X 7 R _ 0 4M D I O2 P1 7
M D I O0 DA T 2 _ M S
P1 8
M D I O1 S D I O/ D A T 0 _ MS
P1 9
S D CM D / MS B S P2 0 DA T 1 _ M S P2 2
B S _ MS GN D
P2 1 P2 3
VSS_ M S GN D
MD R 01 9 -C 0 - 1 04 2
JMB385 Card Reader B - 29

Schematic Diagrams
Audio Codec ALC662
D9 S C S 5 5 1 V -3 0
C A
5V S
L4 3 * H C B 1 00 5 K F -1 2 1 T 20
3. 3 V S 3 .3 V S_ A U D 5 V S _ A UD 5 V _ R E GO U T
U 23
L49 H C B 1 0 0 5K F -1 21 T 2 0 4 5
OU T VIN
C5 3 8 C 532 C5 3 6 C5 3 7 C5 1 2 C 74 5 C 50 8 C 50 6 1
S HD N#
0 . 1 u_ 1 0 V _ X7 R _ 04 1 0 u _ 10 V _ Y 5V _0 80. 1 u _ 1 0V _X 7 R _0 4 0 . 1 u_ 1 0 V _ X 7R _ 04 0. 1u _ 1 0 V _X 7 R _0 4 0 . 1 u _1 0 V _ X 7R _ 0 4 27 3 3 3
1 0 u_ 1 0 V _ Y 5 V _ 0 8* 10 u _ 1 0V _Y 5 VZ_ 08 2 C5 2 8
BY P G ND
* G9 2 4 1 u_ 1 0 V _ 0 6
C 75 6
Sheet 29 of 50 AUD G
25
38
*0 . 1 u _ 16 V _ Y 5V _0 4
4
7
1
9
U 38
D V DD 1
DV DD 2
A V DD 1
DV S S 1
D VSS2
AVD D2
E A P D _ M OD E 2 AUD G A UD G
Z2 701 3 G P I O0 27 Z 27 1 2 C 74 4 1 0 u _1 0 V _ Y 5 V _ 0 8
Layout Note:
Audio Codec
G P I O1 VR EF
C7 8 4 *2 2 p _5 0 V _ N P O_ 0 4
Very close to Audio Codec
R 5 52 33_04 A Z _ S D OU T _ R 5 28 M I C 1 -V R E F O -L AU DG MI C 1 -V R E F O-L M I C 1-V R E F O -R
2 2 ,3 2 A Z _ S DO UT AZ _ BIT C L K_ R S D A T A -O U T MI C 1 -V R E F O-L M I C 1 -V R E F O -R
2 2 ,3 2 A Z _ B IT CL K R 5 53 0_04 6 32
R 5 49 22_04 A Z _ S D IN0 _ R 8 B I T -C L K MI C 1 -V R E F O- R
ALC662
22 A Z _ S D I N0 A Z _ S Y NC _ R S D A T A -I N Z 27 1 3
R 5 48 33_04 10 29 R5 1 6 R 51 5
2 2 ,3 2 A Z _ S Y NC
2 2 , 3 0, 3 2 A Z _ R S T #
R 5 45 33_04 A Z _ R S T #_ R 11 S Y NC DIGITAL L I N E 1 -V R E F O-L 37 Z 27 4 3
R ESET# LI N E 1 -V R E F O- R 2. 2 K _ 0 4 2 .2 K_ 0 4
EAPD R7 4 2 *0 _ 0 4 47 30 M I C 2 -V R E F O
30 EAPD SP D IF I/E APD MI C 2- V R E F O 31 Z 27 1 5 MI C 1 -L MI C 1 -R
SPD IF O L I N E 2- V R E F O
J20090409 32 SP D IF O 48
SPD IF O 35 C5 1 5 C 50 9
F R O N T -O U T -L F R ON T-L 30
R 5 47 1 0K _0 4 Z 27 0 3 Z2 704 12 36
34 BEEP PC BEEP F R ON T - OU T- R F R ON T-R 30
R 5 44 1 K _ 04 *6 8 0p _ 5 0 V _ N P O _ 04 * 68 0 p _ 50 V _ N P O_ 0 4
C7 7 8 *1 0 0p _ 5 0 V _ N P O _ 04C 7 7 7 1 u _ 10 V _ 0 6 39 Z 2 7 44
A UD G S U R R - O U T -L Z 2 7 45
41
J D_ S E NS E _ M IC_ R 13 S U R R -OU T- R AU DG A UD G
J D_ S E NS E _ H P 34 S e n s e A (J D1 ) 43 Z 2 7 16
S e n s e B (J D2 ) C E N -O U T Z 2 7 17
44
L _ HP _ O UT _ A 14 L F E -O U T
3 0 L _ H P _ OU T _ A R _ H P _ OU T _A L I N E 2- L Z 2 7 18
15 45
30 R _ H P _ O U T _ A L I N E 2- R ANALOG S I D E S U R R -O U T -L
S I D E S U R R -OU T- R
46 Z 2 7 19
C 7 62 4 . 7 u _6 . 3 V _ X 5 R _ 0Z62 7 0 8 1 6 MI C 2 -V R E F O J_INTMIC1
I NT _ M IC I N T _ MI C _ R M I C 2 -L
R 56 7 1K _0 4 C 7 58 4 . 7 u _6 . 3 V _ X 5 R _ 0Z62 7 0 9 1 7 33 Z 2 7 20
M I C 2 -R D C V OL 21
18 40 Z 27 2 1 R 52 5 2 0 K _ 1 %_ 0 4 R2 3 7
19 C D -L J DR E F A UD G
20 C D -G N D 23 Z 27 2 2 C 75 1 *1 u _ 1 0V _0 6 Z 2 7 24 2. 2 K _ 0 4
C D -R L I N E 1 -L Z 27 2 3 Z 2 7 25
24 C 74 9 *1 u _ 1 0V _0 6 J _ I N T MI C 1
AV SS1
L I N E 1- R
AVSS2
R 526 75 _ 0 4 Z 2 7 4 6 C 7 54 4 . 7 u _6 . 3 V _ X 5 R _ 0Z62 7 1 0 2 1 I N T_ M I C
32 M I C 1-L M I C 1 -L 1
32 M I C 1-R R 524 75 _ 0 4 Z 2 7 4 7 C 7 52 4 . 7 u _6 . 3 V _ X 5 R _ 0Z62 7 1 1 2 2
M I C 1 -R R5 1 9 R5 2 2 C3 1 6 2
A LC 6 62 -G R 8 8 26 6 -0 2 00 1
26
42
*1 0 0K _0 4 *1 0 0K _0 4 68 0 p _ 50 V _ X 7 R _ 0 4
Z2 708 C 52 1 0 . 1 u_ 1 0 V _ X 7R _ 0 4 8 8 2 6 6- 2 R
Z2 709 C 52 0 0 . 1 u_ 1 0 V _ X 7R _ 0 4
Z2 710 C 51 4 0 . 1 u_ 1 0 V _ X 7R _ 0 4 A U DG A U DG
Z2 711 C 51 0 0 . 1 u_ 1 0 V _ X 7R _ 0 4 A UD G
Layout Note:
AU D G Codec pin 1 ~ pin 11 and pin 47 and pin 48
are Digital signals.
Layout Note: The others are Analog signals.
Very close to Audio Codec
Layout Note:
close to Audio Codec
JD _ S E N S E _ MI C R5 6 8 2 0 K _ 1 %_ 0 4 J D _ S E N S E _ MI C _ R
3 2 J D _ S E N S E _ MI C
3 2 J D_ S E N S E JD _ S E N S E R5 6 9 3 9 . 2 K _ 1% _ 0 4 J D_ SEN SE_ H P
B - 30 Audio Codec ALC662

Schematic Diagrams
Audio AMP TPA6047A4
L 78
H C B 1 0 0 5K F -1 21 T 2 0
5 VS L 79 5 V S _A MP
H C B 1 0 0 5K F -1 21 T 2 0 30mils
C 848 C8 4 9
5 V S _A MP C 850 C8 5 1 C8 5 2 C 85 3
0 . 1 u _ 1 0V _ X7 R _ 04 1u _ 1 0 V _ 0 6
C8 5 4 1 0 u _ 10 V _ Y 5 V _ 08 * 0 . 1 u_ 1 6 V _ Y 5V _0 4 0. 1u _ 1 0 V _ X 7R _ 0 4 0 . 1 u_ 1 0 V _ X 7 R _ 0 4 0 . 1 u _1 0 V _ X 7 R _ 0 4
500Hz High Pass Filter

AU DG
Fcut(-3db)=520Hz AU D G
17
30
18
9
8
U 43 AU D G
R 59 2 2 4 . 9K _1 % _ 0 4 C 85 5 0 . 1 u _ 25 V _X 7 R _0 6 Z 23 0 4 1
H PVD D
29 F R ON T -R
C P V DD
VD D
S P V DD
SPVD D
R 59 3 7 3 . 2K _1 % _ 0 4 S P K R _ RIN - 20 S P K OU TR + J_SPK1
OU TR + S P K O UT R+ 3 2
C 85 6 0 . 1 u _ 25 V _X 7 R _0 6 2 J _S P K 1
S P K R _ RIN + S P K OU TR - S P K OU T L+ Z2 820
A UD G 19 S P K O UT R- 32 L4 F C M1 0 0 5K F -1 2 1T 0 3 2 1
C 85 7 0 . 1 u _ 25 V _X 7 R _0 6 3 O UT R - S P K OU T L- L3 F C M1 0 0 5K F -1 2 1T 0 3 Z2 821 1
S PK R _ L IN+ 2
R 59 4 7 3 . 2K _1 % _ 0 4
R 59 5 2 4 . 9K _1 % _ 0 4 C 85 8 0 . 1 u _ 25 V _X 7 R _0 6 Z 23 0 5 4 TPA 604 7A4 6 S P K OU TL + 8 5 2 04 - 0 2 0 0 1
29 F R ON T -L S PK R _ L IN- L O UT + C1 1 C 12 8 52 0 4 -0 2 R
C8 5 9 4 . 7 u_ 1 0 V _ X 5 R _ 0 8 R 727 0_ 0 4 26 7 S P K OU TL -
29 R _ H P _ OU T _A H P _I N R L OU T - 2 20 p _ 5 0 V _ N P O _2042 0 p _5 0 V _ N P O_ 0 4
C8 6 0 4 . 7 u_ 1 0 V _ X 5 R _ 0 8 R 728 0_ 0 4 27
29 L _H P _ O U T _ A H P _I N L H E A DP HO NE - R
15
Ther ma l
H P _O U T R
H P_ O UT L
16 H E A DP HO NE - L
H E A D P H ON E -R
H E A D P H ON E -L 3 2
32
FOR EMI Sheet 30 of 50
SP K_ EN 23 25 R5 9 6 1 0 0 K_ 0 4
Near CP+ and CP-

H P_ EN 22
SPKR _ EN
H P _E N
Pad R E G_ E N
R E G_ OU T
29
R 5 97
5 VS
5 V _ R E G OU T
1 0 0 K_ 0 4
Audio AMP
BYP ASS
S P GN D
C P GN D
31 R 5 98 * 1 0 0K _0 4
S P G ND
H PVSS
C PVSS
GA I N 0 5 VS
TPA6047A4
Z2308 10 32 R 5 99 * 1 0 0K _0 4
G N D
G ND
C1 P GA I N 1
C8 6 1 12
C1 N
R 6 00 1 0 0 K_ 0 4
1u _ 1 6 V _ X 5R _ 0 6 Z2309 T PA6 0 4 7 A4 RH BR
33
28
21
11
14
13
24
5
C 8 62
C 863 SPEC=0.47U,
1 u _ 1 0V _0 6
1 u _ 1 0 V _ 06 EVM=1U
A U DG A U DG
3 .3 VS
U4 4 A
14
74 L V C 0 8P W
2 7 K B C_ M UT E # 1
3
2
2 2 , 2 9, 32 A Z _ R S T #
3 .3 V S 3 .3 VS
7
3 . 3V S R6 0 1 14 U 44 D
7 4 L VC0 8 PW
1 00 K _ 0 4 12
U 44 B 11 S P K _E N
14
R 60 2 1 0 0K _0 4 7 4 LV C 0 8 P W 13
3 .3 VS 4
D
6
7
5
32 SPK_ H P# HP _ E N G
Q3 6
7
MT N 70 0 2 Z H S 3
3 . 3V S R 74 3
* 0_ 0 4
U4 4 C
14
74 L V C 0 8P W
9
8
10
29 EA PD
7
J20090409
Default( L = Mute )
L51 * H C B 1 0 05 K F -1 21 T 2 0
AUDIOGPIO0# H -> H L47 H C B 10 0 5 K F - 1 2 1 T 20
C 50 5 * 0 . 1u _ 1 0 V _ X 7R _ 0 4
KBC_MUTE# L -> H
C 52 7 * 0 . 1u _ 1 0 V _ X 7R _ 0 4
AZ_RST# L -> H C 51 3 * 0 . 1u _ 1 0 V _ X 7R _ 0 4
SB_MUTE# L -> H
A UD G
Audio AMP TPA6047A4 B - 31

Schematic Diagrams
SATA HDD, Power Good, LID
POWER MANAGMENT POWER GOOD & RESET

For NB control and Level shift
3 . 3V 3 .3 V 3 .3 V 3 . 3V 3. 3 V 3. 3 V
VCORE Power Good delay
3ms and Notice SB U2 5 A All Power Good and
14
7 4L V C 08 P W U2 5 B
14
R2 8 2 C4 3 0 R2 7 2
4 0 1 . 8 V _ P W RG D
1 7 4L V C 08 P W Notice SB
R2 9 4 3 Z 29 1 1 4
*1 0 K _0 4 *0 . 1 u_ 1 6 V _Y 5 V _0 4 *4 . 7 K _ 04 2 6
3 9 1 . 5 V _ P W RG D S B _ P W R OK 2 0 , 22
*1 0 K _ 04 5
KBC _ SUSC # 2 7
7
R 36 7
D
5
7
R 27 3 *1 0 m li _ sh o rt -N M N P
Z 2 9 06 Z 2 9 07 S B _ S U S C# 2 2
1 1 0 K _0 4
R4 8 9 4 Z 29 0 8 G
D
*0 _ 04 2 Q1 4
S
Z29 05 B *M TN 7 00 2 Z H S 3R 2 7 7 3. 3 V
5 NB _ S 3 A UX S W #
G U 19
3
Q2 6 Q1 5 * 7 4A H C 1 G0 8 GW 10 0 K _ 04 U2 5 C
14
S
* D T C 1 1 4E U A *M T N 7 00 2 Z H S 3 7 4L V C 08 P W
E
9
6 ,3 7 D E L A Y _ P W RG D 8 Z 29 1 2
Sheet 31 of 50
10
3 . 3V 3 9 1 . 0 5 V S _P W R GD
7
Close to SIS968
R2 7 6
SATA HDD, Power *4 . 7 K _ 04 R 27 9 *1 0 m li _ sh o rt -N M N P

KBC _ SUSB# 2 7
SU SB# 1 8, 2 5 , 3 3, 3 5 , 3 9, 4 0
3. 3 V
Good, LID
D
R 28 0 R 27 5 *1 0 m li _ sh o rt -N M N P C 5 07 *0 . 1 u_ 1 0 V _X 7 R _ 0 4
*1 00 K _ 0 4 S B _ S U S B # 22
Z 2 9 10 G U2 5 D
14
22 P S ON # Q1 3 7 4L V C 08 P W
S
I f nee d PS ON# C 41 5 *M TN 7 00 2 Z H S 3C 4 0 9 12
11 Z 2 90 9 R 3 3 0 3 3_ 0 4
t ha n u se d 100 K 1 2, 2 1 S B _ P C I R S T # P C I _ R S T # 33
* 0. 1 u _ 16 V _ Y 5 V _ 0 4 *0 . 1 u_ 1 6V _Y 5V _ 0 4 13
a nd 0. 1U R3 3 5 3 3_ 0 4
L P C _R S T# 2 7 , 2 8, 3 3
7
R3 4 2 R3 3 8 3 3_ 0 4
N B _ R S T # 6 , 11
1 00 K _ 0 4
SIGNAL S0/S1 S3 S4/S5
S3AUXSW# 1 0 1
PSON# 0 1 1
SATA HDD
LID SWITCH IC POWER SWITCH CONNECTER
S IS? ? ? ?
3. 3 V
? ? ? ? ?
J _H D D 1
S1
C onn ec to r R 1 1 0K _0 4
3 .3 VS
S2 S A T A TX P 0 _ R C7 4 2 0 . 01 u _ 50 V _ X 7R _0 4 U 1 J _ SW 1
S A T A TX N 0 _ R S A T A T XP 0 2 3 L ID_ S W #
0 . 1 u_ 1 0 V _X 7 R _0 4
S3 C7 4 0 0 . 01 u _ 50 V _ X 7R _0 4 S A T A T XN 0 23 1 2 L I D _ S W # 2 0, 2 7 J_SW1
S4 V CC OU T Z 2 9 13 1
G ND
S5 S A T A RX N0 _ R C7 3 7 0 . 01 u _ 50 V _ X 7R _0 4 M _B T N # 2 4
S A T A RX N 0 2 3 40 M_ BTN# 3
S6 S A T A R X P 0 _R C7 3 5 0 . 01 u _ 50 V _ X 7R _0 4 C 1 1
S7 S A T A RX P 0 2 3 M H -2 48 4
3
3 . 3V S PSU1, PSU2 8 5 20 1 -0 40 5 1
3
P1
P2
1 2
P3 C 72 6 C7 2 7
P4
P5 * 0. 0 1 u _1 6 V _ X7 R _ 0 4 *1 0 u_ 1 0 V _Y 5V _0 8
3
P6
P7 5 VS
G ND
P8
P9 1 2
P 10 V CC OU T
P 11 Z 29 0 1 *M H -2 4 8
U 45
P 12 C 42 1 C 71 0 C 4 20 C 6 99 C7 1 1 C7 0 9
P 13 Z 29 0 2 +
P 14 Z 29 0 3 * 0. 1 u _ 10 V _ X 7R _0 4 1 0 u_ 1 0 V _Y 5 V _0 8 * 0 . 1u _ 1 0V _ X 7 R _ 04 *1 u_ 1 0 V _0 6 1 0u _ 10 V _ Y 5 V _ 0 81 00 u _ 6. 3 V _ B _ A
P 15 Z 29 0 4
? ? ?
A C E S -9 1 90 7 -02 2 0 A - H 0 1
P IN G ND1 ~ 2 = G ND
B - 32 SATA HDD, Power Good, LID

Schematic Diagrams
Multi I/O, ODD, 3G, Click M74
ODD
S IS ? ? ? ? 3G
C6 2 6
? ? ? ? ? 1 50 u _ 4V _B _ A
J _O D D 1 20 mil
+
S1
C on ne ct or J _ 3G 2
S2 S A TA T X P 1 _ R C8 1 5 0 . 0 1u _ 5 0V _ X 7 R _ 0 4 1 2
S A TA T X N 1 _ R S A T A TX P 1 2 3 W AKE# 3 .3 V_ 0 3 .3 VS
S3 C8 1 6 0 . 0 1u _ 5 0V _ X 7 R _ 0 4 S A T A TX N 1 2 3 3 6
S4 5 BT _ DAT A 1 .5 V_ 0 8 M UIM _P W R
S A TA R X N 1 _ R B T _ CHC L K UI M _ P W R M UIM _D A T A
S5 C8 1 7 0 . 0 1u _ 5 0V _ X 7 R _ 0 4 S A T A RX N1 2 3 10
S6 S A TA R X P 1_ R C8 1 8 0 . 0 1u _ 5 0V _ X 7 R _ 0 4 7 U I M_ D A T A 12 M UIM _C LK C1 9 9
S A T A R X P 1 23 C L K R E Q# U I M_ C L K M UIM _R S T
S7 11 14
13 RE F CL K - U I M_ R E S E T 16 M UIM _V P P 0 . 1u _ 1 0V _ X 7 R _ 0 4
RE F CL K + U I M_ V P P
9
15 GN D 0 4
Z 30 0 2 5V S GN D 1 G ND 5
P1
P2
P3
P4 Z 30 0 1 KEY
P5 21 18
P6
9 19 2 3 -01 3 7 P
P IN G N D1 ~ 4 = G N D
C6 5 0
0. 1 u _ 10 V _ X 7 R _ 04
C 65 1
*0 . 1 u _1 0 V _ X 7R _0 4
C 3 22
1 u _ 10 V _ 0 6
C3 2 5
+
C 32 8
*1 0 u _1 0 V _ Y 5 V _ 08
* 10 0 u _6 . 3 V _ B _ A
27 3 G_ D E T #
27
29
35
23
GN D 2
GN D 3
GN D 4
GN D 1 1
G ND 6
G ND 7
G ND 8
G ND 9
G ND 1 0
26
34
40
50
Sheet 32 of 50
Multi I/O, ODD, 3G,
PETn 0
25 20 3G _ E N 27
31 PETp 0 W _ D I S A B LE # 22
P E R n0 PER SET #
33 30
P E R p0 N C (S MB _ C L K ) 32
N C ( S MB _ D A T A ) 3 G_ U S B _P N 4
17 36
Click M74
19 NC 3 N C (U S B _ D - ) 38 3 G_ U S B _P P 4
NC 4 N C (U S B _ D +)
37
39 NC 6 24
5 VS 3 .3 V S NC 7 3 .3 V AU X
41 28
C2 3 1 C 2 32 43 NC 8 1 .5 V_ 1 48
NC 9 1 .5 V_ 2
45 52 3. 3 V S
0 . 1u _ 1 0V _X 7 R _ 0 4 1 0 u _1 0 V _ Y 5 V _ 08 47 NC 10 3 .3 V_ 1 42
NC 11 N C (LE D _ W W A N #)
R4 7 0 49 44 C6 1 4
51 NC 12 L E D_ W L A N # 46 +
NC 13 N C (LE D _ W P A N #)
*1 0K _0 4 1 50 u _ 4V _B _ A
8 8 90 8 -5 20 4
S A T A _L E D #
23 , 3 4 S A T A _ LE D # S A T A _ LE D # 23 , 3 4
J_3G2
J _ 3 G1
3G _ U S B _ P N 4
1
3G _ U S B _ P P 4 1
2
2
8 5 2 05 - 0 2 70 1
R4 9 6 * 4 . 7K _ 0 4
J_ S I M 1
MULTI I/O CONN 5V

LO CK
( TO P V IE W)
J _ A U D I O1 M U I M _C L K R 5 02 * 1 0m i l_ s h ort -N MN
Z 3 0P07 C 3 C7 Z 3 00 8 R4 9 5 *1 0 m li _ sh o rt -N MN P MU I M_ D A TA
5V 3 .3 V M U I M _R S T U I M_ C LK U I M _D A T A MU I M_ V P P
1 C 2 C6
J_ M U L T I 1 MI C 1 -R 2 M U I M _P W R C 1 U I M_ R S T UIM _ V P P C5
2 9 MI C 1 -R U I M_ P W R U I M _G N D
MIC 1 -L 3
1 2 2 9 MI C 1 -L
R 43 * 10 m i _l s h ort - N MNZ P30 1 1 C C D _D E T # 4 C7 2 3 C7 1 9 C7 2 8
3. 3V 3 4 C C D _E N C C D _D E T # 2 7 H E A D P H ON E -R
CC D_ EN 2 7 3 0 H E A D P H ON E -R 5 C 7 25 OPE N *2 2 p _5 0 V _ N P O _0 4 *2 2 p _5 0 V _ N P O _0 4 *2 2 p_ 5 0 V _N P O_ 0 4
A Z _ S D OU T 5 6 S P K OU T R + H E A D P H ON E -L 6 *2 2 p_ 5 0 V _ N P O_ 0 4 91 7 1 8-0 0 6 0A
22 , 2 9 A Z _ S D O U T 7 8 S P K OU T R + 3 0 3 0 H E A D P H ON E -L
AZ _ SY NC S P K OU T R - J D _ S E N S E _M I C 7
22 , 2 9 A Z _ S Y N C 9 10 S P K O UT R- 3 0 2 9 J D _ S E N S E _ MI C
AZ _ S D IN1 SPK_ HP# 8
22 A Z _ S DIN 1 A Z _ R S T# 11 12 U S B _ P N6 3 0 S P K _ HP # J D_ S E NS E
2 2 , 29 , 3 0 A Z _ R S T # U SB_ PN6 2 3 2 9 J D_ S E N S E 9
R 5 70 * 10 m i _l s h ort - N MN P Z 30 1 2 13 14 U SB_ PP6 U S B _P N 7 10
2 2 , 29 A Z _ B I T C L K 15 16 U SB_ PP6 2 3 2 3 U S B _P N 7 U S B _P P 7 11
2 3 U S B _P P 7
C 8 13 C 80 4 8 7 21 6 - 1 60 6 12
F OR E MI
* 3 3p _ 5 0V _ N P O_ 0 4 * 47 p _ 50 V _ N P O_ 04
29 S PDIF O
S P D I F O L 77 Z 3 0 13 13 Layout?
F C M 1 00 5 K F - 1 02 T 0 2
C 81 4
87 2 1 3- 1 3 0 0G
1. SIM ? ? ? ? ? ? ? ? (10mil)
A UD G
1 0 00 p _ 50 V _ X 7R _ 04 2. ? ? ? ? ? ? ? ? G ND
3. SIM hold ? ? ? ? ? G ND? ?
CLICK BOARD LIFT RIGHT 4.SIM CONN ? ? M INI CARD CONN
KEY KEY
SW 6 SW 7
J _ TP1 *T JG -5 33 -S -T / R * TJ G -53 3 -S - T / R For M740
T P B U T TO N _ L 1 2 1 2
1 T P _S C R O L L_ D O W N T P B U T T ON _ L T P B U T T ON _R
3 4 3 4
J_TP2 2 T P _S C R O L L_ U P
3 TP B U T TO N _ R
4
5
6
5
6
Z 30 0 9
1 5 Z 30 1 0
6
7
SW 8 SW 9
8 TP _ C LK *T JG -5 33 -S -T / R * TJ G -53 3 -S - T / R
9 T P _C L K 27 , 3 4 2 4
TP _ D A TA 1 2 1 2
10 T P _D A T A 27 , 3 4 1 3
12 3 4 3 4
11 5V CSW1~2
6- 20 -94 A2 0- 11 2 12 C 28 1
5
6
5
6
*8 7 1 51 -1 2 07 G
0 . 1 u _1 0 V _ X7 R _0 4 For W76
Multi I/O, ODD, 3G, Click M74 B - 33

Schematic Diagrams
New Card, Mini PCIE, USB
3. 3 V S
NEW CARD C7 1 7 *0 . 1 u _1 0 V _ X7 R _0 4
5
L P C _ R S T# 1
4
2
3 .3 V
U4 2 U 35 J _N E W 1
3
C 7 02 0 . 1u _ 1 0V _X 7 R _ 0 4 17 8 NC _ RS T # 7 4 A H C 1G 08 G W N C _P E R S T # 13
AU X IN P E RS T # C 69 3 0. 1 u _ 10 V _ X 7R _ 04 P E RS T #
3 .3 VS 15 N C _3 . 3 V 20 mil 12
A U X OU T +3 . 3 V A U X
6- 01 -74 10 8- Q61
C 7 00 *0 . 1 u _1 0 V _ X7 R _0 4 2 40 mil C 72 1 *0 . 1 u_ 1 0V _X 7 R _ 0 4
3 .3 V IN N C _3 . 3 V S
C 6 91 0 . 1u _ 1 0V _X 7 R _ 0 4 3 14
3 . 3 V OU T C 72 0 0. 1 u _ 10 V _ X 7R _ 04 15 +3 . 3 V
1 .5 VS +3 . 3 V
40 mil C 71 6 *0 . 1 u_ 1 0V _X 7 R _ 0 4
N C _1 . 5 V S
C 7 07 *0 . 1 u _1 0 V _ X7 R _0 4 12 11 9
C 7 08 0 . 1u _ 1 0V _X 7 R _ 0 4 1 .5 V IN 1 . 5 V OU T C 71 3 0. 1 u _ 10 V _ X 7R _ 04 10 +1 . 5 V
+1 . 5 V
10 N C _C P P E # 17
L P C _ R S T# C PPE# N C _C P U S B # CPPE#
2 7 , 28 , 3 1 LP C _ R S T # 6 9 4
19 S Y S RS T # CP U S B # P C I E _W A K E # 11 CPU SB#
23 U S B _O C # 0 O C# 4 , 23 P C I E _ W A K E # W AKE#
2 5 N E W _ C A R D _ C LK R E Q# 16
CL KREQ #
Sheet 33 of 50
1 R 50 0 * 1 00 K _ 0 4 R5 9 1 * 10 K _ 0 4
1 8 , 25 , 3 1 , 35 , 3 9 , 40 S U S B # STBY # 3 .3 VS
R 49 8 * 1 00 K _ 0 4 3 .3 V 2 5 P C I E _C L K _N E W D05 10/2 19
18 R E F C LK +
R5 8 9 * 1 0K _ 0 4 4 18 R 48 4 * 1 0K _ 0 4 2 5 P C I E _C L K _N E W # R E F C LK -
3 .3 V N C R CL K E N
5 20 R 59 0 1 0 K _ 04 22
13 N C S HDN # 2 2 P C I E _ R XP 0 _ N E W _C A R D 21 P E Rp 0
New Card, Mini 14

16
N
N
N
C
C
C
P 22 3 1 N F E 2
G ND
G ND
7
21
2 2 P C I E _ R XN 0 _N E W _ C A R D
2 2 P C I E _ T X P 0_ N E W _ C A R D
2 2 P CIE _ T X N0 _ NE W _ CA R D
C 4 32
C 4 31
0 . 1u _ 1 0V _ X 7 R _ 0 4
0 . 1u _ 1 0V _ X 7 R _ 0 4
P C I E _T X P 0 _N E W _ C A R D _ R 2 5
P C I E _T X N 0 _ N E W _ C A R D _ R 2 4
P E Rn 0
P E Tp 0
P E Tn 0 R E S E RV E D
R E S E RV E D
5
6
Z 3 1 02
Z 3 1 03
US B _ P P 0
PCIE, USB
3
23 U SB_ PP0 US B _ P N 0 2 US B _ D+ 1
EN E P 22 31 NF E2 pin 1, 8, 9, 10, 20 h as 23 U SB_ PN0 US B _ D- GN D
20
in ter na ll y p ul le d h ig h (1 10~ 33 0K 8 GN D 23
9 , 1 0 , 22 , 2 5 S _D A T S MB _ D A T A GN D
oh m) 9 , 1 0 , 22 , 2 5 S _C L K 7 26
S MB _ C L K GN D
1 30 8 0 1-1
G ND1 ~ 4 = G ND
A C NC _ CP P E #
2 2 P C I E _ P R S N T0
D3 2 S C S 33 5 V
R 46 2 * 20 m li _ s ho rt -N MN P
USB PORT MINI CARD Q 24

*A O 34 0 9
D S
3 . 3 V S _W LA N 3. 3 V
R2 4 5 U SBVCC 3 5 U S B _ V C C 3 5_ 2
1 0 K _0 4 60 mil 20 mil R 46 3 C 6 42
G
L 30 H C B 1 6 08 K F -1 2 1 T2 5 J _M I N I 1 *0 . 1 u _1 0 V _ X7 R _0 4
23 U S B _ OC #2 6 3 .3 VS_ W L A N Z 3 11 2
1 2 20 mil * 10 0 K _ 04
R2 4 4 C3 3 9 C 3 48 3 W AKE# 3. 3 V _ 0 6
+ B T_ D A TA 1. 5 V _ 0 U I M_ P W R 1 . 5V S
5 6 0K _ 0 4 5 8
10 0 u _6 . 3 V _ B _ A 0 . 1 u _1 0 V _ X7 R _0 4 B T_ C H C L K U I M_ P W R 10 U I M_ D A TA R 46 5
U I M _D A T A U I M_ C LK
7 12
11 CL KREQ # U I M _C L K 14 U I M_ R S T *1 0 0K _ 0 4 R 4 64
J_ U S B 2 13 R E F C LK - U I M _R E S E T 16 U I M_ V P P *3 30 K _ 0 4
R2 5 4 *1 0 mi l _ sh o rt -N M N P 1 9 R E F C LK + U I M _V P P Z 3 11 3
V+ 15 GN D 0 4
GN D 1 GN D 5
D
4 L32 3 U S B _ P N 5_ R 2
23 US B _ P N 5 D A T A _L D0 3A
1 2 USB_ PP5 _ R 3 G
23 US B _ P P 5 D A T A _H KEY Q2 5 W L A N_ P W R 27
S
G ND1
GN D 2
* W C M 20 1 2 F 2 S -16 1 T 03 4 21 18 *MT N 70 0 2 Z H S 3
R2 5 3 *1 0 mi l _ sh o rt -N M N P G ND 27 GN D 2 GN D 6 26
GN D 3 GN D 7
29 34
U S B -0 4 R S 1 GN D 4 GN D 8 40
U S B _V C C 3 5 _ 2 GN D 9
GN D 1
GN D 2
27 W L A N _D E T# 35 50 W D T _E N 27
23 GN D 1 1 GN D 1 0
60 mil 60 mil P E Tn 0 W L A N_ E N
25 20 W LA N _ E N 2 7 , 34
31 P E Tp 0 W _D I S A B L E # 22
P E Rn 0 P ERSET # Z 3 10 4 P CI_ RS T # 31
C 29 2 C3 1 8 33 30 R 12 4 * 0 _0 4 S _C LK 9 , 1 0, 2 2 , 2 5
+ P E Rp 0 N C (S M B _C L K ) 32 Z 3 10 5 R 12 3 * 0 _0 4
* 10 0 u_ 6 . 3 V _ B _A *0 . 1 u _1 0 V _ X7 R _0 4 17 N C (S MB _D A T A ) 36 U S B _P N 1 S _D A T 9 , 1 0, 2 2 , 2 5
2 7 80 P O R T _D E T # NC3 N C (U S B _ D -) U SB_ PN1 23
19 38 U S B _P P 1
27 3 IN1 Z 3 1 06 37 NC4 N C ( U S B _D + ) U SB_ PP1 23
NC6
20 mil
J _ USB1 39 24
NC7 3 . 3V A U X
1
V+ 3 . 3 V S _ W LA N
41
NC8 1. 5 V _ 1
28 40 mil 3 . 3 V S _ W L A N
R2 4 3 *1 0 mi l _ sh o r t -N M N P 43 48
U S B _P N 3 _R 2 Z 3 1 09 45 NC9 1. 5 V _ 2 52 1 .5 VS
DA T A _ L Z 3 1 10 NC1 0 3. 3 V _ 1 3 .3 VS_ W L A N
? ? ? ? ? ? ? 47 42 20 mil
4 L 28 3 U S B _P P 3_ R 3 49 NC1 1 N C (L E D _ W W A N # ) 44
23 US B _ P N 3 DA T A _ H NC1 2 LE D _ W LA N #
51 46 8 0 CL K 27
1 2 4 VD D3 NC1 3 N C (L E D _ W P A N # )
GN D 1
GN D 2
23 US B _ P P 3 GN D
*W C M2 0 12 F 2 S -1 6 1T 0 3 8 89 0 8- 52 0 4
R2 4 2 *1 0 mi l _ sh o r t -N M N P U S B -0 4R S 1
G ND 2
GN D 1
Add 80PORT
J20090409
5V US B V C C3 5
U 14 100 MIL
4 1
VIN VO UT
3 . 3 V S _W LA N 1 . 5V S 3 .3 V
C3 5 0 3 5 C 33 5 C 2 93 C3 4 3
VIN VO UT C6 3 7 C6 4 0 C 7 03 C7 1 4 C1 1 7
1 0u _ 1 0V _ Y 5V _ 0 8 2 0 . 1 u _1 0 V _ X7 R _0 4 *0 . 1u _ 1 0V _X 7 R _ 0 4 1 0u _ 1 0V _ Y 5V _ 0 8
GN D 0. 1 u _ 10 V _ X 7R _ 04 *1 0 u _1 0 V _ Y 5 V _ 08 0. 1 u _ 10 V _ X 7R _0 4 1 0u _ 10 V _ Y 5 V _ 0 8 0 . 1u _ 1 0V _ X 7 R _ 0 4
R T9 7 0 1-C P L
B - 34 New Card, Mini PCIE, USB

Schematic Diagrams
LED, PC Beep, TP, FP
LED 5 VS 5 VS SCROLL
3 . 3V S
LOCK
R3 8 4 R3 8 5
LED
VD D3 V D D3 R 3 91
47 0 _0 4 4 70 _ 04
22 0 _0 4
Z 3 2 09 Z 3 2 10
R 3 80 R 38 1 Z 3 21 8
A
1
3
2 20 _ 0 4 2 2 0_ 0 4 D 13 WLAN/BT LED D1 8
SG
Y
Z 32 0 1 Z 32 0 2 K P B -30 2 5 Y S GC K P -2 0 12 S G C
1
C
D1 1 Z 3 2 11 Z 3 2 12
AC IN/POWER ON LED
SG
Y
C
K P B -3 0 25 Y S G C
B B L E D _S C R O LL #
2 0 ,2 7 BT _ EN W L A N _E N 2 7, 33 L E D _ S C R OL L # 27
4
Q 32 Q3 1
D TC 11 4 E U A D TC 1 14 E U A
E
27 LE D _A C I N # LE D _ P W R # 2 7
3 .3 VS
HDD/CD-ROM
Sheet 34 of 50
LED
V DD 3 V DD 3
3. 3 V S NUM LOCK
LED
3. 3 V S CAPS LOCK
LED R 38 8
LED, PC Beep, TP,
FP
2 2 0_ 0 4
R 38 9 R 3 90
R3 8 2 R3 8 3
2 2 0_ 0 4 2 2 0 _0 4
2 2 0 _0 4 22 0 _ 04 Z32 22
Z 32 2 0 Z 32 2 1
A
Z 3 2 05 Z 3 2 06
D1 6 D1 7 D1 5
1
K P -2 01 2 S GC K P -2 0 12 S G C
D 12 BAT CHARGE/FULL LED K P -20 1 2 S GC
SG
Y
K P B - 30 2 5Y S GC
C
2
L E D_ CA P # S A T A _L E D #
L E D _N U M # L E D_ CA P # 2 7 S A T A _L E D # 2 3 , 3 2
2 7 L E D _ B A T _ C H G# L E D _ B A T _ F U L L # 27 L E D _ N U M# 2 7
PC BEEP FP CONN CLICK CONN For M76

5 V S _ TP
R 2 92 * 1 0m i l_ s h or t -N MN P F or M 76 5 VS
R2 3 6 * 20 m li _ s ho rt -N MN P
R2 3 5 *0 _0 6
5V
R 23 0 R 2 26
3 .3 VS_ F P L2 9 3 .3 VS
C 4 06 3 .3 VS J_ F P 1 H C B 10 0 5 K F -12 1 T 20 J _ TP2 1 0 K _ 04 10 K _ 0 4
*0 . 1 u _1 6 V _ Y 5 V _ 04 R 28 8 *1 0 K _ 04 1
1
US B _ P P 2 23 2
2 C 3 36 3
3 US B _ P N2 23 T P_ DAT A 2 7, 3 2
5
C 81 1 4 T P_ CL K 2 7, 3 2
1 4 0 . 1 u _1 0 V _ X7 R _0 4 5
27 KBC _ BEEP 1 u _1 0 V _ 06
4 K B C_ B E E P _ R 85 2 0 1-0 4 0 51 6
Z 3 2 16 2
J_FP1 8 5 2 01 -0 6 05 1
3 .3 V S C4 0 5 U1 8 4 1 C3 1 4 C 30 8 C 3 02
3
* 0 . 1u _ 1 6V _ Y 5V _ 0 4 *7 4A H C 1 G 08 G W
J_TP1 1 u_ 1 0 V _0 6 4 7 p_ 5 0 V _ N P O_ 0 447 p _ 50 V _ N P O _ 04
6 -01 -7 41 08- Q6 1 1
5
1 C4 1 9
4 1 u _ 10 V _ 0 6
2 Z 3 2 17 R2 8 1 *1 M_ 0 4 6
BEEP 29
U1 7
* 74 L V C 1 G 14 GW C 42 3
Fo r W7 6
3
* 22 0 0 p_ 5 0 V _X 7 R _ 0 4 C4 3 3
1 u _ 10 V _ 0 6
J _F P 2 3. 3 V S _ F P
22 S P K R OU T
6
5
4 U S B _P N 2 23
3 U S B _P P 2 23
2
1
*8 5 2 01 -0 6 05 1
LED, PC Beep, TP, FP B - 35

Schematic Diagrams
System Power
1.2VS,1.5VS,1.8VS,3.3VS,5VS
Sheet 35 of 50
System Power
PQ 5 8 P Q 26 P Q2 3
SY S1 5 V V DD 5 A O 4 4 68 5V S S Y S 1 5V V D D3 A O 44 6 8 3 .3 V S S Y S 1 5V 1 .8 V A O4 4 6 8 1 . 8V S
8 8 8
4A 7
6
3
2
4A 3A 7
6
3
2
3A 8A 7
6
3
2
8A
PR 1 9 0 5 1 P R 79 5 1 P R6 6 5 1
P C1 9 1 P C 1 94 PR1 8 1 PC 7 4 P C7 5 PR 8 0 PC 6 3 P C6 4 PR 6 8
1 M _0 4 1 M_ 0 4 1 M_ 0 4
4
0. 1u _ 1 0 V _ X7 R _ 041 0 u _1 0 V _ Y 5V _0 810 0 K _ 0 4 0 . 1 u _ 10 V _ X 7 R _ 0 41 0u _ 1 0 V _ Y 5 V _ 0 8* 10 0 K _ 0 4 0 . 1 u _ 10 V _ X 7 R _ 0 410 u _ 1 0 V _ Y 5 V _ 0 8* 10 0 K _ 0 4
Z3301 Z 3 3 02 Z 3 30 5
D
PQ 6 2 P C1 9 8 P Q 25 P C7 3 P Q2 2 PC 6 2
SU SB G M T N 7 0 0 2Z H S 3 S US B G MT N 7 00 2 Z H S 3 SU SB PR 6 7 *1 0 m i _l s h o rt Z 33 1 1 G MT N 70 0 2 Z H S 3
2 20 0 p _ 50 V _ X 7 R _ 0 4 0 . 0 1 u _ 50 V _ X 7 R _ 0 4 0 . 0 3 3 u_ 1 6 V _ X 7 R _ 0 4
S
N V _ P GO OD P R 64 *0 _ 0 4
V DD 5
P Q 38 P Q1 6
S Y S 1 5V 1 .5 V A O 44 6 8 1 .5 V S S Y S 1 5V 1 .2 V A O4 4 6 8 1 .2 VS
P R7 8 8 8
1 00 K _ 0 4
1.5A 7
6
3
2
1.5A 3A 7
6
3
2
3A
P R 11 5 5 1 P R5 6 5 1
S US B PC 1 0 8 P C1 1 0 PR 1 1 4 PC 5 6 P C5 9 PR 5 4
SUSB 1 8 ,4 1 1 M_ 0 4 1 M_ 0 4
D
4
0 . 1 u _ 10 V _ X 7 R _ 0 41 0u _ 1 0 V _ Y 5 V _ 0 8* 10 0 K _ 0 4 0 . 1 u _ 10 V _ X 7 R _ 0 410 u _ 1 0 V _ Y 5 V _ 0 81 0 0 K _ 04
P Q2 4
G MT N 70 0 2 Z H S 3 Z 3 3 03 Z 3 30 4
1 8 , 2 5, 3 1 , 3 3 , 3 9 , 40 S U S B #
D
S
P R 77 P Q 37 P C1 0 9 P Q1 5 PC 5 7
S US B G MT N 7 00 2 Z H S 3 S USB G MT N 70 0 2 Z H S 3
1 0 0K _0 4 0 . 0 3 3 u _1 6 V _ X 7 R _ 0 4 0 . 0 1 u _5 0 V _ X 7 R _ 0 4
S
B - 36 System Power
Schematic Diagrams
AC-In, Charger
VA
P Q 31
VIN
4
A M 48 3 5P Ch ar ge Cur re nt 2.0 A
1 5
2 6 Ch ar ge Vol ta ge 12. 6V
3 7
J_ D C -JA C K 1 PL 1 VA 8 To ta l P owe r 60W
2D C - G2 1 3-B 49 H C B 45 3 2K F - 80 0 T6 0 P Q3 4 A
Z 3 4 01 8 S P 8 K 1 0 S F D 5 TB PL 6 P R1 9 BAT
1 S I 4 8 35 B D Y
7 3 P R 83 20 m _2 0 2 1 0 U H _6 . 8 *7 . 3* 3. 5 3A 2 0m _ 20
2 6 2 1 7 Z 34 0 5 Z 3 4 09 BAT
G ND1 P R 84 5 1
G ND2
P C3 0
P Q 28
P C 32
PC3 4
PC3 3
G ND3
5
6
1 3 0K _ 1 %_ 0 4 PR8 2
G ND4
8
P C1 PC 2 P R8 8 P C7 6 20 0 K _1 % _0 4 P C 26
PC 3 6 P C 35
0 . 1 u _5 0 V _Y 5V _006. 1 u_ 5 0V _ Y 5V _ 0160K _ 0 8 0 . 1 u _5 0 V _Y 5V _ 0 6 Z 34 3 33 0 . 1 u_ 5 0V _ Y 5V _ 0 6
4 . 7 u_ 2 5 V _X 5 R _ 0 8
4 . 7 u _2 5 V _X 5 R _0 8
4 . 7u _ 2 5V _ X 5 R _ 0 8
4 . 7 u _2 5 V _X 5 R _ 048. 7 u_ 2 5V _ X 5 R _ 08
4 . 7u _ 25 V _ X 5 R _ 08
P R 85 PR3 2 *1 0m i _l s ho rt P Q3 4 B
4
P R2 4 S P 8 K 10 S F D 5 T B
1 0 K _1 % _0 4 *1 0m i _l s h ort
P R8 6
PC4 0
C
0. 1 u _2 5 V _ X7 R _ 0 6
A PC5 3 1 u_ 2 5V _ X 7 R _ 08
Sheet 36 of 50
10 0 K _0 4 PD4 F M0 5 4 0- N
VA
S GN D 5 P R 2 7 * 0_ 0 4 P C2 2 0 . 1 u _5 0 V _Y 5 V _0 6 PC1 5 P C1 9
AC-In, Charger
Z3 408
Z 3 40 6
Z 3 4 04
Z 34 0 3
Z 3 40 7
P R3 3 * 0_ 0 4 4 . 7u _ 2 5V _ X 5R _0 84. 7u _ 25 V _ X5 R _0 8
VA
32
31
29
28
26
30
27
25
P U2
P C 2 0 7 0 . 1u _ 50 V _ Y 5 V _ 06
PG ND
C B
LX
VB
CT L 2
OU T -2
C E L LS
OU T - 1
1 24
2 VC C VIN 23 C TL P C 38 0 . 1u _ 50 V _ Y 5 V _ 06
Z 3 41 0 -I N C 1 C TL 1
3 22
Z 34 1 1 4 + INC 1 GN D 21 Z3419
P Q4 PR2 0 5 AC IN VR EF 20 Z 3 4 2 0 P R3 6 3 9 . 2K _ 1 % _0 4
A C OK TRERMAL PAD RT
A O3 40 9 30 0 K _1 % _ 04 6 19 Z 3 4 2 1 P C4 9 0 . 1 u_ 1 0 V _X 7 R _ 04
-I N E 3 C S
C OM P 2
BAT S D Z 34 2 6 Z 3 41 2 7 18 P C2 3
OU T C 2
O UT C1
C OM P 3
B A T1 _ V OL T 2 7 AD J 1 A DJ 3
+ INC 2
-I N C 2
A DJ 2
PR 3 0 8 17
-I N E 1
P R 34 C OMP 1 BAT T 33 S GN D 5 0. 1u _ 50 V _ Y 5 V _ 06
PR2 1 6 20 K _ 1 %_ 0 4 1 0 K _ 1% _ 04 S GN D
G
P R3 5 MB 3 9 A 13 2 P R2 1 PR3 7
9
10
12
13
15
2 00 K _ 04
11
14
16
P R1 6 P C 20 1 6. 2 K _ 1% _ 0 4 S GN D 5 1K _ 1 % _0 4 2 1K _ 1 %_ 0 4
P C3 9
6 0. 4 K _ 1 %_ 0 4 0 . 1 u_ 1 0V _ X 7 R _ 04
0 . 0 1 u_ 5 0V _ X 7R _ 04
J20090409
P R2 1 7
S GN D 5 S G ND5 PR 3 8 * 10 m i _l s ho rt
0 _0 4 P R 1 95 * 10 m i _l s ho rt P C4 2
P R 29 PR3 9
Z 3 4 27 PR35 = 15K for M760SU 10 0 p _5 0 V _N P O_ 0 4
D
(Total Power Limit: PC 1 7 * 22 p _ 50 V _ N P O_ 0 4 1 0 K _ 1% _ 04 1 0K _ 1 %_ 0 4

80W)
G PQ 3
SYS5 V MT N 7 0 02 Z H S 3 P C2 1 P R1 7 2 2K _ 1 %_ 0 4
S
10 0 0p _ 5 0V _ X 7R _0 4 S GN D 5
P C 46
1 0 00 p _ 50 V _ X7 R _ 0 4
V D D3
S G ND5
P R5 1
1 0K _ 0 4 Bt te ry Vo lt age : PM BAT1
SYS5 V
AC_ IN # 1 3 , 27
9V ~1 2. 6V 1
2
Z 3 4 36
3
D
Z 3 4 35
PQ 1 3 PR2 2 P L5 H C B 1 0 05 K F - 1 2 1T 2 0 Z 3 4 30 4
P R5 0 1 M_ 0 4 Z 34 2 9 G M TN 7 00 2 Z H S 3 27 S M C_ B A T P L4 H C B 1 0 05 K F - 1 2 1T 2 0 Z 3 4 31 5
VA 27 S M D_ B A T Z 3 4 32 6
1 00 K _ 0 4 27 B A T _D E T P L3 H C B 1 0 05 K F - 1 2 1T 2 0
S
7
P R 49 CT L 8
9
D
2 0 0K _ 0 4 A L L TO P - C 1 4 4P 8 -1 0 9A 8 -L
P Q5 P C9 7 P C9 6 P C 98
P R 23 1 00 K _ 04 Z 3 42 8 G P R1 4 P R 15
S YS5 V
MT N 7 0 0 2Z H S 3 30 p _5 0 V _ N P O_ 0340 p _5 0 V _N P O_ 0340 p_ 5 0V _ N P O_ 04*1 5 mi l _ sh o rt * 15 m i l_ s ho rt
D
PR5 5 *1 5 mi l _s h o rt
P Q6
1
27 C H G_ E N G
MT N 7 0 02 Z H S 3 P J 13
S
1 mm S G ND5
2
BAT VIN
PC2 7 P C2 5 P C2 8 PC 1 6 P C 47 P C 18 P C 37
0 . 1u _ 50 V _ Y 5 V _ 060. 1 u _ 50 V _ Y 5 V _0 60 . 1 u_ 5 0V _ Y 5 V _ 0 6 0 . 1 u_ 5 0V _ Y 5 V _ 0 6. 1 u_ 5 0V _ Y 5V _ 0 6 0 . 1 u_ 5 0 V _Y 5V _ 006. 1 u_ 5 0V _ Y 5 V _ 0 6
AC-In, Charger B - 37
Schematic Diagrams
VCore
V IN 5V
VCORE FOR PENRYN CPU V IN
2008/06/04
V -R C 1
P C2 0 4 PC2 0 6
1 0 0_ 1 % _ 0 4
1 5u _ 2 5 V _ 6 . 3* 4 . 4 _ C
PC 8 1 + +
*1 5 u _ 25 V _ 6 . 3 *4 . 4 _ C
PC 8 4 PD8
1 u _ 1 0V _0 6
1 0 00 p _ 5 0 V _ X7 R _ 04 F M0 5 4 0 - N P R6
? ? ? Santa Rosa CPU ? ? ? ? ? ? V IN
C
10 _ 0 6
PR 9 2 *1 0 m il _ s h or t Z 3 50 1
PC 7 9 P C 77 P C7 8 PC 2 0 2
P R 1 00
+ 6 80 u _ 2 5 V _ 40 0 * 68 0 _ B
5
6
7
8
PR 2 *0 _ 0 4 PC8 0 P R 90
* 15 m i l _ sh o rt * 0. 1u _ 5 0 V _ Y 5 V _ 0*46. 7 u _ 2 5V _X 5 R _0* 84 . 7 u _2 5 V _ X 5 R _ 0 8
BST1
1u _ 2 5 V _ X 7R _ 0 8 Z 3 51 4 4
S G ND 3 P R 10 1
2
3
1
7 . 5 K _ 1 % _ 04 P C 89 PQ 2 9
Z 3 50 2 I R F 7 4 1 3Z P B F
PR 3 0 _ 04 DPR SL _ STP
2 ,6 H_ D PR ST P #
E N_ V C O RE 1 5 0 0 0p _ 5 0 V _ X 7R _ 0 6 PQ 2
Sheet 37 of 50 PR 9 1 *0 _ 0 4 DP R S L TG 1 PQ 3 0 R QW 20 0 N 03 F D 5 PL 2 V CO RE
6 P M_ D P R S L P V R
close to IMVP6 RQ W 2 0 0 N0 3 F D 5 0 . 5 U H _ 1 0* 1 0 *4 . 1
20 A 40A
VPN 1
D RN 1
? C4 ? PR91 Del 3 .3 V S BG 1
I SH
D R N1
PD 1
VCore
C
5
6
7
8
5
6
7
8
F M 5 8 22
CL K E N# P R8 9 P C1 0 7 P C1 0 6
44
43
41
40
38
37
35
34
25 C L KEN #
42
39
36
PR4 PU 1 4 4 10_06 + +
P C8 3 3 3 0 u _ 2. 5V _V _B 3 30 u _ 2 . 5 V _ V _ B
D PR SL
V P N1
VIN 1
B ST 1
TG 1
B G1
V5 _ 1
D PR STP#
EN
ISH
Z 3 51 5
DR N1
2
3
1
2
3
1
P C6 1 00 p _ 5 0 V _ N P O _ 0 4 68 0 _ 0 4
A
0. 1 u _ 2 5 V _ X7 R _ 0 6 P C 82
P R1 0 2 3 3K _1 % _ 0 4 P R9 6 1 33
1 3 0K _ 1% _ 0 4 V CO R E _ V RE F 2 C LK E N # CS1 + 32 C S1 N 1 0 0 0 p _5 0 V _ X 7 R _ 0 6
V CO R E _ HY S 3 VR EF C S1 - C S2 N
C S1 N
31 J20090413 2008/06/04
V CO R E _ CL SE T 4 H YS C S2 - 30 P R9 5 0_06 Delete PC86
P R1 0 3 2 20 K _ 1 % _ 0 4 H _V I D 6 5 C LS E T CS2 + 29 Z35 03
3 H _ V ID 6 H _V I D 5 V ID 6 E R RO UT V CC A
P R9 7 6 TRERMAL PAD 28
1 3 0K _ 1% _ 0 4 3 H _ V ID 5 H _V I D 4 7 V ID 5 VCC A 27
1K _1 % _ 0 4
3 H _ V ID 4 V ID 4 A G ND
P C8 7 1 00 p _ 5 0 V _ N P O _ 0 4 H _V I D 3 8 26 DA C
PR 5
3 H _ V ID 3 H _V I D 2 V ID 3 DAC VC _ SS
9 25 P R1 1 3 0_06
0 . 0 1u _ 5 0 V _ X 7 R _ 0 4
3 H _ V ID 2 H _V I D 1 1 0 V ID 2 SS 24
3 H _ V ID 1 V ID 1 DR P +
P C5 1 00 0 p _ 5 0V _X 7 R _0 4 H _V I D 0 1 1 23
P C 9 1 0 0 0 p_ 5 0 V _ X 7 R _ 0 4
3 H _ V ID 0 V ID 0 DR P -
1 5 0 0 p_ 5 0 V _ 0 4
C S2 N
P W R GD
1 u _ 1 0V _0 6
P C 4 1 0 0 p _5 0 V _ N P O_ 0 4
7/24 Power PR115 3. 3 V S
E -R C
V P N2
B ST2
DR N2
VIN 2
V5 _ 2
G ND
F B+
TG 2
B G2
PSI#
S G ND 3
from 300K_1%_04
FB-
V IN + P C1 0 0 P C 1 01
PR 1 1 S C 45 2 + +
change to
45
12
VPN 2 1 3
15
16
18
19
21
22
1 K_ 0 4 P C9 3 3 30 u _ 2 . 5 V _ V _ B * 33 0 u _ 2. 5V _V _B
14
17
20
220K_1%_04. 5 6 0 U _ 2 . 5 V _ 6 . 6 *6 . 6 * 5. 9
PR 1 2 * 1 0m i l _ sh o r t Z3 504 P C3 1 PC 2 4 P C2 9 +P C 9 9
PC 8
PC 7
6 , 3 1 D E LA Y _ P W R G D FB+
PC 3
5
6
7
8
P R7 10_04
3 VC C SEN SE FB-
3 VSS SEN SE P R8 10_04 0 . 1 u _ 5 0 V _ Y 5 V _ 0* 64. 7u _ 2 5 V _ X 5R _ 0*48. 7 u _ 2 5V _X 5 R _01 85 u _ 2 5V _6 . 3 * 4 . 4_ C
PR 1 8 * 1 0m i l _ sh o r t Z3 505 4
2 PS I#
D RP - V C OR E _ V R E F
2
3
1
D RP + S G ND 3 PQ 8
PR 1 3 I R F 7 4 1 3Z P B F
PR 9 8 7. 5 K _1 % _ 0 4 C S 2 P P C 85 1 5 00 0 p _ 5 0V _X 7 R _0 6
P C*11 20 0 p_ 5 0 V _ N P O_ 0 4
P C*11 0 0 p_ 5 0 V _ N P O_ 0 4
P C*19 50 0 p_ 5 0 V _ N P O_ 0 4
P C*19 0 0 p_ 5 0 V _ N P O_ 0 4
D R N2
*6 8 0 _ 0 4 PQ 3 2
TG 2 P R1 0 *1 0 m i l_ s h o rt Z 3 5 0 6 PQ 3 3 R QW 20 0 N 03 F D 5 P L7
B G2 R QW 20 0 N 03 F D 5 0 . 5 U H _ 1 0 *1 0 *4 . 1
3. 3 V S
20 A
5V
C
5
6
7
8
5
6
7
8
P R 11 2
A
PD 9
1 0 0 _ 1% _ 0 4
PC 1 3 P C 14 PD 2 P C 11 4 4 1 0_ 0 6
P R9 9
F M 5 8 22
2
3
1
2
3
1
S GN D 3S GN D 3S GN D 3S GN D 3 1 0 00 p _ 5 0 V _ X7 R _ 04 1 u _2 5 V _ X 7 R _ 0 8 F M 0 5 40 -N 1 u _1 0 V _ 0 6 Z3507
A
C
PR 1 0 8 * 1 5 m li _ s ho r t P C 10 5 VC _ SS PR 4 8 * 0_ 0 4 Z 3 5 10
V -R C 2 1 00 0 p _ 5 0V _X 7 R _ 06
5V
J20090413 S GN D 3 P C 55 PC5 4
B S T 2P R 9 *1 0 m il _ s h or t Z3 516 * 0. 1 u _ 1 6 V _ Y 5 V _ 0 4
V IN
*0 . 0 2 2 u_ 1 6 V _ X 7 R _ 0 4
PU 4 Z 3 5 11
D
5
S G ND 3 * 74 A H C T1 G 0 2G W
C L KEN # 1 P Q 14
P R 53 * 0 _ 04 4 Z 3 5 09 G
P RT 1 * MT N 7 0 02 Z H S 3
D PR SL Z3 50 82
S
5V PR 9 3 DR P _ L 1 2 1 C S1 N
PR 4 0 10 K _ 0 4 P R 52 * 0 _ 04
2 8K _1 % _ 0 4
3
EN_ VC O RE 10 0 K _ N TC _ 0 6 _A D PR SL _ STP
D RN 1 P R9 4 P C9 4 0 . 0 33 u _ 1 6 V _ X7 R _ 0 4 P R 1 06
PR 4 6 P R4 1 S GN D 3
47 K _0 4 DR P +
1 7 . 4 K _ 1 % _0 4
D
1 0 0 K_ 0 4 *1 0 K _ 0 4 D CR _ DR 1 P R1 0 7 4 7 K_ 0 4
Z35 13 G D CR _ DR 2 P R1 0 4 4 7 K_ 0 4 P C 92 P R1 0 5
PQ 9
D
S
1
MT N 7 0 02 Z H S 3 6 80 p _ 5 0 V _ X 7R _ 09 4. 1 K _ 1 % _ 0 6
P J 14 D RN 2 P R1 1 1 P C8 8 0 . 0 33 u _ 1 6 V _ X7 R _ 0 4 P R 1 09
P R4 7 *1 0 m li _ s h o rt Z 35 1 2G 1m m DR P -
27 V C OR E _ ON 47 K _0 4
1 7 . 4 K _ 1 % _0 4
P RT 2
S
PQ 1 2
MT N 70 0 2 Z H S 3 P R 1 10 DR P _ L 2 2 1 C S2 N
2 8K _1 % _ 0 4
1 0 0 K _ N T C _ 06 _ A
B - 38 VCore
Schematic Diagrams
VDD3, VDD5
P C 17 0 C A
SY S5 V
0 . 0 1u _ 5 0V _X 7 R _ 0 4
V I N1 Z 3 6 19 Z 36 2 5 P D 22 F M0 5 4 0- N
INT V C C2
P R1 5 8 10 _ 0 6 VIN 2 A C
SY S1 0 V
A
P C 1 64 P C 16 8 P C1 5 1 P D 20 F M0 5 4 0- N P C 16 6
P D1 7 0 . 1 u _5 0 V _ Y 5 V _ 0 6 P D 16 1 u _1 0 V _ 0 6 4 . 7 u _ 10 V _ X 5 R _ 0 8
F M0 5 40 -N 2 2 00 p _ 50 V _ X 7 R _ 0 4
VIN F M0 5 4 0-N V IN P C 16 7 C A
0 . 0 1u _ 5 0V _X 7 R _ 0 4
C
Z 36 1 8 Z 36 3 1 Z 36 2 6 P D 19 F M0 5 4 0- N
P C1 3 4 P C 1 93 P C 1 36 A C
SY S1 5 V
P C 1 54 P C1 9 7 P C1 9 5
18
19
21
15
4. 7 u _ 25 V _ X 5 R _ 048. 7 u _2 5 V _ X 5R _ 080 . 1 u _5 0 V _ Y 5 V _ 0 6 0 . 1 u _2 5 V _ X 7R _ 06 P D 18 F M0 5 4 0- N P C 14 6
P C 16 3 4 . 7 u _ 25 V _ X 5 R _ 0 8 4 . 7u _ 2 5V _X 5 R _ 0 8
IN T VC C
P Q 48
B OO S T 1
B OO S T 2
V IN
0 . 1 u _2 5 V _ X 7R _ 06 2 2 00 p _ 50 V _ X 7 R _ 0 4
8
7
6
5
5
6
7
8
A O4 4 6 8
P Q6 0
4 Z 3 6 16 22 14 Z 36 2 1 4 A O4 4 6 8
TG 1 T G2
3
2
1
1
2
3
V DD5 SY S5 V
P R1 6 7 PL 1 2 P L 13 P R 19 4 SY S3 V VD D3
PJ 8
1 0m _ 1 2 4 . 7 U H _ 6 . 8* 7 . 3* 3 . 5 4 . 7 U H _ 6 . 8* 7 . 3* 3 . 5 1 0 m_ 1 2 PJ 1 1
2 1 4A Z 3 6 17 23
SW 1 SW 2
13 Z3 622 5A 1 2
Sheet 38 of 50
P Q 47
C
5m m
8
7
6
5
5
6
7
8
5m m A O4 4 6 8 PD 2 3 P C1 9 6 P C 19 9
PC1 5 7 + P C 17 2 PD1 5 P Q 65 +
Z 3 6 19 Z 36 2 3 F M 58 2 2
0 . 1u _ 1 0 V _X 7 R _0 4 1 5 0 u_ 6 . 3 V _ V _ A 4 20 17 4 15 0 u _ 6. 3 V _ V _ A 0 . 1 u_ 1 0 V _ X7 R _0 4
F M5 8 22 BG 1 B G2 A O4 4 6 8
VDD3, VDD5
A
3
2
1
1
2
3
A
Z3 61 5 P R 1 73 10 _ 0 4 Z 3 6 02 27 8 Z 36 1 4 P R 1 71 1 0 _0 4 Z 36 2 4
S E NS E 1 + S E NS E 2 + P C 1 81
P C 1 79 1 0 00 p _ 5 0V _ X 7 R _ 0 4
1 0 0 0p _ 5 0V _ X 7 R _ 0 4
P R 1 75 10 _ 0 4 Z 3 6 01 28 7 Z 36 1 3 P R 1 72 1 0 _0 4
S E NS E 1 - SEN SE2 -
Ra P R1 8 2
P C 1 90 10 5 K _ 1 %_ 0 6 P R 18 4 4 7K _ 0 4 Z 3 61 0 P C 19 2 2 20 p _ 50 V _ N P O_ 0 4 Z 3 60 7 2 11 Z3629 P R 1 50 *1 5 m i _l s h ort
IT H 1 E X T V CC 5V
* 18 0 p _ 50 V _ N P O_ 0 4
P C 18 6 *1 0 0 p_ 5 0 V _ N P O _0 4
Z 3 6 03 3 5 Z 36 0 9 P C 1 89 2 2 0p _ 5 0V _ N P O_ 0Z 436 1 1 P R 17 9 1 5 K _ 04
VF B1 IT H2
P R 18 3 PC 1 8 7
P R 16 0 *0 _ 04 12 P C 1 88 *3 0 p _5 0 V _ N P O_ 0 4 Ra
P G OO D
6 3 . 4K _1 % _ 04 * 1 00 0 p _5 0 V _ X 7R _ 04
Rb P R1 8 0 P R 16 4 *1 0 m li _ s ho rt Z 3 6 05 24
I NT V C C2 M OD E / P L L I N Z 36 1 2
20 K _ 1 % _0 4 4
P R 16 6 1 0K _ 0 4 Z 3 6 04 25 VF B2
F R E Q / P LL F L T R
T K/SS 1
T K/SS 2
P R 16 9 3 . 3K _ 1 % _ 04 16 PR1 8 5
RU N2
RU N1
IL IM
PG ND
20 K _ 1 % _0 4
S GN D 4 S GN D 4 PU 8
Rb
10
26
L T C 3 8 50 P NC 1 N C_ 0 4
PIN2 9= SGND4
E N _3 V E N_ 5 V S G ND 4 S GN D 4
T K /SS 2
E N _ 3V
E N _ 5V
S GN D 4
Z 36 3 2
Z 36 3 3
SY S5 V P R 17 7 *0 _ 04 T K /SS2
D
P Q 66 P Q6 3 5V IN T V CC 2 P R1 6 5 * 1 0m i l _s h o rt
INT V C C2 SYS5 V
M TN 7 00 2 Z H S 3 M T N 7 0 02 Z H S 3 P R 17 4
G G *0 _ 0 4
S
E
P R 1 91 PR1 8 9
1 0 K_ 0 4 10 K _ 0 4
S GN D 4 S GN D 4 P C 17 6 PC1 7 7 P C1 8 4 P C 18 5 D D _ ON # B P Q5 5
3 9, 4 0 D D _ ON #
S GN D 4 P R 16 8 D T A 1 14 E U A
0 . 0 1 u _5 0 V _ X 7 R _ 0 4
Z3 634
0. 0 2 2 u _1 6 V _ X 7 R _ 0 4
0 . 01 u _ 5 0V _ X 7 R _0 4
0 . 0 1u _ 5 0V _X 7 R _ 04
C
*1 0 K _ 04
D
D D _ ON H
1
D D_ O NH 40
D
1
P Q6 4 PJ 1 5
P R 19 2 PJ 1 0 P C2 0 0 MT N 7 0 0 2 Z H S 3 27 D D_ O N G 1m m
1 00 K _ 0 4 4 0 mi l G P Q5 9 P C1 8 2 PR 1 7 8
PM _ TH RM TRIP# 2 2
2
S
0 . 1u _ 1 0V _X 5 R _ 0 4 MT N 7 0 0 2 Z H S 3
S
2
P R1 8 7 0. 1 u _ 10 V _ X 7 R _ 0240 0 K _ 04
S G N D 4 S GN D 4 S G N D 4 S GN D 4
1 0 0 K _ 04
P Q2 7 P Q5 4
A O4 4 68 A O4 4 68
S Y S 1 5V VD D3 8 3. 3 V S Y S 1 5V VD D5 8 5V
7 3 7 3
3A 6 2
3A 4A 6 2
4A
5 1 Power Plane 5 1 Power Plane
P R 19 3 P R 17 6
P R8 1 P R1 6 1
4
1 M_ 0 4 1 M_ 0 4
10 0 K _ 0 4 1 00 K _ 0 4
Z 3 62 8 Z 3 62 7
PQ 6 7 PQ 5 6
D
P C 20 1 M TN 7 00 2 Z H S 3 P C 18 0 M TN 7 00 2 Z H S 3
0 . 0 1u _ 5 0V _X 7 R _ 0 4 G D D _O N # 2 2 00 p _ 50 V _ X 7 R _ 0 4 G D D _O N #
S
VDD3, VDD5 B - 39
Schematic Diagrams
1.05VS, 1.2V, 1.5V
P R 12 3 1 0_ 0 6 P R 1 27 1 0 _0 4 PC1 3 3 1 U _ 1 0V _ 0 6
5V
P R 1 26 1 0 _0 4 PC1 3 1 1 U _ 1 0V _ 0 6
S GN D SG ND 1 VIN
V IN 3 .3 V P R 15 6 1 0 K _ 04
A
P D 12
P D 14 31 1 . 05 V S _ P W R GD F M 05 4 0 -N P C1 2 5 P C 12 7 P C 1 28 P C1 2 6
PC1 2 1 P C1 2 3 PC1 2 4 F M 05 4 0 -N
P C 16 1 . 0 01 U _5 0 V _ 04 . 1 U _ 50 V _ 0 6 4 . 7 U _ 25 V _ 0 8 4 . 7 U _ 2 5V _0 8 4. 7 U _ 2 5 V _0 8
. 1U _ 50 V _ 0 6 4 . 7U _ 25 V _ 0 8 4. 7 U _2 5 V _ 08
C
27 13
P G OO D 1 P G OO D 2 P C 16 0 . 0 01 U _5 0 V _ 04
P C1 5 8 1 U _ 1 0V _ 0 6 3 25
V D DP 1 V C CA 1
2
1
P Q 40 A
S P 8 K 10 S F D 5T B P C1 5 9 1 U _ 1 0V _ 0 6 17 11 S G ND S G ND1
Sheet 39 of 50
V D DP 2 V C CA 2
Power Plane 8 6 23 P R 1 34 1 M_ 0 4
1 .2 V V1 .2
PL 9 P R1 3 2 1 0 K _ 1% _ 0 4 4
D H1 T O N1
9 P R 1 35 7 5 0K _0 4
2A
3A I L I M1 T O N2
7
PJ 4 2 . 5 U H +/ -2 0 %
1.05VS, 1.2V, 1.5V 2 1 5

L X1 D H2
20
5
6
7
8
P R1 2 4 Power Plane
6
5
P Q4 0 B 2 21 P C 13 2 . 1 U _ 2 5V _ X 7 R _ 0 6 P Q4 2
D L1 BST2 V1 .0 5
3 mm S P 8 K 10 S F D 5T B * 10 m i _l s h ort 4 A O4 4 7 4 1 . 05 V S
P C1 5 2 P C1 1 9 + P C1 3 7 . 1 U _2 5 V _ X7 R _ 0 6 7 18 P L1 0
BST1 SC413 I L I M2
6A PJ 3
1
2
3
10 0 p_ 5 0 V _0 4 PC1 2 0 3 P R 13 3 5 . 6 K _1 % _ 04 2 . 5 U H +/ -2 0 %
. 1U _ 16 V _ 0 4 5 60 U _ 2 . 5 V _6 . 6 *6 . 6 *5 . 9 26 19 1 2
FBK1 LX 2
C
4
Ra P R1 4 5 24 16
V O UT 1 DL 2
5
6
7
8
1 5K _ 1 % _0 4 P D 11 PC1 1 8 5m m
8 12 P Q4 1 + . 1U _ 16 V _ 0 4 P C1 4 7
EN /PS V2 F BK2 4 F M 58 2 2 P C 1 22
22 10 R Q W 2 00 N 0 3 F D 5 Ra P R1 4 1 22 0 0 p_ 5 0 V _0 4
A
EN /PS V1 V O UT 2
1
2
3
5 6 0 U _ 2 . 5V _ 6 . 6 *6 . 6 *5 . 9 1 1K _ 1 % _0 4
P R1 4 2
5V
PG ND 1
PG ND 2
Rb
A G ND1
A GN D 2
1 0K _ 1 % _0 4
PU7 Vo=0.5(1+Ra/Rb)
1
28
14
15
S GN D PR1 3 0 P R 14 6 Rb P R1 3 8
=0.5(1+11K/10K) 1 0K _ 1 % _0 4
10 0 K _ 04 1 0 0K _ 0 4
=1.05V
Vo=0.5(1+Ra/Rb)
S G ND S GN D 1 S GN D 1
=0.5(1+15K/10K)
D
P Q4 5
=1.25V G
2N 70 0 2 W
P C1 4 9
S
1
. 1 U _ 1 6V _ 0 4
PQ 4 6 P J1 6
G
1m m
SU SB# 1 2 , 2 5, 31 , 3 3, 35 , 4 0 2N 70 0 2 W P R 1 54 *1 5 mi l _ sh o rt P R 15 5 * 1 5m i l_ s h or t
2
S GN D S GN D 1
5V
PR1 7 0 1 0 0K _ 0 4 2 Via 2 V ia 2 Vi a
D
P C1 7 8
3 8 ,4 0 D D _ ON # G P Q5 7
2 N 7 0 02 W . 1 U _ 16 V _ 0 4
S
5V
P C 11 1
1 .8 V
P U6 1 u_ 1 0 V _0 6
3 .3 V PR1 1 7 10 K _ 0 4
1 .5 A 5 6 V1 .5 P J2 1 .5 V
9 VIN V C NT L 3m m
3 1 1 . 5 V _ P W RG D
7 VIN 4 1. 5A 1 2
PO K V OU T
3 P C 61
V OU T
PR1 1 8 47 K _ 0 4 Z 3 7 21 8 PC1 1 3 P C1 1 5 P C 11 2
5V EN 8 2p _ 5 0V _ N P O_ 0 4
1 2 Z 3 72 2 10 u _1 0 V _ Y 5 V _ 081 0u _ 10 V _ Y 5 V _ 0 08 . 1 u_ 1 0V _X 7 R _ 0 4
D
G ND VFB PR 6 3
P C1 1 6 P C1 1 7 P C 11 4 A P L5 9 1 3 1 7 . 4 K _1 % _ 04
G P Q3 9 P R 11 6
3 8 , 40 D D _ ON #
MT N 70 0 2Z H S 30. 1u _ 10 V _ X 7R _ 040 . 1u _ 1 0V _ X 7 R _ 0140 u_ 1 0 V _Y 5 V _0 8
S
1 9. 6K _ 1 % _0 6
B - 40 1.05VS, 1.2V, 1.5V

Schematic Diagrams
1.8V, 0.9VS
VIN 5V 3 .3 V
A
P R7 0 P R 1 48 PR 7 4
PD 1 3
1 0 0 K_ 0 4
1M _ 0 4 1 0 _0 6
V1 .8 F M 0 5 4 0- N
PU 5
C
P R1 4 3 10 _ 0 6 Z 38 0 1 3 7
V D DQ S P GD 1 .8 V_ P W R G D 3 1
Ra
P C1 7 1 PR 1 5 9 P C 14 3 P C1 4 1 PR 1 2 8
Z 38 0 2 2 * 1 5m i l _ s ho rt Z3 82 3
T ON Z3 811
1 0 0 p _ 5 0V _ N P O _ 0 42 . 4 9 K _ 1 % _ 04 1 u _1 0 V _ 0 6 1u _ 1 0 V _ 0 6 24
BST
PR 7 5
Z 38 0 3
Z 38 0 4
Z 38 0 5
6
8
9
FB
R EF
PC 1 3 5
0 . 1 u _ 2 5V _ X7 R _ 0 6
P C1 7 4 PC1 7 5 PC1 8 3
VIN
4 . 7u _ 2 5 V _ X 5 R _ 0 84. 7u _ 2 5 V _ X 5 R _ 0 80. 1u _ 5 0 V _ Y 5V _0 6
Sheet 40 of 50
C OM P
1.8V, 0.9VS
5
6
7
8
Rb PR 6 9
1 0 _ 06 PC 7 1 * 1 5m i l _ s ho rt P Q5 3
P R7 6 PR 7 3 23 Z3 812 Z3 816 4 A O 44 7 4
*0 . 1 u _ 1 0 V _ X 7R _ 0 4 DH
Z 38 0 6 1 0
1
2
3
10_06 1 0 K _ 1 % _ 04 P R 1 29
VT TS
6 . 8 K _ 1 % _ 04
Z 3 80 9 Z 38 0 7 5 21 Z38 13 P L1 1 V1 .8
V C CA IL IM
2 . 5 U H _ 1 0 *1 0 *5 PJ 6
P C7 2 P C7 0 P R 72
*1 5 m i l _s h o rt
P C 66 P C 1 50
LX
22 Z38 14 8A 1 2 1 .8 V
1 u _ 1 0 V_ 0 6 0. 0 6 8 u _ 1 0V _ X7 R _ 0 4 10 0 0 p _ 5 0V _X 7 R _ 04 1 u _1 0 V _ 0 6 19 Z38 15 8m m
D L
C
VSSA 4 P D2 1 PC1 7 3 P C1 6 9 P C 1 30 PC1 2 9
5
6
7
8
VSS A +
PJ 5 Z 38 0 8 1 4 20 4 F M5 8 2 2 22 0 u _ 4 V _ V _ A 4 . 7 u _ 1 0 V _ X5 R _ 0 8 0 . 1 u _1 0 V _ X 7 R _0 4 0. 01 u _ 5 0 V _ X 7 R _ 0 4
0 .9 V S 2 1 1.5A 15
VT T V DD P 1 5V
A
VT T
1
2
3
PC 6 5 P Q 52
3m m 12 RQ W 2 0 0 N0 3 F D 5
V 1. 8 V D DP 2
P R7 1 PC 6 8 P C6 7 13 1 u _1 0 V _ 0 6 J20090413
PC 6 9 V D DP 2 18
2 0 K_ 1 % _ 0 4 4 . 7 u _ 1 0V _X 5 R _ 08 10 u _ 1 0 V _ Y 5 V _ 0 8 + P C 15 6 P C1 4 2 1 PG ND 1 16 V SSA
EN /P SV PG ND 1
*1 5 0 u _ 4V _ B _ A 17 PR1 3 1 * 1 5m i l _ s ho rt
1 0u _ 1 0 V _ Y 5 V _0 8 1 u _ 1 0 V _ 0 6 11
PG ND 2
25
7 / 24 pow e r P C1 03 f rom
VT TEN PG ND 2
2 2 0U _4 V_ D2
SC 4 8 6
c ha nge t o 4 70 U_ 2 .5 V_ D3 .
P R 1 36 4 7 K_ 0 4 1 .8 VEN
A DD PC 19 0 4. 7 U_1 0 V_ 08 .
5V
D
P C1 4 0
3 8 , 39 D D _ ON # G P Q4 3 0 . 1 u _ 1 0 V _ X 7R _ 0 4
MT N 7 00 2 Z H S 3
S
P R 1 47 4 7 K_ 0 4 VT TEN
5V
V DD 3 VIN VA VIN 1
P R 1 53 PD 6 SC S1 4 0 P
A C
D
1 0 0K _ 04 P C1 6 5 P Q1 7
PR 6 1 ND S 3 5 2 A P _ NL PD 5 SC S1 4 0 P
Z3 81 0 G P Q5 0 0 . 1 u _ 1 0 V _ X 7R _ 0 4 S D Z 38 2 2 A C
MT N 7 00 2 Z H S 3 1 0 K_ 0 4
D
27 P W R_ S W #
G
18 , 2 5 , 3 1 , 3 3 , 3 5 , 3 9 S U S B # G P Q4 9 D P Q1 9 P R5 9 1 0 0 K_ 0 4 PR 5 8 2 0K _1 % _ 0 4
MT N 7 0 02 Z H S 3 MT N 7 00 2 Z H S 3 Z 3 81 7 Z3 818
W EB _ AP# 2 7
S
G
PJ 1 7 PQ 2 1 P Q 20
D
S
1m m M TN 7 0 0 2Z H S 3 MT N 7 0 02 Z H S 3
P R6 0 1 0 0 K_ 0 4 Q1 9 Q 33
2
E C Z 3 8 20 Z 3 81 9 G G M TN 7 0 0 2Z H S 3 G G M TN 7 0 0 2Z H S 3
VI N D D _ ON H 38
S
PC 5 8 P Q1 8 P R 62 PC 6 0
0 .1 u _ 5 0 V _ Y5 V_ 0 6 DT A 1 1 4 E U A
B
Z3 821 1 00 K _0 4 0 . 1 u _ 50 V _ Y 5 V _ 0 6
P R 57 10 K _ 0 4
31 M _ BTN #
AP_ KE Y 20
1.8V, 0.9VS B - 41
Schematic Diagrams
VGA M92-S2 Power
1.8VS_VGA TO 1.1VS_VGS
1 . 8V
R7 3 0 5V
0 _0 8 P C 20 8
Reserve
P U9 1 u _1 0 V _ 06
2 .5 A 5
VIN V C NT L
6 V1 .1 P J 19 1 . 1V S _ V G A
9 3 mm
7 VIN
PO K V OU T
4 2 .5 A 1 2
5V P R1 9 6 1 0 K _ 04
R7 3 1 3 P C 20 9
8 V OU T PC2 1 0 P C 21 1 P C 2 12
D
EN 8 2 p_ 5 0 V _N P O_ 0 4
P C2 1 3 *1 0 K _0 4 1 2 1 0u _ 1 0V _ Y 5V _ 0 18 0 u_ 1 0 V _Y 5 V _0 80 . 1 u _1 0 V _ X7 R _0 4
G ND VF B
SU SB G PQ 6 9 PR1 9 7
MT N 7 0 0 2Z H S 3*0 . 1 u_ 1 6 V _Y 5 V _0 4 A P L5 9 1 3 4. 0 2 K _ 1% _ 0 4
S
P R 19 8
Sheet 41 of 50 P C2 1 4 P C 21 5
0 . 1u _ 1 0V _ X 7 R _ 0140 u_ 1 0 V _Y 5 V _0 8
1 0 . 5K _ 1 % _0 6
VGA M92-S2 Power
FOR ATI M92-S2 XT VGA

3 .3 V
5V V IN
M9 2 _G P I O1 5 P R 1 99 *1 0K _0 4
? ? 13 M 92 _ GP I O 1 5
M9 2 _G P I O2 0 P R 2 00 *1 0K _0 4
13 M 92 _ GP I O 2 0
1 .2 V 1. 1V 0.9 5V 0 .9 V 5V
P R 2 01
GPIO15 1 M _1 % _ 04
0 1 0 1
A
E N _ V G A _C OR E P R2 0 2 P R 2 03
GPIO20 PD2 4
0 0 1 1
D
10 0 K _ 04 1 0 0 K _ 04 PR2 0 4
P Q7 0 P C 21 7 1 0 K _ 1% _ 0 4 F M0 5 4 0-N P C 2 16 P C2 1 8 P C 2 29
SU SB G MT N 7 0 0 2Z H S 3
1 8, 3 5 SU SB
C
*2 2 0 0p _ 5 0V _ X 7 R _ 0 6 4 . 7 u _2 5 V _ X5 R _0 8*4 . 7 u_ 2 5 V _X 5 R _ 0 84 . 7 u _2 5 V _ X5 R _0 8
S
1
5
6
7
8
P J2 0 P Q 71
4 A O 44 7 4
4 0m i l
VCORE_VGA
2
3
1
3 .3 VS PC2 1 9
P U1 0 0 . 1u _ 5 0V _ Y 5V _ 0 6
S C 47 1 A V GA _ V C O R E
13
14
15
16
PR2 0 5 P L1 4 PJ 2 1 V CO RE _ V G A
1. 0 u H _ 1 0* 1 0* 4. 5 17A
G0
G1
D H
I LI M
10 K _ 0 4 12 1 1 2 1 2
EN LX
P C 2 20
P C2 2 1
P C 22 2
d GP U _ P W R O K 11 2 12m m
PG D BST
C
10 3
V O UT V CC + +
5
6
7
8
5
6
7
8
PC2 2 3 PD 2 5
S C 4 7 1 A _F B 9 4 P Q 72 P Q 73
FB D L
2 2 0 u_ 4 V _ V _A
2 20 u _4 V _ V _ A
0 . 1 u_ 1 0 V _ X 7R _0 4
*1 0 0p _ 50 V _ N P O_ 04 4 A O 44 5 6 4 A O 44 5 6 F M5 8 22
R TN
G ND
17
D 1
D0
A
PAD
2
3
1
2
3
1
P R 20 6
7 5 K _1 % _ 04
5
J20090324 P C 2 24
5V P R 20 7
5V 1 u _ 10 V _ 0 6
P R 2 13
Frequency adj. P C 22 5 7 5 K _1 % _ 04
P R 2 15
1 5 0K _ 1 % _0 4 4 7 0p _ 5 0V _ X 7 R _ 0 4
PWM voltage fine tuning P R 21 8 * 90 . 9 K _ 1 %_ 0 4
1 0K _0 4
D
P Q7 6
G P R 2 08
R JU 00 3 N 0 3 P C 22 6 P R 2 09 P R 21 0
D
0_04 1 7 . 4K _1 % _ 04
P Q7 4 PR2 1 4 20 p _ 50 V _ N P O _ 04 10 K _ 1 %_ 0 4
M9 2_ G P I O1 5 G P R 21 1
R J U 0 0 3N 0 3 1 0 0 K _0 4
S
P C 22 7 2 0 K _1 % _ 04
P Q 75
M9 2 _ GP I O 20 G P C 2 28 P R 2 12 1 0 00 p _ 50 V _ X 7R _ 04
R J U 00 3 N 0 3
S
0 . 01 u _ 50 V _ X 7R _ 04 49 . 9 K _ 1% _ 0 4
B - 42 VGA M92-S2 Power

Schematic Diagrams
Click Finger Board for M76
C
L
I
C
K
B
O
A
R
D
F
I
N
G
E
R
B
O
A
R
D
CJ _ F P 1
1 2
C GN D C T MU XO U T CT AVD D
C C1 3 3 4 CT T C_ V D D
0 . 1u _ 1 0V _ X 7 R _ 0 4 C T GR I D 0 / S E N S E 5 6
C T MC S C T M OS I CT DV DD1
C5 V 7 8
C T MI S O / MO D E 3 9 10 C TP D _ R E G
W7 60 XX ? C SW 1, C SW 2 C T GP I O 1 11 12 CT NR E S E T
C GN D C J _ TP 2 13 14 C T D A TA 2
M7 65 XX ? C SW 3, C SW 4 C GN D CT DA T A 0 C T E S D _R I N G
15 16 CC 5 C C6 CC 8
1 CJ_TP2 CT DA T A 1 17 18 CT M CL K
2 1 CSW1~4 C T GP I O 0 / I N T 19 20 CT XIN 1u _ 1 0V _0 6 1 u _1 0 V _ 0 6 1u _ 1 0V _ 0 6
C T P _ D A TA 3
RIGHT LIFT C T U S B _ P N 7 _R 21 22 C T X OU T
CT P _ CL K 4 KEY 2 4 KEY CT US B _ P P 7 _ R 23 24
5 1 3
6 6 C SW 1 CS W 2 *C ON 2 4 A
T J G- 5 3 3 -S - T/ R TJ G -53 3 - S -T / R
8 52 0 1 - 06 0 5 1 1 2 1 2 C GN D CG ND C GN D CG ND
3 4 C T P B U T TO N _ R 3 4 C T P B U T TO N _ L
CG ND
Sheet 42 of 50
5
6
5
6
C J _ TP 1
C T P B U T TO N _ L
1 C TP _S C R O LL _ D O W N C SW 3 CS W 4
CJ_TP1 2 C TP _S C R O LL _ U P * TJ G -53 3 -S -T / R *T J G- 5 3 3-S -T/ R
3
Click Finger Board

C T P B U T TO N _ R 1 2 1 2 C T GP I O 0/ I N T C R 17 1. 5 K _ 0 4
1
4
5
Z 3 9 03 3 4 Fo r 3 4 Fo r C T3 . 3 V
Z 3 9 04 C T US B _ P P 7 _ R C T U S B _P P 7
6 M 76 5 M7 65 C J_ F P 2 C R 18 27 . 4 _ 1% _ 0 4
7 CG ND 1
5
6
5
6
CT U S B _ P P 7
CJ_FP1
1
for M76
8 CT P _ CL K 2 C T U S B _P N 7 C C1 9
9 C T P _ D A TA 3
4
10 CG ND C GN D 4 4 7 p_ 5 0 V _N P O_ 0 4
12 11 C 5V
8 5 20 1 -0 40 5 1
6-2 0- 94 A2 0- 112 12 C C 12 CG ND
8 7 1 51 -1 2 07 G
0 . 1u _ 1 0V _ X 7 R _ 0 4 CG ND
C GN D CH 2 CH5 CH1 CH 3 C H4 CH 6
C5 5 D5 5 C 5 5D 5 5 2 9 2 9 2 9 2 9
3 8 3 8 3 8 3 8
4 1 7 4 1 7 4 1 7 4 1 7
5 6 5 6 5 6 5 6
MT H 2 3 7 D 9 1 M TH 2 37 D 91 MT H 2 3 7 D 9 1 M TH 2 37 D 91
CG ND C GN D C GN D CG ND CG ND C GN D C GN D CG ND
TC S4B Un stu ff
C T3 . 3 V
TC S4C 1U _10 V_ 06
CT 3 .3 V
TC S4 B U ns tu ff
TC S4 C 3 30 K_ 04
C C 20 C C 22 C C2 CR 2
0 . 1u _ 2 5V _ X 7 R _ 0 6 1 00 _ 0 6 10mil CU 1 C R3 C C4
1 u_ 1 0 V _0 6 0 . 1u _ 1 0V _ X 7 R _ 0 4 C T GR I D 0 / S E N S E Z 3 9 09 C T E S D_ RI NG 1
3 * 33 0 K _ 04 * 1u _ 1 0V _ 0 6
2
CR 1 C C1
C GN D R C L A MP 05 0 2 B CT PD _ REG
33 0 K _ 0 6 * 47 p _ 50 V _ N P O_ 06
C
C TT C _ V D D
T CS 4B Un st uff
C R4 CD 1
CT DA T A 2 CR 8 4 7K _ 0 4 T CS 4C 47 P_ 50V _0 6
C GN D CT T C_ V D D * S C S 5 5 1V -30
CT DA T A 1 C R 10 4 7K _ 0 4 0 _ 04
CT N RE S E T
A
CR 6 47 K _ 0 4
CT DA T A 0 CR 9 4 7K _ 0 4 C T3 . 3 V
C T U S B _P N 7 _R C R 15 27 . 4 _ 1 %_ 0 4 C T USB_ PN 7
C T GP I O 1 CR 7 3 30 K _ 0 4 CG ND CG ND
CQ 1 CC 9
C T MI S O / MO D E 3 CR 5 4 7K _ 0 4 N D S 3 52 A P _ N L C R1 6 C C1 8
0. 1 u _ 10 V _ X 7 R _ 0 4
S
C T G_ F E T G C R 14
1 0 0K _0 4 4 7 p_ 5 0 V _ N P O _0 4
CG ND *0 _ 06
C C1 7 CG ND
D
0 . 0 2 2u _ 1 6V _ X 7 R _ 0 4 C TA V D D CG ND CG ND
CT T C_ V DD CT X IN C C 10 2 2 p_ 5 0 V _N P O_ 0 4 C GN D
C U2 C TT C _V D D C R1 2 1 5 _0 6
C T M I S O/ M OD E 3 5 8
S V DD
2
C T M OS I 2 CC 3 C C 15 C C1 4 C R1 1
CT M CS Q C T3 . 3 V
1 C R1 3 C C 24 TC S4B 33 P_5 0V _0 4 CX1
CT M CL K 6 CS # 0 . 1u _ 1 0V _ X 7 R _ 0 4 1u _ 1 0V _0 6 0 . 1 u _1 0 V _ X7 R _0 4 0. 1u _ 1 0V _ X 7 R _ 0 4 * 1M _ 04 F S X - 8L _ 1 2M H z
SC K
3 3 3 _ 06 C GN D TC S4C 22 P_5 0V _0 4
E
W P#
1
C TD V D D 1 B CQ 2 C T MU X O U T C T XO U T C C 11 2 2 p_ 5 0 V _N P O_ 0 4 C GN D
B T B 1 19 8 N 3 CG ND C U3 C R 20
4 7 1 8
VSS H O LD # A# V CC
C
C C1 6 33 0 K _ 0 4
M 95 1 2 8W MN 6T P Z 39 0 5 2 C C7
C GN D C GN D 1 u _ 10 V _ 0 6 B 7 Z 3 9 06
Rx /C x 2 2 p_ 5 0 V _ N P O _0 4
CC S 2 CC S 4 CC S3 CC S 1 C R2 1 C C2 3 3 6 Z3907
C T3 . 3 V CL R # C x
S MD 7 5X 2 7 6R S MD 7 5X 2 7 6R S MD 2 28 X 2 76 R S MD 2 28 X 2 76 R C C2 1 2 . 2 u_ 6 . 3 V _Y 5 V _0 6
CG ND 1 0 0 K _0 4 1 u _1 0 V _ 0 6 CG ND
Z 3 9 08C R 1 9 C TG _ F E T
1
4 5 1 0 K_ 0 4
GN D Q
1
S N 7 4L V C 1G 1 23 D C T
CG ND CG ND
C GN D C GN D C GN D C GN D
Click Finger Board for M76 B - 43

Schematic Diagrams
Multi-Function Board
M_ 5 V M5 V _ C C D
SPEAKER CONNECTOR MULTI I/O CONN CCD M C9 MC 10
1 u _ 6. 3 V _ Y 5 V _ 0 41u _ 6 . 3V _Y 5V _0 4
M GN D M GN D
M _5 V MQ 2 M5 V _ C C D
A O 34 0 9 48 mil
ML 2 H C B 1 00 5 K F - 1 2 1T 2 0 Z 40 0 2S D
M _5 V M _3 . 3 V
M J _S P K 1 M J_ F B 1
M D D -S P K R + ML 4 F C M1 0 05 K F -1 2 1T 0 3 Z4001 20 MIL MC 5 M C6 0 . 1u _ 1 0V _ X 7 R _ 04 MR 6 M C3 MC 4
MJ_CCD1
1 1 2
G
Z 40 0 5 MC C D _D E T # Z 40 0 3 1
M D D -S P K R - Z4012 2 3 4 MC C D _E N
ML 3 F C M1 0 05 K F -1 2 1T 0 3 1u _ 6 . 3V _ Y 5V _ 0 4 1 00 K _ 0 4 0 . 1 u _1 0 V _ X7 R _ 0 4 1u _ 6. 3V _ Y 5V _ 0 4
3 M A Z _S D OU T 5 6 MD D -S P K R +
M A Z _S Y NC 7 8 MD D -S P K R -
8 52 0 5 -03 7 0 1 M R7 5
MC 7 MC 8 M A Z _S DIN1 9 10
M A Z _R ST# 11 12 MU S B _P N 1 M GN D 1 0 0K _ 0 4
13 14
Sheet 43 of 50
2 20 p _ 50 V _ N P O _ 04 22 0 p _5 0 V _ N P O _0 4 M A Z _B I TC L K MU S B _P P 1 MR 8 3 3 0 K _0 4 M GN D M J_ C C D 1
15 16 Z 40 0 4
MJ_SPK1
3 88 1 0 7-1 6 0 1 MU S B _ P N 1 1
2
D
MU S B _ P P 1
1 M Q1 MC C D _ D E T# 3
MGN D MC C D _ E N G M TN 70 0 2 Z H S 3 4
FO R E MI
Multi- Function 5
S
M GN D MGN D 8 5 2 05 -0 5 00 1
From H8 default HI MGN D
Board
MG N D
RJ-11
? ? ? ? ? ? ? ? ?
? ? 2.5mm ? ?
MODEM RJ-11
MJ_MODEM1
2 1 MJ _M OD E M1 MJ _ R J 1 1
Z 4 0 08 M L5 F C M 16 0 8 K -12 1 T 06Z 40 1 0 1
2 Z 4 0 09 TI P
M L6 F C M 16 0 8 K -12 1 T 06Z 40 1 1 2
1 RI NG
85 2 05 -0 2 70 1
85 2 05 -0 2 L C 1 0 17 1 -1 02 0 4 -Y
P I N GN D 1 ~ 2= M GN D
MDC MODULE
MJ_MDC1
12 11
2 1
MJ _M D C 1
20 MIL
1 2 Z40 05 ML 1 M _ 3. 3 V
MA Z _S D OU T MA Z _ S D O U T _ R G ND R ESERVE D Z40 06
M R5 3 3 _ 04 3 4 H C B 10 0 5 K F -1 21 T 2 0
MA Z _S Y N C MA Z _ S Y N C _ R
5 A z al i a _S D O
G ND
R ESERVE D
3 . 3 V M ai n / au x
6 Z40 07 10mil
M R4 3 3 _ 04 7 8
MA Z _S D I N 1 M R3 2 2 _ 04 MA Z _ S D I N 1 _R 9 A z al i a _S Y N C GN D 10
MA Z _R S T # MA Z _ R S T # _ R A z al i a _S D I GN D MA Z _B I TC LK _R MA Z _B I TC LK
M R2 3 3 _ 04 11 12 MR 1 0 _0 4
A z al i a _R S T # A za il a _ B C L K
88 0 18 -1 2 0G M C2 MC 1
0 . 1 u _1 0 V _ X7 R _0 4 *2 2p _ 5 0V _N P O_ 0 4
MG N D MGN D
M H5 MH 6 MH 7 M H8 M H3
2 2 2 9 2 9 2 9 M H2 MH 1
3 3 3 8 3 8 3 8 C 60 D 6 0 C 5 2D 5 2
4 1 4 1 4 1 7 4 1 7 4 1 7
5 6 5 6 5 6 5 6 5 6
M T H 2 5 6D 14 6 -5 P MT H 2 5 6D 1 46 - 5 P M TH 3 15 D 1 1 1 M T H 3 15 D 11 1 MT H 2 5 6D 1 11
M GN D M GN D M GN D MGN D M GN D MG N D MGN D MG N D MG N D MG N D
B - 44 Multi-Function Board
Schematic Diagrams
Audio Board
USB PORT
A _U S B V C C AL 5 A _U S B V C C 2
H C B 1 6 0 8K F -12 1 T 25 60 mil
A _ US B V C C
A C1 AC7
A _5 V +
50 mil A U1 50 mil 10 0 u _6 . 3 V _ B _ A 0. 1 u _ 10 V _ X 7R _0 4
4 1
VIN V OU T A J _ US B 1
AC 9 3 5 A C5 AC6 AC 8 1
VIN V OU T A G ND V+
1 0 u_ 1 0 V _Y 5 V _0 8 2 0. 1 u _1 0 V _ X 7R _0 4 0. 1u _ 10 V _ X 7 R _ 04 1 0u _ 1 0V _Y 5V _0 8 A U S B _ P N 4_ R 2
G ND DA T A _ L
R T 9 7 01 - C P L AR 1 *1 0 m li _ sh o r t A US B _ P P 4 _ R 3
DA T A _ H
Sheet 44 of 50
A GN D
A G ND 4
s h ei l d
s h ei l d
sh i e dl
sh i e dl
A U S B _P N 4 1 AL 1 2 GN D
A U S B _P P 4 4 3 C 1 0 7 B 3- 10 4 03 -Y
GN D 1
G ND2
GN D 3
G ND4
*W C M 2 01 2 F 2 S -1 61 T 03
AR 2 *1 0 m li _ sh o r t
A GN D A GN D
Audio Board
AUDIO JACK
Z41 01 5 AJ _ SPDIF 1
Z41 02 4
A C1 1 3 R
0 . 01 u _ 16 V _ X 7R _ 04
A S P DIF O Z4 1 1 0 AL 7 0 _ 04 Z41 03 2
A _5 V AJ _ F B1 Z41 04 6 L
1
1 AR 7 AC 1 2 2 S J -S 3 5 1-S 30
A MI C 1 -R 2
A MI C 1 -L 3 2 2 0_ 0 4
4
* 10 0 0 p_ 5 0 V _X 7 R _ 0 4 S PDIF O UT
A H E A D P H ON E - R 5
A H E A D P H ON E - L 6 BLACK
A MI C _ S E N S E 7
ASPK_ HP# 8 A G ND
A H P _S E N S E 9 A MI C _S E N S E 5 A J _ MI C 1
A U S B _P N 4 10 4
A U S B _P P 4 11 A MI C 1-R AL 4 F C M 10 0 5 K F -1 21 T 03 Z41 05 3 R
3 4 5
12
ASP D IF O 13 A MI C 1-L AL 6 F C M 10 0 5 K F -1 21 T 03 Z41 06 2
Z41 07 6 L
8 72 1 2 -13 G0 1
A C 10 AC 4 2 S J -S 3 5 1-S 30
A _A U D G A GN D
6 8 0p _ 50 V _ X 7R _ 04
6 8 0 p_ 5 0 V _X 7 R _ 0 4
MIC IN 2 1 6
BLACK
A HP _ S E N S E A _ A UD G
ASPK_ HP# 5 A J _ HP 1
4
A H E A D P H ON E -R Z 4 11 2 A L2 F C M1 0 0 5K F -12 1 T 03 Z 4 10 8 3 R
AR 3 10 0 _ 06
A H E A D P H ON E -L Z 4 11 3 A L3 F C M1 0 0 5K F -12 1 T 03 Z 4 10 9 2
AR 5 10 0 _ 06 6 L
1
A R9 AR 8 AC 3 AC 2 2 S J -S 3 5 1-S 30
1 K _0 4 1 K _ 04 6 8 0p _ 50 V _ X 7R _ 04
6 8 0 p_ 5 0 V _X 7 R _ 0 4
H EADPHO NE
AH 5 AH 1 AH 3 AH2 A H4
C 2 96 D 2 9 6 N C 52 D 52 C 5 2 D 5 2 2 9 2 9 AC1 4 0. 1 u _ 10 V _ X 7R _ 04 BLACK
3 8 3 8
4 1 7 4 1 7 AC1 5 0. 1 u _ 10 V _ X 7R _ 04 A _ A UD G
5 6 5 6
AC1 3 0. 1 u _ 10 V _ X 7R _ 04
MT H 2 7 6 D 1 1 1 MT H 27 6 D 1 1 1
AC1 6 0. 1 u _ 10 V _ X 7R _ 04
AG ND A G ND A G ND A GN D
A GN D A _ A UDG
Audio Board B - 45
Schematic Diagrams
Finger Sensor Board
FU1
A1 FESD _ RI NG
EXT_R IN G2
B1 FG RI D 0/ SENS E
C RI DO
C1 FGN D
RI NG
FMUXO UT
Sheet 45 of 50 MU XO UT
AVDD
D1
E1
FAV DD
Finger Sensor MC S
F1
G1
FMCS
PAD _VD D1B FTC _VD D

Board MISO
H1 FMISO / MO DE3
J1 FJ 1
D VDD FD VD D1
A2 FG PIO 1 1 2
GPI O1 FGN D FMUXOU T FAVD D
3 4 FTC_ VDD
B2 FGRI D0/S ENSE 5 6
AG ND FGN D FMCS FMO SI FD VDD 1
7 8
C2 FD ATA0 FMISO /MODE3 9 10 FPD _R EG
D ATA0 FGPIO 1 11 12 FNR ESET
D2 FD ATA1 FGN D 13 14 FDA TA2
D ATA1 FD ATA0 15 16 FESD _R IN G
E2 FG PIO 0/I NT FD ATA1 17 18 FMC LK
GPI O0 FGPIO 0/ IN T 19 20 FXI N
F2 FMCLK FU SB_PN 7 _R 21 22 FXOU T
MCLK FU SB_PP 7_ R 23 24
G2 FU SB_ PN7_R FG ND
USB_ DN SPN Z-24S1- B-017-1- R
H2 FU SB_ PP7_ R
U SB_D P
J2 FMOS I
MOS I
A3 FPD _REG
PD_REG
B3 FN RE SET FJ1
N RESET 1 23 23 1
C3 FGN D
DG ND
D3 FD ATA2 2 24 24 2
D ATA2 BOTTON VIEW TOP VIEW
E3 FESD _ RI NG
EXT_R IN G1
F3
PVDD FTC _VD D
G3 FXIN
XTAL IN
H3
PG ND FG N D
J3 FXOU T
XTALO UT
TC S4B
B - 46 Finger Sensor Board

Schematic Diagrams
Power Switch Board for M74
POWER SW & POWER LED FOR M74
POWER
S M_3. 3V S
SWITCH
POWER BUTTON 20mil
LED
S MS W 1 S MR 1
T J G-533-S -T /R
1
3
2
4 SM _B TN #
22 0_04 Sheet 46 of 50
S M_3. 3V S Power Switch
5
6
S MC 1 20mil S MJ _S W 1
20mil Z 4301
* . 1U _04
SM _BT N #
Z4 302 1
2 4
SJ_ SW1
Board for M74
A
S M GN D 3 1
SM D1 S MG N D 4
85201-04051
S MG N D
KP C -32 16QB C -C
C
SM GN D
SM H 5 S MH 2 S MH 3 SM H 1 S MH 4 SM S1
C 237B 52D 52 N C 52 D 52 C 52D 52 2 9 2 9 C 126
3 8 3 8
1
4 1 7 4 1 7
5 6 5 6
1
MTH 2 37D 87 M TH 237D 87

SM GN D S MG N D S MGN D
S MG N D S MGN D
Power Switch Board for M74 B - 47

Schematic Diagrams
External ODD Board for M74
ODD BOARD
OJ _ OD D1 OJ _OD D 2
S1 S1
S2 Z 440 1 S2
S3 Z 440 2 S3
S4 S4
S5 Z 440 3 S5
S6 Z 440 4 S6
S7 S7
Sheet 47 of 50 P1
OGN D
Z 440 5
OGN D
P1
External ODD P2
P3
P4
O_ 5 VS
Z 440 6
O_5 VS P2
P3
P4
P5 P5
Board for M74 P6 P6
20 20 01 -1 2420 0 1-1
P IN GN D 1~ 2=O GN D P IN GN D 1~ 3=O GN D
OGN D OGN D
O_ 5VS
OC 1 OC 2
0. 1 u_10 V_ X7R _00.

4 1u_ 1 0V_X7R _ 04
OGN D
OH 1 OH 2 OH 3 OH 4
C 237D 9 1 C 2 37D 9 1 C 6 7D67 C 67D 6 7
OGN D OGN D
B - 48 External ODD Board for M74

Schematic Diagrams
Finger Board for M74
F
I
N
G
E
R
B
O
A
R
D
F
O
R
M
7
4
T CS 4B U ns tu ff
F C CT 3 .3 V _ F
F C C T3 . 3 V _ F T CS 4C 1 U_ 10 V_ 06
F C C1 F CR 1 6 TCS 4B U ns tu ff
F C C 13 F CC 1 4 0 . 1 u _ 25 V _ X 7 R _ 0 6 1 00 _ 0 6 10mil F CU 1
F C T G R I D 0/ S E N S E _ F Z 4 50 5 F C T E S D _ R I N G_ F 1 TCS 4C 3 30 K_ 04
1 u _ 1 0V _ 0 6 0 . 1u _ 1 0V _X 7 R _ 0 4 3
2 F C R 15 F CC 6
F C R1 8 F C C1 2
R C L A M P 05 0 2 B *3 3 0K _ 0 4 *1 u _ 10 V _ 0 6
F C GN D 3 3 0K _0 6 *4 7 p _5 0 V _ N P O _ 06
T CS 4B Un st uf f F C TP D _ R E G _ F
T CS 4C 47 P_ 50 V_ 06
C
F CG ND
F C C T3 . 3 V _ F F CD 1
F CT T C_ V D D_ F F C R 14
F C T DAT A2 _ F F CR 1 3 4 7 K _ 04 F CQ 1
*S C S 5 5 1V -3 0
Sheet 48 of 50
A
N D S 3 52 A P _N L 0_ 0 4
S
F C T DAT A1 _ F F CR 8 4 7 K _ 04 F C T G_ F E T _ F G F CR2
Finger Board for

F C T DAT A0 _ F F CR 9 4 7 K _ 04 * 0 _0 6 F C GN D F C GN D
F CC5
D
F C T GP I O 1 _F F CR 1 0 3 3 0K _0 4
0 . 0 2 2 u_ 1 6 V _ X7 R _0 4 F C T A V DD _ F
F C T MI S O / MO D E 3 _FFC R 1 1 4 7 K _ 04
M74
F CT T C_ V D D_ F F CR 3 1 5 _0 6
F CG ND F CC 4 F CC 7
F CR1 9 F CC 2 F C CT 3 .3 V _ F
1 u_ 1 0 V _0 6 0. 1 u _ 10 V _ X 7 R _ 0 4 0 . 1 u _ 10 V _ X 7 R _ 0 4
3 3 _ 06 F CT X IN_ F
E
F C GN D
F C T D V D D 1 _F B F C Q2
B TB 1 1 9 8 N 3 2 1
F C GN D F CU 2 F C R1 F CG ND
1 8 F C T X OU T_ F
A # VC C 3 4
C
F CC1 7 3 3 0K _0 4 F C GN D
F CT T C_ V D D_ F Z4502 2 F CX 1
B Z 4 5 04
F CU 3 1 u _ 10 V _ 0 6 7 H S X 5 3 1 S _1 2 MH Z
F C TM I S O / MO D E 3 _ F 5 8 Rx /C x
F C TM OS I _F S VD D Z 4 5 01
2 F C C2 0 F CR 2 0 F C C1 8 F C CT 3 .3 V _ F 3 6 F CR 2 1 *4 7 K _ 0 4
F C TM C S _F 1 Q C L R# C x F CC 3 2 . 2 u _6 . 3 V _ Y 5 V _ 0 6
CS #
F C TM C L K _ F 6 0 . 1 u_ 1 0 V _ X7 R _0 4 F CG ND 1 00 K _ 0 4 1 u _1 0 V _ 0 6 F C C 15 F C C2 1
SCK 3 4 5 Z 4 5 03 F C R1 7 1 0 K _ 04 F C TG _ F E T _F
WP # G ND Q 18 p _ 50 V _ 0 6 1 8 p _5 0 V _ 0 6
S N 7 4 L V C 1 G 12 3 D C T
4 7 F C GN D F CG ND
VSS H OL D #
M9 5 1 28 W M N 6 T P
F CG ND F CG ND F C GN D F C GN D
T CS 4B 3 3P _5 0V _0 4
F C T TC _ V D D _ F T CS 4C 2 2P _5 0V _0 4
F C T U S B _P N 7 _ R _ F F C R 6 2 7 . 4 _1 % _ 04 F C T U S B _ P N 7 _F F C TG P I O 0/ I N T _ F F C R 4 1 . 5 K _ 04
F C T MU X OU T_ F
F CT NR E S E T _ F F CR 1 2 4 7K _0 4 F C TU S B _ P P 7 _ R _ FF C R 5 2 7 . 4_ 1 % _ 04 F C T U S B _ P P 7 _F
F CR 7 F C C9
1 0 0 K _ 04 4 7 p_ 5 0 V _N P O _0 4 F C C1 1 F CC 8
F C C1 0
22 p _ 5 0V _ N P O_ 0 4 4 7p _ 5 0V _N P O_ 0 4
0 . 1u _ 1 0V _X 7 R _ 0 4
F C GN D F CG ND
F CG ND
F CG ND F C GN D
F CH 8 F CH 7 F CH 2 F CH 1
2 9 2 9 2 9 2 9
3 8 3 8 3 8 3 8
4 1 7 4 1 7 4 1 7 4 1 7
5 6 5 6 5 6 5 6
F C J_ F P 2 MT H 23 7 D 9 1 MT H 23 7 D 9 1 MT H 23 7 D 9 1 MT H 2 37 D 91
F C C T 3 . 3V _ F 1 2 F C TA V D D _F
F CJ _ F P 1 F C GN D F C T MU X OU T_ F 3 4 F CG ND F CG ND F CG ND F CG ND F CG ND F CG ND F C GN D F CG ND
F C T GR I D 0 / S E N S E _ F 5 F C TT C _V D D _ F
6
1 F C T U S B _ P P 7 _F F C T MC S _ F 7 8 F C T M OS I _ F F C TD V D D 1 _F F CS1 F CS 3 F C S2 FC S4
FCJ_FP1
1
2 F C T U S B _P N 7 _F F C T MI S O/ M OD E 3 _F 9 F C TP D _ R E G _ F
10 F CH 4 F CH3 F C H6 F CH5 S MD 7 9X 1 9 7R S MD 79 X 1 97 R S M D 7 9 X 19 7 R S M D 7 9 X1 9 7 R
3 F C T GP I O1 _ F 11 12 F CT NR E S E T _ F F C C1 6 F CC 1 9 F C C 22 C4 4 D4 4 C 4 4D 4 4 C 23 7 D 2 3 7 C 2 37 D 23 7
4
4 13 14 F C T D A T A 2_ F
1
8 5 20 1 - 0 4 05 1 F C GN D F C T D A TA 0 _ F 15 16 F C T E S D _R I N G _ F 1 u _1 0 V _ 0 6 1 u_ 1 0 V _ 06 1u _ 1 0V _0 6
1
F CG ND F C T D A TA 1 _ F 17 18 F CT M CL K _ F
F C T GP I O0 / I N T_ F 19 20 F CT X IN_ F
F C T U S B _P N 7 _ R _ F 2 1 22 F C T X OU T _F
F C T U S B _P P 7 _R _ F 2 3 24
F C GN D F C GN D F CG ND F CG ND
* C ON 2 4 A
F C GN D F C GN D
F CG ND F CG ND
Finger Board for M74 B - 49

Schematic Diagrams
Power Switch Board for M76
POWER SW & POWER LED FOR M76

SH _3. 3V S
POWER
SWITCH
POWER BUTTON LED
2 0mil
S HS W 1 SHR1
Sheet 49 of 50 1
T J G-533-S -T /R
2 220_0 4
3 4 SH _B TN #
Power Switch 20mil
5
6
2 0mil SH C 1 S H _3. 3V S
Board for M76 Z 4901 *. 1U _04 20mil
S H J _S W 1
1
SJ_ SW1
Z4 902
A
SH _BT N # 2 4
S H GN D 3
SHD 1 S HG ND 4 1
85201-04051
KP C -3216Q B C -C S HG ND
C
S HG ND
SH H 5 SHH3 SHH1 SH H 2 S HH 4 SH S1
C 237B 52D 52 N C 52 D 52 C 52D 52 2 9 2 9 C 126
3 8 3 8
1
4 1 7 4 1 7
5 6 5 6
1
MTH 2 37D 87 M TH 237D 87
SH GN D S HG ND S H GN D
SHG ND S H GN D
B - 50 Power Switch Board for M76

Schematic Diagrams
External ODD Board for W76
ODD BOARD FOR W76
WJ _ ODD 1 WJ _ODD 2
S1 S1
S2 Z4901 S2
S3 Z4902 S3
S4 S4
S5 Z4903 S5
S6 Z4904 S6
S7 S7
Sheet 50 of 50
WGN D W GND
P1
P2
P3
Z4905
W _5VS W _5V S
P1
P2
P3
External ODD
P4
P5
P6
Z4906 P4
P5
P6
Board for W76
20 2001 -1 242 00 1-1
PI N PI N
GN D 1 ~2 =W G ND WGN D W GND GN D1 ~3=W GN D
W _5V S
WC1 W C2
0. 1u _10V_X7R _ 04
0 .1u _1 0 V_X7 R _04
W GND
W H1 WH2 WH3 WH4

C 23 7D9 1 C 2 37 D 91 C 67 D6 7 C 67D 67
W GN D WGN D
External ODD Board for W76 B - 51

Schematic Diagrams
B - 52

CLEVO W76xSUA - 6-71-M74S0-D06A PDF

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Preface

About this Manual

The following information is included:

Appendix A, Part Lists

IMPORTANT SAFETY INSTRUCTIONS

TO REDUCE THE RISK OF FIRE, USE ONLY NO. 26 AWG OR LARGER,

This Computer’s Optical Device is a Laser Class 1 Product

Instructions for Care and Operation

Use only approved brands of Unplug the power cord before

The computer has specific power requirements:

968 - PWR GND 4/4 .................................................................... B-25

VDD3, VDD5 ............................................................................... B-39

T7700 (2.4GHz) / T7800 (2.6GHz) One 8Mb SPI Flash ROM

15.6” HD 16:9 Wide Screen (1366 * 768) TFT LCD

Three USB 2.0 Ports 56K Fax Modem

Power Management Dimensions & Weight

Security (Kensington® Type) Lock Slot

Optical Drive Module Options:

External Locator - Top View with LCD Panel Open Figure 1

External Locator - Top View with LCD Panel Open 1 - 5

Figure 2 External Locator - Front & Right side Views

1 - 6 External Locator - Front & Right side Views

External Locator - Left Side & Rear View

External Locator - Left Side & Rear View 1 - 7

External Locator - Bottom View

To prevent your com-

1 - 8 External Locator - Bottom View

Mainboard Overview - Top (Key Parts) Figure 7

1. KBC ITE IT8512E

Mainboard Overview - Top (Key Parts) 1 - 9

Figure 8 Mainboard Overview - Bottom (Key Parts)

1 - 10 Mainboard Overview - Bottom (Key Parts)

Mainboard Overview - Top (Connectors) Figure 9

Mainboard Overview - Top (Connectors) 1 - 11

Figure 10 Mainboard Overview - Bottom (Connectors)

6. CPU Fan Cable

1 - 12 Mainboard Overview - Bottom (Connectors)

An example of these types of boxes are shown in the sidebar. 

To remove the Battery: To remove the Keyboard:

To remove the Modem:

Removing the Battery

1. Turn the computer off, and turn it over.

Removing the Battery 2 - 5

Removing the Hard Disk Drive

a. Locate the HDD bay Hard Disk Upgrade Process

 New HDD’s are blank. Before you begin make sure:

2 - 6 Removing the Hard Disk Drive

3. Remove the hard disk bay cover 63 .

Removing the Hard Disk Drive 2 - 7

Figure 4 Removing the Optical (CD/DVD) Device

2 - 8 Removing the Optical (CD/DVD) Device

Removing the System Memory (RAM) Figure 5

Memory Upgrade Process

Removing the System Memory (RAM) 2 - 9

2 - 10 Removing the System Memory (RAM)

Removing and Installing the Processor

Removing and Installing the Processor 2 - 11

The heat sink, and CPU area in

2 - 12 Removing and Installing the Processor

Processor Installation Procedure Figure 9

Removing and Installing the Processor 2 - 13

Figure 10 Removing the Wireless LAN Module

Note: Make sure you 3