Assignment 1

Due date for this assignment: 2019-03-13, 23:59 IST.

1. In order to remove the body effect, the substrate of an n-channel enhancement mode
MOSFET should be
a) Connected to the most positive bias
b) Connected to the most negative bias
c) Grounded
d) Floating
2. Assuming that the bulk NMOS device has equal source and drain doping then the
effective channel length (Leff) is related to drawn length (Ldrawn) and diffusion length
(LD) as
a) Leff = Ldrawn – 2 LD
b) Leff = Ldrawn – LD
c) Leff = 2Ldrawn – LD
d) Leff = LD – Ldrawn

3. A bulk n-channel enhancement mode MOSFET is biased in the saturation region of

operation, such that VDS> VGS – Vth. Vth is the threshold voltage. Taking into
consideration Channel Length Modulation, the MOSFET in saturation state behaves as
a
a) Constant Voltage Source
b) Variable Voltage Source
c) Current Source with infinite output impedance
d) Current Source with finite output impedance

4. Drain Induced Barrier Lowering (DIBL) for a bulk MOSFET

a) Reduces the device operating frequency
b) Increases the device operating frequency
c) Has no influence on the device operating frequency
d) Increases the carrier transit time

5. Under Gradual Channel Approximation (GCA), the depletion region in the bulk of the
long channel MOSFET on application of a drain bias
a) Reduces as we move towards the drain end
b) Increases as we move towards the drain end
c) Remains constant
d) Has no relationship

6. The unit of mobility is

a) m^2/V-s
b) m/V^2-s
c) m/V-s^2
d) m/V-s
7. Assuming λ as the Channel Length Parameter for a short channel MOSFET, the
formulation used for drain current in SPICE Level-2 for the MOSFET is given as
a) ID= IDsat[1 /(1-λ VDS)]
b) ID = IDsat[1 / (1-VDS) ]
c) ID= IDsat[λ /(1-λ VDS)]
d) ID= IDsat[λ/(λ -λ VDS)]

8. For a bulk MOSFET with aspect ratio of W/L and a depletion width of XD the analytical
expression for gate-to-drain overlap capacitance (Cgd) is
a) Cgd = 2CoxWXD
b) Cgd = CoxXDW/2
c) Cgd = 2CoxXDWL
d) Cgd = CoxXDWL

9. A static CMOS Inverter is powered by a supply voltage of VDD. Assuming the pull-up
and pull-down networks are equal and symmetric, which of the following statement are
true
a) The switching threshold is VDD/2
b) The switching threshold is 2VDD
c) The switching threshold is VDD
d) The switching threshold is VDD/4

10. For a static CMOS, the output is high, then the state of the NMOS and PMOS are as
follows
a) NMOS on and PMOS non-linear
b) NMOS off and PMOS linear
c) NMOS off and PMOS non-linear
d) NMOS on and PMOS linear