MOS Transistor Principles and Digital Integrated Circuits

Digital Integrated Circuits
- A Design Perspective
E. KONGUVEL
Teaching Fellow
Department of Electronics Engineering, Anna University – MIT.
Common for EC7651, EC8651, VE7103 & NE7081

CHAPTER – I
MOS TRANSISTOR
PRINCIPLES
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The MOS(FET) Transistor
• Workhorse of contemporary digital design.
• Performs very well as switch & introduces few
parasitic effects.
• Advantages – Integration density:
– Possibility of producing large & complex circuits in an
economical way.
First Glance:
• Four terminal device:
– Voltage applied at Gate determines amount of current flow
between Source and Drain.
– Body terminal is secondary because it only serves to
modulate the device characteristics and parameters.
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Switch Operation:
• When applied gate voltage is larger than given voltage
(Threshold Voltage VT), a conducting channel is
formed between Drain & Source.
• In presence of Voltage difference between Drain &
Source, electrical current flows.
• Conductivity of channel is controlled by gate voltage.
• i.e., Larger the voltage difference between Gate &
Source, Smaller the resistance of channel & Larger the
current.
• When gate voltage is lower than VT, the Switch is
considered to be open.
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Types of MOSFET:
NMOS PMOS
n+ Drain & Source regions p+ Drain & Source regions
p substrate n substrate
n channel p channel
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The MOSFET under static conditions
Threshold Voltage:
• Assume VGS = 0 / Drain, Source & Bulk are GNDed.
– Drain & Source are connected by back-to-back PN junctions.
– Source (N) – Substrate (P) – Drain (N).
– The device at 0 V bias.
– Considered to be OFF.
– High resistance between Source & Drain.
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Threshold Voltage:
• Positive voltage is applied to Gate:
– Gate & Substrate forms the plate of the capacitor with gate
oxide as dielectric.
– Positive charges accumulates on Gate & Negative charges on
substrate.
– Hence depletion region is formed below the gate.
– Width of depletion layer:
– Space charge per unit area:

 Ф – Voltage across depletion layer
 NA – Substrate Doping
 Ɛsi – Electrical permittivity
(1.053 x 10-10 F/m)
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Threshold Voltage:
• Gate Voltage still increases:
– At a critical point semi-conductor surfaces inverts to n-type
material.
– Strong inversion occurs @ voltage equals twice of Fermi
potential. (-0.3 V for typical p-substrates)
– Further increase in voltage causes additional electrons in the

thin inversion layer directly under oxide. (Drawn from
heavily doped Source and Drain)
– Width remains same, and charge will be
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Threshold Voltage:
• But for n-channel devices:
– Substrate Bias Voltage (VSB) is applied.
– This causes surface potential required for strong inversion to
increase. So,
• VGS when strong inversion occurs is called Threshold

voltage VT.
 VT0 – VT for VSB = 0.

 γ – Body effect co-efficient
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Resistive Operation:
• Now VGS > VT & Small VDS is applied:
– Voltage difference causes ID to flow.
– ID as a function of VGS & VDS.
• Consider: Voltage at point x on channel – V(x).

• Voltage at x (assume voltage exceeds VT):
(Gate to Source Volt. – Voltage at x – Threshold Voltage)
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• So, Charge at point x: Prob.:
Qi(x) = – Cox[VGS – V(x) – VT] Calculate Cox for an
oxide thickness of 5nm.
Cox = εox / tox.
where εox = 3.97 x εo = 3.5 x 10-11 F/m.
• Drift Velocity, Mobility & Electric field:
– Current is product of Drift velocity & charge.
– W is width of channel in perpendicular direction to
current flow.
– So ID = – υn(x)Qi(x)W.
– Electron Velocity is related to electric field by
mobility μn:
υn = – μn(dV/dx) (Velocity Equation)
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• Combining all above relations,
IDdx = μnCoxW(VGS – V(x) – VT)dV.
– Integrating ID over the length of the channel,
where, kn‟ = process transconductance parameter
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• Gain factor kn:
Gain factor kn = Product of kn‟ & W/L ratio.
• Relationship between VDS & ID:
– For smaller VDS, quadratic factor can be ignored
– So, linear dependence between VDS & ID.
– Region under the curve is resistive or linear region
– Property: A continuous conductive channel between
source & drain.
Effective Channel Width and Length:
W = Wd – ΔW
L = Ld – ΔL
where d subscript denotes drawn size
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The Saturation Region:
VDS further increased (VDS > VGS - VT):
– Channel voltage larger than threshold voltage ceases to hold
at VGS – V(x) < VT.
– Induced charge becomes zero and channel disappears or
pinched-off.
– This happens at VGS – VDS ≤ VT.
– Voltage at induced channel remains at VGS – VT & ID remains
constant.
– Replacing VDS by VGS – VT
in ID (for resistive operation),
Observance: Squared dependency of ID w.r.t VGS.

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Channel-Length Modulation:
• ID relation in saturation region suggests it acts as a
current source.
• But, Effective channel length is modulated by applied
VDS: increasing VDS causes depletion region at drain
junction to grow, reducing the length of effective
channel.
– So,
where, ID‟ is current in saturation region
λ is channel length modulation,
is complex,
is inaccurate &
inverse of channel length.
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Velocity Saturation:
• Behaviors of short-channel devices varies from
resistive and saturation modes.
• From Velocity equation, Velocity is proportional to
electric field, independent of value of that field.
• At high field strengths, carriers fail to follow linear
model.
• When electric field reaches
a critical value ξc, velocity
saturates due to scattering
effects.
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• For p-type silicon, critical field is 1.5 V/μm and saturation
velocity υsat is 105m/s.
• Inference:
– Only few volts requires to saturate an NMOS of 1μm.
– Can be easily achieved in short channel devices.
– Holes in n-type silicon saturates at same velocity but requires
higher electric field.
– Velocity saturation effects are less pronounced in PMOS
devices.
• Impact:
– Velocity as a function of electrical field can be approximated
as,
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• The drain current ID, after considering revised
velocities,
• Inference:
– For Long channel devices, κ approaches 1.
• Simplifies to traditional current
– For short channel devices, κ will be less than 1.
• Current is less than expected.
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Observations:
• For short channel device, κ is less than 1. Device enters
saturation before VDS reaches VGS – VT.
Hence, short-channel devices experiences an
extended saturation region and tend to operate more
often in saturation conditions.
• IDSAT has a linear dependence
w.r.t VGS for short-channel
devices whereas it has
squared dependence in
long-channel devices.
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Drain current versus Voltage charts:
ID vs. VDS (Parameter - VGS):
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Drain current versus Voltage charts:
ID vs. VGS (Fixed VDS):
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PMOS Characteristics (?):
i. Similar
characteristics
& relations.
ii. All voltages &
currents are
reversed.
iii.Third-
quadrant
curves.
iv.Velocity
saturation
effects are poor.
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Problem(s):
1. Determine the mode of operation of NMOS transistor
and drain current ID for each of the biasing
configurations given below.
Transistor data: kn‟ = 115 µA/V2, VT = 0.43 V and
λ = 0.06 V-1. Assume W/L = 1.
i. VGS = VDS = 2.5 V.
ii. VGS = 3.3 V, VDS = 2.2 V.
iii. VGS = 0.6 V, VDS = 0.1 V.
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Problem(s):
1. Determine the mode of operation of PMOS transistor
and drain current ID for each of the biasing
configurations given below.
Transistor data: kn‟ = 30 µA/V2, VT = -0.4 V and
λ = -0.1 V-1. Assume W/L = 1.
i. VGS = -0.5 V, VDS = -1.25 V.
ii. VGS = -2.5 V, VDS = -1.8 V.
iii. VGS = -2.5 V, VDS = -0.7 V.
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Sub-threshold Conduction:
• On log-scale of ID – VGS curves, it is apparent that MOS
transistor is already partially conducting below threshold
voltage: - Sub-threshold or weak-inversion.
• On strong inversion, ample carriers are available for conduction,
so for very low VGS voltages, smaller currents are available.
• For VGS < VT, ID decays in an
exponential fashion, similar to a
bipolar transistor.
• In absence of conducting
channel, n+ (source) – p (bulk) –
n+ (drain) forms a parasitic
bipolar transistor.
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• So, ID can be approximated as,
where, IS & n are empirical parameters, typically n≥1 (1.5)

• Impact: Presence of sub-threshold current is undesirable in most
digital applications because it deviates from ideal switch like
behavior.
• Quality measure of a device: Rate of decline of current w.r.t.
VGS below VT: - Slope factor S.
mV/decade
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• For n = 1, S = 60mV/decade @ room temperature & for n = 1.5,
S = 90mV/decade.
• By reducing temperature T, current roll-off factor can further be
decreased.
• Value of n is determined by intrinsic topology & structure. So to
decrease n, requires a different process technology.
• Generally, ID must be as close as possible to zero at VGS = 0.
• In dynamic circuits (in presence of sub-threshold current), it can
be achieved by a firm lower bound on value of threshold voltage
of devices.
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The MOSFET: Manual Analysis
Unified Model (?):
• Complex deep-submicron
– Non-linear
– Second order effects.
• Simple and Tangible analytical model – Unified Model.
– Simplifies to the available current equations.
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The MOSFET: Manual Analysis
Unified Model (?):
• Five parameters to be employed: - VTO, γ, VDSAT, k‟& λ.
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The MOSFET: Dynamic Behavior
• Dynamic response:
– A function of time it takes to (dis)charge the parasitic
capacitances that are intrinsic to the device and the extra
capacitances introduced by the interconnecting lines and
load.
• Intrinsic capacitances arises from:

– Basic MOS structure
– Channel charge
– Depletion regions of reverse-biased pn-junctions
• All capacitors are non-linear & vary with the applied

voltage.
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MOS Structure Capacitances:
• The gate of MOS transistor is isolated from conducting channel
by gate oxide which has a capacitance equal to Cox = εox / tox.
• For ID to be larger, Cox must be larger  tox must be smaller.
• This Gate capacitance Cg can be decomposed into two elements:
– Channel charge
– Topological structure
• Lateral diffusion of source & drain.
• Effective channel length L becomes
shorter than Ld. (ΔL = 2xd)
• Overlap capacitance b/w gate &
source (drain).
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Channel Capacitances:
• Gate-to-Channel capacitances (CGC):
– Gate-to-Source (CGCS) Depends on:
– Gate-to-Drain (CGCD) i. Operating regions
– Gate-to-Body (CGCB) ii. Terminal Voltages
• Operating Conditions & Voltages:

a. Cut-Off
• CGC between Gate & Body
b. Resistive
• CGCB = 0
• Symmetric C exists b/w Source & Drain
c. Saturation
• CGCD = 0; CGCB = 0.
• C exists b/w Gate & Source
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Gate-Channel Capacitance vs. VGS (VDS = 0):
i. When VGS = 0,
Capacitance exists b/w
Gate & Body (WLCox).
ii. When VGS increases,
depletion region forms,
CGC decreases.
iii.At VGS = VT, channel
forms, CGCB drops to 0.
iv. At VDS = 0, capacitance
divides b/w Source &
Drain.
CGCS = CGCD = WLCox/2
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Gate-Channel Capacitance vs. VDS/(VGS-VT):
(Degree of Saturation)
When saturation
increases,
i. CGCD drops to 0.
ii. CGCS increases to
2WLCox/3 from
WLCox/2.
iii.So, CGC also
decreases.
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Avg. Distribution of Channel Capacitance:
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Junction Capacitances:
• Final Capacitive Component:
– By Reverse biased Source-Body & Drain-Body PN junctions.
• Two Components:
– Bottom Plate Junction
• Source Region (ND) &
Substrate (NA)
• Cbottom = CjWLS.
– Side-wall Junction
• Source Region (ND) &
p+ Channel-stop implant
• Csw = C‟jswxj(W + 2 x LS)
• Total Capacitance:
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Capacitive Device Model:
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Source-Drain Resistance:
• RC – Contact Resistance.
• R□ – Sheet Resistance
(Constant = 20 ~ 100 Ω /□).
• Lowering R, Gain ID.
• Silicidation: Covering the drain and
source regions with low-resistivity
materials (Titanium/Tungsten).
(R□ = 1 ~ 4 Ω /□).
• „W‟ should be larger.
• Careful Layout is necessary.
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Problem:
Consider an NMOS transistor with the following parameters:
tox = 6nm, L = 0.24 µm, W = 0.36 µm, LD = LS = 0.625 µm,
CO = 3 x 10-10 F/m, Cjo = 2 x 10-3 F/m2, Cjsw0 = 2.75 x 10-10 F/m.
Determine the zero-bias value of all relevant capacitances.
(Assume: Ɛox = 3.97 x Ɛo = 3.97 x 8.854 x 10-12 F/m)
Sol.: Cox = 5.7 fF/pm2, CG = 0.7fF & Cdiff = 0.89fF.
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The MOSFET: SECONDARY EFFECTS
Deep Sub-Micron Realm:
1. Threshold Variations
2. Hot-Carrier Effects
3. CMOS Latchup
1. Threshold Variations:
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2. Hot Carrier Effects:
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3. CMOS Latchup:
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The MOSFET: PROCESS VARIATIONS
Important Factors:
1. Variations in the process parameters (Threshold Voltage):
– Impurity Concentration Densities
– Oxide Thickness
– Diffusion depths
2. Variations in the Dimensions – (W/L ratio):
– Limited resolution in lithographic process
Uncorrelated Deviations:
• Circuit performance – transistor current.
• Threshold Voltage – Oxide thickness, substrate, poly silicon,
impurity level & surface charge.
• Process Transconductance – Mobility – Oxide thickness.
• W & L ratio by field oxide and poly-silicon definition –
Photolithographic process.
“Economic Dilemma for the Designer” – Ends in
Optimization with Simulations
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The MOSFET: PROCESS VARIATIONS
• Fast and Slow Device models
• Best (or Worst Cases) models
Distribution plots of speed of adder circuit:
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The MOSFET: TECHNOLOGY SCALING
• Spectacular increase in integration density and computational
complexity.
• Advances in device manufacturing technology:
– Reduction in feature size.
• Reduction in feature size

Influence on
– Characteristics
– Properties
– Design Metrics
• Operating Frequency
• Power dissipation
• Need of Scaling analysis

– Dimensions (S)
– Voltages (U)
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Full Scaling (Constant Electrical Field Scaling)
• Voltages and Dimensions are scaled by same factor S.
• Goal: Keeping Electrical Field Patterns as Same.
• Advantages:
– Greater Device Density (Area)
– Higher Performance (Intrinsic Delay )
– Reduced Power Consumption (P)
• Ron : Constant since both Voltage and Currents are scaling down.
• Improved performance is solely due to Capacitance.
• Effects:
– Speed increases linearly
– Power scales down quadratically
::: Unsustainable Practically :::
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Fixed-Voltage Scaling:
• Full Scaling is not feasible:
– To keep new devices
compatible with existing
components, voltages cannot
be scaled arbitrarily.
– Multiply supply voltages add
costs to the system
• Designers adhere to well-
defined standards for supply
voltages and signal levels.
• Higher Voltage level causes
Power Dissipation.
• Other effects:
– Hot-carrier effect
– Oxide breakdown ::: Unsustainable Practically :::
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General Scaling:
• Supply voltages are not scaling as fast as the technology (Slide 47)
• Why not Full-Scaling?
(Because no convincing effect for keeping higher voltages)
– Voltages (Built-in Junc. Potential, Silicon Band-Gap) can‟t be
scaled.
– Scaling of VT is limited too. (Difficult to turn ON/OFF device)
• So independent voltage & dimensions scaling may be considered
• Dimensions by S & Voltages by U (For U = 1, this becomes
fixed-voltage scaling model).
• General-scaling model offers a performance scenario identical to
the full- and the fixed scaling, while its power dissipation lies
between the two models (for S > U > 1).
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Scaling Scenarios:
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Verifying the Model:
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Verifying the Model:
FinFET Dual Gate
Vertical Dual Gate
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The MOSFET: Summary
• MOSFET – Voltage Controlled Device
– Cut-off, Linear & Saturation
– Switch: On & Off Concepts
• Substantial Deviations:
– Velocity Saturation – Quadratic to Linear dependence of current to
voltage.
– Sub-Threshold Conduction – Device to conduct even in low voltages
(<VT)
• Dynamic Operation of the device

– Device capacitors
– Gate Capacitance & Junction Capacitance
• Models represent only average behavior & can vary over a

single wafer or die.
• MOS transistor will dominate digital integrated circuits.
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CMOS INVERTER
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Design Metrics
• Cost
– Complexity
– Area
• Integrity & robustness
– Steady-state (Static) response
• Performance
– Transient (Dynamic) response
• Energy efficiency
– Energy/Power consumption
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The Static CMOS inverter
NMOS Trans. modeled as a switch
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The Static CMOS inverter
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CMOS inverter - properties
• High noise margins
– Voltage swing is equal to supply voltage
• Ratio-less
– Logic levels doesn‟t depend on device sizes
• Low output impedance
– Direct path b/w Output and Supply/GND
• High input resistance
• Gate of MOS transistor is an insulator
• No direct path b/w Supply & GND
• Doesn‟t consume static power
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Voltage Transfer Characteristics of PMOS
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Load curves for NMOS & PMOS
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VTC of CMOS inverter
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Transient Response
• CL
– (Drain Capa. + I/O wire
Capa.)
• Td α RpCL
• Faster Gate:
Low Rp/Small CL
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CMOS inverter: Static Behavior
• Switching Threshold
• Noise Margins
• Device Variations
• Scaling the Supply Voltage
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Switching threshold
• Switching threshold, Vm : Vin = Vout.
• At the intersection, VGS = VDS.
• By equating the current through transistors in velocity
saturation, (neglecting channel length modulation),
• For larger values of VDD,
• VM depends on ratio „r‟ which compares the relative drive

strength of the two transistors.
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Switching threshold
• Considering the location of VM at the middle of available
voltage swing, or at VDD/2,
r ≈ 1 or drive strength of PMOS,
• So, for rising VM towards VDD requires wider PMOS.

• Similarly, for lowering VM towards GND requires wider
NMOS.
• For all above analysis, both devices should be in velocity
saturation satisfying,
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Switching threshold
• VM for an inverter with long-channel devices and low
supply voltage,
– Non-occurrence of velocity saturation.
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Switching threshold (Problem)
• On deriving the ratio of sizes of PMOS and NMOS, for a
0.25µm process, assuming the supply voltage of 2.5V for
the following parameters.
VTn = 0.43, VTp = -0.4, kn‟ = 115 x 10-6A/V2,
kp‟ = -30x10-6A/V2, VDSATn = 0.63V and VDSATp = -1V.
Ans: 3.5
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Switching Threshold vs. PMOS/NMOS ratio
Inference 1:
VM is relatively
insensitive to device
size ratio.
3 – 1.22V
2.5 – 1.18V
2 – 1.13V
Inference 2:
Shifting the transient
region of VTC.
(Asymmetrical VTC)
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Demonstration for Inference 2:
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Noise Margin
• g = dVout/dVin.
• Piece wise linear approx.
• Width of the transition region VIL
to VIH.
• For infinite gain, NMH = VOH –

VM and NML = VM – VOL.
(Spanning Complete V swing)
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Noise Margin
• For determining mid-point of gain:
• Considering current equations (including velocity saturation &
channel length effects),
• Ignoring some second order terms and sub. Vin = VM,

Major Parameter:
Channel Length Modulation &
Technology
Minor Parameter: Choice of
voltages
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Device variations
• Temp. effect: Parameters vary from nominal
optimized values.
• Re-simulate worst- & best- case scenarios.
– Good NMOS + Worst PMOS
– Worst NMOS + Good PMOS
• Shifting threshold
• Operation remains same over
wide range of conditions.
• Good Device:
• Smaller tox: -3nm
• Smaller length: -25nm
• Higher width: +30nm
• Smaller thresdhold: -60mV.
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Scaling supply voltage
• Technology Scaling: Forces supply voltage to reduce at rates
similar to device dimensions but rather VT is constant.
• From equation, Gain increases
as supply voltage reduces.
• For fixed „r‟, VM is proportional
to VDD.
• Plotting VTC with different supply voltages:
For 0.5 to 2.5V:
– Width of transition region is 10% wider for 0.5V.
– Width of transition region is 17% wider for 2.5V.
For 50mV to 200mV:
– Transistor VT is same.
– Still VTC is obtained, even though supply voltage is not enough
to turn the device ON.
– Subthreshold conduction provides this VTC. (On & Off)
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Scaling supply voltage
• Device scaling reduces supply voltage
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CMOS inverter: Dynamic Behavior
• Computing the capacitances.

• Propagation delay
–First order analysis
–Design perspective
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Computing the Capacitances
Parasitic capacitances, influencing the transient
behavior of the cascaded inverter pair
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Computing the Capacitances
• Load Capacitance CL breaks down into
following components:
– Gate Drain capacitance Cgd12
– Diffusion capacitances
• Cdb1
• Cdb2
– Wiring capacitance Cw
– Gate capacitance of fanout
• Cg3
• Cg4
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Gate Drain capacitance Cgd12
• M1 & M2 are either in cut-off or saturation mode in first half
cycle: Contribution is only by Overlap cap. Of M1 and M2.
• Channel cap. has no role (as it is between G & Bulk or G & S).
• Miller effect:
– During transitions, terminals moving in opp. directions
– Therefore, Capacitor voltage = 2 * Output swing
– Cgd = 2 CGDOW.
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Diffusion capacitances Cdb1 & Cdb2
• Due to reverse biased pn junction (Drain & Bulk)
– Non-linear capacitor (depends on applied voltage)
• To linearize it, a multiplication factor Keq is used,
– Cj0 = Junc. Capacitance under zero-bias.
ϕo = Built-in junction potential & m = grading coefficient.

• To linearize it, a multiplication factor Keq is used,
EC7651/EC8651/VE7103/NE7081 - EK. 78
Diffusion capacitances Cdb1 & Cdb2 : Problem
Keq for 2.5-V CMOS inverter:
Analysis of NMOS transistor: Cdb1:

• Linearizing the junction capacitance over (– based on tpd / 50% point)
– {2.5V, 1.25V} for high to low transition
– {0V, 1.25V} for low to high transition
• During high to low transition, Vout = 2.5V, Since bulk of NMOS is
connected to GND, Voltage over drain junction is Vhigh = -2.5 V. At 50%
point, Vout = 1.25V or Vlow = -1.25V.
 Bottom plate: Keq = 0.57
 Sidewall: Keq = 0.61
• During low to high transition, Vlow = 0V and Vhigh = -1.25V.
EC7651/EC8651/VE7103/NE7081 - EK. 79
Diffusion capacitances Cdb1 & Cdb2 : Problem
Keq for 2.5-V CMOS inverter:
Analysis of PMOS transistor: Cdb2:

• PMOS transistor displays a reverse behavior:
• During high to low transition, the bulk of PMOS is connected to 2.5V,
Vhigh = -1.25 V & Vlow = 0V.
• During low to high transition, Vlow = -1.25V and Vhigh = -2.5V.
EC7651/EC8651/VE7103/NE7081 - EK. 80
Wiring capacitance Cw
• Wiring capacitance depends on
– Length
– Width
• Function of
– Distance of fanout from the driving gate
– Number of fanout gates
• Growing in importance with scaling of the technology
EC7651/EC8651/VE7103/NE7081 - EK. 81
Gate capacitance of fanout Cg3 & Cg3
• Fanout capacitances equal to total gate capacitances
• First approximation:
– Assumption: All the components of Gate capacitances are
connected between Vout and GND (or VDD).
– Ignores miller effect on gate-drain capacitances.
– This has a relatively minor effect on the accuracy, since we
can safely assume that the connecting gate does not switch
before the 50% point is reached, and Vout2, therefore,
remains constant in the interval of interest
EC7651/EC8651/VE7103/NE7081 - EK. 82
Gate capacitance of fanout Cg3 & Cg3
• Second approximation
– Channel capacitance is constant not exactly as previous
discussions.
– Channel capacitance varies from 2/3 WLCox (Saturation) to
WLCox (Cut-off / Linear).
– Drop in transition.
– One transistor is Linear
– And one in Saturation
– 10% of error in ignoring above discussions.
EC7651/EC8651/VE7103/NE7081 - EK. 83
An Example with Layout of two chained minimum size inverters:
EC7651/EC8651/VE7103/NE7081 - EK. 84
Components of CL:
Intrinsic Capacitance: Diffusion and Overlap Capacitances.

Extrinsic Load Capacitances: Wire and connecting gate.
EC7651/EC8651/VE7103/NE7081 - EK. 85
Propagation Delay: First Order Analysis
• By integrating capacitor (dis)charge current,
• Since CL(v) & i(v) are non-linear functions of voltage, an

exact computation is intractable.
• Using switch model, load resistance is,
• Propagation delay of linear RC network, depends on time

constant,
• For low-to-high transition,
EC7651/EC8651/VE7103/NE7081 - EK. 86
• This analysis assumes CL is identical for low-to-high as well as
high-to-low transitions.
• Identical Propagation delay for Low to High & High to Low

transitions:
– On resistance of NMOS & PMOS must be equal
– Symmetrical VTC
EC7651/EC8651/VE7103/NE7081 - EK. 87
Propagation Delay: Problem
Determine the delay for the 2.5V CMOS inverter with the
following specifications: CL(high-to-low) = 6.1fF, CL(low-to-
high) = 6.0fF, Reqn = 13kΩ, Reqp = 31kΩ, (W/L)n = 1.5 and
(W/L)p = 4.5.
• Spice simulation shows

– 39.9 ps & 31.7 ps.
• Overshoots:
– Because of the G-D Capacitances, couples the steep voltage step at the
input node directly to the output before the transistors can even start.
– Negative impact on the performance of the inverter.
EC7651/EC8651/VE7103/NE7081 - EK. 88
• For optimizing gate delay, considering Req values (ignoring λ),
• If Vdd >> VTn + VDSATn/2 (in most designs), – delay becomes

virtually independent of supply voltage.
Plot: Delay vs VDD

• The plot is only valid when
the devices are velocity
saturated.
• The deviation at low supply
voltages.
• Sharp increase in tp,
VDD≈ 2VT. EC7651/EC8651/VE7103/NE7081 - EK. 89
Propagation Delay: Design Techniques
• Reduce CL:
– Internal diffusion capacitance + interconnect capacitance +
fanout capacitance
– Careful layout & small drain diffusion area
• Increase W/L ratio:
– Most powerful & effective performance optimization
– Increasing W/L also raises diffusion capacitance, so CL, again
delay will be increased with the Area : “Self-loading”
– Wide transistors have larger gate capacitance, which increases
fan-out factor of driving gate, that affects the speed.
• Increase VDD:
– Reduces delay
– Trade off for energy dissipation with performance
– Reliability concerns arises in deep submicron process.
• Oxide breakdown & hot-electron effects
EC7651/EC8651/VE7103/NE7081 - EK. 90
Propagation Delay: Design Perspective
 NMOS to PMOS ratio
 Sizing inverters for performance
 Sizing a chain of inverters
 Choosing the right number of stages in an inverter chain
 Rise-Fall time of the input signal
 Delay in the presence of (long) interconnect wires.
EC7651/EC8651/VE7103/NE7081 - EK. 91
NMOS to PMOS ratio:
• Widened PMOS to match the resistance values, with a ratio of
3 ~ 3.5 to get symmetric VTC & equal transition delays.
• But minimizing overall propagation delay is not possible
considering symmetry & noise margins.
– Widening PMOS improves tpLH but degrades tpHL because
of larger parasitic capacitances.
• For this contradictory effects, there must be some optimization
in transistor ratio exists.
• Considering two cascaded CMOS inverters, CL of first is,
Cdp1 & Cdn1 are drain diffusion capacitances of first gate,

Cgp2 & Cgn2 are Gate capacitances of second gate and CW is
wiring capacitance.
EC7651/EC8651/VE7103/NE7081 - EK. 92
NMOS to PMOS ratio:
• When PMOS is β times larger than NMOS,
β = (W/L)p/(W/L)n
• All capacitances can be scaled like,

{Cdp1 = Cdn1; Cgp2 = Cgn2}
• Therefore propagation delay can be,
where r = Reqp/Reqn, resistance ratio.

EC7651/EC8651/VE7103/NE7081 - EK. 93
NMOS to PMOS ratio:
• β can be found using partial diff.,
If wiring capacitance CW is
negligible, (Cdn1+Cdn2)>>Cw,
β = √r
• Inference:
Smaller devices yield a
faster design at the expense of
For Reqp = 31kΩ & Reqn = 13k Ω,
symmetry & noise margin β = 2.4
EC7651/EC8651/VE7103/NE7081 - EK. 94
Sizing Inverters for performance
• Symmetrical inverter
– Rise and fall delays are identical in PMOS & NMOS
• Load capacitance: CL = Cint + Cext
• Propagation delay,
• represents intrinsic/unloadad delay

• S being sizing factor, Cint consists of miller and diffusion
capacitances, which depends on width of the transistors.
Cint=SCiref and Req = Rref/S
EC7651/EC8651/VE7103/NE7081 - EK. 95
Sizing Inverters for performance
Inferences
• Intrinsic delay is independent of the sizing of the gate
– Is determined only by technology & inverter layout
• Maximizing S  Maximum Gain
– Eliminating impact of any external load & reducing delay
to intrinsic.
EC7651/EC8651/VE7103/NE7081 - EK. 96
Sizing a Chain of Inverters
• Sizing of a single gate affects the performance (delay) of
preceding gates; Sizing is so necessary for a gate when
embedded in a real environment.
• Relationship between the CG & Cint can be,
γ = proportionality factor
• Rewriting tp,
• Ratio between ext. & gate capacitance – Effective fan-out f.
EC7651/EC8651/VE7103/NE7081 - EK. 97
• Delay of jth inverter,
• Total delay:
• This has N – 1 unknowns, from Cg,2 to Cg,N. Minimum delay

can be found by partial differentiation and can be found as,
• Optimum size of each inverter is geometric mean of neighbor

sizes,
EC7651/EC8651/VE7103/NE7081 - EK. 98
• This means in overall, each inverter is sized up by same factor,
f, with respect to preceding gate, which can be,
• And minimum delay through the chain,
F – The overall effective fan-out & equals to CL/Cg,1.

– Strong function of number of gates.
• Inference:
– Relationship is linear when only one stage is present.
– Introducing second turns it to square and so on.
– How to choose number of stages?
EC7651/EC8651/VE7103/NE7081 - EK. 99
Choosing the right number of stages
• From previous equation, If no. of stages are high, intrinsic
delays dominants.
• If no. of stages are low, effective fan-out dominants.
• Optimum value can be found by differentiating minimum
delay expression by number of stages and setting it to 0,
• When γ = 0, (ignoring self loading), optimal number of stages

becomes N = ln(f) or 2.71 (e). For self-loading value should be
calculated.
EC7651/EC8651/VE7103/NE7081 - EK. 100

Choosing the right number of stages
• For γ = 1, f = 3.6.
• Choosing values of the higher fanout, does not impact the
delay, reduces number of buffer stages and area.
EC7651/EC8651/VE7103/NE7081 - EK. 101
Rise-Fall time of the Input signal
• All the expressions derived assuming
– Abrupt change in input signal
– Only one device is in “ON” state
• In reality,
– Input changes gradually or temporarily
– Devices conduct simultaneously
– This affects current for (dis)charging and impacts tp
Propagation Delay
vs.
Slope of input signal
EC7651/EC8651/VE7103/NE7081 - EK. 102
Rise-Fall time of the Input signal
• Revised propagation delay:
• Delay of inverter i equals to sum of delay of same gate for step

input and augmented with a fraction of step input delay of the
preceding gate (i-1)
• η =~ 0.25 (Empirical constant)
• For greater performance,
Rise time must be smaller or equal to gate propagation delays.
EC7651/EC8651/VE7103/NE7081 - EK. 103

Delay in the presence of Interconnects (Long)
• For far apart gates, capacitance & resistance dominate the
transient response
• The 0.38 factor accounts for the fact that wire represents
distributed delay.
• Delay expression contains linear as well as quadratic
components, which causes delay is a dominant factor in longer
wires.
EC7651/EC8651/VE7103/NE7081 - EK. 104

Power, Energy and Energy Delay
Robustness:
Symmetrical VTC
Full logic swing
High noise margin Most Contemporary Design
Low power consumption:
In steady state operation
EC7651/EC8651/VE7103/NE7081 - EK. 105

Power, Energy and Energy Delay
• Dynamic power dissipation

– Due to Charging & Discharging capacitances
– Low energy-power design techniques
– Dissipation due to Direct-path currents
• Static Consumption
• Putting it all together
– Power-Delay product
– Energy-Delay product
• Analyzing power consumption using SPICE
EC7651/EC8651/VE7103/NE7081 - EK. 106

Dynamic Power Dissipation
Charging & Discharging of capacitances
• ON PMOS:
– Voltage across CL raises from 0 to VDD
– Energy drawn from supply =
Energy dissipated in PMOS + Energy stored in CL
• ON NMOS (High to Low transition):
• Capacitor discharges
• Stored energy dissipated in NMOS
EC7651/EC8651/VE7103/NE7081 - EK. 107

• Assumption:
– Low to High transition
– Zero rise & fall times for input
– NMOS & PMOS never on simultaneously
– EVDD: Energy taken from supply
– EC: energy stored in the capacitor
• Energy taken from supply:
EC7651/EC8651/VE7103/NE7081 - EK. 108

• Energy stored in the capacitor:
• So, EC = EVDD/2
• Remaining power – Dissipated in the device.
• Dissipation doesn‟t depend on size.
EC7651/EC8651/VE7103/NE7081 - EK. 109

• Energy consumption depends on transitions:
– Low to High & High to Low
• If gate is switched ON & OFF f01 times,
• Advances on Technology
– Higher values of f01
– Total capacitance CL increases as gate count increases
• Switching activity f01
– Easily computed for one inverter
– Complex for higher-order gates and circuits
– Depends on the input signal
EC7651/EC8651/VE7103/NE7081 - EK. 110

Problem:
Calculate the dynamic energy and power dissipation for
an inverter with a load capacitance of 6fF that operates
at a maximum possible rate. (tp = 32.5ps).
Ans: Edyn = 37.5fJ, Pdyn = 580µW.
EC7651/EC8651/VE7103/NE7081 - EK. 111

• Rewriting the dynamic power equn.,
• f: Max. possible event rate

• P01: Probability that clock event results in 01.
• CEFF = P01CL : Effective capacitance
• Power consuming transitions: 2/8 = 0.25 (25%)

EC7651/EC8651/VE7103/NE7081 - EK. 112
Low Energy-Power design techniques
Pdyn = CEFFVDD2f
• Reducing VDD has quadratic effect on Pdyn

– But propagation delay increases
• Reduction in switching activity
– Accomplished only at Logic & architectural abstraction
levels
• Lowering the physical capacitances
– Sum of capacitances due to all transistors
– Minimal transistor size
– Maximal transistor size when Cext > CL
EC7651/EC8651/VE7103/NE7081 - EK. 113

Dissipation due to Direct-Path currents
• Assumption of zero rise & fall times are not correct
– NMOS & PMOS: simultaneously ON
– Finite slope cause direct path b/w VDD & GND
EC7651/EC8651/VE7103/NE7081 - EK. 114

• Energy during switching period (tsc),
Edp = tscVDDIpeak
• Avg. power consumption,
Pdp = tscVDDIpeakf
Pdp = CscVDD2f
• Ipeak: Function of ratio b/w input & output slopes
– Assumptions: Large CL & Small CL
EC7651/EC8651/VE7103/NE7081 - EK. 115

• Large CL:
– I/p moves through the transient before o/p starts to change
– Source-drain Voltage of PMOS is 0.
– Isc is close to zero
• Small CL:
– Source-Drain voltage is equal to VDD
– Maximal short circuit current
• Isc as a func. of CL:
EC7651/EC8651/VE7103/NE7081 - EK. 116

Design techniques
• Power dissipation minimized by matching the rise/fall
times of input & output signals
• Lowering supply voltage.
EC7651/EC8651/VE7103/NE7081 - EK. 117

Static consumption
Pstat = IstatVDD
• Istat – Current flow in supply rails in absence of switching activity
• Istat = 0 : PMOS & NMOS never simultaneously ON in steady state
• Leakage current: RB diode junctions of the transistors
– Very small & Ignored
– ~10 – 100 pA/μm2
– For 1 million transistors,
Leakage power = 0.125mW
• But, leakage current
α Temperature
• Leakage current:
– Sub-threshold current
@ Weak inversion region
EC7651/EC8651/VE7103/NE7081 - EK. 118
Total Power dissipation
Ptot = Pdyn + Pdp + Pstat

Ptot = CLVDD2f01 + VDDIpeaktsf01 + VDDIleak
Dynamic Power Direct Path Power Leakage Power
CL Ipeak Ileak
Dominant Factor Kept within Bounds Ignorable @ present
EC7651/EC8651/VE7103/NE7081 - EK. 119

Power-Delay product
• Quality measure of a logic gate
• Average energy consumed per switching event
PDP = Ptot * tp
• Assuming fmax = 1/(2tp), ignoring Ipeak & Ileak,
PDP = CLVDD2fmaxtp
=(CLVDD2)/2
• But Energy,
– Average energy per switching cycle
– Twice that of PDP
EC7651/EC8651/VE7103/NE7081 - EK. 120

Energy-Delay Product
• Measure of performance and energy
EDP = PDP x tp
= Ptot x tp
={(CLVDD2)/2} x tp
• Delay from first order analysis,
α – Technology parameter
Taking Derivative
EC7651/EC8651/VE7103/NE7081 - EK. 121

SPICE Modeling: Power Consumption plot
Average Power
(Over One Cycle)
Vin : 01
Vout : 10
EC7651/EC8651/VE7103/NE7081 - EK. 122

Gate delay vs. Scaling
EC7651/EC8651/VE7103/NE7081 - EK. 123

Summary: CMOS inverter – A Circuit Perspective
• Static CMOS: Pull-up PMOS + Pull-down NMOS
– Wider PMOS due to its lower current driving capabilities
• Ideal VTC
– Logic swing = VDD & Not a function of transistor sizes
• Propagation delay:
– Dominated by CL : time taken to charge & discharge
• Dynamic power
– Dominated by CL : power consuming during charging &
discharging
– Ignoring static & direct-path power
• Scaling the technology
– Reducing area, power & delay
• Interconnections: Larger fraction in delay & performance
EC7651/EC8651/VE7103/NE7081 - EK. 124
CHAPTER – II
Designing Combinational
Logic Gates in CMOS
EC7651/EC8651/VE7103/NE7081 - EK. 125
Introduction
Combinational Logic:
“Non-Regenerative circuits”
• At any point in time, output of the circuit is related to
its current input signals by some Boolean expression
• No intentional connection between i/p & o/p
Sequential Logic:
“Regenerative circuits”
• Output is not only a function of current input data but
also previous values of input signals.
• Connecting (some) output intentionally to the input
• Sense of “Remembering” the history
• Combinational Logic + Module to hold the state
EC7651/EC8651/VE7103/NE7081 - EK. 126
Introduction
• Function: Combinational Logic
– Numerous Logic Styles
• Emphasis:
– Application depended
• Metrics:
– Area Sequential Logic
– Speed
– Energy
– Power
– Reliability
– Sensitivity to noise
EC7651/EC8651/VE7103/NE7081 - EK. 127

Static CMOS design
• Static CMOS style:
– Extension of CMOS inverter to multiple inputs
• Advantages of Static CMOS inverter:
– Robustness to noise
– High performance
– Low power consumption
• Static circuits:
– Each gate output is connected to either VDD or VSS
implementing some Boolean function (ignoring transient
effects during switching)
• Dynamic circuits:
– Output relies on temporary storage of signals on the
capacitances of high impedance nodes
EC7651/EC8651/VE7103/NE7081 - EK. 128
Complementary CMOS
• Generic N-input logic gate

where all inputs are
distributed to both PUN
and PDN.
• PUN: Connection between

VDD and Output.
• PDN: Connection between

GND and Output.
• PDN and PUN are

mutually exclusive.
EC7651/EC8651/VE7103/NE7081 - EK. 129

Complementary CMOS
Observations (Constructing PUN & PDN):
• Transistor can be thought of a switch
Gate Signal NMOS PMOS
High ON OFF
Low OFF ON
• PDN is constructed using NMOS & PUN is

constructed using PMOS devices
– NMOS produces STRONG zeros
– PMOS produces STRONG ones
EC7651/EC8651/VE7103/NE7081 - EK. 130

Complementary CMOS
Observations:
• Set of construction rules can be formed
Connection NMOS PMOS
Series AND NOR
Parallel OR NAND
NMOS in Series:
NMOS in Parallel:
EC7651/EC8651/VE7103/NE7081 - EK. 131

Complementary CMOS
Observations:
• Using De-Morgan‟s theorems,
– PUN & PDN of complementary CMOS are dual networks.
– Parallel connection in PUN corresponds to Serial
connection in PDN
• Complementary gate is naturally inverting
– Can implement inverting Boolean functions
(NAND, NOR & XNOR)
– Realization of Non-inverting Boolean functions requires
additional inverter stage
(AND, OR & XOR)
• No. of transistors required to implement N-input logic
gate is 2N.
EC7651/EC8651/VE7103/NE7081 - EK. 132

Two input NAND gate
EC7651/EC8651/VE7103/NE7081 - EK. 133

Synthesis of complex CMOS gate
Steps:
1. Derive pull down network
i. Series NMOS = AND
ii. Parallel NMOS = OR
2. Use duality to derive pull up network
[Break PDN into subnets (SNs)]
EC7651/EC8651/VE7103/NE7081 - EK. 134

EC7651/EC8651/VE7103/NE7081 - EK. 135

EC7651/EC8651/VE7103/NE7081 - EK. 136

Static properties of C-CMOS
• Rail to rail swing
– VOH = VDD & VOL = GND
• No static power dissipation
– PUN & PDN are mutually exclusive
• VTC is complicated than CMOS inverter
– Depend on input patterns
• For two-input NAND gate
– Three possible combinations to switch high to low
o A=B=0
o A = 1, B = 0
o A =0, B = 1
EC7651/EC8651/VE7103/NE7081 - EK. 137

Static properties of C-CMOS
EC7651/EC8651/VE7103/NE7081 - EK. 138

Propagation Delay of
Complementary CMOS
EC7651/EC8651/VE7103/NE7081 - EK. 139

Propagation Delay of C-CMOS Gates
• For Delay analysis,
Transistor ≡ Resistor in series with a Switch
EC7651/EC8651/VE7103/NE7081 - EK. 140

• Propagation delay depends on input patterns
Consider 2 input NAND:
L  H transition
– 00, 01 & 10.
– For 00,
Both PMOS are ON,
0.69 X (RP/2) X CL
– For 01 or 10,
Only one PMOS is ON,
0.69 X RP X CL
H  L transition
– For 11,
Adding devices in series,
Both NMOS are ON, Slow down the circuit
0.69 X 2RN X CL
EC7651/EC8651/VE7103/NE7081 - EK. 141
Delay dependencies on Input Patterns
EC7651/EC8651/VE7103/NE7081 - EK. 142

NOR implementation:
EC7651/EC8651/VE7103/NE7081 - EK. 143

Strategies in NOR implementation:
• Worst-case Pull Down:
– A or B is high.
• NMOS can have same sizes (in Parallel)
• Pull Up:
– A & B are high
– Resistances add-up
– So, Increasing size of PMOS
• Due to lower mobility in PMOS,
– Series stacking must be avoided
A NAND implementation is preferred over NOR

implementation
EC7651/EC8651/VE7103/NE7081 - EK. 144
Cint for Larger fan-ins – 4 input NAND gate:
EC7651/EC8651/VE7103/NE7081 - EK. 145

Cint for Larger fan-ins – 4 input NAND gate:
• By Elmore‟s delay model,
• For equal size NMOS,
EC7651/EC8651/VE7103/NE7081 - EK. 146

Problems in C-CMOS Style
1. No. of transistors
• 2N transistors for N input gate
• Increase in overall capacitance
• L  H delay increases with fan-in, when
capacitance increases as resistance remains
unchanged
2. Propagation delay
• Series connection of transistors causes additional
slow-down
• Quadratic delay (H  L)
EC7651/EC8651/VE7103/NE7081 - EK. 147

Problems in C-CMOS Style
Fan-in vs. Delay
EC7651/EC8651/VE7103/NE7081 - EK. 148

Design Techniques for Large Fan-in
Techniques to reduce delay of large fan-in circuits:
I. Transistor sizing
II. Progressive transistor sizing
III. Input Reordering
IV. Logic Restructuring
EC7651/EC8651/VE7103/NE7081 - EK. 149

Transistor Sizing:
• Increase transistor size

• Lowers the resistance & therefore lowers the delay
• But increases parasitic capacitance
– Increases delay
– Larger load
– “Self-Loading”
• Sizing is effective when load is dominated by fan-out.
EC7651/EC8651/VE7103/NE7081 - EK. 150

Progressive transistor sizing:
• Consider,
• R1 appears N times, R2 appears N-1 times & so on

• Keep R1 smallest, R2 next smallest….
• Therefore, M1 largest, M2 next largest….
M1 > M2 > M3 > MN
• Not easy in real layout

EC7651/EC8651/VE7103/NE7081 - EK. 151
Progressive transistor sizing:
EC7651/EC8651/VE7103/NE7081 - EK. 152

Input Reordering:
• Critical input – Last signal of all input to make a

stable value
• Critical path – The path through the logic
determines the speed of the structure
• Putting the critical path transistor closer to the output
of the gate.
EC7651/EC8651/VE7103/NE7081 - EK. 153

Logic Restructuring:
• Manipulating the fan-in requirements

– By analyzing logic equations
• Quadratic delay can be reduced by splitting fan-ins
1. 6 input NOR  2 X 3 input NOR
2. NOT  2 input NAND
EC7651/EC8651/VE7103/NE7081 - EK. 154

Optimizing Performance in Combinational Circuits
• Delay equation of the inverter,
• Modified to,
tp0 = intrinsic delay of the inverter

f = effective fan-out or electrical effort
p = ratio of intrinsic delay of complex gate and inverter
γ = proportionality factor
g = logical effort
• Logical effort: For given load, complex gates have to
work harder than an inverter to produce similar
responses
EC7651/EC8651/VE7103/NE7081 - EK. 155
Values of P for some standard gates (ignoring second order effects)
EC7651/EC8651/VE7103/NE7081 - EK. 156

Logical effort:
For given load, complex gates have to work harder than an

inverter to produce similar responses.
OR
The logical effort of a logic gate tells how much worse it is at

producing output current than an inverter, given that each of
its inputs may contain only the same input capacitance as the
inverter.
OR
Logical effort is how much more input capacitance a gate

presents to deliver the same output current as an inverter.
EC7651/EC8651/VE7103/NE7081 - EK. 157
Logical effort:
EC7651/EC8651/VE7103/NE7081 - EK. 158

Logical Effort for Standard Gates
(Assuming PMOS-NMOS ratio of 2)
EC7651/EC8651/VE7103/NE7081 - EK. 159

Delay as a function of fan-out:
Observations:
• Fan-Out (f) and Logical

Effort (g) contribute to
the delay in a similar
way.
• Gate Effort,
Product of the two,
h = fg
EC7651/EC8651/VE7103/NE7081 - EK. 160

Delay as a function of fan-out:
• The total path delay can be,
• By finding N – 1 partial derivatives & each stage bear same

„effort‟,
• Fan-outs along the path can be multiplied to get a path
effective fan-out, so can the logical efforts,
• As in inverter, the gate effort that minimizes the path delay,
• So, minimum delay through the path,
EC7651/EC8651/VE7103/NE7081 - EK. 161

Power Consumption in
CMOS Logic Gates
EC7651/EC8651/VE7103/NE7081 - EK. 162

Power Consumption in C-CMOS
• Function of
– Transistor sizing
– Input & Output Rise/Fall times
– Device threshold
– Temperature
– Switching activity
• Power consumption,
CLVDD2f01
• Switching activity:
– Static Component: Function of topology of logic network
– Dynamic component: Timing behavior
EC7651/EC8651/VE7103/NE7081 - EK. 163

Logic Function:
• Transition activity depends on the input function
• Transition probability:
• For N independent & uniformly distributed inputs,
N0 : Number of Zero entries

N1 : Number of One entries
EC7651/EC8651/VE7103/NE7081 - EK. 164
Logic Function:
Transition probability for two-input NOR gate:
EC7651/EC8651/VE7103/NE7081 - EK. 165

Signal Statistics:
• In 2 input NOR gate: For uncorrelated inputs,
p1 : Probability that output node is one

pa : Probability that input A is one
pb : Probability that input B is one
• Probability of transition from 0 to 1,
EC7651/EC8651/VE7103/NE7081 - EK. 166

Intersignal Correlations:
• Uncorrelated signals  Correlated
Fig. 1:
• Node C has probability of ½ for 1 (0).
• P0 to 1 for AND gate is 3/16.
Fig. 2:
• Above assumption fails for inter-signal
dependencies because Z = C . B = A .
A’ = 0, thus no transition takes place.
• Include conditional probabilities to

deal this issue.
• pZ = p(C=1|B=1) • p(B=1)
EC7651/EC8651/VE7103/NE7081 - EK. 167

Dynamic or Glitching Transitions:
• Finite propagation delay in logic blocks.
• A node can exhibit multiple transitions in single clock cycle
before settling to correct logic level.
EC7651/EC8651/VE7103/NE7081 - EK. 168

Design techniques to reduce switching activity
• Dynamic power depends on
– Physical capacitance
– Switching activity
• Physical capacitance can be reduced by

– Circuit style selection
– Transistor sizing
– Placement
– Routing
– Architectural optimizations
• Switching activity can be reduced at all levels of

design abstraction
EC7651/EC8651/VE7103/NE7081 - EK. 169

Logic Restructuring:
EC7651/EC8651/VE7103/NE7081 - EK. 170

Input Reordering:
EC7651/EC8651/VE7103/NE7081 - EK. 171

Time Multiplexing Resources:
EC7651/EC8651/VE7103/NE7081 - EK. 172

Glitch reduction by balancing signal paths:
EC7651/EC8651/VE7103/NE7081 - EK. 173

Ratioed Logic
EC7651/EC8651/VE7103/NE7081 - EK. 174

Ratioed Logic
Concept:
• Attempt to reduce the number of transistors used to
implement a given logic function
• PUN & PDN – Provides conditional path
• In ratioed logic, entire PUN is replaced by
unconditional load
• Types: Generic & Pseudo NMOS
EC7651/EC8651/VE7103/NE7081 - EK. 175

Ratioed Logic
Concept:
• No. of transistors reduced to (N+1)
(2N for C-CMOS)
• For low input: PDN are turned off, so F = VDD.
• For high input: F ≠ GND.
– Reasons: Fight between PDN & grounded PMOS.
– Results in reduced noise margin
– Size of PMOS and PDN can be used to find out delay,
power & noise margins
• DC transfer characteristics: (for Pseudo NMOS)
– Value of VOL can be obtained by equating current through
driver and load devices for Vin = VDD
– NMOS: Linear region
– PMOS load: Saturated.
EC7651/EC8651/VE7103/NE7081 - EK. 176
Ratioed Logic
Concept:
• To make VOL as low as possible, PMOS must be sized

smaller than NMOS.
• Unfortunately, this has a negative impact on the
propagation delay for charging up the output node since
the current provided by the PMOS device is limited.
• Power: (Direct path when Output is LOW)
EC7651/EC8651/VE7103/NE7081 - EK. 177

Ratioed Logic
VTC of pseudo-NMOS inverter as a function of PMOS size:
EC7651/EC8651/VE7103/NE7081 - EK. 178

Ratioed Logic
VTC of pseudo-NMOS inverter as a function of PMOS size:
EC7651/EC8651/VE7103/NE7081 - EK. 179

Ratioed Logic
Concept:
• For Larger Fan-in circuits:
– When area is most important, the reduced transistor count
compared to complimentary CMOS is quite attractive.
EC7651/EC8651/VE7103/NE7081 - EK. 180

Ratioed Logic
Building Better Load:
• It is possible to build ratioed logic that completely
eliminates static current and provides rail-to-rail
swing.
• Combination of differential logic & positive feedback
• Differential logic: requires each input in
complementary format & produces output in
complementary format.
• Feedback circuit ensures load devices are turned off
when not needed.
• Ex.: Differential Cascode Voltage Switch Logic
(DCVSL)
EC7651/EC8651/VE7103/NE7081 - EK. 181

Ratioed Logic
Building better load:
• PDN1 & PDN2 are

mutually exclusive
• Required logic function
and its inverse are
simultaneously
implemented.
• Assume, Out is ON &
Out’ is OFF.
• Turning ON PDN1
(PDN2 - OFF), bring
OUT to GND (Fight).
• In turn, OUT will bring
M2 ON, making Out’ to
VDD.
• In turn M1 will be OFF.
EC7651/EC8651/VE7103/NE7081 - EK. 182

Ratioed Logic
Building better load: (XOR & XNOR logic)
EC7651/EC8651/VE7103/NE7081 - EK. 183

Ratioed Logic
Advantages:
• Provides rail-to-rail swing
• Static dissipation is eliminated
• No simultaneous NMOS/load devices conduct
Disadvantages:
• Power dissipation due to cross-over currents
• Transition period (both are simultaneously ON)
• Increasing complexity
EC7651/EC8651/VE7103/NE7081 - EK. 184

Ratioed Logic
DCVSL Transient response for AND/NAND logic:
• Out is pulled down to VDD-|VTp|, Out’ starts to charge up to VDD

quickly.
• The delay from the input to Out is 197 psec and to Out’ is 321 psec.
• A static CMOS AND gate (NAND followed by an inverter) has a delay
of 200ps.
EC7651/EC8651/VE7103/NE7081 - EK. 185
Ratioed Logic
Design considerations:
• In DCVSL, both output & its inverse are simultaneously
available
• Additional inverter stage is not needed.
• No. of gates are reduced. Disadvantages:
• The differential nature
virtually doubles the
number of wires that
has to be routed,
leading very often to
unwieldy designs (on
top of the additional
implementation over-
head in the individual
gates).
• Additionally, the
dynamic power
dissipation is high.
EC7651/EC8651/VE7103/NE7081 - EK. 186
Pass Transistor Logic
EC7651/EC8651/VE7103/NE7081 - EK. 187

Basics:
• Alternative to C-CMOS:
– Primary Inputs drive the gate as well as source/drain
terminals.
• AND logic:
• The B’ switch is not
redundant.
• It ensures a low
impedance path exists
to rails when B = 0.
• Advantages:
– No. of Transistors: 4 (2 + 2 for inverting B)
– Using C-CMOS: 6 transistors
EC7651/EC8651/VE7103/NE7081 - EK. 188

Basics:
• Pulling 0 for NMOS device is effective but for pulling to VDD,
it is poor because, it will charge upto VDD – VTn.
• Body effect since both source/drain & gate is connected to
VDD.
• If IN is low, NO low impedance path also to rails exists.
EC7651/EC8651/VE7103/NE7081 - EK. 189

Cascading pass transistor:
• Pass-transistor gates cannot be cascaded by connecting
the output of a pass gate to the gate input of another
pass transistor.
EC7651/EC8651/VE7103/NE7081 - EK. 190

VTC of AND using pass transistor:
• Inverter threshold: VDD/2
EC7651/EC8651/VE7103/NE7081 - EK. 191

Differential Pass Transistor Logic
Concept:
• For high performance design, differential pass transistor logic is
used, CPL or DPL.
• Basic idea is to accept true and complementary inputs and to
produce true and complementary outputs.
• CPL gates:
EC7651/EC8651/VE7103/NE7081 - EK. 192

Properties of CPL gates:
• Since the circuits are differential,
– True & Complementary outputs are always available
– Complex circuits can be realized efficiently
– Inverter can be eliminated
• CPL belongs to static gates
– Output nodes are always connected to VDD or GND
– Advantages over noise margins
• Modular design
– All gates use same topology
– Library of gates are simple
– Only inputs are permuted
EC7651/EC8651/VE7103/NE7081 - EK. 193

4 input AND/NAND using CPL:
EC7651/EC8651/VE7103/NE7081 - EK. 194

Robustness and Efficient Pass Transistor design:
Problem: Static power dissipation since high input

charging up to VDD - VTn
Solutions:
1. Level Restoration
2. Multiple-threshold transistors
3. Transmission gate logic
EC7651/EC8651/VE7103/NE7081 - EK. 195

Level Restoration:
EC7651/EC8651/VE7103/NE7081 - EK. 196

Level Restoration (A level restorer that is too large can
result in incorrect evaluation):
EC7651/EC8651/VE7103/NE7081 - EK. 197

Multiple-threshold transistors:
EC7651/EC8651/VE7103/NE7081 - EK. 198

Transmission Gate Logic:
EC7651/EC8651/VE7103/NE7081 - EK. 199

Transmission Gate Logic: Inverting Multiplexer:
EC7651/EC8651/VE7103/NE7081 - EK. 200

Transmission Gate Logic: Example – XOR:
EC7651/EC8651/VE7103/NE7081 - EK. 201

Performance of Pass-Transistor & Transmission Gate
Logic:
EC7651/EC8651/VE7103/NE7081 - EK. 202

Dynamic CMOS Design
EC7651/EC8651/VE7103/NE7081 - EK. 203

Schema
• Basic Principles
• Speed and Power dissipation
• Signal integrity issues
• Cascading dynamic gates
EC7651/EC8651/VE7103/NE7081 - EK. 204

Dynamic CMOS Design
Basic Principles: (n-type)
• Two phases:
– Precharge
– Evaluation
• PDN – similar to C-CMOS
• Precharge:
– CLK = 0
– Me eliminates static power
• Evaluation:
– CLK = 1
– Output is conditionally
discharged based on i/p
– If PDN is ON, Out  GND
– If PDN is OFF, Out  CL
– The inputs can make atmost
one transition during this
phase. EC7651/EC8651/VE7103/NE7081 - EK. 205
Dynamic CMOS Design
Basic Principles:
Example:
EC7651/EC8651/VE7103/NE7081 - EK. 206

Dynamic CMOS Design
Properties:
• Logic function is implemented by NMOS pull-down
network only
• No. of transistors = N + 2
• It is non-ratioed
– Size of precharge (PMOS) device can be made larger to
improve L  H transition time
• It consumes only dynamic power
• Faster switching speeds
– Lower no. of transistors  Lower CL value
– No short circuit current; all current goes to discharge load
capacitance.
EC7651/EC8651/VE7103/NE7081 - EK. 207
Dynamic CMOS Design
Speed and Power Dissipation:
• After precharge phase,
– Output is high
• For low i/p signal, no switching occurs: (After

precharge phase, O/P = 1)
– tpLH = 0
• For high i/p signal, discharging occurs:

– tpHL α CL
• Precharge time:
– Time takes to charge CL
– Logic in the gate cannot be utilized
– Dead zone !! (Other functions can be used)
EC7651/EC8651/VE7103/NE7081 - EK. 208
Dynamic CMOS Design
Four input dynamic NAND:
EC7651/EC8651/VE7103/NE7081 - EK. 209

Dynamic CMOS Design
Power Dissipation:
• Advantage:
– Physical capacitance is low
– One transition per clock cycle
– Do not exhibit static power dissipation
• Offset considerations:
– Dynamic clock power
– No. of transistors may be higher (for particular logic)
– Short circuit current due to leakage
– Higher switching activity due to precharge & evaluation
– O/p transition doesn't depend on inputs rather signal
probabilities.
EC7651/EC8651/VE7103/NE7081 - EK. 210

Dynamic CMOS Design
Activity Estimation in dynamic NOR:
For High to Low transition

• Static NOR – Based on logic (correlated inputs), P0 = 3/16 = 0.1875.
• Dynamic NOR – P0 = ¾ = 0.75.
• Static NAND – P0 = 3/16 = 0.1875.
• Dynamic NAND – P0 = ¼ = 0.25.
EC7651/EC8651/VE7103/NE7081 - EK. 211
Dynamic CMOS Design
Signal Integrity Issues:
Considerations to make Dynamic circuits function

properly:
1. Charge leakage
2. Charge sharing
3. Capacitive coupling
4. Clock feedthrough
EC7651/EC8651/VE7103/NE7081 - EK. 212

Dynamic CMOS Design
1. Charge Leakage:
• Operation of dynamic gate
relies on dynamic storage of
output value on capacitor
• If PDN is off, o/p should
remain at pre-charged state
of VDD.
• But due to leakage currents,
charge gradually leaks
EC7651/EC8651/VE7103/NE7081 - EK. 213

Dynamic CMOS Design
1. Charge Leakage:
• NMOS leakage:
– Source 1: Reverse-biased diode
– Source 2: Sub-threshold leakage
– Effect: Leakage
– Low performance
• PMOS leakage;
– Source 3: Reverse-biased diode
– Source 4: Sub-threshold leakage
– PMOS leakage counteracts
NMOS leakage
– O/p will be set by resistive
divider composed of pull-up and
pull-down paths
EC7651/EC8651/VE7103/NE7081 - EK. 214
Dynamic CMOS Design
1. Charge Leakage:
EC7651/EC8651/VE7103/NE7081 - EK. 215

Dynamic CMOS Design
Impact of charge leakage: The output settles to an intermediate
voltage determined by a resistive divider of the pulldown and
pull up devices.
EC7651/EC8651/VE7103/NE7081 - EK. 216

Dynamic CMOS Design
1. Charge Leakage:
• Leakage is due to high impedance state of o/p during
evaluation mode, when PDN is off.
• Leakage can be counteracted by reducing o/p
impedance by connecting bleeder transistor to o/p.
• Function of bleeder is to only compensate lost charge
• Static current can be avoided by:
– Keeping small device
– Connecting in feedback configuration
EC7651/EC8651/VE7103/NE7081 - EK. 217

Dynamic CMOS Design
1. Charge Leakage: Bleeder Transistor
Bleeder Transistor With Feedback
EC7651/EC8651/VE7103/NE7081 - EK. 218

Dynamic CMOS Design
2. Charge Sharing:
• Initial state: A, B = 0
– Ca is discharged.
• Precharge:
– CL – Charged upto VDD.
• Evaluation:
– Only A takes 0  1
– Charge on CL is distributed to Ca
– This causes drop in o/p voltage
– Can‟t be recovered
• Scenarios:
– Vout < VTn: Vx = VDD – VTn
– Vout > VTn: Vx = Vout
EC7651/EC8651/VE7103/NE7081 - EK. 219
Dynamic CMOS Design
2. Charge Sharing:
Approach to deal with charge sharing:
Precharge internal nodes
EC7651/EC8651/VE7103/NE7081 - EK. 220

Dynamic CMOS Design
3. Capacitive Coupling:
In 0  1, makes out 2 to low, causing out 1 drops.
EC7651/EC8651/VE7103/NE7081 - EK. 221

Dynamic CMOS Design
4. Clock feedthrough:
• Special case of capacitive coupling

• Coupling b/w clock i/p of precharge & o/p node
• Coupling capacitance rises charge over VDD.
• This causes the junction diodes to forward biased
– Electron injection into substrate
– Faulty operation
EC7651/EC8651/VE7103/NE7081 - EK. 222

Dynamic CMOS Design
Cascading Dynamic gates:
• Inverter Cascading
EC7651/EC8651/VE7103/NE7081 - EK. 223

Dynamic CMOS Design
Domino Logic:
EC7651/EC8651/VE7103/NE7081 - EK. 224

Dynamic CMOS Design
Domino Logic:
Properties:
• Since each gate has static inverter, only non-inverting
logic can be implemented.
• Higher speed can be achieved (tpLH = 0).
Ripple precharge when Me is removed:
EC7651/EC8651/VE7103/NE7081 - EK. 225

Dynamic CMOS Design
np-CMOS:
EC7651/EC8651/VE7103/NE7081 - EK. 226

Summary
• Static Complementary CMOS combines PDN &
PUN, only one of which can be enabled at any time.
• Performance of CMOS gate is function of fan-in.
• Ratioed logic style consists of active pull down
network connected to load device.
• Pass transistor logic implements a logic gate as a
simple switch network.
• Dynamic logic gate operates based on charge stored
on the capacitive output node.
• Power consumption is strongly related to switching
activity of network.
EC7651/EC8651/VE7103/NE7081 - EK. 227
CHAPTER – III
Part - A
Designing Sequential
Logic Circuits
EC7651/EC8651/VE7103/NE7081 - EK. 228
Schema
 Introduction
 Static Latches and Registers
◦ Bistability principle
◦ Static SR Flip-Flops
◦ Multiplexer based Latches
◦ Master-Slave Edge-Triggered Register
◦ Low-Voltage Static Latches
 Dynamic Latches and Registers
◦ Dynamic Transmission-Gate Edge-Triggered Registers
◦ C2MOS – A Clock-Skew Insensitive Approach
◦ True Single-Phase Clocked Register (TSPCR)
 Pipelining: An approach to Optimize Sequential Circuits
 Perspective: Choosing a Clocking Strategy
EC7651/EC8651/VE7103/NE7081 - EK. 229

Introduction
 Combinational Logic:
◦ O/P is the function current i/p values
◦ It doesn’t remembers history of inputs
 Sequential Logic:
◦ O/P is not only the function of current i/p values but
also upon preceding i/p values
◦ Remembers some of the history – requires memory.
 Example: Finite State Machine
EC7651/EC8651/VE7103/NE7081 - EK. 230

Introduction
Timing Metrics for Sequential Circuits:
 Setup time (tsu): Time data input is valid before the
clock transition
 Hold time (thold): Time the data input must remain
valid after clock edge.
 Propagation delay (tc-q): Assuming setup time and
hold time met, input D is copied to output Q after a
delay.
EC7651/EC8651/VE7103/NE7081 - EK. 231

Introduction
Timing Metrics for Sequential Circuits:
 Assume, tplogic is worst case propagation delay of the
logic & tcd is minimum delay (contamination delay),
The minimum clock period for proper operation of
sequential circuit is,
T ≥ tc-q + tplogic + tsu
tcdregister + tcdlogic ≥ thold
(tcdregister is Propagation delay of register)
 Timing parameters directly associated with clock

period
EC7651/EC8651/VE7103/NE7081 - EK. 232

Introduction
Classification of Memory elements:
Foreground vs Background memory:
 Foreground: Memory embedded in a logic
(Registers, Register banks)
 Background: Large amount of centralized core
(Array structures)
Static vs Dynamic memory:
 Static:
◦ Preserve the state as long as power is turned on
◦ Built using positive feedback or regeneration
◦ Useful when registers will not be updated for
extended periods of time
◦ Memory based on positive feedback: Multivibrator
◦ Bistable element is popular representative.
◦ Astable/Monostable also can be used.
EC7651/EC8651/VE7103/NE7081 - EK. 233
Introduction
 Dynamic:
◦ Stores data for a short period of time
◦ Based on charge storage on parasitic capacitors
◦ In dynamic logic, capacitors have to be refreshed to
compensate for charge leakage. (Precharge)
◦ Higher performance, low power dissipation.
◦ Periodical clocking
Latches vs Registers:
◦ Latch used to construct edge triggered register
◦ Level sensitive
◦ Positive latch: Transparent mode: CLK is high.
Hold mode: CLK is low.
◦ Negative latch: Transparent mode: CLK is low.
Hold mode: CLK is high.
EC7651/EC8651/VE7103/NE7081 - EK. 234

Introduction
◦ Registers: - Edge triggered
◦ Positive edge triggered: 0  1
◦ Negative edge triggered: 1  0
 Edge-triggered storage element: Register
 Latch: Level-sensitive device
 Bistable element formed by cross coupling of gates:
Flip-flops
EC7651/EC8651/VE7103/NE7081 - EK. 235

Schema
 Introduction
EC7651/EC8651/VE7103/NE7081 - EK. 236

Static Latches and Registers
The Bistability principle:
 Static memories use positive feedback to create a
bistable circuit.
 Basic Idea: “Two cascaded Inverters”
Rotated to
accentuate
Vi2 = Vo1
EC7651/EC8651/VE7103/NE7081 - EK. 237

 Important Conjecture:
◦ Under the condition that the gain of the inverter in the
transient region is larger than 1, only A & B are stable
operating points, C is a meta-stable operating point.
 If the inverter is biased at point C, a small
deviation caused (by noise) is amplified and
regenerated around the loop: Meta-stability.
Meta-stable Stable
Point: Points:
C A&B
EC7651/EC8651/VE7103/NE7081 - EK. 238

 Bistable circuit serves as a memory element:
◦ Two stable states – Storing 1 or 0
 To change the state:
◦ Bring the state from A to B / B to A.
◦ Making A (or B) to temporarily unstable state by
increasing G (Gain) larger than unity by using a
trigger pulse at Vi1 or Vi2.
◦ Width of trigger pulse need to be little larger than
total propagation delay of the circuit.
 Summary:
◦ Without triggering, circuit remains in single state.
◦ With triggering, state can be changed.
◦ Bistable circuit: Flip-Flops or Edge-triggered register.
EC7651/EC8651/VE7103/NE7081 - EK. 239

Schema
 Introduction
EC7651/EC8651/VE7103/NE7081 - EK. 240

The S-R Flip-Flop:
 Extra circuitry is needed to control memory states.
 Simplest incarnation: Set-Reset Flip-Flop.
 Nor based SR Flip-Flop:
EC7651/EC8651/VE7103/NE7081 - EK. 241

The S-R Flip-Flop:
 But most systems operate in synchronous fashion
with transition events referred to a Clock
 Possible realization is Clocked SR FF using
inverters with 8 transistors (4 for Inv. + 4 to drive one
state to other)
 Same no. of transistors
with added Clocking
feature.
EC7651/EC8651/VE7103/NE7081 - EK. 242

Sizing of S-R Flip-Flop:
 Drawback of saving more transistors in fully
complementary CMOS is that transistors sizing
becomes critical in ensuring proper functionality.
 Case: Q is High & Reset pulse is applied.
◦ Transistor M4, M7 & M8 forms Ratioed inverter.
◦ In-order to bring Q less than below switching threshold of
M1 & M2, Sizing of M5, M6, M7 & M8 have to be done.
It is must
to have
W/L ratio
of M5 & M6
larger than
3 to switch
SR FF.
EC7651/EC8651/VE7103/NE7081 - EK. 243

Propagation Delay of S-R Flip-Flop:
 Case: Q and Qbar are set to be 0 & 1.
 So, pulse is to be applied to node S.
i. Qbar discharges &

Q remains at 0.
ii. Q raises only

when switching
threshold of M3-
M4 is reached.
iii.Delay of the
transient solely
determined by
M3-M4.
iv.Delay:
tpQ < tpQbar
EC7651/EC8651/VE7103/NE7081 - EK. 244

Schema
 Introduction
EC7651/EC8651/VE7103/NE7081 - EK. 245

Multiplexer-based Latches:
 Use of transmission gate multiplexers to build a
latch is most common and robust approach.
CLK Negative Latch Positive Latch
i. Input 0 is selected i. Input 0 is selected
Low
ii. D is passed to output ii. Output is connected as feedback
i. Input 1 is selected i. Input 1 is selected
High
ii. Output is connected as feedback ii. D is passed to output
EC7651/EC8651/VE7103/NE7081 - EK. 246

Transistor Level implementation of Positive latch
using Transmission gates:
i. When CLK is high, bottom
transmission gate is on, D
is copied into Q.
ii. Feedback loop is open

because top transmission
gate is OFF.
iii.Sizing is not critical here
iv.Activity factor of CLK is

one.
v. Not very efficient design:

It presents load of four
transistors to CLK signal.
EC7651/EC8651/VE7103/NE7081 - EK. 247

Multiplexer based NMOS latch by using NMOS-only
pass transistors:
i. CLK load is reduced
ii. NMOS pass transistor passes

VDD – VTn
iii.Causes static power dissipation
because PMOS of inv never fully
turned off.
EC7651/EC8651/VE7103/NE7081 - EK. 248

Schema
 Introduction
EC7651/EC8651/VE7103/NE7081 - EK. 249

Master-Slave Edge-Triggered Register:
 Common approach for designing Edge-triggered
register is to use master-slave configuration.
Positive Edge Triggered Negative Edge Triggered

Master Negative Latch Positive Latch
Slave Positive Latch Negative Latch
EC7651/EC8651/VE7103/NE7081 - EK. 250

Master-Slave Edge-Triggered Register:
Transistor Level implementation of positive edge
triggered register:
CLK T1 T2 Event 1 T3 T4 Event 2
Low On Off D is sampled into QM Off On I5 & I6 Holds Slave
High Off On I2 & I3 Holds QM On Off QM is copied to Q
EC7651/EC8651/VE7103/NE7081 - EK. 251

Timing Properties of Master-Slave Edge-Triggered Registers:
 Setup time:
◦ Time before the rising edge of the CLK that the input data
D must be valid.
◦ i.e., How long D is stable such that QM samples the
value?
◦ D has to propagate through I1, T1, I3 & I2 (To ensure
node voltages on both terminal of T2 are same) before
rising edge of the CLK.
◦ Therefore, Setup time = [(3 X tpd_inv) + tpd_tx].
 Hold time:
◦ Time that the input is stable after rising edge of the CLK
◦ T1 turns off when CLK is high & any changes in D after
CLK going high are not seen by input .
◦ Therefore, Hold time = 0.
EC7651/EC8651/VE7103/NE7081 - EK. 252

 Propagation delay:
◦ Time takes for QM to propagate to Q
◦ Since, delay of I2 is included in setup time, I4 is valid
before rising edge of the clock.
◦ Therefore, delay tc-q is delay through T3 & I6.
◦ tc-q = tpd_tx + tpd_inv.
 Timing Analysis:
◦ Case 1:
 Setup time = 210ps
 Correct value of D is sampled; Q remains at VDD.
◦ Case 2:
 Setup time = 200ps
 Incorrect value propagates, Q transitions to 0.
 QM goes to high when output of I2 starts to fall.
EC7651/EC8651/VE7103/NE7081 - EK. 253
 Setup time analysis:
EC7651/EC8651/VE7103/NE7081 - EK. 254

 Propagation delay analysis:
i. Input transition at
least one setup
time before rising
edge of CLK.
ii. Delay is measured

from 50% point of
CLK edge to 50%
point of Q.
iii.Tc-q(LH) = 160 ps
iv.Tc-q(HL) = 180 ps
EC7651/EC8651/VE7103/NE7081 - EK. 255

Drawback of Transmission-gate Registers:
 High capacitive load presented to the clock signal.
 CLK load per register is very important:

◦ Directly impacts the power dissipation.
 Ignoring overhead required to invert CLK signal,

since inverter overhead can be amortized over
single register bits, each register has a clock load
of eight transistors.
 Approach to reduce CLK load:
◦ To make Ratioed circuit.
◦ Increased design complexity.
EC7651/EC8651/VE7103/NE7081 - EK. 256

Reduced CLK load static Register:
i. T1 should overpower I2
to switch the state of
the cross-coupled
inverter.
ii. I1 Input must brought
below switching
threshold in order to
make transition
iii.Using minimum size
Reverse Conduction: devices is desirable to
reduce power
dissipation.
iv.Reverse conduction:
Second stage can
affect state of first
latch. When slave is
ON, T2 & I4 can
influence I1-I2 latch.
EC7651/EC8651/VE7103/NE7081 - EK. 257

Non-Ideal Clock signals:
 Assumption so far, CLKbar is a perfect inversion of
CLK, considering zero delay for generating
inverter.
 Variations can exist because of wires or load
capacitances; effect is called Clock Skew, causes
Clock signals to overlap.
EC7651/EC8651/VE7103/NE7081 - EK. 258

 Clock overlap causes two types of failures:

i. When CLK is high (for shorter time), both sampling pass
transistors conduct, direct path exists from D to Q. Data
value can change on rising edge, which is undesired for
negative edge-triggered register. Q value is a function of D
arrives at node X before or falling edge of CLKbar. If node X
is sampled at meta-stable state, output will be determined by
noise in the system.
ii. Node A can be driven by both D & B during CLK overlap,
resulting in an undefined state.
EC7651/EC8651/VE7103/NE7081 - EK. 259
 Problems can be avoided by using two non-
overlapping clocks.
◦ Tnon_overlap must be larger enough so that no overlap
occurs even in presence of routing delays.
◦ Pseudo-static design.
EC7651/EC8651/VE7103/NE7081 - EK. 260

Schema
 Introduction
EC7651/EC8651/VE7103/NE7081 - EK. 261

Low-Voltage Static Latches:
 Scaling supply voltages is critical for low power
operation.
 But, certain latches do not function at reduced supply
voltages.
◦ Input to inverter cannot be raised above switching
threshold, resulting in incorrect evaluation.
 Scaling supply voltages requires use of reduced
threshold devices.
◦ Negative effects: Exponentially increasing subthreshold
leakage power. When accessed constantly, leakage
energy is insignificant when compared with switching
power.
◦ Use of conditional clocks, registers can be made idle for
extended periods, leakage energy can be quite
significant.
EC7651/EC8651/VE7103/NE7081 - EK. 262
Solving Leakage problem using Multilple-
Threshold CMOS:
i. Shaded inverters &
transmission gates are low-
threshold devices.
ii. During normal mode, sleep
devices are ON.
iii.D is sampled and propagated
to Q when CLK is low.
iv.Latch is in Hold mode when
CLK is high.
v. An extra parallel inverter is to
store the state of latch.
vi.High threshold devices in
series with low-threshold
inverter are turned off when
sleep is high.
EC7651/EC8651/VE7103/NE7081 - EK. 263

Schema
 Introduction
EC7651/EC8651/VE7103/NE7081 - EK. 264

Dynamic Latches and Registers
Concept:
 Storage in static sequential circuits relies on cross-
coupled inverter, and bistable element.
 Stored value remains in the circuit as long as voltage
is applied.
 Major disadvantage is complexity.
 This results in class of circuits with temporary storage
of charge on parasitic capacitors.
 Dynamic logic: 0 when no charge, 1 when capacitor is
charged.
 Periodic refreshing is required to preserve signal
integrity. (Dynamic devices)
 Reading the charge on capacitor without disrupting stored
charge requires devices with high input impedance.
EC7651/EC8651/VE7103/NE7081 - EK. 265

Schema
 Introduction
EC7651/EC8651/VE7103/NE7081 - EK. 266

Dynamic Transmission-Gate Edge-Triggered
Registers:
Capacitance C1: i. When CLK = 0, D is sampled & Implementation

Equivalent Capacitance of stored to Node 1. requires only 8
Gate C of I1, Junc. C of T1 & ii. When CLK = 0, Slave is in Hold transistors.
Overlap Gate C of T1. mode with High Input When
impedance at node 2. implementing
Capacitance C2: iii.On rising edge of CLK, T2 is On, using NMOS pass
Equivalent Capacitance of Value at 1 is sampled to Q. transistors, only 6
Gate C of I3, Junc. C of T2 & iv.Now, Node 2 has inverted value transistors
Overlap Gate C of T2. of Node 1. required.
EC7651/EC8651/VE7103/NE7081 - EK. 267

Registers:
 Setup time:
◦ Delay of transmission gate and it corresponds to time
takes node 1 to sample D.
 Hold time:
◦ ≈ Zero (Trans. Gate is OFF & Changes are ignored on
rising edge)
 Propagation delay:
◦ Two inverter delays + T2 delay.
 Consideration:
◦ Storage nodes have to be refreshed at periodic intervals
to prevent leakage.
◦ In datapath circuits, refresh rate is not an issue, since,
registers are clocked periodically and storage nodes are
constantly updated.
EC7651/EC8651/VE7103/NE7081 - EK. 268
Registers:
 Clock overlap issues:
 During 0-0 overlap:
◦ NMOS of T1 & PMOS of
T2 simultaneously ON.
◦ Creates direct path for
D to Q.
◦ Q can change on the falling edge is overlap time is larger –
Undesirable effect for Positive edge-triggered register.
 During 1-1 overlap:
◦ PMOS of T1 & NMOS of T2 are ON.
◦ Can be overcome by enforcing Hold time constraint
 Conditions:
◦ toverlap0-0 < tT1 + tI1 + tT2
◦ thold > toverlap1-1
EC7651/EC8651/VE7103/NE7081 - EK. 269

Schema
 Introduction
EC7651/EC8651/VE7103/NE7081 - EK. 270

C2MOS – A Clock-Skew Insensitive approach:
 Clocked CMOS Register
 Positive-Edge Triggered Register based on master-
slave concept insensitive to clock skew.
Two Phases of Operation:
 CLK = 0 (CLKbar = 1)
First Tristate driver turned On,
master stage acts as an inverter
sampling inverted version of D to
X. Slave section in hold mode. M7
& M8 are off, decoupling Q from
input. Q retains its previous value
stored on CL2.
 CLK = 1:
Master stage is in hold mode (M3 &
M4 are off) while slave evaluates
(M7 & M8 On).Value on Node X
propagates to Q, through slave
which acts as an inverter.
EC7651/EC8651/VE7103/NE7081 - EK. 271

 0-0 Overlap Case:
0-0 Overlap:
i. Both PMOS devices are ON.
ii. New data is sample on X through

M2 & M4 and node X make
transition from 0 to 1.
iii.But this cannot propagate to Q

since M7 is off.
iv.At end, CLKbar = 1, M7 & M8 turns

off, putting slave in hold mode.
v. Signal propagation requires one

pull-up followed by pull-down
which is not feasible in this case.
EC7651/EC8651/VE7103/NE7081 - EK. 272

 1-1 Overlap Case:
1-1 Overlap:
i. Both NMOS devices M3 & M7 are
ON.
ii. If D changes during overlap period,

X can make 1 to 0 transition, but
cannot propagate further.
iii.At end of overlap period, M8 turns

ON, and 0 propagates to output
which is not desirable.
iv.Problem can be fixed by imposing

hold-time constraint on D or D
should be stable during overlap
period.
EC7651/EC8651/VE7103/NE7081 - EK. 273

 C2MOS latch is insensitive to clock overlaps because
those overlaps activate either pull-up or pull-down
networks of latches.
 But if rise & fall times of CLK are sufficiently slow, both
NMOS & PMOS are conducting, creates path from D
to Q, destroying state of the circuit.
Simulations:
i. Circuit functions properly if CLK
rise (fall) times smaller than five
times of propagation delay of
register.
ii. Simulation for clock slopes of

0.1nS & 3nS is shown.
iii.For slow clocks, potential for a

race condition exists.
EC7651/EC8651/VE7103/NE7081 - EK. 274

Dual-Edge registers:
 It is also possible to design sequential circuits that
sample the input on both edges.
 Advantage: Lower frequency clock – half the original

rate – is distributed for same functional throughput,
resulting in power savings in clock distribution
network.
 A modification of C2MOS register enabling sampling

on both edges.
 Two parallel master-slave edge triggered registers,

whose outputs are multiplexed by using tristate
drivers.
EC7651/EC8651/VE7103/NE7081 - EK. 275
Dual-Edge registers:
When CLK = 1:
i. Transistors M1 – M4 is sampling
D to node X.
ii. M9 & M10 are OFF, node Y is

stable.
iii.On falling edge M5 – M8 turns

ON, driving inverted value of X to
Q.
When CLK = 0:
i. M1, M4, M9, M10 are ON,
sampling D to node Y.
ii. Devices M1 & M4 are reused,

reducing load on the D input.
iii.On rising edge, bottom slave

conducts, drives inverted Y on Q.
EC7651/EC8651/VE7103/NE7081 - EK. 276

Schema
 Introduction
EC7651/EC8651/VE7103/NE7081 - EK. 277

True Single-Phase Clocked Registers (TSPCR):
 In two-phase clocking schemes, care must be taken in
routing two clock signals to ensure the overlap is
minimized.
 While C2MOS provides skew-tolerant solutions, it is
possible to design registers that use only a single
phase clock.
For POSITIVE latch:
When CLK = 1:
i. Latch is transparent;
corresponds to two
cascaded inverters; latch is
non-inverting, propagates
input to output.
When CLK = 0:
i. Both inverters are disabled,
latch is in hold mode.
EC7651/EC8651/VE7103/NE7081 - EK. 278

True Single-Phase Clocked Registers (TSPCR):
 Only pull-up networks are still active while pull-down
network is deactivated.
 So, NO signal can propagate from Input to Output.
 Register can be constructed by cascading positive and
negative latch & CLK load is similar to C2MOS.
 Advantages: Use of Single Clock Phase.
 Disadvantages: Increase in no. of transistors – 12.
 Caution:
◦ When CLK = 0, Output node may be floating & exposed
to coupling from other signals.
◦ Charge sharing may also occur if output node drives
transmission gates.
◦ So, dynamic nodes should be isolated with the aid of
static inverters or made pseudo-static for noise
immunity.
EC7651/EC8651/VE7103/NE7081 - EK. 279
TSPCR – Embedding Logic Functionality:
Including LOGIC into Latch AND Logic into Latch
i. If setup time is increased, overall performance of digital

circuit can be improved.
ii. This approach of embedding logic into latches is used in the

design of EV4 DEC Alpha micro-processor.
EC7651/EC8651/VE7103/NE7081 - EK. 280

Simplified TSPC Latch:
i. Only first inverter is controlled by CLK.

ii. CLK load is reduced by half.
iii.Not all node voltages in latch experience full logic swing.
iv.Voltage at A (Vin = 0V) for positive latch equals to VDD – VTn,
which results in reduced drive for output NMOS transistor.
v. Voltage at A (Vin = VDD) for negative latch is only driven to VTP.
This limits amount of VDD scaling possible on latch.
EC7651/EC8651/VE7103/NE7081 - EK. 281

Positive Single-Phase Edge-Triggered Register:
i. When CLK = 0, Input inverter sampling
inverted D into X.
ii. Second inverter is in precharge mode,
with M6 charging node Y to VDD.
iii. Third inverter is in hold mode, since M8
& M9 are off.
iv. During low phase of CLK, input to final
inverter is holding its previous value &
output Q is stable.
v. On rising edge of CLK, dynamic
 Set-up time: inverter M4 – M6 evaluates.
Time for node X to be valid, is vi. If X is high on rising edge, node Y
one inverter delay. discharges.
 Hold time:
Less than 1 inverter delay since vii. During high phase, M7 – M8 is ON,
it takes 1 delay for input to affect node value Y is passed to Q.
node X. viii.On positive phase, node X transitions
 Propagation Delay: to low if D transitions at high level.
Three inverters since value on ix. D must me stable till node X before
node X must propagate to Q. rising edge of CLK propagates to Y.
EC7651/EC8651/VE7103/NE7081 - EK. 282
Transistor Sizing issues in TSPC:
 Transistor sizing is critical for achieving correct
functionality in TSPC register.
Problem:
Case: D = 0 & Q = 0 (Qbar = 1)
i. For CLK is Low, Y is precharged high turning M7
ON.
ii. When CLK transitions from LH, nodes Y & Qbar
discharge simultaneously through M4 – M5 & M7
– M8.
iii.When Y is sufficiently low, trend on Qbar is
reversed and pulled High through M9.
iv.Glitch may be the cause of fatal errors, it create
unwanted events & reduces contamination
delay.
Solution:
i. Resizing pull-down paths through M4 – M5 and
M7 – M8, so Y discharges faster than Qbar.
ii. This is achieved by reducing strength of M7 –
M8 pull-down path by speeding up M4 – M5 pull-
down path.
EC7651/EC8651/VE7103/NE7081 - EK. 283
Schema
 Introduction
EC7651/EC8651/VE7103/NE7081 - EK. 284
Pipelining
An Approach to Optimize Sequential Circuits:
 Technique used to accelerate operation of datapaths
in digital processors.
 Example:
Log( | a + b | ).
 Minimum Clock period
◦ Tmin = tc-q + tpd,logic + tsu
◦ tc-q & tsu are propagation delay & setup time of register.
◦ tpd,logic is worst case delay through combinational network
(Much larger than delays associated with registers)
 Assumption:
◦ Each logic modules has an equal propagation delay.
◦ Ex. Adder module is active during 1/3 of period and
remains idle during other 2/3 period.
EC7651/EC8651/VE7103/NE7081 - EK. 285
Pipelining
 Pipelining is a technique used to improve resource
utilization & increase functional throughput.
 Assumption: Introduce Registers between logic blocks
 So computation for one set of data spreads over no. of

clock-periods.
EC7651/EC8651/VE7103/NE7081 - EK. 286

Pipelining
 Minimum clock period for pipelined circuit,
◦ Tmin,pipe = tc-q + max(tpd,add,tpd,abs,tpd,log)
 Combinational circuit is partitioned into three sections,
each of which has a smaller propagation delay than
the original function.
 If all logic blocks have same propagation delay and
register overhead is small with respect to logic delay,
 The pipelined circuit outperforms original circuit by a
factor of 3,
◦ Tmin,pipe = Tmin / 3.
 The increased performance comes at a relatively small cost
of two additional registers and latency.
 So, pipelining is used in implementations of very high-
performance datapath circuits.
EC7651/EC8651/VE7103/NE7081 - EK. 287
Pipelining
Latch- versus Register-based Pipelines:
 Pipelined circuits can be constructed using level-
sensitive latches instead of edge-triggered registers.
 Consider the system:
i. Logic is introduced between master and slave

circuits.
ii. CLK – CLKbar denotes two-phase clock system.
iii. When CLK & CLKbar is non-overlapping, correct
pipeline operation is obtained.
iv. Input is sampled on C1 at negative edge of CLK &
computation of F starts, result is stored in C2 on
falling edge of CLKbar & computation of G starts.
v. If overlapping occurs, race condition exists between
input and current value.
EC7651/EC8651/VE7103/NE7081 - EK. 288
Pipelining
NORA – CMOS: A Logic Style for Pipelined Structures:
 Latch based pipeline circuit can also be implemented
by using C2MOS latches.
“A C2MOS-based pipelined circuit is race free as long as all the

logic functions F (implemented by using Static Logic) between
the latches are non-inverting”
EC7651/EC8651/VE7103/NE7081 - EK. 289

Pipelining
NORA – CMOS: A Logic Style for Pipelined Structures:
 The only way a signal can race from stage to stage
under this condition is when the logic function F is
inverting as below: (0-0 Overlap)
EC7651/EC8651/VE7103/NE7081 - EK. 290

Pipelining
NORA – CMOS:
 NORA – CMOS combines C2MOS pipeline registers
and NORA dynamic logic function blocks.
 Each module consists of a block of combinational logic

that can be a mixture of static and dynamic logic,
followed by C2MOS logic.
 Logic and latch are clocked in such a way that both

are simultaneously in either evaluation or hold
(precharge) mode.
 A block that is in evaluation during CLK = 1 is called a

CLK module, inverse is CLKbar module.
EC7651/EC8651/VE7103/NE7081 - EK. 291

Pipelining
NORA – CMOS:
 NORA datapath consists of chain of alternating CLK &
CLKbar modules.
 While one class of module is precharging with its
output latch in hold mode, preserving previous output
value, other class is evaluating.
 Data is passed in a pipelined fashion from module to
module.
 Static & Dynamic logic can be mixed freely, both CLKp
& CLKn dynamic blocks can be used in cascaded or in
pipelined form.
 This style avoids extra inverter required in Domino
CMOS.
 As a result of added complexity, NORA has been
limited to high-performance applications.
EC7651/EC8651/VE7103/NE7081 - EK. 292
Pipelining
NORA – CMOS:
 CLK Module
Logic Latch
CLK = 0 Precharge Hold
CLK = 1 Evaluate Evaluate
EC7651/EC8651/VE7103/NE7081 - EK. 293

Pipelining
NORA – CMOS:
 CLKbar Module
Logic Latch
CLK = 0 Evaluate Evaluate
CLK = 1 Precharge Hold
EC7651/EC8651/VE7103/NE7081 - EK. 294

Schema
 Introduction
EC7651/EC8651/VE7103/NE7081 - EK. 295

Perspective: Choosing a Clocking Strategy
 Selecting appropriate clocking methodology is a crucial
decision.
 Reliable synchronization of various operations in a complex
circuit is an intriguing challenge for an digital designer.
 Choosing right clocking scheme affects functionality, speed
& power of a circuit.
 Most robust and conceptually simple scheme is two-phase
master-slave design.
 Predominant approach is to use multiplexer-based register
& to generate two clock phases locally by inverting the clock.
 More exotic schemes such as glitch register are also used in
practice.
 But these schemes require fine-tuning and must be used in
specific situations.
 Example: Need for a negative setup time to cope with clock
skew.
EC7651/EC8651/VE7103/NE7081 - EK. 296
Perspective: Choosing a Clocking Strategy
 General trend in High-performance CMOS VLSI
design is to use simple clocking schemes, even at
the expense of performance.
 Most automated design methodologies such as

standard cell employ a single-phase, edge-triggered
approach, based on static flip-flops.
 Nevertheless, the tendency towards simpler clocking

approaches also is apparent in high-performance
designs such as microprocessors.
 The use of latches between logic to improve circuit

performance is common as well.
EC7651/EC8651/VE7103/NE7081 - EK. 297

Summary
EC7651/EC8651/VE7103/NE7081 - EK. 298

Summary
 The cross-coupling of two inverters creates a bistable
circuit, also known as a flip-flop. A third potential
operation point turns out to be meta-stable; that is, any
diversion from this bias point causes the flip-flop to
converge to one of the stable states.
 A latch is a level-sensitive memory element that samples

data on one phase and holds data on the other phase. A
register, on the other hand, samples the data on the rising
or falling edge.
 Registers can be static or dynamic. A static register

holds state as long as the power supply is turned on.
Dynamic memory is based on temporary charge store on
capacitors.
EC7651/EC8651/VE7103/NE7081 - EK. 299

Summary
 Registers can also be constructed using the pulse or
glitch concept.
 Choice of clocking style is an important consideration.

Two phase design can result in race problems. Circuit
techniques such as C2MOS can be used to eliminate race
conditions in two-phase clocking.
 The combination of dynamic logic with dynamic latches

can produce extremely fast computational structures. An
example of such an approach, the NORA logic style, is
very effective in pipelined datapaths.
EC7651/EC8651/VE7103/NE7081 - EK. 300

CHAPTER – III
Part - B
Memory Architectures
& Control Circuits
EC7651/EC8651/VE7103/NE7081 - EK. 301

Schema
 Introduction
◦ Memory Classifications
◦ Memory Architectures and Building Blocks
 The Memory Core
◦ Read-Only Memories
◦ Nonvolatile Read-Write Memories
◦ RAM
◦ Contents – Addressable Memory
 Memory Peripheral Circuitry
◦ Address Decoders
◦ Sense Amplifiers
◦ Voltage References
◦ Drivers/Buffers
◦ Timing and Control
EC7651/EC8651/VE7103/NE7081 - EK. 302

Memory Classifications
 Size:
• Bits or Bytes
 Timing Parameters:
EC7651/EC8651/VE7103/NE7081 - EK. 303

 Function:
• Read-Only Memory (ROM) and Read-Write Memory (RWM)
• RWM has less access times ad most flexible memories.
• Data stored in flip-flops or in a capacitor. (Volatile)
• ROM: Encoding information into the circuit topology, cannot be
modified, only be read. (Non-Volatile)
 Access Pattern:
• Order in which data can be accessed
• Random-access class - RAM
 Input/Output Architecture:
• Number of data input and output ports
 Application:
• Embedded Memories (System-on-a-chip)
EC7651/EC8651/VE7103/NE7081 - EK. 304

Non-Volatile
Read-Write Memory Read-Write Read-Only Memory
Memory
Random Non-Random
EPROM Mask-Programmed
Access Access
E2PROM Programmable (PROM)
SRAM FIFO FLASH
DRAM LIFO
Shift Register
CAM
EC7651/EC8651/VE7103/NE7081 - EK. 305

Memory Architectures and Building Blocks
EC7651/EC8651/VE7103/NE7081 - EK. 306

EC7651/EC8651/VE7103/NE7081 - EK. 307

EC7651/EC8651/VE7103/NE7081 - EK. 308

Memory Core: Read-Only Memories
BL BL BL
VDD
WL
WL WL
1
BL BL BL
WL WL
WL
0
GND
Diode ROM MOS ROM 1 MOS ROM 2
EC7651/EC8651/VE7103/NE7081 - EK. 309

A 4 x 4 OR ROM Cell Array:
BL [0] BL [1] BL [2] BL [3]
WL [0]
V DD
WL [1]
WL [2]
V DD
WL [3]
V bias
Pull-down loads
EC7651/EC8651/VE7103/NE7081 - EK. 310

A 4 x 4 NOR ROM Cell Array:
V DD
Pull-up devices
WL [0]
GND
WL [1]
WL [2]
GND
WL [3]
BL [0] BL [1] BL [2] BL [3]
EC7651/EC8651/VE7103/NE7081 - EK. 311

A 4 x 4 NOR ROM Cell Array: (Layout I)
Cell (9.5l x 7l)
Programmming using the

Active Layer Only
Polysilicon (WL)
Metal1 (BL)
Diffusion (GND)
Metal1 on Diffusion
EC7651/EC8651/VE7103/NE7081 - EK. 312

A 4 x 4 NOR ROM Cell Array: (Layout II)
Cell (11l x 7l)
Programmming using
the Contact Layer Only
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
EC7651/EC8651/VE7103/NE7081 - EK. 313

A 4 x 4 NAND ROM Cell Array:
V DD
Pull-up devices
BL [0] BL [1] BL [2] BL [3]
WL [0]
WL [1]
WL [2]
WL [3]
All word lines high by default with exception of selected row
EC7651/EC8651/VE7103/NE7081 - EK. 314

A 4 x 4 NAND ROM Cell Array: (Layout – Metal 1 Prog)
Cell (8l x 7l)
Programmming using
the Metal-1 Layer Only
No contact to VDD or GND necessary;

drastically reduced cell size
Loss in performance compared to NOR ROM
Polysilicon
Diffusion
Metal1 on Diffusion
EC7651/EC8651/VE7103/NE7081 - EK. 315

A 4 x 4 NAND ROM Cell Array: (Layout – Threshold Lowering)
Cell (5l x 6l)
Programmming using
Implants Only
Polysilicon
Threshold-altering
implant
Metal1 on Diffusion
EC7651/EC8651/VE7103/NE7081 - EK. 316

Equivalent Transient Model for NOR ROM:
V DD
BL
r word
WL Cbit
cword
WL – Distributed RC line – Polysilicon

BL – Capacitive only – Aluminium
EC7651/EC8651/VE7103/NE7081 - EK. 317

Equivalent Transient Model for NAND ROM:
V DD
BL
CL
rbit
cbit
rword
WL
cword
WL – Distributed RC line – Polysilicon

BL – Column is populated with transistors
EC7651/EC8651/VE7103/NE7081 - EK. 318

Precharged 4 x 4 NOR ROM:
f V DD
pre
Precharge devices
WL [0]
GND
WL [1]
WL [2]
GND
WL [3]
BL [0] BL [1] BL [2] BL [3]
EC7651/EC8651/VE7103/NE7081 - EK. 319

Memory Core: Non-Volatile Read Write Memories
The Floating-Gate Transistor:
Floating gate Gate

D
Source Drain
tox G
tox
S
n+ p n +_
Substrate
Device cross-section Schematic symbol
EC7651/EC8651/VE7103/NE7081 - EK. 320

The Floating-Gate Transistor:
0V 5V
20 V
2 5V 0V 2 2.5 V 5V
10 V 5V 20 V
S D S D
S D
Removing programming Programming results in

Avalanche injection higher V T .
voltage leaves charge trapped
EC7651/EC8651/VE7103/NE7081 - EK. 321

EEPROM or E2PROM:
Floating gate Gate I
Source Drain
20–30 nm -10 V V GD
10 V
n1 n1
Substrate
p
10 nm
FLOTOX transistor (Floating Gate Fowler-Nordheim

Tunneling Oxide) I-V characteristic
EC7651/EC8651/VE7103/NE7081 - EK. 322

EEPROM or E2PROM:
BL
EEPROM cell as configured
during a read operation.
WL
VDD
EC7651/EC8651/VE7103/NE7081 - EK. 323

Flash EEPROM:
Control gate
Floating gate
erasure Thin tunneling oxide
n 1 source n 1 drain
programming
p- substrate
EC7651/EC8651/VE7103/NE7081 - EK. 324

Basic Operations in a NOR Flash Memory: - Erase
EC7651/EC8651/VE7103/NE7081 - EK. 325

Basic Operations in a NOR Flash Memory: - Write
EC7651/EC8651/VE7103/NE7081 - EK. 326

Basic Operations in a NOR Flash Memory: - Read
EC7651/EC8651/VE7103/NE7081 - EK. 327

Comparison between nonvolatile memories:
EC7651/EC8651/VE7103/NE7081 - EK. 328

Memory Core: Read-Write Memories (RAM)
 STATIC (SRAM)
Data stored as long as supply is applied

Large (6 transistors/cell)
Fast
Differential
 DYNAMIC (DRAM)
Periodic refresh required

Small (1-3 transistors/cell)
Slower
Single Ended
EC7651/EC8651/VE7103/NE7081 - EK. 329

Static Random-Access Memory (SRAM):
(Six-Transistor CMOS SRAM Cell)
WL
V DD
M2 M4
Q
M5 Q M6
M1 M3
BL BL
EC7651/EC8651/VE7103/NE7081 - EK. 330

Six-Transistor CMOS SRAM Cell - Read
WL
V DD
BL M4
BL
Q= 0
Q= 1 M6
M5
V DD M1 V DD V DD
C bit C bit
EC7651/EC8651/VE7103/NE7081 - EK. 331

Six-Transistor CMOS SRAM Cell - Read
1.2
1
0.8
Voltage Rise (V)
0.6
0.4
0.2 rise [V]
Voltage
0
0 0.5 1 1.2 1.5 2 2.5 3
Cell Ratio (CR)
EC7651/EC8651/VE7103/NE7081 - EK. 332

Six-Transistor CMOS SRAM Cell - Write
WL
V DD
M4
Q= 0 M6
M5 Q= 1
M1
V DD
BL = 1 BL = 0
EC7651/EC8651/VE7103/NE7081 - EK. 333

Six-Transistor CMOS SRAM Cell - Write
EC7651/EC8651/VE7103/NE7081 - EK. 334

Six-Transistor CMOS SRAM Cell - Layout
VDD
M2 M4
Q Q
M1 M3
GND
M5 M6 WL
BL BL
EC7651/EC8651/VE7103/NE7081 - EK. 335

Resistive Load SRAM Cell
WL
V DD
RL RL
Q Q
M3 M4
BL M1 M2 BL
Static power dissipation -- Want R L large

Bit lines precharged to V DD to address t p problem
EC7651/EC8651/VE7103/NE7081 - EK. 336
Comparison of CMOS SRAM Cells:
EC7651/EC8651/VE7103/NE7081 - EK. 337

Dynamic Random-Access Memory (DRAM):
Three Transistor Dynamic Memory Cell:
BL 1 BL 2
WWL
RWL WWL
M3 RWL
M1 X X VDD 2 VT
M2
VDD
CS BL 1
BL 2 VDD 2 VT DV
No constraints on device ratios

Reads are non-destructive
Value stored at node X when writing a “1” = V WWL-VTn
EC7651/EC8651/VE7103/NE7081 - EK. 338
Dynamic Random-Access Memory (DRAM):
Three Transistor Dynamic Memory Cell:
Write: C S is charged or discharged by asserting WL and BL.

Read: Charge redistribution takes places between bit line and storage capacitance
CS
D V = VBL – V PRE = V BIT – V PRE ------------
C S + CBL
Voltage swing is small; typically around 250 mV.

EC7651/EC8651/VE7103/NE7081 - EK. 339
Memory Core: CAM
Content Addressable or Associative Memory:
Bit Bit Bit Bit

Word Bit Bit
M8 M9
M4 M5
CAM ••• CAM
M6 M7
Word ••• •••

Word S S
int
CAM ••• CAM M3 M2
Match
M1
Wired-NOR Match Line
EC7651/EC8651/VE7103/NE7081 - EK. 340

Memory Core: CAM
Content Addressable or Associative Memory:
CAM SRAM
ARRAY ARRAY
Hit Logic
Address Decoder
Input Drivers Sense Amps / Input Drivers
Address Tag Hit R/W Data
EC7651/EC8651/VE7103/NE7081 - EK. 341

Memory Peripheral Circuitry: The Address Decoders
Row Decoders:
Collection of 2M complex logic gates
Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder
EC7651/EC8651/VE7103/NE7081 - EK. 342

Static Decoders:
Multi-stage implementation improves performance
•••
WL 1
WL 0
A 0A 1 A 0A 1 A 0A 1 A 0A 1 A 2A 3 A 2A 3 A 2A 3 A 2A 3
•••
NAND decoder using
2-input pre-decoders
A1 A0 A0 A1 A3 A2 A2 A3
EC7651/EC8651/VE7103/NE7081 - EK. 343

Dynamic Decoders:
Precharge devices GND GND V DD
WL 3
V DD
WL 3
WL 2
WL 2 V DD
WL 1
WL 1
V DD
WL 0
WL 0
V DD f A0 A0 A1 A1
A0 A0 A1 A1 f
2-input NOR decoder 2-input NAND decoder
EC7651/EC8651/VE7103/NE7081 - EK. 344

Column Decoders:
BL 0 BL 1 BL 2 BL 3
S0
A0
S1
S2
A1 S3
2-input NOR decoder
Advantages: speed (tpd does not add to overall memory access time)
Only one extra transistor in signal path
Disadvantage: Large transistor count
EC7651/EC8651/VE7103/NE7081 - EK. 345

A 4-to-1 tree based column decoder:
BL 0 BL 1 BL 2 BL 3
A0
A0
A1
A1
D
Number of devices drastically reduced
Delay increases quadratically with # of sections; prohibitive for large decoders
Solutions: buffers
progressive sizing
combination of tree and pass transistor approaches
EC7651/EC8651/VE7103/NE7081 - EK. 346
Decoder for Circular Shift:
VDD VDD VDD VDD VDD VDD
WL 0 WL 1 WL 2
f f f f f f
• • •
R f f R f f R f f
VDD
EC7651/EC8651/VE7103/NE7081 - EK. 347

Memory Peripheral Circuitry: Sense Amplifiers
Basic Differential Sense Amplifier Circuit:
VDD
M3 M4
y Out
bit M1 M2 bit
SE M5
Directly applicable to
SRAMs
EC7651/EC8651/VE7103/NE7081 - EK. 348

Memory Peripheral Circuitry: Sense Amplifiers
Differential Sensing as applied to SRAM Memory Column:
V DD V DD
PC
BL BL V DD V DD
EQ
y M3 M4 2y
WL i
x M1 M2 2x x 2x
SE M5 SE
SE
SRAM cell i
V DD
Diff.
x Sense 2x Output
Amp y
SE
Output
(a) SRAM sensing scheme (b) two stage differential amplifier
EC7651/EC8651/VE7103/NE7081 - EK. 349
Memory Peripheral Circuitry: Voltage References:
Voltage Regulator:
VDD
M drive
VREF VDL
Equivalent Model
Vbias
V REF
-
M drive
+
VDL
EC7651/EC8651/VE7103/NE7081 - EK. 350

Memory Peripheral Circuitry: Voltage References:
Charge Pump and Waveforms:
EC7651/EC8651/VE7103/NE7081 - EK. 351

CHAPTER – IV
Part - B
TESTING
EC7651/EC8651/VE7103/NE7081 - EK. 352

Schema
• Introduction
• Test Procedure
• Design for Testability
– Issues in DFT
– Ad Hoc testing
– Scan based test
– Boundary Scan design
– Built-in Self-Test (BIST)
• Test pattern generation
– Fault Models
– Automatic Test-Pattern Generation (ATPG)
– Fault Simulation
EC7651/EC8651/VE7103/NE7081 - EK. 353

Introduction
• Overlooking issues?
– Returning a component? / Meeting specs? / Actually works?
– Discovery of fault? / Replacement cost?
• Guarantee from correct design? – No
• Manufacturing defects:
– Fabrication / base material / process variation / misalignment
– Stress test
• Designer access & Consumer access
• Testing equipments: Very expensive
• Early testing approach: Design for Testability
• Components in DFT:
– Necessary Circuitry
– Necessary Test Patterns
EC7651/EC8651/VE7103/NE7081 - EK. 354

Test Procedure
• Categories of manufacturing test:
– Diagnostic Test:
• Is used during debugging of chip
• Given a failing part, identify and locate offending fault.
– Functional Test:
• Determines a component is functional / non-functional
• Simple & Swift
– Parametric Test:
• Checks number of non-discrete parameters, noise margins,
propagation delay, frequencies, & various operating conditions
• Sub-divided into Static (dc) & Dynamic (ac) tests
• Procedure:
– Tester
– Device under test (DUT)
– Test program
EC7651/EC8651/VE7103/NE7081 - EK. 355

Design for Testability
Issues in DFT:
• Speed, Time, Cost of the tester.
• Combinational block:
– For N input, 2N patterns of input
– If single pattern takes 1μS, total
module test will take 1S.
• Sequential block:
– 2N+M input patterns
– If M = 10, total module will take
16 minutes
– If M = 50 (in modern μPs), take
billion years.
EC7651/EC8651/VE7103/NE7081 - EK. 356

Issues in DFT:
• Alternative approaches:
– Redundancy
• Single fault is covered by number of input patterns
– Fault coverage
• Relaxing the condition that all faults must be detected.
– Converting Sequential into Combinational circuits
– Self test
• Properties of DFT:
– Controllability
• Measures the ease of bringing a circuit node to a given condition
using only the input pins
• High degree of controllability is desirable
– Observability
• Measures the ease of observing the value of a node at the output pins
• High observability for a given complexity & output pins in a circuit
EC7651/EC8651/VE7103/NE7081 - EK. 357
Ad Hoc Testing:
• Combination of tricks and techniques that can increase
observability and controllability
EC7651/EC8651/VE7103/NE7081 - EK. 358

Ad Hoc Testing:
• Important DFT Concepts:
– Extra Hardware:
• No functionality yet improving testability
• Small penalty in area and performance
– Extra I/O pins:
• Multiplex Test signals and Functional signals to reduce pads.
• Examples of Ad Hoc Test approaches:

– Partitioning large state machines
– Addition of extra test points
– Provision of reset states
– Test buses
EC7651/EC8651/VE7103/NE7081 - EK. 359

Scan-based Test:
• To avoid sequential test problems, convert all registers
into externally loadable and readable elements
• Two modes of registers:

– Normal Mode
– Test Mode
• Test Procedure:
i. An excitation vector is entered through Scan In.
ii. Excitation is applied and propagated.
iii. Result is shifted out through Scan Out.
• Overhead Reduction
EC7651/EC8651/VE7103/NE7081 - EK. 360
Scan-based Test:
Register extended with serial scan:
Test
Low: Normal
High: Test Mode
EC7651/EC8651/VE7103/NE7081 - EK. 361
Boundary Scan design:
• Problem? Testing printed circuits boards are easy.
– Abundant availability of test points
– Testing every pin in the package
– Recently, Controllability & Observability is reduced.
Boundary Scan:
• I/O pins of all
components are
connected.
• Normal Mode: I/O
operation
• Test Mode: Vectors
can be scanned in and
out.
EC7651/EC8651/VE7103/NE7081 - EK. 362

Built-In Self-Test (BIST):
• Circuit itself generate test patterns & decides whether
results are correct.
• Addition of extra circuitry.
EC7651/EC8651/VE7103/NE7081 - EK. 363

Stimulus Generator:
a) Exhaustive approach:
• Test length is 2N, where N is number of inputs.
• All detectable faults will be detected.
• Ex.: N-bit counter
b) Random approach:
• Randomly chosen subset of 2N input patterns.
• Ex.: Linear Feedback Shift Register (LFSR)
• Repetition after 2N-1 states.
EC7651/EC8651/VE7103/NE7081 - EK. 364

Stimulus Generator: (LFSR)
EC7651/EC8651/VE7103/NE7081 - EK. 365

Response analyzer:
• Implementing as a comparator b/w generated response
and expected response (stored in a memory) represents
too much area overhead in practice.
• So, compressing data before comparing saves area.
• Compressed output is Signature and approach is called
Signature analysis.
• Example: Single bit stream signature analysis.
EC7651/EC8651/VE7103/NE7081 - EK. 366

Built-in Logic Block Observation (BILBO):
EC7651/EC8651/VE7103/NE7081 - EK. 367

Test-Pattern Generation
Fault Models:
• Common manufacturing faults:
– Short Circuits b/w signals, to rails, & floating nodes
• To evaluate effectiveness of test approach & concept of
a good or bad circuit, a circuit model is considered
• Stuck-at model
– Stuck-at-zero
– Stuck-at-one
• Stuck-at-open (β)
• Stuck-at-short (α, γ)
• Common fault coverage:
– α = Asa1
– β = Asa0 / Bsa0
– γ = Zsa1
EC7651/EC8651/VE7103/NE7081 - EK. 368
Fault Models:
• α – Stuck-at-open:
EC7651/EC8651/VE7103/NE7081 - EK. 369

Automatic Test-Pattern Generation:
• Task: To determine a minimum set of excitation vectors
that covers a sufficient portion of fault sets.
• Additional vectors can be added or removed based on the
results.
• Example:
Sa0 at U
• Controllability:
– Making fault to
appear
• Observability:
– Giving inputs to
observe fault
• Path Sensitizing
EC7651/EC8651/VE7103/NE7081 - EK. 370

Thank You
EC7651/EC8651/VE7103/NE7081 - EK. 371

MOS Transistor Principles and Digital Integrated Circuits

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Digital Integrated Circuits

Common for EC7651, EC8651, VE7103 & NE7081

– Space charge per unit area:

– Further increase in voltage causes additional electrons in the

• VGS when strong inversion occurs is called Threshold

 VT0 – VT for VSB = 0.

• Consider: Voltage at point x on channel – V(x).

where, kn‟ = process transconductance parameter

Observance: Squared dependency of ID w.r.t VGS.

where, IS & n are empirical parameters, typically n≥1 (1.5)

• Intrinsic capacitances arises from:

• All capacitors are non-linear & vary with the applied

• Operating Conditions & Voltages:

Sol.: Cox = 5.7 fF/pm2, CG = 0.7fF & Cdiff = 0.89fF.

Distribution plots of speed of adder circuit:

• Reduction in feature size

• Need of Scaling analysis

Vertical Dual Gate

• Dynamic Operation of the device

• Models represent only average behavior & can vary over a

NMOS Trans. modeled as a switch

• For larger values of VDD,

• VM depends on ratio „r‟ which compares the relative drive

• So, for rising VM towards VDD requires wider PMOS.

• For infinite gain, NMH = VOH –

• Ignoring some second order terms and sub. Vin = VM,

• Computing the capacitances.

ϕo = Built-in junction potential & m = grading coefficient.

Analysis of NMOS transistor: Cdb1:

Analysis of PMOS transistor: Cdb2:

Intrinsic Capacitance: Diffusion and Overlap Capacitances.

• Since CL(v) & i(v) are non-linear functions of voltage, an

• Propagation delay of linear RC network, depends on time

• For low-to-high transition,

• Identical Propagation delay for Low to High & High to Low

• Spice simulation shows

• If Vdd >> VTn + VDSATn/2 (in most designs), – delay becomes

Plot: Delay vs VDD

 NMOS to PMOS ratio

 Sizing inverters for performance

 Sizing a chain of inverters

 Choosing the right number of stages in an inverter chain

 Rise-Fall time of the input signal

 Delay in the presence of (long) interconnect wires.

Cdp1 & Cdn1 are drain diffusion capacitances of first gate,

• All capacitances can be scaled like,

• Therefore propagation delay can be,

where r = Reqp/Reqn, resistance ratio.

• represents intrinsic/unloadad delay

• Ratio between ext. & gate capacitance – Effective fan-out f.

• This has N – 1 unknowns, from Cg,2 to Cg,N. Minimum delay

• Optimum size of each inverter is geometric mean of neighbor

• And minimum delay through the chain,

F – The overall effective fan-out & equals to CL/Cg,1.

• When γ = 0, (ignoring self loading), optimal number of stages

EC7651/EC8651/VE7103/NE7081 - EK. 100

• Delay of inverter i equals to sum of delay of same gate for step

EC7651/EC8651/VE7103/NE7081 - EK. 103

EC7651/EC8651/VE7103/NE7081 - EK. 104

EC7651/EC8651/VE7103/NE7081 - EK. 105

• Dynamic power dissipation

EC7651/EC8651/VE7103/NE7081 - EK. 106